Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg	(revision 106)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg	(revision 108)
@@ -11,4 +11,5 @@
 1	1	+1	# nb_inst_branch_complete 
 0	0	+1	# nb_branch_speculated    [0][0] [nb_front_end][nb_context]
+1       1       +1      # size_nb_inst_decod
 32	32	+1	# size_general_data       
 1	1	+1	# size_store_queue_ptr    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg	(revision 106)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg	(revision 108)
@@ -11,4 +11,5 @@
 1	1	+1	# nb_inst_branch_complete 
 0	0	+1	# nb_branch_speculated    [0][0] [nb_front_end][nb_context]
+1       1       +1      # size_nb_inst_decod
 32	32	+1	# size_general_data       
 1	1	+1	# size_store_queue_ptr    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp	(revision 106)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp	(revision 108)
@@ -8,5 +8,5 @@
 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/include/test.h"
 
-#define NB_PARAMS 15
+#define NB_PARAMS 16
 
 void usage (int argc, char * argv[])
@@ -25,4 +25,5 @@
   err (_(" * nb_inst_branch_complete                            (uint32_t         )\n"));
   err (_(" * nb_branch_speculated    [nb_front_end][nb_context] (uint32_t         )\n"));
+  err (_(" * size_nb_inst_decod                                 (uint32_t         )\n"));
   err (_(" * size_general_data                                  (uint32_t         )\n"));
   err (_(" * size_store_queue_ptr                               (uint32_t         )\n"));
@@ -88,4 +89,5 @@
     }
 
+  uint32_t          _size_nb_inst_decod      = fromString<uint32_t         >(argv[x++]);
   uint32_t          _size_general_data       = fromString<uint32_t         >(argv[x++]);
   uint32_t          _size_store_queue_ptr    = fromString<uint32_t         >(argv[x++]);
@@ -112,4 +114,5 @@
 	 _nb_inst_branch_complete ,
 	 _nb_branch_speculated    ,
+	 _size_nb_inst_decod      ,
 	 _size_general_data       ,
 	 _size_store_queue_ptr    ,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp	(revision 106)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp	(revision 108)
@@ -68,4 +68,7 @@
   ALLOC2_SC_SIGNAL( in_INSERT_NO_EXECUTE              ," in_INSERT_NO_EXECUTE              ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   ALLOC2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT           ," in_INSERT_IS_DELAY_SLOT           ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#ifdef DEBUG
+  ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS                 ," in_INSERT_ADDRESS                 ",Taddress_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#endif
   ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT            ," in_INSERT_ADDRESS_NEXT            ",Taddress_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION               ," in_INSERT_EXCEPTION               ",Texception_t      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -167,4 +170,5 @@
   ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_ALL             ,"out_NB_INST_COMMIT_ALL             ",Tcounter_t        ,_param->_nb_front_end,_param->_nb_context[it1]);
   ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_MEM             ,"out_NB_INST_COMMIT_MEM             ",Tcounter_t        ,_param->_nb_front_end,_param->_nb_context[it1]);
+  ALLOC2_SC_SIGNAL( in_NB_INST_DECOD_ALL              ," in_NB_INST_DECOD_ALL              ",Tcounter_t        ,_param->_nb_front_end,_param->_nb_context[it1]);
   ALLOC2_SC_SIGNAL( in_DEPTH_MIN                      ," in_DEPTH_MIN                      ",Tdepth_t          ,_param->_nb_front_end,_param->_nb_context[it1]);
   ALLOC2_SC_SIGNAL( in_DEPTH_MAX                      ," in_DEPTH_MAX                      ",Tdepth_t          ,_param->_nb_front_end,_param->_nb_context[it1]);
@@ -206,4 +210,7 @@
   INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_IS_DELAY_SLOT           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NO_EXECUTE              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#ifdef DEBUG
+  INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#endif
   INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS_NEXT            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_EXCEPTION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -317,4 +324,5 @@
   INSTANCE2_SC_SIGNAL(_Commit_unit,out_NB_INST_COMMIT_ALL             ,_param->_nb_front_end,_param->_nb_context[it1]);
   INSTANCE2_SC_SIGNAL(_Commit_unit,out_NB_INST_COMMIT_MEM             ,_param->_nb_front_end,_param->_nb_context[it1]);
+  INSTANCE2_SC_SIGNAL(_Commit_unit, in_NB_INST_DECOD_ALL              ,_param->_nb_front_end,_param->_nb_context[it1]);
   
   if (_param->_have_port_depth)
@@ -617,4 +625,7 @@
   DELETE2_SC_SIGNAL( in_INSERT_NO_EXECUTE              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#ifdef DEBUG
+  DELETE2_SC_SIGNAL( in_INSERT_ADDRESS                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#endif
   DELETE2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_EXCEPTION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -714,4 +725,5 @@
   DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_ALL             ,_param->_nb_front_end,_param->_nb_context[it1]);
   DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_MEM             ,_param->_nb_front_end,_param->_nb_context[it1]);
+  DELETE2_SC_SIGNAL( in_NB_INST_DECOD_ALL              ,_param->_nb_front_end,_param->_nb_context[it1]);
   DELETE2_SC_SIGNAL( in_DEPTH_MIN                      ,_param->_nb_front_end,_param->_nb_context[it1]);
   DELETE2_SC_SIGNAL( in_DEPTH_MAX                      ,_param->_nb_front_end,_param->_nb_context[it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 106)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 108)
@@ -83,4 +83,7 @@
   public    : SC_IN (Tcontrol_t         ) ***  in_INSERT_NO_EXECUTE                ;//[nb_rename_unit][nb_inst_insert]
   public    : SC_IN (Tcontrol_t         ) ***  in_INSERT_IS_DELAY_SLOT             ;//[nb_rename_unit][nb_inst_insert]
+#ifdef DEBUG
+  public    : SC_IN (Taddress_t         ) ***  in_INSERT_ADDRESS                   ;//[nb_rename_unit][nb_inst_insert]
+#endif
   public    : SC_IN (Taddress_t         ) ***  in_INSERT_ADDRESS_NEXT              ;//[nb_rename_unit][nb_inst_insert]
   public    : SC_IN (Texception_t       ) ***  in_INSERT_EXCEPTION                 ;//[nb_rename_unit][nb_inst_insert]
@@ -195,4 +198,5 @@
   public    : SC_OUT(Tcounter_t         ) *** out_NB_INST_COMMIT_ALL               ;//[nb_front_end][nb_context]
   public    : SC_OUT(Tcounter_t         ) *** out_NB_INST_COMMIT_MEM               ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcounter_t         ) ***  in_NB_INST_DECOD_ALL                ;//[nb_front_end][nb_context]
 										   
     // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h	(revision 106)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h	(revision 108)
@@ -81,4 +81,5 @@
 			uint32_t            nb_inst_branch_complete ,
 			uint32_t         ** nb_branch_speculated    ,
+                        uint32_t            size_nb_inst_decod      ,
 			uint32_t            size_general_data       ,
 			uint32_t            size_store_queue_ptr    ,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 106)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 108)
@@ -90,5 +90,9 @@
   public  : Tspecial_data_t    flags                   ;
   public  : Tcontrol_t         no_sequence             ;
+  public  : Tcontrol_t         speculative             ;
 //public  : Tgeneral_data_t    data_commit             ; // branch's destination
+#ifdef DEBUG
+  public  : Taddress_t         address                 ;
+#endif
   public  : Taddress_t         address_next            ;
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 106)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 108)
@@ -71,4 +71,7 @@
       _ALLOC2_SIGNAL_IN ( in_INSERT_NO_EXECUTE              ,"no_execute"           ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
       _ALLOC2_SIGNAL_IN ( in_INSERT_IS_DELAY_SLOT           ,"is_delay_slot"        ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#ifdef DEBUG
+      _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS                 ,"address"              ,Taddress_t        ,_param->_size_instruction_address   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#endif
       _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS_NEXT            ,"address_next"         ,Taddress_t        ,_param->_size_instruction_address   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
       _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION               ,"exception"            ,Texception_t      ,_param->_size_exception             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -216,4 +219,5 @@
       _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_ALL             ,"commit_all",Tcounter_t         ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_MEM             ,"commit_mem",Tcounter_t         ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_NB_INST_DECOD_ALL              ,"decod_all" ,Tcounter_t         ,_param->_size_nb_inst_decod ,_param->_nb_front_end, _param->_nb_context[it1]);
     }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 106)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 108)
@@ -39,4 +39,7 @@
         DELETE2_SIGNAL( in_INSERT_NO_EXECUTE              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
         DELETE2_SIGNAL( in_INSERT_IS_DELAY_SLOT           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+#ifdef DEBUG
+        DELETE2_SIGNAL( in_INSERT_ADDRESS                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address               );
+#endif
         DELETE2_SIGNAL( in_INSERT_ADDRESS_NEXT            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address               );
         DELETE2_SIGNAL( in_INSERT_EXCEPTION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception             );
@@ -143,4 +146,5 @@
         DELETE2_SIGNAL(out_NB_INST_COMMIT_ALL             ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_commit);
         DELETE2_SIGNAL(out_NB_INST_COMMIT_MEM             ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_commit);
+        DELETE2_SIGNAL( in_NB_INST_DECOD_ALL              ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_decod);
 
         DELETE2_SIGNAL( in_DEPTH_MIN                      ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 106)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 108)
@@ -77,5 +77,6 @@
               case EVENT_STATE_WAITEND  : 
                 {
-                  if (reg_NB_INST_COMMIT_ALL [i][j] == 0)
+                  Tcounter_t nb_inst_all = PORT_READ(in_NB_INST_DECOD_ALL [i][j]) + reg_NB_INST_COMMIT_ALL [i][j];
+                  if (nb_inst_all == 0)
                     {
                       reg_EVENT_STATE [i][j] = EVENT_STATE_END;
@@ -163,4 +164,8 @@
 		  entry->num_reg_re_phy_new      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW    [x][y]);
                   entry->no_sequence             = type == TYPE_BRANCH;
+                  entry->speculative             = true;
+#ifdef DEBUG
+		  entry->address                 = PORT_READ(in_INSERT_ADDRESS               [x][y]);
+#endif
 		  entry->address_next            = PORT_READ(in_INSERT_ADDRESS_NEXT          [x][y]);
 
@@ -173,26 +178,38 @@
                   //                       other -> wait end of instruction
                   //            * OTHER
-		  if (exception == EXCEPTION_NONE)
-		    {
-                      Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]);
-                      // no_execute : l.j, l.nop, l.rfe
-
-                      log_printf(TRACE,Commit_unit,FUNCTION,"    * no_execute     : %d",no_execute);
-
-		      switch (type)
-			{
-			case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;}
-			case TYPE_MEMORY : {entry->state=(is_store  ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;}
-			default          : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
-			}
-		    }
-		  else
-		    {
-                      // Have an exception : wait head of ROB
-
-                      // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
-
-		      entry->state = ROB_END_EXCEPTION_WAIT_HEAD;
-		    }
+
+//                   bool       flush      = reg_EVENT_FLUSH [front_end_id][context_id];
+
+//                   log_printf(TRACE,Commit_unit,FUNCTION,"    * flush          : %d",flush);
+
+//                   if (flush)
+//                     {
+//                       entry->state    = ROB_END_MISS; // All type (branch, memory and others), because, is not execute
+//                     }
+//                   else
+                    {
+                      if (exception == EXCEPTION_NONE)
+                        {
+                          Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]);
+                          // no_execute : l.j, l.nop, l.rfe
+                          
+                          log_printf(TRACE,Commit_unit,FUNCTION,"    * no_execute     : %d",no_execute);
+                          
+                          switch (type)
+                            {
+                            case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END  ; break;}
+                            case TYPE_MEMORY : {entry->state=(is_store  ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;}
+                            default          : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
+                            }
+                        }
+                      else
+                        {
+                          // Have an exception : wait head of ROB
+                          
+                          // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
+                          
+                          entry->state = ROB_END_EXCEPTION_WAIT_HEAD;
+                        }
+                    }
 
                   // Push in rob
@@ -351,8 +368,8 @@
 	      Ttype_t    type         = entry->type        ;
 
-              if ((state == ROB_END_OK         ) or // LOAD_MISS
+              if ((state == ROB_END_OK         ) or
 // 		  (state == ROB_END_KO         ) or 
-		  (state == ROB_END_BRANCH_MISS)//  or 
-// 		  (state == ROB_END_LOAD_MISS  ) or 
+		  (state == ROB_END_BRANCH_MISS) or 
+ 		  (state == ROB_END_LOAD_MISS  )//  or 
 // 		  (state == ROB_END_MISS       ) or 
 // 		  (state == ROB_END_EXCEPTION  )
@@ -468,7 +485,16 @@
 	// =====[ EVENT ]=====================================================
 	// ===================================================================
-        {
-          // Not yet implemented
-        }
+//         for (uint32_t i=0; i < _param->_nb_front_end; ++i)
+//           for (uint32_t j=0; j < _param->_nb_context[i]; ++j)
+//             if (PORT_READ(in_EVENT_VAL [i][j]) and internal_EVENT_ACK [i][j])
+//               {
+//                 log_printf(TRACE,Commit_unit,FUNCTION,"  * EVENT [%d][%d]",i,j);
+
+//                 reg_PC_CURRENT            [i][j] = PORT_READ(in_EVENT_ADDRESS      [i][j]);
+//                 reg_PC_CURRENT_IS_DS      [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE   [i][j]); // ??
+//                 reg_PC_CURRENT_IS_DS_TAKE [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE   [i][j]);
+//                 reg_PC_NEXT               [i][j] = PORT_READ(in_EVENT_ADDRESS_NEXT [i][j]);
+//                 // PORT_READ(in_EVENT_ADDRESS_NEXT_VAL [i][j]);
+//               }
 
 	// ===================================================================
@@ -505,10 +531,10 @@
               
               bool         flush         = reg_EVENT_FLUSH [front_end_id][context_id];
-
-              Tcontrol_t   is_valid      = (((depth == depth_min) or 
-                                             depth_full or
-                                             ((depth_min <= depth_max)?
-                                              ((depth >= depth_min) and (depth <=depth_max)):
-                                              ((depth >= depth_min) or  (depth <=depth_max))))
+              bool         speculative   = entry->speculative and not (depth == depth_min);
+              Tcontrol_t   is_valid      = ((not speculative or 
+                                             (speculative and (depth_full or // all is valid
+                                                               ((depth_min <= depth_max)? // test if depth is overflow
+                                                                ((depth >= depth_min) and (depth <=depth_max)):
+                                                                ((depth >= depth_min) or  (depth <=depth_max))))))
                                              and not flush);
 
@@ -532,11 +558,18 @@
 		    case ROB_BRANCH_WAIT_END             : {state = ROB_MISS_WAIT_END; break;}
 		    case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS     ; break;}
+                    case ROB_END_BRANCH_MISS             :
                     case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS     ; break;}
+                    case ROB_END_LOAD_MISS_UPDATE        :
+                    case ROB_END_LOAD_MISS               :
                     case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_MISS     ; break;}
 		    case ROB_STORE_WAIT_HEAD_OK          : {state = ROB_STORE_HEAD_KO; break;}
 		  //case ROB_STORE_WAIT_HEAD_KO          : {state = ; break;}
 		    case ROB_OTHER_WAIT_END              : {state = ROB_MISS_WAIT_END; break;}
+		    case ROB_END_OK                      :
 		    case ROB_END_OK_SPECULATIVE          : {state = ROB_END_MISS     ; break;}
+		    case ROB_END_KO                      :
 		    case ROB_END_KO_SPECULATIVE          : {state = ROB_END_MISS     ; break;}
+		    case ROB_END_EXCEPTION_UPDATE        :
+		    case ROB_END_EXCEPTION               :
 		    case ROB_END_EXCEPTION_WAIT_HEAD     : {state = ROB_END_MISS     ; break;}
 		                                         
@@ -548,14 +581,7 @@
 		      // can't have miss speculation     
 		    case ROB_STORE_HEAD_OK               :
-		    case ROB_END_OK                      :
-		    case ROB_END_KO                      :
-                    case ROB_END_BRANCH_MISS             :
-                    case ROB_END_LOAD_MISS_UPDATE        :
-                    case ROB_END_LOAD_MISS               :
-		    case ROB_END_EXCEPTION_UPDATE        :
-		    case ROB_END_EXCEPTION               :
 		    default                              : 
 		      {
-			throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n"));
+			throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str()));
 			break;
 		      }
@@ -566,5 +592,7 @@
 	      // test if instruction is not speculative
 	      //------------------------------------------------------
-	      if (entry->depth == depth_min)
+              entry->speculative = speculative;
+// 	      if (entry->depth == depth_min)
+	      if (not speculative)
 		{
 		  switch (state)
@@ -574,5 +602,5 @@
 		    case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS        ; break;}
 		    case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_LOAD_MISS_UPDATE   ; break;}
-		    default : {break;}
+		    default : {break;} // else, no change
 		  }
 		}
@@ -587,5 +615,5 @@
 		    case ROB_STORE_WAIT_HEAD_OK      : {state = ROB_STORE_HEAD_OK;        break;}
 		    case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;}
-		    default : {break;}
+		    default : {break;} // else, no change
 		    }
 		}
@@ -599,80 +627,131 @@
     // ===================================================================
 
-    log_printf(TRACE,Commit_unit,FUNCTION,"  * Dump ROB (Re-Order-Buffer)");
-    log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank_head : %d",reg_NUM_BANK_HEAD);
-    log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank_tail : %d",reg_NUM_BANK_TAIL);
-
-    for (uint32_t i=0; i<_param->_nb_front_end; i++)
-      for (uint32_t j=0; j<_param->_nb_context [i]; j++)
+#ifdef STATISTICS
+    for (uint32_t i=0; i<_param->_nb_bank; i++)
+      if (usage_is_set(_usage,USE_STATISTICS))
+        *(_stat_bank_nb_inst [i]) += _rob[i].size();
+#endif
+
+#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true)
+    {
+      log_printf(TRACE,Commit_unit,FUNCTION,"  * Dump ROB (Re-Order-Buffer)");
+      log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank_head : %d",reg_NUM_BANK_HEAD);
+      log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank_tail : %d",reg_NUM_BANK_TAIL);
+      
+      for (uint32_t i=0; i<_param->_nb_front_end; i++)
+        for (uint32_t j=0; j<_param->_nb_context [i]; j++)
+          {
+            log_printf(TRACE,Commit_unit,FUNCTION,"    * [%d][%d]",i,j);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STATE  : %s",toString(reg_EVENT_STATE [i][j]).c_str());
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_FLUSH  : %d",reg_EVENT_FLUSH [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_ALL  : %d",reg_NB_INST_COMMIT_ALL[i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_MEM  : %d",reg_NB_INST_COMMIT_MEM[i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * PC_CURRENT   : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * PC_NEXT      : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2);
+          }
+
+      for (uint32_t i=0; i<_param->_nb_bank; i++)
         {
-          log_printf(TRACE,Commit_unit,FUNCTION,"    * [%d][%d] state        : %s",i,j,toString(reg_EVENT_STATE [i][j]).c_str());
-          log_printf(TRACE,Commit_unit,FUNCTION,"    * num_inst_all : %d",reg_NB_INST_COMMIT_ALL[i][j]);
-          log_printf(TRACE,Commit_unit,FUNCTION,"    * num_inst_mem : %d",reg_NB_INST_COMMIT_MEM[i][j]);
-          log_printf(TRACE,Commit_unit,FUNCTION,"    * PC_CURRENT   : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]);
-          log_printf(TRACE,Commit_unit,FUNCTION,"    * PC_NEXT      : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2);
+          uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
+
+          log_printf(TRACE,Commit_unit,FUNCTION,"      * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]);
+          
+          uint32_t x=0;
+          for (std::list<entry_t*>::iterator it=_rob[num_bank].begin();
+               it!=_rob[num_bank].end();
+               it++)
+            {
+              log_printf(TRACE,Commit_unit,FUNCTION,"        [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s - %d",
+                         x,
+                         (*it)->front_end_id            ,
+                         (*it)->context_id              ,
+                         (*it)->rename_unit_id          ,
+                         (*it)->depth                   ,
+                         (*it)->type                    ,
+                         (*it)->operation               ,
+                         (*it)->is_delay_slot           ,
+                         (*it)->use_store_queue         ,
+                         (*it)->store_queue_ptr_write   ,
+                         (*it)->use_load_queue          ,
+                         (*it)->load_queue_ptr_write    ,
+                         toString((*it)->state).c_str() ,
+                         (*it)->ptr                     );
+              log_printf(TRACE,Commit_unit,FUNCTION,"               %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ",
+                         (*it)->read_ra                 ,
+                         (*it)->num_reg_ra_log          ,
+                         (*it)->num_reg_ra_phy          ,
+                         (*it)->read_rb                 ,
+                         (*it)->num_reg_rb_log          ,
+                         (*it)->num_reg_rb_phy          ,
+                         (*it)->read_rc                 ,
+                         (*it)->num_reg_rc_log          ,
+                         (*it)->num_reg_rc_phy          ,
+                         (*it)->write_rd                ,
+                         (*it)->num_reg_rd_log          ,
+                         (*it)->num_reg_rd_phy_old      ,
+                         (*it)->num_reg_rd_phy_new      ,
+                         (*it)->write_re                ,
+                         (*it)->num_reg_re_log          ,
+                         (*it)->num_reg_re_phy_old      ,
+                         (*it)->num_reg_re_phy_new      );
+              
+              log_printf(TRACE,Commit_unit,FUNCTION,"               %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)",
+                         (*it)->exception_use ,
+                         (*it)->exception     ,
+                         (*it)->flags         ,
+                         (*it)->no_sequence   ,
+                         (*it)->speculative   ,
+                         (*it)->address       ,
+                         (*it)->address<<2    ,
+                         (*it)->address_next  ,
+                         (*it)->address_next<<2
+                         );
+              
+              x++;
+            }
         }
-	
-    for (uint32_t i=0; i<_param->_nb_bank; i++)
-      {
-        log_printf(TRACE,Commit_unit,FUNCTION,"    * Bank [%d] size : %d, ptr : %d",i,(int)_rob[i].size(), reg_BANK_PTR [i]);
-
-#ifdef STATISTICS
-        if (usage_is_set(_usage,USE_STATISTICS))
-          *(_stat_bank_nb_inst [i]) += _rob[i].size();
-#endif
-
-	uint32_t x=0;
-	for (std::list<entry_t*>::iterator it=_rob[i].begin();
-	     it!=_rob[i].end();
-	     it++)
-	  {
-            log_printf(TRACE,Commit_unit,FUNCTION,"      [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s - %d",
-                       x,
-                       (*it)->front_end_id            ,
-                       (*it)->context_id              ,
-                       (*it)->rename_unit_id          ,
-                       (*it)->depth                   ,
-                       (*it)->type                    ,
-                       (*it)->operation               ,
-//                     (*it)->address                 ,
-//                     (*it)->address << 2            ,
-                       (*it)->is_delay_slot           ,
-                       (*it)->use_store_queue         ,
-                       (*it)->store_queue_ptr_write   ,
-                       (*it)->use_load_queue          ,
-                       (*it)->load_queue_ptr_write    ,
-                       toString((*it)->state).c_str() ,
-                       (*it)->ptr                     );
-            log_printf(TRACE,Commit_unit,FUNCTION,"             %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ",
-                       (*it)->read_ra                 ,
-                       (*it)->num_reg_ra_log          ,
-                       (*it)->num_reg_ra_phy          ,
-                       (*it)->read_rb                 ,
-                       (*it)->num_reg_rb_log          ,
-                       (*it)->num_reg_rb_phy          ,
-                       (*it)->read_rc                 ,
-                       (*it)->num_reg_rc_log          ,
-                       (*it)->num_reg_rc_phy          ,
-                       (*it)->write_rd                ,
-                       (*it)->num_reg_rd_log          ,
-                       (*it)->num_reg_rd_phy_old      ,
-                       (*it)->num_reg_rd_phy_new      ,
-                       (*it)->write_re                ,
-                       (*it)->num_reg_re_log          ,
-                       (*it)->num_reg_re_phy_old      ,
-                       (*it)->num_reg_re_phy_new      );
-            
-            log_printf(TRACE,Commit_unit,FUNCTION,"             %.2d %.2d %.1d %.1d %.8x (%.8x)",
-                       (*it)->exception_use ,
-                       (*it)->exception     ,
-                       (*it)->flags         ,
-                       (*it)->no_sequence   ,
-                       (*it)->address_next  ,
-                       (*it)->address_next<<2
-                       );
-
-	    x++;
-	  }
-      }
+    }
+#endif
+
+#ifdef DEBUG_TEST
+    {
+      uint32_t x=reg_NUM_BANK_HEAD;
+      if (not _rob[x].empty())
+        {
+          entry_t * entry = _rob [x].front();
+
+          if (false
+//            or (entry->state == ROB_EMPTY                      )
+//            or (entry->state == ROB_BRANCH_WAIT_END            )
+//            or (entry->state == ROB_BRANCH_COMPLETE            )
+//            or (entry->state == ROB_STORE_WAIT_HEAD_OK         )
+//          //or (entry->state == ROB_STORE_WAIT_HEAD_KO         )
+//            or (entry->state == ROB_STORE_HEAD_OK              )
+//            or (entry->state == ROB_STORE_HEAD_KO              )
+//            or (entry->state == ROB_OTHER_WAIT_END             )
+//            or (entry->state == ROB_MISS_WAIT_END              )
+//            or (entry->state == ROB_END_OK_SPECULATIVE         )
+              or (entry->state == ROB_END_OK                     )
+//            or (entry->state == ROB_END_KO_SPECULATIVE         )
+//            or (entry->state == ROB_END_KO                     )
+//            or (entry->state == ROB_END_BRANCH_MISS_SPECULATIVE)
+              or (entry->state == ROB_END_BRANCH_MISS            )
+//            or (entry->state == ROB_END_LOAD_MISS_SPECULATIVE  )
+//            or (entry->state == ROB_END_LOAD_MISS_UPDATE       )
+              or (entry->state == ROB_END_LOAD_MISS              )
+//            or (entry->state == ROB_END_MISS                   )
+//            or (entry->state == ROB_END_EXCEPTION_WAIT_HEAD    )
+//            or (entry->state == ROB_END_EXCEPTION_UPDATE       )
+//            or (entry->state == ROB_END_EXCEPTION              )
+              )
+          if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id])
+            throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (%x) is different of reg_PC_CURRENT[%d][%d] (%x).\n"),
+                                                 entry->address,
+                                                 entry->front_end_id,
+                                                 entry->context_id,
+                                                 reg_PC_CURRENT[entry->front_end_id][entry->context_id]));
+        }
+    }
+#endif
 
 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp	(revision 106)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp	(revision 108)
@@ -31,4 +31,5 @@
 			  uint32_t            nb_inst_branch_complete ,
 			  uint32_t         ** nb_branch_speculated    ,
+                          uint32_t            size_nb_inst_decod      ,
 			  uint32_t            size_general_data       ,
 			  uint32_t            size_store_queue_ptr    ,
@@ -93,4 +94,5 @@
         _size_depth               = max<uint32_t>(_array_size_depth,_nb_front_end,_nb_context);
         _size_nb_inst_commit      = log2(_size_queue)+1;
+        _size_nb_inst_decod       = size_nb_inst_decod;
         
         _have_port_front_end_id   = _size_front_end_id   > 0;
