Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/test.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/test.cpp (revision 108) @@ -59,5 +59,5 @@ cout << "------------------------------------------------------" << endl; - Instance * instance = new Instance ("../../../Files/Instance_scalar_1.cfg", + Instance * instance = new Instance ("../../../Files/Instance_debug.cfg", generator1, _get_custom_information @@ -68,39 +68,4 @@ } - { - cout << "------------------------------------------------------" << endl; - - Instance * instance = new Instance ("../../../Files/Instance_scalar_2.cfg", - generator1, - _get_custom_information - ); - instance->toFile("data_out"); - - delete instance; - } - - { - cout << "------------------------------------------------------" << endl; - - Instance * instance = new Instance ("../../../Files/Instance_scalar_3.cfg", - generator1, - _get_custom_information - ); - instance->toFile("data_out"); - - delete instance; - } - - { - cout << "------------------------------------------------------" << endl; - - Instance * instance = new Instance ("../../../Files/Instance_scalar_4.cfg", - generator1, - _get_custom_information - ); - instance->toFile("data_out"); - - delete instance; - } delete configuration1; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_fromFile.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_fromFile.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_fromFile.cpp (revision 108) @@ -45,25 +45,40 @@ XML_t * xml = vect[i]; - // Test node - testNodeName (xml,"parameter"); - testSingleton (xml,true); + std::string child_name = xml->getName(); - // Take attributes of this tag - - attributes_t attributes = xml->getAttributes(); - -// std::cout << "Node [" << name << "]" << std::endl; -// std::cout << " * nb attributes : " << xml->getAttributes().size() << std::endl; - - attribute_t value_name = getAttribute(xml,attributes,"name" ); - attribute_t value = getAttribute(xml,attributes,"value"); - - testAttributesEmpty(xml,attributes); - - // Insert in array - Parameter_affectation * param = new Parameter_affectation(value_name, - value ); - - insert(param); + //-------------------------------------------- + // Child : Parameter + //-------------------------------------------- + if (child_name == "parameter") + { + // testNodeName (xml,"parameter"); + testSingleton (xml,true); + + // Take attributes of this tag + + attributes_t attributes = xml->getAttributes(); + + // std::cout << "Node [" << name << "]" << std::endl; + // std::cout << " * nb attributes : " << xml->getAttributes().size() << std::endl; + + attribute_t value_name = getAttribute(xml,attributes,"name" ); + attribute_t value = getAttribute(xml,attributes,"value"); + + testAttributesEmpty(xml,attributes); + + // Insert in array + Parameter_affectation * param = new Parameter_affectation(value_name, + value ); + + insert(param); + } + //-------------------------------------------- + // Child : Simulation + //-------------------------------------------- + else + { + testNodeName (xml,"simulation"); + testSingleton (xml,true); + } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Parameters_msg_error.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Parameters_msg_error.cpp (revision 108) @@ -28,5 +28,5 @@ if (_size_queue < _nb_inst_retire) - test.error("The reservation_station can't have more retire port than entry in the queue."); + test.error(toString(_("The reservation_station can't have more retire port (%d) than entry in the queue (%d).\n"),_nb_inst_retire,_size_queue)); log_printf(FUNC,Reservation_station,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h (revision 108) @@ -33,4 +33,6 @@ CONTEXT_STATE_KO_MISS_LOAD_ADDR , // update address manager CONTEXT_STATE_KO_MISS_LOAD_WAITEND , // wait end of event (miss load)) + CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR , // update address manager + CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND, // wait end of event (miss branch) // CONTEXT_STATE_KO_MSYNC , // wait completion of all memory operation // CONTEXT_STATE_KO_MSYNC_ISSUE , // issue msync operation @@ -64,4 +66,6 @@ case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_ADDR : return "context_state_ko_miss_branch_addr" ; break; case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : return "context_state_ko_miss_branch_waitend"; break; + case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR : return "context_state_ko_miss_branch_and_load_addr" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND : return "context_state_ko_miss_branch_and_load_waitend"; break; case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_ADDR : return "context_state_ko_miss_load_addr" ; break; case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_WAITEND : return "context_state_ko_miss_load_waitend" ; break; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp (revision 108) @@ -33,4 +33,5 @@ Tcontrol_t val = ((state == CONTEXT_STATE_KO_EXCEP_ADDR ) or (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or (state == CONTEXT_STATE_KO_PSYNC_ADDR ) or @@ -53,4 +54,5 @@ { case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break; + case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR: case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: (type = EVENT_TYPE_BRANCH_MISS_SPECULATION); break; case CONTEXT_STATE_KO_MISS_LOAD_ADDR : (type = EVENT_TYPE_LOAD_MISS_SPECULATION ); break; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (revision 108) @@ -82,4 +82,13 @@ break; } + case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND : + { + // Wait end of all instruction + if (inst_all == 0) + +// state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) + state = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR; + break; + } case CONTEXT_STATE_KO_EXCEP_SPR : { @@ -93,4 +102,9 @@ } case CONTEXT_STATE_KO_MISS_LOAD_ADDR : + { + // nothing, wait the update of internal register (pc) + break; + } + case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR : { // nothing, wait the update of internal register (pc) @@ -209,8 +223,10 @@ // priority : miss > excep > spr/sync - uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or - (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or - (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or - (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); + uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or + (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); uint8_t priority1 = 2; // miss @@ -272,8 +288,10 @@ // miss > excep > spr/sync - uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or - (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or - (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or - (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); + uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or + (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; @@ -405,8 +423,10 @@ // miss > excep > spr/sync - uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or - (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or - (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or - (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); + uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or + (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) @@ -437,5 +457,16 @@ { case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} - case EVENT_TYPE_LOAD_MISS_SPECULATION : {state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; break;} + case EVENT_TYPE_LOAD_MISS_SPECULATION : + { + // Test if previous branch occure + if ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND)) + state_next = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND; + else + state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; + break; + } case EVENT_TYPE_BRANCH_MISS_SPECULATION : case EVENT_TYPE_SPR_ACCESS : @@ -480,4 +511,5 @@ } case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: + // { // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) @@ -489,4 +521,9 @@ { reg_STATE [i] = CONTEXT_STATE_OK; + break; + } + case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR: + { + reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR; break; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp (revision 108) @@ -71,4 +71,7 @@ ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); +#ifdef DEBUG + ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); +#endif ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); @@ -148,4 +151,7 @@ INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); +#ifdef DEBUG + INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS ,_param->_nb_inst_decod); +#endif INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); @@ -450,4 +456,7 @@ delete [] out_DECOD_NO_EXECUTE ; delete [] out_DECOD_IS_DELAY_SLOT ; +#ifdef DEBUG + delete [] out_DECOD_ADDRESS ; +#endif delete [] out_DECOD_ADDRESS_NEXT ; delete [] out_DECOD_HAS_IMMEDIAT ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h (revision 108) @@ -88,4 +88,7 @@ public : SC_OUT(Tcontrol_t ) ** out_DECOD_NO_EXECUTE ;//[nb_inst_decod] public : SC_OUT(Tcontrol_t ) ** out_DECOD_IS_DELAY_SLOT ;//[nb_inst_decod] +#ifdef DEBUG + public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS ;//[nb_inst_decod] +#endif public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS_NEXT ;//[nb_inst_decod] public : SC_OUT(Tcontrol_t ) ** out_DECOD_HAS_IMMEDIAT ;//[nb_inst_decod] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp (revision 108) @@ -89,4 +89,7 @@ ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); +#ifdef DEBUG + ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); +#endif ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp (revision 108) @@ -49,4 +49,7 @@ DELETE1_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod,1 ); DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT,_param->_nb_inst_decod,1 ); +#ifdef DEBUG + DELETE1_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_inst_decod,_param->_size_instruction_address ); +#endif DELETE1_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod,_param->_size_instruction_address ); DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod,1 ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp (revision 108) @@ -43,5 +43,6 @@ Tcontrol_t can_continue [_param->_nb_context]; - Tcontrol_t can_continue_next [_param->_nb_context]; +// Tcontrol_t can_continue_next [_param->_nb_context]; +// Tcontrol_t have_decod_branch [_param->_nb_context]; for (uint32_t i=0; i<_param->_nb_context; i++) @@ -52,5 +53,6 @@ can_continue [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); - can_continue_next [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); +// can_continue_next [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); +// have_decod_branch [i] = false; } @@ -79,5 +81,5 @@ log_printf(TRACE,Decod,FUNCTION," * decod_ack [%d] : %d",i,PORT_READ(in_DECOD_ACK [i])); - can_continue [x] = can_continue_next [x]; +// can_continue [x] = can_continue_next [x]; decod_val [i] = true; // fetch_val and decod_enable @@ -139,5 +141,7 @@ PORT_WRITE(out_DECOD_NO_EXECUTE [i], _decod_instruction->_no_execute ); PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot ); -// PORT_WRITE(out_DECOD_ADDRESS [i], addr); +#ifdef DEBUG + PORT_WRITE(out_DECOD_ADDRESS [i], addr); +#endif // if ((type == TYPE_BRANCH) and // ((_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_SET) or @@ -193,5 +197,7 @@ //can_continue_next [x] = PORT_READ(in_PREDICT_CAN_CONTINUE [i]); // can continue is set if direction is "not take" (also, continue is sequential order) - can_continue_next [x] = false; // one branch per context, the DS don't execute + can_continue [x] = false; // one branch per context, the DS don't execute +// can_continue_next [x] = false; // one branch per context, the DS don't execute +// have_decod_branch [x] = true; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp (revision 108) @@ -60,4 +60,7 @@ ALLOC1_SC_SIGNAL( in_DECOD_IN_NO_EXECUTE ," in_DECOD_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT ," in_DECOD_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); +#ifdef DEBUG + ALLOC1_SC_SIGNAL( in_DECOD_IN_ADDRESS ," in_DECOD_IN_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); +#endif ALLOC1_SC_SIGNAL( in_DECOD_IN_ADDRESS_NEXT ," in_DECOD_IN_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL( in_DECOD_IN_HAS_IMMEDIAT ," in_DECOD_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); @@ -84,4 +87,7 @@ ALLOC1_SC_SIGNAL(out_DECOD_OUT_NO_EXECUTE ,"out_DECOD_OUT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,"out_DECOD_OUT_IS_DELAY_SLOT",Tcontrol_t ,_param->_nb_inst_decod); +#ifdef DEBUG + ALLOC1_SC_SIGNAL(out_DECOD_OUT_ADDRESS ,"out_DECOD_OUT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); +#endif ALLOC1_SC_SIGNAL(out_DECOD_OUT_ADDRESS_NEXT ,"out_DECOD_OUT_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_OUT_HAS_IMMEDIAT ,"out_DECOD_OUT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); @@ -125,4 +131,7 @@ INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_NO_EXECUTE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_IS_DELAY_SLOT ,_param->_nb_inst_decod); +#ifdef DEBUG + INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_ADDRESS ,_param->_nb_inst_decod); +#endif INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_ADDRESS_NEXT ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_HAS_IMMEDIAT ,_param->_nb_inst_decod); @@ -151,4 +160,7 @@ INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_NO_EXECUTE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod); +#ifdef DEBUG + INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_ADDRESS ,_param->_nb_inst_decod); +#endif INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_ADDRESS_NEXT ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_HAS_IMMEDIAT ,_param->_nb_inst_decod); @@ -304,4 +316,7 @@ DELETE1_SC_SIGNAL( in_DECOD_IN_NO_EXECUTE ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT ,_param->_nb_inst_decod); +#ifdef DEBUG + DELETE1_SC_SIGNAL( in_DECOD_IN_ADDRESS ,_param->_nb_inst_decod); +#endif DELETE1_SC_SIGNAL( in_DECOD_IN_ADDRESS_NEXT ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL( in_DECOD_IN_HAS_IMMEDIAT ,_param->_nb_inst_decod); @@ -328,4 +343,7 @@ DELETE1_SC_SIGNAL(out_DECOD_OUT_NO_EXECUTE ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod); +#ifdef DEBUG + DELETE1_SC_SIGNAL(out_DECOD_OUT_ADDRESS ,_param->_nb_inst_decod); +#endif DELETE1_SC_SIGNAL(out_DECOD_OUT_ADDRESS_NEXT ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_OUT_HAS_IMMEDIAT ,_param->_nb_inst_decod); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h (revision 108) @@ -75,4 +75,7 @@ public : SC_IN (Tcontrol_t ) ** in_DECOD_IN_NO_EXECUTE ;//[nb_inst_decod] public : SC_IN (Tcontrol_t ) ** in_DECOD_IN_IS_DELAY_SLOT ;//[nb_inst_decod] +#ifdef DEBUG + public : SC_IN (Tgeneral_data_t ) ** in_DECOD_IN_ADDRESS ;//[nb_inst_decod] +#endif public : SC_IN (Tgeneral_data_t ) ** in_DECOD_IN_ADDRESS_NEXT ;//[nb_inst_decod] public : SC_IN (Tcontrol_t ) ** in_DECOD_IN_HAS_IMMEDIAT ;//[nb_inst_decod] @@ -100,4 +103,7 @@ public : SC_OUT(Tcontrol_t ) ** out_DECOD_OUT_NO_EXECUTE ;//[nb_inst_decod] public : SC_OUT(Tcontrol_t ) ** out_DECOD_OUT_IS_DELAY_SLOT ;//[nb_inst_decod] +#ifdef DEBUG + public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_OUT_ADDRESS ;//[nb_inst_decod] +#endif public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_OUT_ADDRESS_NEXT ;//[nb_inst_decod] public : SC_OUT(Tcontrol_t ) ** out_DECOD_OUT_HAS_IMMEDIAT ;//[nb_inst_decod] @@ -129,5 +135,6 @@ private : std::list* reg_QUEUE ; private : uint32_t * reg_NB_INST ;//[nb_context] - + private : uint32_t reg_LAST_SLOT ; + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ private : Tcontrol_t * internal_DECOD_IN_ACK ;//[nb_inst_decod] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h (revision 108) @@ -30,4 +30,7 @@ public : Tcontrol_t * _no_execute ; public : Tcontrol_t * _is_delay_slot ; +#ifdef DEBUG + public : Tgeneral_data_t * _address ; +#endif public : Tgeneral_data_t * _address_next ; public : Tcontrol_t * _has_immediat ; @@ -56,4 +59,7 @@ _no_execute = new Tcontrol_t [_nb_inst]; _is_delay_slot = new Tcontrol_t [_nb_inst]; +#ifdef DEBUG + _address = new Tgeneral_data_t [_nb_inst]; +#endif _address_next = new Tgeneral_data_t [_nb_inst]; _has_immediat = new Tcontrol_t [_nb_inst]; @@ -85,4 +91,7 @@ delete [] _no_execute ; delete [] _is_delay_slot ; +#ifdef DEBUG + delete [] _address ; +#endif delete [] _address_next ; delete [] _has_immediat ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp (revision 108) @@ -67,4 +67,7 @@ ALLOC1_SIGNAL_IN ( in_DECOD_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_DECOD_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); +#ifdef DEBUG + ALLOC1_SIGNAL_IN ( in_DECOD_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); +#endif ALLOC1_SIGNAL_IN ( in_DECOD_IN_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_IN ( in_DECOD_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); @@ -96,4 +99,7 @@ ALLOC1_SIGNAL_OUT(out_DECOD_OUT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_DECOD_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); +#ifdef DEBUG + ALLOC1_SIGNAL_OUT(out_DECOD_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); +#endif ALLOC1_SIGNAL_OUT(out_DECOD_OUT_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_OUT(out_DECOD_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp (revision 108) @@ -37,4 +37,7 @@ DELETE1_SIGNAL( in_DECOD_IN_NO_EXECUTE ,_param->_nb_inst_decod,1 ); DELETE1_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT ,_param->_nb_inst_decod,1 ); +#ifdef DEBUG + DELETE1_SIGNAL( in_DECOD_IN_ADDRESS ,_param->_nb_inst_decod,_param->_size_instruction_address ); +#endif DELETE1_SIGNAL( in_DECOD_IN_ADDRESS_NEXT ,_param->_nb_inst_decod,_param->_size_instruction_address ); DELETE1_SIGNAL( in_DECOD_IN_HAS_IMMEDIAT ,_param->_nb_inst_decod,1 ); @@ -61,4 +64,7 @@ DELETE1_SIGNAL(out_DECOD_OUT_NO_EXECUTE ,_param->_nb_inst_decod,1 ); DELETE1_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod,1 ); +#ifdef DEBUG + DELETE1_SIGNAL(out_DECOD_OUT_ADDRESS ,_param->_nb_inst_decod,_param->_size_instruction_address ); +#endif DELETE1_SIGNAL(out_DECOD_OUT_ADDRESS_NEXT ,_param->_nb_inst_decod,_param->_size_instruction_address ); DELETE1_SIGNAL(out_DECOD_OUT_HAS_IMMEDIAT ,_param->_nb_inst_decod,1 ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp (revision 108) @@ -35,64 +35,75 @@ if (not reg_QUEUE->empty()) for (uint32_t i=0; i<_param->_nb_inst_decod; i++) - if (reg_QUEUE->front()->_val [i]) - { - log_printf(TRACE,Decod_queue,FUNCTION,_(" * Queue is not empty, slot [%d] is valid."),i); + { + uint32_t index = reg_LAST_SLOT + i; - Tcontext_t context = reg_QUEUE->front()->_context_id [i]; - Tdepth_t depth = reg_QUEUE->front()->_depth [i]; - Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context]):0; - Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX [context]):0; - Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL[context]); + // Stop + if (index >= _param->_nb_inst_decod) + break; - // is a valid instruction ? - // If DEPTH_CURRENT : - // equal at DEPTH_MIN -> not speculative - // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss - // include ]DEPTH_MIN:DEPTH_MAX] -> speculative + if (reg_QUEUE->front()->_val [index]) + { + log_printf(TRACE,Decod_queue,FUNCTION,_(" * Queue is not empty, slot [%d] is valid."),i); + + Tcontext_t context = reg_QUEUE->front()->_context_id [index]; + Tdepth_t depth = reg_QUEUE->front()->_depth [index]; + Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context]):0; + Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX [context]):0; + Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL[context]); - // All case - // ....... min ...X... max ....... OK - // ....... min ....... max ...X... KO - // ...X... min ....... max ....... KO - // ....... max ....... min ...X... OK - // ...X... max ....... min ....... OK - // ....... max ...X... min ....... KO + // is a valid instruction ? + // If DEPTH_CURRENT : + // equal at DEPTH_MIN -> not speculative + // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss + // include ]DEPTH_MIN:DEPTH_MAX] -> speculative + + // All case + // ....... min ...X... max ....... OK + // ....... min ....... max ...X... KO + // ...X... min ....... max ....... KO + // ....... max ....... min ...X... OK + // ...X... max ....... min ....... OK + // ....... max ...X... min ....... KO + + Tcontrol_t is_valid = ((depth == depth_min) or + depth_full or + ((depth_min <= depth_max)? + ((depth >= depth_min) and (depth <=depth_max)): + ((depth >= depth_min) or (depth <=depth_max)))); + //Tcontrol_t is_valid = ((depth == depth_min) or + // ((depth_min < depth_max)? + // (depth<=depth_max): + // ((depth > depth_min) or (depth <= depth_max)))); + //Tcontrol_t is_valid = depth <= depth_max; - Tcontrol_t is_valid = ((depth == depth_min) or - depth_full or - ((depth_min <= depth_max)? - ((depth >= depth_min) and (depth <=depth_max)): - ((depth >= depth_min) or (depth <=depth_max)))); -// Tcontrol_t is_valid = ((depth == depth_min) or -// ((depth_min < depth_max)? -// (depth<=depth_max): -// ((depth > depth_min) or (depth <= depth_max)))); -// Tcontrol_t is_valid = depth <= depth_max; - - log_printf(TRACE,Decod_queue,FUNCTION," * is_valid : %d",is_valid); - log_printf(TRACE,Decod_queue,FUNCTION," * context : %d",context); - log_printf(TRACE,Decod_queue,FUNCTION," * depth : %d",depth); - log_printf(TRACE,Decod_queue,FUNCTION," * depth_min : %d",depth_min); - log_printf(TRACE,Decod_queue,FUNCTION," * depth_max : %d",depth_max); - log_printf(TRACE,Decod_queue,FUNCTION," * depth_full : %d",depth_full); - log_printf(TRACE,Decod_queue,FUNCTION," * address_next : 0x%x (0x%x)",reg_QUEUE->front()->_address_next[i],reg_QUEUE->front()->_address_next[i]<<2); - internal_DECOD_OUT_VAL [i] = 1; // in all case, val is set (entry is not empty, and instruction is valid) - if (is_valid) - { - val [i] = 1; - internal_DECOD_OUT_ACK [i] = PORT_READ(in_DECOD_OUT_ACK [i]); - } - else - { - // Consume the instruction (to erase) - internal_DECOD_OUT_ACK [i] = 1; - } - } + log_printf(TRACE,Decod_queue,FUNCTION," * is_valid : %d",is_valid); + log_printf(TRACE,Decod_queue,FUNCTION," * context : %d",context); + log_printf(TRACE,Decod_queue,FUNCTION," * depth : %d",depth); + log_printf(TRACE,Decod_queue,FUNCTION," * depth_min : %d",depth_min); + log_printf(TRACE,Decod_queue,FUNCTION," * depth_max : %d",depth_max); + log_printf(TRACE,Decod_queue,FUNCTION," * depth_full : %d",depth_full); +#ifdef DEBUG + log_printf(TRACE,Decod_queue,FUNCTION," * address : 0x%x (0x%x)",reg_QUEUE->front()->_address [index],reg_QUEUE->front()->_address [index]<<2); +#endif + log_printf(TRACE,Decod_queue,FUNCTION," * address_next : 0x%x (0x%x)",reg_QUEUE->front()->_address_next[index],reg_QUEUE->front()->_address_next[index]<<2); + internal_DECOD_OUT_VAL [index] = 1; // in all case, val is set (entry is not empty, and instruction is valid) + if (is_valid) + { + val [i] = 1; + internal_DECOD_OUT_ACK [index] = PORT_READ(in_DECOD_OUT_ACK [i]); + } + else + { + // Consume the instruction (to erase) + internal_DECOD_OUT_ACK [index] = 1; + } + } + } for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { log_printf(TRACE,Decod_queue,FUNCTION," * DECOD_OUT_VAL : %d",val [i]); - - PORT_WRITE(out_DECOD_OUT_VAL [i],val [i]); + + PORT_WRITE(out_DECOD_OUT_VAL [i],val [i]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp (revision 108) @@ -44,27 +44,36 @@ for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { + uint32_t index = reg_LAST_SLOT + i; + + // Stop + if (index >= _param->_nb_inst_decod) + break; + if (_param->_have_port_context_id) - PORT_WRITE(out_DECOD_OUT_CONTEXT_ID [i],reg_QUEUE->front()->_context_id [i]); + PORT_WRITE(out_DECOD_OUT_CONTEXT_ID [i],reg_QUEUE->front()->_context_id [index]); if (_param->_have_port_depth) - PORT_WRITE(out_DECOD_OUT_DEPTH [i],reg_QUEUE->front()->_depth [i]); - PORT_WRITE(out_DECOD_OUT_TYPE [i],reg_QUEUE->front()->_type [i]); - PORT_WRITE(out_DECOD_OUT_OPERATION [i],reg_QUEUE->front()->_operation [i]); - PORT_WRITE(out_DECOD_OUT_NO_EXECUTE [i],reg_QUEUE->front()->_no_execute [i]); - PORT_WRITE(out_DECOD_OUT_IS_DELAY_SLOT [i],reg_QUEUE->front()->_is_delay_slot [i]); - PORT_WRITE(out_DECOD_OUT_ADDRESS_NEXT [i],reg_QUEUE->front()->_address_next [i]); - PORT_WRITE(out_DECOD_OUT_HAS_IMMEDIAT [i],reg_QUEUE->front()->_has_immediat [i]); - PORT_WRITE(out_DECOD_OUT_IMMEDIAT [i],reg_QUEUE->front()->_immediat [i]); - PORT_WRITE(out_DECOD_OUT_READ_RA [i],reg_QUEUE->front()->_read_ra [i]); - PORT_WRITE(out_DECOD_OUT_NUM_REG_RA [i],reg_QUEUE->front()->_num_reg_ra [i]); - PORT_WRITE(out_DECOD_OUT_READ_RB [i],reg_QUEUE->front()->_read_rb [i]); - PORT_WRITE(out_DECOD_OUT_NUM_REG_RB [i],reg_QUEUE->front()->_num_reg_rb [i]); - PORT_WRITE(out_DECOD_OUT_READ_RC [i],reg_QUEUE->front()->_read_rc [i]); - PORT_WRITE(out_DECOD_OUT_NUM_REG_RC [i],reg_QUEUE->front()->_num_reg_rc [i]); - PORT_WRITE(out_DECOD_OUT_WRITE_RD [i],reg_QUEUE->front()->_write_rd [i]); - PORT_WRITE(out_DECOD_OUT_NUM_REG_RD [i],reg_QUEUE->front()->_num_reg_rd [i]); - PORT_WRITE(out_DECOD_OUT_WRITE_RE [i],reg_QUEUE->front()->_write_re [i]); - PORT_WRITE(out_DECOD_OUT_NUM_REG_RE [i],reg_QUEUE->front()->_num_reg_re [i]); - PORT_WRITE(out_DECOD_OUT_EXCEPTION_USE [i],reg_QUEUE->front()->_exception_use [i]); - PORT_WRITE(out_DECOD_OUT_EXCEPTION [i],reg_QUEUE->front()->_exception [i]); + PORT_WRITE(out_DECOD_OUT_DEPTH [i],reg_QUEUE->front()->_depth [index]); + PORT_WRITE(out_DECOD_OUT_TYPE [i],reg_QUEUE->front()->_type [index]); + PORT_WRITE(out_DECOD_OUT_OPERATION [i],reg_QUEUE->front()->_operation [index]); + PORT_WRITE(out_DECOD_OUT_NO_EXECUTE [i],reg_QUEUE->front()->_no_execute [index]); + PORT_WRITE(out_DECOD_OUT_IS_DELAY_SLOT [i],reg_QUEUE->front()->_is_delay_slot [index]); +#ifdef DEBUG + PORT_WRITE(out_DECOD_OUT_ADDRESS [i],reg_QUEUE->front()->_address [index]); +#endif + PORT_WRITE(out_DECOD_OUT_ADDRESS_NEXT [i],reg_QUEUE->front()->_address_next [index]); + PORT_WRITE(out_DECOD_OUT_HAS_IMMEDIAT [i],reg_QUEUE->front()->_has_immediat [index]); + PORT_WRITE(out_DECOD_OUT_IMMEDIAT [i],reg_QUEUE->front()->_immediat [index]); + PORT_WRITE(out_DECOD_OUT_READ_RA [i],reg_QUEUE->front()->_read_ra [index]); + PORT_WRITE(out_DECOD_OUT_NUM_REG_RA [i],reg_QUEUE->front()->_num_reg_ra [index]); + PORT_WRITE(out_DECOD_OUT_READ_RB [i],reg_QUEUE->front()->_read_rb [index]); + PORT_WRITE(out_DECOD_OUT_NUM_REG_RB [i],reg_QUEUE->front()->_num_reg_rb [index]); + PORT_WRITE(out_DECOD_OUT_READ_RC [i],reg_QUEUE->front()->_read_rc [index]); + PORT_WRITE(out_DECOD_OUT_NUM_REG_RC [i],reg_QUEUE->front()->_num_reg_rc [index]); + PORT_WRITE(out_DECOD_OUT_WRITE_RD [i],reg_QUEUE->front()->_write_rd [index]); + PORT_WRITE(out_DECOD_OUT_NUM_REG_RD [i],reg_QUEUE->front()->_num_reg_rd [index]); + PORT_WRITE(out_DECOD_OUT_WRITE_RE [i],reg_QUEUE->front()->_write_re [index]); + PORT_WRITE(out_DECOD_OUT_NUM_REG_RE [i],reg_QUEUE->front()->_num_reg_re [index]); + PORT_WRITE(out_DECOD_OUT_EXCEPTION_USE [i],reg_QUEUE->front()->_exception_use [index]); + PORT_WRITE(out_DECOD_OUT_EXCEPTION [i],reg_QUEUE->front()->_exception [index]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp (revision 108) @@ -31,4 +31,6 @@ for (uint32_t i=0; i<_param->_nb_context; i++) reg_NB_INST [i]=0; + + reg_LAST_SLOT = 0; } else @@ -62,4 +64,7 @@ entry->_no_execute [i] = PORT_READ(in_DECOD_IN_NO_EXECUTE [i]); entry->_is_delay_slot [i] = PORT_READ(in_DECOD_IN_IS_DELAY_SLOT [i]); +#ifdef DEBUG + entry->_address [i] = PORT_READ(in_DECOD_IN_ADDRESS [i]); +#endif entry->_address_next [i] = PORT_READ(in_DECOD_IN_ADDRESS_NEXT [i]); entry->_has_immediat [i] = PORT_READ(in_DECOD_IN_HAS_IMMEDIAT [i]); @@ -90,13 +95,20 @@ if (not reg_QUEUE->empty()) { - bool find = false; + bool find = false; for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { // Test transaction : if ok then invalid slot + // In order by rename logic if (internal_DECOD_OUT_VAL [i] and internal_DECOD_OUT_ACK[i]) { log_printf(TRACE,Decod_queue,FUNCTION,_(" * DECOD_OUT [%d]"),i); +#ifdef DEBUG_TEST + if (reg_LAST_SLOT != i) + throw ERRORMORPHEO(FUNCTION,toString(_("reg_LAST_SLOT (%d) is different at decod_out port (%d)."),reg_LAST_SLOT,i)); +#endif + reg_LAST_SLOT ++; + reg_QUEUE->front()->_val [i] = 0; @@ -108,9 +120,9 @@ } // Test if slot is (again) valid, if yes, then have less one instruction in the entry - find |= reg_QUEUE->front()->_val [i]; + find |= reg_QUEUE->front()->_val [i]; } - // test if can free the entry - if (not find) // no valid instruction in current slot + // test if can free the entry : test if have consume all entry + if (not find) // no valid instruction in current slot { log_printf(TRACE,Decod_queue,FUNCTION,_(" * POP queue")); @@ -119,4 +131,6 @@ delete reg_QUEUE->front(); reg_QUEUE->pop_front(); + + reg_LAST_SLOT = 0; } } @@ -125,4 +139,5 @@ #if defined(DEBUG) and defined(DEBUG_Decod_queue) and (DEBUG >= DEBUG_TRACE) log_printf(TRACE,Decod_queue,FUNCTION," * Dump decod_queue"); + log_printf(TRACE,Decod_queue,FUNCTION," * reg_LAST_SLOT : %d",reg_LAST_SLOT); uint32_t x=0; for (std::list::iterator it=reg_QUEUE->begin(); @@ -144,6 +159,6 @@ ,(*it)->_no_execute [i] ,(*it)->_is_delay_slot [i] - ,(*it)->_address_next [i] - ,(*it)->_address_next [i]<<2 + ,(*it)->_address [i] + ,(*it)->_address [i]<<2 ,(*it)->_has_immediat [i] ,(*it)->_immediat [i] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp (revision 108) @@ -73,4 +73,7 @@ ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); +#ifdef DEBUG + ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); +#endif ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); @@ -159,4 +162,7 @@ INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); +#ifdef DEBUG + INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_ADDRESS ,_param->_nb_inst_decod); +#endif INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); @@ -490,4 +496,7 @@ DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); +#ifdef DEBUG + DELETE1_SC_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_inst_decod); +#endif DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h (revision 108) @@ -87,4 +87,7 @@ public : SC_OUT(Tcontrol_t ) ** out_DECOD_NO_EXECUTE ;//[nb_inst_decod] public : SC_OUT(Tcontrol_t ) ** out_DECOD_IS_DELAY_SLOT ;//[nb_inst_decod] +#ifdef DEBUG + public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS ;//[nb_inst_decod] +#endif public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS_NEXT ;//[nb_inst_decod] public : SC_OUT(Tcontrol_t ) ** out_DECOD_HAS_IMMEDIAT ;//[nb_inst_decod] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp (revision 108) @@ -89,4 +89,7 @@ ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); +#ifdef DEBUG + ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); +#endif ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); @@ -293,4 +296,8 @@ COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_IS_DELAY_SLOT", dest, "in_DECOD_IN_"+toString(i)+"_IS_DELAY_SLOT"); +#ifdef DEBUG + COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_ADDRESS" , + dest, "in_DECOD_IN_"+toString(i)+"_ADDRESS" ); +#endif COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_ADDRESS_NEXT" , dest, "in_DECOD_IN_"+toString(i)+"_ADDRESS_NEXT" ); @@ -435,4 +442,5 @@ // in_DECOD_IN_NO_EXECUTE - component decod // in_DECOD_IN_IS_DELAY_SLOT - component decod + // in_DECOD_IN_ADDRESS - component decod // in_DECOD_IN_ADDRESS_NEXT - component decod // in_DECOD_IN_HAS_IMMEDIAT - component decod @@ -478,4 +486,8 @@ PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_IS_DELAY_SLOT", dest,"out_DECOD_" +toString(i)+"_IS_DELAY_SLOT"); +#ifdef DEBUG + PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_ADDRESS" , + dest,"out_DECOD_" +toString(i)+"_ADDRESS" ); +#endif PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_ADDRESS_NEXT" , dest,"out_DECOD_" +toString(i)+"_ADDRESS_NEXT" ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp (revision 108) @@ -48,4 +48,7 @@ DELETE1_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod,1 ); DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod,1 ); +#ifdef DEBUG + DELETE1_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_inst_decod,_param->_size_instruction_address ); +#endif DELETE1_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod,_param->_size_instruction_address ); DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod,1 ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_1-decod_unit_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_1-decod_unit_1.cfg (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_1-decod_unit_1.cfg (revision 108) @@ -8,2 +8,3 @@ 2 2 +1 # size_depth [0] [nb_context] 4 4 +1 # nb_branch_speculated [0] [nb_context] +4 4 +1 # size_nb_inst_decod Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_1.cfg (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_1.cfg (revision 108) @@ -17,2 +17,3 @@ 2 2 +1 # nb_branch_speculated [2] [nb_context] 8 8 +1 # nb_branch_speculated [3] [nb_context] +4 4 +1 # size_nb_inst_decod Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-a.cfg (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-a.cfg (revision 108) @@ -18,2 +18,3 @@ 2 2 +1 # nb_branch_speculated [2] [nb_context] 8 8 +1 # nb_branch_speculated [3] [nb_context] +4 4 +1 # size_nb_inst_decod Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-b.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-b.cfg (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-b.cfg (revision 108) @@ -18,2 +18,3 @@ 2 2 +1 # nb_branch_speculated [2] [nb_context] 8 8 +1 # nb_branch_speculated [3] [nb_context] +4 4 +1 # size_nb_inst_decod Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_4.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_4.cfg (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_4.cfg (revision 108) @@ -20,2 +20,3 @@ 2 2 +1 # nb_branch_speculated [2] [nb_context] 8 8 +1 # nb_branch_speculated [3] [nb_context] +4 4 +1 # size_nb_inst_decod Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-min.cfg (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-min.cfg (revision 108) @@ -8,2 +8,3 @@ 0 0 +1 # size_depth [0] [nb_context] 1 1 +1 # nb_branch_speculated [0] [nb_context] +1 1 +1 # size_nb_inst_decod Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/main.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/main.cpp (revision 108) @@ -8,5 +8,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/include/test.h" -#define NB_PARAMS 4 +#define NB_PARAMS 5 void usage (int argc, char * argv[]) @@ -22,4 +22,5 @@ err (_(" * size_depth [nb_context] (uint32_t)\n")); err (_(" * nb_branch_speculated [nb_context] (uint32_t)\n")); + err (_(" * size_nb_inst_decod (uint32_t)\n")); exit (1); @@ -69,4 +70,6 @@ _nb_branch_speculated [i] = fromString(argv[x++]); + uint32_t _size_nb_inst_decod = fromString(argv[x++]); + std::vector * _translate_context_id_from_decod_unit = new std::vector [_nb_decod_unit]; @@ -87,4 +90,5 @@ _size_depth , _nb_branch_speculated , + _size_nb_inst_decod , true // is_toplevel ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp (revision 108) @@ -104,4 +104,8 @@ ALLOC2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH_VAL ,"out_CONTEXT_DECOD_UNIT_DEPTH_VAL ",Tcontrol_t,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); ALLOC2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH ,"out_CONTEXT_DECOD_UNIT_DEPTH ",Tdepth_t ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + ALLOC1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,"out_NB_INST_DECOD_ALL ",Tcounter_t,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_UNIT_DECOD_ALL ," in_NB_INST_DECOD_UNIT_DECOD_ALL ",Tcounter_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_NB_INST_CONTEXT_STATE_DECOD_ALL ,"out_NB_INST_CONTEXT_STATE_DECOD_ALL ",Tcounter_t,_param->_nb_context); /******************************************************** @@ -182,4 +186,8 @@ } + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_NB_INST_DECOD_ALL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_NB_INST_DECOD_UNIT_DECOD_ALL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_NB_INST_CONTEXT_STATE_DECOD_ALL ,_param->_nb_context); + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -282,4 +290,8 @@ DELETE2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH_VAL ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); DELETE2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + DELETE1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_NB_INST_DECOD_UNIT_DECOD_ALL ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_NB_INST_CONTEXT_STATE_DECOD_ALL ,_param->_nb_context); } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h (revision 108) @@ -133,4 +133,12 @@ public : SC_OUT(Tcontrol_t ) *** out_CONTEXT_DECOD_UNIT_DEPTH_VAL ;//[nb_decod_unit][nb_decod_unit_context] public : SC_OUT(Tdepth_t ) *** out_CONTEXT_DECOD_UNIT_DEPTH ;//[nb_decod_unit][nb_decod_unit_context] + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcounter_t ) ** out_NB_INST_DECOD_ALL ;//[nb_context] + + public : SC_IN (Tcounter_t ) ** in_NB_INST_DECOD_UNIT_DECOD_ALL ;//[nb_context] + + public : SC_OUT(Tcounter_t ) ** out_NB_INST_CONTEXT_STATE_DECOD_ALL ;//[nb_context] + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -177,4 +185,5 @@ public : void genMealy_event (void); public : void genMealy_depth (void); + public : void genMealy_nb_inst (void); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h (revision 108) @@ -54,4 +54,5 @@ uint32_t * size_depth , uint32_t * nb_branch_speculated , + uint32_t size_nb_inst_decod , uint32_t is_toplevel=false); // public : Parameters (Parameters & param) ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp (revision 108) @@ -176,4 +176,15 @@ # endif + log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Method - genMealy_nb_inst"),_name.c_str()); + + SC_METHOD (genMealy_nb_inst); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + for (uint32_t i=0; i<_param->_nb_context; ++i) + sensitive << (*( in_NB_INST_DECOD_UNIT_DECOD_ALL [i])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp (revision 108) @@ -155,5 +155,14 @@ _ALLOC2_SIGNAL_OUT(out_CONTEXT_DECOD_UNIT_DEPTH ,"DECOD_UNIT_DEPTH" ,Tdepth_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); } - + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("nb_inst",OUT,EAST,_("nb inst"),_param->_nb_context); + + ALLOC1_SIGNAL_OUT(out_NB_INST_DECOD_ALL ,"DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod); + ALLOC1_SIGNAL_IN ( in_NB_INST_DECOD_UNIT_DECOD_ALL ,"DECOD_UNIT_DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod); + ALLOC1_SIGNAL_OUT(out_NB_INST_CONTEXT_STATE_DECOD_ALL ,"CONTEXT_STATE_DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod); + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp (revision 108) @@ -87,4 +87,8 @@ DELETE2_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH_VAL ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],1); DELETE2_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth); + + DELETE1_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); + DELETE1_SIGNAL( in_NB_INST_DECOD_UNIT_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); + DELETE1_SIGNAL(out_NB_INST_CONTEXT_STATE_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_nb_inst.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_nb_inst.cpp (revision 108) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_nb_inst.cpp (revision 108) @@ -0,0 +1,42 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::genMealy_nb_inst" + void Front_end_Glue::genMealy_nb_inst (void) + { + log_begin(Front_end_Glue,FUNCTION); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + Tcounter_t nb_inst = PORT_READ(in_NB_INST_DECOD_UNIT_DECOD_ALL [i]); + + PORT_WRITE(out_NB_INST_DECOD_ALL [i], nb_inst); + PORT_WRITE(out_NB_INST_CONTEXT_STATE_DECOD_ALL [i], nb_inst); + } + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters.cpp (revision 108) @@ -28,4 +28,5 @@ uint32_t * size_depth , uint32_t * nb_branch_speculated , + uint32_t size_nb_inst_decod , uint32_t is_toplevel): morpheo::behavioural::Parameters() @@ -55,5 +56,6 @@ _size_instruction_address = size_address; _size_depth = max(size_depth,_nb_context); - + _size_nb_inst_decod = size_nb_inst_decod; + _have_port_context_id = _size_context_id > 0; _have_port_depth = _size_depth > 0; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp (revision 108) @@ -28,6 +28,18 @@ { log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * PREDICT [%d]",i); + + Tcontrol_t val = PORT_READ(in_PREDICT_VAL [i]); + Tcontrol_t register_ack = PORT_READ(in_PREDICT_REGISTER_ACK [i]); + Tcontrol_t sort_val = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_VAL [i]):true; + Tcontrol_t victim_ack = (_param->_have_port_victim)?PORT_READ(in_PREDICT_VICTIM_ACK [i]):true; + + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * val : %d",val ); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * register_ack : %d",register_ack); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * sort_val : %d",sort_val ); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * victim_ack : %d",victim_ack ); + Tptr_t index = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_INDEX [i]):0; - Tcontrol_t hit = PORT_READ(in_PREDICT_REGISTER_HIT [i][index]); + Tcontrol_t hit = // (_param->_have_port_victim)?sort_val: + PORT_READ(in_PREDICT_REGISTER_HIT [i][index]); Tgeneral_data_t address_src = PORT_READ(in_PREDICT_REGISTER_ADDRESS_SRC [i][index]); @@ -44,18 +56,8 @@ PORT_WRITE(out_PREDICT_IS_ACCURATE [i],PORT_READ(in_PREDICT_REGISTER_IS_ACCURATE [i][index])); - Tcontrol_t val = PORT_READ(in_PREDICT_VAL [i]); - Tcontrol_t register_ack = PORT_READ(in_PREDICT_REGISTER_ACK [i]); - Tcontrol_t sort_val = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_VAL [i]):true; - Tcontrol_t victim_ack = (_param->_have_port_victim)?PORT_READ(in_PREDICT_VICTIM_ACK [i]):true; - - log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * val : %d",val ); - log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * register_ack : %d",register_ack); - log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * sort_val : %d",sort_val ); - log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * victim_ack : %d",victim_ack ); - PORT_WRITE(out_PREDICT_ACK [i], ( // val and register_ack and - sort_val and +// sort_val and victim_ack )); @@ -63,5 +65,5 @@ val and // register_ack and - sort_val and +// sort_val and victim_ack )); @@ -71,6 +73,6 @@ PORT_WRITE(out_PREDICT_VICTIM_VAL [i], ( val and - register_ack and - sort_val // and + register_ack // and +// sort_val and // victim_ack )); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp (revision 108) @@ -54,4 +54,5 @@ // * context is the same // * address_src must be higher that the address, because the address lower is previous the current pc. + // * prediction is no accurate is address_dest is not valid. PORT_WRITE(out_PREDICT_HIT [i][j],hit); PORT_WRITE(out_PREDICT_ADDRESS_SRC [i][j],reg_BTB[num_bank][j]._address_src ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp (revision 108) @@ -224,9 +224,11 @@ dest,"out_PREDICT_"+toString(i)+"_"+toString(j)+"_ADDRESS_SRC"); - // out_OUTPUT_VAL -> glue - // out_OUTPUT_INDEX -> glue - // out_OUTPUT_ADDRESS -> no exist } - } + + // 1 output + // out_OUTPUT_VAL -> glue + // out_OUTPUT_INDEX -> glue + // out_OUTPUT_ADDRESS -> no exist + } //================================================================ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 108) @@ -126,4 +126,9 @@ if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i]) reg_UPT_EMPTY [i] = false; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); } @@ -210,5 +215,5 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write); - + if (miss_ifetch or miss_decod) { @@ -218,5 +223,4 @@ throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state.")); #endif - if (reg_UFPT_NB_NEED_UPDATE [context] == 0) { @@ -312,124 +316,8 @@ reg_UPT_EMPTY [context] = false; // reg_UPT_UPDATE [context] = reg_UPT_TOP [context]; + +// if (miss_ifetch or miss_decod) +// reg_UPT_TOP_EVENT [context] = reg_UPT_TOP [context]; } - - // =================================================================== - // =====[ BRANCH_COMPLETE ]=========================================== - // =================================================================== - - // The branch is complete - // * Hit prediction : - // * update status - // * Miss prediction : - for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) - if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i]) - { - Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; - Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; - Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i]; - Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i]; - Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i]; - - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); - - if (miss) - { - // Have a miss !!! - // Flush UPFT - flush_UFPT [context] = true; - - // Flush UPT - uint32_t top = reg_UPT_TOP [context]; - uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; - - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); - - for (uint32_t j=(depth+1)%_param->_size_upt_queue[context]; - j!=top; - j=(j+1)%_param->_size_upt_queue[context]) - reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; - - -// reg_UPT_BOTTOM [context]; - reg_UPT_TOP [context] = depth; - reg_UPT_TOP_EVENT [context] = top; - - if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context]) - reg_UPT_EMPTY [context] = true; - -#ifdef DEBUG_TEST - if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) - throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); -#endif - - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth); - reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; - - Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; - event_state_t event_state = reg_EVENT_STATE [context]; - bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or - (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or - (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or - (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); -// bool update_ras = (new_update != depth); - -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); - - if (reg_UFPT_NB_NEED_UPDATE [context] > 0) - { - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context); - reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT; - } - else - { -// if (not previous_update_ras) - { - // have ras prediction ? - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context); - - reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT; - - } - } - - if (not previous_update_ras) - { - reg_UPT_UPDATE [context] = new_update; - } - // else no update - - reg_EVENT_DEPTH [context] = depth; - reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State - reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; - reg_EVENT_ADDRESS_DEST [context] = good_addr; - } - else - { - // Hit case - -#ifdef DEBUG_TEST - if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) - throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); -#endif - - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth); - reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK; - } - - // In all case : update good_take - reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take; - - // Write address_dest if need read register - Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; - - if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or - (condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or - (condition == BRANCH_CONDITION_READ_STACK ) ) - reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr; - } // =================================================================== @@ -599,4 +487,128 @@ } + + // =================================================================== + // =====[ BRANCH_COMPLETE ]=========================================== + // =================================================================== + + // The branch is complete + // * Hit prediction : + // * update status + // * Miss prediction : + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) + if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i]) + { + Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; + Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; + Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i]; + Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i]; + Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i]; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); + + if (miss) + { + // Have a miss !!! + // Flush UPFT + flush_UFPT [context] = true; + + // Flush UPT + uint32_t top = reg_UPT_TOP [context]; + uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); + + for (uint32_t j=(depth+1)%_param->_size_upt_queue[context]; + j!=top; + j=(j+1)%_param->_size_upt_queue[context]) + reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; + + +// reg_UPT_BOTTOM [context]; + reg_UPT_TOP [context] = depth; + reg_UPT_TOP_EVENT [context] = top; + + if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context]) + reg_UPT_EMPTY [context] = true; + +#ifdef DEBUG_TEST + if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) + throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); +#endif + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth); + reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; + + Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; + event_state_t event_state = reg_EVENT_STATE [context]; + bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or + (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or + (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or + (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); +// bool update_ras = (new_update != depth); + +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_update_ras : %d",previous_update_ras); + + if (reg_UFPT_NB_NEED_UPDATE [context] > 0) + { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context); + reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT; + } + else + { +// if (not previous_update_ras) + { + // have ras prediction ? + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context); + + reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT; + + } + } + + if (not previous_update_ras) + { + reg_UPT_UPDATE [context] = new_update; + } + // else no update + + reg_EVENT_DEPTH [context] = depth; + reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State + reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; + reg_EVENT_ADDRESS_DEST [context] = good_addr; + } + else + { + // Hit case + +// #ifdef DEBUG_TEST +// if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) +// throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); +// #endif + + if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END) + { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth); + reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK; + } + } + + // In all case : update good_take + reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take; + + // Write address_dest if need read register + Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; + + if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or + (condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or + (condition == BRANCH_CONDITION_READ_STACK ) ) + reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr; + } + // =================================================================== // =====[ BRANCH_EVENT ]============================================== @@ -695,18 +707,42 @@ uint32_t bottom = reg_UPT_BOTTOM [i]; uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; - uint32_t full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); + bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); +// bool empty = reg_UPT_EMPTY [i]; + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); - // Test empty - if (not reg_UPT_EMPTY [i]) + event_state_t event_state = reg_EVENT_STATE [i]; + bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or + (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or + (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or + (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); + + bool find = false; // have slot to update ??? + + // flush all slot after the event + for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; + j!=top; + j=(j+1)%_param->_size_upt_queue[i]) + if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and + (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)) + { + find = true; + reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; + } + + if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and + (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY)) { -#ifdef DEBUG_TEST - if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) - throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); -#endif + find = true; reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; - + } + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find); + + // Test if have update slot + if (find) + { // flush all slot after the event for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; @@ -714,25 +750,23 @@ j=(j+1)%_param->_size_upt_queue[i]) reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; + + reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; + + // reg_UPT_BOTTOM [i]; + // TODO : special case : event is an exception on branch, also depth is not valid + reg_UPT_TOP [i] = depth; // depth is again valid + reg_UPT_TOP_EVENT [i] = top; + + if (bottom == reg_UPT_TOP [i]) + reg_UPT_EMPTY [i] = true; } + + bool update_ras = find and ((top != depth) or full); + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); + + if (not previous_update_ras and update_ras) + reg_UPT_UPDATE [i] = new_update; -// reg_UPT_BOTTOM [i]; - // TODO : special case : event is an exception on branch, also depth is not valid - reg_UPT_TOP [i] = depth; // depth is again valid - reg_UPT_TOP_EVENT [i] = top; - - if (bottom == reg_UPT_TOP [i]) - reg_UPT_EMPTY [i] = true; - - reg_EVENT_VAL [i] = true; - reg_EVENT_UPT_PTR [i] = depth; - event_state_t event_state = reg_EVENT_STATE [i]; - bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or - (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or - (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or - (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); - bool update_ras = (top != depth) or full; - - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); - // new state : // * test if ufpt is empty @@ -741,4 +775,7 @@ // * ok : nothing // * ko : flush upt + reg_EVENT_VAL [i] = true; + reg_EVENT_UPT_PTR [i] = depth; + if (reg_UFPT_NB_NEED_UPDATE [i] > 0) { @@ -766,12 +803,11 @@ else { + // special case : nothing + reg_EVENT_VAL [i] = false; + reg_EVENT_STATE [i] = EVENT_STATE_OK; } } - - if (not previous_update_ras and update_ras) - { - reg_UPT_UPDATE [i] = new_update; - } + // else no update @@ -817,8 +853,12 @@ { for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) - { - reg_UFPT_NB_UPDATE [i] ++; - reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; - } + // EMPTY : no event + // END : already update + // EVENT : previous event + if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state == UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD) + { + reg_UFPT_NB_UPDATE [i] ++; + reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; + } // TOP is next write slot : last slot is TOP-1 @@ -862,7 +902,7 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x",reg_EVENT_ADDRESS_SRC [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x",reg_EVENT_ADDRESS_DEST [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x (%.8x)",reg_EVENT_ADDRESS_DEST [i],reg_EVENT_ADDRESS_DEST [i]<<2); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Fetch_Prediction_Table [%d]",i); @@ -914,4 +954,15 @@ } #endif + +#ifdef DEBUG_TEST + for (uint32_t i=0; i<_param->_nb_context; i++) + { + if (reg_UFPT_NB_NEED_UPDATE [i] > _param->_size_ufpt_queue[i]) + throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_NEED_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_NEED_UPDATE [i],_param->_size_ufpt_queue[i])); + if (reg_UFPT_NB_UPDATE [i] > _param->_size_ufpt_queue[i]) + throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_UPDATE [i],_param->_size_ufpt_queue[i])); + } +#endif + } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp (revision 108) @@ -68,4 +68,7 @@ ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_sum_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_sum_inst_decod); +#ifdef DEBUG + ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_sum_inst_decod); +#endif ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_sum_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_sum_inst_decod); @@ -116,4 +119,5 @@ ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,"out_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); @@ -156,4 +160,7 @@ INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod); INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod); +#ifdef DEBUG + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS ,_param->_sum_inst_decod); +#endif INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod); INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod); @@ -208,4 +215,5 @@ INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_ALL ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_MEM ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_NB_INST_DECOD_ALL ,_param->_nb_context); if (_param->_have_port_depth) { @@ -317,4 +325,7 @@ DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod); +#ifdef DEBUG + DELETE1_SC_SIGNAL(out_DECOD_ADDRESS ,_param->_sum_inst_decod); +#endif DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod); @@ -365,4 +376,5 @@ DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context); DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context); DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context); DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h (revision 108) @@ -94,4 +94,7 @@ public : SC_OUT(Tcontrol_t ) ** out_DECOD_NO_EXECUTE ;//[sum_inst_decod] public : SC_OUT(Tcontrol_t ) ** out_DECOD_IS_DELAY_SLOT ;//[sum_inst_decod] +#ifdef DEBUG + public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS ;//[sum_inst_decod] +#endif public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS_NEXT ;//[sum_inst_decod] public : SC_OUT(Tcontrol_t ) ** out_DECOD_HAS_IMMEDIAT ;//[sum_inst_decod] @@ -152,4 +155,5 @@ public : SC_IN (Tcounter_t ) ** in_NB_INST_COMMIT_ALL ;//[nb_context] public : SC_IN (Tcounter_t ) ** in_NB_INST_COMMIT_MEM ;//[nb_context] + public : SC_OUT(Tcounter_t ) ** out_NB_INST_DECOD_ALL ;//[nb_context] // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 108) @@ -97,4 +97,7 @@ ALLOC1_SIGNAL_OUT (out_DECOD_NO_EXECUTE ,"NO_EXECUTE" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT (out_DECOD_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); +#ifdef DEBUG + ALLOC1_SIGNAL_OUT (out_DECOD_ADDRESS ,"ADDRESS" ,Tgeneral_data_t ,_param->_size_instruction_address ); +#endif ALLOC1_SIGNAL_OUT (out_DECOD_ADDRESS_NEXT ,"ADDRESS_NEXT" ,Tgeneral_data_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_OUT (out_DECOD_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ); @@ -175,4 +178,5 @@ ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_ALL ,"COMMIT_ALL" ,Tcounter_t ,_param->_size_nb_inst_commit); ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_MEM ,"COMMIT_MEM" ,Tcounter_t ,_param->_size_nb_inst_commit); + ALLOC1_SIGNAL_OUT (out_NB_INST_DECOD_ALL ,"DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod ); } @@ -699,4 +703,8 @@ PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_IS_DELAY_SLOT", dest,"out_DECOD_"+toString(x)+"_IS_DELAY_SLOT"); +#ifdef DEBUG + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_ADDRESS" , + dest,"out_DECOD_"+toString(x)+"_ADDRESS" ); +#endif PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_ADDRESS_NEXT" , dest,"out_DECOD_"+toString(x)+"_ADDRESS_NEXT" ); @@ -809,5 +817,5 @@ uint32_t y=(_param->_translate_context_id_from_decod_unit[i])[j]; - dest = _name+"_context_state"; + dest = _name+"_glue"; #ifdef POSITION _component->interface_map (src ,"nb_inst_"+toString(j), @@ -815,6 +823,6 @@ #endif - COMPONENT_MAP(_component,src ,"out_NB_INST_"+toString(j)+"_DECOD_ALL", - dest, "in_NB_INST_"+toString(y)+"_DECOD_ALL"); + COMPONENT_MAP(_component,src ,"out_NB_INST_"+toString(j)+ "_DECOD_ALL", + dest, "in_NB_INST_"+toString(y)+"_DECOD_UNIT_DECOD_ALL"); } @@ -965,12 +973,10 @@ // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - // in_NB_INST_DECOD_ALL - component_decod_unit - for (uint32_t i=0; i<_param->_nb_context; ++i) { dest = _name; #ifdef POSITION - _component->interface_map (src ,"nb_inst", - dest,"nb_inst"); + _component->interface_map (src ,"nb_inst_"+toString(i), + dest,"nb_inst_"+toString(i)); #endif @@ -979,4 +985,13 @@ PORT_MAP(_component,src , "in_NB_INST_"+toString(i)+"_COMMIT_MEM", dest, "in_NB_INST_"+toString(i)+"_COMMIT_MEM"); + + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"nb_inst_"+toString(i), + dest,"nb_inst_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src , "in_NB_INST_"+toString(i)+ "_DECOD_ALL", + dest,"out_NB_INST_"+toString(i)+"_CONTEXT_STATE_DECOD_ALL"); } @@ -1218,4 +1233,20 @@ // out_CONTEXT_DECOD_UNIT_DEPTH_VAL - component_decod_unit // out_CONTEXT_DECOD_UNIT_DEPTH - component_decod_unit + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"nb_inst_"+toString(i), + dest,"nb_inst_"+toString(i)); +#endif + + PORT_MAP(_component,src ,"out_NB_INST_"+toString(i)+"_DECOD_ALL", + dest,"out_NB_INST_"+toString(i)+"_DECOD_ALL"); + + // in_NB_INST_DECOD_UNIT_DECOD_ALL - component_decod_unit + // out_NB_INST_CONTEXT_STATE_DECOD_ALL - component_context_state + } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp (revision 108) @@ -49,4 +49,7 @@ DELETE1_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod,1 ); DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod,1 ); +#ifdef DEBUG + DELETE1_SIGNAL(out_DECOD_ADDRESS ,_param->_sum_inst_decod,_param->_size_instruction_address ); +#endif DELETE1_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod,_param->_size_instruction_address ); DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod,1 ); @@ -102,4 +105,5 @@ DELETE1_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context,_param->_size_nb_inst_commit); DELETE1_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context,_param->_size_nb_inst_commit); + DELETE1_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp (revision 108) @@ -109,4 +109,6 @@ _array_size_nb_inst_decod [i] = log2(_size_decod_queue[i]+1); + uint32_t size_nb_inst_decod = max(_array_size_nb_inst_decod,_nb_decod_unit); + _param_ifetch_unit = new behavioural::core::multi_front_end::front_end::ifetch_unit::Parameters * [_nb_context]; for (uint32_t i=0; i<_nb_context; ++i) @@ -236,5 +238,6 @@ size_instruction_address , _array_size_depth , - _upt_size_queue //_nb_branch_speculated + _upt_size_queue ,//_nb_branch_speculated + size_nb_inst_decod ); @@ -244,5 +247,5 @@ _size_instruction_address = size_instruction_address; _size_general_data = size_general_data; - _size_nb_inst_decod = max(_array_size_nb_inst_decod,_nb_decod_unit); + _size_nb_inst_decod = size_nb_inst_decod; _size_nb_inst_commit = size_nb_inst_commit; _size_depth = max(_array_size_depth,_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg (revision 108) @@ -11,4 +11,5 @@ 1 1 +1 # nb_inst_branch_complete 0 0 +1 # nb_branch_speculated [0][0] [nb_front_end][nb_context] +1 1 +1 # size_nb_inst_decod 32 32 +1 # size_general_data 1 1 +1 # size_store_queue_ptr Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg (revision 108) @@ -11,4 +11,5 @@ 1 1 +1 # nb_inst_branch_complete 0 0 +1 # nb_branch_speculated [0][0] [nb_front_end][nb_context] +1 1 +1 # size_nb_inst_decod 32 32 +1 # size_general_data 1 1 +1 # size_store_queue_ptr Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp (revision 108) @@ -8,5 +8,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/include/test.h" -#define NB_PARAMS 15 +#define NB_PARAMS 16 void usage (int argc, char * argv[]) @@ -25,4 +25,5 @@ err (_(" * nb_inst_branch_complete (uint32_t )\n")); err (_(" * nb_branch_speculated [nb_front_end][nb_context] (uint32_t )\n")); + err (_(" * size_nb_inst_decod (uint32_t )\n")); err (_(" * size_general_data (uint32_t )\n")); err (_(" * size_store_queue_ptr (uint32_t )\n")); @@ -88,4 +89,5 @@ } + uint32_t _size_nb_inst_decod = fromString(argv[x++]); uint32_t _size_general_data = fromString(argv[x++]); uint32_t _size_store_queue_ptr = fromString(argv[x++]); @@ -112,4 +114,5 @@ _nb_inst_branch_complete , _nb_branch_speculated , + _size_nb_inst_decod , _size_general_data , _size_store_queue_ptr , Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp (revision 108) @@ -68,4 +68,7 @@ ALLOC2_SC_SIGNAL( in_INSERT_NO_EXECUTE ," in_INSERT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); ALLOC2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ," in_INSERT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +#ifdef DEBUG + ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS ," in_INSERT_ADDRESS ",Taddress_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +#endif ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT ," in_INSERT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION ," in_INSERT_EXCEPTION ",Texception_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); @@ -167,4 +170,5 @@ ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_ALL ,"out_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_MEM ,"out_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); ALLOC2_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); ALLOC2_SC_SIGNAL( in_DEPTH_MAX ," in_DEPTH_MAX ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); @@ -206,4 +210,7 @@ INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +#ifdef DEBUG + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +#endif INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); @@ -317,4 +324,5 @@ INSTANCE2_SC_SIGNAL(_Commit_unit,out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); INSTANCE2_SC_SIGNAL(_Commit_unit,out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_NB_INST_DECOD_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); if (_param->_have_port_depth) @@ -617,4 +625,7 @@ DELETE2_SC_SIGNAL( in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); DELETE2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +#ifdef DEBUG + DELETE2_SC_SIGNAL( in_INSERT_ADDRESS ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +#endif DELETE2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); DELETE2_SC_SIGNAL( in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); @@ -714,4 +725,5 @@ DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); DELETE2_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1]); DELETE2_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 108) @@ -83,4 +83,7 @@ public : SC_IN (Tcontrol_t ) *** in_INSERT_NO_EXECUTE ;//[nb_rename_unit][nb_inst_insert] public : SC_IN (Tcontrol_t ) *** in_INSERT_IS_DELAY_SLOT ;//[nb_rename_unit][nb_inst_insert] +#ifdef DEBUG + public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS ;//[nb_rename_unit][nb_inst_insert] +#endif public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS_NEXT ;//[nb_rename_unit][nb_inst_insert] public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION ;//[nb_rename_unit][nb_inst_insert] @@ -195,4 +198,5 @@ public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context] public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] + public : SC_IN (Tcounter_t ) *** in_NB_INST_DECOD_ALL ;//[nb_front_end][nb_context] // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h (revision 108) @@ -81,4 +81,5 @@ uint32_t nb_inst_branch_complete , uint32_t ** nb_branch_speculated , + uint32_t size_nb_inst_decod , uint32_t size_general_data , uint32_t size_store_queue_ptr , Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h (revision 108) @@ -90,5 +90,9 @@ public : Tspecial_data_t flags ; public : Tcontrol_t no_sequence ; + public : Tcontrol_t speculative ; //public : Tgeneral_data_t data_commit ; // branch's destination +#ifdef DEBUG + public : Taddress_t address ; +#endif public : Taddress_t address_next ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 108) @@ -71,4 +71,7 @@ _ALLOC2_SIGNAL_IN ( in_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); _ALLOC2_SIGNAL_IN ( in_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +#ifdef DEBUG + _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +#endif _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); @@ -216,4 +219,5 @@ _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_ALL ,"commit_all",Tcounter_t ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_MEM ,"commit_mem",Tcounter_t ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_NB_INST_DECOD_ALL ,"decod_all" ,Tcounter_t ,_param->_size_nb_inst_decod ,_param->_nb_front_end, _param->_nb_context[it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 108) @@ -39,4 +39,7 @@ DELETE2_SIGNAL( in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); DELETE2_SIGNAL( in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); +#ifdef DEBUG + DELETE2_SIGNAL( in_INSERT_ADDRESS ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address ); +#endif DELETE2_SIGNAL( in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address ); DELETE2_SIGNAL( in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception ); @@ -143,4 +146,5 @@ DELETE2_SIGNAL(out_NB_INST_COMMIT_ALL ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_commit); DELETE2_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_commit); + DELETE2_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_decod); DELETE2_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 108) @@ -77,5 +77,6 @@ case EVENT_STATE_WAITEND : { - if (reg_NB_INST_COMMIT_ALL [i][j] == 0) + Tcounter_t nb_inst_all = PORT_READ(in_NB_INST_DECOD_ALL [i][j]) + reg_NB_INST_COMMIT_ALL [i][j]; + if (nb_inst_all == 0) { reg_EVENT_STATE [i][j] = EVENT_STATE_END; @@ -163,4 +164,8 @@ entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); entry->no_sequence = type == TYPE_BRANCH; + entry->speculative = true; +#ifdef DEBUG + entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); +#endif entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]); @@ -173,26 +178,38 @@ // other -> wait end of instruction // * OTHER - if (exception == EXCEPTION_NONE) - { - Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); - // no_execute : l.j, l.nop, l.rfe - - log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); - - switch (type) - { - case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;} - case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;} - default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} - } - } - else - { - // Have an exception : wait head of ROB - - // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap - - entry->state = ROB_END_EXCEPTION_WAIT_HEAD; - } + +// bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; + +// log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); + +// if (flush) +// { +// entry->state = ROB_END_MISS; // All type (branch, memory and others), because, is not execute +// } +// else + { + if (exception == EXCEPTION_NONE) + { + Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); + // no_execute : l.j, l.nop, l.rfe + + log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); + + switch (type) + { + case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;} + case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;} + default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} + } + } + else + { + // Have an exception : wait head of ROB + + // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap + + entry->state = ROB_END_EXCEPTION_WAIT_HEAD; + } + } // Push in rob @@ -351,8 +368,8 @@ Ttype_t type = entry->type ; - if ((state == ROB_END_OK ) or // LOAD_MISS + if ((state == ROB_END_OK ) or // (state == ROB_END_KO ) or - (state == ROB_END_BRANCH_MISS)// or -// (state == ROB_END_LOAD_MISS ) or + (state == ROB_END_BRANCH_MISS) or + (state == ROB_END_LOAD_MISS )// or // (state == ROB_END_MISS ) or // (state == ROB_END_EXCEPTION ) @@ -468,7 +485,16 @@ // =====[ EVENT ]===================================================== // =================================================================== - { - // Not yet implemented - } +// for (uint32_t i=0; i < _param->_nb_front_end; ++i) +// for (uint32_t j=0; j < _param->_nb_context[i]; ++j) +// if (PORT_READ(in_EVENT_VAL [i][j]) and internal_EVENT_ACK [i][j]) +// { +// log_printf(TRACE,Commit_unit,FUNCTION," * EVENT [%d][%d]",i,j); + +// reg_PC_CURRENT [i][j] = PORT_READ(in_EVENT_ADDRESS [i][j]); +// reg_PC_CURRENT_IS_DS [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); // ?? +// reg_PC_CURRENT_IS_DS_TAKE [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); +// reg_PC_NEXT [i][j] = PORT_READ(in_EVENT_ADDRESS_NEXT [i][j]); +// // PORT_READ(in_EVENT_ADDRESS_NEXT_VAL [i][j]); +// } // =================================================================== @@ -505,10 +531,10 @@ bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; - - Tcontrol_t is_valid = (((depth == depth_min) or - depth_full or - ((depth_min <= depth_max)? - ((depth >= depth_min) and (depth <=depth_max)): - ((depth >= depth_min) or (depth <=depth_max)))) + bool speculative = entry->speculative and not (depth == depth_min); + Tcontrol_t is_valid = ((not speculative or + (speculative and (depth_full or // all is valid + ((depth_min <= depth_max)? // test if depth is overflow + ((depth >= depth_min) and (depth <=depth_max)): + ((depth >= depth_min) or (depth <=depth_max)))))) and not flush); @@ -532,11 +558,18 @@ case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} + case ROB_END_BRANCH_MISS : case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} + case ROB_END_LOAD_MISS_UPDATE : + case ROB_END_LOAD_MISS : case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} + case ROB_END_OK : case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} + case ROB_END_KO : case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} + case ROB_END_EXCEPTION_UPDATE : + case ROB_END_EXCEPTION : case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} @@ -548,14 +581,7 @@ // can't have miss speculation case ROB_STORE_HEAD_OK : - case ROB_END_OK : - case ROB_END_KO : - case ROB_END_BRANCH_MISS : - case ROB_END_LOAD_MISS_UPDATE : - case ROB_END_LOAD_MISS : - case ROB_END_EXCEPTION_UPDATE : - case ROB_END_EXCEPTION : default : { - throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n")); + throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str())); break; } @@ -566,5 +592,7 @@ // test if instruction is not speculative //------------------------------------------------------ - if (entry->depth == depth_min) + entry->speculative = speculative; +// if (entry->depth == depth_min) + if (not speculative) { switch (state) @@ -574,5 +602,5 @@ case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} - default : {break;} + default : {break;} // else, no change } } @@ -587,5 +615,5 @@ case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} - default : {break;} + default : {break;} // else, no change } } @@ -599,80 +627,131 @@ // =================================================================== - log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); - log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); - log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); - - for (uint32_t i=0; i<_param->_nb_front_end; i++) - for (uint32_t j=0; j<_param->_nb_context [i]; j++) +#ifdef STATISTICS + for (uint32_t i=0; i<_param->_nb_bank; i++) + if (usage_is_set(_usage,USE_STATISTICS)) + *(_stat_bank_nb_inst [i]) += _rob[i].size(); +#endif + +#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true) + { + log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); + log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); + log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context [i]; j++) + { + log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d]",i,j); + log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s",toString(reg_EVENT_STATE [i][j]).c_str()); + log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]); + log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : %d",reg_NB_INST_COMMIT_ALL[i][j]); + log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_MEM : %d",reg_NB_INST_COMMIT_MEM[i][j]); + log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); + log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); + } + + for (uint32_t i=0; i<_param->_nb_bank; i++) { - log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] state : %s",i,j,toString(reg_EVENT_STATE [i][j]).c_str()); - log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_all : %d",reg_NB_INST_COMMIT_ALL[i][j]); - log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_mem : %d",reg_NB_INST_COMMIT_MEM[i][j]); - log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); - log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); + uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; + + log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]); + + uint32_t x=0; + for (std::list::iterator it=_rob[num_bank].begin(); + it!=_rob[num_bank].end(); + it++) + { + log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s - %d", + x, + (*it)->front_end_id , + (*it)->context_id , + (*it)->rename_unit_id , + (*it)->depth , + (*it)->type , + (*it)->operation , + (*it)->is_delay_slot , + (*it)->use_store_queue , + (*it)->store_queue_ptr_write , + (*it)->use_load_queue , + (*it)->load_queue_ptr_write , + toString((*it)->state).c_str() , + (*it)->ptr ); + log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", + (*it)->read_ra , + (*it)->num_reg_ra_log , + (*it)->num_reg_ra_phy , + (*it)->read_rb , + (*it)->num_reg_rb_log , + (*it)->num_reg_rb_phy , + (*it)->read_rc , + (*it)->num_reg_rc_log , + (*it)->num_reg_rc_phy , + (*it)->write_rd , + (*it)->num_reg_rd_log , + (*it)->num_reg_rd_phy_old , + (*it)->num_reg_rd_phy_new , + (*it)->write_re , + (*it)->num_reg_re_log , + (*it)->num_reg_re_phy_old , + (*it)->num_reg_re_phy_new ); + + log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)", + (*it)->exception_use , + (*it)->exception , + (*it)->flags , + (*it)->no_sequence , + (*it)->speculative , + (*it)->address , + (*it)->address<<2 , + (*it)->address_next , + (*it)->address_next<<2 + ); + + x++; + } } - - for (uint32_t i=0; i<_param->_nb_bank; i++) - { - log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",i,(int)_rob[i].size(), reg_BANK_PTR [i]); - -#ifdef STATISTICS - if (usage_is_set(_usage,USE_STATISTICS)) - *(_stat_bank_nb_inst [i]) += _rob[i].size(); -#endif - - uint32_t x=0; - for (std::list::iterator it=_rob[i].begin(); - it!=_rob[i].end(); - it++) - { - log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s - %d", - x, - (*it)->front_end_id , - (*it)->context_id , - (*it)->rename_unit_id , - (*it)->depth , - (*it)->type , - (*it)->operation , -// (*it)->address , -// (*it)->address << 2 , - (*it)->is_delay_slot , - (*it)->use_store_queue , - (*it)->store_queue_ptr_write , - (*it)->use_load_queue , - (*it)->load_queue_ptr_write , - toString((*it)->state).c_str() , - (*it)->ptr ); - log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", - (*it)->read_ra , - (*it)->num_reg_ra_log , - (*it)->num_reg_ra_phy , - (*it)->read_rb , - (*it)->num_reg_rb_log , - (*it)->num_reg_rb_phy , - (*it)->read_rc , - (*it)->num_reg_rc_log , - (*it)->num_reg_rc_phy , - (*it)->write_rd , - (*it)->num_reg_rd_log , - (*it)->num_reg_rd_phy_old , - (*it)->num_reg_rd_phy_new , - (*it)->write_re , - (*it)->num_reg_re_log , - (*it)->num_reg_re_phy_old , - (*it)->num_reg_re_phy_new ); - - log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x (%.8x)", - (*it)->exception_use , - (*it)->exception , - (*it)->flags , - (*it)->no_sequence , - (*it)->address_next , - (*it)->address_next<<2 - ); - - x++; - } - } + } +#endif + +#ifdef DEBUG_TEST + { + uint32_t x=reg_NUM_BANK_HEAD; + if (not _rob[x].empty()) + { + entry_t * entry = _rob [x].front(); + + if (false +// or (entry->state == ROB_EMPTY ) +// or (entry->state == ROB_BRANCH_WAIT_END ) +// or (entry->state == ROB_BRANCH_COMPLETE ) +// or (entry->state == ROB_STORE_WAIT_HEAD_OK ) +// //or (entry->state == ROB_STORE_WAIT_HEAD_KO ) +// or (entry->state == ROB_STORE_HEAD_OK ) +// or (entry->state == ROB_STORE_HEAD_KO ) +// or (entry->state == ROB_OTHER_WAIT_END ) +// or (entry->state == ROB_MISS_WAIT_END ) +// or (entry->state == ROB_END_OK_SPECULATIVE ) + or (entry->state == ROB_END_OK ) +// or (entry->state == ROB_END_KO_SPECULATIVE ) +// or (entry->state == ROB_END_KO ) +// or (entry->state == ROB_END_BRANCH_MISS_SPECULATIVE) + or (entry->state == ROB_END_BRANCH_MISS ) +// or (entry->state == ROB_END_LOAD_MISS_SPECULATIVE ) +// or (entry->state == ROB_END_LOAD_MISS_UPDATE ) + or (entry->state == ROB_END_LOAD_MISS ) +// or (entry->state == ROB_END_MISS ) +// or (entry->state == ROB_END_EXCEPTION_WAIT_HEAD ) +// or (entry->state == ROB_END_EXCEPTION_UPDATE ) +// or (entry->state == ROB_END_EXCEPTION ) + ) + if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id]) + throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (%x) is different of reg_PC_CURRENT[%d][%d] (%x).\n"), + entry->address, + entry->front_end_id, + entry->context_id, + reg_PC_CURRENT[entry->front_end_id][entry->context_id])); + } + } +#endif #if defined(STATISTICS) or defined(VHDL_TESTBENCH) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp (revision 108) @@ -31,4 +31,5 @@ uint32_t nb_inst_branch_complete , uint32_t ** nb_branch_speculated , + uint32_t size_nb_inst_decod , uint32_t size_general_data , uint32_t size_store_queue_ptr , @@ -93,4 +94,5 @@ _size_depth = max(_array_size_depth,_nb_front_end,_nb_context); _size_nb_inst_commit = log2(_size_queue)+1; + _size_nb_inst_decod = size_nb_inst_decod; _have_port_front_end_id = _size_front_end_id > 0; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp (revision 108) @@ -27,8 +27,8 @@ if (not is_multiple(_size_queue, _nb_bank)) - test.error(toString(_("nb_bank must be a multiple of size_queue.\n"))); + test.error(toString(_("nb_bank (%d) must be a multiple of size_queue (%d).\n"),_nb_bank,_size_queue)); if (not is_multiple(_nb_bank, _nb_inst_issue)) - test.error(toString(_("nb_inst_issue must be a multiple of nb_bank.\n"))); + test.error(toString(_("nb_inst_issue (%d) must be a multiple of nb_bank (%d) .\n"),_nb_inst_issue,_nb_bank)); if (_nb_rename_unit_select > _nb_rename_unit) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Free_List_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Free_List_unit.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Free_List_unit.h (revision 108) @@ -89,5 +89,5 @@ // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - private : uint32_t internal_BANK_PRIORITY; + private : uint32_t reg_BANK_PRIORITY; private : Tcontrol_t * internal_POP_ACK ; //[nb_pop] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_pop.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_pop.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_pop.cpp (revision 108) @@ -28,21 +28,30 @@ for (uint32_t i=0; i<_param->_nb_pop; i++) { - uint32_t offset = i*_param->_nb_bank_by_pop; + log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); + + uint32_t offset = i*_param->_nb_bank_by_pop; // GPR bool gpr_ack = not PORT_READ(in_POP_GPR_VAL[i]); + log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_POP_GPR_VAL[i])); + if (not gpr_ack) for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) { - uint32_t bank = offset+((j+internal_BANK_PRIORITY)%_param->_nb_bank_by_pop); + uint32_t bank = offset+((j+reg_BANK_PRIORITY)%_param->_nb_bank_by_pop + ); + + log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); if (not _gpr_list[bank].empty()) { // find + log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[bank].front()); + gpr_ack = true; internal_POP_GPR_BANK [i] = bank; PORT_WRITE(out_POP_GPR_NUM_REG [i], - //(bank << _param->_shift) | + //(bank << _param->_shift) | // only in VHDL _gpr_list[bank].front()); @@ -54,16 +63,23 @@ bool spr_ack = not PORT_READ(in_POP_SPR_VAL[i]); + log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i])); + if (not spr_ack) for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) { - uint32_t bank = offset+((j+internal_BANK_PRIORITY)%_param->_nb_bank_by_pop); + uint32_t bank = offset+((j+reg_BANK_PRIORITY)%_param->_nb_bank_by_pop + ); + + log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); if (not _spr_list[bank].empty()) { // find + log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[bank].front()); + spr_ack = true; internal_POP_SPR_BANK [i] = bank; PORT_WRITE(out_POP_SPR_NUM_REG [i], - //(bank << _param->_shift) | + //(bank << _param->_shift) | // only in VHDL _spr_list[bank].front()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_gpr.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_gpr.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_gpr.cpp (revision 108) @@ -26,4 +26,5 @@ log_function(Free_List_unit,FUNCTION,_name.c_str()); + // bank conflit bool bank_use [_param->_nb_bank]; for (uint32_t i=0; i<_param->_nb_bank; i++) @@ -32,13 +33,22 @@ for (uint32_t i=0; i<_param->_nb_push; i++) { + log_printf(TRACE,Free_List_unit,FUNCTION," * PUSH [%d]",i); + bool gpr_ack = not PORT_READ(in_PUSH_GPR_VAL[i]); + + log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_PUSH_GPR_VAL[i])); if (not gpr_ack) { - // num_bank : MSB - uint32_t bank = PORT_READ(in_PUSH_GPR_NUM_REG[i]) >> _param->_bank_gpr_size_slot; +// // num_bank : MSB +// uint32_t bank = PORT_READ(in_PUSH_GPR_NUM_REG[i]) >> _param->_bank_gpr_size_slot; + // num_bank : LSB + uint32_t bank = PORT_READ(in_PUSH_GPR_NUM_REG[i]) & _param->_mask_gpr; if (not bank_use [bank]) { + log_printf(TRACE,Free_List_unit,FUNCTION," * find "); + log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); + // find gpr_ack = true; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_spr.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_spr.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_spr.cpp (revision 108) @@ -36,6 +36,8 @@ if (not spr_ack) { - // num_bank : MSB - uint32_t bank = PORT_READ(in_PUSH_SPR_NUM_REG[i]) >> _param->_bank_spr_size_slot; +// // num_bank : MSB +// uint32_t bank = PORT_READ(in_PUSH_SPR_NUM_REG[i]) >> _param->_bank_spr_size_slot; + // num_bank : LSB + uint32_t bank = PORT_READ(in_PUSH_SPR_NUM_REG[i]) & _param->_mask_spr; if (not bank_use [bank]) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp (revision 108) @@ -28,5 +28,5 @@ if (PORT_READ(in_NRESET) == 0) { - internal_BANK_PRIORITY = 0; + reg_BANK_PRIORITY = 0; for (uint32_t i=0; i<_param->_nb_bank; i++) { @@ -59,7 +59,8 @@ { log_printf(TRACE,Free_List_unit,FUNCTION," * PUSH_GPR[%d]",i); + log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",internal_PUSH_GPR_BANK[i]); + log_printf(TRACE,Free_List_unit,FUNCTION," * num_reg : %d",PORT_READ(in_PUSH_GPR_NUM_REG [i])); - _gpr_list [internal_PUSH_GPR_BANK[i]].push_back(//_param->_mask_gpr & - PORT_READ(in_PUSH_GPR_NUM_REG [i])); + _gpr_list [internal_PUSH_GPR_BANK[i]].push_back(PORT_READ(in_PUSH_GPR_NUM_REG [i])); } // ================================================== @@ -70,11 +71,12 @@ { log_printf(TRACE,Free_List_unit,FUNCTION," * PUSH_SPR[%d]",i); + log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",internal_PUSH_SPR_BANK[i]); + log_printf(TRACE,Free_List_unit,FUNCTION," * num_reg : %d",PORT_READ(in_PUSH_SPR_NUM_REG [i])); - _spr_list [internal_PUSH_SPR_BANK[i]].push_back(//_param->_mask_spr & - PORT_READ(in_PUSH_SPR_NUM_REG [i])); + _spr_list [internal_PUSH_SPR_BANK[i]].push_back(PORT_READ(in_PUSH_SPR_NUM_REG [i])); } - if (_param->_priority == PRIORITY_ROUND_ROBIN) - internal_BANK_PRIORITY = (internal_BANK_PRIORITY+1)%_param->_nb_bank_by_pop; + if (_param->_priority == PRIORITY_ROUND_ROBIN) + reg_BANK_PRIORITY = (reg_BANK_PRIORITY+1)%_param->_nb_bank_by_pop; #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Free_List_unit == true) @@ -83,10 +85,11 @@ log_printf(TRACE,Free_List_unit,FUNCTION," * Dump Free List"); - for (uint32_t i=0; i<_param->_nb_bank; ++i) { + log_printf(TRACE,Free_List_unit,FUNCTION," * GPR [%d] - NB_ELT : %d",i,_gpr_list[i].size()); + uint32_t j=0; - for (std::list::iterator it=_gpr_list->begin(); - it!=_gpr_list->end(); + for (std::list::iterator it=_gpr_list[i].begin(); + it!=_gpr_list[i].end(); ) { @@ -95,5 +98,5 @@ for (uint32_t x=0; xend()) + if (it==_gpr_list[i].end()) break; else @@ -108,7 +111,9 @@ for (uint32_t i=0; i<_param->_nb_bank; ++i) { + log_printf(TRACE,Free_List_unit,FUNCTION," * SPR [%d] - NB_ELT : %d",i,_spr_list[i].size()); + uint32_t j=0; - for (std::list::iterator it=_spr_list->begin(); - it!=_spr_list->end(); + for (std::list::iterator it=_spr_list[i].begin(); + it!=_spr_list[i].end(); ) { @@ -117,5 +122,5 @@ for (uint32_t x=0; xend()) + if (it==_spr_list[i].end()) break; else @@ -132,7 +137,8 @@ #ifdef DEBUG_TEST if (1) + for (uint32_t i=0; i<_param->_nb_bank; ++i) { - for (std::list::iterator it1=_gpr_list->begin(); - it1!=_gpr_list->end(); + for (std::list::iterator it1=_gpr_list[i].begin(); + it1!=_gpr_list[i].end(); ++it1 ) @@ -141,5 +147,5 @@ it2 ++; - while (it2 != _gpr_list->end()) + while (it2 != _gpr_list[i].end()) { if (*it1 == *it2) @@ -149,6 +155,6 @@ } - for (std::list::iterator it1=_spr_list->begin(); - it1!=_spr_list->end(); + for (std::list::iterator it1=_spr_list[i].begin(); + it1!=_spr_list[i].end(); ++it1 ) @@ -157,5 +163,5 @@ it2 ++; - while (it2 != _spr_list->end()) + while (it2 != _spr_list[i].end()) { if (*it1 == *it2) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Parameters.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Parameters.cpp (revision 108) @@ -52,5 +52,5 @@ _bank_gpr_size_slot = size_general_register-log2(nb_bank); - _mask_gpr = gen_mask (_bank_gpr_size_slot); + _mask_gpr = gen_mask (log2(nb_bank)); uint32_t spr_nb_slot = nb_special_register - nb_thread*_nb_special_register_logic; @@ -59,5 +59,5 @@ _bank_spr_size_slot = size_special_register-log2(nb_bank); - _mask_spr = gen_mask (_bank_spr_size_slot); + _mask_spr = gen_mask (log2(nb_bank)); if (is_toplevel) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/test.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/test.cpp (revision 108) @@ -59,4 +59,7 @@ ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ," in_RENAME_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ," in_RENAME_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); +#ifdef DEBUG + ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS ",Taddress_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); +#endif ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ," in_RENAME_IN_ADDRESS_NEXT ",Taddress_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ," in_RENAME_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); @@ -84,4 +87,7 @@ ALLOC1_SC_SIGNAL(out_RENAME_OUT_NO_EXECUTE ,"out_RENAME_OUT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_rename); ALLOC1_SC_SIGNAL(out_RENAME_OUT_IS_DELAY_SLOT,"out_RENAME_OUT_IS_DELAY_SLOT",Tcontrol_t ,_param->_nb_inst_rename); +#ifdef DEBUG + ALLOC1_SC_SIGNAL(out_RENAME_OUT_ADDRESS ,"out_RENAME_OUT_ADDRESS ",Taddress_t ,_param->_nb_inst_rename); +#endif ALLOC1_SC_SIGNAL(out_RENAME_OUT_ADDRESS_NEXT ,"out_RENAME_OUT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_inst_rename); ALLOC1_SC_SIGNAL(out_RENAME_OUT_HAS_IMMEDIAT ,"out_RENAME_OUT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_rename); @@ -99,4 +105,6 @@ ALLOC1_SC_SIGNAL(out_RENAME_OUT_EXCEPTION_USE,"out_RENAME_OUT_EXCEPTION_USE",Texception_t ,_param->_nb_inst_rename); ALLOC1_SC_SIGNAL(out_RENAME_OUT_EXCEPTION ,"out_RENAME_OUT_EXCEPTION ",Texception_t ,_param->_nb_inst_rename); + + ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_STATE ," in_RETIRE_EVENT_STATE ",Tevent_state_t ,_param->_nb_front_end,_param->_nb_context[it1]); /******************************************************** @@ -121,4 +129,7 @@ INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); +#ifdef DEBUG + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); +#endif INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); @@ -149,4 +160,7 @@ INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_NO_EXECUTE ,_param->_nb_inst_rename); INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_IS_DELAY_SLOT,_param->_nb_inst_rename); +#ifdef DEBUG + INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_ADDRESS ,_param->_nb_inst_rename); +#endif INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_ADDRESS_NEXT ,_param->_nb_inst_rename); INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_HAS_IMMEDIAT ,_param->_nb_inst_rename); @@ -165,4 +179,6 @@ INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_EXCEPTION ,_param->_nb_inst_rename); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1]); + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -194,4 +210,8 @@ SC_START(5); in_NRESET->write(1); + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + in_RETIRE_EVENT_STATE [i][j]->write(EVENT_STATE_NO_EVENT); LABEL("Loop of Test"); @@ -329,4 +349,7 @@ delete [] in_RENAME_IN_NO_EXECUTE ; delete [] in_RENAME_IN_IS_DELAY_SLOT ; +#ifdef DEBUG + delete [] in_RENAME_IN_ADDRESS ; +#endif delete [] in_RENAME_IN_ADDRESS_NEXT ; delete [] in_RENAME_IN_HAS_IMMEDIAT ; @@ -354,4 +377,7 @@ delete [] out_RENAME_OUT_NO_EXECUTE ; delete [] out_RENAME_OUT_IS_DELAY_SLOT; +#ifdef DEBUG + delete [] out_RENAME_OUT_ADDRESS ; +#endif delete [] out_RENAME_OUT_ADDRESS_NEXT ; delete [] out_RENAME_OUT_HAS_IMMEDIAT ; @@ -369,4 +395,6 @@ delete [] out_RENAME_OUT_EXCEPTION_USE; delete [] out_RENAME_OUT_EXCEPTION ; + + DELETE2_SC_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1]); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h (revision 108) @@ -76,4 +76,7 @@ public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] +#ifdef DEBUG + public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod] +#endif public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS_NEXT ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] @@ -102,4 +105,7 @@ public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_NO_EXECUTE ;//[nb_inst_rename] public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_IS_DELAY_SLOT;//[nb_inst_rename] +#ifdef DEBUG + public : SC_OUT(Taddress_t ) ** out_RENAME_OUT_ADDRESS ;//[nb_inst_rename] +#endif public : SC_OUT(Taddress_t ) ** out_RENAME_OUT_ADDRESS_NEXT ;//[nb_inst_rename] public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_HAS_IMMEDIAT ;//[nb_inst_rename] @@ -117,4 +123,7 @@ public : SC_OUT(Texception_t ) ** out_RENAME_OUT_EXCEPTION_USE;//[nb_inst_rename] public : SC_OUT(Texception_t ) ** out_RENAME_OUT_EXCEPTION ;//[nb_inst_rename] + + // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tevent_state_t ) *** in_RETIRE_EVENT_STATE ;//[nb_front_end][nb_context] // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select.cpp (revision 108) @@ -97,4 +97,7 @@ << (*(in_RENAME_IN_NO_EXECUTE [i][j])) << (*(in_RENAME_IN_IS_DELAY_SLOT [i][j])) +#ifdef DEBUG + << (*(in_RENAME_IN_ADDRESS [i][j])) +#endif << (*(in_RENAME_IN_ADDRESS_NEXT [i][j])) << (*(in_RENAME_IN_HAS_IMMEDIAT [i][j])) @@ -119,4 +122,9 @@ sensitive << (*(in_RENAME_IN_DEPTH [i][j])); } + +// for (uint32_t i=0; i<_param->_nb_front_end; i++) +// for (uint32_t j=0; j<_param->_nb_context [i]; j++) +// sensitive << (*(in_RETIRE_EVENT_STATE [i][j])); + for (uint32_t i=0; i<_param->_nb_inst_rename; i++) sensitive << (*(in_RENAME_OUT_ACK [i])); @@ -163,4 +171,8 @@ (*(out_RENAME_OUT_IS_DELAY_SLOT [x])) (*(in_RENAME_IN_VAL [i][j])); (*(out_RENAME_OUT_IS_DELAY_SLOT [x])) (*(in_RENAME_IN_IS_DELAY_SLOT [i][j])); +#ifdef DEBUG + (*(out_RENAME_OUT_ADDRESS [x])) (*(in_RENAME_IN_VAL [i][j])); + (*(out_RENAME_OUT_ADDRESS [x])) (*(in_RENAME_IN_ADDRESS [i][j])); +#endif (*(out_RENAME_OUT_ADDRESS_NEXT [x])) (*(in_RENAME_IN_VAL [i][j])); (*(out_RENAME_OUT_ADDRESS_NEXT [x])) (*(in_RENAME_IN_ADDRESS_NEXT [i][j])); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp (revision 108) @@ -69,4 +69,7 @@ _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); +#ifdef DEBUG + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); +#endif _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); @@ -99,4 +102,7 @@ ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); +#ifdef DEBUG + ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ); +#endif ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); @@ -114,4 +120,11 @@ ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); + } + + // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp (revision 108) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -40,4 +41,7 @@ delete [] in_RENAME_IN_NO_EXECUTE ; delete [] in_RENAME_IN_IS_DELAY_SLOT ; +#ifdef DEBUG + delete [] in_RENAME_IN_ADDRESS ; +#endif delete [] in_RENAME_IN_ADDRESS_NEXT ; delete [] in_RENAME_IN_HAS_IMMEDIAT ; @@ -66,4 +70,7 @@ delete [] out_RENAME_OUT_TYPE ; delete [] out_RENAME_OUT_OPERATION ; +#ifdef DEBUG + delete [] out_RENAME_OUT_ADDRESS ; +#endif delete [] out_RENAME_OUT_ADDRESS_NEXT ; delete [] out_RENAME_OUT_HAS_IMMEDIAT ; @@ -80,4 +87,6 @@ delete [] out_RENAME_OUT_NUM_REG_RE ; delete [] out_RENAME_OUT_EXCEPTION_USE; + + DELETE2_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp (revision 108) @@ -65,26 +65,54 @@ log_printf(TRACE,Rename_select,FUNCTION," * rename_out_ack : %d",PORT_READ(in_RENAME_OUT_ACK[i])); + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_IN_FRONT_END_ID [x][y]):0; + Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_IN_CONTEXT_ID [x][y]):0; + + Tcontrol_t no_execute = (PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y])); + + Tcontrol_t read_ra = (PORT_READ(in_RENAME_IN_READ_RA [x][y])); + Tcontrol_t read_rb = (PORT_READ(in_RENAME_IN_READ_RB [x][y])); + Tcontrol_t read_rc = (PORT_READ(in_RENAME_IN_READ_RC [x][y])); + Tcontrol_t write_rd = (PORT_READ(in_RENAME_IN_WRITE_RD [x][y])); + Tcontrol_t write_re = (PORT_READ(in_RENAME_IN_WRITE_RE [x][y])); + + // Attention, j'ai enlevé event_state de la liste de sensibilité +// Tevent_state_t event_state = PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]); + +// Tcontrol_t no_execute = (PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y]) or +// // ROB Flush +// ((event_state == EVENT_STATE_EVENT ) or +// (event_state == EVENT_STATE_WAITEND))); + +// Tcontrol_t read_ra = (PORT_READ(in_RENAME_IN_READ_RA [x][y]) and not no_execute); +// Tcontrol_t read_rb = (PORT_READ(in_RENAME_IN_READ_RB [x][y]) and not no_execute); +// Tcontrol_t read_rc = (PORT_READ(in_RENAME_IN_READ_RC [x][y]) and not no_execute); +// Tcontrol_t write_rd = (PORT_READ(in_RENAME_IN_WRITE_RD [x][y]) and not no_execute); +// Tcontrol_t write_re = (PORT_READ(in_RENAME_IN_WRITE_RE [x][y]) and not no_execute); + if (_param->_have_port_front_end_id) - PORT_WRITE(out_RENAME_OUT_FRONT_END_ID [i],PORT_READ(in_RENAME_IN_FRONT_END_ID [x][y])); + PORT_WRITE(out_RENAME_OUT_FRONT_END_ID [i],front_end_id); if (_param->_have_port_context_id) - PORT_WRITE(out_RENAME_OUT_CONTEXT_ID [i],PORT_READ(in_RENAME_IN_CONTEXT_ID [x][y])); + PORT_WRITE(out_RENAME_OUT_CONTEXT_ID [i],context_id); if (_param->_have_port_depth) PORT_WRITE(out_RENAME_OUT_DEPTH [i],PORT_READ(in_RENAME_IN_DEPTH [x][y])); PORT_WRITE(out_RENAME_OUT_TYPE [i],PORT_READ(in_RENAME_IN_TYPE [x][y])); PORT_WRITE(out_RENAME_OUT_OPERATION [i],PORT_READ(in_RENAME_IN_OPERATION [x][y])); - PORT_WRITE(out_RENAME_OUT_NO_EXECUTE [i],PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y])); + PORT_WRITE(out_RENAME_OUT_NO_EXECUTE [i],no_execute); PORT_WRITE(out_RENAME_OUT_IS_DELAY_SLOT[i],PORT_READ(in_RENAME_IN_IS_DELAY_SLOT [x][y])); +#ifdef DEBUG + PORT_WRITE(out_RENAME_OUT_ADDRESS [i],PORT_READ(in_RENAME_IN_ADDRESS [x][y])); +#endif PORT_WRITE(out_RENAME_OUT_ADDRESS_NEXT [i],PORT_READ(in_RENAME_IN_ADDRESS_NEXT [x][y])); PORT_WRITE(out_RENAME_OUT_HAS_IMMEDIAT [i],PORT_READ(in_RENAME_IN_HAS_IMMEDIAT [x][y])); PORT_WRITE(out_RENAME_OUT_IMMEDIAT [i],PORT_READ(in_RENAME_IN_IMMEDIAT [x][y])); - PORT_WRITE(out_RENAME_OUT_READ_RA [i],PORT_READ(in_RENAME_IN_READ_RA [x][y])); + PORT_WRITE(out_RENAME_OUT_READ_RA [i],read_ra); PORT_WRITE(out_RENAME_OUT_NUM_REG_RA [i],PORT_READ(in_RENAME_IN_NUM_REG_RA [x][y])); - PORT_WRITE(out_RENAME_OUT_READ_RB [i],PORT_READ(in_RENAME_IN_READ_RB [x][y])); + PORT_WRITE(out_RENAME_OUT_READ_RB [i],read_rb); PORT_WRITE(out_RENAME_OUT_NUM_REG_RB [i],PORT_READ(in_RENAME_IN_NUM_REG_RB [x][y])); - PORT_WRITE(out_RENAME_OUT_READ_RC [i],PORT_READ(in_RENAME_IN_READ_RC [x][y])); + PORT_WRITE(out_RENAME_OUT_READ_RC [i],read_rc); PORT_WRITE(out_RENAME_OUT_NUM_REG_RC [i],PORT_READ(in_RENAME_IN_NUM_REG_RC [x][y])); - PORT_WRITE(out_RENAME_OUT_WRITE_RD [i],PORT_READ(in_RENAME_IN_WRITE_RD [x][y])); + PORT_WRITE(out_RENAME_OUT_WRITE_RD [i],write_rd); PORT_WRITE(out_RENAME_OUT_NUM_REG_RD [i],PORT_READ(in_RENAME_IN_NUM_REG_RD [x][y])); - PORT_WRITE(out_RENAME_OUT_WRITE_RE [i],PORT_READ(in_RENAME_IN_WRITE_RE [x][y])); + PORT_WRITE(out_RENAME_OUT_WRITE_RE [i],write_re); PORT_WRITE(out_RENAME_OUT_NUM_REG_RE [i],PORT_READ(in_RENAME_IN_NUM_REG_RE [x][y])); PORT_WRITE(out_RENAME_OUT_EXCEPTION_USE[i],PORT_READ(in_RENAME_IN_EXCEPTION_USE [x][y])); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp (revision 108) @@ -57,4 +57,7 @@ ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ," in_RENAME_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ," in_RENAME_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); +#ifdef DEBUG + ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); +#endif ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ," in_RENAME_IN_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ," in_RENAME_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); @@ -81,4 +84,7 @@ ALLOC1_SC_SIGNAL(out_INSERT_NO_EXECUTE ,"out_INSERT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_insert); ALLOC1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT ,"out_INSERT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_insert); +#ifdef DEBUG + ALLOC1_SC_SIGNAL(out_INSERT_ADDRESS ,"out_INSERT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_insert); +#endif ALLOC1_SC_SIGNAL(out_INSERT_ADDRESS_NEXT ,"out_INSERT_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_insert); ALLOC1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT ,"out_INSERT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_insert); @@ -155,4 +161,7 @@ INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); +#ifdef DEBUG + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); +#endif INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); @@ -183,4 +192,7 @@ INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert); INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert); +#ifdef DEBUG + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_ADDRESS ,_param->_nb_inst_insert); +#endif INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_ADDRESS_NEXT ,_param->_nb_inst_insert); INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert); @@ -297,4 +309,7 @@ DELETE2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); DELETE2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); +#ifdef DEBUG + DELETE2_SC_SIGNAL( in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); +#endif DELETE2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); DELETE2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); @@ -322,4 +337,7 @@ DELETE1_SC_SIGNAL(out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert); DELETE1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert); +#ifdef DEBUG + DELETE1_SC_SIGNAL(out_INSERT_ADDRESS ,_param->_nb_inst_insert); +#endif DELETE1_SC_SIGNAL(out_INSERT_ADDRESS_NEXT ,_param->_nb_inst_insert); DELETE1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h (revision 108) @@ -78,4 +78,7 @@ public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] +#ifdef DEBUG + public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod] +#endif public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS_NEXT ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] @@ -104,4 +107,7 @@ public : SC_OUT(Tcontrol_t ) ** out_INSERT_NO_EXECUTE ;//[nb_inst_insert] public : SC_OUT(Tcontrol_t ) ** out_INSERT_IS_DELAY_SLOT ;//[nb_inst_insert] +#ifdef DEBUG + public : SC_OUT(Taddress_t ) ** out_INSERT_ADDRESS ;//[nb_inst_insert] +#endif public : SC_OUT(Taddress_t ) ** out_INSERT_ADDRESS_NEXT ;//[nb_inst_insert] public : SC_OUT(Tcontrol_t ) ** out_INSERT_HAS_IMMEDIAT ;//[nb_inst_insert] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp (revision 108) @@ -69,4 +69,7 @@ _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); +#ifdef DEBUG + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); +#endif _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); @@ -99,4 +102,7 @@ ALLOC1_SIGNAL_OUT(out_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ); +#ifdef DEBUG + ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ); +#endif ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_OUT(out_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); @@ -301,4 +307,8 @@ PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT", dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT"); +#ifdef DEBUG + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); +#endif PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" , dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" ); @@ -349,4 +359,8 @@ PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_DEPTH" , dest,"out_INSERT_" +toString(i)+"_DEPTH" ); +#ifdef DEBUG + PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_ADDRESS" , + dest,"out_INSERT_" +toString(i)+"_ADDRESS" ); +#endif PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_ADDRESS_NEXT", dest,"out_INSERT_" +toString(i)+"_ADDRESS_NEXT"); @@ -412,4 +426,17 @@ dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_EXCEPTION" ); } + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + dest = _name; + +#ifdef POSITION + _component->interface_map (src ,"retire_event_"+toString(i)+"_"+toString(j), + dest,"retire_event_"+toString(i)+"_"+toString(j)); +#endif + PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE", + dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE"); + } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp (revision 108) @@ -37,4 +37,7 @@ DELETE2_SIGNAL( in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); DELETE2_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); +#ifdef DEBUG + DELETE2_SIGNAL( in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_instruction_address ); +#endif DELETE2_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_instruction_address ); DELETE2_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); @@ -62,4 +65,7 @@ DELETE1_SIGNAL(out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert,1 ); DELETE1_SIGNAL(out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert,1 ); +#ifdef DEBUG + DELETE1_SIGNAL(out_INSERT_ADDRESS ,_param->_nb_inst_insert,_param->_size_instruction_address ); +#endif DELETE1_SIGNAL(out_INSERT_ADDRESS_NEXT ,_param->_nb_inst_insert,_param->_size_instruction_address ); DELETE1_SIGNAL(out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert,1 ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg (revision 108) @@ -13,4 +13,5 @@ 1 1 +1 # nb_inst_branch_complete 1 1 +1 # nb_branch_speculated [0][0] [nb_front_end][nb_context] +1 1 +1 # size_nb_inst_decod 1 1 +1 # nb_rename_unit_select 1 1 +1 # nb_execute_loop_select Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp (revision 108) @@ -8,5 +8,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/include/test.h" -#define NB_PARAMS 22 +#define NB_PARAMS 23 void usage (int argc, char * argv[]) @@ -27,4 +27,5 @@ err (_(" * nb_inst_branch_complete (uint32_t )\n")); err (_(" * nb_branch_speculated [nb_front_end][nb_context] (uint32_t )\n")); + err (_(" * size_nb_inst_decod (uint32_t )\n")); err (_(" * nb_rename_unit_select (uint32_t )\n")); err (_(" * nb_execute_loop_select (uint32_t )\n")); @@ -130,4 +131,5 @@ _nb_branch_speculated [i][j] = fromString(argv[x++]); } + uint32_t _size_nb_inst_decod = fromString(argv[x++]); uint32_t _nb_rename_unit_select = fromString(argv[x++]); uint32_t _nb_execute_loop_select = fromString(argv[x++]); @@ -275,4 +277,5 @@ _nb_inst_branch_complete , _nb_branch_speculated , + _size_nb_inst_decod , _nb_rename_unit_select , _nb_execute_loop_select , Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp (revision 108) @@ -57,4 +57,7 @@ ALLOC2_SC_SIGNAL( in_RENAME_NO_EXECUTE ," in_RENAME_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); ALLOC2_SC_SIGNAL( in_RENAME_IS_DELAY_SLOT ," in_RENAME_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); +#ifdef DEBUG + ALLOC2_SC_SIGNAL( in_RENAME_ADDRESS ," in_RENAME_ADDRESS ",Taddress_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); +#endif ALLOC2_SC_SIGNAL( in_RENAME_ADDRESS_NEXT ," in_RENAME_ADDRESS_NEXT ",Taddress_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); ALLOC2_SC_SIGNAL( in_RENAME_HAS_IMMEDIAT ," in_RENAME_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); @@ -165,4 +168,5 @@ ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_ALL ,"out_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_MEM ,"out_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); ALLOC2_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); @@ -194,4 +198,7 @@ INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); +#ifdef DEBUG + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_ADDRESS ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); +#endif INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); @@ -315,4 +322,5 @@ INSTANCE2_SC_SIGNAL(_OOO_Engine,out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); INSTANCE2_SC_SIGNAL(_OOO_Engine,out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_NB_INST_DECOD_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); if (_param->_have_port_depth) @@ -378,4 +386,7 @@ DELETE2_SC_SIGNAL( in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); DELETE2_SC_SIGNAL( in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); +#ifdef DEBUG + DELETE2_SC_SIGNAL( in_RENAME_ADDRESS ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); +#endif DELETE2_SC_SIGNAL( in_RENAME_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); DELETE2_SC_SIGNAL( in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); @@ -484,4 +495,5 @@ DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); DELETE2_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1]); DELETE2_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h (revision 108) @@ -77,4 +77,7 @@ public : SC_IN (Tcontrol_t ) *** in_RENAME_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tcontrol_t ) *** in_RENAME_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] +#ifdef DEBUG + public : SC_IN (Taddress_t ) *** in_RENAME_ADDRESS ;//[nb_front_end][nb_inst_decod] +#endif public : SC_IN (Taddress_t ) *** in_RENAME_ADDRESS_NEXT ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tcontrol_t ) *** in_RENAME_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] @@ -194,4 +197,5 @@ public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context] public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] + public : SC_IN (Tcounter_t ) *** in_NB_INST_DECOD_ALL ;//[nb_front_end][nb_context] // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h (revision 108) @@ -134,4 +134,5 @@ uint32_t nb_inst_branch_complete , uint32_t ** nb_branch_speculated ,//[nb_front_end][nb_context] + uint32_t size_nb_inst_decod , uint32_t nb_rename_unit_select , uint32_t nb_execute_loop_select , Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 108) @@ -66,4 +66,7 @@ _ALLOC2_SIGNAL_IN ( in_RENAME_NO_EXECUTE ,"NO_EXECUTE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); +#ifdef DEBUG + _ALLOC2_SIGNAL_IN ( in_RENAME_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); +#endif _ALLOC2_SIGNAL_IN ( in_RENAME_ADDRESS_NEXT ,"ADDRESS_NEXT" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); @@ -158,5 +161,5 @@ // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("branch_complete",OUT,WEST,_("Instruction to execute_loop"),_param->_nb_inst_issue); + ALLOC1_INTERFACE("branch_complete",OUT,WEST,_("Instruction to execute_loop"),_param->_nb_inst_branch_complete); ALLOC1_VALACK_OUT (out_BRANCH_COMPLETE_VAL , VAL); @@ -219,4 +222,5 @@ _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_ALL ,"COMMIT_ALL" ,Tcounter_t ,_param->_size_nb_inst_commit ,_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_MEM ,"COMMIT_MEM" ,Tcounter_t ,_param->_size_nb_inst_commit ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_NB_INST_DECOD_ALL ,"DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod ,_param->_nb_front_end,_param->_nb_context[it1]); } @@ -413,4 +417,8 @@ PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_IS_DELAY_SLOT", dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_IS_DELAY_SLOT"); +#ifdef DEBUG + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_ADDRESS" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_ADDRESS" ); +#endif PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_ADDRESS_NEXT" , dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_ADDRESS_NEXT" ); @@ -477,4 +485,8 @@ COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_IS_DELAY_SLOT" , dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT" ); +#ifdef DEBUG + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_ADDRESS" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); +#endif COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_ADDRESS_NEXT" , dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" ); @@ -755,4 +767,5 @@ // in_INSERT_DEPTH - component_rename_unit + // in_INSERT_ADDRESS - component_rename_unit // in_INSERT_ADDRESS_NEXT - component_rename_unit // in_INSERT_EXCEPTION_USE - component_rename_unit @@ -991,4 +1004,6 @@ PORT_MAP(_component,src ,"out_NB_INST_"+toString(i)+"_"+toString(j)+"_COMMIT_MEM", dest,"out_NB_INST_"+toString(i)+"_"+toString(j)+"_COMMIT_MEM"); + PORT_MAP(_component,src , "in_NB_INST_"+toString(i)+"_"+toString(j)+"_DECOD_ALL" , + dest, "in_NB_INST_"+toString(i)+"_"+toString(j)+"_DECOD_ALL" ); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp (revision 108) @@ -36,4 +36,7 @@ DELETE2_SIGNAL( in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); DELETE2_SIGNAL( in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); +#ifdef DEBUG + DELETE2_SIGNAL( in_RENAME_ADDRESS ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); +#endif DELETE2_SIGNAL( in_RENAME_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); DELETE2_SIGNAL( in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); @@ -142,4 +145,5 @@ DELETE2_SIGNAL(out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_nb_inst_commit ); DELETE2_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_nb_inst_commit ); + DELETE2_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_nb_inst_decod ); DELETE2_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth ); DELETE2_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp (revision 108) @@ -31,4 +31,5 @@ uint32_t nb_inst_branch_complete , uint32_t ** nb_branch_speculated ,//[nb_front_end][nb_context] + uint32_t size_nb_inst_decod , uint32_t nb_rename_unit_select , uint32_t nb_execute_loop_select , @@ -242,4 +243,5 @@ _nb_inst_branch_complete , _nb_branch_speculated , + size_nb_inst_decod , size_general_data , size_store_queue_ptr , @@ -336,4 +338,5 @@ _size_rob_ptr = size_packet_id; _size_nb_inst_commit = log2(size_re_order_buffer)+1; + _size_nb_inst_decod = size_nb_inst_decod; _have_port_front_end_id = _size_front_end_id > 0; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp (revision 108) @@ -286,4 +286,5 @@ // out_DECOD_NO_EXECUTE - ooo_engine. in_RENAME_NO_EXECUTE // out_DECOD_IS_DELAY_SLOT - ooo_engine. in_RENAME_IS_DELAY_SLOT + // out_DECOD_ADDRESS - ooo_engine. in_RENAME_ADDRESS // out_DECOD_ADDRESS_NEXT - ooo_engine. in_RENAME_ADDRESS_NEXT // out_DECOD_HAS_IMMEDIAT - ooo_engine. in_RENAME_HAS_IMMEDIAT @@ -457,4 +458,8 @@ COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_IS_DELAY_SLOT", dest,"out_DECOD_" +toString(k)+"_IS_DELAY_SLOT"); +#ifdef DEBUG + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_ADDRESS" , + dest,"out_DECOD_" +toString(k)+"_ADDRESS" ); +#endif COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_ADDRESS_NEXT" , dest,"out_DECOD_" +toString(k)+"_ADDRESS_NEXT" ); @@ -635,4 +640,6 @@ COMPONENT_MAP(_component,src ,"out_NB_INST_"+toString(j)+"_"+toString(k)+"_COMMIT_MEM", dest, "in_NB_INST_" +toString(k)+"_COMMIT_MEM"); + COMPONENT_MAP(_component,src , "in_NB_INST_"+toString(j)+"_"+toString(k)+"_DECOD_ALL" , + dest,"out_NB_INST_" +toString(k)+"_DECOD_ALL" ); } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp (revision 108) @@ -848,16 +848,21 @@ for (uint32_t j=0; j<_nb_inst_issue[i]; ++j) for (uint32_t k=0; k<_nb_read_bloc; ++k) - // have route between this slot's ooo_engine and an read_bloc - if (_table_dispatch [i][j][k]) - { - uint32_t num_execute_loop = _link_read_unit_with_read_bloc [k].first; - - list_execute_loop[i].push_back(num_execute_loop); - } - - sort (list_execute_loop[i].begin(), - list_execute_loop[i].end()); - unique(list_execute_loop[i].begin(), - list_execute_loop[i].end()); + { + // have route between this slot's ooo_engine and an read_bloc + if (_table_dispatch [i][j][k]) + { + uint32_t num_execute_loop = _link_read_unit_with_read_bloc [k].first; + + list_execute_loop[i].push_back(num_execute_loop); + } + } + + { + sort (list_execute_loop[i].begin(), + list_execute_loop[i].end()); + std::vector::iterator it=std::unique(list_execute_loop[i].begin(), + list_execute_loop[i].end()); + list_execute_loop[i].erase(it,list_execute_loop[i].end()); + } _ooo_engine_nb_execute_loop [i] = list_execute_loop[i].size(); @@ -895,10 +900,10 @@ ALLOC2(_ooo_engine_nb_inst_execute ,uint32_t ,_nb_ooo_engine,_ooo_engine_nb_execute_loop[it1]); - + for (uint32_t i=0; i<_nb_ooo_engine; ++i) for (uint32_t j=0; j<_ooo_engine_nb_execute_loop[i]; ++j) { uint32_t num_execute_loop = _translate_ooo_engine_num_execute_loop [i][j]; - + // each write_unit manage one instruction per cycle. _ooo_engine_nb_inst_execute [i][j] = _nb_write_unit [num_execute_loop]; @@ -1052,9 +1057,11 @@ } // sort and erase duplicate value - - sort (list_thread_with_inst_issue [j].begin(), - list_thread_with_inst_issue [j].end()); - unique(list_thread_with_inst_issue [j].begin(), - list_thread_with_inst_issue [j].end()); + { + sort (list_thread_with_inst_issue [j].begin(), + list_thread_with_inst_issue [j].end()); + std::vector::iterator it=unique(list_thread_with_inst_issue [j].begin(), + list_thread_with_inst_issue [j].end()); + list_thread_with_inst_issue [j].erase(it,list_thread_with_inst_issue [j].end()); + } } @@ -1063,12 +1070,18 @@ { // sort and erase duplicate value - sort (_list_load_store_unit_with_rename_unit [i][j].begin(), - _list_load_store_unit_with_rename_unit [i][j].end()); - unique(_list_load_store_unit_with_rename_unit [i][j].begin(), - _list_load_store_unit_with_rename_unit [i][j].end()); - sort (_list_functionnal_unit_with_rename_unit [i][j].begin(), - _list_functionnal_unit_with_rename_unit [i][j].end()); - unique(_list_functionnal_unit_with_rename_unit [i][j].begin(), - _list_functionnal_unit_with_rename_unit [i][j].end()); + { + sort (_list_load_store_unit_with_rename_unit [i][j].begin(), + _list_load_store_unit_with_rename_unit [i][j].end()); + std::vector::iterator it=unique(_list_load_store_unit_with_rename_unit [i][j].begin(), + _list_load_store_unit_with_rename_unit [i][j].end()); + _list_load_store_unit_with_rename_unit [i][j].erase(it,_list_load_store_unit_with_rename_unit [i][j].end()); + } + { + sort (_list_functionnal_unit_with_rename_unit [i][j].begin(), + _list_functionnal_unit_with_rename_unit [i][j].end()); + std::vector::iterator it=unique(_list_functionnal_unit_with_rename_unit [i][j].begin(), + _list_functionnal_unit_with_rename_unit [i][j].end()); + _list_functionnal_unit_with_rename_unit [i][j].erase(it,_list_functionnal_unit_with_rename_unit [i][j].end()); + } uint32_t num_rename_bloc = _link_rename_bloc_with_rename_unit[i][j]; @@ -1227,13 +1240,18 @@ for (uint32_t i=0; i<_nb_execute_loop; ++i) { - sort (_list_ooo_engine_with_execute_loop[i].begin(), - _list_ooo_engine_with_execute_loop[i].end()); - unique(_list_ooo_engine_with_execute_loop[i].begin(), - _list_ooo_engine_with_execute_loop[i].end()); - - sort (_list_front_end_with_execute_loop [i].begin(), - _list_front_end_with_execute_loop [i].end()); - unique(_list_front_end_with_execute_loop [i].begin(), - _list_front_end_with_execute_loop [i].end()); + { + sort (_list_ooo_engine_with_execute_loop[i].begin(), + _list_ooo_engine_with_execute_loop[i].end()); + std::vector::iterator it=unique(_list_ooo_engine_with_execute_loop[i].begin(), + _list_ooo_engine_with_execute_loop[i].end()); + _list_ooo_engine_with_execute_loop[i].erase(it,_list_ooo_engine_with_execute_loop[i].end()); + } + { + sort (_list_front_end_with_execute_loop[i].begin(), + _list_front_end_with_execute_loop[i].end()); + std::vector::iterator it=unique(_list_front_end_with_execute_loop[i].begin(), + _list_front_end_with_execute_loop[i].end()); + _list_front_end_with_execute_loop[i].erase(it,_list_front_end_with_execute_loop[i].end()); + } } @@ -1313,14 +1331,21 @@ ALLOC2(_execute_loop_nb_inst_retire ,uint32_t,_nb_execute_loop,_nb_read_unit[it1]); + log_printf(TRACE,Core,FUNCTION,_(" * execute_loop - Read_unit")); for (uint32_t i=0; i<_nb_execute_loop; ++i) - for (uint32_t j=0; j<_nb_read_unit[i]; ++j) - { - uint32_t num_read_bloc = _link_read_bloc_with_read_unit [i][j]; - - _execute_loop_size_read_queue [i][j] = _size_read_queue [num_read_bloc]; - _execute_loop_size_reservation_station [i][j] = _size_reservation_station [num_read_bloc]; - _execute_loop_nb_inst_retire [i][j] = _nb_inst_retire [num_read_bloc]; - } - + { + log_printf(TRACE,Core,FUNCTION,_(" * [%d] nb_read_unit : %d"),i,_nb_read_unit[i]); + + for (uint32_t j=0; j<_nb_read_unit[i]; ++j) + { + uint32_t num_read_bloc = _link_read_bloc_with_read_unit [i][j]; + + log_printf(TRACE,Core,FUNCTION,_(" * num_read_bloc : %d"),num_read_bloc); + + _execute_loop_size_read_queue [i][j] = _size_read_queue [num_read_bloc]; + _execute_loop_size_reservation_station [i][j] = _size_reservation_station [num_read_bloc]; + _execute_loop_nb_inst_retire [i][j] = _nb_inst_retire_reservation_station [num_read_bloc]; + } + } + ALLOC2(_execute_loop_nb_inst_functionnal_unit ,uint32_t,_nb_execute_loop,_execute_loop_nb_functionnal_unit[it1]); ALLOC4(_execute_loop_timing ,multi_execute_loop::execute_loop::execute_timing_t @@ -1802,4 +1827,5 @@ _nb_inst_branch_complete [i], _ooo_engine_nb_branch_speculated [i], + _size_nb_inst_decod , _nb_rename_unit_select [i], _nb_execute_loop_select [i], Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 108) @@ -10,8 +10,8 @@ #define MORPHEO_MAJOR_VERSION 0 #define MORPHEO_MINOR_VERSION 2 -#define MORPHEO_REVISION "107" +#define MORPHEO_REVISION "108" #define MORPHEO_CODENAME "Castor" -#define MORPHEO_DATE_DAY "11" +#define MORPHEO_DATE_DAY "12" #define MORPHEO_DATE_MONTH "02" #define MORPHEO_DATE_YEAR "2009" Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg (revision 108) @@ -5,6 +5,6 @@ - - + + @@ -16,6 +16,6 @@ - - + + @@ -24,5 +24,5 @@ - + @@ -30,7 +30,7 @@ - - - + + + @@ -41,4 +41,10 @@ + + + + + + @@ -54,9 +60,21 @@ + + + + + + + + + + + + - - - - + + + + @@ -76,9 +94,9 @@ - - + + - + @@ -115,5 +133,5 @@ - + @@ -121,10 +139,10 @@ - - + + - - + + @@ -135,12 +153,12 @@ - - + + - - + + - - + + @@ -171,6 +189,9 @@ + + + @@ -181,10 +202,19 @@ + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 107) +++ trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 108) @@ -3,28 +3,96 @@ - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/Makefile.flags =================================================================== --- trunk/Makefile.flags (revision 107) +++ trunk/Makefile.flags (revision 108) @@ -17,9 +17,9 @@ -DDEBUG=DEBUG_TRACE \ -DSTATISTICS \ - -DVHDL \ - -DVHDL_TESTBENCH \ - -DVHDL_TESTBENCH_ASSERT \ -DTRANSLATION +# -DVHDL \ +# -DVHDL_TESTBENCH \ +# -DVHDL_TESTBENCH_ASSERT \ # -DPRINT_COLOR \ # -DPOSITION \ Index: trunk/Platforms/Test/Makefile =================================================================== --- trunk/Platforms/Test/Makefile (revision 107) +++ trunk/Platforms/Test/Makefile (revision 108) @@ -36,5 +36,6 @@ DIR_BIN = $(DIR_TMP)/bin DIR_LOG = $(DIR_TMP)/log -DIR_DATA = ./data +DIR_DATA_TEST = ./data_test +DIR_DATA_BENCH = ./data_bench DIR_SOFT = $(MORPHEO_TOPLEVEL)/Softwares @@ -57,6 +58,7 @@ OBJECTS = $(patsubst $(DIR_SRC)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SRC)/*.cpp)) -LOGS = $(patsubst $(DIR_DATA)/%.cfg,$(DIR_LOG)/%.log,$(wildcard $(DIR_DATA)/*.cfg)) -DEBUG_CFG = $(DIR_DATA)/debug.cfg +LOGS = $(patsubst $(DIR_DATA_TEST)/%.cfg,$(DIR_LOG)/%.log,$(wildcard $(DIR_DATA_TEST)/*.cfg)) +BENCHS = $(patsubst $(DIR_DATA_BENCH)/%.cfg,$(DIR_LOG)/%.log,$(wildcard $(DIR_DATA_BENCH)/*.cfg)) +DEBUG_CFG = $(DIR_DATA_TEST)/debug.cfg DEBUG_LOG = $(DIR_LOG)/debug.log @@ -93,5 +95,5 @@ vpath %.cpp $(DIR_SRC) vpath %.o $(DIR_OBJ) -vpath %.cfg $(DIR_DATA) +vpath %.cfg $(DIR_DATA_TEST) $(DIR_DATA_BENCH) .PRECIOUS : $(DIR_OBJ)/%.o $(DIR_BIN)/%.x $(DIR_LOG)/%.log @@ -106,5 +108,5 @@ $(CXX) $(PLATFORMS_L_FLAGS) -o $@ $^ $(LIBNAME); -run : $(DIR_LOG) all +test : $(DIR_LOG) all @\ declare logs; \ @@ -132,5 +134,10 @@ fi; -execute : run +bench : $(DIR_LOG) all + @\ + declare logs="$(BENCHS)"; \ + $(MAKE) $$logs; + +execute : bench $(DIR_LOG)/%.log : %.cfg @@ -190,5 +197,5 @@ @\ $(ECHO) "Delete temporary files in directory $(PWD)";\ - $(RM) *~ $(DIR_SRC)/*~ $(DIR_INC)/*~ $(DIR_DATA)/*~ *core* tty* *.vhdl *.log *.stat *.pos\ + $(RM) *~ $(DIR_SRC)/*~ $(DIR_INC)/*~ $(DIR_DATA_TEST)/*~ $(DIR_DATA_BENCH)/*~ *core* tty* *.vhdl *.log *.stat *.pos\ $(DIR_OBJ) $(DIR_BIN) $(DIR_LOG); @@ -206,8 +213,9 @@ $(ECHO) "";\ $(ECHO) " * all (default rules) : create software";\ - $(ECHO) " * run : execute platforms";\ + $(ECHO) " * test : execute platforms with test configuration";\ + $(ECHO) " * bench : execute platforms with bench configuration";\ $(ECHO) " * lib : make library";\ $(ECHO) " * soft : make software";\ - $(ECHO) " * execute : cf 'make run'";\ + $(ECHO) " * execute : cf 'make bench'";\ $(ECHO) " * clean : erase temporary files";\ $(ECHO) " * clean_all : erase generated files";\ Index: trunk/Platforms/Test/data_bench/Bench_000_000.cfg =================================================================== --- trunk/Platforms/Test/data_bench/Bench_000_000.cfg (revision 108) +++ trunk/Platforms/Test/data_bench/Bench_000_000.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_min.cfg +../../Softwares/Test/Test_099/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_bench/Bench_001_000.cfg =================================================================== --- trunk/Platforms/Test/data_bench/Bench_001_000.cfg (revision 108) +++ trunk/Platforms/Test/data_bench/Bench_001_000.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_w1_1.cfg +../../Softwares/Test/Test_099/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_bench/Bench_002_000.cfg =================================================================== --- trunk/Platforms/Test/data_bench/Bench_002_000.cfg (revision 108) +++ trunk/Platforms/Test/data_bench/Bench_002_000.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_w1_2.cfg +../../Softwares/Test/Test_099/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_bench/Bench_003_000.cfg =================================================================== --- trunk/Platforms/Test/data_bench/Bench_003_000.cfg (revision 108) +++ trunk/Platforms/Test/data_bench/Bench_003_000.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_w1_3.cfg +../../Softwares/Test/Test_099/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_bench/Bench_004_000.cfg =================================================================== --- trunk/Platforms/Test/data_bench/Bench_004_000.cfg (revision 108) +++ trunk/Platforms/Test/data_bench/Bench_004_000.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_w1_4.cfg +../../Softwares/Test/Test_099/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_000.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_000.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_000.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_000/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_001.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_001.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_001.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_001/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_002.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_002.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_002.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_002/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_003.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_003.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_003.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_003/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_004.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_004.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_004.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_004/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_005.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_005.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_005.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_005/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_006.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_006.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_006.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_006/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_007.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_007.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_007.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_007/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_008.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_008.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_008.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_008/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_009.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_009.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_009.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_009/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_010.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_010.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_010.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_010/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_011.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_011.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_011.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_011/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_012.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_012.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_012.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_012/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_013.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_013.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_013.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_013/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_014.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_014.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_014.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_014/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_015.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_015.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_015.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_015/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_016.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_016.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_016.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_016/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_017.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_017.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_017.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_017/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_018.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_018.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_018.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_018/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_019.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_019.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_019.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_019/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_020.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_020.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_020.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_020/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_021.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_021.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_021.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_021/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_022.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_022.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_022.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_022/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_023.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_023.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_023.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_023/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_024.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_024.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_024.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_024/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_025.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_025.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_025.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_025/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_026.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_026.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_026.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_026/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_027.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_027.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_027.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_027/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_028.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_028.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_028.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_028/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_029.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_029.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_029.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_029/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_030.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_030.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_030.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_030/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_031.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_031.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_031.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_031/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_032.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_032.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_032.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_032/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_033.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_033.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_033.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_033/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_034.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_034.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_034.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_034/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_035.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_035.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_035.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_035/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_036.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_036.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_036.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_036/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_037.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_037.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_037.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_037/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_038.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_038.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_038.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_038/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_039.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_039.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_039.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_039/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_040.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_040.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_040.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_040/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_041.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_041.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_041.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_041/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_042.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_042.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_042.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_042/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_043.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_043.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_043.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_043/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_044.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_044.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_044.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_044/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_045.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_045.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_045.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_045/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_046.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_046.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_046.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_046/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_047.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_047.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_047.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_047/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_048.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_048.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_048.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_048/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_049.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_049.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_049.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_049/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_050.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_050.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_050.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_050/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_051.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_051.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_051.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_051/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_052.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_052.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_052.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_052/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_053.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_053.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_053.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_053/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_054.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_054.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_054.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_054/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_055.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_055.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_055.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_055/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_056.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_056.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_056.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_056/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_057.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_057.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_057.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_057/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_058.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_058.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_058.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_058/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_059.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_059.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_059.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_059/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_060.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_060.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_060.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_060/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_061.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_061.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_061.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_061/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_062.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_062.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_062.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_062/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_063.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_063.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_063.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_063/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_064.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_064.cfg (revision 108) +++ trunk/Platforms/Test/data_test/Test_000_064.cfg (revision 108) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_064/bin/soft.x +0 +0 +4096 +2 Index: trunk/Softwares/Common/src/c/func_factoriel.c =================================================================== --- trunk/Softwares/Common/src/c/func_factoriel.c (revision 107) +++ trunk/Softwares/Common/src/c/func_factoriel.c (revision 108) @@ -9,6 +9,8 @@ if ( x <= 1) return 1; + + unsigned int res = mul_soft (x , factoriel_recursif (x-1)); - return (mul_soft (x , factoriel_recursif (x-1) ) ); + return res; } @@ -31,4 +33,5 @@ void test_factoriel_iteratif (int x) { + int x_min = 0; int x_max = 12; int wait [x_max+1]; @@ -48,5 +51,5 @@ wait[12] = 479001600; // 1c8cfc00 - for (int i = 0; i <= ((x