Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 108)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 111)
@@ -16,4 +16,16 @@
 namespace context_state {
 
+
+#define get_priority(x) \
+  (((state == CONTEXT_STATE_KO_MISS_LOAD_ADDR                  ) or  \
+    (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR       ) or  \
+    (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND               ) or  \
+    (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND    ) or  \
+    (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE))?3: \
+  (((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR                ) or  \
+    (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND             ) or  \
+    (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE         ))?2: \
+   ((state == EVENT_TYPE_EXCEPTION)?1:                           \
+    0)))
 
 #undef  FUNCTION
@@ -65,4 +77,9 @@
                   break;
                 }
+              case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE :
+                {
+                  // nothing : wait end of update upt
+                  break;
+                }
               case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND :
                 {
@@ -82,5 +99,30 @@
                   break;
                 }
-              case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND :
+              case CONTEXT_STATE_KO_EXCEP_SPR    :
+                {
+                  // nothing, wait the update of internal register (epcr, eear, sr, esr)
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_BRANCH_ADDR    :
+                {
+                  // nothing, wait the update of internal register (pc)
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_LOAD_ADDR    :
+                {
+                  // nothing, wait the update of internal register (pc)
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE :
+                {
+                  // nothing : wait end of update upt
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR    :
+                {
+                  // nothing, wait the update of internal register (pc)
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND :
                 {
                   // Wait end of all instruction
@@ -88,25 +130,5 @@
                     
 //                  state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
-                    state = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR;
-                  break;
-                }
-              case CONTEXT_STATE_KO_EXCEP_SPR    :
-                {
-                  // nothing, wait the update of internal register (epcr, eear, sr, esr)
-                  break;
-                }
-              case CONTEXT_STATE_KO_MISS_BRANCH_ADDR    :
-                {
-                  // nothing, wait the update of internal register (pc)
-                  break;
-                }
-              case CONTEXT_STATE_KO_MISS_LOAD_ADDR    :
-                {
-                  // nothing, wait the update of internal register (pc)
-                  break;
-                }
-              case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR    :
-                {
-                  // nothing, wait the update of internal register (pc)
+                    state = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR;
                   break;
                 }
@@ -203,4 +225,49 @@
 
         // -------------------------------------------------------------------
+        // -----[ EVENT ]-----------------------------------------------------
+        // -------------------------------------------------------------------
+        for (uint32_t i=0; i<_param->_nb_context; i++)
+          if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i]))
+            {
+              log_printf(TRACE,Context_State,FUNCTION,"  * EVENT [%d]",i);
+              // Write pc
+              context_state_t state = reg_STATE [i];
+
+              switch (state)
+                {
+                case CONTEXT_STATE_KO_EXCEP_ADDR :
+                  {
+                    reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR;
+                    break;
+                  }
+                case CONTEXT_STATE_KO_MISS_BRANCH_ADDR:
+
+//                   {
+//                     reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
+//                     break;
+//                   }
+                case CONTEXT_STATE_KO_MISS_LOAD_ADDR  :
+                case CONTEXT_STATE_KO_PSYNC_ADDR :
+                case CONTEXT_STATE_KO_CSYNC_ADDR :
+                  {
+                    reg_STATE [i] = CONTEXT_STATE_OK;
+                    break;
+                  }
+                case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR:
+                  {
+                    reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
+                    break;
+                  }
+                default :
+                  {
+#ifdef DEBUG_TEST
+                    throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
+#endif
+                    break;
+                  }
+                }
+            }
+
+        // -------------------------------------------------------------------
         // -----[ BRANCH_EVENT ]----------------------------------------------
         // -------------------------------------------------------------------
@@ -222,11 +289,6 @@
 //               Tdepth_t   depth1     = (depth    >=depth_min)?(depth    ):((depth    +depth_max));
 
-              // priority : miss > excep > spr/sync
-              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR            ) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR              ) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR   ) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND         ) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND           ) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
+              // priority : miss_load > miss_branch > excep > spr/sync
+              uint8_t    priority0  = get_priority(state);
               uint8_t    priority1  = 2; // miss
 
@@ -235,6 +297,14 @@
               //   if context_state_ko : test the depth, and the priority of event
               bool       is_valid   = ((state == CONTEXT_STATE_OK) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or
                                        (depth1< depth0) or
                                        ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth
+
+#ifdef DEBUG_TEST
+              if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and
+                  (depth0 != depth1))
+                throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str()));
+#endif
 
               log_printf(TRACE,Context_State,FUNCTION,"    * depth     : %d",depth     );
@@ -250,14 +320,73 @@
               if (is_valid)
                 {
-                  Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
 //                reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
-                  reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; //@@@ TODO : make MISS fast (miss decod)
-                  reg_EVENT_ADDRESS          [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC  [i])+1; // address delay slot
-                  reg_EVENT_ADDRESS_EPCR     [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]);   // address_next
-                  reg_EVENT_ADDRESS_EPCR_VAL [i] =  dest_val;
-                //reg_EVENT_ADDRESS_EEAR     [i] =  0; 
-                  reg_EVENT_ADDRESS_EEAR_VAL [i] =  0;
-                  reg_EVENT_IS_DELAY_SLOT    [i] =  1;
-                  reg_EVENT_IS_DS_TAKE       [i] =  dest_val;
+
+                  if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE)
+                    {
+                      reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND;
+                    }
+                  else
+                    {
+                      reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; //@@@ TODO : make MISS fast (miss decod)
+
+                      Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
+                      reg_EVENT_ADDRESS          [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC  [i])+1; // address delay slot
+                      reg_EVENT_ADDRESS_EPCR     [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]);   // address_next
+                      reg_EVENT_ADDRESS_EPCR_VAL [i] =  dest_val;
+                    //reg_EVENT_ADDRESS_EEAR     [i] =  0; 
+                      reg_EVENT_ADDRESS_EEAR_VAL [i] =  0;
+                      reg_EVENT_IS_DELAY_SLOT    [i] =  1;
+                      reg_EVENT_IS_DS_TAKE       [i] =  dest_val;
+                      reg_EVENT_DEPTH            [i] =  depth;
+                    }
+                }
+            }
+
+        // -------------------------------------------------------------------
+        // -----[ BRANCH_COMPLETE ]----------------------------------------------
+        // -------------------------------------------------------------------
+        for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
+          if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i] 
+              and PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))
+            {
+              log_printf(TRACE,Context_State,FUNCTION,"  * BRANCH_COMPLETE [%d]",i);
+
+              context_state_t state = reg_STATE [i];
+
+              Tdepth_t   depth      = (_param->_have_port_depth)?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
+              Tdepth_t   depth_cur  = reg_EVENT_DEPTH [i];
+              Tdepth_t   depth_min  = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0;
+              Tdepth_t   depth_max  = _param->_nb_inst_branch_speculated [i];
+              
+              Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
+              Tdepth_t   depth1     = (depth    >=depth_min)?(depth    -depth_min):((depth    +depth_max-depth_min));
+//               Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
+//               Tdepth_t   depth1     = (depth    >=depth_min)?(depth    ):((depth    +depth_max));
+
+              // priority : miss_load > miss_branch > excep > spr/sync
+              uint8_t    priority0  = get_priority(state);
+              uint8_t    priority1  = 2; // miss
+
+              // is_valid = can modify local information
+              //   if context_state_ok : yes
+              //   if context_state_ko : test the depth, and the priority of event
+              bool       is_valid   = ((state == CONTEXT_STATE_OK) or
+                                       (depth1< depth0) or
+                                       ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth
+
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth     : %d",depth     );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth_cur : %d",depth_cur );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth_min : %d",depth_min );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth_max : %d",depth_max );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth0    : %d",depth0    );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth1    : %d",depth1    );
+              log_printf(TRACE,Context_State,FUNCTION,"    * priority0 : %d",priority0 );
+              log_printf(TRACE,Context_State,FUNCTION,"    * priority1 : %d",priority1 );
+              log_printf(TRACE,Context_State,FUNCTION,"  * is_valid    : %d",is_valid  );
+
+              if (is_valid)
+                {
+//                reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
+                  reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE;
                   reg_EVENT_DEPTH            [i] =  depth;
                 }
@@ -287,11 +416,6 @@
               Tevent_type_t   type  = PORT_READ(in_DECOD_EVENT_TYPE [i]);
               
-              // miss > excep > spr/sync
-              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR            ) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR              ) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR   ) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND         ) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND           ) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+              // miss_load > miss_branch > excep > spr/sync
+              uint8_t    priority0  = get_priority(state);
               uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?1:0;
 
@@ -410,41 +534,45 @@
             Tcontext_t context    = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0;
             Tdepth_t   depth      = (_param->_have_port_depth     )?PORT_READ(in_COMMIT_EVENT_DEPTH      ):0;
-            Tdepth_t   depth_cur  = reg_EVENT_DEPTH [context];
-            Tdepth_t   depth_min = (_param->_have_port_depth     )?PORT_READ(in_DEPTH_MIN [context]):0;
-            Tdepth_t   depth_max  = _param->_nb_inst_branch_speculated [context];
+//             Tdepth_t   depth_cur  = reg_EVENT_DEPTH [context];
+//             Tdepth_t   depth_min = (_param->_have_port_depth     )?PORT_READ(in_DEPTH_MIN [context]):0;
+//             Tdepth_t   depth_max  = _param->_nb_inst_branch_speculated [context];
             
-            Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
-            Tdepth_t   depth1     = (depth    >=depth_min)?(depth    -depth_min):((depth    +depth_max-depth_min));
-//             Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
-//             Tdepth_t   depth1     = (depth    >=depth_min)?(depth    ):((depth    +depth_max));
+//             Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
+//             Tdepth_t   depth1     = (depth    >=depth_min)?(depth    -depth_min):((depth    +depth_max-depth_min));
+// //             Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
+// //             Tdepth_t   depth1     = (depth    >=depth_min)?(depth    ):((depth    +depth_max));
 
             context_state_t state = reg_STATE [context];
             Tevent_type_t   type  = PORT_READ(in_COMMIT_EVENT_TYPE );
             
-            // miss > excep > spr/sync
-              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR            ) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR              ) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR   ) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND         ) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND           ) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
-            uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION)
-
-            // is_valid = can modify local information
-            //  if context_state_ok : yes
-            //  if context_state_ko : test the depth, and the priority of envent
-
-            bool       is_valid   = ((state == CONTEXT_STATE_OK) or
-                                     (depth1< depth0) or
-                                     ((depth1==depth0) and (priority1>=priority0)));
+//             // miss > excep > spr/sync
+//               uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR            ) or
+//                                        (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR              ) or
+//                                        (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR   ) or
+//                                        (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND         ) or
+//                                        (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE     ) or
+//                                        (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND           ) or
+//                                        (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+//             uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION)
+
+//             // is_valid = can modify local information
+//             //  if context_state_ok : yes
+//             //  if context_state_ko : test the depth, and the priority of envent
+
+//             bool       is_valid   = ((state == CONTEXT_STATE_OK) or
+//                                      (depth1< depth0) or
+//                                      ((depth1==depth0) and (priority1>=priority0)));
+
+            // if commit send an event, also they have not yet event previous this instruction
+            bool       is_valid   = true;
 
             log_printf(TRACE,Context_State,FUNCTION,"    * depth     : %d",depth     );
-            log_printf(TRACE,Context_State,FUNCTION,"    * depth_cur : %d",depth_cur );
-            log_printf(TRACE,Context_State,FUNCTION,"    * depth_min : %d",depth_min );
-            log_printf(TRACE,Context_State,FUNCTION,"    * depth_max : %d",depth_max );
-            log_printf(TRACE,Context_State,FUNCTION,"    * depth0    : %d",depth0    );
-            log_printf(TRACE,Context_State,FUNCTION,"    * depth1    : %d",depth1    );
-            log_printf(TRACE,Context_State,FUNCTION,"    * priority0 : %d",priority0 );
-            log_printf(TRACE,Context_State,FUNCTION,"    * priority1 : %d",priority1 );
+//             log_printf(TRACE,Context_State,FUNCTION,"    * depth_cur : %d",depth_cur );
+//             log_printf(TRACE,Context_State,FUNCTION,"    * depth_min : %d",depth_min );
+//             log_printf(TRACE,Context_State,FUNCTION,"    * depth_max : %d",depth_max );
+//             log_printf(TRACE,Context_State,FUNCTION,"    * depth0    : %d",depth0    );
+//             log_printf(TRACE,Context_State,FUNCTION,"    * depth1    : %d",depth1    );
+//             log_printf(TRACE,Context_State,FUNCTION,"    * priority0 : %d",priority0 );
+//             log_printf(TRACE,Context_State,FUNCTION,"    * priority1 : %d",priority1 );
             log_printf(TRACE,Context_State,FUNCTION,"  * is_valid    : %d",is_valid  );
 
@@ -460,11 +588,25 @@
                     {
                       // Test if previous branch occure
-                      if ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR            ) or
-                          (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND         ) or
-                          (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR   ) or
-                          (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))
-                        state_next = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND;
-                      else
-                        state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND;
+                      switch (state)
+                        {
+                        case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE      :
+                          {
+                            state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE;
+                            break;
+                          }
+                        case CONTEXT_STATE_KO_MISS_BRANCH_ADDR             :
+                        case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND          :
+                        case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR    :
+                        case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND :
+                          {
+                            state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND;
+                            break;
+                          }
+                        default :
+                          {
+                            state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND;
+                            break;
+                          }
+                        }
                       break;
                     }
@@ -494,49 +636,4 @@
 
         // -------------------------------------------------------------------
-        // -----[ EVENT ]-----------------------------------------------------
-        // -------------------------------------------------------------------
-        for (uint32_t i=0; i<_param->_nb_context; i++)
-          if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i]))
-            {
-              log_printf(TRACE,Context_State,FUNCTION,"  * EVENT [%d]",i);
-              // Write pc
-              context_state_t state = reg_STATE [i];
-
-              switch (state)
-                {
-                case CONTEXT_STATE_KO_EXCEP_ADDR :
-                  {
-                    reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR;
-                    break;
-                  }
-                case CONTEXT_STATE_KO_MISS_BRANCH_ADDR:
-
-//                   {
-//                     reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
-//                     break;
-//                   }
-                case CONTEXT_STATE_KO_MISS_LOAD_ADDR  :
-                case CONTEXT_STATE_KO_PSYNC_ADDR :
-                case CONTEXT_STATE_KO_CSYNC_ADDR :
-                  {
-                    reg_STATE [i] = CONTEXT_STATE_OK;
-                    break;
-                  }
-                case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR:
-                  {
-                    reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
-                    break;
-                  }
-                default :
-                  {
-#ifdef DEBUG_TEST
-                    throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
-#endif
-                    break;
-                  }
-                }
-            }
-
-        // -------------------------------------------------------------------
         // -----[ SPR_EVENT ]-------------------------------------------------
         // -------------------------------------------------------------------
