Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp	(revision 111)
@@ -53,4 +53,6 @@
 	if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL)
 	  {
+	    log_printf(TRACE,Address_management,FUNCTION,"  * PREDICT");
+
             bool branch_is_current = reg_PC_NEXT_IS_DS_TAKE;
             if (branch_is_current)
@@ -90,4 +92,5 @@
 	if (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK))
           {
+
             reg_PC_ACCESS_VAL = 0;
 #ifdef STATISTICS
@@ -102,9 +105,14 @@
 #endif
           }
+
+	// =========================================
+	// ===== Shift Register ====================
+	// =========================================
         
         // Shift register
-
-        if (not reg_PC_ACCESS_VAL and reg_PC_CURRENT_VAL and reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL)
-          {
+        if (reg_PC_NEXT_NEXT_VAL and reg_PC_NEXT_VAL and reg_PC_CURRENT_VAL and not reg_PC_ACCESS_VAL)
+          {
+	    log_printf(TRACE,Address_management,FUNCTION,"  * New PC_ACCESS");
+
             reg_PC_ACCESS_VAL  = 1; // new request
             reg_PC_CURRENT_VAL = 0; // invalid current
@@ -120,40 +128,38 @@
           }
         
-        if (not reg_PC_CURRENT_VAL)
-          {
-            bool val = reg_PC_NEXT_VAL;
-            reg_PC_CURRENT_VAL = val; // new PC_CURRENT if PC_NEXT is valid
-            reg_PC_NEXT_VAL    = 0;   // invalid next
-
-            if (val)
-              {
-                reg_PC_CURRENT                             = reg_PC_NEXT                            ;
-                reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
-                reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
-                reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
-                reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
-                
-                for (uint32_t i=0; i<_param->_nb_instruction; i++)
-                  reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
-              }
-          }
-
-        if (not reg_PC_NEXT_VAL)
-          {
-            bool val = reg_PC_NEXT_NEXT_VAL;
-            reg_PC_NEXT_VAL      = val; // new PC_NEXT if PC_NEXT_NEXT is valid
-            reg_PC_NEXT_NEXT_VAL = 0;   // invalid next_next
-            
-            if (val)
-              {
-                reg_PC_NEXT                             = reg_PC_NEXT_NEXT                            ;
-                reg_PC_NEXT_IS_DS_TAKE                  = reg_PC_NEXT_NEXT_IS_DS_TAKE                 ;
-//              reg_PC_NEXT_INST_IFETCH_PTR             = reg_PC_NEXT_NEXT_INST_IFETCH_PTR            ;
-//              reg_PC_NEXT_BRANCH_STATE                = reg_PC_NEXT_NEXT_BRANCH_STATE               ;
-//              reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID;
-             
-//              for (uint32_t i=0; i<_param->_nb_instruction; i++)
-//                reg_PC_NEXT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE [i];
-              }
+//      if (not reg_PC_CURRENT_VAL and reg_PC_NEXT_VAL)
+        if (reg_PC_NEXT_NEXT_VAL and reg_PC_NEXT_VAL and not reg_PC_CURRENT_VAL)
+          {
+	    log_printf(TRACE,Address_management,FUNCTION,"  * New PC_CURRENT");
+
+            reg_PC_CURRENT_VAL = 1; // new PC_CURRENT if PC_NEXT is valid
+            reg_PC_NEXT_VAL    = 0; // invalid next
+
+            reg_PC_CURRENT                             = reg_PC_NEXT                            ;
+            reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
+            reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
+            reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
+            reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
+            
+            for (uint32_t i=0; i<_param->_nb_instruction; i++)
+              reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
+          }
+
+//      if (not reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL)
+        if (reg_PC_NEXT_NEXT_VAL and not reg_PC_NEXT_VAL)
+          {
+	    log_printf(TRACE,Address_management,FUNCTION,"  * New PC_NEXT");
+
+            reg_PC_NEXT_VAL      = 1; // new PC_NEXT if PC_NEXT_NEXT is valid
+            reg_PC_NEXT_NEXT_VAL = 0; // invalid next_next
+            
+            reg_PC_NEXT                             = reg_PC_NEXT_NEXT                            ;
+            reg_PC_NEXT_IS_DS_TAKE                  = reg_PC_NEXT_NEXT_IS_DS_TAKE                 ;
+//          reg_PC_NEXT_INST_IFETCH_PTR             = reg_PC_NEXT_NEXT_INST_IFETCH_PTR            ;
+//          reg_PC_NEXT_BRANCH_STATE                = reg_PC_NEXT_NEXT_BRANCH_STATE               ;
+//          reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID;
+            
+//          for (uint32_t i=0; i<_param->_nb_instruction; i++)
+//            reg_PC_NEXT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE [i];
           }
 
@@ -161,4 +167,7 @@
 	// ===== EVENT =============================
 	// =========================================
+
+        // Event is after shift register : because, it's to write in pc_next and in not pc_current
+
 	if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK)
 	  {
