Changeset 111 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include

Timestamp:

Feb 27, 2009, 7:37:40 PM (15 years ago)

Author:

rosiere

Message:

1) Decod_queue : multi implementation (one_fifo, multi_fifo)
2) Issue_queue : multi implementation (in_order, out_of_order)
3) Direction : Add Meta predictor
4) Context_State : re add Branch_complete, More priority to Load miss (is not speculative)
5) Return_Address_Stack : update reg_PREDICT pointer on decod miss prediction
6) UPT : Fix bug in multi event
7) Prediction_glue : in read_stack case, insert in UPT pc_next
8) Rename select : when rob have an event (need flush), read_r{a,b,c} and write_r{d,e} is set at 0

Location:

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include

Files:

• Parameters.h (modified) (2 diffs)
• Prediction_unit.h (modified) (1 diff)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Parameters.h

@@ -52 +52 @@
   public : uint32_t *   _upt_size_queue                ;//[nb_context]
   public : uint32_t *   _ufpt_size_queue               ;//[nb_context]
+  public : uint32_t     _nb_thread                          ;
+  public : uint32_t *   _translate_num_context_to_num_thread;//[nb_context]                    
+
+
 
 //public : uint32_t     _size_context_id               ;
@@ -98 +102 @@
                         uint32_t *   upt_size_queue                ,//[nb_context]
                         uint32_t *   ufpt_size_queue               ,//[nb_context]
+                        uint32_t     nb_thread                           ,
+                        uint32_t *   translate_num_context_to_num_thread ,//[nb_context]                    
                         bool         is_toplevel=false
                         );

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h

@@ -101 +101 @@
   public    : SC_IN (Tcontrol_t         )  **  in_BRANCH_COMPLETE_NO_SEQUENCE         ; //[nb_inst_branch_complete]
   public    : SC_OUT(Tcontrol_t         )  ** out_BRANCH_COMPLETE_MISS_PREDICTION     ; //[nb_inst_branch_complete]
-  public    : SC_OUT(Tcontrol_t         )  ** out_BRANCH_COMPLETE_TAKE                ; //[nb_inst_branch_complete]
-  public    : SC_OUT(Taddress_t         )  ** out_BRANCH_COMPLETE_ADDRESS_SRC         ; //[nb_inst_branch_complete]
-  public    : SC_OUT(Taddress_t         )  ** out_BRANCH_COMPLETE_ADDRESS_DEST        ; //[nb_inst_branch_complete]
+//   public    : SC_OUT(Tcontrol_t         )  ** out_BRANCH_COMPLETE_TAKE                ; //[nb_inst_branch_complete]
+//   public    : SC_OUT(Taddress_t         )  ** out_BRANCH_COMPLETE_ADDRESS_SRC         ; //[nb_inst_branch_complete]
+//   public    : SC_OUT(Taddress_t         )  ** out_BRANCH_COMPLETE_ADDRESS_DEST        ; //[nb_inst_branch_complete]
 
     // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~