Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_allocation.cpp	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_allocation.cpp	(revision 112)
@@ -56,5 +56,5 @@
     // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("icache_req",WEST,OUT,_("Request to instruction cache"),_param->_nb_icache_port);
+      ALLOC1_INTERFACE_BEGIN("icache_req",WEST,OUT,_("Request to instruction cache"),_param->_nb_icache_port);
       
       ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL         ,VAL);
@@ -64,9 +64,11 @@
       ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS     ,"address"  ,Ticache_address_t    ,_param->_size_address         );
       ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE        ,"type"     ,Ticache_type_t       ,_param->_size_icache_type     );
+
+      ALLOC1_INTERFACE_END(_param->_nb_icache_port);
     }
 
     // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~  
     {
-      ALLOC1_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port);
+      ALLOC1_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port);
 
       ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL         ,VAL);
@@ -75,15 +77,18 @@
       ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID   ,"packet_id"  ,Tpacket_t            ,_param->_size_icache_packet_id);
       ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR       ,"error"      ,Ticache_error_t      ,_param->_size_icache_error    );
+
+      ALLOC1_INTERFACE_END(_param->_nb_icache_port);
     }
     {
-      // NOTE : max_nb_instruction is too wide ...
-      ALLOC2_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port,_param->_icache_nb_instruction[it1]);
+      ALLOC2_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port,_param->_icache_nb_instruction[it1]);
 
       _ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_param->_size_instruction,_param->_nb_icache_port,_param->_icache_nb_instruction[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_icache_port,_param->_icache_nb_instruction[it1]);
     }
 
     // ~~~~~[ Interface "context_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC2_INTERFACE("context_req",EAST,IN ,_("Request from context_unit."),_param->_nb_front_end, _param->_nb_context[it1]);
+      ALLOC2_INTERFACE_BEGIN("context_req",EAST,IN ,_("Request from context_unit."),_param->_nb_front_end, _param->_nb_context[it1]);
 
       _ALLOC2_VALACK_IN ( in_CONTEXT_REQ_VAL        ,VAL,_param->_nb_front_end, _param->_nb_context[it1]);
@@ -93,9 +98,11 @@
       _ALLOC2_SIGNAL_IN ( in_CONTEXT_REQ_ADDRESS    ,"address"    ,Ticache_address_t    ,_param->_size_address            ,_param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_IN ( in_CONTEXT_REQ_TYPE       ,"type"       ,Ticache_type_t       ,_param->_size_icache_type        ,_param->_nb_front_end, _param->_nb_context[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
     }
 
     // ~~~~~[ Interface "context_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC2_INTERFACE("context_rsp",EAST,OUT,_("Respons to context_unit."),_param->_nb_front_end, _param->_nb_context[it1]);
+      ALLOC2_INTERFACE_BEGIN("context_rsp",EAST,OUT,_("Respons to context_unit."),_param->_nb_front_end, _param->_nb_context[it1]);
 
       _ALLOC2_VALACK_OUT(out_CONTEXT_RSP_VAL        ,VAL,_param->_nb_front_end, _param->_nb_context[it1]);
@@ -104,9 +111,13 @@
       _ALLOC2_SIGNAL_OUT(out_CONTEXT_RSP_PACKET_ID  ,"packet_id"  ,Tpacket_t            ,_param->_size_packet_id[it1][it2],_param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_OUT(out_CONTEXT_RSP_ERROR      ,"error"      ,Ticache_error_t      ,_param->_size_icache_error       ,_param->_nb_front_end, _param->_nb_context[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
     }
     {
-      ALLOC3_INTERFACE("context_rsp",EAST,OUT,_("Respons to context_unit."),_param->_nb_front_end, _param->_nb_context[it1],_param->_nb_instruction[it1][it2]);
+      ALLOC3_INTERFACE_BEGIN("context_rsp",EAST,OUT,_("Respons to context_unit."),_param->_nb_front_end, _param->_nb_context[it1],_param->_nb_instruction[it1][it2]);
 
       _ALLOC3_SIGNAL_OUT(out_CONTEXT_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction,_param->_nb_front_end, _param->_nb_context[it1],_param->_nb_instruction[it1][it2]);
+
+      ALLOC3_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1],_param->_nb_instruction[it1][it2]);
     }
 
@@ -115,6 +126,6 @@
         // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 #ifdef STATISTICS
-        _internal_ICACHE_REQ_NB_ACCESS         = new uint32_t [_param->_nb_icache_port];
-        _internal_ICACHE_REQ_NB_ACCESS_CONFLIT = new uint32_t [_param->_nb_icache_port];
+        ALLOC1(_internal_ICACHE_REQ_NB_ACCESS        ,uint32_t,_param->_nb_icache_port);
+        ALLOC1(_internal_ICACHE_REQ_NB_ACCESS_CONFLIT,uint32_t,_param->_nb_icache_port);
 #endif
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_deallocation.cpp	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_deallocation.cpp	(revision 112)
@@ -56,6 +56,6 @@
         // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 #ifdef STATISTICS
-        delete [] _internal_ICACHE_REQ_NB_ACCESS        ;
-        delete [] _internal_ICACHE_REQ_NB_ACCESS_CONFLIT;
+        DELETE1(_internal_ICACHE_REQ_NB_ACCESS        ,_param->_nb_icache_port);
+        DELETE1(_internal_ICACHE_REQ_NB_ACCESS_CONFLIT,_param->_nb_icache_port);
 #endif
       }
