Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp	(revision 110)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp	(revision 112)
@@ -48,5 +48,5 @@
 							 ,IN
 							 ,SOUTH,
-							 "Generalist interface"
+							 _("Generalist interface")
 #endif
 							 );
@@ -58,60 +58,73 @@
     // ~~~~~[ Interface : "address" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("address", IN, NORTH, "Transaction with PC management.");
+      ALLOC0_INTERFACE_BEGIN("address", IN, NORTH, "Transaction with PC management.");
 
-      ALLOC_VALACK_IN ( in_ADDRESS_VAL                        ,VAL);
-      ALLOC_VALACK_OUT(out_ADDRESS_ACK                        ,ACK);
-      ALLOC_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t ,_param->_size_instruction_address        );
-      ALLOC_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr);
-      ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state   );
-      ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_depth          );
-      ALLOC_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID            ,"ifetch_queue_id"            ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr);
+      ALLOC0_VALACK_IN ( in_ADDRESS_VAL                        ,VAL);
+      ALLOC0_VALACK_OUT(out_ADDRESS_ACK                        ,ACK);
+      ALLOC0_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t ,_param->_size_instruction_address        );
+      ALLOC0_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr);
+      ALLOC0_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state   );
+      ALLOC0_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_depth          );
+      ALLOC0_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID            ,"ifetch_queue_id"            ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr);
 
+      ALLOC0_INTERFACE_END();
     }
     {
-      ALLOC1_INTERFACE("address", IN, NORTH, "Transaction with PC management.",_param->_nb_instruction);
+      ALLOC1_INTERFACE_BEGIN("address", IN, NORTH, _("Transaction with PC management."),_param->_nb_instruction);
 
       ALLOC1_SIGNAL_IN( in_ADDRESS_INSTRUCTION_ENABLE         ,"instruction_enable"         ,Tcontrol_t         ,1);
+
+      ALLOC1_INTERFACE_END(_param->_nb_instruction);
     }
 
     // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage.",_param->_nb_instruction);
+      ALLOC1_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage."),_param->_nb_instruction);
       
       ALLOC1_VALACK_OUT(out_DECOD_VAL        ,VAL);
       ALLOC1_VALACK_IN ( in_DECOD_ACK        ,ACK);
       ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION,"instruction",Tinstruction_t,_param->_size_instruction);
+
+      ALLOC1_INTERFACE_END(_param->_nb_instruction);
     }
     {
-      ALLOC_INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage.");
+      ALLOC0_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage."));
       
-      ALLOC_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address         );
-      ALLOC_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr );
-      ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state    );
-      ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth           );
-      ALLOC_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
+      ALLOC0_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address         );
+      ALLOC0_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr );
+      ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state    );
+      ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth           );
+      ALLOC0_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
+
+      ALLOC0_INTERFACE_END();
     }
 
     // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("icache_rsp", IN, WEST, "Respons from Instruction Cache.");
+      ALLOC0_INTERFACE_BEGIN("icache_rsp", IN, WEST, _("Respons from Instruction Cache."));
       
-      ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL      ,VAL);
-      ALLOC_VALACK_OUT(out_ICACHE_RSP_ACK      ,ACK);
-      ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t      ,_param->_size_ifetch_queue_ptr);
-      ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR    ,"error"    ,Ticache_error_t,_param->_size_icache_error);
+      ALLOC0_VALACK_IN ( in_ICACHE_RSP_VAL      ,VAL);
+      ALLOC0_VALACK_OUT(out_ICACHE_RSP_ACK      ,ACK);
+      ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t      ,_param->_size_ifetch_queue_ptr);
+      ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_ERROR    ,"error"    ,Ticache_error_t,_param->_size_icache_error);
+
+      ALLOC0_INTERFACE_END();
     }
     {
-      ALLOC1_INTERFACE("icache_rsp", IN, WEST, "Respons from Instruction Cache.",_param->_nb_instruction);
+      ALLOC1_INTERFACE_BEGIN("icache_rsp", IN, WEST, _("Respons from Instruction Cache."),_param->_nb_instruction);
       
       ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction);
+
+      ALLOC1_INTERFACE_END(_param->_nb_instruction);
     }
 
     // ~~~~~[ Interface "event_reset" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("event_reset", IN, NORTH, "An event occure and reset queue.");
+      ALLOC0_INTERFACE_BEGIN("event_reset", IN, NORTH, _("An event occure and reset queue."));
 
-      ALLOC_VALACK_IN ( in_EVENT_RESET_VAL,VAL);
-      ALLOC_VALACK_OUT(out_EVENT_RESET_ACK,ACK);
+      ALLOC0_VALACK_IN ( in_EVENT_RESET_VAL,VAL);
+      ALLOC0_VALACK_OUT(out_EVENT_RESET_ACK,ACK);
+
+      ALLOC0_INTERFACE_END();
     }
 
@@ -119,5 +132,5 @@
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
-        internal_DECOD_VAL = new Tcontrol_t [_param->_nb_instruction];
+        ALLOC1(internal_DECOD_VAL,Tcontrol_t,_param->_nb_instruction);
         
         _queue = new ifetch_queue_entry_t * [_param->_size_queue];
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp	(revision 110)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp	(revision 112)
@@ -7,4 +7,5 @@
 
 #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h"
+#include "Behavioural/include/Allocation.h"
 
 namespace morpheo                    {
@@ -28,33 +29,30 @@
 	delete    in_NRESET;
 
-	delete     in_ADDRESS_VAL                        ;
-	delete    out_ADDRESS_ACK                        ;
-	if (_param->_have_port_ifetch_queue_ptr)
-	delete    out_ADDRESS_IFETCH_QUEUE_ID            ;
-	delete []  in_ADDRESS_INSTRUCTION_ENABLE         ;
-	delete     in_ADDRESS_INSTRUCTION_ADDRESS        ;
-	if (_param->_have_port_inst_ifetch_ptr)
-	delete     in_ADDRESS_INST_IFETCH_PTR            ;
-	delete     in_ADDRESS_BRANCH_STATE               ;
-	if (_param->_have_port_depth)
-	delete     in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
-	delete [] out_DECOD_VAL                          ;
-	delete []  in_DECOD_ACK                          ;
-	delete [] out_DECOD_INSTRUCTION                  ;
-	delete    out_DECOD_ADDRESS                      ;
-	if (_param->_have_port_inst_ifetch_ptr)
-	delete    out_DECOD_INST_IFETCH_PTR              ;
-	delete    out_DECOD_BRANCH_STATE                 ;
-	if (_param->_have_port_depth)
-	delete    out_DECOD_BRANCH_UPDATE_PREDICTION_ID  ;
-	delete    out_DECOD_EXCEPTION                    ;
-	delete     in_ICACHE_RSP_VAL                     ;
-	delete    out_ICACHE_RSP_ACK                     ;
-	if (_param->_have_port_ifetch_queue_ptr)
-	delete     in_ICACHE_RSP_PACKET_ID               ;
-	delete []  in_ICACHE_RSP_INSTRUCTION             ;
-	delete     in_ICACHE_RSP_ERROR                   ;
-	delete     in_EVENT_RESET_VAL                    ;
-	delete    out_EVENT_RESET_ACK                    ;
+        DELETE0_SIGNAL( in_ADDRESS_VAL                        ,1);
+        DELETE0_SIGNAL(out_ADDRESS_ACK                        ,1);
+        DELETE0_SIGNAL( in_ADDRESS_INSTRUCTION_ADDRESS        ,_param->_size_instruction_address);
+        DELETE0_SIGNAL( in_ADDRESS_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr);
+        DELETE0_SIGNAL( in_ADDRESS_BRANCH_STATE               ,_param->_size_branch_state   );
+        DELETE0_SIGNAL( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth          );
+        DELETE0_SIGNAL(out_ADDRESS_IFETCH_QUEUE_ID            ,_param->_size_ifetch_queue_ptr);
+        DELETE1_SIGNAL( in_ADDRESS_INSTRUCTION_ENABLE         ,1,_param->_nb_instruction);
+      
+        DELETE1_SIGNAL(out_DECOD_VAL                        ,1,_param->_nb_instruction);
+        DELETE1_SIGNAL( in_DECOD_ACK                        ,1,_param->_nb_instruction);
+        DELETE1_SIGNAL(out_DECOD_INSTRUCTION                ,_param->_size_instruction,_param->_nb_instruction);
+        DELETE0_SIGNAL(out_DECOD_ADDRESS                    ,_param->_size_instruction_address);
+        DELETE0_SIGNAL(out_DECOD_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr );
+        DELETE0_SIGNAL(out_DECOD_BRANCH_STATE               ,_param->_size_branch_state    );
+        DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth           );
+        DELETE0_SIGNAL(out_DECOD_EXCEPTION                  ,_param->_size_exception_ifetch);
+
+        DELETE0_SIGNAL( in_ICACHE_RSP_VAL        ,1);
+        DELETE0_SIGNAL(out_ICACHE_RSP_ACK        ,1);
+        DELETE0_SIGNAL( in_ICACHE_RSP_PACKET_ID  ,_param->_size_ifetch_queue_ptr);
+        DELETE0_SIGNAL( in_ICACHE_RSP_ERROR      ,_param->_size_icache_error);
+        DELETE1_SIGNAL( in_ICACHE_RSP_INSTRUCTION,_param->_size_instruction,_param->_nb_instruction);
+
+        DELETE0_SIGNAL( in_EVENT_RESET_VAL,1);
+        DELETE0_SIGNAL(out_EVENT_RESET_ACK,1);
       }
 
@@ -62,5 +60,8 @@
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
-        delete    internal_DECOD_VAL;
+        DELETE1(internal_DECOD_VAL,_param->_nb_instruction);
+       
+        for (uint32_t i=0;i<_param->_size_queue; i++)
+          delete _queue[i];
         delete [] _queue;
       }
