Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp	(revision 112)
@@ -51,29 +51,29 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
-  ALLOC_SC_SIGNAL (out_ADDRESS_VAL                        ,"out_ADDRESS_VAL                        ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL ( in_ADDRESS_ACK                        ," in_ADDRESS_ACK                        ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS        ,"out_ADDRESS_INSTRUCTION_ADDRESS        ",Tgeneral_address_t);
+  ALLOC0_SC_SIGNAL (out_ADDRESS_VAL                        ,"out_ADDRESS_VAL                        ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL ( in_ADDRESS_ACK                        ," in_ADDRESS_ACK                        ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS        ,"out_ADDRESS_INSTRUCTION_ADDRESS        ",Tgeneral_address_t);
   ALLOC1_SC_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE         ,"out_ADDRESS_INSTRUCTION_ENABLE         ",Tcontrol_t        ,_param->_nb_instruction);
-  ALLOC_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR            ,"out_ADDRESS_INST_IFETCH_PTR            ",Tinst_ifetch_ptr_t);
-  ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_STATE               ,"out_ADDRESS_BRANCH_STATE               ",Tbranch_state_t   );
-  ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
-  ALLOC_SC_SIGNAL (out_PREDICT_VAL                        ,"out_PREDICT_VAL                        ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL ( in_PREDICT_ACK                        ," in_PREDICT_ACK                        ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS                ,"out_PREDICT_PC_PREVIOUS                ",Tgeneral_address_t);
-  ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT                 ,"out_PREDICT_PC_CURRENT                 ",Tgeneral_address_t);
-  ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE      ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT                    ," in_PREDICT_PC_NEXT                    ",Tgeneral_address_t);
-  ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE         ," in_PREDICT_PC_NEXT_IS_DS_TAKE         ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR            ,"out_ADDRESS_INST_IFETCH_PTR            ",Tinst_ifetch_ptr_t);
+  ALLOC0_SC_SIGNAL (out_ADDRESS_BRANCH_STATE               ,"out_ADDRESS_BRANCH_STATE               ",Tbranch_state_t   );
+  ALLOC0_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
+  ALLOC0_SC_SIGNAL (out_PREDICT_VAL                        ,"out_PREDICT_VAL                        ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL ( in_PREDICT_ACK                        ," in_PREDICT_ACK                        ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL (out_PREDICT_PC_PREVIOUS                ,"out_PREDICT_PC_PREVIOUS                ",Tgeneral_address_t);
+  ALLOC0_SC_SIGNAL (out_PREDICT_PC_CURRENT                 ,"out_PREDICT_PC_CURRENT                 ",Tgeneral_address_t);
+  ALLOC0_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE      ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL ( in_PREDICT_PC_NEXT                    ," in_PREDICT_PC_NEXT                    ",Tgeneral_address_t);
+  ALLOC0_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE         ," in_PREDICT_PC_NEXT_IS_DS_TAKE         ",Tcontrol_t        );
   ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE         ," in_PREDICT_INSTRUCTION_ENABLE         ",Tcontrol_t        ,_param->_nb_instruction);
-  ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR            ," in_PREDICT_INST_IFETCH_PTR            ",Tinst_ifetch_ptr_t);
-//ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_IS_CURRENT          ," in_PREDICT_BRANCH_IS_CURRENT          ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE               ," in_PREDICT_BRANCH_STATE               ",Tbranch_state_t   );
-  ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
-  ALLOC_SC_SIGNAL ( in_EVENT_VAL                          ," in_EVENT_VAL                          ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL (out_EVENT_ACK                          ,"out_EVENT_ACK                          ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS                      ," in_EVENT_ADDRESS                      ",Tgeneral_address_t);
-  ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT                 ," in_EVENT_ADDRESS_NEXT                 ",Tgeneral_address_t);
-  ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL             ," in_EVENT_ADDRESS_NEXT_VAL             ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL ( in_EVENT_IS_DS_TAKE                   ," in_EVENT_IS_DS_TAKE                   ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR            ," in_PREDICT_INST_IFETCH_PTR            ",Tinst_ifetch_ptr_t);
+//ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_IS_CURRENT          ," in_PREDICT_BRANCH_IS_CURRENT          ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_STATE               ," in_PREDICT_BRANCH_STATE               ",Tbranch_state_t   );
+  ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
+  ALLOC0_SC_SIGNAL ( in_EVENT_VAL                          ," in_EVENT_VAL                          ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL (out_EVENT_ACK                          ,"out_EVENT_ACK                          ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS                      ," in_EVENT_ADDRESS                      ",Tgeneral_address_t);
+  ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT                 ," in_EVENT_ADDRESS_NEXT                 ",Tgeneral_address_t);
+  ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL             ," in_EVENT_ADDRESS_NEXT_VAL             ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL ( in_EVENT_IS_DS_TAKE                   ," in_EVENT_IS_DS_TAKE                   ",Tcontrol_t        );
   
   /********************************************************
@@ -86,33 +86,33 @@
   (*(_Address_management->in_NRESET))       (*(in_NRESET));
 
-  INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_VAL                        );
-  INSTANCE_SC_SIGNAL (_Address_management, in_ADDRESS_ACK                        );
-  INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS        );
+  INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_VAL                        );
+  INSTANCE0_SC_SIGNAL (_Address_management, in_ADDRESS_ACK                        );
+  INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS        );
   INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE         ,_param->_nb_instruction);
   if (_param->_have_port_inst_ifetch_ptr)
-  INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR            );
-  INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE               );
+  INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR            );
+  INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE               );
   if (_param->_have_port_depth)
-  INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
-  INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_VAL                        );
-  INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_ACK                        );
-  INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS                );
-  INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT                 );
-  INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE      );
-  INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT                    );
-  INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE         );
+  INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
+  INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_VAL                        );
+  INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_ACK                        );
+  INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS                );
+  INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT                 );
+  INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE      );
+  INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT                    );
+  INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE         );
   INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE         ,_param->_nb_instruction);
   if (_param->_have_port_inst_ifetch_ptr)
-  INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR            );
-//INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_IS_CURRENT          );
-  INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE               );
+  INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR            );
+//INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_IS_CURRENT          );
+  INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE               );
   if (_param->_have_port_depth)
-  INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
-  INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_VAL                          );
-  INSTANCE_SC_SIGNAL (_Address_management,out_EVENT_ACK                          );
-  INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS                      );
-  INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT                 );
-  INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT_VAL             );
-  INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_IS_DS_TAKE                   );
+  INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
+  INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_VAL                          );
+  INSTANCE0_SC_SIGNAL (_Address_management,out_EVENT_ACK                          );
+  INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS                      );
+  INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT                 );
+  INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT_VAL             );
+  INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_IS_DS_TAKE                   );
 
   msg(_("<%s> : Start Simulation ............\n"),name.c_str());
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp	(revision 112)
@@ -16,6 +16,4 @@
 namespace ifetch_unit {
 namespace address_management {
-
-
 
 #undef  FUNCTION
@@ -58,52 +56,62 @@
     // ~~~~~[ Interface : "address" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("address", OUT, SOUTH, "Access at request icache.");
+      ALLOC0_INTERFACE_BEGIN("address", OUT, SOUTH, _("Access at request icache."));
 
-      ALLOC_VALACK_OUT (out_ADDRESS_VAL                        ,VAL);
-      ALLOC_VALACK_IN  ( in_ADDRESS_ACK                        ,ACK);
-      ALLOC_SIGNAL_OUT (out_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t,_param->_size_instruction_address     );
-      ALLOC_SIGNAL_OUT (out_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr         );
-      ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state            );
-      ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
+      ALLOC0_VALACK_OUT (out_ADDRESS_VAL                        ,VAL);
+      ALLOC0_VALACK_IN  ( in_ADDRESS_ACK                        ,ACK);
+      ALLOC0_SIGNAL_OUT (out_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t,_param->_size_instruction_address     );
+      ALLOC0_SIGNAL_OUT (out_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr         );
+      ALLOC0_SIGNAL_OUT (out_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state            );
+      ALLOC0_SIGNAL_OUT (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
+
+      ALLOC0_INTERFACE_END();
     }
 
     {
-      ALLOC1_INTERFACE("address", OUT, SOUTH, "Access at request icache.",_param->_nb_instruction);
+      ALLOC1_INTERFACE_BEGIN("address", OUT, SOUTH, _("Access at request icache."),_param->_nb_instruction);
 
       ALLOC1_SIGNAL_OUT(out_ADDRESS_INSTRUCTION_ENABLE         ,"instruction_enable"         ,Tcontrol_t        ,1);
+
+      ALLOC1_INTERFACE_END(_param->_nb_instruction);
     }
 
     // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("predict", IN, NORTH, "Request the prediction unit.");
+      ALLOC0_INTERFACE_BEGIN("predict", IN, NORTH, _("Request the prediction unit."));
 
-      ALLOC_VALACK_OUT (out_PREDICT_VAL                        ,VAL);
-      ALLOC_VALACK_IN  ( in_PREDICT_ACK                        ,ACK);
-      ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS                ,"pc_previous"                ,Tgeneral_address_t,_param->_size_instruction_address);
-      ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT                 ,"pc_current"                 ,Tgeneral_address_t,_param->_size_instruction_address);
-      ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,"pc_current_is_ds_take"      ,Tcontrol_t        ,1);
-      ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT                    ,"pc_next"                    ,Tgeneral_address_t,_param->_size_instruction_address);
-      ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT_IS_DS_TAKE         ,"pc_next_is_ds_take"         ,Tcontrol_t        ,1);
-//    ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_IS_CURRENT          ,"branch_is_current"          ,Tcontrol_t        ,1);
-      ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
-      ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
-      ALLOC_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
+      ALLOC0_VALACK_OUT (out_PREDICT_VAL                        ,VAL);
+      ALLOC0_VALACK_IN  ( in_PREDICT_ACK                        ,ACK);
+      ALLOC0_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS                ,"pc_previous"                ,Tgeneral_address_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT                 ,"pc_current"                 ,Tgeneral_address_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,"pc_current_is_ds_take"      ,Tcontrol_t        ,1);
+      ALLOC0_SIGNAL_IN  ( in_PREDICT_PC_NEXT                    ,"pc_next"                    ,Tgeneral_address_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_IN  ( in_PREDICT_PC_NEXT_IS_DS_TAKE         ,"pc_next_is_ds_take"         ,Tcontrol_t        ,1);
+//    ALLOC0_SIGNAL_IN  ( in_PREDICT_BRANCH_IS_CURRENT          ,"branch_is_current"          ,Tcontrol_t        ,1);
+      ALLOC0_SIGNAL_IN  ( in_PREDICT_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
+      ALLOC0_SIGNAL_IN  ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
+      ALLOC0_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
+
+      ALLOC0_INTERFACE_END();
     }
     {
-      ALLOC1_INTERFACE("predict", IN, NORTH, "Request the prediction unit.",_param->_nb_instruction);
+      ALLOC1_INTERFACE_BEGIN("predict", IN, NORTH, _("Request the prediction unit."),_param->_nb_instruction);
 
       ALLOC1_SIGNAL_IN (in_PREDICT_INSTRUCTION_ENABLE          ,"instruction_enable"         ,Tcontrol_t        ,1);
+
+      ALLOC1_INTERFACE_END(_param->_nb_instruction);
     }
 
     // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("event", IN, SOUTH, "Event (miss, exception ...)");
+      ALLOC0_INTERFACE_BEGIN("event", IN, SOUTH, _("Event (miss, exception ...)"));
 
-      ALLOC_VALACK_IN ( in_EVENT_VAL          ,VAL);
-      ALLOC_VALACK_OUT(out_EVENT_ACK          ,ACK);
-      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS         ,"address"         ,Tgeneral_address_t,_param->_size_instruction_address);
-      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT    ,"address_next"    ,Tgeneral_address_t,_param->_size_instruction_address);
-      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"address_next_val",Tcontrol_t,1);
-      ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE      ,"is_ds_take"      ,Tcontrol_t,1);
+      ALLOC0_VALACK_IN ( in_EVENT_VAL          ,VAL);
+      ALLOC0_VALACK_OUT(out_EVENT_ACK          ,ACK);
+      ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS         ,"address"         ,Tgeneral_address_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT    ,"address_next"    ,Tgeneral_address_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"address_next_val",Tcontrol_t,1);
+      ALLOC0_SIGNAL_IN ( in_EVENT_IS_DS_TAKE      ,"is_ds_take"      ,Tcontrol_t,1);
+
+      ALLOC0_INTERFACE_END();
     }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp	(revision 112)
@@ -7,4 +7,5 @@
 
 #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h"
+#include "Behavioural/include/Allocation.h"
 
 namespace morpheo                    {
@@ -27,44 +28,37 @@
 	delete    in_CLOCK ;
 	delete    in_NRESET;
-
-	delete    out_ADDRESS_VAL                        ;
-	delete     in_ADDRESS_ACK                        ;
-	delete    out_ADDRESS_INSTRUCTION_ADDRESS        ;
-	delete [] out_ADDRESS_INSTRUCTION_ENABLE         ;
-	if (_param->_have_port_inst_ifetch_ptr)
-	delete    out_ADDRESS_INST_IFETCH_PTR            ;
-	delete    out_ADDRESS_BRANCH_STATE               ;
-	if (_param->_have_port_depth)
-	delete    out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
-	delete    out_PREDICT_VAL                        ;
-	delete     in_PREDICT_ACK                        ;
-	delete    out_PREDICT_PC_PREVIOUS                ;
-	delete    out_PREDICT_PC_CURRENT                 ;
-	delete    out_PREDICT_PC_CURRENT_IS_DS_TAKE      ;
-	delete     in_PREDICT_PC_NEXT                    ;
-	delete     in_PREDICT_PC_NEXT_IS_DS_TAKE         ;
-	delete []  in_PREDICT_INSTRUCTION_ENABLE         ;
-	if (_param->_have_port_inst_ifetch_ptr)
-	delete     in_PREDICT_INST_IFETCH_PTR            ;
-// 	delete     in_PREDICT_BRANCH_IS_CURRENT          ;
-	delete     in_PREDICT_BRANCH_STATE               ;
-	if (_param->_have_port_depth)
-	delete     in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
-	delete     in_EVENT_VAL                          ;
-	delete    out_EVENT_ACK                          ;
-	delete     in_EVENT_ADDRESS                      ;
-	delete     in_EVENT_ADDRESS_NEXT                 ;
-	delete     in_EVENT_ADDRESS_NEXT_VAL             ;
-	delete     in_EVENT_IS_DS_TAKE                   ;
-      
-        // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-        if (usage_is_set(_usage,USE_SYSTEMC))
-          {
-            delete reg_PC_ACCESS_INSTRUCTION_ENABLE ;
-            delete reg_PC_CURRENT_INSTRUCTION_ENABLE;
-            delete reg_PC_NEXT_INSTRUCTION_ENABLE   ;
-          }
+        
+        DELETE0_SIGNAL(out_ADDRESS_VAL                        ,1);
+        DELETE0_SIGNAL( in_ADDRESS_ACK                        ,1);
+        DELETE0_SIGNAL(out_ADDRESS_INSTRUCTION_ADDRESS        ,_param->_size_instruction_address     );
+        DELETE0_SIGNAL(out_ADDRESS_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr         );
+        DELETE0_SIGNAL(out_ADDRESS_BRANCH_STATE               ,_param->_size_branch_state            );
+        DELETE0_SIGNAL(out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth);
+        DELETE1_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE          ,1,_param->_nb_instruction);
+        
+        DELETE0_SIGNAL(out_PREDICT_VAL                        ,1);
+        DELETE0_SIGNAL( in_PREDICT_ACK                        ,1);
+        DELETE0_SIGNAL(out_PREDICT_PC_PREVIOUS                ,_param->_size_instruction_address);
+        DELETE0_SIGNAL(out_PREDICT_PC_CURRENT                 ,_param->_size_instruction_address);
+        DELETE0_SIGNAL(out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,1);
+        DELETE0_SIGNAL( in_PREDICT_PC_NEXT                    ,_param->_size_instruction_address);
+        DELETE0_SIGNAL( in_PREDICT_PC_NEXT_IS_DS_TAKE         ,1);
+//      DELETE0_SIGNAL( in_PREDICT_BRANCH_IS_CURRENT          ,1);
+        DELETE0_SIGNAL( in_PREDICT_BRANCH_STATE               ,_param->_size_branch_state);
+        DELETE0_SIGNAL( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth);
+        DELETE0_SIGNAL( in_PREDICT_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr);
+        DELETE1_SIGNAL(in_PREDICT_INSTRUCTION_ENABLE           ,1,_param->_nb_instruction);
+        
+        DELETE0_SIGNAL( in_EVENT_VAL             ,1);
+        DELETE0_SIGNAL(out_EVENT_ACK             ,1);
+        DELETE0_SIGNAL( in_EVENT_ADDRESS         ,_param->_size_instruction_address);
+        DELETE0_SIGNAL( in_EVENT_ADDRESS_NEXT    ,_param->_size_instruction_address);
+        DELETE0_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL,1);
+        DELETE0_SIGNAL( in_EVENT_IS_DS_TAKE      ,1);
+        
+        DELETE1(reg_PC_ACCESS_INSTRUCTION_ENABLE ,_param->_nb_instruction);
+        DELETE1(reg_PC_CURRENT_INSTRUCTION_ENABLE,_param->_nb_instruction);
+        DELETE1(reg_PC_NEXT_INSTRUCTION_ENABLE   ,_param->_nb_instruction);
       }
-
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp	(revision 112)
@@ -68,27 +68,27 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
-  ALLOC_SC_SIGNAL ( in_ADDRESS_VAL                        ," in_ADDRESS_VAL                        ",Tcontrol_t           );
-  ALLOC_SC_SIGNAL (out_ADDRESS_ACK                        ,"out_ADDRESS_ACK                        ",Tcontrol_t           );
-  ALLOC_SC_SIGNAL (out_ADDRESS_IFETCH_QUEUE_ID            ,"out_ADDRESS_IFETCH_QUEUE_ID            ",Tifetch_queue_ptr_t  );
+  ALLOC0_SC_SIGNAL( in_ADDRESS_VAL                        ," in_ADDRESS_VAL                        ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL(out_ADDRESS_ACK                        ,"out_ADDRESS_ACK                        ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL(out_ADDRESS_IFETCH_QUEUE_ID            ,"out_ADDRESS_IFETCH_QUEUE_ID            ",Tifetch_queue_ptr_t  );
   ALLOC1_SC_SIGNAL( in_ADDRESS_INSTRUCTION_ENABLE         ," in_ADDRESS_INSTRUCTION_ENABLE         ",Tcontrol_t           ,_param->_nb_instruction);
-  ALLOC_SC_SIGNAL ( in_ADDRESS_INSTRUCTION_ADDRESS        ," in_ADDRESS_INSTRUCTION_ADDRESS        ",Tgeneral_address_t   );
-  ALLOC_SC_SIGNAL ( in_ADDRESS_INST_IFETCH_PTR            ," in_ADDRESS_INST_IFETCH_PTR            ",Tinst_ifetch_ptr_t   );
-  ALLOC_SC_SIGNAL ( in_ADDRESS_BRANCH_STATE               ," in_ADDRESS_BRANCH_STATE               ",Tbranch_state_t      );
-  ALLOC_SC_SIGNAL ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID," in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t    );
+  ALLOC0_SC_SIGNAL( in_ADDRESS_INSTRUCTION_ADDRESS        ," in_ADDRESS_INSTRUCTION_ADDRESS        ",Tgeneral_address_t   );
+  ALLOC0_SC_SIGNAL( in_ADDRESS_INST_IFETCH_PTR            ," in_ADDRESS_INST_IFETCH_PTR            ",Tinst_ifetch_ptr_t   );
+  ALLOC0_SC_SIGNAL( in_ADDRESS_BRANCH_STATE               ," in_ADDRESS_BRANCH_STATE               ",Tbranch_state_t      );
+  ALLOC0_SC_SIGNAL( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID," in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t    );
   ALLOC1_SC_SIGNAL(out_DECOD_VAL                          ,"out_DECOD_VAL                          ",Tcontrol_t           ,_param->_nb_instruction);
   ALLOC1_SC_SIGNAL( in_DECOD_ACK                          ," in_DECOD_ACK                          ",Tcontrol_t           ,_param->_nb_instruction);
   ALLOC1_SC_SIGNAL(out_DECOD_INSTRUCTION                  ,"out_DECOD_INSTRUCTION                  ",Tinstruction_t       ,_param->_nb_instruction);
-  ALLOC_SC_SIGNAL (out_DECOD_ADDRESS                      ,"out_DECOD_ADDRESS                      ",Tgeneral_address_t   );
-  ALLOC_SC_SIGNAL (out_DECOD_INST_IFETCH_PTR              ,"out_DECOD_INST_IFETCH_PTR              ",Tinst_ifetch_ptr_t   );
-  ALLOC_SC_SIGNAL (out_DECOD_BRANCH_STATE                 ,"out_DECOD_BRANCH_STATE                 ",Tbranch_state_t      );
-  ALLOC_SC_SIGNAL (out_DECOD_BRANCH_UPDATE_PREDICTION_ID  ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID  ",Tprediction_ptr_t    );
-  ALLOC_SC_SIGNAL (out_DECOD_EXCEPTION                    ,"out_DECOD_EXCEPTION                    ",Tprediction_ptr_t    );
-  ALLOC_SC_SIGNAL ( in_ICACHE_RSP_VAL                     ," in_ICACHE_RSP_VAL                     ",Tcontrol_t           );
-  ALLOC_SC_SIGNAL (out_ICACHE_RSP_ACK                     ,"out_ICACHE_RSP_ACK                     ",Tcontrol_t           );
-  ALLOC_SC_SIGNAL ( in_ICACHE_RSP_PACKET_ID               ," in_ICACHE_RSP_PACKET_ID               ",Tpacket_t            );
+  ALLOC0_SC_SIGNAL(out_DECOD_ADDRESS                      ,"out_DECOD_ADDRESS                      ",Tgeneral_address_t   );
+  ALLOC0_SC_SIGNAL(out_DECOD_INST_IFETCH_PTR              ,"out_DECOD_INST_IFETCH_PTR              ",Tinst_ifetch_ptr_t   );
+  ALLOC0_SC_SIGNAL(out_DECOD_BRANCH_STATE                 ,"out_DECOD_BRANCH_STATE                 ",Tbranch_state_t      );
+  ALLOC0_SC_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID  ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID  ",Tprediction_ptr_t    );
+  ALLOC0_SC_SIGNAL(out_DECOD_EXCEPTION                    ,"out_DECOD_EXCEPTION                    ",Tprediction_ptr_t    );
+  ALLOC0_SC_SIGNAL( in_ICACHE_RSP_VAL                     ," in_ICACHE_RSP_VAL                     ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL(out_ICACHE_RSP_ACK                     ,"out_ICACHE_RSP_ACK                     ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID               ," in_ICACHE_RSP_PACKET_ID               ",Tpacket_t            );
   ALLOC1_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION             ," in_ICACHE_RSP_INSTRUCTION             ",Ticache_instruction_t,_param->_nb_instruction);
-  ALLOC_SC_SIGNAL ( in_ICACHE_RSP_ERROR                   ," in_ICACHE_RSP_ERROR                   ",Ticache_error_t      );
-  ALLOC_SC_SIGNAL ( in_EVENT_RESET_VAL                    ," in_EVENT_RESET_VAL                    ",Tcontrol_t           );
-  ALLOC_SC_SIGNAL (out_EVENT_RESET_ACK                    ,"out_EVENT_RESET_ACK                    ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL( in_ICACHE_RSP_ERROR                   ," in_ICACHE_RSP_ERROR                   ",Ticache_error_t      );
+  ALLOC0_SC_SIGNAL( in_EVENT_RESET_VAL                    ," in_EVENT_RESET_VAL                    ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL(out_EVENT_RESET_ACK                    ,"out_EVENT_RESET_ACK                    ",Tcontrol_t           );
   
   /********************************************************
@@ -101,33 +101,33 @@
   (*(_Ifetch_queue->in_NRESET))       (*(in_NRESET));
 
-  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_VAL                        );
-  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_ACK                        );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_VAL                        );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_ADDRESS_ACK                        );
   if (_param->_have_port_ifetch_queue_ptr)
-  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_IFETCH_QUEUE_ID            );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_ADDRESS_IFETCH_QUEUE_ID            );
   INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ENABLE         ,_param->_nb_instruction);
-  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INSTRUCTION_ADDRESS        );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ADDRESS        );
   if (_param->_have_port_inst_ifetch_ptr)
-  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INST_IFETCH_PTR            );
-  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_STATE               );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INST_IFETCH_PTR            );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_BRANCH_STATE               );
   if (_param->_have_port_depth)
-  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
   INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_VAL                          ,_param->_nb_instruction);
   INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_DECOD_ACK                          ,_param->_nb_instruction);
   INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_INSTRUCTION                  ,_param->_nb_instruction);
-  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_ADDRESS                      );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_ADDRESS                      );
   if (_param->_have_port_inst_ifetch_ptr)
-  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_INST_IFETCH_PTR              );
-  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_STATE                 );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_INST_IFETCH_PTR              );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_BRANCH_STATE                 );
   if (_param->_have_port_depth)
-  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_UPDATE_PREDICTION_ID  );
-  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_EXCEPTION                    );
-  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_VAL                     );
-  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ICACHE_RSP_ACK                     );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_BRANCH_UPDATE_PREDICTION_ID  );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_EXCEPTION                    );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_VAL                     );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_ICACHE_RSP_ACK                     );
   if (_param->_have_port_ifetch_queue_ptr)
-  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_PACKET_ID               );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_PACKET_ID               );
   INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_INSTRUCTION             ,_param->_nb_instruction);
-  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_ERROR                   );
-  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_EVENT_RESET_VAL                    );
-  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_EVENT_RESET_ACK                    );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_ERROR                   );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_EVENT_RESET_VAL                    );
+  INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_EVENT_RESET_ACK                    );
 
   msg(_("<%s> : Start Simulation ............\n"),name.c_str());
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp	(revision 112)
@@ -48,5 +48,5 @@
 							 ,IN
 							 ,SOUTH,
-							 "Generalist interface"
+							 _("Generalist interface")
 #endif
 							 );
@@ -58,60 +58,73 @@
     // ~~~~~[ Interface : "address" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("address", IN, NORTH, "Transaction with PC management.");
+      ALLOC0_INTERFACE_BEGIN("address", IN, NORTH, "Transaction with PC management.");
 
-      ALLOC_VALACK_IN ( in_ADDRESS_VAL                        ,VAL);
-      ALLOC_VALACK_OUT(out_ADDRESS_ACK                        ,ACK);
-      ALLOC_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t ,_param->_size_instruction_address        );
-      ALLOC_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr);
-      ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state   );
-      ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_depth          );
-      ALLOC_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID            ,"ifetch_queue_id"            ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr);
+      ALLOC0_VALACK_IN ( in_ADDRESS_VAL                        ,VAL);
+      ALLOC0_VALACK_OUT(out_ADDRESS_ACK                        ,ACK);
+      ALLOC0_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t ,_param->_size_instruction_address        );
+      ALLOC0_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr);
+      ALLOC0_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state   );
+      ALLOC0_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_depth          );
+      ALLOC0_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID            ,"ifetch_queue_id"            ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr);
 
+      ALLOC0_INTERFACE_END();
     }
     {
-      ALLOC1_INTERFACE("address", IN, NORTH, "Transaction with PC management.",_param->_nb_instruction);
+      ALLOC1_INTERFACE_BEGIN("address", IN, NORTH, _("Transaction with PC management."),_param->_nb_instruction);
 
       ALLOC1_SIGNAL_IN( in_ADDRESS_INSTRUCTION_ENABLE         ,"instruction_enable"         ,Tcontrol_t         ,1);
+
+      ALLOC1_INTERFACE_END(_param->_nb_instruction);
     }
 
     // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage.",_param->_nb_instruction);
+      ALLOC1_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage."),_param->_nb_instruction);
       
       ALLOC1_VALACK_OUT(out_DECOD_VAL        ,VAL);
       ALLOC1_VALACK_IN ( in_DECOD_ACK        ,ACK);
       ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION,"instruction",Tinstruction_t,_param->_size_instruction);
+
+      ALLOC1_INTERFACE_END(_param->_nb_instruction);
     }
     {
-      ALLOC_INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage.");
+      ALLOC0_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage."));
       
-      ALLOC_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address         );
-      ALLOC_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr );
-      ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state    );
-      ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth           );
-      ALLOC_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
+      ALLOC0_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address         );
+      ALLOC0_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr );
+      ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state    );
+      ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth           );
+      ALLOC0_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
+
+      ALLOC0_INTERFACE_END();
     }
 
     // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("icache_rsp", IN, WEST, "Respons from Instruction Cache.");
+      ALLOC0_INTERFACE_BEGIN("icache_rsp", IN, WEST, _("Respons from Instruction Cache."));
       
-      ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL      ,VAL);
-      ALLOC_VALACK_OUT(out_ICACHE_RSP_ACK      ,ACK);
-      ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t      ,_param->_size_ifetch_queue_ptr);
-      ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR    ,"error"    ,Ticache_error_t,_param->_size_icache_error);
+      ALLOC0_VALACK_IN ( in_ICACHE_RSP_VAL      ,VAL);
+      ALLOC0_VALACK_OUT(out_ICACHE_RSP_ACK      ,ACK);
+      ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t      ,_param->_size_ifetch_queue_ptr);
+      ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_ERROR    ,"error"    ,Ticache_error_t,_param->_size_icache_error);
+
+      ALLOC0_INTERFACE_END();
     }
     {
-      ALLOC1_INTERFACE("icache_rsp", IN, WEST, "Respons from Instruction Cache.",_param->_nb_instruction);
+      ALLOC1_INTERFACE_BEGIN("icache_rsp", IN, WEST, _("Respons from Instruction Cache."),_param->_nb_instruction);
       
       ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction);
+
+      ALLOC1_INTERFACE_END(_param->_nb_instruction);
     }
 
     // ~~~~~[ Interface "event_reset" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("event_reset", IN, NORTH, "An event occure and reset queue.");
+      ALLOC0_INTERFACE_BEGIN("event_reset", IN, NORTH, _("An event occure and reset queue."));
 
-      ALLOC_VALACK_IN ( in_EVENT_RESET_VAL,VAL);
-      ALLOC_VALACK_OUT(out_EVENT_RESET_ACK,ACK);
+      ALLOC0_VALACK_IN ( in_EVENT_RESET_VAL,VAL);
+      ALLOC0_VALACK_OUT(out_EVENT_RESET_ACK,ACK);
+
+      ALLOC0_INTERFACE_END();
     }
 
@@ -119,5 +132,5 @@
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
-        internal_DECOD_VAL = new Tcontrol_t [_param->_nb_instruction];
+        ALLOC1(internal_DECOD_VAL,Tcontrol_t,_param->_nb_instruction);
         
         _queue = new ifetch_queue_entry_t * [_param->_size_queue];
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp	(revision 112)
@@ -7,4 +7,5 @@
 
 #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h"
+#include "Behavioural/include/Allocation.h"
 
 namespace morpheo                    {
@@ -28,33 +29,30 @@
 	delete    in_NRESET;
 
-	delete     in_ADDRESS_VAL                        ;
-	delete    out_ADDRESS_ACK                        ;
-	if (_param->_have_port_ifetch_queue_ptr)
-	delete    out_ADDRESS_IFETCH_QUEUE_ID            ;
-	delete []  in_ADDRESS_INSTRUCTION_ENABLE         ;
-	delete     in_ADDRESS_INSTRUCTION_ADDRESS        ;
-	if (_param->_have_port_inst_ifetch_ptr)
-	delete     in_ADDRESS_INST_IFETCH_PTR            ;
-	delete     in_ADDRESS_BRANCH_STATE               ;
-	if (_param->_have_port_depth)
-	delete     in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
-	delete [] out_DECOD_VAL                          ;
-	delete []  in_DECOD_ACK                          ;
-	delete [] out_DECOD_INSTRUCTION                  ;
-	delete    out_DECOD_ADDRESS                      ;
-	if (_param->_have_port_inst_ifetch_ptr)
-	delete    out_DECOD_INST_IFETCH_PTR              ;
-	delete    out_DECOD_BRANCH_STATE                 ;
-	if (_param->_have_port_depth)
-	delete    out_DECOD_BRANCH_UPDATE_PREDICTION_ID  ;
-	delete    out_DECOD_EXCEPTION                    ;
-	delete     in_ICACHE_RSP_VAL                     ;
-	delete    out_ICACHE_RSP_ACK                     ;
-	if (_param->_have_port_ifetch_queue_ptr)
-	delete     in_ICACHE_RSP_PACKET_ID               ;
-	delete []  in_ICACHE_RSP_INSTRUCTION             ;
-	delete     in_ICACHE_RSP_ERROR                   ;
-	delete     in_EVENT_RESET_VAL                    ;
-	delete    out_EVENT_RESET_ACK                    ;
+        DELETE0_SIGNAL( in_ADDRESS_VAL                        ,1);
+        DELETE0_SIGNAL(out_ADDRESS_ACK                        ,1);
+        DELETE0_SIGNAL( in_ADDRESS_INSTRUCTION_ADDRESS        ,_param->_size_instruction_address);
+        DELETE0_SIGNAL( in_ADDRESS_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr);
+        DELETE0_SIGNAL( in_ADDRESS_BRANCH_STATE               ,_param->_size_branch_state   );
+        DELETE0_SIGNAL( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth          );
+        DELETE0_SIGNAL(out_ADDRESS_IFETCH_QUEUE_ID            ,_param->_size_ifetch_queue_ptr);
+        DELETE1_SIGNAL( in_ADDRESS_INSTRUCTION_ENABLE         ,1,_param->_nb_instruction);
+      
+        DELETE1_SIGNAL(out_DECOD_VAL                        ,1,_param->_nb_instruction);
+        DELETE1_SIGNAL( in_DECOD_ACK                        ,1,_param->_nb_instruction);
+        DELETE1_SIGNAL(out_DECOD_INSTRUCTION                ,_param->_size_instruction,_param->_nb_instruction);
+        DELETE0_SIGNAL(out_DECOD_ADDRESS                    ,_param->_size_instruction_address);
+        DELETE0_SIGNAL(out_DECOD_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr );
+        DELETE0_SIGNAL(out_DECOD_BRANCH_STATE               ,_param->_size_branch_state    );
+        DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth           );
+        DELETE0_SIGNAL(out_DECOD_EXCEPTION                  ,_param->_size_exception_ifetch);
+
+        DELETE0_SIGNAL( in_ICACHE_RSP_VAL        ,1);
+        DELETE0_SIGNAL(out_ICACHE_RSP_ACK        ,1);
+        DELETE0_SIGNAL( in_ICACHE_RSP_PACKET_ID  ,_param->_size_ifetch_queue_ptr);
+        DELETE0_SIGNAL( in_ICACHE_RSP_ERROR      ,_param->_size_icache_error);
+        DELETE1_SIGNAL( in_ICACHE_RSP_INSTRUCTION,_param->_size_instruction,_param->_nb_instruction);
+
+        DELETE0_SIGNAL( in_EVENT_RESET_VAL,1);
+        DELETE0_SIGNAL(out_EVENT_RESET_ACK,1);
       }
 
@@ -62,5 +60,8 @@
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
-        delete    internal_DECOD_VAL;
+        DELETE1(internal_DECOD_VAL,_param->_nb_instruction);
+       
+        for (uint32_t i=0;i<_param->_size_queue; i++)
+          delete _queue[i];
         delete [] _queue;
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp	(revision 112)
@@ -50,20 +50,20 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
-  ALLOC_SC_SIGNAL(out_ICACHE_REQ_VAL        ,"out_ICACHE_REQ_VAL        ",Tcontrol_t);
-  ALLOC_SC_SIGNAL( in_ICACHE_REQ_ADDRESS_VAL," in_ICACHE_REQ_ADDRESS_VAL",Tcontrol_t);
-  ALLOC_SC_SIGNAL(out_ICACHE_REQ_QUEUE_VAL  ,"out_ICACHE_REQ_QUEUE_VAL  ",Tcontrol_t);
-  ALLOC_SC_SIGNAL( in_ICACHE_REQ_ACK        ," in_ICACHE_REQ_ACK        ",Tcontrol_t);
-  ALLOC_SC_SIGNAL(out_ICACHE_REQ_ADDRESS_ACK,"out_ICACHE_REQ_ADDRESS_ACK",Tcontrol_t);
-  ALLOC_SC_SIGNAL( in_ICACHE_REQ_QUEUE_ACK  ," in_ICACHE_REQ_QUEUE_ACK  ",Tcontrol_t);
-  ALLOC_SC_SIGNAL(out_ICACHE_REQ_TYPE       ,"out_ICACHE_REQ_TYPE       ",Ticache_type_t);
-  ALLOC_SC_SIGNAL(out_ICACHE_REQ_ADDRESS        ,"out_ICACHE_REQ_ADDRESS        ",Taddress_t);
-  ALLOC_SC_SIGNAL( in_ICACHE_REQ_ADDRESS_ADDRESS," in_ICACHE_REQ_ADDRESS_ADDRESS",Taddress_t);
-  ALLOC_SC_SIGNAL(out_ICACHE_REQ_QUEUE_ADDRESS  ,"out_ICACHE_REQ_QUEUE_ADDRESS  ",Taddress_t);
-  ALLOC_SC_SIGNAL( in_EVENT_VAL             ," in_EVENT_VAL             ",Tcontrol_t);
-  ALLOC_SC_SIGNAL(out_EVENT_ADDRESS_VAL     ,"out_EVENT_ADDRESS_VAL     ",Tcontrol_t);
-  ALLOC_SC_SIGNAL(out_EVENT_QUEUE_VAL       ,"out_EVENT_QUEUE_VAL       ",Tcontrol_t);
-  ALLOC_SC_SIGNAL(out_EVENT_ACK             ,"out_EVENT_ACK             ",Tcontrol_t);
-  ALLOC_SC_SIGNAL( in_EVENT_ADDRESS_ACK     ," in_EVENT_ADDRESS_ACK     ",Tcontrol_t);
-  ALLOC_SC_SIGNAL( in_EVENT_QUEUE_ACK       ," in_EVENT_QUEUE_ACK       ",Tcontrol_t);
+  ALLOC0_SC_SIGNAL(out_ICACHE_REQ_VAL        ,"out_ICACHE_REQ_VAL        ",Tcontrol_t);
+  ALLOC0_SC_SIGNAL( in_ICACHE_REQ_ADDRESS_VAL," in_ICACHE_REQ_ADDRESS_VAL",Tcontrol_t);
+  ALLOC0_SC_SIGNAL(out_ICACHE_REQ_QUEUE_VAL  ,"out_ICACHE_REQ_QUEUE_VAL  ",Tcontrol_t);
+  ALLOC0_SC_SIGNAL( in_ICACHE_REQ_ACK        ," in_ICACHE_REQ_ACK        ",Tcontrol_t);
+  ALLOC0_SC_SIGNAL(out_ICACHE_REQ_ADDRESS_ACK,"out_ICACHE_REQ_ADDRESS_ACK",Tcontrol_t);
+  ALLOC0_SC_SIGNAL( in_ICACHE_REQ_QUEUE_ACK  ," in_ICACHE_REQ_QUEUE_ACK  ",Tcontrol_t);
+  ALLOC0_SC_SIGNAL(out_ICACHE_REQ_TYPE       ,"out_ICACHE_REQ_TYPE       ",Ticache_type_t);
+  ALLOC0_SC_SIGNAL(out_ICACHE_REQ_ADDRESS        ,"out_ICACHE_REQ_ADDRESS        ",Taddress_t);
+  ALLOC0_SC_SIGNAL( in_ICACHE_REQ_ADDRESS_ADDRESS," in_ICACHE_REQ_ADDRESS_ADDRESS",Taddress_t);
+  ALLOC0_SC_SIGNAL(out_ICACHE_REQ_QUEUE_ADDRESS  ,"out_ICACHE_REQ_QUEUE_ADDRESS  ",Taddress_t);
+  ALLOC0_SC_SIGNAL( in_EVENT_VAL             ," in_EVENT_VAL             ",Tcontrol_t);
+  ALLOC0_SC_SIGNAL(out_EVENT_ADDRESS_VAL     ,"out_EVENT_ADDRESS_VAL     ",Tcontrol_t);
+  ALLOC0_SC_SIGNAL(out_EVENT_QUEUE_VAL       ,"out_EVENT_QUEUE_VAL       ",Tcontrol_t);
+  ALLOC0_SC_SIGNAL(out_EVENT_ACK             ,"out_EVENT_ACK             ",Tcontrol_t);
+  ALLOC0_SC_SIGNAL( in_EVENT_ADDRESS_ACK     ," in_EVENT_ADDRESS_ACK     ",Tcontrol_t);
+  ALLOC0_SC_SIGNAL( in_EVENT_QUEUE_ACK       ," in_EVENT_QUEUE_ACK       ",Tcontrol_t);
   
   /********************************************************
@@ -76,20 +76,20 @@
   (*(_Ifetch_unit_Glue->in_NRESET))       (*(in_NRESET));
 
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_VAL        );
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ADDRESS_VAL);
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_QUEUE_VAL  );
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ACK        );
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_ADDRESS_ACK);
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_QUEUE_ACK  );
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_ADDRESS        );
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ADDRESS_ADDRESS);
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_QUEUE_ADDRESS  );
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_TYPE       );
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_VAL             );
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_EVENT_ADDRESS_VAL     );
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_EVENT_QUEUE_VAL       );
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_EVENT_ACK             );
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_ADDRESS_ACK     );
-  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_QUEUE_ACK       );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_VAL        );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ADDRESS_VAL);
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_QUEUE_VAL  );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ACK        );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_ADDRESS_ACK);
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_QUEUE_ACK  );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_ADDRESS        );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ADDRESS_ADDRESS);
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_QUEUE_ADDRESS  );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_TYPE       );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_VAL             );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_EVENT_ADDRESS_VAL     );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_EVENT_QUEUE_VAL       );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_EVENT_ACK             );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_ADDRESS_ACK     );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_QUEUE_ACK       );
 
   msg(_("<%s> : Start Simulation ............\n"),name.c_str());
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp	(revision 112)
@@ -48,5 +48,5 @@
 							 ,IN
 							 ,SOUTH,
-							 "Generalist interface"
+							 _("Generalist interface")
 #endif
 							 );
@@ -58,28 +58,32 @@
     // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("icache_req",OUT, WEST, "Instruction Cache request.");
+      ALLOC0_INTERFACE_BEGIN("icache_req",OUT, WEST, "Instruction Cache request.");
 
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_VAL            ,"val"            ,Tcontrol_t,1);
-      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_VAL    ,"address_val"    ,Tcontrol_t,1);
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_VAL      ,"queue_val"      ,Tcontrol_t,1);
-      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ACK            ,"ack"            ,Tcontrol_t,1);
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS_ACK    ,"address_ack"    ,Tcontrol_t,1);
-      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_QUEUE_ACK      ,"queue_ack"      ,Tcontrol_t,1);
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE           ,"type"           ,Ticache_type_t,_param->_size_icache_type);
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS        ,"address"        ,Taddress_t,_param->_size_instruction_address);
-      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_ADDRESS,"address_address",Taddress_t,_param->_size_instruction_address);
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_ADDRESS  ,"queue_address"  ,Taddress_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_VAL            ,"val"            ,Tcontrol_t,1);
+      ALLOC0_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_VAL    ,"address_val"    ,Tcontrol_t,1);
+      ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_VAL      ,"queue_val"      ,Tcontrol_t,1);
+      ALLOC0_SIGNAL_IN ( in_ICACHE_REQ_ACK            ,"ack"            ,Tcontrol_t,1);
+      ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS_ACK    ,"address_ack"    ,Tcontrol_t,1);
+      ALLOC0_SIGNAL_IN ( in_ICACHE_REQ_QUEUE_ACK      ,"queue_ack"      ,Tcontrol_t,1);
+      ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_TYPE           ,"type"           ,Ticache_type_t,_param->_size_icache_type);
+      ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS        ,"address"        ,Taddress_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_ADDRESS,"address_address",Taddress_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_ADDRESS  ,"queue_address"  ,Taddress_t,_param->_size_instruction_address);
+
+      ALLOC0_INTERFACE_END();
     }
 
     // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("event",IN, EAST, "Event interface.");
+      ALLOC0_INTERFACE_BEGIN("event",IN, EAST, _("Event interface."));
 
-      ALLOC_SIGNAL_IN ( in_EVENT_VAL        ,"val"        ,Tcontrol_t,1);
-      ALLOC_SIGNAL_OUT(out_EVENT_ADDRESS_VAL,"address_val",Tcontrol_t,1);
-      ALLOC_SIGNAL_OUT(out_EVENT_QUEUE_VAL  ,"queue_val"  ,Tcontrol_t,1);
-      ALLOC_SIGNAL_OUT(out_EVENT_ACK        ,"ack"        ,Tcontrol_t,1);
-      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_ACK,"address_ack",Tcontrol_t,1);
-      ALLOC_SIGNAL_IN ( in_EVENT_QUEUE_ACK  ,"queue_ack"  ,Tcontrol_t,1);
+      ALLOC0_SIGNAL_IN ( in_EVENT_VAL        ,"val"        ,Tcontrol_t,1);
+      ALLOC0_SIGNAL_OUT(out_EVENT_ADDRESS_VAL,"address_val",Tcontrol_t,1);
+      ALLOC0_SIGNAL_OUT(out_EVENT_QUEUE_VAL  ,"queue_val"  ,Tcontrol_t,1);
+      ALLOC0_SIGNAL_OUT(out_EVENT_ACK        ,"ack"        ,Tcontrol_t,1);
+      ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_ACK,"address_ack",Tcontrol_t,1);
+      ALLOC0_SIGNAL_IN ( in_EVENT_QUEUE_ACK  ,"queue_ack"  ,Tcontrol_t,1);
+
+      ALLOC0_INTERFACE_END();
     }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp	(revision 112)
@@ -7,4 +7,5 @@
 
 #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Ifetch_unit_Glue.h"
+#include "Behavioural/include/Allocation.h"
 
 namespace morpheo                    {
@@ -28,23 +29,22 @@
 	delete     in_NRESET;
 
-	delete    out_ICACHE_REQ_VAL         ;
-	delete     in_ICACHE_REQ_ADDRESS_VAL ;
-	delete    out_ICACHE_REQ_QUEUE_VAL   ;
-	delete     in_ICACHE_REQ_ACK         ;
-	delete    out_ICACHE_REQ_ADDRESS_ACK ;
-	delete     in_ICACHE_REQ_QUEUE_ACK   ;
-	delete    out_ICACHE_REQ_TYPE        ;
-	delete    out_ICACHE_REQ_ADDRESS         ;
-	delete     in_ICACHE_REQ_ADDRESS_ADDRESS ;
-	delete    out_ICACHE_REQ_QUEUE_ADDRESS   ;
-	
-	delete     in_EVENT_VAL              ;
-	delete    out_EVENT_ADDRESS_VAL      ;
-	delete    out_EVENT_QUEUE_VAL        ;
-	delete    out_EVENT_ACK              ;
-	delete     in_EVENT_ADDRESS_ACK      ;
-	delete     in_EVENT_QUEUE_ACK        ;
+        DELETE0_SIGNAL(out_ICACHE_REQ_VAL            ,1);
+        DELETE0_SIGNAL( in_ICACHE_REQ_ADDRESS_VAL    ,1);
+        DELETE0_SIGNAL(out_ICACHE_REQ_QUEUE_VAL      ,1);
+        DELETE0_SIGNAL( in_ICACHE_REQ_ACK            ,1);
+        DELETE0_SIGNAL(out_ICACHE_REQ_ADDRESS_ACK    ,1);
+        DELETE0_SIGNAL( in_ICACHE_REQ_QUEUE_ACK      ,1);
+        DELETE0_SIGNAL(out_ICACHE_REQ_TYPE           ,_param->_size_icache_type);
+        DELETE0_SIGNAL(out_ICACHE_REQ_ADDRESS        ,_param->_size_instruction_address);
+        DELETE0_SIGNAL( in_ICACHE_REQ_ADDRESS_ADDRESS,_param->_size_instruction_address);
+        DELETE0_SIGNAL(out_ICACHE_REQ_QUEUE_ADDRESS  ,_param->_size_instruction_address);
+        
+        DELETE0_SIGNAL( in_EVENT_VAL        ,1);
+        DELETE0_SIGNAL(out_EVENT_ADDRESS_VAL,1);
+        DELETE0_SIGNAL(out_EVENT_QUEUE_VAL  ,1);
+        DELETE0_SIGNAL(out_EVENT_ACK        ,1);
+        DELETE0_SIGNAL( in_EVENT_ADDRESS_ACK,1);
+        DELETE0_SIGNAL( in_EVENT_QUEUE_ACK  ,1);
       }
-
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config.cfg	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config.cfg	(revision 112)
@@ -1,4 +1,4 @@
 Ifetch_unit
-1	8	*2	# _size_queue                   
+8	16	*2	# _size_queue                   
 1	8	*2	# _nb_instruction               
 1	1	*2	# _size_branch_update_prediction
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp	(revision 112)
@@ -66,42 +66,42 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
-  ALLOC_SC_SIGNAL (out_ICACHE_REQ_VAL                     ,"out_ICACHE_REQ_VAL                     ",Tcontrol_t           );
-  ALLOC_SC_SIGNAL ( in_ICACHE_REQ_ACK                     ," in_ICACHE_REQ_ACK                     ",Tcontrol_t           );
-//ALLOC_SC_SIGNAL (out_ICACHE_REQ_THREAD_ID               ,"out_ICACHE_REQ_THREAD_ID               ",Tcontext_t           );
-  ALLOC_SC_SIGNAL (out_ICACHE_REQ_PACKET_ID               ,"out_ICACHE_REQ_PACKET_ID               ",Tpacket_t            );
-  ALLOC_SC_SIGNAL (out_ICACHE_REQ_ADDRESS                 ,"out_ICACHE_REQ_ADDRESS                 ",Ticache_instruction_t);
-  ALLOC_SC_SIGNAL (out_ICACHE_REQ_TYPE                    ,"out_ICACHE_REQ_TYPE                    ",Ticache_type_t       );
-  ALLOC_SC_SIGNAL ( in_ICACHE_RSP_VAL                     ," in_ICACHE_RSP_VAL                     ",Tcontrol_t           );
-  ALLOC_SC_SIGNAL (out_ICACHE_RSP_ACK                     ,"out_ICACHE_RSP_ACK                     ",Tcontrol_t           );
-//ALLOC_SC_SIGNAL ( in_ICACHE_RSP_THREAD_ID               ," in_ICACHE_RSP_THREAD_ID               ",Tcontext_t           );
-  ALLOC_SC_SIGNAL ( in_ICACHE_RSP_PACKET_ID               ," in_ICACHE_RSP_PACKET_ID               ",Tpacket_t            );
+  ALLOC0_SC_SIGNAL(out_ICACHE_REQ_VAL                     ,"out_ICACHE_REQ_VAL                     ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL( in_ICACHE_REQ_ACK                     ," in_ICACHE_REQ_ACK                     ",Tcontrol_t           );
+//ALLOC0_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID               ,"out_ICACHE_REQ_THREAD_ID               ",Tcontext_t           );
+  ALLOC0_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID               ,"out_ICACHE_REQ_PACKET_ID               ",Tpacket_t            );
+  ALLOC0_SC_SIGNAL(out_ICACHE_REQ_ADDRESS                 ,"out_ICACHE_REQ_ADDRESS                 ",Ticache_instruction_t);
+  ALLOC0_SC_SIGNAL(out_ICACHE_REQ_TYPE                    ,"out_ICACHE_REQ_TYPE                    ",Ticache_type_t       );
+  ALLOC0_SC_SIGNAL( in_ICACHE_RSP_VAL                     ," in_ICACHE_RSP_VAL                     ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL(out_ICACHE_RSP_ACK                     ,"out_ICACHE_RSP_ACK                     ",Tcontrol_t           );
+//ALLOC0_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID               ," in_ICACHE_RSP_THREAD_ID               ",Tcontext_t           );
+  ALLOC0_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID               ," in_ICACHE_RSP_PACKET_ID               ",Tpacket_t            );
   ALLOC1_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION             ," in_ICACHE_RSP_INSTRUCTION             ",Ticache_instruction_t,_param->_nb_instruction);
-  ALLOC_SC_SIGNAL ( in_ICACHE_RSP_ERROR                   ," in_ICACHE_RSP_ERROR                   ",Ticache_error_t      );
-  ALLOC_SC_SIGNAL (out_PREDICT_VAL                        ,"out_PREDICT_VAL                        ",Tcontrol_t           );
-  ALLOC_SC_SIGNAL ( in_PREDICT_ACK                        ," in_PREDICT_ACK                        ",Tcontrol_t           );
-  ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS                ,"out_PREDICT_PC_PREVIOUS                ",Tgeneral_address_t   );
-  ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT                 ,"out_PREDICT_PC_CURRENT                 ",Tgeneral_address_t   );
-  ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE      ",Tcontrol_t           );
-  ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT                    ," in_PREDICT_PC_NEXT                    ",Tgeneral_address_t   );
-  ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE         ," in_PREDICT_PC_NEXT_IS_DS_TAKE         ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL( in_ICACHE_RSP_ERROR                   ," in_ICACHE_RSP_ERROR                   ",Ticache_error_t      );
+  ALLOC0_SC_SIGNAL(out_PREDICT_VAL                        ,"out_PREDICT_VAL                        ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL( in_PREDICT_ACK                        ," in_PREDICT_ACK                        ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL(out_PREDICT_PC_PREVIOUS                ,"out_PREDICT_PC_PREVIOUS                ",Tgeneral_address_t   );
+  ALLOC0_SC_SIGNAL(out_PREDICT_PC_CURRENT                 ,"out_PREDICT_PC_CURRENT                 ",Tgeneral_address_t   );
+  ALLOC0_SC_SIGNAL(out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE      ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL( in_PREDICT_PC_NEXT                    ," in_PREDICT_PC_NEXT                    ",Tgeneral_address_t   );
+  ALLOC0_SC_SIGNAL( in_PREDICT_PC_NEXT_IS_DS_TAKE         ," in_PREDICT_PC_NEXT_IS_DS_TAKE         ",Tcontrol_t           );
   ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE         ," in_PREDICT_INSTRUCTION_ENABLE         ",Tcontrol_t           ,_param->_nb_instruction);
-  ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR            ," in_PREDICT_INST_IFETCH_PTR            ",Tinst_ifetch_ptr_t   );
-  ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE               ," in_PREDICT_BRANCH_STATE               ",Tbranch_state_t      );
-  ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t    );
+  ALLOC0_SC_SIGNAL( in_PREDICT_INST_IFETCH_PTR            ," in_PREDICT_INST_IFETCH_PTR            ",Tinst_ifetch_ptr_t   );
+  ALLOC0_SC_SIGNAL( in_PREDICT_BRANCH_STATE               ," in_PREDICT_BRANCH_STATE               ",Tbranch_state_t      );
+  ALLOC0_SC_SIGNAL( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t    );
   ALLOC1_SC_SIGNAL(out_DECOD_VAL                          ,"out_DECOD_VAL                          ",Tcontrol_t           ,_param->_nb_instruction);
   ALLOC1_SC_SIGNAL( in_DECOD_ACK                          ," in_DECOD_ACK                          ",Tcontrol_t           ,_param->_nb_instruction);
   ALLOC1_SC_SIGNAL(out_DECOD_INSTRUCTION                  ,"out_DECOD_INSTRUCTION                  ",Tinstruction_t       ,_param->_nb_instruction);
-//ALLOC_SC_SIGNAL (out_DECOD_CONTEXT_ID                   ,"out_DECOD_CONTEXT_ID                   ",Tcontext_t           );
-  ALLOC_SC_SIGNAL (out_DECOD_ADDRESS                      ,"out_DECOD_ADDRESS                      ",Tgeneral_address_t   );
-  ALLOC_SC_SIGNAL (out_DECOD_INST_IFETCH_PTR              ,"out_DECOD_INST_IFETCH_PTR              ",Tinst_ifetch_ptr_t   );
-  ALLOC_SC_SIGNAL (out_DECOD_BRANCH_STATE                 ,"out_DECOD_BRANCH_STATE                 ",Tbranch_state_t      );
-  ALLOC_SC_SIGNAL (out_DECOD_BRANCH_UPDATE_PREDICTION_ID  ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID  ",Tprediction_ptr_t    );
-  ALLOC_SC_SIGNAL (out_DECOD_EXCEPTION                    ,"out_DECOD_EXCEPTION                    ",Texception_t         );
-  ALLOC_SC_SIGNAL ( in_EVENT_VAL                          ," in_EVENT_VAL                          ",Tcontrol_t           );
-  ALLOC_SC_SIGNAL (out_EVENT_ACK                          ,"out_EVENT_ACK                          ",Tcontrol_t           );
-  ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS                      ," in_EVENT_ADDRESS                      ",Tgeneral_address_t   );
-  ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT                 ," in_EVENT_ADDRESS_NEXT                 ",Tgeneral_address_t   );
-  ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL             ," in_EVENT_ADDRESS_NEXT_VAL             ",Tcontrol_t           );
-  ALLOC_SC_SIGNAL ( in_EVENT_IS_DS_TAKE                   ," in_EVENT_IS_DS_TAKE                   ",Tcontrol_t           );
+//ALLOC0_SC_SIGNAL(out_DECOD_CONTEXT_ID                   ,"out_DECOD_CONTEXT_ID                   ",Tcontext_t           );
+  ALLOC0_SC_SIGNAL(out_DECOD_ADDRESS                      ,"out_DECOD_ADDRESS                      ",Tgeneral_address_t   );
+  ALLOC0_SC_SIGNAL(out_DECOD_INST_IFETCH_PTR              ,"out_DECOD_INST_IFETCH_PTR              ",Tinst_ifetch_ptr_t   );
+  ALLOC0_SC_SIGNAL(out_DECOD_BRANCH_STATE                 ,"out_DECOD_BRANCH_STATE                 ",Tbranch_state_t      );
+  ALLOC0_SC_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID  ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID  ",Tprediction_ptr_t    );
+  ALLOC0_SC_SIGNAL(out_DECOD_EXCEPTION                    ,"out_DECOD_EXCEPTION                    ",Texception_t         );
+  ALLOC0_SC_SIGNAL( in_EVENT_VAL                          ," in_EVENT_VAL                          ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL(out_EVENT_ACK                          ,"out_EVENT_ACK                          ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL( in_EVENT_ADDRESS                      ," in_EVENT_ADDRESS                      ",Tgeneral_address_t   );
+  ALLOC0_SC_SIGNAL( in_EVENT_ADDRESS_NEXT                 ," in_EVENT_ADDRESS_NEXT                 ",Tgeneral_address_t   );
+  ALLOC0_SC_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL             ," in_EVENT_ADDRESS_NEXT_VAL             ",Tcontrol_t           );
+  ALLOC0_SC_SIGNAL( in_EVENT_IS_DS_TAKE                   ," in_EVENT_IS_DS_TAKE                   ",Tcontrol_t           );
   
   /********************************************************
@@ -114,48 +114,48 @@
   (*(_Ifetch_unit->in_NRESET))       (*(in_NRESET));
 
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_VAL                     );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_REQ_ACK                     );
-//INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_THREAD_ID               );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_ICACHE_REQ_VAL                     );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_ICACHE_REQ_ACK                     );
+//INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_ICACHE_REQ_THREAD_ID               );
   if (_param->_have_port_ifetch_queue_ptr)
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_PACKET_ID               );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_ADDRESS                 );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_TYPE                    );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_VAL                     );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_RSP_ACK                     );
-//INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_THREAD_ID               );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_ICACHE_REQ_PACKET_ID               );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_ICACHE_REQ_ADDRESS                 );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_ICACHE_REQ_TYPE                    );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_VAL                     );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_ICACHE_RSP_ACK                     );
+//INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_THREAD_ID               );
   if (_param->_have_port_ifetch_queue_ptr)
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_PACKET_ID               );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_PACKET_ID               );
   INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_INSTRUCTION             ,_param->_nb_instruction);
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_ERROR                   );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_VAL                        );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_ACK                        );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_PREVIOUS                );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_CURRENT                 );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_CURRENT_IS_DS_TAKE      );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_PC_NEXT                    );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_PC_NEXT_IS_DS_TAKE         );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_ERROR                   );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_PREDICT_VAL                        );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_PREDICT_ACK                        );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_PREDICT_PC_PREVIOUS                );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_PREDICT_PC_CURRENT                 );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_PREDICT_PC_CURRENT_IS_DS_TAKE      );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_PREDICT_PC_NEXT                    );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_PREDICT_PC_NEXT_IS_DS_TAKE         );
   INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_PREDICT_INSTRUCTION_ENABLE         ,_param->_nb_instruction);
   if (_param->_have_port_inst_ifetch_ptr)
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_INST_IFETCH_PTR            );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_STATE               );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_PREDICT_INST_IFETCH_PTR            );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_PREDICT_BRANCH_STATE               );
   if (_param->_have_port_depth)
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
   INSTANCE1_SC_SIGNAL(_Ifetch_unit,out_DECOD_VAL                          ,_param->_nb_instruction);
   INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_DECOD_ACK                          ,_param->_nb_instruction);
   INSTANCE1_SC_SIGNAL(_Ifetch_unit,out_DECOD_INSTRUCTION                  ,_param->_nb_instruction);
-//INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_CONTEXT_ID                   );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_ADDRESS                      );
+//INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_DECOD_CONTEXT_ID                   );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_DECOD_ADDRESS                      );
   if (_param->_have_port_inst_ifetch_ptr)
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_INST_IFETCH_PTR              );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_STATE                 );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_DECOD_INST_IFETCH_PTR              );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_DECOD_BRANCH_STATE                 );
   if (_param->_have_port_depth)
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_UPDATE_PREDICTION_ID  );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_EXCEPTION                    );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_VAL                          );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_EVENT_ACK                          );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS                      );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS_NEXT                 );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS_NEXT_VAL             );
-  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_IS_DS_TAKE                   );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_DECOD_BRANCH_UPDATE_PREDICTION_ID  );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_DECOD_EXCEPTION                    );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_EVENT_VAL                          );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_EVENT_ACK                          );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_EVENT_ADDRESS                      );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_EVENT_ADDRESS_NEXT                 );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_EVENT_ADDRESS_NEXT_VAL             );
+  INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_EVENT_IS_DS_TAKE                   );
 
   msg(_("<%s> : Start Simulation ............\n"),name.c_str());
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp	(revision 112)
@@ -47,5 +47,5 @@
 							 ,IN
 							 ,SOUTH,
-							 "Generalist interface"
+							 _("Generalist interface")
 #endif
 							 );
@@ -57,80 +57,96 @@
     // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("icache_req",OUT, WEST, _("Instruction cache request."));
-
-      ALLOC_VALACK_OUT(out_ICACHE_REQ_VAL      ,VAL);
-      ALLOC_VALACK_IN ( in_ICACHE_REQ_ACK      ,ACK);
-    //ALLOC_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t           ,_param->_size_context_id );
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t            ,_param->_size_ifetch_queue_ptr  );
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS  ,"address"  ,Ticache_instruction_t,_param->_size_instruction_address    );
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE     ,"type"     ,Ticache_type_t       ,_param->_size_icache_type);
+      ALLOC0_INTERFACE_BEGIN("icache_req",OUT, WEST, _("Instruction cache request."));
+
+      ALLOC0_VALACK_OUT(out_ICACHE_REQ_VAL      ,VAL);
+      ALLOC0_VALACK_IN ( in_ICACHE_REQ_ACK      ,ACK);
+    //ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t           ,_param->_size_context_id );
+      ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t            ,_param->_size_ifetch_queue_ptr  );
+      ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS  ,"address"  ,Ticache_instruction_t,_param->_size_instruction_address    );
+      ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_TYPE     ,"type"     ,Ticache_type_t       ,_param->_size_icache_type);
+
+      ALLOC0_INTERFACE_END();
     }
 
     // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons."));
-
-      ALLOC_VALACK_IN  ( in_ICACHE_RSP_VAL        ,VAL);
-      ALLOC_VALACK_OUT (out_ICACHE_RSP_ACK        ,ACK);
-    //ALLOC_SIGNAL_IN  ( in_ICACHE_RSP_THREAD_ID  ,"thread_id"  ,Tcontext_t           ,_param->_size_context_id  );
-      ALLOC_SIGNAL_IN  ( in_ICACHE_RSP_PACKET_ID  ,"packet_id"  ,Tpacket_t            ,_param->_size_ifetch_queue_ptr   );
-      ALLOC_SIGNAL_IN  ( in_ICACHE_RSP_ERROR      ,"error"      ,Ticache_error_t      ,_param->_size_icache_error);
-    }
-    {
-      ALLOC1_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_instruction);
+      ALLOC0_INTERFACE_BEGIN("icache_rsp",IN , WEST, _("Instruction cache respons."));
+
+      ALLOC0_VALACK_IN  ( in_ICACHE_RSP_VAL        ,VAL);
+      ALLOC0_VALACK_OUT (out_ICACHE_RSP_ACK        ,ACK);
+    //ALLOC0_SIGNAL_IN  ( in_ICACHE_RSP_THREAD_ID  ,"thread_id"  ,Tcontext_t           ,_param->_size_context_id  );
+      ALLOC0_SIGNAL_IN  ( in_ICACHE_RSP_PACKET_ID  ,"packet_id"  ,Tpacket_t            ,_param->_size_ifetch_queue_ptr   );
+      ALLOC0_SIGNAL_IN  ( in_ICACHE_RSP_ERROR      ,"error"      ,Ticache_error_t      ,_param->_size_icache_error);
+
+      ALLOC0_INTERFACE_END();
+    }
+    {
+      ALLOC1_INTERFACE_BEGIN("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_instruction);
 
       ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction );
+
+      ALLOC1_INTERFACE_END(_param->_nb_instruction);
     }
 
     // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("predict",OUT, NORTH, _("Predict the next pc."));
-
-      ALLOC_VALACK_OUT (out_PREDICT_VAL                        ,VAL);
-      ALLOC_VALACK_IN  ( in_PREDICT_ACK                        ,ACK);
-      ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS                ,"pc_previous"                ,Tgeneral_address_t,_param->_size_instruction_address);
-      ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT                 ,"pc_current"                 ,Tgeneral_address_t,_param->_size_instruction_address);
-      ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,"pc_current_is_ds_take"      ,Tcontrol_t        ,1);
-      ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT                    ,"pc_next"                    ,Tgeneral_address_t,_param->_size_instruction_address);
-      ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT_IS_DS_TAKE         ,"pc_next_is_ds_take"         ,Tcontrol_t        ,1);
-      ALLOC_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
-      ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
-      ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
-    }
-    {
-      ALLOC1_INTERFACE("predict",IN , NORTH, _("Predict the next pc."),_param->_nb_instruction);
+      ALLOC0_INTERFACE_BEGIN("predict",OUT, NORTH, _("Predict the next pc."));
+
+      ALLOC0_VALACK_OUT (out_PREDICT_VAL                        ,VAL);
+      ALLOC0_VALACK_IN  ( in_PREDICT_ACK                        ,ACK);
+      ALLOC0_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS                ,"pc_previous"                ,Tgeneral_address_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT                 ,"pc_current"                 ,Tgeneral_address_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,"pc_current_is_ds_take"      ,Tcontrol_t        ,1);
+      ALLOC0_SIGNAL_IN  ( in_PREDICT_PC_NEXT                    ,"pc_next"                    ,Tgeneral_address_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_IN  ( in_PREDICT_PC_NEXT_IS_DS_TAKE         ,"pc_next_is_ds_take"         ,Tcontrol_t        ,1);
+      ALLOC0_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
+      ALLOC0_SIGNAL_IN  ( in_PREDICT_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
+      ALLOC0_SIGNAL_IN  ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
+
+      ALLOC0_INTERFACE_END();
+    }
+    {
+      ALLOC1_INTERFACE_BEGIN("predict",IN , NORTH, _("Predict the next pc."),_param->_nb_instruction);
 
       ALLOC1_SIGNAL_IN ( in_PREDICT_INSTRUCTION_ENABLE         ,"instruction_enable"         ,Tcontrol_t        ,1);
+
+      ALLOC1_INTERFACE_END(_param->_nb_instruction);
     }
 
     // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit."));
-
-    //ALLOC_SIGNAL_OUT (out_DECOD_CONTEXT_ID                 ,"context_id"                 ,Tcontext_t        ,_param->_size_context_id);
-      ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address);
-      ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
-      ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
-      ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
-      ALLOC_SIGNAL_OUT (out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
-    }
-    {
-      ALLOC1_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction);
+      ALLOC0_INTERFACE_BEGIN("decod",OUT , EAST, _("Send bundle to the decod unit."));
+
+    //ALLOC0_SIGNAL_OUT (out_DECOD_CONTEXT_ID                 ,"context_id"                 ,Tcontext_t        ,_param->_size_context_id);
+      ALLOC0_SIGNAL_OUT (out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
+      ALLOC0_SIGNAL_OUT (out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
+      ALLOC0_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
+      ALLOC0_SIGNAL_OUT (out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
+
+      ALLOC0_INTERFACE_END();
+    }
+    {
+      ALLOC1_INTERFACE_BEGIN("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction);
 
       ALLOC1_VALACK_OUT(out_DECOD_VAL                        ,VAL);
       ALLOC1_VALACK_IN ( in_DECOD_ACK                        ,ACK);
       ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION                ,"instruction"                ,Tinstruction_t    ,_param->_size_instruction);
+
+      ALLOC1_INTERFACE_END(_param->_nb_instruction);
     }
 
     // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("event",IN , NORTH, _("Event interface."));
-
-      ALLOC_VALACK_IN ( in_EVENT_VAL              ,VAL);
-      ALLOC_VALACK_OUT(out_EVENT_ACK              ,ACK);
-      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS          ,"address"         ,Tgeneral_address_t,_param->_size_instruction_address);
-      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT     ,"address_next"    ,Tgeneral_address_t,_param->_size_instruction_address);
-      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t,1);
-      ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE       ,"is_ds_take"      ,Tcontrol_t,1);
+      ALLOC0_INTERFACE_BEGIN("event",IN , NORTH, _("Event interface."));
+
+      ALLOC0_VALACK_IN ( in_EVENT_VAL              ,VAL);
+      ALLOC0_VALACK_OUT(out_EVENT_ACK              ,ACK);
+      ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS          ,"address"         ,Tgeneral_address_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT     ,"address_next"    ,Tgeneral_address_t,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t,1);
+      ALLOC0_SIGNAL_IN ( in_EVENT_IS_DS_TAKE       ,"is_ds_take"      ,Tcontrol_t,1);
+ 
+      ALLOC0_INTERFACE_END();
     }
     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp	(revision 112)
@@ -7,4 +7,5 @@
 
 #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h"
+#include "Behavioural/include/Allocation.h"
 
 namespace morpheo                    {
@@ -27,53 +28,48 @@
 	delete     in_NRESET;
 
-	delete    out_ICACHE_REQ_VAL                      ;
-	delete     in_ICACHE_REQ_ACK                      ;
-      //delete    out_ICACHE_REQ_THREAD_ID                ;
-	if (_param->_have_port_ifetch_queue_ptr)
-	delete    out_ICACHE_REQ_PACKET_ID                ;
-	delete    out_ICACHE_REQ_ADDRESS                  ;
-	delete    out_ICACHE_REQ_TYPE                     ;
+        DELETE0_SIGNAL(out_ICACHE_REQ_VAL      ,1);
+        DELETE0_SIGNAL( in_ICACHE_REQ_ACK      ,1);
+//      DELETE0_SIGNAL(out_ICACHE_REQ_THREAD_ID,_param->_size_context_id );
+        DELETE0_SIGNAL(out_ICACHE_REQ_PACKET_ID,_param->_size_ifetch_queue_ptr  );
+        DELETE0_SIGNAL(out_ICACHE_REQ_ADDRESS  ,_param->_size_instruction_address    );
+        DELETE0_SIGNAL(out_ICACHE_REQ_TYPE     ,_param->_size_icache_type);
 
-	delete     in_ICACHE_RSP_VAL                      ;
-	delete    out_ICACHE_RSP_ACK                      ;
-      //delete     in_ICACHE_RSP_THREAD_ID                ;
-	if (_param->_have_port_ifetch_queue_ptr)
-        delete     in_ICACHE_RSP_PACKET_ID                ;
-	delete []  in_ICACHE_RSP_INSTRUCTION              ;
-	delete     in_ICACHE_RSP_ERROR                    ;
+        DELETE0_SIGNAL( in_ICACHE_RSP_VAL        ,1);
+        DELETE0_SIGNAL(out_ICACHE_RSP_ACK        ,1);
+    //  DELETE0_SIGNAL( in_ICACHE_RSP_THREAD_ID  ,_param->_size_context_id  );
+        DELETE0_SIGNAL( in_ICACHE_RSP_PACKET_ID  ,_param->_size_ifetch_queue_ptr   );
+        DELETE0_SIGNAL( in_ICACHE_RSP_ERROR      ,_param->_size_icache_error);
+        DELETE1_SIGNAL( in_ICACHE_RSP_INSTRUCTION,_param->_size_instruction,_param->_nb_instruction);
 
-	delete    out_PREDICT_VAL                         ;
-	delete     in_PREDICT_ACK                         ;
-	delete    out_PREDICT_PC_PREVIOUS                 ;
-	delete    out_PREDICT_PC_CURRENT                  ;
-	delete    out_PREDICT_PC_CURRENT_IS_DS_TAKE       ;
-	delete     in_PREDICT_PC_NEXT                     ;
-	delete     in_PREDICT_PC_NEXT_IS_DS_TAKE          ;
-	delete []  in_PREDICT_INSTRUCTION_ENABLE          ;
-	if (_param->_have_port_inst_ifetch_ptr)
-	delete     in_PREDICT_INST_IFETCH_PTR             ;
-	delete     in_PREDICT_BRANCH_STATE                ;
-	if (_param->_have_port_depth)
-	delete     in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ;
+        DELETE0_SIGNAL(out_PREDICT_VAL                        ,1);
+        DELETE0_SIGNAL( in_PREDICT_ACK                        ,1);
+        DELETE0_SIGNAL(out_PREDICT_PC_PREVIOUS                ,_param->_size_instruction_address);
+        DELETE0_SIGNAL(out_PREDICT_PC_CURRENT                 ,_param->_size_instruction_address);
+        DELETE0_SIGNAL(out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,1);
+        DELETE0_SIGNAL( in_PREDICT_PC_NEXT                    ,_param->_size_instruction_address);
+        DELETE0_SIGNAL( in_PREDICT_PC_NEXT_IS_DS_TAKE         ,1);
+        DELETE0_SIGNAL( in_PREDICT_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr);
+        DELETE0_SIGNAL( in_PREDICT_BRANCH_STATE               ,_param->_size_branch_state);
+        DELETE0_SIGNAL( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth);
+        DELETE1_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE         ,1,_param->_nb_instruction);
 
-	delete [] out_DECOD_VAL                           ;
-	delete []  in_DECOD_ACK                           ;
-	delete [] out_DECOD_INSTRUCTION                   ;
-      //delete    out_DECOD_CONTEXT_ID                    ;
-	delete    out_DECOD_ADDRESS                       ;
-	if (_param->_have_port_inst_ifetch_ptr)
-	delete    out_DECOD_INST_IFETCH_PTR               ;
-	delete    out_DECOD_BRANCH_STATE                  ;
-	if (_param->_have_port_depth)
-	delete    out_DECOD_BRANCH_UPDATE_PREDICTION_ID   ;
-	delete    out_DECOD_EXCEPTION                     ;
+    //  DELETE0_SIGNAL(out_DECOD_CONTEXT_ID                 ,_param->_size_context_id);
+        DELETE0_SIGNAL(out_DECOD_ADDRESS                    ,_param->_size_instruction_address);
+        DELETE0_SIGNAL(out_DECOD_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr);
+        DELETE0_SIGNAL(out_DECOD_BRANCH_STATE               ,_param->_size_branch_state);
+        DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth);
+        DELETE0_SIGNAL(out_DECOD_EXCEPTION                  ,_param->_size_exception_ifetch);
+        DELETE1_SIGNAL(out_DECOD_VAL                        ,1,_param->_nb_instruction);
+        DELETE1_SIGNAL( in_DECOD_ACK                        ,1,_param->_nb_instruction);
+        DELETE1_SIGNAL(out_DECOD_INSTRUCTION                ,_param->_size_instruction,_param->_nb_instruction);
 
-	delete     in_EVENT_VAL                           ;
-	delete    out_EVENT_ACK                           ;
-	delete     in_EVENT_ADDRESS                       ;
-	delete     in_EVENT_ADDRESS_NEXT                  ;
-	delete     in_EVENT_ADDRESS_NEXT_VAL              ;
-	delete     in_EVENT_IS_DS_TAKE                    ;
+        DELETE0_SIGNAL( in_EVENT_VAL              ,1);
+        DELETE0_SIGNAL(out_EVENT_ACK              ,1);
+        DELETE0_SIGNAL( in_EVENT_ADDRESS          ,_param->_size_instruction_address);
+        DELETE0_SIGNAL( in_EVENT_ADDRESS_NEXT     ,_param->_size_instruction_address);
+        DELETE0_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL ,1);
+        DELETE0_SIGNAL( in_EVENT_IS_DS_TAKE       ,1);
       }
+
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
     delete _component_address_management;
