Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp	(revision 112)
@@ -153,16 +153,16 @@
   ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE    ,"out_BRANCH_COMPLETE_NO_SEQUENCE    ",Tcontrol_t        ,_param->_nb_inst_branch_complete);
   ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t        ,_param->_nb_inst_branch_complete);
-  ALLOC_SC_SIGNAL (out_UPDATE_VAL                      ,"out_UPDATE_VAL                      ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL ( in_UPDATE_ACK                      ," in_UPDATE_ACK                      ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL (out_UPDATE_CONTEXT_ID               ,"out_UPDATE_CONTEXT_ID               ",Tcontext_t        );
-  ALLOC_SC_SIGNAL (out_UPDATE_FRONT_END_ID             ,"out_UPDATE_FRONT_END_ID             ",Tcontext_t        );
-  ALLOC_SC_SIGNAL (out_UPDATE_DEPTH                    ,"out_UPDATE_DEPTH                    ",Tdepth_t          );
-  ALLOC_SC_SIGNAL (out_UPDATE_TYPE                     ,"out_UPDATE_TYPE                     ",Tevent_type_t     );
-  ALLOC_SC_SIGNAL (out_UPDATE_IS_DELAY_SLOT            ,"out_UPDATE_IS_DELAY_SLOT            ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS                  ,"out_UPDATE_ADDRESS                  ",Taddress_t        );
-  ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR_VAL         ,"out_UPDATE_ADDRESS_EPCR_VAL         ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR             ,"out_UPDATE_ADDRESS_EPCR             ",Taddress_t        );
-  ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL         ,"out_UPDATE_ADDRESS_EEAR_VAL         ",Tcontrol_t        );
-  ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR             ,"out_UPDATE_ADDRESS_EEAR             ",Tgeneral_data_t   );
+  ALLOC0_SC_SIGNAL(out_UPDATE_VAL                      ,"out_UPDATE_VAL                      ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL( in_UPDATE_ACK                      ," in_UPDATE_ACK                      ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL(out_UPDATE_CONTEXT_ID               ,"out_UPDATE_CONTEXT_ID               ",Tcontext_t        );
+  ALLOC0_SC_SIGNAL(out_UPDATE_FRONT_END_ID             ,"out_UPDATE_FRONT_END_ID             ",Tcontext_t        );
+  ALLOC0_SC_SIGNAL(out_UPDATE_DEPTH                    ,"out_UPDATE_DEPTH                    ",Tdepth_t          );
+  ALLOC0_SC_SIGNAL(out_UPDATE_TYPE                     ,"out_UPDATE_TYPE                     ",Tevent_type_t     );
+  ALLOC0_SC_SIGNAL(out_UPDATE_IS_DELAY_SLOT            ,"out_UPDATE_IS_DELAY_SLOT            ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS                  ,"out_UPDATE_ADDRESS                  ",Taddress_t        );
+  ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS_EPCR_VAL         ,"out_UPDATE_ADDRESS_EPCR_VAL         ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS_EPCR             ,"out_UPDATE_ADDRESS_EPCR             ",Taddress_t        );
+  ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS_EEAR_VAL         ,"out_UPDATE_ADDRESS_EEAR_VAL         ",Tcontrol_t        );
+  ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS_EEAR             ,"out_UPDATE_ADDRESS_EEAR             ",Tgeneral_data_t   );
 
   ALLOC2_SC_SIGNAL( in_EVENT_VAL             ," in_EVENT_VAL             ",Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]);
@@ -304,19 +304,19 @@
   INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_NO_SEQUENCE    ,_param->_nb_inst_branch_complete);
   INSTANCE1_SC_SIGNAL(_Commit_unit, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
-  INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_VAL                      );
-  INSTANCE_SC_SIGNAL (_Commit_unit, in_UPDATE_ACK                      );
+  INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_VAL                      );
+  INSTANCE0_SC_SIGNAL(_Commit_unit, in_UPDATE_ACK                      );
   if (_param->_have_port_context_id)
-  INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_CONTEXT_ID               );
+  INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_CONTEXT_ID               );
   if (_param->_have_port_front_end_id)
-  INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_FRONT_END_ID             );
+  INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_FRONT_END_ID             );
   if (_param->_have_port_depth)
-  INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_DEPTH                    );
-  INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_TYPE                     );
-  INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_IS_DELAY_SLOT            );
-  INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS                  );
-  INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EPCR_VAL         );
-  INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EPCR             );
-  INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EEAR_VAL         );
-  INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EEAR             );
+  INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_DEPTH                    );
+  INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_TYPE                     );
+  INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_IS_DELAY_SLOT            );
+  INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS                  );
+  INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EPCR_VAL         );
+  INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EPCR             );
+  INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EEAR_VAL         );
+  INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EEAR             );
 
   INSTANCE2_SC_SIGNAL(_Commit_unit, in_EVENT_VAL                       ,_param->_nb_front_end, _param->_nb_context[it1]);
@@ -708,16 +708,16 @@
   DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE    ,_param->_nb_inst_branch_complete);
   DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
-  DELETE_SC_SIGNAL (out_UPDATE_VAL                      );
-  DELETE_SC_SIGNAL ( in_UPDATE_ACK                      );
-  DELETE_SC_SIGNAL (out_UPDATE_CONTEXT_ID               );
-  DELETE_SC_SIGNAL (out_UPDATE_FRONT_END_ID             );
-  DELETE_SC_SIGNAL (out_UPDATE_DEPTH                    );
-  DELETE_SC_SIGNAL (out_UPDATE_TYPE                     );
-  DELETE_SC_SIGNAL (out_UPDATE_IS_DELAY_SLOT            );
-  DELETE_SC_SIGNAL (out_UPDATE_ADDRESS                  );
-  DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR_VAL         );
-  DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR             );
-  DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL         );
-  DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR             );
+  DELETE0_SC_SIGNAL(out_UPDATE_VAL                      );
+  DELETE0_SC_SIGNAL( in_UPDATE_ACK                      );
+  DELETE0_SC_SIGNAL(out_UPDATE_CONTEXT_ID               );
+  DELETE0_SC_SIGNAL(out_UPDATE_FRONT_END_ID             );
+  DELETE0_SC_SIGNAL(out_UPDATE_DEPTH                    );
+  DELETE0_SC_SIGNAL(out_UPDATE_TYPE                     );
+  DELETE0_SC_SIGNAL(out_UPDATE_IS_DELAY_SLOT            );
+  DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS                  );
+  DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS_EPCR_VAL         );
+  DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS_EPCR             );
+  DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS_EEAR_VAL         );
+  DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS_EEAR             );
 
   DELETE2_SC_SIGNAL( in_EVENT_VAL                       ,_param->_nb_front_end, _param->_nb_context[it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 112)
@@ -238,4 +238,5 @@
   private   : Tevent_state_t               ** reg_EVENT_STATE                      ;//[nb_front_end][nb_context]
   private   : bool                         ** reg_EVENT_FLUSH                      ;//[nb_front_end][nb_context]
+  private   : bool                         ** reg_EVENT_STOP                       ;//[nb_front_end][nb_context]
 
 //private   : Taddress_t                   ** reg_PC_PREVIOUS                      ;//[nb_front_end][nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 112)
@@ -35,5 +35,7 @@
       ROB_STORE_HEAD_KO              , // 
       ROB_OTHER_WAIT_END             , // 
-      ROB_MISS_WAIT_END              , // 
+
+      ROB_EVENT_WAIT_END             , // 
+
       ROB_END_OK_SPECULATIVE         , // 
       ROB_END_OK                     , // 
@@ -49,4 +51,5 @@
       ROB_END_EXCEPTION_UPDATE       , // 
       ROB_END_EXCEPTION                // 
+
     } rob_state_t;
 
@@ -121,5 +124,5 @@
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO              : return "ROB_STORE_HEAD_KO"               ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END             : return "ROB_OTHER_WAIT_END"              ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_MISS_WAIT_END              : return "ROB_MISS_WAIT_END"               ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EVENT_WAIT_END             : return "ROB_EVENT_WAIT_END"              ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK_SPECULATIVE         : return "ROB_END_OK_SPECULATIVE"          ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK                     : return "ROB_END_OK"                      ; break;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp	(revision 112)
@@ -118,13 +118,13 @@
 # ifdef SYSTEMCASS_SPECIFIC
 	// List dependency information
-	for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
-	  for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++)
-	    for (uint32_t x=0; x<_param->_nb_rename_unit; x++)
-	      for (uint32_t y=0; y<_param->_nb_inst_insert[x]; y++)
-		{
-		  (*(out_INSERT_ACK       [i][j])) (*(in_INSERT_VAL [x][y]));
-		  if (_param->_have_port_rob_ptr)
-		  (*(out_INSERT_PACKET_ID [i][j])) (*(in_INSERT_VAL [x][y]));
-		}
+// 	for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
+// 	  for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++)
+// 	    for (uint32_t x=0; x<_param->_nb_rename_unit; x++)
+// 	      for (uint32_t y=0; y<_param->_nb_inst_insert[x]; y++)
+// 		{
+// 		  (*(out_INSERT_ACK       [i][j])) (*(in_INSERT_VAL [x][y]));
+// 		  if (_param->_have_port_rob_ptr)
+// 		  (*(out_INSERT_PACKET_ID [i][j])) (*(in_INSERT_VAL [x][y]));
+// 		}
 # endif    
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 112)
@@ -58,5 +58,5 @@
     // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC2_INTERFACE("insert", IN, SOUTH, _("Interface with rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      ALLOC2_INTERFACE_BEGIN("insert", IN, SOUTH, _("Interface with rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
 
       _ALLOC2_VALACK_IN ( in_INSERT_VAL                     ,VAL,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -96,9 +96,11 @@
       _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_OLD      ,"num_reg_re_phy_old"   ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
       _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_NEW      ,"num_reg_re_phy_new"   ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
     }
 
     // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC2_INTERFACE("retire",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+      ALLOC2_INTERFACE_BEGIN("retire",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
       
       _ALLOC2_VALACK_OUT(out_RETIRE_VAL                     ,VAL,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
@@ -125,18 +127,22 @@
       _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RE_PHY_OLD      ,"num_reg_re_phy_old"   ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
       _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RE_PHY_NEW      ,"num_reg_re_phy_new"   ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
     }
 
     // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC2_INTERFACE("retire_event",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_front_end,_param->_nb_context[it1]);
+      ALLOC2_INTERFACE_BEGIN("retire_event",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_front_end,_param->_nb_context[it1]);
     
       _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_VAL               ,VAL,_param->_nb_front_end,_param->_nb_context[it1]);
       _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_ACK               ,ACK,_param->_nb_front_end,_param->_nb_context[it1]);
       _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STATE             ,"state"                ,Tevent_state_t    ,_param->_size_event_state           ,_param->_nb_front_end,_param->_nb_context[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]);
     }
 
     // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("commit",IN,EAST,_("End of execute."),_param->_nb_inst_commit);
+      ALLOC1_INTERFACE_BEGIN("commit",IN,EAST,_("End of execute."),_param->_nb_inst_commit);
 
       ALLOC1_VALACK_IN ( in_COMMIT_VAL               ,VAL);
@@ -152,9 +158,11 @@
 //    ALLOC1_SIGNAL_OUT(out_COMMIT_NUM_REG_RD        ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register+_param->_size_rename_unit_id);
       ALLOC1_SIGNAL_OUT(out_COMMIT_NUM_REG_RD        ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register);
+
+      ALLOC1_INTERFACE_END(_param->_nb_inst_commit);
     }
 
     // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("reexecute",OUT,EAST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_reexecute);
+      ALLOC1_INTERFACE_BEGIN("reexecute",OUT,EAST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_reexecute);
 
       ALLOC1_VALACK_OUT(out_REEXECUTE_VAL                  ,VAL);
@@ -166,9 +174,11 @@
       ALLOC1_SIGNAL_OUT(out_REEXECUTE_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type);
       ALLOC1_SIGNAL_OUT(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
+
+      ALLOC1_INTERFACE_END(_param->_nb_inst_reexecute);
     }
 
     // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("branch_complete",OUT,WEST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_branch_complete);
+      ALLOC1_INTERFACE_BEGIN("branch_complete",OUT,WEST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_branch_complete);
 
       ALLOC1_VALACK_OUT(out_BRANCH_COMPLETE_VAL            ,VAL);
@@ -181,27 +191,31 @@
       ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_NO_SEQUENCE    ,"no_sequence"    ,Tcontrol_t         ,1);
       ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION,"miss_prediction",Tcontrol_t         ,1);
+
+      ALLOC1_INTERFACE_END(_param->_nb_inst_branch_complete);
     }
 
     // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC_INTERFACE("update", OUT, WEST,_("Interface with to Context State."));
-
-      ALLOC_VALACK_OUT(out_UPDATE_VAL                      ,VAL);
-      ALLOC_VALACK_IN ( in_UPDATE_ACK                      ,ACK);
-      ALLOC_SIGNAL_OUT(out_UPDATE_CONTEXT_ID               ,"context_id"      ,Tcontext_t         ,_param->_size_context_id);
-      ALLOC_SIGNAL_OUT(out_UPDATE_FRONT_END_ID             ,"front_end_id"    ,Tcontext_t         ,_param->_size_front_end_id);
-      ALLOC_SIGNAL_OUT(out_UPDATE_DEPTH                    ,"depth"           ,Tdepth_t           ,_param->_size_depth    );
-      ALLOC_SIGNAL_OUT(out_UPDATE_TYPE                     ,"type"            ,Tevent_type_t      ,_param->_size_event_type);
-      ALLOC_SIGNAL_OUT(out_UPDATE_IS_DELAY_SLOT            ,"is_delay_slot"   ,Tcontrol_t         ,1);
-      ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS                  ,"address"         ,Taddress_t         ,_param->_size_instruction_address);
-      ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR_VAL         ,"address_epcr_val",Tcontrol_t         ,1);
-      ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR             ,"address_epcr"    ,Taddress_t         ,_param->_size_instruction_address);
-      ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR_VAL         ,"address_eear_val",Tcontrol_t         ,1);
-      ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR             ,"address_eear"    ,Tgeneral_data_t    ,_param->_size_general_data);
+      ALLOC0_INTERFACE_BEGIN("update", OUT, WEST,_("Interface with to Context State."));
+
+      ALLOC0_VALACK_OUT(out_UPDATE_VAL                      ,VAL);
+      ALLOC0_VALACK_IN ( in_UPDATE_ACK                      ,ACK);
+      ALLOC0_SIGNAL_OUT(out_UPDATE_CONTEXT_ID               ,"context_id"      ,Tcontext_t         ,_param->_size_context_id);
+      ALLOC0_SIGNAL_OUT(out_UPDATE_FRONT_END_ID             ,"front_end_id"    ,Tcontext_t         ,_param->_size_front_end_id);
+      ALLOC0_SIGNAL_OUT(out_UPDATE_DEPTH                    ,"depth"           ,Tdepth_t           ,_param->_size_depth    );
+      ALLOC0_SIGNAL_OUT(out_UPDATE_TYPE                     ,"type"            ,Tevent_type_t      ,_param->_size_event_type);
+      ALLOC0_SIGNAL_OUT(out_UPDATE_IS_DELAY_SLOT            ,"is_delay_slot"   ,Tcontrol_t         ,1);
+      ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS                  ,"address"         ,Taddress_t         ,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR_VAL         ,"address_epcr_val",Tcontrol_t         ,1);
+      ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR             ,"address_epcr"    ,Taddress_t         ,_param->_size_instruction_address);
+      ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR_VAL         ,"address_eear_val",Tcontrol_t         ,1);
+      ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR             ,"address_eear"    ,Tgeneral_data_t    ,_param->_size_general_data);
+
+      ALLOC0_INTERFACE_END();
     }
 
     // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC2_INTERFACE("event",IN,WEST,_("Interface with Context State (event)."),_param->_nb_front_end, _param->_nb_context[it1]);
+      ALLOC2_INTERFACE_BEGIN("event",IN,WEST,_("Interface with Context State (event)."),_param->_nb_front_end, _param->_nb_context[it1]);
 
       _ALLOC2_VALACK_IN ( in_EVENT_VAL             , VAL                                                           ,_param->_nb_front_end, _param->_nb_context[it1]);
@@ -211,22 +225,28 @@
       _ALLOC2_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"ADDRESS_NEXT_VAL",Tcontrol_t,1                                ,_param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_IN ( in_EVENT_IS_DS_TAKE      ,"IS_DS_TAKE"      ,Tcontrol_t,1                                ,_param->_nb_front_end, _param->_nb_context[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
     }  
 
     // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC2_INTERFACE("nb_inst",OUT,WEST,_("Interface with Context State (synchronization)."),_param->_nb_front_end, _param->_nb_context[it1]);
+      ALLOC2_INTERFACE_BEGIN("nb_inst",OUT,WEST,_("Interface with Context State (synchronization)."),_param->_nb_front_end, _param->_nb_context[it1]);
 
       _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_ALL             ,"commit_all",Tcounter_t         ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_MEM             ,"commit_mem",Tcounter_t         ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_IN ( in_NB_INST_DECOD_ALL              ,"decod_all" ,Tcounter_t         ,_param->_size_nb_inst_decod ,_param->_nb_front_end, _param->_nb_context[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
     }
 
     // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC2_INTERFACE("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);
+      ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);
 
       _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN                     ,"min"      ,Tdepth_t           ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX                     ,"max"      ,Tdepth_t           ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL                    ,"full"     ,Tcontrol_t         ,1                  ,_param->_nb_front_end, _param->_nb_context[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
     }
 
@@ -234,12 +254,14 @@
     // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC2_INTERFACE("spr_read",IN ,EAST,_("Interface with special register file (read)."),_param->_nb_front_end, _param->_nb_context[it1]);
+      ALLOC2_INTERFACE_BEGIN("spr_read",IN ,EAST,_("Interface with special register file (read)."),_param->_nb_front_end, _param->_nb_context[it1]);
 
       _ALLOC2_SIGNAL_IN ( in_SPR_READ_SR_OVE                ,"sr_ove"    ,Tcontrol_t         ,1,_param->_nb_front_end, _param->_nb_context[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
     }
 
     // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC2_INTERFACE("spr_write",OUT,EAST,_("Interface with special register file (write)."),_param->_nb_front_end, _param->_nb_context[it1]);
+      ALLOC2_INTERFACE_BEGIN("spr_write",OUT,EAST,_("Interface with special register file (write)."),_param->_nb_front_end, _param->_nb_context[it1]);
 
       _ALLOC2_VALACK_OUT(out_SPR_WRITE_VAL                    ,VAL,_param->_nb_front_end, _param->_nb_context[it1]);
@@ -251,4 +273,6 @@
       _ALLOC2_SIGNAL_OUT(out_SPR_WRITE_SR_OV_VAL              ,"sr_ov_val"   ,Tcontrol_t         ,1                         ,_param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_OUT(out_SPR_WRITE_SR_OV                  ,"sr_ov"       ,Tcontrol_t         ,1                         ,_param->_nb_front_end, _param->_nb_context[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
     }
 
@@ -289,4 +313,5 @@
     ALLOC2(reg_EVENT_STATE          ,Tevent_state_t,_param->_nb_front_end,_param->_nb_context [it1]);
     ALLOC2(reg_EVENT_FLUSH          ,bool          ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_STOP           ,bool          ,_param->_nb_front_end,_param->_nb_context [it1]);
 
 //  ALLOC2(reg_PC_PREVIOUS          ,Taddress_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 112)
@@ -124,16 +124,16 @@
         DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1);
 
-        DELETE_SIGNAL (out_UPDATE_VAL                      ,1                         );
-        DELETE_SIGNAL ( in_UPDATE_ACK                      ,1                         );
-        DELETE_SIGNAL (out_UPDATE_CONTEXT_ID               ,_param->_size_context_id  );
-        DELETE_SIGNAL (out_UPDATE_FRONT_END_ID             ,_param->_size_front_end_id);
-        DELETE_SIGNAL (out_UPDATE_DEPTH                    ,_param->_size_depth       );
-        DELETE_SIGNAL (out_UPDATE_TYPE                     ,_param->_size_event_type  );
-        DELETE_SIGNAL (out_UPDATE_IS_DELAY_SLOT            ,1                         );
-        DELETE_SIGNAL (out_UPDATE_ADDRESS                  ,_param->_size_instruction_address     );
-        DELETE_SIGNAL (out_UPDATE_ADDRESS_EPCR_VAL         ,1                         );
-        DELETE_SIGNAL (out_UPDATE_ADDRESS_EPCR             ,_param->_size_instruction_address     );
-        DELETE_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL         ,1                         );
-        DELETE_SIGNAL (out_UPDATE_ADDRESS_EEAR             ,_param->_size_instruction_address     );
+        DELETE0_SIGNAL(out_UPDATE_VAL                      ,1                         );
+        DELETE0_SIGNAL( in_UPDATE_ACK                      ,1                         );
+        DELETE0_SIGNAL(out_UPDATE_CONTEXT_ID               ,_param->_size_context_id  );
+        DELETE0_SIGNAL(out_UPDATE_FRONT_END_ID             ,_param->_size_front_end_id);
+        DELETE0_SIGNAL(out_UPDATE_DEPTH                    ,_param->_size_depth       );
+        DELETE0_SIGNAL(out_UPDATE_TYPE                     ,_param->_size_event_type  );
+        DELETE0_SIGNAL(out_UPDATE_IS_DELAY_SLOT            ,1                         );
+        DELETE0_SIGNAL(out_UPDATE_ADDRESS                  ,_param->_size_instruction_address     );
+        DELETE0_SIGNAL(out_UPDATE_ADDRESS_EPCR_VAL         ,1                         );
+        DELETE0_SIGNAL(out_UPDATE_ADDRESS_EPCR             ,_param->_size_instruction_address     );
+        DELETE0_SIGNAL(out_UPDATE_ADDRESS_EEAR_VAL         ,1                         );
+        DELETE0_SIGNAL(out_UPDATE_ADDRESS_EEAR             ,_param->_size_instruction_address     );
 
         DELETE2_SIGNAL( in_EVENT_VAL                       ,_param->_nb_front_end, _param->_nb_context[it1],1                    );
@@ -194,4 +194,5 @@
         DELETE2(reg_EVENT_STATE          ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_EVENT_FLUSH          ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_STOP           ,_param->_nb_front_end,_param->_nb_context [it1]);
 //      DELETE2(reg_PC_PREVIOUS          ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_PC_CURRENT           ,_param->_nb_front_end,_param->_nb_context [it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 112)
@@ -30,6 +30,11 @@
 #endif
     bool       can_rename_select [_param->_nb_rename_unit];
-    
-    // Initialisation
+    bool       event_stop;
+   
+//     Initialisation
+    event_stop = false; // one signal for all context.
+    for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+      for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+        event_stop |= reg_EVENT_STOP [i][j];
     for (uint32_t i=0; i<_param->_nb_bank; i++)
       {
@@ -52,64 +57,67 @@
 //     log_printf(TRACE,Commit_unit,FUNCTION,"  * reg_NUM_BANK_TAIL : %d",reg_NUM_BANK_TAIL);
 
-    std::list<generic::priority::select_t> * select_insert = _priority_insert ->select(); // same select for all insert
-    std::list<generic::priority::select_t>::iterator it=select_insert ->begin();
-
-    // Scan all bank ...
-    for (uint32_t i=0; i<_param->_nb_bank; i++)
+    if (not event_stop)
       {
-	// compute the bank number (num_bank_tail is the older write slot)
-	uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank;
-
-// 	log_printf(TRACE,Commit_unit,FUNCTION,"  * BANK : %d", num_bank);
-// 	log_printf(TRACE,Commit_unit,FUNCTION,"    * val  : %d", internal_BANK_INSERT_VAL [num_bank]);
-// 	log_printf(TRACE,Commit_unit,FUNCTION,"    * full : %d", bank_full [num_bank]);
-
-        // Scan all insert interface to find a valid transaction
-	while (it!=select_insert ->end())
-	  {
-	    uint32_t num_rename_unit = it->grp;
-	    uint32_t num_inst_insert = it->elt;
-
-	    it++;
-
- 	    log_printf(TRACE,Commit_unit,FUNCTION,"  * INSERT [%d][%d]", num_rename_unit,num_inst_insert);
-//  	    log_printf(TRACE,Commit_unit,FUNCTION,"    * INSERT_VAL        : %d", PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert]));
- 	    log_printf(TRACE,Commit_unit,FUNCTION,"    * can_rename_select : %d", can_rename_select [num_rename_unit]);
-
-	    // Test if have instruction
-            //   -> rename_unit_glue test the in-order insert !!!!!
-	    if (can_rename_select [num_rename_unit] // and 
-// 		PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert])
-                )
-	      {
-                log_printf(TRACE,Commit_unit,FUNCTION,"      * have instruction");
-                log_printf(TRACE,Commit_unit,FUNCTION,"      * bank_full : %d",bank_full [num_bank]);
-
-		// test if bank is not busy (full or previous access)
-		if (not bank_full [num_bank])
-		  {
-		    // find !!!
-		    insert_ack       [num_rename_unit][num_inst_insert] = true;
-
-		    Tpacket_t packet_id = ((num_bank << _param->_shift_num_bank) | reg_BANK_PTR [num_bank]);
-
+        std::list<generic::priority::select_t> * select_insert = _priority_insert ->select(); // same select for all insert
+        std::list<generic::priority::select_t>::iterator it=select_insert ->begin();
+        
+        // Scan all bank ...
+        for (uint32_t i=0; i<_param->_nb_bank; i++)
+          {
+            // compute the bank number (num_bank_tail is the older write slot)
+            uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank;
+      
+//          log_printf(TRACE,Commit_unit,FUNCTION,"  * BANK : %d", num_bank);
+//     	    log_printf(TRACE,Commit_unit,FUNCTION,"    * val  : %d", internal_BANK_INSERT_VAL [num_bank]);
+//     	    log_printf(TRACE,Commit_unit,FUNCTION,"    * full : %d", bank_full [num_bank]);
+      
+            // Scan all insert interface to find a valid transaction
+            while (it!=select_insert ->end())
+              {
+                uint32_t num_rename_unit = it->grp;
+                uint32_t num_inst_insert = it->elt;
+      
+                it++;
+      
+                log_printf(TRACE,Commit_unit,FUNCTION,"  * INSERT [%d][%d]", num_rename_unit,num_inst_insert);
+//      	    log_printf(TRACE,Commit_unit,FUNCTION,"    * INSERT_VAL        : %d", PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert]));
+                log_printf(TRACE,Commit_unit,FUNCTION,"    * can_rename_select : %d", can_rename_select [num_rename_unit]);
+      
+                // Test if have instruction
+                //   -> rename_unit_glue test the in-order insert !!!!!
+                if (can_rename_select [num_rename_unit] // and 
+//     		PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert])
+                    )
+                  {
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * have instruction");
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * bank_full : %d",bank_full [num_bank]);
+                    
+                    // test if bank is not busy (full or previous access)
+                    if (not bank_full [num_bank])
+                      {
+                        // find !!!
+                        insert_ack       [num_rename_unit][num_inst_insert] = true;
+                        
+                        Tpacket_t packet_id = ((num_bank << _param->_shift_num_bank) | reg_BANK_PTR [num_bank]);
+                        
 #ifdef SYSTEMC_VHDL_COMPATIBILITY
-		    insert_packet_id [num_rename_unit][num_inst_insert] = packet_id;
+                        insert_packet_id [num_rename_unit][num_inst_insert] = packet_id;
 #else
-		    if (_param->_have_port_rob_ptr  )
-		    PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id);
+                        if (_param->_have_port_rob_ptr  )
+                        PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id);
 #endif
-		    internal_BANK_INSERT_VAL             [num_bank] = true;
-		    internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit;
-		    internal_BANK_INSERT_NUM_INST        [num_bank] = num_inst_insert;
-		    
-		    break;
-		  }
-	      }
+                        internal_BANK_INSERT_VAL             [num_bank] = true;
+                        internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit;
+                        internal_BANK_INSERT_NUM_INST        [num_bank] = num_inst_insert;
+                        
+                        break;
+                      }
+                  }
 		
-	    // is a valid instruction, but it's not send at a bank
-	    //  ... invalid this rename_unit (because, insert in_order)
-	    can_rename_select [num_rename_unit] = false;
-	  }
+                // is a valid instruction, but it's not send at a bank
+                //  ... invalid this rename_unit (because, insert in_order)
+                can_rename_select [num_rename_unit] = false;
+              }
+          }
       }
     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 112)
@@ -76,102 +76,101 @@
 		PORT_READ(in_RETIRE_ACK [x][y])) // not busy
 	      {
-		rob_state_t state = entry->state;
-		
-		if ((state == ROB_END_OK         ) or 
-		    (state == ROB_END_KO         ) or 
-		    (state == ROB_END_BRANCH_MISS) or 
-		    (state == ROB_END_LOAD_MISS  ) or 
-		    (state == ROB_END_MISS       )//  or 
-// 		    (state == ROB_END_EXCEPTION)
-		    )
-		  {
-		    Tcontext_t         front_end_id   = entry->front_end_id;
-		    Tcontext_t         context_id     = entry->context_id;  
-		    Tcontrol_t         write_re       = entry->write_re;
-		    Tspecial_address_t num_reg_re_log = entry->num_reg_re_log;
-
-		    // if state is ok, when write flags in the SR regsiters
-		    bool spr_write_ack = true;
-
-                    // Write in SR the good flag
-		    if ((state == ROB_END_OK  ) and write_re)
-                      // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE
-		      {
-			spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]);
-
-			// retire_ack is set !!!
-			spr_write_val       [front_end_id][context_id] = 1;
-
-			Tspecial_data_t flags = entry->flags;
-
-			switch (num_reg_re_log)
-			  {
-			  case SPR_LOGIC_SR_F     : 
-			    {
-			      spr_write_sr_f_val  [front_end_id][context_id] = 1;
-			      spr_write_sr_f      [front_end_id][context_id] = (flags & FLAG_F )!=0;
-
-			      break;
-			    }
-			  case SPR_LOGIC_SR_CY_OV :
-			    {
-			      spr_write_sr_cy_val [front_end_id][context_id] = 1;
-			      spr_write_sr_ov_val [front_end_id][context_id] = 1;	
-			      spr_write_sr_cy     [front_end_id][context_id] = (flags & FLAG_CY)!=0;
-			      spr_write_sr_ov     [front_end_id][context_id] = (flags & FLAG_OV)!=0;
-			
-			      break;
-			    }
-			  default : 
-			    {
+		rob_state_t state        = entry->state;
+                  if ((state == ROB_END_OK         ) or 
+                      (state == ROB_END_KO         ) or 
+                      (state == ROB_END_BRANCH_MISS) or 
+                      (state == ROB_END_LOAD_MISS  ) or 
+                      (state == ROB_END_MISS       )//  or 
+// 		      (state == ROB_END_EXCEPTION)
+                      )
+                    {
+                      Tcontrol_t         write_re       = entry->write_re;
+                      Tspecial_address_t num_reg_re_log = entry->num_reg_re_log;
+                      Tcontext_t         front_end_id   = entry->front_end_id;
+                      Tcontext_t         context_id     = entry->context_id;  
+                      
+                      // if state is ok, when write flags in the SR regsiters
+                      bool spr_write_ack = true;
+                      
+                      // Write in SR the good flag
+                      if ((state == ROB_END_OK  ) and write_re)
+                        // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE
+                        {
+                          spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]);
+                          
+                          // retire_ack is set !!!
+                          spr_write_val       [front_end_id][context_id] = 1;
+                          
+                          Tspecial_data_t flags = entry->flags;
+                          
+                          switch (num_reg_re_log)
+                            {
+                            case SPR_LOGIC_SR_F     : 
+                              {
+                                spr_write_sr_f_val  [front_end_id][context_id] = 1;
+                                spr_write_sr_f      [front_end_id][context_id] = (flags & FLAG_F )!=0;
+                                
+                                break;
+                              }
+                            case SPR_LOGIC_SR_CY_OV :
+                              {
+                                spr_write_sr_cy_val [front_end_id][context_id] = 1;
+                                spr_write_sr_ov_val [front_end_id][context_id] = 1;	
+                                spr_write_sr_cy     [front_end_id][context_id] = (flags & FLAG_CY)!=0;
+                                spr_write_sr_ov     [front_end_id][context_id] = (flags & FLAG_OV)!=0;
+                                
+                                break;
+                              }
+                            default : 
+                              {
 #ifdef DEBUG_TEST
-			      throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n"));
+                                throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n"));
 #endif
-			    }
-			  }
-		      }
-
-		    // find an instruction can be retire, and in order
-
-		    if (spr_write_ack)
-		      {
-			retire_val [x][y] = 1;
-			num_inst_retire [x] ++;
-			internal_BANK_RETIRE_VAL [num_bank] = true;
-		      }
-
-		    internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x;
-		    internal_BANK_RETIRE_NUM_INST        [num_bank] = y;
-
-		    if (_param->_have_port_front_end_id)
-		    PORT_WRITE(out_RETIRE_FRONT_END_ID          [x][y], front_end_id                );
-		    if (_param->_have_port_context_id)
-		    PORT_WRITE(out_RETIRE_CONTEXT_ID            [x][y], context_id                  );
-// 		    PORT_WRITE(out_RETIRE_RENAME_UNIT_ID        [x][y], entry->rename_unit_id       );
-		    PORT_WRITE(out_RETIRE_USE_STORE_QUEUE       [x][y], entry->use_store_queue      );
-		    PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE        [x][y], entry->use_load_queue       );
-		    PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write);
-		    if (_param->_have_port_load_queue_ptr)
-		    PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE  [x][y], entry->load_queue_ptr_write );
-		    PORT_WRITE(out_RETIRE_READ_RA               [x][y], entry->read_ra              );
-		    PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY        [x][y], entry->num_reg_ra_phy       );
-		    PORT_WRITE(out_RETIRE_READ_RB               [x][y], entry->read_rb              );
-		    PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY        [x][y], entry->num_reg_rb_phy       );
-		    PORT_WRITE(out_RETIRE_READ_RC               [x][y], entry->read_rc              );
-		    PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY        [x][y], entry->num_reg_rc_phy       );
-		    PORT_WRITE(out_RETIRE_WRITE_RD              [x][y], entry->write_rd             );
-		    PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG        [x][y], entry->num_reg_rd_log       );
-		    PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD    [x][y], entry->num_reg_rd_phy_old   );
-		    PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW    [x][y], entry->num_reg_rd_phy_new   );
-		    PORT_WRITE(out_RETIRE_WRITE_RE              [x][y], write_re                    );
-		    PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG        [x][y], num_reg_re_log              );
-		    PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD    [x][y], entry->num_reg_re_phy_old   );
-		    PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW    [x][y], entry->num_reg_re_phy_new   );
-
-                    // Event -> rob must be manage this event
-                    if ((state == ROB_END_BRANCH_MISS) or
-                        (state == ROB_END_LOAD_MISS))
-                      can_retire [x] = false;
-		  }
+                              }
+                            }
+                        }
+                      
+                      // find an instruction can be retire, and in order
+                      
+                      if (spr_write_ack)
+                        {
+                          retire_val [x][y] = 1;
+                          num_inst_retire [x] ++;
+                          internal_BANK_RETIRE_VAL [num_bank] = true;
+                        }
+                      
+                      internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x;
+                      internal_BANK_RETIRE_NUM_INST        [num_bank] = y;
+                      
+                      if (_param->_have_port_front_end_id)
+                      PORT_WRITE(out_RETIRE_FRONT_END_ID          [x][y], front_end_id                );
+                      if (_param->_have_port_context_id)
+                      PORT_WRITE(out_RETIRE_CONTEXT_ID            [x][y], context_id                  );
+// 		      PORT_WRITE(out_RETIRE_RENAME_UNIT_ID        [x][y], entry->rename_unit_id       );
+                      PORT_WRITE(out_RETIRE_USE_STORE_QUEUE       [x][y], entry->use_store_queue      );
+                      PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE        [x][y], entry->use_load_queue       );
+                      PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write);
+                      if (_param->_have_port_load_queue_ptr)
+		      PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE  [x][y], entry->load_queue_ptr_write );
+                      PORT_WRITE(out_RETIRE_READ_RA               [x][y], entry->read_ra              );
+                      PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY        [x][y], entry->num_reg_ra_phy       );
+                      PORT_WRITE(out_RETIRE_READ_RB               [x][y], entry->read_rb              );
+                      PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY        [x][y], entry->num_reg_rb_phy       );
+                      PORT_WRITE(out_RETIRE_READ_RC               [x][y], entry->read_rc              );
+                      PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY        [x][y], entry->num_reg_rc_phy       );
+                      PORT_WRITE(out_RETIRE_WRITE_RD              [x][y], entry->write_rd             );
+                      PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG        [x][y], entry->num_reg_rd_log       );
+                      PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD    [x][y], entry->num_reg_rd_phy_old   );
+                      PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW    [x][y], entry->num_reg_rd_phy_new   );
+                      PORT_WRITE(out_RETIRE_WRITE_RE              [x][y], write_re                    );
+                      PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG        [x][y], num_reg_re_log              );
+                      PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD    [x][y], entry->num_reg_re_phy_old   );
+                      PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW    [x][y], entry->num_reg_re_phy_new   );
+
+                      // Event -> rob must be manage this event
+                      if ((state == ROB_END_BRANCH_MISS) or
+                          (state == ROB_END_LOAD_MISS))
+                        can_retire [x] = false;
+                    }
 	      }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 112)
@@ -49,4 +49,5 @@
               reg_EVENT_STATE           [i][j] = EVENT_STATE_NO_EVENT;
               reg_EVENT_FLUSH           [i][j] = false;
+              reg_EVENT_STOP            [i][j] = false;
 
 //            reg_PC_PREVIOUS           [i][j] = (0x100-4)>>2;
@@ -90,4 +91,5 @@
                       reg_EVENT_STATE [i][j] = EVENT_STATE_END;
                       reg_EVENT_FLUSH [i][j] = false;
+                      //reg_EVENT_STOP  [i][j] = false;
                     }
                   break;
@@ -324,5 +326,5 @@
                       case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;}
                         // Store KO
-                      case ROB_MISS_WAIT_END   : {state = ROB_END_KO_SPECULATIVE; break;}
+                      case ROB_EVENT_WAIT_END  : {state = ROB_END_KO_SPECULATIVE; break;}
                         // Store OK, Load and other instruction
                       case ROB_OTHER_WAIT_END  : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_LOAD_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE); break;}
@@ -333,4 +335,8 @@
                         }
                       }
+
+                    if ((have_exception or have_miss_speculation) and
+                        (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0))
+                      reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true;
 
 		    // update Re Order Buffer
@@ -364,4 +370,5 @@
                 
                 log_printf(TRACE,Commit_unit,FUNCTION,"  * RETIRE            [%d][%d]",x,y);
+                log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank     : %d",num_bank     );
                 
 #ifdef DEBUG_TEST
@@ -381,4 +388,5 @@
                 log_printf(TRACE,Commit_unit,FUNCTION,"    * front_end_id : %d",front_end_id );
                 log_printf(TRACE,Commit_unit,FUNCTION,"    * context_id   : %d",context_id   );
+                log_printf(TRACE,Commit_unit,FUNCTION,"    * rob_ptr      : %d",((num_bank << _param->_shift_num_bank) | entry->ptr));
                 log_printf(TRACE,Commit_unit,FUNCTION,"    * num_thread   : %d",num_thread   );
                 log_printf(TRACE,Commit_unit,FUNCTION,"    * type         : %s",toString(type).c_str());
@@ -406,11 +414,12 @@
 //                     throw ERRORMORPHEO(FUNCTION,toString(_("Retire : Instruction's address_next (%.8x) is different of commit_unit's address_next (%.8x)"),entry->address_next,reg_PC_NEXT [front_end_id][context_id]));
                   }
-                
+
                 if ((state == ROB_END_BRANCH_MISS) or
                     (state == ROB_END_LOAD_MISS))
-                  {
-                    reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT;
-                    reg_EVENT_FLUSH [front_end_id][context_id] = true;
-                  }
+                    {
+                      reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT;
+                      reg_EVENT_FLUSH [front_end_id][context_id] = true;
+                      reg_EVENT_STOP  [front_end_id][context_id] = false;
+                    }
                 
 #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true)
@@ -475,5 +484,5 @@
 	      {
 	      case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; }
-	      case ROB_STORE_HEAD_KO : {state = ROB_MISS_WAIT_END ; break; }
+	      case ROB_STORE_HEAD_KO : {state = ROB_EVENT_WAIT_END; break; }
 	      default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));}
 	      }
@@ -500,6 +509,12 @@
 		throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n"));
 #endif
-
-              entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE;
+              Tcontrol_t miss = PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]);
+              
+              entry->state = (miss)?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE;
+              
+              if (miss and (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0))
+                reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true;
+
+
 //               entry->state = ROB_END_OK_SPECULATIVE;
 	    }
@@ -612,25 +627,25 @@
 		  switch (state)
 		    {
-		    case ROB_BRANCH_WAIT_END             : {state = ROB_MISS_WAIT_END; break;}
-		    case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS     ; break;}
+		    case ROB_BRANCH_WAIT_END             : {state = ROB_EVENT_WAIT_END; break;}
+		    case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS      ; break;}
                     case ROB_END_BRANCH_MISS             :
-                    case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS     ; break;}
+                    case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS      ; break;}
                     case ROB_END_LOAD_MISS_UPDATE        :
                     case ROB_END_LOAD_MISS               :
-                    case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_MISS     ; break;}
-		    case ROB_STORE_WAIT_HEAD_OK          : {state = ROB_STORE_HEAD_KO; break;}
+                    case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_MISS      ; break;}
+		    case ROB_STORE_WAIT_HEAD_OK          : {state = ROB_STORE_HEAD_KO ; break;}
 		  //case ROB_STORE_WAIT_HEAD_KO          : {state = ; break;}
-		    case ROB_OTHER_WAIT_END              : {state = ROB_MISS_WAIT_END; break;}
+		    case ROB_OTHER_WAIT_END              : {state = ROB_EVENT_WAIT_END; break;}
 		    case ROB_END_OK                      :
-		    case ROB_END_OK_SPECULATIVE          : {state = ROB_END_MISS     ; break;}
+		    case ROB_END_OK_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
 		    case ROB_END_KO                      :
-		    case ROB_END_KO_SPECULATIVE          : {state = ROB_END_MISS     ; break;}
+		    case ROB_END_KO_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
 		    case ROB_END_EXCEPTION_UPDATE        :
 		    case ROB_END_EXCEPTION               :
-		    case ROB_END_EXCEPTION_WAIT_HEAD     : {state = ROB_END_MISS     ; break;}
+		    case ROB_END_EXCEPTION_WAIT_HEAD     : {state = ROB_END_MISS      ; break;}
 		                                         
 		      // don't change                    
 		    case ROB_STORE_HEAD_KO               : {break;}
-		    case ROB_MISS_WAIT_END               : {break;}
+		    case ROB_EVENT_WAIT_END              : {break;}
 		    case ROB_END_MISS                    : {break;}
 		                                         
@@ -671,5 +686,5 @@
 		    case ROB_STORE_WAIT_HEAD_OK      : {state = ROB_STORE_HEAD_OK;        break;}
 		    case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;}
-		    default : {break;} // else, no change
+                    default : {break;} // else, no change
 		    }
 		}
@@ -701,4 +716,5 @@
             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STATE  : %s",toString(reg_EVENT_STATE [i][j]).c_str());
             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_FLUSH  : %d",reg_EVENT_FLUSH [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STOP   : %d",reg_EVENT_STOP  [i][j]);
             log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_ALL  : %d",reg_NB_INST_COMMIT_ALL[i][j]);
             log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_MEM  : %d",reg_NB_INST_COMMIT_MEM[i][j]);
@@ -784,5 +800,5 @@
 //            or (entry->state == ROB_STORE_HEAD_KO              )
 //            or (entry->state == ROB_OTHER_WAIT_END             )
-//            or (entry->state == ROB_MISS_WAIT_END              )
+//            or (entry->state == ROB_EVENT_WAIT_END             )
 //            or (entry->state == ROB_END_OK_SPECULATIVE         )
               or (entry->state == ROB_END_OK                     )
