Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_allocation.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_allocation.cpp	(revision 112)
@@ -52,5 +52,5 @@
     // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("icache_req",WEST,OUT,_("Request to instruction cache"),_nb_icache_port);
+      ALLOC1_INTERFACE_BEGIN("icache_req",WEST,OUT,_("Request to instruction cache"),_nb_icache_port);
 
       ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL         ,behavioural::VAL);
@@ -60,9 +60,11 @@
       ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS     ,"address"  ,Ticache_address_t    ,_size_icache_address  );
       ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE        ,"type"     ,Ticache_type_t       ,_size_icache_type     );
+
+      ALLOC1_INTERFACE_END(_nb_icache_port);
     }
 
     // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port);
+      ALLOC1_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port);
       
       ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL         ,behavioural::VAL);
@@ -71,14 +73,18 @@
       ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID   ,"packet_id"  ,Ticache_packet_t     ,_size_icache_packet_id);
       ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR       ,"error"      ,Ticache_error_t      ,_size_icache_error);
-    }
-    {
-      ALLOC2_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port,_icache_nb_instruction[it1]);
+
+      ALLOC1_INTERFACE_END(_nb_icache_port);
+    }
+    {
+      ALLOC2_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port,_icache_nb_instruction[it1]);
       
       _ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_size_icache_instruction,_nb_icache_port,_icache_nb_instruction[it1]);
+
+      ALLOC2_INTERFACE_END(_nb_icache_port,_icache_nb_instruction[it1]);
     }
 
     // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("dcache_req", OUT, NORTH, _("Request to data cache"),_nb_dcache_port);
+      ALLOC1_INTERFACE_BEGIN("dcache_req", OUT, NORTH, _("Request to data cache"),_nb_dcache_port);
       
       ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL         ,behavioural::VAL);
@@ -89,9 +95,11 @@
       ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA       ,"wdata"    ,Tdcache_data_t       ,_size_dcache_data);
       ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE        ,"type"     ,Tdcache_type_t       ,_size_dcache_type);
+
+      ALLOC1_INTERFACE_END(_nb_dcache_port);
     }
 									    
     // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~  
     {
-      ALLOC1_INTERFACE("dcache_rsp", IN , NORTH, _("Respons from data cache"),_nb_dcache_port);
+      ALLOC1_INTERFACE_BEGIN("dcache_rsp", IN , NORTH, _("Respons from data cache"),_nb_dcache_port);
 
       ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL         ,behavioural::VAL);
@@ -101,11 +109,15 @@
       ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA       ,"rdata"    ,Tdcache_data_t       ,_size_dcache_data);
       ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR       ,"error"    ,Tdcache_error_t      ,_size_dcache_error);
+
+      ALLOC1_INTERFACE_END(_nb_dcache_port);
     }
 
     // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("interrupt", IN , NORTH, _("Interruption line"),_nb_thread);
+      ALLOC1_INTERFACE_BEGIN("interrupt", IN , NORTH, _("Interruption line"),_nb_thread);
 
       ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE      ,"enable",Tcontrol_t           ,1);
+
+      ALLOC1_INTERFACE_END(_nb_thread);
     }
 
Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_configuration.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_configuration.cpp	(revision 111)
+++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_configuration.cpp	(revision 112)
@@ -72,5 +72,5 @@
        param->_nb_reg_free                                   ,
        param->_nb_rename_unit_bank                           ,
-       param->_size_read_counter                             ,
+//        param->_size_read_counter                             ,
 
        param->_nb_read_bloc                                  ,
