Index: trunk/IPs/systemC/Environment/src/Environment.cpp =================================================================== --- trunk/IPs/systemC/Environment/src/Environment.cpp (revision 111) +++ trunk/IPs/systemC/Environment/src/Environment.cpp (revision 112) @@ -325,4 +325,5 @@ delete [] DCACHE_RSP_ERROR ; + delete [] context_stop; delete [] write_dram; delete [] read_dram [0]; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameters.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameters.h (revision 112) @@ -53,5 +53,5 @@ public : uint32_t * _nb_reg_free ;//[nb_rename_bloc] public : uint32_t * _nb_rename_unit_bank ;//[nb_rename_bloc] - public : uint32_t * _size_read_counter ;//[nb_rename_bloc] +// public : uint32_t * _size_read_counter ;//[nb_rename_bloc] // Read bloc Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_header.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_header.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_header.cpp (revision 112) @@ -59,4 +59,5 @@ str += toString(MSG_INFORMATION)+_(" Kamel Chekkal - VHDL\n" ); str += toString(MSG_INFORMATION)+_(" Stéphane Dubuisson - XMLLight\n"); + str += toString(MSG_INFORMATION)+_(" Ramsis Farhat - VHDL\n" ); str += toString(MSG_INFORMATION)+_(" Vincent Moulu - VHDL\n" ); str += toString(MSG_INFORMATION)+"\n"; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance.cpp (revision 112) @@ -150,5 +150,5 @@ DELETE1(_param->_size_reservation_station ,_param->_nb_read_bloc); DELETE1(_param->_size_read_queue ,_param->_nb_read_bloc); - DELETE1(_param->_size_read_counter ,_param->_nb_rename_bloc); +// DELETE1(_param->_size_read_counter ,_param->_nb_rename_bloc); DELETE1(_param->_nb_rename_unit_bank ,_param->_nb_rename_bloc); DELETE1(_param->_nb_reg_free ,_param->_nb_rename_bloc); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp (revision 112) @@ -113,5 +113,5 @@ ALLOC1(_param->_nb_reg_free ,uint32_t ,_param->_nb_rename_bloc); ALLOC1(_param->_nb_rename_unit_bank ,uint32_t ,_param->_nb_rename_bloc); - ALLOC1(_param->_size_read_counter ,uint32_t ,_param->_nb_rename_bloc); +// ALLOC1(_param->_size_read_counter ,uint32_t ,_param->_nb_rename_bloc); for (uint32_t i=0; i<_param->_nb_rename_bloc; ++i) @@ -128,5 +128,5 @@ _param->_nb_reg_free [i] = fromString (getParam("nb_reg_free" , "rename_bloc",toString(i).c_str(),"")); _param->_nb_rename_unit_bank [i] = fromString (getParam("nb_rename_unit_bank" , "rename_bloc",toString(i).c_str(),"")); - _param->_size_read_counter [i] = fromString (getParam("size_read_counter" , "rename_bloc",toString(i).c_str(),"")); +// _param->_size_read_counter [i] = fromString (getParam("size_read_counter" , "rename_bloc",toString(i).c_str(),"")); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_fromFile.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_fromFile.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_fromFile.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Configuration/include/Simulator.h" +#include "Behavioural/include/Simulation.h" #include "Common/include/FromString.h" #include @@ -80,4 +81,14 @@ testNodeName (xml,"component"); testSingleton (xml,true); + + attributes_t attributes = xml->getAttributes(); + + std::string value_name = getAttribute(xml,attributes,"name" ); + model_type_t value_model = fromString(getAttribute(xml,attributes,"model")); + debug_verbosity_t value_debug = fromString(getAttribute(xml,attributes,"debug")); + + testAttributesEmpty(xml,attributes); + + _model.set_model(value_name, value_model, value_debug); } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp (revision 112) @@ -56,12 +56,14 @@ // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("rename",SOUTH,OUT,_("Request between the decod unit and the rename unit"),_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_INTERFACE_BEGIN("rename",SOUTH,OUT,_("Request between the decod unit and the rename unit"),_param->_nb_front_end,_param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_OUT(out_RENAME_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_inst_decod[it1]); } // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("branch_complete_front_end",SOUTH,OUT,_("Branch complete : request between commit unit and prediction unit"),_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + ALLOC2_INTERFACE_BEGIN("branch_complete_front_end",SOUTH,OUT,_("Branch complete : request between commit unit and prediction unit"),_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_FRONT_END_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); @@ -72,7 +74,10 @@ _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ,"MISS_PREDICTION" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); - } - { - ALLOC2_INTERFACE("branch_complete_ooo_engine",SOUTH,IN ,_("Branch complete : request between commit unit and prediction unit"),_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + + } + { + ALLOC2_INTERFACE_BEGIN("branch_complete_ooo_engine",SOUTH,IN ,_("Branch complete : request between commit unit and prediction unit"),_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_OOO_ENGINE_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); @@ -84,9 +89,11 @@ _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,"MISS_PREDICTION" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); - } + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); +} // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("commit_event_front_end",SOUTH,OUT,_("Commit event : request between commit unit and context state"),_param->_nb_front_end); + ALLOC1_INTERFACE_BEGIN("commit_event_front_end",SOUTH,OUT,_("Commit event : request between commit unit and context state"),_param->_nb_front_end); ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_VAL ,"VAL" ,Tcontrol_t ,1); @@ -101,8 +108,10 @@ ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data); - } - - { - ALLOC1_INTERFACE("commit_event_ooo_engine",SOUTH,IN ,_("Commit event : request between commit unit and context state"),_param->_nb_ooo_engine); + + ALLOC1_INTERFACE_END(_param->_nb_front_end); + } + + { + ALLOC1_INTERFACE_BEGIN("commit_event_ooo_engine",SOUTH,IN ,_("Commit event : request between commit unit and context state"),_param->_nb_ooo_engine); ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_VAL ,"VAL" ,Tcontrol_t ,1); @@ -118,9 +127,11 @@ ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data); + + ALLOC1_INTERFACE_END(_param->_nb_ooo_engine); } // ~~~~~[ Interface : "issue" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("issue_ooo_engine",SOUTH,IN ,_("Issue : request between rename unit and execute loop"),_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_INTERFACE_BEGIN("issue_ooo_engine",SOUTH,IN ,_("Issue : request between rename unit and execute loop"),_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); @@ -145,8 +156,10 @@ _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); - } - - { - ALLOC2_INTERFACE("issue_execute_loop",SOUTH,OUT,_("Issue : request between rename unit and execute loop"),_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + } + + { + ALLOC2_INTERFACE_BEGIN("issue_execute_loop",SOUTH,OUT,_("Issue : request between rename unit and execute loop"),_param->_nb_execute_loop,_param->_nb_read_unit[it1]); _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); @@ -172,9 +185,11 @@ _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_execute_loop,_param->_nb_read_unit[it1]); } // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC3_INTERFACE("execute_ooo_engine",SOUTH,OUT,_("Execute : request between execute loop and commit unit"),_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + ALLOC3_INTERFACE_BEGIN("execute_ooo_engine",SOUTH,OUT,_("Execute : request between execute loop and commit unit"),_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); @@ -190,8 +205,10 @@ _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_DATA ,"DATA" ,Tgeneral_data_t ,_param->_size_general_data,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); - } - - { - ALLOC2_INTERFACE("execute_execute_loop",SOUTH,IN ,_("Execute : request between execute loop and commit unit"),_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + + ALLOC3_INTERFACE_END(_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + } + + { + ALLOC2_INTERFACE_BEGIN("execute_execute_loop",SOUTH,IN ,_("Execute : request between execute loop and commit unit"),_param->_nb_execute_loop,_param->_nb_write_unit[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); @@ -208,9 +225,11 @@ _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_DATA ,"DATA" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_execute_loop,_param->_nb_write_unit[it1]); } // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("insert_ooo_engine",SOUTH,IN ,_("Insert"),_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + ALLOC2_INTERFACE_BEGIN("insert_ooo_engine",SOUTH,IN ,_("Insert"),_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); _ALLOC2_SIGNAL_IN ( in_INSERT_OOO_ENGINE_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); @@ -220,8 +239,10 @@ _ALLOC2_SIGNAL_IN ( in_INSERT_OOO_ENGINE_RE_USE ,"RE_USE" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); _ALLOC2_SIGNAL_IN ( in_INSERT_OOO_ENGINE_RE_NUM_REG,"RE_NUM_REG",Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); - } - - { - ALLOC3_INTERFACE("insert_execute_loop",SOUTH,IN ,_("Insert"),_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + } + + { + ALLOC3_INTERFACE_BEGIN("insert_execute_loop",SOUTH,IN ,_("Insert"),_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); _ALLOC3_SIGNAL_OUT(out_INSERT_EXECUTE_LOOP_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); @@ -231,4 +252,6 @@ _ALLOC3_SIGNAL_OUT(out_INSERT_EXECUTE_LOOP_RE_USE ,"RE_USE" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); _ALLOC3_SIGNAL_OUT(out_INSERT_EXECUTE_LOOP_RE_NUM_REG,"RE_NUM_REG",Tspecial_address_t,_param->_size_special_register,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + + ALLOC3_INTERFACE_END(_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_allocation.cpp (revision 112) @@ -56,5 +56,5 @@ // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("dcache_req", OUT, NORTH, _("Request to data cache"),_param->_nb_dcache_port); + ALLOC1_INTERFACE_BEGIN("dcache_req", OUT, NORTH, _("Request to data cache"),_param->_nb_dcache_port); ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,VAL); @@ -65,9 +65,11 @@ ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_data); ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type); + + ALLOC1_INTERFACE_END(param->_nb_dcache_port); } // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("dcache_rsp", IN , NORTH, _("Respons from data cache"),_param->_nb_dcache_port); + ALLOC1_INTERFACE_BEGIN("dcache_rsp", IN , NORTH, _("Respons from data cache"),_param->_nb_dcache_port); ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,VAL); @@ -77,9 +79,11 @@ ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_data); ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t ,_param->_size_dcache_error); + + ALLOC1_INTERFACE_END(_param->_nb_dcache_port); } // ~~~~~[ Interface "lsq_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC3_INTERFACE("lsq_req", IN, SOUTH, _("Request from load_store queue"), _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + ALLOC3_INTERFACE_BEGIN("lsq_req", IN, SOUTH, _("Request from load_store queue"), _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); _ALLOC3_VALACK_IN ( in_LSQ_REQ_VAL ,VAL, _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); @@ -90,9 +94,11 @@ _ALLOC3_SIGNAL_IN ( in_LSQ_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_data , _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); _ALLOC3_SIGNAL_IN ( in_LSQ_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type , _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + + ALLOC3_INTERFACE_END(_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); } // ~~~~~[ Interface "lsq_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC3_INTERFACE("lsq_rsp",OUT, SOUTH, _("Respons to load_store queue"), _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + ALLOC3_INTERFACE_BEGIN("lsq_rsp",OUT, SOUTH, _("Respons to load_store queue"), _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); _ALLOC3_VALACK_OUT(out_LSQ_RSP_VAL ,VAL, _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); @@ -102,4 +108,6 @@ _ALLOC3_SIGNAL_OUT(out_LSQ_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_data , _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); _ALLOC3_SIGNAL_OUT(out_LSQ_RSP_ERROR ,"error" ,Tdcache_error_t ,_param->_size_dcache_error , _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + + ALLOC3_INTERFACE_END(_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); } @@ -108,6 +116,6 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - _internal_DCACHE_REQ_NB_ACCESS = new uint32_t [_param->_nb_dcache_port]; - _internal_DCACHE_REQ_NB_ACCESS_CONFLIT = new uint32_t [_param->_nb_dcache_port]; + ALLOC1(_internal_DCACHE_REQ_NB_ACCESS ,uint32_t,_param->_nb_dcache_port); + ALLOC1(_internal_DCACHE_REQ_NB_ACCESS_CONFLIT,uint32_t,_param->_nb_dcache_port); } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_deallocation.cpp (revision 112) @@ -58,6 +58,6 @@ // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef STATISTICS - delete [] _internal_DCACHE_REQ_NB_ACCESS ; - delete [] _internal_DCACHE_REQ_NB_ACCESS_CONFLIT; + DELETE1(_internal_DCACHE_REQ_NB_ACCESS ,_param->_nb_dcache_port); + DELETE1(_internal_DCACHE_REQ_NB_ACCESS_CONFLIT,_param->_nb_dcache_port); #endif } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/test.cpp (revision 112) @@ -119,6 +119,6 @@ if (_param->_have_port_packet_id [i][j]) { - INSTANCE_SC_SIGNAL(_Icache_Access, in_CONTEXT_REQ_PACKET_ID [i][j]); - INSTANCE_SC_SIGNAL(_Icache_Access,out_CONTEXT_RSP_PACKET_ID [i][j]); + INSTANCE0_SC_SIGNAL(_Icache_Access, in_CONTEXT_REQ_PACKET_ID [i][j]); + INSTANCE0_SC_SIGNAL(_Icache_Access,out_CONTEXT_RSP_PACKET_ID [i][j]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_allocation.cpp (revision 112) @@ -56,5 +56,5 @@ // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("icache_req",WEST,OUT,_("Request to instruction cache"),_param->_nb_icache_port); + ALLOC1_INTERFACE_BEGIN("icache_req",WEST,OUT,_("Request to instruction cache"),_param->_nb_icache_port); ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL); @@ -64,9 +64,11 @@ ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_address_t ,_param->_size_address ); ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type ); + + ALLOC1_INTERFACE_END(_param->_nb_icache_port); } // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port); + ALLOC1_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port); ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); @@ -75,15 +77,18 @@ ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_icache_packet_id); ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error ); + + ALLOC1_INTERFACE_END(_param->_nb_icache_port); } { - // NOTE : max_nb_instruction is too wide ... - ALLOC2_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + ALLOC2_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); _ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_param->_size_instruction,_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); } // ~~~~~[ Interface "context_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("context_req",EAST,IN ,_("Request from context_unit."),_param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("context_req",EAST,IN ,_("Request from context_unit."),_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_VALACK_IN ( in_CONTEXT_REQ_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); @@ -93,9 +98,11 @@ _ALLOC2_SIGNAL_IN ( in_CONTEXT_REQ_ADDRESS ,"address" ,Ticache_address_t ,_param->_size_address ,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_CONTEXT_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type ,_param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } // ~~~~~[ Interface "context_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("context_rsp",EAST,OUT,_("Respons to context_unit."),_param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("context_rsp",EAST,OUT,_("Respons to context_unit."),_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_VALACK_OUT(out_CONTEXT_RSP_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); @@ -104,9 +111,13 @@ _ALLOC2_SIGNAL_OUT(out_CONTEXT_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id[it1][it2],_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_OUT(out_CONTEXT_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error ,_param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } { - ALLOC3_INTERFACE("context_rsp",EAST,OUT,_("Respons to context_unit."),_param->_nb_front_end, _param->_nb_context[it1],_param->_nb_instruction[it1][it2]); + ALLOC3_INTERFACE_BEGIN("context_rsp",EAST,OUT,_("Respons to context_unit."),_param->_nb_front_end, _param->_nb_context[it1],_param->_nb_instruction[it1][it2]); _ALLOC3_SIGNAL_OUT(out_CONTEXT_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction,_param->_nb_front_end, _param->_nb_context[it1],_param->_nb_instruction[it1][it2]); + + ALLOC3_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1],_param->_nb_instruction[it1][it2]); } @@ -115,6 +126,6 @@ // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef STATISTICS - _internal_ICACHE_REQ_NB_ACCESS = new uint32_t [_param->_nb_icache_port]; - _internal_ICACHE_REQ_NB_ACCESS_CONFLIT = new uint32_t [_param->_nb_icache_port]; + ALLOC1(_internal_ICACHE_REQ_NB_ACCESS ,uint32_t,_param->_nb_icache_port); + ALLOC1(_internal_ICACHE_REQ_NB_ACCESS_CONFLIT,uint32_t,_param->_nb_icache_port); #endif } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_deallocation.cpp (revision 112) @@ -56,6 +56,6 @@ // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef STATISTICS - delete [] _internal_ICACHE_REQ_NB_ACCESS ; - delete [] _internal_ICACHE_REQ_NB_ACCESS_CONFLIT; + DELETE1(_internal_ICACHE_REQ_NB_ACCESS ,_param->_nb_icache_port); + DELETE1(_internal_ICACHE_REQ_NB_ACCESS_CONFLIT,_param->_nb_icache_port); #endif } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_allocation.cpp (revision 112) @@ -58,5 +58,5 @@ // -----[ Interface "gpr_write_write_unit" ]-------------------------- { - ALLOC1_INTERFACE("gpr_write_write_unit", IN, EAST, _("General register write (from write_unit)"), _param->_nb_gpr_write); + ALLOC1_INTERFACE_BEGIN("gpr_write_write_unit", IN, EAST, _("General register write (from write_unit)"), _param->_nb_gpr_write); ALLOC1_VALACK_IN ( in_GPR_WRITE_WRITE_UNIT_VAL ,VAL); @@ -65,9 +65,11 @@ ALLOC1_SIGNAL_IN ( in_GPR_WRITE_WRITE_UNIT_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); ALLOC1_SIGNAL_IN ( in_GPR_WRITE_WRITE_UNIT_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_write); } // -----[ Interface "gpr_write_register_file" ]----------------------- { - ALLOC1_INTERFACE("gpr_write_register_file",OUT,SOUTH, _("General register write (to register file)"), _param->_nb_gpr_write); + ALLOC1_INTERFACE_BEGIN("gpr_write_register_file",OUT,SOUTH, _("General register write (to register file)"), _param->_nb_gpr_write); ALLOC1_VALACK_OUT(out_GPR_WRITE_REGISTER_FILE_VAL ,VAL); @@ -76,9 +78,11 @@ ALLOC1_SIGNAL_OUT(out_GPR_WRITE_REGISTER_FILE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); ALLOC1_SIGNAL_OUT(out_GPR_WRITE_REGISTER_FILE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_write); } // -----[ Interface "gpr_write_read_unit" ]--------------------------- { - ALLOC1_INTERFACE("gpr_write_read_unit",OUT,SOUTH, _("General register write (to read unit)"), _param->_nb_gpr_write); + ALLOC1_INTERFACE_BEGIN("gpr_write_read_unit",OUT,SOUTH, _("General register write (to read unit)"), _param->_nb_gpr_write); ALLOC1_VALACK_OUT(out_GPR_WRITE_READ_UNIT_VAL ,VAL); @@ -86,9 +90,11 @@ ALLOC1_SIGNAL_OUT(out_GPR_WRITE_READ_UNIT_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); ALLOC1_SIGNAL_OUT(out_GPR_WRITE_READ_UNIT_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_write); } // -----[ Interface "spr_write_write_unit" ]-------------------------- { - ALLOC1_INTERFACE("spr_write_write_unit", IN, EAST, _("Special register write (from write_unit)"), _param->_nb_spr_write); + ALLOC1_INTERFACE_BEGIN("spr_write_write_unit", IN, EAST, _("Special register write (from write_unit)"), _param->_nb_spr_write); ALLOC1_VALACK_IN ( in_SPR_WRITE_WRITE_UNIT_VAL ,VAL); @@ -97,9 +103,11 @@ ALLOC1_SIGNAL_IN ( in_SPR_WRITE_WRITE_UNIT_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); ALLOC1_SIGNAL_IN ( in_SPR_WRITE_WRITE_UNIT_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data); + + ALLOC1_INTERFACE_END(_param->_nb_spr_write); } // -----[ Interface "spr_write_register_file" ]----------------------- { - ALLOC1_INTERFACE("spr_write_register_file",OUT,SOUTH, _("Special register write (to register file)"), _param->_nb_spr_write); + ALLOC1_INTERFACE_BEGIN("spr_write_register_file",OUT,SOUTH, _("Special register write (to register file)"), _param->_nb_spr_write); ALLOC1_VALACK_OUT(out_SPR_WRITE_REGISTER_FILE_VAL ,VAL); @@ -108,9 +116,11 @@ ALLOC1_SIGNAL_OUT(out_SPR_WRITE_REGISTER_FILE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); ALLOC1_SIGNAL_OUT(out_SPR_WRITE_REGISTER_FILE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data); + + ALLOC1_INTERFACE_END(_param->_nb_spr_write); } // -----[ Interface "spr_write_read_unit" ]--------------------------- { - ALLOC1_INTERFACE("spr_write_read_unit",OUT,SOUTH, _("Special register write (to read unit)"), _param->_nb_spr_write); + ALLOC1_INTERFACE_BEGIN("spr_write_read_unit",OUT,SOUTH, _("Special register write (to read unit)"), _param->_nb_spr_write); ALLOC1_VALACK_OUT(out_SPR_WRITE_READ_UNIT_VAL ,VAL); @@ -118,4 +128,6 @@ ALLOC1_SIGNAL_OUT(out_SPR_WRITE_READ_UNIT_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); ALLOC1_SIGNAL_OUT(out_SPR_WRITE_READ_UNIT_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data); + + ALLOC1_INTERFACE_END(_param->_nb_spr_write); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -50,69 +51,52 @@ // ~~~~~[ Interface : "execute_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - { - Interface_fifo * interface = _interfaces->set_interface("execute_in" -#ifdef POSITION - ,IN - ,WEST, - "Input of Functionnal Unit" -#endif - ); - - in_EXECUTE_IN_VAL = interface->set_signal_valack_in (VAL); - out_EXECUTE_IN_ACK = interface->set_signal_valack_out (ACK); - if (_param->_have_port_context_id) - in_EXECUTE_IN_CONTEXT_ID = interface->set_signal_in ("context_id" , _param->_size_context_id ); - if (_param->_have_port_front_end_id) - in_EXECUTE_IN_FRONT_END_ID = interface->set_signal_in ("front_end_id" , _param->_size_front_end_id ); - if (_param->_have_port_ooo_engine_id) - in_EXECUTE_IN_OOO_ENGINE_ID = interface->set_signal_in ("ooo_engine_id", _param->_size_ooo_engine_id); - if (_param->_have_port_rob_ptr) - in_EXECUTE_IN_PACKET_ID = interface->set_signal_in ("packet_id" , _param->_size_rob_ptr ); - in_EXECUTE_IN_OPERATION = interface->set_signal_in ("operation" , _param->_size_operation ); - in_EXECUTE_IN_TYPE = interface->set_signal_in ("type" , _param->_size_type ); - in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in ("store_queue_ptr_write",_param->_size_store_queue_ptr); - if (_param->_have_port_load_queue_ptr) - in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in ("load_queue_ptr_write" ,_param->_size_load_queue_ptr); - in_EXECUTE_IN_HAS_IMMEDIAT = interface->set_signal_in ("has_immediat" , 1); - in_EXECUTE_IN_IMMEDIAT = interface->set_signal_in ("immediat" , _param->_size_general_data); - in_EXECUTE_IN_DATA_RA = interface->set_signal_in ("data_ra" , _param->_size_general_data); - in_EXECUTE_IN_DATA_RB = interface->set_signal_in ("data_rb" , _param->_size_general_data); - in_EXECUTE_IN_DATA_RC = interface->set_signal_in ("data_rc" , _param->_size_special_data); - in_EXECUTE_IN_WRITE_RD = interface->set_signal_in ("write_rd" , 1); - in_EXECUTE_IN_NUM_REG_RD = interface->set_signal_in ("num_reg_rd" , _param->_size_general_register); - in_EXECUTE_IN_WRITE_RE = interface->set_signal_in ("write_re" , 1); - in_EXECUTE_IN_NUM_REG_RE = interface->set_signal_in ("num_reg_re" , _param->_size_special_register); + { + ALLOC0_INTERFACE_BEGIN("execute_in",IN,WEST,"Input of Functionnal Unit"); + + ALLOC0_VALACK_IN ( in_EXECUTE_IN_VAL ,VAL); + ALLOC0_VALACK_OUT(out_EXECUTE_IN_ACK ,ACK); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_CONTEXT_ID ,"context_id" ,Tcontext_t , _param->_size_context_id ); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t , _param->_size_front_end_id ); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t , _param->_size_ooo_engine_id); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_PACKET_ID ,"packet_id" ,Tpacket_t , _param->_size_rob_ptr ); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_OPERATION ,"operation" ,Toperation_t , _param->_size_operation ); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_TYPE ,"type" ,Ttype_t , _param->_size_type ); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE ,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t , 1); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t , _param->_size_general_data); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_DATA_RA ,"data_ra" ,Tgeneral_data_t , _param->_size_general_data); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_DATA_RB ,"data_rb" ,Tgeneral_data_t , _param->_size_general_data); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_DATA_RC ,"data_rc" ,Tspecial_data_t , _param->_size_special_data); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_WRITE_RD ,"write_rd" ,Tcontrol_t , 1); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t, _param->_size_general_register); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_WRITE_RE ,"write_re" ,Tcontrol_t , 1); + ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t, _param->_size_special_register); + + ALLOC0_INTERFACE_END(); } // ~~~~~[ Interface : "execute_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - Interface_fifo * interface = _interfaces->set_interface("execute_out" -#ifdef POSITION - ,IN - ,EAST, - "Output of Functionnal Unit" -#endif - ); - - out_EXECUTE_OUT_VAL = interface->set_signal_valack_out (VAL); - in_EXECUTE_OUT_ACK = interface->set_signal_valack_in (ACK); - if (_param->_have_port_context_id) - out_EXECUTE_OUT_CONTEXT_ID = interface->set_signal_out ("context_id" ,_param->_size_context_id ); - if (_param->_have_port_front_end_id) - out_EXECUTE_OUT_FRONT_END_ID = interface->set_signal_out ("front_end_id" ,_param->_size_front_end_id ); - if (_param->_have_port_ooo_engine_id) - out_EXECUTE_OUT_OOO_ENGINE_ID = interface->set_signal_out ("ooo_engine_id",_param->_size_ooo_engine_id); - if (_param->_have_port_rob_ptr) - out_EXECUTE_OUT_PACKET_ID = interface->set_signal_out ("packet_id" ,_param->_size_rob_ptr ); - //out_EXECUTE_OUT_OPERATION = interface->set_signal_out ("operation" ,_param->_size_operation ); - //out_EXECUTE_OUT_TYPE = interface->set_signal_out ("type" ,_param->_size_type ); - out_EXECUTE_OUT_WRITE_RD = interface->set_signal_out ("write_rd" ,1); - out_EXECUTE_OUT_NUM_REG_RD = interface->set_signal_out ("num_reg_rd" ,_param->_size_general_register); - out_EXECUTE_OUT_DATA_RD = interface->set_signal_out ("data_rd" ,_param->_size_general_data); - out_EXECUTE_OUT_WRITE_RE = interface->set_signal_out ("write_re" ,1); - out_EXECUTE_OUT_NUM_REG_RE = interface->set_signal_out ("num_reg_re" ,_param->_size_special_register); - out_EXECUTE_OUT_DATA_RE = interface->set_signal_out ("data_re" ,_param->_size_special_data); - out_EXECUTE_OUT_EXCEPTION = interface->set_signal_out ("exception" ,_param->_size_exception); - out_EXECUTE_OUT_NO_SEQUENCE = interface->set_signal_out ("no_sequence" ,1); - out_EXECUTE_OUT_ADDRESS = interface->set_signal_out ("address" ,_param->_size_instruction_address); + ALLOC0_INTERFACE_BEGIN("execute_out",IN,EAST,"Output of Functionnal Unit"); + + ALLOC0_VALACK_OUT(out_EXECUTE_OUT_VAL ,VAL); + ALLOC0_VALACK_IN ( in_EXECUTE_OUT_ACK ,ACK); + ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); + //ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + //ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data); + ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); + ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data); + ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception); + ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_OUT(out_EXECUTE_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + + ALLOC0_INTERFACE_END(); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -29,50 +30,41 @@ delete in_NRESET; - delete in_EXECUTE_IN_VAL ; - delete out_EXECUTE_IN_ACK ; - if (_param->_have_port_context_id) - delete in_EXECUTE_IN_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete in_EXECUTE_IN_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete in_EXECUTE_IN_OOO_ENGINE_ID ; - if (_param->_have_port_rob_ptr) - delete in_EXECUTE_IN_PACKET_ID ; - delete in_EXECUTE_IN_OPERATION ; - delete in_EXECUTE_IN_TYPE ; - delete in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE; - if (_param->_have_port_load_queue_ptr) - delete in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE ; - delete in_EXECUTE_IN_HAS_IMMEDIAT ; - delete in_EXECUTE_IN_IMMEDIAT ; - delete in_EXECUTE_IN_DATA_RA ; - delete in_EXECUTE_IN_DATA_RB ; - delete in_EXECUTE_IN_DATA_RC ; - delete in_EXECUTE_IN_WRITE_RD ; - delete in_EXECUTE_IN_NUM_REG_RD ; - delete in_EXECUTE_IN_WRITE_RE ; - delete in_EXECUTE_IN_NUM_REG_RE ; + DELETE0_SIGNAL( in_EXECUTE_IN_VAL ,1); + DELETE0_SIGNAL(out_EXECUTE_IN_ACK ,1); + DELETE0_SIGNAL( in_EXECUTE_IN_CONTEXT_ID , _param->_size_context_id ); + DELETE0_SIGNAL( in_EXECUTE_IN_FRONT_END_ID , _param->_size_front_end_id ); + DELETE0_SIGNAL( in_EXECUTE_IN_OOO_ENGINE_ID , _param->_size_ooo_engine_id); + DELETE0_SIGNAL( in_EXECUTE_IN_PACKET_ID , _param->_size_rob_ptr ); + DELETE0_SIGNAL( in_EXECUTE_IN_OPERATION , _param->_size_operation ); + DELETE0_SIGNAL( in_EXECUTE_IN_TYPE , _param->_size_type ); + DELETE0_SIGNAL( in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE ,_param->_size_store_queue_ptr); + DELETE0_SIGNAL( in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE ,_param->_size_load_queue_ptr); + DELETE0_SIGNAL( in_EXECUTE_IN_HAS_IMMEDIAT , 1); + DELETE0_SIGNAL( in_EXECUTE_IN_IMMEDIAT , _param->_size_general_data); + DELETE0_SIGNAL( in_EXECUTE_IN_DATA_RA , _param->_size_general_data); + DELETE0_SIGNAL( in_EXECUTE_IN_DATA_RB , _param->_size_general_data); + DELETE0_SIGNAL( in_EXECUTE_IN_DATA_RC , _param->_size_special_data); + DELETE0_SIGNAL( in_EXECUTE_IN_WRITE_RD , 1); + DELETE0_SIGNAL( in_EXECUTE_IN_NUM_REG_RD , _param->_size_general_register); + DELETE0_SIGNAL( in_EXECUTE_IN_WRITE_RE , 1); + DELETE0_SIGNAL( in_EXECUTE_IN_NUM_REG_RE , _param->_size_special_register); - delete out_EXECUTE_OUT_VAL ; - delete in_EXECUTE_OUT_ACK ; - if (_param->_have_port_context_id) - delete out_EXECUTE_OUT_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete out_EXECUTE_OUT_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete out_EXECUTE_OUT_OOO_ENGINE_ID ; - if (_param->_have_port_rob_ptr) - delete out_EXECUTE_OUT_PACKET_ID ; -// delete out_EXECUTE_OUT_OPERATION ; -// delete out_EXECUTE_OUT_TYPE ; - delete out_EXECUTE_OUT_WRITE_RD ; - delete out_EXECUTE_OUT_NUM_REG_RD ; - delete out_EXECUTE_OUT_DATA_RD ; - delete out_EXECUTE_OUT_WRITE_RE ; - delete out_EXECUTE_OUT_NUM_REG_RE ; - delete out_EXECUTE_OUT_DATA_RE ; - delete out_EXECUTE_OUT_EXCEPTION ; - delete out_EXECUTE_OUT_NO_SEQUENCE ; - delete out_EXECUTE_OUT_ADDRESS ; + DELETE0_SIGNAL(out_EXECUTE_OUT_VAL ,1); + DELETE0_SIGNAL( in_EXECUTE_OUT_ACK ,1); + DELETE0_SIGNAL(out_EXECUTE_OUT_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL(out_EXECUTE_OUT_FRONT_END_ID ,_param->_size_front_end_id ); + DELETE0_SIGNAL(out_EXECUTE_OUT_OOO_ENGINE_ID ,_param->_size_ooo_engine_id); + DELETE0_SIGNAL(out_EXECUTE_OUT_PACKET_ID ,_param->_size_rob_ptr ); + //DELETE0_SIGNAL(out_EXECUTE_OUT_OPERATION ,_param->_size_operation ); + //DELETE0_SIGNAL(out_EXECUTE_OUT_TYPE ,_param->_size_type ); + DELETE0_SIGNAL(out_EXECUTE_OUT_WRITE_RD ,1); + DELETE0_SIGNAL(out_EXECUTE_OUT_NUM_REG_RD ,_param->_size_general_register); + DELETE0_SIGNAL(out_EXECUTE_OUT_DATA_RD ,_param->_size_general_data); + DELETE0_SIGNAL(out_EXECUTE_OUT_WRITE_RE ,1); + DELETE0_SIGNAL(out_EXECUTE_OUT_NUM_REG_RE ,_param->_size_special_register); + DELETE0_SIGNAL(out_EXECUTE_OUT_DATA_RE ,_param->_size_special_data); + DELETE0_SIGNAL(out_EXECUTE_OUT_EXCEPTION ,_param->_size_exception); + DELETE0_SIGNAL(out_EXECUTE_OUT_NO_SEQUENCE ,1); + DELETE0_SIGNAL(out_EXECUTE_OUT_ADDRESS ,_param->_size_instruction_address); // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp (revision 112) @@ -54,5 +54,5 @@ // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("memory_in",IN,WEST,_("Instruction from Reservations station"),_param->_nb_inst_memory); + ALLOC1_INTERFACE_BEGIN("memory_in",IN,WEST,_("Instruction from Reservations station"),_param->_nb_inst_memory); ALLOC1_VALACK_IN ( in_MEMORY_IN_VAL ,VAL); @@ -75,9 +75,11 @@ ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_memory); } // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("memory_out",OUT,EAST,_("Instruction to write queue"),_param->_nb_inst_memory); + ALLOC1_INTERFACE_BEGIN("memory_out",OUT,EAST,_("Instruction to write queue"),_param->_nb_inst_memory); ALLOC1_VALACK_OUT(out_MEMORY_OUT_VAL ,VAL); @@ -98,9 +100,11 @@ ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + + ALLOC1_INTERFACE_END(_param->_nb_inst_memory); } // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("dcache_req",OUT,NORTH,_("Request port to dcache"),_param->_nb_cache_port); + ALLOC1_INTERFACE_BEGIN("dcache_req",OUT,NORTH,_("Request port to dcache"),_param->_nb_cache_port); ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,VAL); @@ -111,9 +115,11 @@ ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type ); ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_general_data); + + ALLOC1_INTERFACE_END(_param->_nb_cache_port); } // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("dcache_rsp",IN,NORTH,_("Respons port from dcache"),_param->_nb_cache_port); + ALLOC1_INTERFACE_BEGIN("dcache_rsp",IN,NORTH,_("Respons port from dcache"),_param->_nb_cache_port); ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,VAL); @@ -123,9 +129,11 @@ ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_general_data); ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t,_param->_size_dcache_error); + + ALLOC1_INTERFACE_END(_param->_nb_cache_port); } // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("bypass_memory",OUT,NORTH,_("Bypass between the load queue and the reservation station"),_param->_nb_bypass_memory); + ALLOC1_INTERFACE_BEGIN("bypass_memory",OUT,NORTH,_("Bypass between the load queue and the reservation station"),_param->_nb_bypass_memory); ALLOC1_VALACK_OUT(out_BYPASS_MEMORY_VAL ,VAL); @@ -133,4 +141,6 @@ ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t, _param->_size_general_register); ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t , _param->_size_general_data ); + + ALLOC1_INTERFACE_END(_param->_nb_bypass_memory); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (revision 112) @@ -596,6 +596,6 @@ // check find a bypass. A speculative load have been committed : report a speculation miss. - if ((_load_queue[index_load]._check_hit != 0)// and -// (_load_queue[index_load]._write_rd == 0) + if ((_load_queue[index_load]._check_hit != 0) and + (_load_queue[index_load]._write_rd == 0) // is commit ) { Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_allocation.cpp (revision 112) @@ -8,4 +8,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Read_queue.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -50,194 +51,119 @@ // ~~~~~[ Interface : "read_queue_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - Interface_fifo * interface = _interfaces->set_interface("read_queue_in" -#ifdef POSITION - ,IN - ,EAST - ,"Input of read_queue" -#endif - ); + ALLOC0_INTERFACE_BEGIN("read_queue_in",IN,EAST,"Input of read_queue"); - in_READ_QUEUE_IN_VAL = interface->set_signal_valack_in ("val" , VAL); - out_READ_QUEUE_IN_ACK = interface->set_signal_valack_out ("ack" , ACK); - if(_param->_have_port_context_id ) - in_READ_QUEUE_IN_CONTEXT_ID = interface->set_signal_in ("context_id" ,_param->_size_context_id ); - if(_param->_have_port_front_end_id) - in_READ_QUEUE_IN_FRONT_END_ID = interface->set_signal_in ("front_end_id" ,_param->_size_front_end_id ); - if(_param->_have_port_ooo_engine_id) - in_READ_QUEUE_IN_OOO_ENGINE_ID = interface->set_signal_in ("ooo_engine_id",_param->_size_ooo_engine_id ); - if(_param->_have_port_rob_ptr ) - in_READ_QUEUE_IN_ROB_ID = interface->set_signal_in ("rob_id" ,_param->_size_rob_ptr ); - in_READ_QUEUE_IN_OPERATION = interface->set_signal_in ("operation" ,_param->_size_operation ); - in_READ_QUEUE_IN_TYPE = interface->set_signal_in ("type" ,_param->_size_type ); - in_READ_QUEUE_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in ("store_queue_ptr_write", _param->_size_store_queue_ptr); - if (_param->_have_port_load_queue_ptr) - in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in ("load_queue_ptr_write" , _param->_size_load_queue_ptr); - in_READ_QUEUE_IN_HAS_IMMEDIAT = interface->set_signal_in ("has_immediat",1 ); - in_READ_QUEUE_IN_IMMEDIAT = interface->set_signal_in ("immediat" ,_param->_size_general_data ); - in_READ_QUEUE_IN_READ_RA = interface->set_signal_in ("read_ra" ,1 ); - in_READ_QUEUE_IN_NUM_REG_RA = interface->set_signal_in ("num_reg_ra" ,_param->_size_general_register ); - in_READ_QUEUE_IN_READ_RB = interface->set_signal_in ("read_rb" ,1 ); - in_READ_QUEUE_IN_NUM_REG_RB = interface->set_signal_in ("num_reg_rb" ,_param->_size_general_register ); - in_READ_QUEUE_IN_READ_RC = interface->set_signal_in ("read_rc" ,1 ); - in_READ_QUEUE_IN_NUM_REG_RC = interface->set_signal_in ("num_reg_rc" ,_param->_size_special_register ); - in_READ_QUEUE_IN_WRITE_RD = interface->set_signal_in ("write_rd" ,1 ); - in_READ_QUEUE_IN_NUM_REG_RD = interface->set_signal_in ("num_reg_rd" ,_param->_size_general_register ); - in_READ_QUEUE_IN_WRITE_RE = interface->set_signal_in ("write_re" ,1 ); - in_READ_QUEUE_IN_NUM_REG_RE = interface->set_signal_in ("num_reg_re" ,_param->_size_special_register ); - } + ALLOC0_VALACK_IN ( in_READ_QUEUE_IN_VAL ,VAL); + ALLOC0_VALACK_OUT(out_READ_QUEUE_IN_ACK ,ACK); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_ROB_ID ,"rob_id" ,Tpacket_t ,_param->_size_rob_ptr ); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); + + ALLOC0_INTERFACE_END(); + } // ~~~~~[ Interface : "read_queue_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - Interface_fifo * interface = _interfaces->set_interface("read_queue_out" -#ifdef POSITION - ,OUT - ,EAST - ,"Input of read_queue" -#endif - ); + ALLOC0_INTERFACE_BEGIN("read_queue_out",OUT,EAST,"Input of read_queue"); - out_READ_QUEUE_OUT_VAL = interface->set_signal_valack_out ("val" , VAL); - in_READ_QUEUE_OUT_ACK = interface->set_signal_valack_in ("ack" , ACK); - - if(_param->_have_port_context_id ) - out_READ_QUEUE_OUT_CONTEXT_ID = interface->set_signal_out ("context_id" ,_param->_size_context_id ); - if(_param->_have_port_front_end_id) - out_READ_QUEUE_OUT_FRONT_END_ID = interface->set_signal_out ("front_end_id" ,_param->_size_front_end_id ); - if(_param->_have_port_ooo_engine_id) - out_READ_QUEUE_OUT_OOO_ENGINE_ID = interface->set_signal_out ("ooo_engine_id",_param->_size_ooo_engine_id ); - if(_param->_have_port_rob_ptr ) - out_READ_QUEUE_OUT_ROB_ID = interface->set_signal_out ("rob_id" ,_param->_size_rob_ptr ); - out_READ_QUEUE_OUT_OPERATION = interface->set_signal_out ("operation" ,_param->_size_operation ); - out_READ_QUEUE_OUT_TYPE = interface->set_signal_out ("type" ,_param->_size_type ); - out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE = interface->set_signal_out ("store_queue_ptr_write", _param->_size_store_queue_ptr); - if (_param->_have_port_load_queue_ptr) - out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE = interface->set_signal_out ("load_queue_ptr_write" , _param->_size_load_queue_ptr); - out_READ_QUEUE_OUT_HAS_IMMEDIAT = interface->set_signal_out ("has_immediat",1 ); - out_READ_QUEUE_OUT_IMMEDIAT = interface->set_signal_out ("immediat" ,_param->_size_general_data ); -// out_READ_QUEUE_OUT_READ_RA = interface->set_signal_out ("read_ra" ,1 ); - out_READ_QUEUE_OUT_NUM_REG_RA = interface->set_signal_out ("num_reg_ra" ,_param->_size_general_register ); - out_READ_QUEUE_OUT_DATA_RA_VAL = interface->set_signal_out ("data_ra_val" ,1 ); - out_READ_QUEUE_OUT_DATA_RA = interface->set_signal_out ("data_ra" ,_param->_size_general_data ); -// out_READ_QUEUE_OUT_READ_RB = interface->set_signal_out ("read_rb" ,1 ); - out_READ_QUEUE_OUT_NUM_REG_RB = interface->set_signal_out ("num_reg_rb" ,_param->_size_general_register ); - out_READ_QUEUE_OUT_DATA_RB_VAL = interface->set_signal_out ("data_rb_val" ,1 ); - out_READ_QUEUE_OUT_DATA_RB = interface->set_signal_out ("data_rb" ,_param->_size_general_data ); -// out_READ_QUEUE_OUT_READ_RC = interface->set_signal_out ("read_rc" ,1 ); - out_READ_QUEUE_OUT_NUM_REG_RC = interface->set_signal_out ("num_reg_rc" ,_param->_size_special_register ); - out_READ_QUEUE_OUT_DATA_RC_VAL = interface->set_signal_out ("data_rc_val" ,1 ); - out_READ_QUEUE_OUT_DATA_RC = interface->set_signal_out ("data_rc" ,_param->_size_special_data ); - out_READ_QUEUE_OUT_WRITE_RD = interface->set_signal_out ("write_rd" ,1 ); - out_READ_QUEUE_OUT_NUM_REG_RD = interface->set_signal_out ("num_reg_rd" ,_param->_size_general_register ); - out_READ_QUEUE_OUT_WRITE_RE = interface->set_signal_out ("write_re" ,1 ); - out_READ_QUEUE_OUT_NUM_REG_RE = interface->set_signal_out ("num_reg_re" ,_param->_size_special_register ); - } + ALLOC0_VALACK_OUT(out_READ_QUEUE_OUT_VAL ,VAL); + ALLOC0_VALACK_IN ( in_READ_QUEUE_OUT_ACK ,ACK); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_ROB_ID ,"rob_id" ,Tpacket_t ,_param->_size_rob_ptr ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE ,"store_queue_ptr_write",Tlsq_ptr_t , _param->_size_store_queue_ptr ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t , _param->_size_load_queue_ptr ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); +// ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_DATA_RA_VAL ,"data_ra_val" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data ); +// ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_DATA_RB_VAL ,"data_rb_val" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data ); +// ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_DATA_RC_VAL ,"data_rc_val" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); + + ALLOC0_INTERFACE_END(); + } // ~~~~~[ Interface : "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("gpr_read",IN,SOUTH,_("Interface with the General RegisterFile"),_param->_nb_gpr_read); + + ALLOC1_VALACK_OUT(out_GPR_READ_VAL ,VAL); + ALLOC1_VALACK_IN ( in_GPR_READ_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_GPR_READ_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_OUT(out_GPR_READ_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_GPR_READ_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + ALLOC1_SIGNAL_IN ( in_GPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_read); + } - out_GPR_READ_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_read]; - in_GPR_READ_ACK = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_read]; - if(_param->_have_port_ooo_engine_id) - out_GPR_READ_OOO_ENGINE_ID= new SC_OUT(Tcontext_t ) * [_param->_nb_gpr_read]; - out_GPR_READ_NUM_REG = new SC_OUT(Tgeneral_address_t) * [_param->_nb_gpr_read]; - in_GPR_READ_DATA = new SC_IN (Tgeneral_data_t ) * [_param->_nb_gpr_read]; - in_GPR_READ_DATA_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_read]; + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("spr_read",IN,SOUTH,_("Interface with the General RegisterFile"),_param->_nb_spr_read); - for (uint32_t i=0; i<_param->_nb_gpr_read; i++) - { - Interface_fifo * interface = _interfaces->set_interface("gpr_read_"+toString(i) -#ifdef POSITION - , IN - ,SOUTH - , "Interface with the General RegisterFile." -#endif - ); + ALLOC1_VALACK_OUT(out_SPR_READ_VAL ,VAL); + ALLOC1_VALACK_IN ( in_SPR_READ_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_SPR_READ_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_OUT(out_SPR_READ_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_SPR_READ_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + ALLOC1_SIGNAL_IN ( in_SPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t ,1); - out_GPR_READ_VAL [i] = interface->set_signal_valack_out ("val" , VAL); - in_GPR_READ_ACK [i] = interface->set_signal_valack_in ("ack" , ACK); - if(_param->_have_port_ooo_engine_id) - out_GPR_READ_OOO_ENGINE_ID [i] = interface->set_signal_out ("ooo_engine_id",_param->_size_ooo_engine_id); - out_GPR_READ_NUM_REG [i] = interface->set_signal_out ("num_reg" ,_param->_size_general_register); - in_GPR_READ_DATA [i] = interface->set_signal_in ("data" ,_param->_size_general_data); - in_GPR_READ_DATA_VAL [i] = interface->set_signal_in ("data_val" ,1); - } - - // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - out_SPR_READ_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_read]; - in_SPR_READ_ACK = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_read]; - if(_param->_have_port_ooo_engine_id) - out_SPR_READ_OOO_ENGINE_ID= new SC_OUT(Tcontext_t ) * [_param->_nb_spr_read]; - out_SPR_READ_NUM_REG = new SC_OUT(Tspecial_address_t) * [_param->_nb_spr_read]; - in_SPR_READ_DATA = new SC_IN (Tspecial_data_t ) * [_param->_nb_spr_read]; - in_SPR_READ_DATA_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_read]; - - for (uint32_t i=0; i<_param->_nb_spr_read; i++) - { - Interface_fifo * interface = _interfaces->set_interface("spr_read_"+toString(i) -#ifdef POSITION - , IN - ,SOUTH - , "Interface with the Special RegisterFile." -#endif - ); - - out_SPR_READ_VAL [i] = interface->set_signal_valack_out ("val" , VAL); - in_SPR_READ_ACK [i] = interface->set_signal_valack_in ("ack" , ACK); - if(_param->_have_port_ooo_engine_id) - out_SPR_READ_OOO_ENGINE_ID [i] = interface->set_signal_out ("ooo_engine_id",_param->_size_ooo_engine_id); - out_SPR_READ_NUM_REG [i] = interface->set_signal_out ("num_reg" ,_param->_size_special_register); - in_SPR_READ_DATA [i] = interface->set_signal_in ("data" ,_param->_size_special_data); - in_SPR_READ_DATA_VAL [i] = interface->set_signal_in ("data_val" ,1); - } + ALLOC1_INTERFACE_END(_param->_nb_spr_read); + } // ~~~~~[ Interface : "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - in_GPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_write]; - if(_param->_have_port_ooo_engine_id) - in_GPR_WRITE_OOO_ENGINE_ID= new SC_IN (Tcontext_t ) * [_param->_nb_gpr_write]; - in_GPR_WRITE_NUM_REG = new SC_IN (Tgeneral_address_t) * [_param->_nb_gpr_write]; - in_GPR_WRITE_DATA = new SC_IN (Tgeneral_data_t ) * [_param->_nb_gpr_write]; + { + ALLOC1_INTERFACE_BEGIN("gpr_write",IN,SOUTH,_("Interface with write queue to bypass the write in the RegisterFile"),_param->_nb_gpr_write); - for (uint32_t i=0; i<_param->_nb_gpr_write; i++) - { - Interface_fifo * interface = _interfaces->set_interface("gpr_write_"+toString(i) -#ifdef POSITION - , IN - ,SOUTH - , "Interface with write queue to bypass the write in the RegisterFile." -#endif - ); - - in_GPR_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); - if(_param->_have_port_ooo_engine_id) - in_GPR_WRITE_OOO_ENGINE_ID [i] = interface->set_signal_in ("ooo_engine_id",_param->_size_ooo_engine_id); - in_GPR_WRITE_NUM_REG [i] = interface->set_signal_in ("num_reg" ,_param->_size_general_register); - in_GPR_WRITE_DATA [i] = interface->set_signal_in ("data" ,_param->_size_general_data); - } + ALLOC1_VALACK_IN (in_GPR_WRITE_VAL ,VAL); + ALLOC1_SIGNAL_IN (in_GPR_WRITE_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_IN (in_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN (in_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_write); + } // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - in_SPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_write]; - if(_param->_have_port_ooo_engine_id) - in_SPR_WRITE_OOO_ENGINE_ID= new SC_IN (Tcontext_t ) * [_param->_nb_spr_write]; - in_SPR_WRITE_NUM_REG = new SC_IN (Tspecial_address_t) * [_param->_nb_spr_write]; - in_SPR_WRITE_DATA = new SC_IN (Tspecial_data_t ) * [_param->_nb_spr_write]; + { + ALLOC1_INTERFACE_BEGIN("spr_write",IN,SOUTH,_("Interface with write queue to bypass the write in the RegisterFile"),_param->_nb_spr_write); - for (uint32_t i=0; i<_param->_nb_spr_write; i++) - { - Interface_fifo * interface = _interfaces->set_interface("spr_write_"+toString(i) -#ifdef POSITION - , IN - ,SOUTH - , "Interface with write queue to bypass the write in the RegisterFile." -#endif - ); - - in_SPR_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); - if(_param->_have_port_ooo_engine_id) - in_SPR_WRITE_OOO_ENGINE_ID [i] = interface->set_signal_in ("ooo_engine_id",_param->_size_ooo_engine_id); - in_SPR_WRITE_NUM_REG [i] = interface->set_signal_in ("num_reg" ,_param->_size_special_register); - in_SPR_WRITE_DATA [i] = interface->set_signal_in ("data" ,_param->_size_special_data); - } + ALLOC1_VALACK_IN (in_SPR_WRITE_VAL ,VAL); + ALLOC1_SIGNAL_IN (in_SPR_WRITE_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_IN (in_SPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN (in_SPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + + ALLOC1_INTERFACE_END(_param->_nb_spr_write); + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_deallocation.cpp (revision 112) @@ -8,4 +8,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Read_queue.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -25,109 +26,82 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete in_CLOCK ; - delete in_NRESET; + delete in_CLOCK ; + delete in_NRESET; - // ~~~~~[ Interface : "read_queue_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete in_READ_QUEUE_IN_VAL ; - delete out_READ_QUEUE_IN_ACK ; + DELETE0_SIGNAL( in_READ_QUEUE_IN_VAL ,1 ); + DELETE0_SIGNAL(out_READ_QUEUE_IN_ACK ,1 ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_FRONT_END_ID ,_param->_size_front_end_id ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_OOO_ENGINE_ID ,_param->_size_ooo_engine_id ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_ROB_ID ,_param->_size_rob_ptr ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_OPERATION ,_param->_size_operation ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_TYPE ,_param->_size_type ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_STORE_QUEUE_PTR_WRITE ,_param->_size_store_queue_ptr ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE ,_param->_size_load_queue_ptr ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_HAS_IMMEDIAT ,1 ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_IMMEDIAT ,_param->_size_general_data ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_READ_RA ,1 ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_NUM_REG_RA ,_param->_size_general_register); + DELETE0_SIGNAL( in_READ_QUEUE_IN_READ_RB ,1 ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_NUM_REG_RB ,_param->_size_general_register); + DELETE0_SIGNAL( in_READ_QUEUE_IN_READ_RC ,1 ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_NUM_REG_RC ,_param->_size_special_register); + DELETE0_SIGNAL( in_READ_QUEUE_IN_WRITE_RD ,1 ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_NUM_REG_RD ,_param->_size_general_register); + DELETE0_SIGNAL( in_READ_QUEUE_IN_WRITE_RE ,1 ); + DELETE0_SIGNAL( in_READ_QUEUE_IN_NUM_REG_RE ,_param->_size_special_register); + + DELETE0_SIGNAL(out_READ_QUEUE_OUT_VAL ,1 ); + DELETE0_SIGNAL( in_READ_QUEUE_OUT_ACK ,1 ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_FRONT_END_ID ,_param->_size_front_end_id ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_OOO_ENGINE_ID ,_param->_size_ooo_engine_id ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_ROB_ID ,_param->_size_rob_ptr ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_OPERATION ,_param->_size_operation ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_TYPE ,_param->_size_type ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE, _param->_size_store_queue_ptr ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE , _param->_size_load_queue_ptr ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_HAS_IMMEDIAT ,1 ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_IMMEDIAT ,_param->_size_general_data ); +// DELETE0_SIGNAL(out_READ_QUEUE_OUT_READ_RA ,1 ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_NUM_REG_RA ,_param->_size_general_register ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_DATA_RA_VAL ,1 ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_DATA_RA ,_param->_size_general_data ); +// DELETE0_SIGNAL(out_READ_QUEUE_OUT_READ_RB ,1 ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_NUM_REG_RB ,_param->_size_general_register ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_DATA_RB_VAL ,1 ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_DATA_RB ,_param->_size_general_data ); +// DELETE0_SIGNAL(out_READ_QUEUE_OUT_READ_RC ,1 ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_NUM_REG_RC ,_param->_size_special_register ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_DATA_RC_VAL ,1 ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_DATA_RC ,_param->_size_special_data ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_WRITE_RD ,1 ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_NUM_REG_RD ,_param->_size_general_register ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_WRITE_RE ,1 ); + DELETE0_SIGNAL(out_READ_QUEUE_OUT_NUM_REG_RE ,_param->_size_special_register ); - if(_param->_have_port_context_id ) - delete in_READ_QUEUE_IN_CONTEXT_ID ; - if(_param->_have_port_front_end_id ) - delete in_READ_QUEUE_IN_FRONT_END_ID ; - if(_param->_have_port_ooo_engine_id) - delete in_READ_QUEUE_IN_OOO_ENGINE_ID ; - if(_param->_have_port_rob_ptr ) - delete in_READ_QUEUE_IN_ROB_ID ; - delete in_READ_QUEUE_IN_OPERATION ; - delete in_READ_QUEUE_IN_TYPE ; - delete in_READ_QUEUE_IN_STORE_QUEUE_PTR_WRITE; - if (_param->_have_port_load_queue_ptr) - delete in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE ; - delete in_READ_QUEUE_IN_HAS_IMMEDIAT ; - delete in_READ_QUEUE_IN_IMMEDIAT ; - delete in_READ_QUEUE_IN_READ_RA ; - delete in_READ_QUEUE_IN_NUM_REG_RA ; - delete in_READ_QUEUE_IN_READ_RB ; - delete in_READ_QUEUE_IN_NUM_REG_RB ; - delete in_READ_QUEUE_IN_READ_RC ; - delete in_READ_QUEUE_IN_NUM_REG_RC ; - delete in_READ_QUEUE_IN_WRITE_RD ; - delete in_READ_QUEUE_IN_NUM_REG_RD ; - delete in_READ_QUEUE_IN_WRITE_RE ; - delete in_READ_QUEUE_IN_NUM_REG_RE ; + DELETE1_SIGNAL(out_GPR_READ_VAL ,_param->_nb_gpr_read,1); + DELETE1_SIGNAL( in_GPR_READ_ACK ,_param->_nb_gpr_read,1); + DELETE1_SIGNAL(out_GPR_READ_OOO_ENGINE_ID ,_param->_nb_gpr_read,_param->_size_ooo_engine_id); + DELETE1_SIGNAL(out_GPR_READ_NUM_REG ,_param->_nb_gpr_read,_param->_size_general_register); + DELETE1_SIGNAL( in_GPR_READ_DATA ,_param->_nb_gpr_read,_param->_size_general_data); + DELETE1_SIGNAL( in_GPR_READ_DATA_VAL ,_param->_nb_gpr_read,1); - // ~~~~~[ Interface : "read_queue_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete out_READ_QUEUE_OUT_VAL ; - delete in_READ_QUEUE_OUT_ACK ; + DELETE1_SIGNAL(out_SPR_READ_VAL ,_param->_nb_spr_read,1); + DELETE1_SIGNAL( in_SPR_READ_ACK ,_param->_nb_spr_read,1); + DELETE1_SIGNAL(out_SPR_READ_OOO_ENGINE_ID ,_param->_nb_spr_read,_param->_size_ooo_engine_id); + DELETE1_SIGNAL(out_SPR_READ_NUM_REG ,_param->_nb_spr_read,_param->_size_general_register); + DELETE1_SIGNAL( in_SPR_READ_DATA ,_param->_nb_spr_read,_param->_size_general_data); + DELETE1_SIGNAL( in_SPR_READ_DATA_VAL ,_param->_nb_spr_read,1); + + DELETE1_SIGNAL(in_GPR_WRITE_VAL ,_param->_nb_gpr_write,1); + DELETE1_SIGNAL(in_GPR_WRITE_OOO_ENGINE_ID ,_param->_nb_gpr_write,_param->_size_ooo_engine_id); + DELETE1_SIGNAL(in_GPR_WRITE_NUM_REG ,_param->_nb_gpr_write,_param->_size_general_register); + DELETE1_SIGNAL(in_GPR_WRITE_DATA ,_param->_nb_gpr_write,_param->_size_general_data); - if(_param->_have_port_context_id ) - delete out_READ_QUEUE_OUT_CONTEXT_ID ; - if(_param->_have_port_front_end_id ) - delete out_READ_QUEUE_OUT_FRONT_END_ID ; - if(_param->_have_port_ooo_engine_id) - delete out_READ_QUEUE_OUT_OOO_ENGINE_ID ; - if(_param->_have_port_rob_ptr ) - delete out_READ_QUEUE_OUT_ROB_ID ; - delete out_READ_QUEUE_OUT_OPERATION ; - delete out_READ_QUEUE_OUT_TYPE ; - delete out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE; - if (_param->_have_port_load_queue_ptr) - delete out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE ; - delete out_READ_QUEUE_OUT_HAS_IMMEDIAT ; - delete out_READ_QUEUE_OUT_IMMEDIAT ; -// delete out_READ_QUEUE_OUT_READ_RA ; - delete out_READ_QUEUE_OUT_NUM_REG_RA ; - delete out_READ_QUEUE_OUT_DATA_RA_VAL ; - delete out_READ_QUEUE_OUT_DATA_RA ; -// delete out_READ_QUEUE_OUT_READ_RB ; - delete out_READ_QUEUE_OUT_NUM_REG_RB ; - delete out_READ_QUEUE_OUT_DATA_RB_VAL ; - delete out_READ_QUEUE_OUT_DATA_RB ; -// delete out_READ_QUEUE_OUT_READ_RC ; - delete out_READ_QUEUE_OUT_NUM_REG_RC ; - delete out_READ_QUEUE_OUT_DATA_RC_VAL ; - delete out_READ_QUEUE_OUT_DATA_RC ; - delete out_READ_QUEUE_OUT_WRITE_RD ; - delete out_READ_QUEUE_OUT_NUM_REG_RD ; - delete out_READ_QUEUE_OUT_WRITE_RE ; - delete out_READ_QUEUE_OUT_NUM_REG_RE ; - - // ~~~~~[ Interface : "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - delete [] out_GPR_READ_VAL ; - delete [] in_GPR_READ_ACK ; - if(_param->_have_port_ooo_engine_id) - delete [] out_GPR_READ_OOO_ENGINE_ID; - delete [] out_GPR_READ_NUM_REG ; - delete [] in_GPR_READ_DATA ; - delete [] in_GPR_READ_DATA_VAL ; - - // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - delete [] out_SPR_READ_VAL ; - delete [] in_SPR_READ_ACK ; - if(_param->_have_port_ooo_engine_id) - delete [] out_SPR_READ_OOO_ENGINE_ID; - delete [] out_SPR_READ_NUM_REG ; - delete [] in_SPR_READ_DATA ; - delete [] in_SPR_READ_DATA_VAL ; - - // ~~~~~[ Interface : "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - delete [] in_GPR_WRITE_VAL ; - if(_param->_have_port_ooo_engine_id) - delete [] in_GPR_WRITE_OOO_ENGINE_ID; - delete [] in_GPR_WRITE_NUM_REG ; - delete [] in_GPR_WRITE_DATA ; - - // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - delete [] in_SPR_WRITE_VAL ; - if(_param->_have_port_ooo_engine_id) - delete [] in_SPR_WRITE_OOO_ENGINE_ID; - delete [] in_SPR_WRITE_NUM_REG ; - delete [] in_SPR_WRITE_DATA ; + DELETE1_SIGNAL(in_SPR_WRITE_VAL ,_param->_nb_spr_write,1); + DELETE1_SIGNAL(in_SPR_WRITE_OOO_ENGINE_ID ,_param->_nb_spr_write,_param->_size_ooo_engine_id); + DELETE1_SIGNAL(in_SPR_WRITE_NUM_REG ,_param->_nb_spr_write,_param->_size_general_register); + DELETE1_SIGNAL(in_SPR_WRITE_DATA ,_param->_nb_spr_write,_param->_size_general_data); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp (revision 112) @@ -34,5 +34,10 @@ // > 2) flush all slot in one cycle - _queue->clear(); + while (_queue->empty() == false) + { + delete _queue->front(); + _queue->pop_front(); + } + // _queue->clear(); // Init, else error in registerfile Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/src/test.cpp (revision 112) @@ -7,5 +7,5 @@ */ #define NB_ITERATION 1 -#define CYCLE_MAX (2048*NB_ITERATION) +#define CYCLE_MAX (10000*NB_ITERATION) #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/include/test.h" Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp (revision 112) @@ -8,4 +8,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -43,5 +44,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -50,219 +51,123 @@ in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); - // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~ - { - Interface_fifo * interface = _interfaces->set_interface("insert" -#ifdef POSITION - ,IN - ,EAST - ,"Input of reservation_station" -#endif - ); - - in_INSERT_VAL = interface->set_signal_valack_in (VAL); - out_INSERT_ACK = interface->set_signal_valack_out (ACK); - if (_param->_have_port_context_id) - in_INSERT_CONTEXT_ID = interface->set_signal_in ("context_id" ,_param->_size_context_id ); - if (_param->_have_port_front_end_id) - in_INSERT_FRONT_END_ID = interface->set_signal_in ("front_end_id" ,_param->_size_front_end_id ); - if (_param->_have_port_ooo_engine_id) - in_INSERT_OOO_ENGINE_ID = interface->set_signal_in ("ooo_engine_id" ,_param->_size_ooo_engine_id ); - if (_param->_have_port_rob_ptr) - in_INSERT_ROB_ID = interface->set_signal_in ("rob_id" ,_param->_size_rob_ptr ); - in_INSERT_OPERATION = interface->set_signal_in ("operation" ,_param->_size_operation ); - in_INSERT_TYPE = interface->set_signal_in ("type" ,_param->_size_type ); - in_INSERT_STORE_QUEUE_PTR_WRITE = interface->set_signal_in ("store_queue_ptr_write" ,_param->_size_store_queue_ptr); - if (_param->_have_port_load_queue_ptr) - in_INSERT_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in ("load_queue_ptr_write" ,_param->_size_load_queue_ptr ); - in_INSERT_HAS_IMMEDIAT = interface->set_signal_in ("has_immediat" ,1 ); - in_INSERT_IMMEDIAT = interface->set_signal_in ("immediat" ,_param->_size_general_data ); -// in_INSERT_READ_RA = interface->set_signal_in ("read_ra" ,1 ); - in_INSERT_NUM_REG_RA = interface->set_signal_in ("num_reg_ra" ,_param->_size_general_register ); - in_INSERT_DATA_RA_VAL = interface->set_signal_in ("data_ra_val" ,1 ); - in_INSERT_DATA_RA = interface->set_signal_in ("data_ra" ,_param->_size_general_data ); -// in_INSERT_READ_RB = interface->set_signal_in ("read_rb" ,1 ); - in_INSERT_NUM_REG_RB = interface->set_signal_in ("num_reg_rb" ,_param->_size_general_register ); - in_INSERT_DATA_RB_VAL = interface->set_signal_in ("data_rb_val" ,1 ); - in_INSERT_DATA_RB = interface->set_signal_in ("data_rb" ,_param->_size_general_data ); -// in_INSERT_READ_RC = interface->set_signal_in ("read_rc" ,1 ); - in_INSERT_NUM_REG_RC = interface->set_signal_in ("num_reg_rc" ,_param->_size_special_register ); - in_INSERT_DATA_RC_VAL = interface->set_signal_in ("data_rc_val" ,1 ); - in_INSERT_DATA_RC = interface->set_signal_in ("data_rc" ,_param->_size_special_data ); - in_INSERT_WRITE_RD = interface->set_signal_in ("write_rd" ,1 ); - in_INSERT_NUM_REG_RD = interface->set_signal_in ("num_reg_rd" ,_param->_size_general_register ); - in_INSERT_WRITE_RE = interface->set_signal_in ("write_re" ,1 ); - in_INSERT_NUM_REG_RE = interface->set_signal_in ("num_reg_re" ,_param->_size_special_register ); + // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC0_INTERFACE_BEGIN("insert",IN,EAST,_("Input of reservation_station")); + + ALLOC0_VALACK_IN ( in_INSERT_VAL ,VAL); + ALLOC0_VALACK_OUT(out_INSERT_ACK ,ACK); + ALLOC0_SIGNAL_IN ( in_INSERT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_IN ( in_INSERT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC0_SIGNAL_IN ( in_INSERT_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); + ALLOC0_SIGNAL_IN ( in_INSERT_ROB_ID ,"rob_id" ,Tpacket_t ,_param->_size_rob_ptr ); + ALLOC0_SIGNAL_IN ( in_INSERT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC0_SIGNAL_IN ( in_INSERT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC0_SIGNAL_IN ( in_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); + ALLOC0_SIGNAL_IN ( in_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); + ALLOC0_SIGNAL_IN ( in_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_INSERT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); +// ALLOC0_SIGNAL_IN ( in_INSERT_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RA_VAL ,"data_ra_val" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data ); +// ALLOC0_SIGNAL_IN ( in_INSERT_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RB_VAL ,"data_rb_val" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data ); +// ALLOC0_SIGNAL_IN ( in_INSERT_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register); + ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RC_VAL ,"data_rc_val" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data ); + ALLOC0_SIGNAL_IN ( in_INSERT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC0_SIGNAL_IN ( in_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); + + ALLOC0_INTERFACE_END(); + } + + // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("retire",OUT,WEST,_("Output of reservation_station"),_param->_nb_inst_retire); + + ALLOC1_VALACK_OUT(out_RETIRE_VAL ,VAL); + ALLOC1_VALACK_IN ( in_RETIRE_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_RETIRE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_OUT(out_RETIRE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); + ALLOC1_SIGNAL_OUT(out_RETIRE_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_OUT(out_RETIRE_ROB_ID ,"rob_id" ,Tpacket_t ,_param->_size_rob_ptr); + ALLOC1_SIGNAL_OUT(out_RETIRE_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation); + ALLOC1_SIGNAL_OUT(out_RETIRE_TYPE ,"type" ,Ttype_t ,_param->_size_type); + ALLOC1_SIGNAL_OUT(out_RETIRE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); + ALLOC1_SIGNAL_OUT(out_RETIRE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); + ALLOC1_SIGNAL_OUT(out_RETIRE_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_RETIRE_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data); + ALLOC1_SIGNAL_OUT(out_RETIRE_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data); + ALLOC1_SIGNAL_OUT(out_RETIRE_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data); + ALLOC1_SIGNAL_OUT(out_RETIRE_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data); + ALLOC1_SIGNAL_OUT(out_RETIRE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_RETIRE_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_OUT(out_RETIRE_WRITE_RE ,"write_re" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_RETIRE_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); + + ALLOC1_INTERFACE_END(_param->_nb_inst_retire); + } + + // ~~~~~[ Interface : "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("gpr_write",IN,SOUTH,_("Interface with write queue to bypass the write in the RegisterFile."),_param->_nb_gpr_write); + + ALLOC1_VALACK_IN ( in_GPR_WRITE_VAL ,VAL); + ALLOC1_SIGNAL_IN ( in_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_IN ( in_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_write); } - // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~ - out_RETIRE_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_inst_retire]; - in_RETIRE_ACK = new SC_IN (Tcontrol_t ) * [_param->_nb_inst_retire]; - if (_param->_have_port_context_id) - out_RETIRE_CONTEXT_ID = new SC_OUT(Tcontext_t ) * [_param->_nb_inst_retire]; - if (_param->_have_port_front_end_id) - out_RETIRE_FRONT_END_ID = new SC_OUT(Tcontext_t ) * [_param->_nb_inst_retire]; - if (_param->_have_port_ooo_engine_id) - out_RETIRE_OOO_ENGINE_ID = new SC_OUT(Tcontext_t ) * [_param->_nb_inst_retire]; - if (_param->_have_port_rob_ptr) - out_RETIRE_ROB_ID = new SC_OUT(Tpacket_t ) * [_param->_nb_inst_retire]; - out_RETIRE_OPERATION = new SC_OUT(Toperation_t ) * [_param->_nb_inst_retire]; - out_RETIRE_TYPE = new SC_OUT(Ttype_t ) * [_param->_nb_inst_retire]; - out_RETIRE_STORE_QUEUE_PTR_WRITE = new SC_OUT(Tlsq_ptr_t ) * [_param->_nb_inst_retire]; - if (_param->_have_port_load_queue_ptr) - out_RETIRE_LOAD_QUEUE_PTR_WRITE = new SC_OUT(Tlsq_ptr_t ) * [_param->_nb_inst_retire]; - out_RETIRE_HAS_IMMEDIAT = new SC_OUT(Tcontrol_t ) * [_param->_nb_inst_retire]; - out_RETIRE_IMMEDIAT = new SC_OUT(Tgeneral_data_t ) * [_param->_nb_inst_retire]; - out_RETIRE_DATA_RA = new SC_OUT(Tgeneral_data_t ) * [_param->_nb_inst_retire]; - out_RETIRE_DATA_RB = new SC_OUT(Tgeneral_data_t ) * [_param->_nb_inst_retire]; - out_RETIRE_DATA_RC = new SC_OUT(Tspecial_data_t ) * [_param->_nb_inst_retire]; - out_RETIRE_WRITE_RD = new SC_OUT(Tcontrol_t ) * [_param->_nb_inst_retire]; - out_RETIRE_NUM_REG_RD = new SC_OUT(Tgeneral_address_t) * [_param->_nb_inst_retire]; - out_RETIRE_WRITE_RE = new SC_OUT(Tcontrol_t ) * [_param->_nb_inst_retire]; - out_RETIRE_NUM_REG_RE = new SC_OUT(Tspecial_address_t) * [_param->_nb_inst_retire]; - - for (uint32_t i=0; i<_param->_nb_inst_retire; i++) - { - Interface_fifo * interface = _interfaces->set_interface("retire_"+toString(i) -#ifdef POSITION - ,OUT - ,WEST - ,"Output of reservation_station" -#endif - ); - out_RETIRE_VAL [i] = interface->set_signal_valack_out(VAL); - in_RETIRE_ACK [i] = interface->set_signal_valack_in (ACK); - if (_param->_have_port_context_id) - out_RETIRE_CONTEXT_ID [i] = interface->set_signal_out ("context_id" ,_param->_size_context_id); - if (_param->_have_port_front_end_id) - out_RETIRE_FRONT_END_ID [i] = interface->set_signal_out ("front_end_id" ,_param->_size_front_end_id); - if (_param->_have_port_ooo_engine_id) - out_RETIRE_OOO_ENGINE_ID[i] = interface->set_signal_out ("ooo_engine_id",_param->_size_ooo_engine_id); - if (_param->_have_port_rob_ptr) - out_RETIRE_ROB_ID [i] = interface->set_signal_out ("rob_id" ,_param->_size_rob_ptr); - out_RETIRE_OPERATION [i] = interface->set_signal_out ("operation" ,_param->_size_operation); - out_RETIRE_TYPE [i] = interface->set_signal_out ("type" ,_param->_size_type); - out_RETIRE_STORE_QUEUE_PTR_WRITE [i] = interface->set_signal_out ("store_queue_ptr_write" ,_param->_size_store_queue_ptr); - if (_param->_have_port_load_queue_ptr) - out_RETIRE_LOAD_QUEUE_PTR_WRITE [i] = interface->set_signal_out ("load_queue_ptr_write" ,_param->_size_load_queue_ptr ); + // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("spr_write",IN,SOUTH,_("Interface with write queue to bypass the write in the RegisterFile."),_param->_nb_spr_write); + + ALLOC1_VALACK_IN ( in_SPR_WRITE_VAL ,VAL); + ALLOC1_SIGNAL_IN ( in_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_IN ( in_SPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_SPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); - out_RETIRE_HAS_IMMEDIAT [i] = interface->set_signal_out ("has_immediat" ,1); - out_RETIRE_IMMEDIAT [i] = interface->set_signal_out ("immediat" ,_param->_size_general_data); - out_RETIRE_DATA_RA [i] = interface->set_signal_out ("data_ra" ,_param->_size_general_data); - out_RETIRE_DATA_RB [i] = interface->set_signal_out ("data_rb" ,_param->_size_general_data); - out_RETIRE_DATA_RC [i] = interface->set_signal_out ("data_rc" ,_param->_size_special_data); - out_RETIRE_WRITE_RD [i] = interface->set_signal_out ("write_rd" ,1); - out_RETIRE_NUM_REG_RD [i] = interface->set_signal_out ("num_reg_rd" ,_param->_size_general_register); - out_RETIRE_WRITE_RE [i] = interface->set_signal_out ("write_re" ,1); - out_RETIRE_NUM_REG_RE [i] = interface->set_signal_out ("num_reg_re" ,_param->_size_special_register); - } + ALLOC1_INTERFACE_END(_param->_nb_spr_write); + } - // ~~~~~[ Interface : "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_GPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_write]; - if (_param->_have_port_ooo_engine_id) - in_GPR_WRITE_OOO_ENGINE_ID= new SC_IN (Tcontext_t ) * [_param->_nb_gpr_write]; - in_GPR_WRITE_NUM_REG = new SC_IN (Tgeneral_address_t) * [_param->_nb_gpr_write]; - in_GPR_WRITE_DATA = new SC_IN (Tgeneral_data_t ) * [_param->_nb_gpr_write]; + // ~~~~~[ Interface : "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("bypass_write",IN,NORTH,_("Interface with write queue to bypass the write in the RegisterFile."),_param->_nb_bypass_write); - for (uint32_t i=0; i<_param->_nb_gpr_write; i++) - { - Interface_fifo * interface = _interfaces->set_interface("gpr_write_"+toString(i) -#ifdef POSITION - , IN - ,SOUTH - , "Interface with write queue to bypass the write in the RegisterFile." -#endif - ); + ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_VAL ,"gpr_val" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_NUM_REG ,"gpr_num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_DATA ,"gpr_data" ,Tgeneral_data_t ,_param->_size_general_data); + ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_VAL ,"spr_val" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_register); + ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_data); + + ALLOC1_INTERFACE_END(_param->_nb_bypass_write); + } + + // ~~~~~[ Interface : "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("bypass_memory",IN,NORTH,_("Interface with load/store unit to bypass the write in the RegisterFile."),_param->_nb_bypass_memory); - in_GPR_WRITE_VAL [i] = interface->set_signal_valack_in (VAL); - if (_param->_have_port_ooo_engine_id) - in_GPR_WRITE_OOO_ENGINE_ID [i] = interface->set_signal_in ("ooo_engine_id",_param->_size_ooo_engine_id); - in_GPR_WRITE_NUM_REG [i] = interface->set_signal_in ("num_reg" ,_param->_size_general_register); - in_GPR_WRITE_DATA [i] = interface->set_signal_in ("data" ,_param->_size_general_data); - } - - // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_SPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_write]; - if (_param->_have_port_ooo_engine_id) - in_SPR_WRITE_OOO_ENGINE_ID= new SC_IN (Tcontext_t ) * [_param->_nb_spr_write]; - in_SPR_WRITE_NUM_REG = new SC_IN (Tspecial_address_t) * [_param->_nb_spr_write]; - in_SPR_WRITE_DATA = new SC_IN (Tspecial_data_t ) * [_param->_nb_spr_write]; - - for (uint32_t i=0; i<_param->_nb_spr_write; i++) - { - Interface_fifo * interface = _interfaces->set_interface("spr_write_"+toString(i) -#ifdef POSITION - , IN - ,SOUTH - , "Interface with write queue to bypass the write in the RegisterFile." -#endif - ); - - in_SPR_WRITE_VAL [i] = interface->set_signal_valack_in (VAL); - if (_param->_have_port_ooo_engine_id) - in_SPR_WRITE_OOO_ENGINE_ID [i] = interface->set_signal_in ("ooo_engine_id",_param->_size_ooo_engine_id); - in_SPR_WRITE_NUM_REG [i] = interface->set_signal_in ("num_reg" ,_param->_size_special_register); - in_SPR_WRITE_DATA [i] = interface->set_signal_in ("data" ,_param->_size_special_data); - } - - // ~~~~~[ Interface : "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - if (_param->_have_port_ooo_engine_id) - in_BYPASS_WRITE_OOO_ENGINE_ID = new SC_IN (Tcontext_t ) * [_param->_nb_bypass_write]; - in_BYPASS_WRITE_GPR_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_bypass_write]; - in_BYPASS_WRITE_GPR_NUM_REG = new SC_IN (Tgeneral_address_t) * [_param->_nb_bypass_write]; - in_BYPASS_WRITE_GPR_DATA = new SC_IN (Tgeneral_data_t ) * [_param->_nb_bypass_write]; - in_BYPASS_WRITE_SPR_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_bypass_write]; - in_BYPASS_WRITE_SPR_NUM_REG = new SC_IN (Tspecial_address_t) * [_param->_nb_bypass_write]; - in_BYPASS_WRITE_SPR_DATA = new SC_IN (Tspecial_data_t ) * [_param->_nb_bypass_write]; - - for (uint32_t i=0; i<_param->_nb_bypass_write; i++) - { - Interface_fifo * interface = _interfaces->set_interface("bypass_write_"+toString(i) -#ifdef POSITION - , IN - ,NORTH - , "Interface with write queue to bypass the write in the RegisterFile." -#endif - ); - - if (_param->_have_port_ooo_engine_id) - in_BYPASS_WRITE_OOO_ENGINE_ID [i] = interface->set_signal_in ("ooo_engine_id" ,_param->_size_ooo_engine_id); - in_BYPASS_WRITE_GPR_VAL [i] = interface->set_signal_valack_in ("gpr_val",VAL); - in_BYPASS_WRITE_GPR_NUM_REG [i] = interface->set_signal_in ("gpr_num_reg" ,_param->_size_general_register); - in_BYPASS_WRITE_GPR_DATA [i] = interface->set_signal_in ("gpr_data" ,_param->_size_general_data); - in_BYPASS_WRITE_SPR_VAL [i] = interface->set_signal_valack_in ("spr_val",VAL); - in_BYPASS_WRITE_SPR_NUM_REG [i] = interface->set_signal_in ("spr_num_reg" ,_param->_size_special_register); - in_BYPASS_WRITE_SPR_DATA [i] = interface->set_signal_in ("spr_data" ,_param->_size_special_data); - } - - // ~~~~~[ Interface : "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_BYPASS_MEMORY_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_bypass_memory]; - if (_param->_have_port_ooo_engine_id) - in_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_IN (Tcontext_t ) * [_param->_nb_bypass_memory]; - in_BYPASS_MEMORY_NUM_REG = new SC_IN (Tgeneral_address_t) * [_param->_nb_bypass_memory]; - in_BYPASS_MEMORY_DATA = new SC_IN (Tgeneral_data_t ) * [_param->_nb_bypass_memory]; - - for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) - { - Interface_fifo * interface = _interfaces->set_interface("bypass_memory_"+toString(i) -#ifdef POSITION - , IN - , NORTH - , "Interface with load/store unit to bypass the write in the RegisterFile." -#endif - ); - - in_BYPASS_MEMORY_VAL [i] = interface->set_signal_valack_in (VAL); - if (_param->_have_port_ooo_engine_id) - in_BYPASS_MEMORY_OOO_ENGINE_ID[i] = interface->set_signal_in ("ooo_engine_id",_param->_size_ooo_engine_id); - in_BYPASS_MEMORY_NUM_REG [i] = interface->set_signal_in ("num_reg" ,_param->_size_general_register); - in_BYPASS_MEMORY_DATA [i] = interface->set_signal_in ("data" ,_param->_size_general_data); - } - + ALLOC1_VALACK_IN ( in_BYPASS_MEMORY_VAL ,VAL); + ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + + ALLOC1_INTERFACE_END(_param->_nb_bypass_memory); + } if (usage_is_set(_usage,USE_SYSTEMC)) { // ~~~~~[ internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - internal_RETIRE_VAL = new Tcontrol_t [_param->_nb_inst_retire]; - internal_RETIRE_SLOT = new uint32_t [_param->_nb_inst_retire]; + ALLOC1(internal_RETIRE_VAL ,Tcontrol_t,_param->_nb_inst_retire); + ALLOC1(internal_RETIRE_SLOT,uint32_t ,_param->_nb_inst_retire); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_deallocation.cpp (revision 112) @@ -11,4 +11,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -30,97 +31,83 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - delete in_CLOCK ; - delete in_NRESET; + delete in_CLOCK ; + delete in_NRESET; - delete in_INSERT_VAL ; - delete out_INSERT_ACK ; - if (_param->_have_port_context_id) - delete in_INSERT_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete in_INSERT_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete in_INSERT_OOO_ENGINE_ID ; - if (_param->_have_port_rob_ptr) - delete in_INSERT_ROB_ID ; - delete in_INSERT_OPERATION ; - delete in_INSERT_TYPE ; - delete in_INSERT_STORE_QUEUE_PTR_WRITE; - if (_param->_have_port_load_queue_ptr) - delete in_INSERT_LOAD_QUEUE_PTR_WRITE ; - delete in_INSERT_HAS_IMMEDIAT ; - delete in_INSERT_IMMEDIAT ; -// delete in_INSERT_READ_RA ; - delete in_INSERT_NUM_REG_RA ; - delete in_INSERT_DATA_RA_VAL ; - delete in_INSERT_DATA_RA ; -// delete in_INSERT_READ_RB ; - delete in_INSERT_NUM_REG_RB ; - delete in_INSERT_DATA_RB_VAL ; - delete in_INSERT_DATA_RB ; -// delete in_INSERT_READ_RC ; - delete in_INSERT_NUM_REG_RC ; - delete in_INSERT_DATA_RC_VAL ; - delete in_INSERT_DATA_RC ; - delete in_INSERT_WRITE_RD ; - delete in_INSERT_NUM_REG_RD ; - delete in_INSERT_WRITE_RE ; - delete in_INSERT_NUM_REG_RE ; - - delete [] out_RETIRE_VAL ; - delete [] in_RETIRE_ACK ; - if (_param->_have_port_context_id) - delete [] out_RETIRE_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete [] out_RETIRE_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete [] out_RETIRE_OOO_ENGINE_ID ; - if (_param->_have_port_rob_ptr) - delete [] out_RETIRE_ROB_ID ; - delete [] out_RETIRE_OPERATION ; - delete [] out_RETIRE_TYPE ; - delete [] out_RETIRE_STORE_QUEUE_PTR_WRITE; - if (_param->_have_port_load_queue_ptr) - delete [] out_RETIRE_LOAD_QUEUE_PTR_WRITE ; - delete [] out_RETIRE_HAS_IMMEDIAT ; - delete [] out_RETIRE_IMMEDIAT ; - delete [] out_RETIRE_DATA_RA ; - delete [] out_RETIRE_DATA_RB ; - delete [] out_RETIRE_DATA_RC ; - delete [] out_RETIRE_WRITE_RD ; - delete [] out_RETIRE_NUM_REG_RD ; - delete [] out_RETIRE_WRITE_RE ; - delete [] out_RETIRE_NUM_REG_RE ; - - delete [] in_GPR_WRITE_VAL ; - if (_param->_have_port_ooo_engine_id) - delete [] in_GPR_WRITE_OOO_ENGINE_ID; - delete [] in_GPR_WRITE_NUM_REG ; - delete [] in_GPR_WRITE_DATA ; - - delete [] in_SPR_WRITE_VAL ; - if (_param->_have_port_ooo_engine_id) - delete [] in_SPR_WRITE_OOO_ENGINE_ID; - delete [] in_SPR_WRITE_NUM_REG ; - delete [] in_SPR_WRITE_DATA ; - - if (_param->_have_port_ooo_engine_id) - delete [] in_BYPASS_WRITE_OOO_ENGINE_ID; - delete [] in_BYPASS_WRITE_GPR_VAL ; - delete [] in_BYPASS_WRITE_GPR_NUM_REG; - delete [] in_BYPASS_WRITE_GPR_DATA ; - delete [] in_BYPASS_WRITE_SPR_VAL ; - delete [] in_BYPASS_WRITE_SPR_NUM_REG; - delete [] in_BYPASS_WRITE_SPR_DATA ; - - delete [] in_BYPASS_MEMORY_VAL ; - if (_param->_have_port_ooo_engine_id) - delete [] in_BYPASS_MEMORY_OOO_ENGINE_ID; - delete [] in_BYPASS_MEMORY_NUM_REG ; - delete [] in_BYPASS_MEMORY_DATA ; - - // ~~~~~[ internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] internal_RETIRE_VAL; - delete [] internal_RETIRE_SLOT; + DELETE0_SIGNAL( in_INSERT_VAL ,1); + DELETE0_SIGNAL(out_INSERT_ACK ,1); + DELETE0_SIGNAL( in_INSERT_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL( in_INSERT_FRONT_END_ID ,_param->_size_front_end_id ); + DELETE0_SIGNAL( in_INSERT_OOO_ENGINE_ID ,_param->_size_ooo_engine_id ); + DELETE0_SIGNAL( in_INSERT_ROB_ID ,_param->_size_rob_ptr ); + DELETE0_SIGNAL( in_INSERT_OPERATION ,_param->_size_operation ); + DELETE0_SIGNAL( in_INSERT_TYPE ,_param->_size_type ); + DELETE0_SIGNAL( in_INSERT_STORE_QUEUE_PTR_WRITE,_param->_size_store_queue_ptr ); + DELETE0_SIGNAL( in_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_size_load_queue_ptr ); + DELETE0_SIGNAL( in_INSERT_HAS_IMMEDIAT ,1 ); + DELETE0_SIGNAL( in_INSERT_IMMEDIAT ,_param->_size_general_data ); +// DELETE0_SIGNAL( in_INSERT_READ_RA ,1 ); + DELETE0_SIGNAL( in_INSERT_NUM_REG_RA ,_param->_size_general_register); + DELETE0_SIGNAL( in_INSERT_DATA_RA_VAL ,1 ); + DELETE0_SIGNAL( in_INSERT_DATA_RA ,_param->_size_general_data ); +// DELETE0_SIGNAL( in_INSERT_READ_RB ,1 ); + DELETE0_SIGNAL( in_INSERT_NUM_REG_RB ,_param->_size_general_register); + DELETE0_SIGNAL( in_INSERT_DATA_RB_VAL ,1 ); + DELETE0_SIGNAL( in_INSERT_DATA_RB ,_param->_size_general_data ); +// DELETE0_SIGNAL( in_INSERT_READ_RC ,1 ); + DELETE0_SIGNAL( in_INSERT_NUM_REG_RC ,_param->_size_special_register); + DELETE0_SIGNAL( in_INSERT_DATA_RC_VAL ,1 ); + DELETE0_SIGNAL( in_INSERT_DATA_RC ,_param->_size_special_data ); + DELETE0_SIGNAL( in_INSERT_WRITE_RD ,1 ); + DELETE0_SIGNAL( in_INSERT_NUM_REG_RD ,_param->_size_general_register); + DELETE0_SIGNAL( in_INSERT_WRITE_RE ,1 ); + DELETE0_SIGNAL( in_INSERT_NUM_REG_RE ,_param->_size_special_register); + + DELETE1_SIGNAL(out_RETIRE_VAL ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_RETIRE_ACK ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_CONTEXT_ID ,_param->_nb_inst_retire,_param->_size_context_id); + DELETE1_SIGNAL(out_RETIRE_FRONT_END_ID ,_param->_nb_inst_retire,_param->_size_front_end_id); + DELETE1_SIGNAL(out_RETIRE_OOO_ENGINE_ID ,_param->_nb_inst_retire,_param->_size_ooo_engine_id); + DELETE1_SIGNAL(out_RETIRE_ROB_ID ,_param->_nb_inst_retire,_param->_size_rob_ptr); + DELETE1_SIGNAL(out_RETIRE_OPERATION ,_param->_nb_inst_retire,_param->_size_operation); + DELETE1_SIGNAL(out_RETIRE_TYPE ,_param->_nb_inst_retire,_param->_size_type); + DELETE1_SIGNAL(out_RETIRE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire,_param->_size_store_queue_ptr); + DELETE1_SIGNAL(out_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire,_param->_size_load_queue_ptr ); + DELETE1_SIGNAL(out_RETIRE_HAS_IMMEDIAT ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_IMMEDIAT ,_param->_nb_inst_retire,_param->_size_general_data); + DELETE1_SIGNAL(out_RETIRE_DATA_RA ,_param->_nb_inst_retire,_param->_size_general_data); + DELETE1_SIGNAL(out_RETIRE_DATA_RB ,_param->_nb_inst_retire,_param->_size_general_data); + DELETE1_SIGNAL(out_RETIRE_DATA_RC ,_param->_nb_inst_retire,_param->_size_special_data); + DELETE1_SIGNAL(out_RETIRE_WRITE_RD ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_NUM_REG_RD ,_param->_nb_inst_retire,_param->_size_general_register); + DELETE1_SIGNAL(out_RETIRE_WRITE_RE ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_NUM_REG_RE ,_param->_nb_inst_retire,_param->_size_special_register); + + DELETE1_SIGNAL( in_GPR_WRITE_VAL ,_param->_nb_gpr_write,1); + DELETE1_SIGNAL( in_GPR_WRITE_OOO_ENGINE_ID,_param->_nb_gpr_write,_param->_size_ooo_engine_id); + DELETE1_SIGNAL( in_GPR_WRITE_NUM_REG ,_param->_nb_gpr_write,_param->_size_general_register); + DELETE1_SIGNAL( in_GPR_WRITE_DATA ,_param->_nb_gpr_write,_param->_size_general_data); + + DELETE1_SIGNAL( in_SPR_WRITE_VAL ,_param->_nb_spr_write,1); + DELETE1_SIGNAL( in_SPR_WRITE_OOO_ENGINE_ID,_param->_nb_spr_write,_param->_size_ooo_engine_id); + DELETE1_SIGNAL( in_SPR_WRITE_NUM_REG ,_param->_nb_spr_write,_param->_size_general_register); + DELETE1_SIGNAL( in_SPR_WRITE_DATA ,_param->_nb_spr_write,_param->_size_general_data); + + DELETE1_SIGNAL( in_BYPASS_WRITE_OOO_ENGINE_ID,_param->_nb_bypass_write,_param->_size_ooo_engine_id); + DELETE1_SIGNAL( in_BYPASS_WRITE_GPR_VAL ,_param->_nb_bypass_write,1); + DELETE1_SIGNAL( in_BYPASS_WRITE_GPR_NUM_REG ,_param->_nb_bypass_write,_param->_size_general_register); + DELETE1_SIGNAL( in_BYPASS_WRITE_GPR_DATA ,_param->_nb_bypass_write,_param->_size_general_data); + DELETE1_SIGNAL( in_BYPASS_WRITE_SPR_VAL ,_param->_nb_bypass_write,1); + DELETE1_SIGNAL( in_BYPASS_WRITE_SPR_NUM_REG ,_param->_nb_bypass_write,_param->_size_special_register); + DELETE1_SIGNAL( in_BYPASS_WRITE_SPR_DATA ,_param->_nb_bypass_write,_param->_size_special_data); + + DELETE1_SIGNAL( in_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory,1); + DELETE1_SIGNAL( in_BYPASS_MEMORY_OOO_ENGINE_ID,_param->_nb_bypass_memory,_param->_size_ooo_engine_id); + DELETE1_SIGNAL( in_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory,_param->_size_general_register); + DELETE1_SIGNAL( in_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory,_param->_size_general_data); + + DELETE1(internal_RETIRE_VAL ,_param->_nb_inst_retire); + DELETE1(internal_RETIRE_SLOT,_param->_nb_inst_retire); } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/test.cpp (revision 112) @@ -64,26 +64,26 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_VAL ," in_READ_UNIT_IN_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_READ_UNIT_IN_ACK ,"out_READ_UNIT_IN_ACK ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_CONTEXT_ID ," in_READ_UNIT_IN_CONTEXT_ID ",Tcontext_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_FRONT_END_ID ," in_READ_UNIT_IN_FRONT_END_ID ",Tcontext_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_OOO_ENGINE_ID ," in_READ_UNIT_IN_OOO_ENGINE_ID ",Tcontext_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_PACKET_ID ," in_READ_UNIT_IN_PACKET_ID ",Tpacket_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_OPERATION ," in_READ_UNIT_IN_OPERATION ",Toperation_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_TYPE ," in_READ_UNIT_IN_TYPE ",Ttype_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE ," in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ," in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_HAS_IMMEDIAT ," in_READ_UNIT_IN_HAS_IMMEDIAT ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_IMMEDIAT ," in_READ_UNIT_IN_IMMEDIAT ",Tgeneral_data_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_READ_RA ," in_READ_UNIT_IN_READ_RA ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_NUM_REG_RA ," in_READ_UNIT_IN_NUM_REG_RA ",Tgeneral_address_t); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_READ_RB ," in_READ_UNIT_IN_READ_RB ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_NUM_REG_RB ," in_READ_UNIT_IN_NUM_REG_RB ",Tgeneral_address_t); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_READ_RC ," in_READ_UNIT_IN_READ_RC ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_NUM_REG_RC ," in_READ_UNIT_IN_NUM_REG_RC ",Tspecial_address_t); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_WRITE_RD ," in_READ_UNIT_IN_WRITE_RD ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_NUM_REG_RD ," in_READ_UNIT_IN_NUM_REG_RD ",Tgeneral_address_t); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_WRITE_RE ," in_READ_UNIT_IN_WRITE_RE ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_NUM_REG_RE ," in_READ_UNIT_IN_NUM_REG_RE ",Tspecial_address_t); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_VAL ," in_READ_UNIT_IN_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_READ_UNIT_IN_ACK ,"out_READ_UNIT_IN_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_CONTEXT_ID ," in_READ_UNIT_IN_CONTEXT_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_FRONT_END_ID ," in_READ_UNIT_IN_FRONT_END_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_OOO_ENGINE_ID ," in_READ_UNIT_IN_OOO_ENGINE_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_PACKET_ID ," in_READ_UNIT_IN_PACKET_ID ",Tpacket_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_OPERATION ," in_READ_UNIT_IN_OPERATION ",Toperation_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_TYPE ," in_READ_UNIT_IN_TYPE ",Ttype_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE ," in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ," in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_HAS_IMMEDIAT ," in_READ_UNIT_IN_HAS_IMMEDIAT ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_IMMEDIAT ," in_READ_UNIT_IN_IMMEDIAT ",Tgeneral_data_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_READ_RA ," in_READ_UNIT_IN_READ_RA ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_NUM_REG_RA ," in_READ_UNIT_IN_NUM_REG_RA ",Tgeneral_address_t); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_READ_RB ," in_READ_UNIT_IN_READ_RB ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_NUM_REG_RB ," in_READ_UNIT_IN_NUM_REG_RB ",Tgeneral_address_t); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_READ_RC ," in_READ_UNIT_IN_READ_RC ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_NUM_REG_RC ," in_READ_UNIT_IN_NUM_REG_RC ",Tspecial_address_t); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_WRITE_RD ," in_READ_UNIT_IN_WRITE_RD ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_NUM_REG_RD ," in_READ_UNIT_IN_NUM_REG_RD ",Tgeneral_address_t); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_WRITE_RE ," in_READ_UNIT_IN_WRITE_RE ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_NUM_REG_RE ," in_READ_UNIT_IN_NUM_REG_RE ",Tspecial_address_t); ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_VAL ,"out_READ_UNIT_OUT_VAL ",Tcontrol_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_ACK ," in_READ_UNIT_OUT_ACK ",Tcontrol_t ,_param->_nb_inst_retire); @@ -146,31 +146,31 @@ (*(_Read_unit->in_NRESET)) (*(in_NRESET)); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_VAL ); - INSTANCE_SC_SIGNAL (_Read_unit,out_READ_UNIT_IN_ACK ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_VAL ); + INSTANCE0_SC_SIGNAL(_Read_unit,out_READ_UNIT_IN_ACK ); if (_param->_have_port_context_id) - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_CONTEXT_ID ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_CONTEXT_ID ); if (_param->_have_port_front_end_id) - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_FRONT_END_ID ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_FRONT_END_ID ); if (_param->_have_port_ooo_engine_id) - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_OOO_ENGINE_ID ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_OOO_ENGINE_ID ); if (_param->_have_port_rob_ptr) - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_PACKET_ID ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_OPERATION ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_TYPE ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_PACKET_ID ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_OPERATION ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_TYPE ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE ); if (_param->_have_port_load_queue_ptr) - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_HAS_IMMEDIAT ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_IMMEDIAT ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_READ_RA ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_NUM_REG_RA ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_READ_RB ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_NUM_REG_RB ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_READ_RC ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_NUM_REG_RC ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_WRITE_RD ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_NUM_REG_RD ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_WRITE_RE ); - INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_NUM_REG_RE ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_HAS_IMMEDIAT ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_IMMEDIAT ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_READ_RA ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_NUM_REG_RA ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_READ_RB ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_NUM_REG_RB ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_READ_RC ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_NUM_REG_RC ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_WRITE_RD ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_NUM_REG_RD ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_WRITE_RE ); + INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_NUM_REG_RE ); INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_VAL ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Read_unit, in_READ_UNIT_OUT_ACK ,_param->_nb_inst_retire); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp (revision 112) @@ -57,33 +57,35 @@ // ~~~~~[ Interface "read_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("read_unit_in", IN, WEST, _("Enter of new operation")); - - ALLOC_VALACK_IN ( in_READ_UNIT_IN_VAL,VAL); - ALLOC_VALACK_OUT (out_READ_UNIT_IN_ACK,ACK); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_READ_RA ,"read_ra" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_READ_RB ,"read_rb" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_READ_RC ,"read_rc" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); + ALLOC0_INTERFACE_BEGIN("read_unit_in", IN, WEST, _("Enter of new operation")); + + ALLOC0_VALACK_IN ( in_READ_UNIT_IN_VAL,VAL); + ALLOC0_VALACK_OUT (out_READ_UNIT_IN_ACK,ACK); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_READ_RA ,"read_ra" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_READ_RB ,"read_rb" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_READ_RC ,"read_rc" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); + + ALLOC0_INTERFACE_END(); } // ~~~~~[ Interface "read_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("read_unit_out", OUT, EAST, _("Output of operation. All operand is valid."), _param->_nb_inst_retire); + ALLOC1_INTERFACE_BEGIN("read_unit_out", OUT, EAST, _("Output of operation. All operand is valid."), _param->_nb_inst_retire); ALLOC1_VALACK_OUT (out_READ_UNIT_OUT_VAL,VAL); @@ -106,9 +108,11 @@ ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); + + ALLOC1_INTERFACE_END(_param->_nb_inst_retire); } // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("gpr_read", OUT, SOUTH, _("Read port."), _param->_nb_gpr_read); + ALLOC1_INTERFACE_BEGIN("gpr_read", OUT, SOUTH, _("Read port."), _param->_nb_gpr_read); ALLOC1_VALACK_OUT (out_GPR_READ_VAL,VAL); @@ -118,9 +122,11 @@ ALLOC1_SIGNAL_IN ( in_GPR_READ_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); ALLOC1_SIGNAL_IN ( in_GPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_read); } // ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("spr_read", OUT, SOUTH, _("Read port."), _param->_nb_spr_read); + ALLOC1_INTERFACE_BEGIN("spr_read", OUT, SOUTH, _("Read port."), _param->_nb_spr_read); ALLOC1_VALACK_OUT (out_SPR_READ_VAL,VAL); @@ -130,9 +136,11 @@ ALLOC1_SIGNAL_IN ( in_SPR_READ_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data ); ALLOC1_SIGNAL_IN ( in_SPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_spr_read); } // ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("gpr_write", IN , SOUTH, _("Write port."), _param->_nb_gpr_write); + ALLOC1_INTERFACE_BEGIN("gpr_write", IN , SOUTH, _("Write port."), _param->_nb_gpr_write); ALLOC1_VALACK_IN ( in_GPR_WRITE_VAL,VAL); @@ -140,9 +148,11 @@ ALLOC1_SIGNAL_IN ( in_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); ALLOC1_SIGNAL_IN ( in_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_write); } // ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("spr_write", IN , SOUTH, _("Write port."), _param->_nb_spr_write); + ALLOC1_INTERFACE_BEGIN("spr_write", IN , SOUTH, _("Write port."), _param->_nb_spr_write); ALLOC1_VALACK_IN ( in_SPR_WRITE_VAL,VAL); @@ -150,9 +160,11 @@ ALLOC1_SIGNAL_IN ( in_SPR_WRITE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); ALLOC1_SIGNAL_IN ( in_SPR_WRITE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data); + + ALLOC1_INTERFACE_END(_param->_nb_spr_write); } // ~~~~~[ Interface "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("bypass_write", IN , NORTH, _("Output of write_queue."), _param->_nb_bypass_write); + ALLOC1_INTERFACE_BEGIN("bypass_write", IN , NORTH, _("Output of write_queue."), _param->_nb_bypass_write); ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); @@ -163,9 +175,11 @@ ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_register); ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_data ); + + ALLOC1_INTERFACE_END(_param->_nb_bypass_write); } // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("bypass_memory", IN , NORTH, _("Output of write_queue."), _param->_nb_bypass_memory); + ALLOC1_INTERFACE_BEGIN("bypass_memory", IN , NORTH, _("Output of write_queue."), _param->_nb_bypass_memory); ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_VAL ,"val" ,Tcontrol_t ,1); @@ -173,4 +187,6 @@ ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); + + ALLOC1_INTERFACE_END(_param->_nb_bypass_memory); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/include/Read_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -28,107 +29,83 @@ delete in_NRESET; - // ~~~~~[ Interface "read_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete in_READ_UNIT_IN_VAL ; - delete out_READ_UNIT_IN_ACK ; - if (_param->_have_port_context_id) - delete in_READ_UNIT_IN_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete in_READ_UNIT_IN_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete in_READ_UNIT_IN_OOO_ENGINE_ID ; - if (_param->_have_port_rob_ptr) - delete in_READ_UNIT_IN_PACKET_ID ; - delete in_READ_UNIT_IN_OPERATION ; - delete in_READ_UNIT_IN_TYPE ; - delete in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE; - if (_param->_have_port_load_queue_ptr) - delete in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ; - delete in_READ_UNIT_IN_HAS_IMMEDIAT ; - delete in_READ_UNIT_IN_IMMEDIAT ; - delete in_READ_UNIT_IN_READ_RA ; - delete in_READ_UNIT_IN_NUM_REG_RA ; - delete in_READ_UNIT_IN_READ_RB ; - delete in_READ_UNIT_IN_NUM_REG_RB ; - delete in_READ_UNIT_IN_READ_RC ; - delete in_READ_UNIT_IN_NUM_REG_RC ; - delete in_READ_UNIT_IN_WRITE_RD ; - delete in_READ_UNIT_IN_NUM_REG_RD ; - delete in_READ_UNIT_IN_WRITE_RE ; - delete in_READ_UNIT_IN_NUM_REG_RE ; + DELETE0_SIGNAL( in_READ_UNIT_IN_VAL ,1); + DELETE0_SIGNAL(out_READ_UNIT_IN_ACK ,1); + DELETE0_SIGNAL( in_READ_UNIT_IN_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL( in_READ_UNIT_IN_FRONT_END_ID ,_param->_size_front_end_id ); + DELETE0_SIGNAL( in_READ_UNIT_IN_OOO_ENGINE_ID ,_param->_size_ooo_engine_id); + DELETE0_SIGNAL( in_READ_UNIT_IN_PACKET_ID ,_param->_size_rob_ptr ); + DELETE0_SIGNAL( in_READ_UNIT_IN_OPERATION ,_param->_size_operation ); + DELETE0_SIGNAL( in_READ_UNIT_IN_TYPE ,_param->_size_type ); + DELETE0_SIGNAL( in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE,_param->_size_store_queue_ptr); + DELETE0_SIGNAL( in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,_param->_size_load_queue_ptr); + DELETE0_SIGNAL( in_READ_UNIT_IN_HAS_IMMEDIAT ,1); + DELETE0_SIGNAL( in_READ_UNIT_IN_IMMEDIAT ,_param->_size_general_data); + DELETE0_SIGNAL( in_READ_UNIT_IN_READ_RA ,1); + DELETE0_SIGNAL( in_READ_UNIT_IN_NUM_REG_RA ,_param->_size_general_register); + DELETE0_SIGNAL( in_READ_UNIT_IN_READ_RB ,1); + DELETE0_SIGNAL( in_READ_UNIT_IN_NUM_REG_RB ,_param->_size_general_register); + DELETE0_SIGNAL( in_READ_UNIT_IN_READ_RC ,1); + DELETE0_SIGNAL( in_READ_UNIT_IN_NUM_REG_RC ,_param->_size_special_register); + DELETE0_SIGNAL( in_READ_UNIT_IN_WRITE_RD ,1); + DELETE0_SIGNAL( in_READ_UNIT_IN_NUM_REG_RD ,_param->_size_general_register); + DELETE0_SIGNAL( in_READ_UNIT_IN_WRITE_RE ,1); + DELETE0_SIGNAL( in_READ_UNIT_IN_NUM_REG_RE ,_param->_size_special_register); - // ~~~~~[ Interface "read_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] out_READ_UNIT_OUT_VAL ; - delete [] in_READ_UNIT_OUT_ACK ; - if (_param->_have_port_context_id) - delete [] out_READ_UNIT_OUT_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete [] out_READ_UNIT_OUT_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete [] out_READ_UNIT_OUT_OOO_ENGINE_ID ; - if (_param->_have_port_rob_ptr) - delete [] out_READ_UNIT_OUT_PACKET_ID ; - delete [] out_READ_UNIT_OUT_OPERATION ; - delete [] out_READ_UNIT_OUT_TYPE ; - delete [] out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE; - if (_param->_have_port_load_queue_ptr) - delete [] out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ; - delete [] out_READ_UNIT_OUT_HAS_IMMEDIAT ; - delete [] out_READ_UNIT_OUT_IMMEDIAT ; - delete [] out_READ_UNIT_OUT_DATA_RA ; - delete [] out_READ_UNIT_OUT_DATA_RB ; - delete [] out_READ_UNIT_OUT_DATA_RC ; - delete [] out_READ_UNIT_OUT_WRITE_RD ; - delete [] out_READ_UNIT_OUT_NUM_REG_RD ; - delete [] out_READ_UNIT_OUT_WRITE_RE ; - delete [] out_READ_UNIT_OUT_NUM_REG_RE ; + DELETE1_SIGNAL(out_READ_UNIT_OUT_VAL ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_READ_UNIT_OUT_ACK ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_READ_UNIT_OUT_CONTEXT_ID ,_param->_nb_inst_retire,_param->_size_context_id ); + DELETE1_SIGNAL(out_READ_UNIT_OUT_FRONT_END_ID ,_param->_nb_inst_retire,_param->_size_front_end_id ); + DELETE1_SIGNAL(out_READ_UNIT_OUT_OOO_ENGINE_ID ,_param->_nb_inst_retire,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL(out_READ_UNIT_OUT_PACKET_ID ,_param->_nb_inst_retire,_param->_size_rob_ptr ); + DELETE1_SIGNAL(out_READ_UNIT_OUT_OPERATION ,_param->_nb_inst_retire,_param->_size_operation ); + DELETE1_SIGNAL(out_READ_UNIT_OUT_TYPE ,_param->_nb_inst_retire,_param->_size_type ); + DELETE1_SIGNAL(out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire,_param->_size_store_queue_ptr); + DELETE1_SIGNAL(out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire,_param->_size_load_queue_ptr); + DELETE1_SIGNAL(out_READ_UNIT_OUT_HAS_IMMEDIAT ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL(out_READ_UNIT_OUT_IMMEDIAT ,_param->_nb_inst_retire,_param->_size_general_data ); + DELETE1_SIGNAL(out_READ_UNIT_OUT_DATA_RA ,_param->_nb_inst_retire,_param->_size_general_data ); + DELETE1_SIGNAL(out_READ_UNIT_OUT_DATA_RB ,_param->_nb_inst_retire,_param->_size_general_data ); + DELETE1_SIGNAL(out_READ_UNIT_OUT_DATA_RC ,_param->_nb_inst_retire,_param->_size_special_data ); + DELETE1_SIGNAL(out_READ_UNIT_OUT_WRITE_RD ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL(out_READ_UNIT_OUT_NUM_REG_RD ,_param->_nb_inst_retire,_param->_size_general_register); + DELETE1_SIGNAL(out_READ_UNIT_OUT_WRITE_RE ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL(out_READ_UNIT_OUT_NUM_REG_RE ,_param->_nb_inst_retire,_param->_size_special_register); - // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] out_GPR_READ_VAL ; - delete [] in_GPR_READ_ACK ; - if (_param->_have_port_ooo_engine_id) - delete [] out_GPR_READ_OOO_ENGINE_ID; - delete [] out_GPR_READ_NUM_REG ; - delete [] in_GPR_READ_DATA ; - delete [] in_GPR_READ_DATA_VAL ; + DELETE1_SIGNAL(out_GPR_READ_VAL , _param->_nb_gpr_read,1); + DELETE1_SIGNAL( in_GPR_READ_ACK , _param->_nb_gpr_read,1); + DELETE1_SIGNAL(out_GPR_READ_OOO_ENGINE_ID, _param->_nb_gpr_read,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL(out_GPR_READ_NUM_REG , _param->_nb_gpr_read,_param->_size_general_register); + DELETE1_SIGNAL( in_GPR_READ_DATA , _param->_nb_gpr_read,_param->_size_general_data ); + DELETE1_SIGNAL( in_GPR_READ_DATA_VAL , _param->_nb_gpr_read,1); - // ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] out_SPR_READ_VAL ; - delete [] in_SPR_READ_ACK ; - if (_param->_have_port_ooo_engine_id) - delete [] out_SPR_READ_OOO_ENGINE_ID; - delete [] out_SPR_READ_NUM_REG ; - delete [] in_SPR_READ_DATA ; - delete [] in_SPR_READ_DATA_VAL ; + DELETE1_SIGNAL(out_SPR_READ_VAL , _param->_nb_spr_read,1); + DELETE1_SIGNAL( in_SPR_READ_ACK , _param->_nb_spr_read,1); + DELETE1_SIGNAL(out_SPR_READ_OOO_ENGINE_ID, _param->_nb_spr_read,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL(out_SPR_READ_NUM_REG , _param->_nb_spr_read,_param->_size_special_register); + DELETE1_SIGNAL( in_SPR_READ_DATA , _param->_nb_spr_read,_param->_size_special_data ); + DELETE1_SIGNAL( in_SPR_READ_DATA_VAL , _param->_nb_spr_read,1); - // ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_GPR_WRITE_VAL ; - if (_param->_have_port_ooo_engine_id) - delete [] in_GPR_WRITE_OOO_ENGINE_ID; - delete [] in_GPR_WRITE_NUM_REG ; - delete [] in_GPR_WRITE_DATA ; + DELETE1_SIGNAL( in_GPR_WRITE_VAL , _param->_nb_gpr_write,1); + DELETE1_SIGNAL( in_GPR_WRITE_OOO_ENGINE_ID, _param->_nb_gpr_write,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL( in_GPR_WRITE_NUM_REG , _param->_nb_gpr_write,_param->_size_general_register); + DELETE1_SIGNAL( in_GPR_WRITE_DATA , _param->_nb_gpr_write,_param->_size_general_data); - // ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_SPR_WRITE_VAL ; - if (_param->_have_port_ooo_engine_id) - delete [] in_SPR_WRITE_OOO_ENGINE_ID; - delete [] in_SPR_WRITE_NUM_REG ; - delete [] in_SPR_WRITE_DATA ; + DELETE1_SIGNAL( in_SPR_WRITE_VAL , _param->_nb_spr_write,1); + DELETE1_SIGNAL( in_SPR_WRITE_OOO_ENGINE_ID, _param->_nb_spr_write,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL( in_SPR_WRITE_NUM_REG , _param->_nb_spr_write,_param->_size_special_register); + DELETE1_SIGNAL( in_SPR_WRITE_DATA , _param->_nb_spr_write,_param->_size_special_data); - // ~~~~~[ Interface "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - if (_param->_have_port_ooo_engine_id) - delete [] in_BYPASS_WRITE_OOO_ENGINE_ID ; - delete [] in_BYPASS_WRITE_GPR_VAL ; - delete [] in_BYPASS_WRITE_GPR_NUM_REG ; - delete [] in_BYPASS_WRITE_GPR_DATA ; - delete [] in_BYPASS_WRITE_SPR_VAL ; - delete [] in_BYPASS_WRITE_SPR_NUM_REG ; - delete [] in_BYPASS_WRITE_SPR_DATA ; + DELETE1_SIGNAL( in_BYPASS_WRITE_OOO_ENGINE_ID, _param->_nb_bypass_write,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL( in_BYPASS_WRITE_GPR_VAL , _param->_nb_bypass_write,1); + DELETE1_SIGNAL( in_BYPASS_WRITE_GPR_NUM_REG , _param->_nb_bypass_write,_param->_size_general_register); + DELETE1_SIGNAL( in_BYPASS_WRITE_GPR_DATA , _param->_nb_bypass_write,_param->_size_general_data ); + DELETE1_SIGNAL( in_BYPASS_WRITE_SPR_VAL , _param->_nb_bypass_write,1); + DELETE1_SIGNAL( in_BYPASS_WRITE_SPR_NUM_REG , _param->_nb_bypass_write,_param->_size_special_register); + DELETE1_SIGNAL( in_BYPASS_WRITE_SPR_DATA , _param->_nb_bypass_write,_param->_size_special_data ); - // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_BYPASS_MEMORY_VAL ; - if (_param->_have_port_ooo_engine_id) - delete [] in_BYPASS_MEMORY_OOO_ENGINE_ID; - delete [] in_BYPASS_MEMORY_NUM_REG ; - delete [] in_BYPASS_MEMORY_DATA ; + DELETE1_SIGNAL( in_BYPASS_MEMORY_VAL , _param->_nb_bypass_memory,1); + DELETE1_SIGNAL( in_BYPASS_MEMORY_OOO_ENGINE_ID, _param->_nb_bypass_memory,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL( in_BYPASS_MEMORY_NUM_REG , _param->_nb_bypass_memory,_param->_size_general_register); + DELETE1_SIGNAL( in_BYPASS_MEMORY_DATA , _param->_nb_bypass_memory,_param->_size_general_data ); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/test.cpp (revision 112) @@ -112,30 +112,30 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_VAL ," in_EXECUTE_QUEUE_IN_VAL" , Tcontrol_t ); - ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_IN_ACK ,"out_EXECUTE_QUEUE_IN_ACK" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_CONTEXT_ID ," in_EXECUTE_QUEUE_IN_CONTEXT_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_FRONT_END_ID ," in_EXECUTE_QUEUE_IN_FRONT_END_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID ," in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_PACKET_ID ," in_EXECUTE_QUEUE_IN_PACKET_ID" , Tpacket_t ); -//ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_OPERATION ," in_EXECUTE_QUEUE_IN_OPERATION" , Toperation_t ); -//ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_TYPE ," in_EXECUTE_QUEUE_IN_TYPE" , Ttype_t ); - ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_FLAGS ," in_EXECUTE_QUEUE_IN_FLAGS" , Tspecial_data_t ); - ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_EXCEPTION ," in_EXECUTE_QUEUE_IN_EXCEPTION" , Texception_t ); - ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_NO_SEQUENCE ," in_EXECUTE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_ADDRESS ," in_EXECUTE_QUEUE_IN_ADDRESS" , Taddress_t ); - ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_DATA ," in_EXECUTE_QUEUE_IN_DATA" , Tgeneral_data_t ); - ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_VAL ,"out_EXECUTE_QUEUE_OUT_VAL" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_OUT_ACK ," in_EXECUTE_QUEUE_OUT_ACK" , Tcontrol_t ); - ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_CONTEXT_ID ,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_FRONT_END_ID ,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID", Tcontext_t ); - ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_PACKET_ID ,"out_EXECUTE_QUEUE_OUT_PACKET_ID" , Tpacket_t ); -//ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_OPERATION ,"out_EXECUTE_QUEUE_OUT_OPERATION" , Toperation_t ); -//ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_TYPE ,"out_EXECUTE_QUEUE_OUT_TYPE" , Ttype_t ); - ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_FLAGS ,"out_EXECUTE_QUEUE_OUT_FLAGS" , Tspecial_data_t ); - ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_EXCEPTION ,"out_EXECUTE_QUEUE_OUT_EXCEPTION" , Texception_t ); - ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); - ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_ADDRESS ,"out_EXECUTE_QUEUE_OUT_ADDRESS" , Taddress_t ); - ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_DATA ,"out_EXECUTE_QUEUE_OUT_DATA" , Tgeneral_data_t ); + ALLOC0_SC_SIGNAL( in_EXECUTE_QUEUE_IN_VAL ," in_EXECUTE_QUEUE_IN_VAL" , Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_EXECUTE_QUEUE_IN_ACK ,"out_EXECUTE_QUEUE_IN_ACK" , Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_EXECUTE_QUEUE_IN_CONTEXT_ID ," in_EXECUTE_QUEUE_IN_CONTEXT_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL( in_EXECUTE_QUEUE_IN_FRONT_END_ID ," in_EXECUTE_QUEUE_IN_FRONT_END_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL( in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID ," in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL( in_EXECUTE_QUEUE_IN_PACKET_ID ," in_EXECUTE_QUEUE_IN_PACKET_ID" , Tpacket_t ); +//ALLOC0_SC_SIGNAL( in_EXECUTE_QUEUE_IN_OPERATION ," in_EXECUTE_QUEUE_IN_OPERATION" , Toperation_t ); +//ALLOC0_SC_SIGNAL( in_EXECUTE_QUEUE_IN_TYPE ," in_EXECUTE_QUEUE_IN_TYPE" , Ttype_t ); + ALLOC0_SC_SIGNAL( in_EXECUTE_QUEUE_IN_FLAGS ," in_EXECUTE_QUEUE_IN_FLAGS" , Tspecial_data_t ); + ALLOC0_SC_SIGNAL( in_EXECUTE_QUEUE_IN_EXCEPTION ," in_EXECUTE_QUEUE_IN_EXCEPTION" , Texception_t ); + ALLOC0_SC_SIGNAL( in_EXECUTE_QUEUE_IN_NO_SEQUENCE ," in_EXECUTE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_EXECUTE_QUEUE_IN_ADDRESS ," in_EXECUTE_QUEUE_IN_ADDRESS" , Taddress_t ); + ALLOC0_SC_SIGNAL( in_EXECUTE_QUEUE_IN_DATA ," in_EXECUTE_QUEUE_IN_DATA" , Tgeneral_data_t ); + ALLOC0_SC_SIGNAL(out_EXECUTE_QUEUE_OUT_VAL ,"out_EXECUTE_QUEUE_OUT_VAL" , Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_EXECUTE_QUEUE_OUT_ACK ," in_EXECUTE_QUEUE_OUT_ACK" , Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_EXECUTE_QUEUE_OUT_CONTEXT_ID ,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL(out_EXECUTE_QUEUE_OUT_FRONT_END_ID ,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL(out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID", Tcontext_t ); + ALLOC0_SC_SIGNAL(out_EXECUTE_QUEUE_OUT_PACKET_ID ,"out_EXECUTE_QUEUE_OUT_PACKET_ID" , Tpacket_t ); +//ALLOC0_SC_SIGNAL(out_EXECUTE_QUEUE_OUT_OPERATION ,"out_EXECUTE_QUEUE_OUT_OPERATION" , Toperation_t ); +//ALLOC0_SC_SIGNAL(out_EXECUTE_QUEUE_OUT_TYPE ,"out_EXECUTE_QUEUE_OUT_TYPE" , Ttype_t ); + ALLOC0_SC_SIGNAL(out_EXECUTE_QUEUE_OUT_FLAGS ,"out_EXECUTE_QUEUE_OUT_FLAGS" , Tspecial_data_t ); + ALLOC0_SC_SIGNAL(out_EXECUTE_QUEUE_OUT_EXCEPTION ,"out_EXECUTE_QUEUE_OUT_EXCEPTION" , Texception_t ); + ALLOC0_SC_SIGNAL(out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_EXECUTE_QUEUE_OUT_ADDRESS ,"out_EXECUTE_QUEUE_OUT_ADDRESS" , Taddress_t ); + ALLOC0_SC_SIGNAL(out_EXECUTE_QUEUE_OUT_DATA ,"out_EXECUTE_QUEUE_OUT_DATA" , Tgeneral_data_t ); @@ -149,39 +149,39 @@ (*(_Execute_queue->in_NRESET)) (*(in_NRESET)); - INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_VAL ); - INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_IN_ACK ); + INSTANCE0_SC_SIGNAL(_Execute_queue, in_EXECUTE_QUEUE_IN_VAL ); + INSTANCE0_SC_SIGNAL(_Execute_queue, out_EXECUTE_QUEUE_IN_ACK ); if (_param->_have_port_context_id) - INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_CONTEXT_ID ); + INSTANCE0_SC_SIGNAL(_Execute_queue, in_EXECUTE_QUEUE_IN_CONTEXT_ID ); if (_param->_have_port_front_end_id) - INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_FRONT_END_ID ); + INSTANCE0_SC_SIGNAL(_Execute_queue, in_EXECUTE_QUEUE_IN_FRONT_END_ID ); if (_param->_have_port_ooo_engine_id) - INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID ); + INSTANCE0_SC_SIGNAL(_Execute_queue, in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID ); if (_param->_have_port_rob_ptr) - INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_PACKET_ID ); -//INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_OPERATION ); -//INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_TYPE ); - INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_FLAGS ); - INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_EXCEPTION ); - INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_NO_SEQUENCE ); - INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_ADDRESS ); - INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_DATA ); - - INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_VAL ); - INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_OUT_ACK ); + INSTANCE0_SC_SIGNAL(_Execute_queue, in_EXECUTE_QUEUE_IN_PACKET_ID ); +//INSTANCE0_SC_SIGNAL(_Execute_queue, in_EXECUTE_QUEUE_IN_OPERATION ); +//INSTANCE0_SC_SIGNAL(_Execute_queue, in_EXECUTE_QUEUE_IN_TYPE ); + INSTANCE0_SC_SIGNAL(_Execute_queue, in_EXECUTE_QUEUE_IN_FLAGS ); + INSTANCE0_SC_SIGNAL(_Execute_queue, in_EXECUTE_QUEUE_IN_EXCEPTION ); + INSTANCE0_SC_SIGNAL(_Execute_queue, in_EXECUTE_QUEUE_IN_NO_SEQUENCE ); + INSTANCE0_SC_SIGNAL(_Execute_queue, in_EXECUTE_QUEUE_IN_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Execute_queue, in_EXECUTE_QUEUE_IN_DATA ); + + INSTANCE0_SC_SIGNAL(_Execute_queue, out_EXECUTE_QUEUE_OUT_VAL ); + INSTANCE0_SC_SIGNAL(_Execute_queue, in_EXECUTE_QUEUE_OUT_ACK ); if (_param->_have_port_context_id) - INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_CONTEXT_ID ); + INSTANCE0_SC_SIGNAL(_Execute_queue, out_EXECUTE_QUEUE_OUT_CONTEXT_ID ); if (_param->_have_port_front_end_id) - INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_FRONT_END_ID ); + INSTANCE0_SC_SIGNAL(_Execute_queue, out_EXECUTE_QUEUE_OUT_FRONT_END_ID ); if (_param->_have_port_ooo_engine_id) - INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID); + INSTANCE0_SC_SIGNAL(_Execute_queue, out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID); if (_param->_have_port_rob_ptr) - INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_PACKET_ID ); -//INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_OPERATION ); -//INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_TYPE ); - INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_FLAGS ); - INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_EXCEPTION ); - INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ); - INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_ADDRESS ); - INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_DATA ); + INSTANCE0_SC_SIGNAL(_Execute_queue, out_EXECUTE_QUEUE_OUT_PACKET_ID ); +//INSTANCE0_SC_SIGNAL(_Execute_queue, out_EXECUTE_QUEUE_OUT_OPERATION ); +//INSTANCE0_SC_SIGNAL(_Execute_queue, out_EXECUTE_QUEUE_OUT_TYPE ); + INSTANCE0_SC_SIGNAL(_Execute_queue, out_EXECUTE_QUEUE_OUT_FLAGS ); + INSTANCE0_SC_SIGNAL(_Execute_queue, out_EXECUTE_QUEUE_OUT_EXCEPTION ); + INSTANCE0_SC_SIGNAL(_Execute_queue, out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ); + INSTANCE0_SC_SIGNAL(_Execute_queue, out_EXECUTE_QUEUE_OUT_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Execute_queue, out_EXECUTE_QUEUE_OUT_DATA ); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp (revision 112) @@ -50,46 +50,42 @@ // -----[ Interface "execute_queue_in" ]-------------------------------- { - ALLOC_INTERFACE ("execute_queue_in", IN, WEST, "Input of execute_queue"); + ALLOC0_INTERFACE_BEGIN("execute_queue_in", IN, WEST, "Input of execute_queue"); - ALLOC_VALACK_IN ( in_EXECUTE_QUEUE_IN_VAL,VAL); - ALLOC_VALACK_OUT(out_EXECUTE_QUEUE_IN_ACK,ACK); - if(_param->_have_port_context_id) - ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - if(_param->_have_port_front_end_id) - ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); - if(_param->_have_port_ooo_engine_id) - ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); - if(_param->_have_port_rob_ptr) - ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); -// ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); -// ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); - ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_FLAGS ,"flags" ,Tspecial_data_t ,_param->_size_special_data ); - ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); - ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); - ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC0_VALACK_IN ( in_EXECUTE_QUEUE_IN_VAL,VAL); + ALLOC0_VALACK_OUT(out_EXECUTE_QUEUE_IN_ACK,ACK); + ALLOC0_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC0_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); + ALLOC0_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); +// ALLOC0_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); +// ALLOC0_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC0_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_FLAGS ,"flags" ,Tspecial_data_t ,_param->_size_special_data ); + ALLOC0_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); + ALLOC0_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC0_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); + + ALLOC0_INTERFACE_END(); } // -----[ Interface "execute_queue_out" ]------------------------------- { - ALLOC_INTERFACE ("execute_queue_out", OUT, EAST, "Output of execute_queue"); + ALLOC0_INTERFACE_BEGIN("execute_queue_out", OUT, EAST, "Output of execute_queue"); - ALLOC_VALACK_OUT(out_EXECUTE_QUEUE_OUT_VAL,VAL); - ALLOC_VALACK_IN ( in_EXECUTE_QUEUE_OUT_ACK,ACK); - if(_param->_have_port_context_id) - ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - if(_param->_have_port_front_end_id) - ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); - if(_param->_have_port_ooo_engine_id) - ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); - if(_param->_have_port_rob_ptr) - ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); -// ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); -// ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); - ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_FLAGS ,"flags" ,Tspecial_data_t,_param->_size_special_data ); - ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); - ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); - ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); + ALLOC0_VALACK_OUT(out_EXECUTE_QUEUE_OUT_VAL,VAL); + ALLOC0_VALACK_IN ( in_EXECUTE_QUEUE_OUT_ACK,ACK); + ALLOC0_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC0_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC0_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); +// ALLOC0_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); +// ALLOC0_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC0_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_FLAGS ,"flags" ,Tspecial_data_t,_param->_size_special_data ); + ALLOC0_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); + ALLOC0_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); + + ALLOC0_INTERFACE_END(); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -29,41 +30,31 @@ delete in_NRESET; - // -----[ Interface "execute_queue_in" ]-------------------------------- - delete in_EXECUTE_QUEUE_IN_VAL ; - delete out_EXECUTE_QUEUE_IN_ACK ; - if (_param->_have_port_context_id) - delete in_EXECUTE_QUEUE_IN_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete in_EXECUTE_QUEUE_IN_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID; - if (_param->_have_port_rob_ptr) - delete in_EXECUTE_QUEUE_IN_PACKET_ID ; -// delete in_EXECUTE_QUEUE_IN_OPERATION ; -// delete in_EXECUTE_QUEUE_IN_TYPE ; - delete in_EXECUTE_QUEUE_IN_FLAGS ; - delete in_EXECUTE_QUEUE_IN_EXCEPTION ; - delete in_EXECUTE_QUEUE_IN_NO_SEQUENCE ; - delete in_EXECUTE_QUEUE_IN_ADDRESS ; - delete in_EXECUTE_QUEUE_IN_DATA ; - - // -----[ Interface "execute_queue_out" ]------------------------------- - delete out_EXECUTE_QUEUE_OUT_VAL ; - delete in_EXECUTE_QUEUE_OUT_ACK ; - if (_param->_have_port_context_id) - delete out_EXECUTE_QUEUE_OUT_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete out_EXECUTE_QUEUE_OUT_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID; - if (_param->_have_port_rob_ptr) - delete out_EXECUTE_QUEUE_OUT_PACKET_ID ; -// delete out_EXECUTE_QUEUE_OUT_OPERATION ; -// delete out_EXECUTE_QUEUE_OUT_TYPE ; - delete out_EXECUTE_QUEUE_OUT_FLAGS ; - delete out_EXECUTE_QUEUE_OUT_EXCEPTION ; - delete out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ; - delete out_EXECUTE_QUEUE_OUT_ADDRESS ; - delete out_EXECUTE_QUEUE_OUT_DATA ; + DELETE0_SIGNAL( in_EXECUTE_QUEUE_IN_VAL ,1); + DELETE0_SIGNAL(out_EXECUTE_QUEUE_IN_ACK ,1); + DELETE0_SIGNAL( in_EXECUTE_QUEUE_IN_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL( in_EXECUTE_QUEUE_IN_FRONT_END_ID ,_param->_size_front_end_id ); + DELETE0_SIGNAL( in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID ,_param->_size_ooo_engine_id ); + DELETE0_SIGNAL( in_EXECUTE_QUEUE_IN_PACKET_ID ,_param->_size_rob_ptr ); +// DELETE0_SIGNAL( in_EXECUTE_QUEUE_IN_OPERATION ,_param->_size_operation ); +// DELETE0_SIGNAL( in_EXECUTE_QUEUE_IN_TYPE ,_param->_size_type ); + DELETE0_SIGNAL( in_EXECUTE_QUEUE_IN_FLAGS ,_param->_size_special_data ); + DELETE0_SIGNAL( in_EXECUTE_QUEUE_IN_EXCEPTION ,_param->_size_exception ); + DELETE0_SIGNAL( in_EXECUTE_QUEUE_IN_NO_SEQUENCE ,1 ); + DELETE0_SIGNAL( in_EXECUTE_QUEUE_IN_ADDRESS ,_param->_size_instruction_address); + DELETE0_SIGNAL( in_EXECUTE_QUEUE_IN_DATA ,_param->_size_general_data ); + + DELETE0_SIGNAL(out_EXECUTE_QUEUE_OUT_VAL ,1); + DELETE0_SIGNAL( in_EXECUTE_QUEUE_OUT_ACK ,1); + DELETE0_SIGNAL(out_EXECUTE_QUEUE_OUT_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL(out_EXECUTE_QUEUE_OUT_FRONT_END_ID ,_param->_size_front_end_id ); + DELETE0_SIGNAL(out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID,_param->_size_ooo_engine_id); + DELETE0_SIGNAL(out_EXECUTE_QUEUE_OUT_PACKET_ID ,_param->_size_rob_ptr ); +// DELETE0_SIGNAL(out_EXECUTE_QUEUE_OUT_OPERATION ,_param->_size_operation ); +// DELETE0_SIGNAL(out_EXECUTE_QUEUE_OUT_TYPE ,_param->_size_type ); + DELETE0_SIGNAL(out_EXECUTE_QUEUE_OUT_FLAGS ,_param->_size_special_data ); + DELETE0_SIGNAL(out_EXECUTE_QUEUE_OUT_EXCEPTION ,_param->_size_exception ); + DELETE0_SIGNAL(out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ,1 ); + DELETE0_SIGNAL(out_EXECUTE_QUEUE_OUT_ADDRESS ,_param->_size_instruction_address); + DELETE0_SIGNAL(out_EXECUTE_QUEUE_OUT_DATA ,_param->_size_general_data ); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/test.cpp (revision 112) @@ -126,34 +126,34 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_VAL ," in_WRITE_UNIT_IN_VAL" , Tcontrol_t ); - ALLOC_SC_SIGNAL (out_WRITE_UNIT_IN_ACK ,"out_WRITE_UNIT_IN_ACK" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_CONTEXT_ID ," in_WRITE_UNIT_IN_CONTEXT_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_FRONT_END_ID ," in_WRITE_UNIT_IN_FRONT_END_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_OOO_ENGINE_ID ," in_WRITE_UNIT_IN_OOO_ENGINE_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_PACKET_ID ," in_WRITE_UNIT_IN_PACKET_ID" , Tpacket_t ); -//ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_OPERATION ," in_WRITE_UNIT_IN_OPERATION" , Toperation_t ); -//ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_TYPE ," in_WRITE_UNIT_IN_TYPE" , Ttype_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_WRITE_RD ," in_WRITE_UNIT_IN_WRITE_RD" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_NUM_REG_RD ," in_WRITE_UNIT_IN_NUM_REG_RD" , Tgeneral_address_t); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_DATA_RD ," in_WRITE_UNIT_IN_DATA_RD" , Tgeneral_data_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_WRITE_RE ," in_WRITE_UNIT_IN_WRITE_RE" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_NUM_REG_RE ," in_WRITE_UNIT_IN_NUM_REG_RE" , Tspecial_address_t); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_DATA_RE ," in_WRITE_UNIT_IN_DATA_RE" , Tspecial_data_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_EXCEPTION ," in_WRITE_UNIT_IN_EXCEPTION" , Texception_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_NO_SEQUENCE ," in_WRITE_UNIT_IN_NO_SEQUENCE" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_ADDRESS ," in_WRITE_UNIT_IN_ADDRESS" , Taddress_t ); - ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_VAL ,"out_WRITE_UNIT_OUT_VAL" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_OUT_ACK ," in_WRITE_UNIT_OUT_ACK" , Tcontrol_t ); - ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_CONTEXT_ID ,"out_WRITE_UNIT_OUT_CONTEXT_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_FRONT_END_ID ,"out_WRITE_UNIT_OUT_FRONT_END_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID", Tcontext_t ); - ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_PACKET_ID ,"out_WRITE_UNIT_OUT_PACKET_ID" , Tpacket_t ); -//ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_OPERATION ,"out_WRITE_UNIT_OUT_OPERATION" , Toperation_t ); -//ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_TYPE ,"out_WRITE_UNIT_OUT_TYPE" , Ttype_t ); - ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_FLAGS ,"out_WRITE_UNIT_OUT_FLAGS" , Tspecial_data_t ); - ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_EXCEPTION ,"out_WRITE_UNIT_OUT_EXCEPTION" , Texception_t ); - ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_NO_SEQUENCE ,"out_WRITE_UNIT_OUT_NO_SEQUENCE" , Tcontrol_t ); - ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_ADDRESS ,"out_WRITE_UNIT_OUT_ADDRESS" , Taddress_t ); - ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_DATA ,"out_WRITE_UNIT_OUT_DATA" , Tgeneral_data_t ); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_VAL ," in_WRITE_UNIT_IN_VAL" , Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_WRITE_UNIT_IN_ACK ,"out_WRITE_UNIT_IN_ACK" , Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_CONTEXT_ID ," in_WRITE_UNIT_IN_CONTEXT_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_FRONT_END_ID ," in_WRITE_UNIT_IN_FRONT_END_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_OOO_ENGINE_ID ," in_WRITE_UNIT_IN_OOO_ENGINE_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_PACKET_ID ," in_WRITE_UNIT_IN_PACKET_ID" , Tpacket_t ); +//ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_OPERATION ," in_WRITE_UNIT_IN_OPERATION" , Toperation_t ); +//ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_TYPE ," in_WRITE_UNIT_IN_TYPE" , Ttype_t ); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_WRITE_RD ," in_WRITE_UNIT_IN_WRITE_RD" , Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_NUM_REG_RD ," in_WRITE_UNIT_IN_NUM_REG_RD" , Tgeneral_address_t); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_DATA_RD ," in_WRITE_UNIT_IN_DATA_RD" , Tgeneral_data_t ); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_WRITE_RE ," in_WRITE_UNIT_IN_WRITE_RE" , Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_NUM_REG_RE ," in_WRITE_UNIT_IN_NUM_REG_RE" , Tspecial_address_t); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_DATA_RE ," in_WRITE_UNIT_IN_DATA_RE" , Tspecial_data_t ); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_EXCEPTION ," in_WRITE_UNIT_IN_EXCEPTION" , Texception_t ); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_NO_SEQUENCE ," in_WRITE_UNIT_IN_NO_SEQUENCE" , Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_ADDRESS ," in_WRITE_UNIT_IN_ADDRESS" , Taddress_t ); + ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_VAL ,"out_WRITE_UNIT_OUT_VAL" , Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_WRITE_UNIT_OUT_ACK ," in_WRITE_UNIT_OUT_ACK" , Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_CONTEXT_ID ,"out_WRITE_UNIT_OUT_CONTEXT_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_FRONT_END_ID ,"out_WRITE_UNIT_OUT_FRONT_END_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID", Tcontext_t ); + ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_PACKET_ID ,"out_WRITE_UNIT_OUT_PACKET_ID" , Tpacket_t ); +//ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_OPERATION ,"out_WRITE_UNIT_OUT_OPERATION" , Toperation_t ); +//ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_TYPE ,"out_WRITE_UNIT_OUT_TYPE" , Ttype_t ); + ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_FLAGS ,"out_WRITE_UNIT_OUT_FLAGS" , Tspecial_data_t ); + ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_EXCEPTION ,"out_WRITE_UNIT_OUT_EXCEPTION" , Texception_t ); + ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_NO_SEQUENCE ,"out_WRITE_UNIT_OUT_NO_SEQUENCE" , Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_ADDRESS ,"out_WRITE_UNIT_OUT_ADDRESS" , Taddress_t ); + ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_DATA ,"out_WRITE_UNIT_OUT_DATA" , Tgeneral_data_t ); ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write); ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write); @@ -184,42 +184,42 @@ (*(_Write_unit->in_NRESET)) (*(in_NRESET)); - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_VAL ); - INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_IN_ACK ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_VAL ); + INSTANCE0_SC_SIGNAL(_Write_unit, out_WRITE_UNIT_IN_ACK ); if (_param->_have_port_context_id) - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_CONTEXT_ID ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_CONTEXT_ID ); if (_param->_have_port_front_end_id) - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_FRONT_END_ID ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_FRONT_END_ID ); if (_param->_have_port_ooo_engine_id) - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_OOO_ENGINE_ID ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_OOO_ENGINE_ID ); if (_param->_have_port_rob_ptr) - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_PACKET_ID ); -//INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_OPERATION ); -//INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_TYPE ); - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_WRITE_RD ); - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_NUM_REG_RD ); - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_DATA_RD ); - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_WRITE_RE ); - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_NUM_REG_RE ); - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_DATA_RE ); - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_EXCEPTION ); - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_NO_SEQUENCE ); - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_ADDRESS ); - INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_VAL ); - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_OUT_ACK ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_PACKET_ID ); +//INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_OPERATION ); +//INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_TYPE ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_WRITE_RD ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_NUM_REG_RD ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_DATA_RD ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_WRITE_RE ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_NUM_REG_RE ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_DATA_RE ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_EXCEPTION ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_NO_SEQUENCE ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_IN_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Write_unit, out_WRITE_UNIT_OUT_VAL ); + INSTANCE0_SC_SIGNAL(_Write_unit, in_WRITE_UNIT_OUT_ACK ); if (_param->_have_port_context_id) - INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_CONTEXT_ID ); + INSTANCE0_SC_SIGNAL(_Write_unit, out_WRITE_UNIT_OUT_CONTEXT_ID ); if (_param->_have_port_front_end_id) - INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_FRONT_END_ID ); + INSTANCE0_SC_SIGNAL(_Write_unit, out_WRITE_UNIT_OUT_FRONT_END_ID ); if (_param->_have_port_ooo_engine_id) - INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_OOO_ENGINE_ID); + INSTANCE0_SC_SIGNAL(_Write_unit, out_WRITE_UNIT_OUT_OOO_ENGINE_ID); if (_param->_have_port_rob_ptr) - INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_PACKET_ID ); -//INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_OPERATION ); -//INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_TYPE ); - INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_FLAGS ); - INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_EXCEPTION ); - INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_NO_SEQUENCE ); - INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_ADDRESS ); - INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_DATA ); + INSTANCE0_SC_SIGNAL(_Write_unit, out_WRITE_UNIT_OUT_PACKET_ID ); +//INSTANCE0_SC_SIGNAL(_Write_unit, out_WRITE_UNIT_OUT_OPERATION ); +//INSTANCE0_SC_SIGNAL(_Write_unit, out_WRITE_UNIT_OUT_TYPE ); + INSTANCE0_SC_SIGNAL(_Write_unit, out_WRITE_UNIT_OUT_FLAGS ); + INSTANCE0_SC_SIGNAL(_Write_unit, out_WRITE_UNIT_OUT_EXCEPTION ); + INSTANCE0_SC_SIGNAL(_Write_unit, out_WRITE_UNIT_OUT_NO_SEQUENCE ); + INSTANCE0_SC_SIGNAL(_Write_unit, out_WRITE_UNIT_OUT_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Write_unit, out_WRITE_UNIT_OUT_DATA ); INSTANCE1_SC_SIGNAL(_Write_unit, out_GPR_WRITE_VAL , _param->_nb_gpr_write); INSTANCE1_SC_SIGNAL(_Write_unit, in_GPR_WRITE_ACK , _param->_nb_gpr_write); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/test.cpp (revision 112) @@ -125,34 +125,34 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_VAL ," in_WRITE_QUEUE_IN_VAL" , Tcontrol_t ); - ALLOC_SC_SIGNAL (out_WRITE_QUEUE_IN_ACK ,"out_WRITE_QUEUE_IN_ACK" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_CONTEXT_ID ," in_WRITE_QUEUE_IN_CONTEXT_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_FRONT_END_ID ," in_WRITE_QUEUE_IN_FRONT_END_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_OOO_ENGINE_ID ," in_WRITE_QUEUE_IN_OOO_ENGINE_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_PACKET_ID ," in_WRITE_QUEUE_IN_PACKET_ID" , Tpacket_t ); -//ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_OPERATION ," in_WRITE_QUEUE_IN_OPERATION" , Toperation_t ); -//ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_TYPE ," in_WRITE_QUEUE_IN_TYPE" , Ttype_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_WRITE_RD ," in_WRITE_QUEUE_IN_WRITE_RD" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NUM_REG_RD ," in_WRITE_QUEUE_IN_NUM_REG_RD" , Tgeneral_address_t); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_DATA_RD ," in_WRITE_QUEUE_IN_DATA_RD" , Tgeneral_data_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_WRITE_RE ," in_WRITE_QUEUE_IN_WRITE_RE" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NUM_REG_RE ," in_WRITE_QUEUE_IN_NUM_REG_RE" , Tspecial_address_t); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_DATA_RE ," in_WRITE_QUEUE_IN_DATA_RE" , Tspecial_data_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_EXCEPTION ," in_WRITE_QUEUE_IN_EXCEPTION" , Texception_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NO_SEQUENCE ," in_WRITE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_ADDRESS ," in_WRITE_QUEUE_IN_ADDRESS" , Taddress_t ); - ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_VAL ,"out_WRITE_QUEUE_OUT_VAL" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_OUT_ACK ," in_WRITE_QUEUE_OUT_ACK" , Tcontrol_t ); - ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_CONTEXT_ID ,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_FRONT_END_ID ,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , Tcontext_t ); - ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", Tcontext_t ); - ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_PACKET_ID ,"out_WRITE_QUEUE_OUT_PACKET_ID" , Tpacket_t ); -//ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_OPERATION ,"out_WRITE_QUEUE_OUT_OPERATION" , Toperation_t ); -//ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_TYPE ,"out_WRITE_QUEUE_OUT_TYPE" , Ttype_t ); - ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_FLAGS ,"out_WRITE_QUEUE_OUT_FLAGS" , Tspecial_data_t ); - ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_EXCEPTION ,"out_WRITE_QUEUE_OUT_EXCEPTION" , Texception_t ); - ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); - ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_ADDRESS ,"out_WRITE_QUEUE_OUT_ADDRESS" , Tgeneral_data_t ); - ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_DATA ,"out_WRITE_QUEUE_OUT_DATA" , Taddress_t ); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_VAL ," in_WRITE_QUEUE_IN_VAL" , Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_IN_ACK ,"out_WRITE_QUEUE_IN_ACK" , Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_CONTEXT_ID ," in_WRITE_QUEUE_IN_CONTEXT_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_FRONT_END_ID ," in_WRITE_QUEUE_IN_FRONT_END_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_OOO_ENGINE_ID ," in_WRITE_QUEUE_IN_OOO_ENGINE_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_PACKET_ID ," in_WRITE_QUEUE_IN_PACKET_ID" , Tpacket_t ); +//ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_OPERATION ," in_WRITE_QUEUE_IN_OPERATION" , Toperation_t ); +//ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_TYPE ," in_WRITE_QUEUE_IN_TYPE" , Ttype_t ); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_WRITE_RD ," in_WRITE_QUEUE_IN_WRITE_RD" , Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_NUM_REG_RD ," in_WRITE_QUEUE_IN_NUM_REG_RD" , Tgeneral_address_t); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_DATA_RD ," in_WRITE_QUEUE_IN_DATA_RD" , Tgeneral_data_t ); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_WRITE_RE ," in_WRITE_QUEUE_IN_WRITE_RE" , Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_NUM_REG_RE ," in_WRITE_QUEUE_IN_NUM_REG_RE" , Tspecial_address_t); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_DATA_RE ," in_WRITE_QUEUE_IN_DATA_RE" , Tspecial_data_t ); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_EXCEPTION ," in_WRITE_QUEUE_IN_EXCEPTION" , Texception_t ); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_NO_SEQUENCE ," in_WRITE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_ADDRESS ," in_WRITE_QUEUE_IN_ADDRESS" , Taddress_t ); + ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_VAL ,"out_WRITE_QUEUE_OUT_VAL" , Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_OUT_ACK ," in_WRITE_QUEUE_OUT_ACK" , Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_CONTEXT_ID ,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_FRONT_END_ID ,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , Tcontext_t ); + ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", Tcontext_t ); + ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_PACKET_ID ,"out_WRITE_QUEUE_OUT_PACKET_ID" , Tpacket_t ); +//ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_OPERATION ,"out_WRITE_QUEUE_OUT_OPERATION" , Toperation_t ); +//ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_TYPE ,"out_WRITE_QUEUE_OUT_TYPE" , Ttype_t ); + ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_FLAGS ,"out_WRITE_QUEUE_OUT_FLAGS" , Tspecial_data_t ); + ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_EXCEPTION ,"out_WRITE_QUEUE_OUT_EXCEPTION" , Texception_t ); + ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_ADDRESS ,"out_WRITE_QUEUE_OUT_ADDRESS" , Tgeneral_data_t ); + ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_DATA ,"out_WRITE_QUEUE_OUT_DATA" , Taddress_t ); ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write); ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write); @@ -182,42 +182,42 @@ (*(_Write_queue->in_NRESET)) (*(in_NRESET)); - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_VAL ); - INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_IN_ACK ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_VAL ); + INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_IN_ACK ); if (_param->_have_port_context_id) - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_CONTEXT_ID ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_CONTEXT_ID ); if (_param->_have_port_front_end_id) - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_FRONT_END_ID ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_FRONT_END_ID ); if (_param->_have_port_ooo_engine_id) - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_OOO_ENGINE_ID ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_OOO_ENGINE_ID ); if (_param->_have_port_rob_ptr ) - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_PACKET_ID ); -//INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_OPERATION ); -//INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_TYPE ); - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_WRITE_RD ); - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RD ); - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_DATA_RD ); - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_WRITE_RE ); - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RE ); - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_DATA_RE ); - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_EXCEPTION ); - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NO_SEQUENCE ); - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_ADDRESS ); - INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_VAL ); - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_OUT_ACK ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_PACKET_ID ); +//INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_OPERATION ); +//INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_TYPE ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_WRITE_RD ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RD ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_DATA_RD ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_WRITE_RE ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RE ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_DATA_RE ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_EXCEPTION ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_NO_SEQUENCE ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_VAL ); + INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_OUT_ACK ); if (_param->_have_port_context_id) - INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_CONTEXT_ID ); + INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_CONTEXT_ID ); if (_param->_have_port_front_end_id) - INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_FRONT_END_ID ); + INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_FRONT_END_ID ); if (_param->_have_port_ooo_engine_id) - INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_OOO_ENGINE_ID); + INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_OOO_ENGINE_ID); if (_param->_have_port_rob_ptr ) - INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_PACKET_ID ); -//INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_OPERATION ); -//INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_TYPE ); - INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_FLAGS ); - INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_EXCEPTION ); - INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_NO_SEQUENCE ); - INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_ADDRESS ); - INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_DATA ); + INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_PACKET_ID ); +//INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_OPERATION ); +//INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_TYPE ); + INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_FLAGS ); + INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_EXCEPTION ); + INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_NO_SEQUENCE ); + INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_DATA ); INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_VAL , _param->_nb_gpr_write); INSTANCE1_SC_SIGNAL(_Write_queue, in_GPR_WRITE_ACK , _param->_nb_gpr_write); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_allocation.cpp (revision 112) @@ -51,47 +51,51 @@ // -----[ Interface "Write_queue_in" ]-------------------------------- { - ALLOC_INTERFACE ("write_queue_in", IN, WEST, "Input of write_queue"); + ALLOC0_INTERFACE_BEGIN ("write_queue_in", IN, WEST, "Input of write_queue"); - ALLOC_VALACK_IN ( in_WRITE_QUEUE_IN_VAL,VAL); - ALLOC_VALACK_OUT(out_WRITE_QUEUE_IN_ACK,ACK); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); -// ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); -// ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC0_VALACK_IN ( in_WRITE_QUEUE_IN_VAL,VAL); + ALLOC0_VALACK_OUT(out_WRITE_QUEUE_IN_ACK,ACK); + ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); + ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); +// ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); +// ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data ); + ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); + ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + + ALLOC0_INTERFACE_END(); } // -----[ Interface "Write_queue_out" ]------------------------------- { - ALLOC_INTERFACE ("write_queue_out", OUT, EAST, "Output of write_queue"); + ALLOC0_INTERFACE_BEGIN("write_queue_out", OUT, EAST, "Output of write_queue"); - ALLOC_VALACK_OUT(out_WRITE_QUEUE_OUT_VAL,VAL); - ALLOC_VALACK_IN ( in_WRITE_QUEUE_OUT_ACK,ACK); - ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); - ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); - ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); -// ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); -// ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); - ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_FLAGS ,"flags" ,Tspecial_data_t,_param->_size_special_data ); - ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); - ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); - ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); + ALLOC0_VALACK_OUT(out_WRITE_QUEUE_OUT_VAL,VAL); + ALLOC0_VALACK_IN ( in_WRITE_QUEUE_OUT_ACK,ACK); + ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); +// ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); +// ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_FLAGS ,"flags" ,Tspecial_data_t,_param->_size_special_data ); + ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); + ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); + + ALLOC0_INTERFACE_END(); } // -----[ Interface "gpr_write" ]------------------------------------- { - ALLOC1_INTERFACE("gpr_write", OUT, SOUTH ,"Output of write_queue", _param->_nb_gpr_write); + ALLOC1_INTERFACE_BEGIN("gpr_write", OUT, SOUTH ,"Output of write_queue", _param->_nb_gpr_write); ALLOC1_VALACK_OUT(out_GPR_WRITE_VAL,VAL); @@ -100,9 +104,11 @@ ALLOC1_SIGNAL_OUT(out_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); ALLOC1_SIGNAL_OUT(out_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_write); } // -----[ Interface "spr_write" ]------------------------------------- { - ALLOC1_INTERFACE("spr_write", OUT, SOUTH ,"Output of write_queue", _param->_nb_spr_write); + ALLOC1_INTERFACE_BEGIN("spr_write", OUT, SOUTH ,"Output of write_queue", _param->_nb_spr_write); ALLOC1_VALACK_OUT(out_SPR_WRITE_VAL,VAL); @@ -111,9 +117,11 @@ ALLOC1_SIGNAL_OUT(out_SPR_WRITE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); ALLOC1_SIGNAL_OUT(out_SPR_WRITE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data ); + + ALLOC1_INTERFACE_END(_param->_nb_spr_write); } // -----[ Interface "bypass_write" ]---------------------------------- { - ALLOC1_INTERFACE("bypass_write", OUT, NORTH ,"Output of internal write_queue", _param->_nb_bypass_write); + ALLOC1_INTERFACE_BEGIN("bypass_write", OUT, NORTH ,"Output of internal write_queue", _param->_nb_bypass_write); ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); @@ -124,5 +132,8 @@ ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_register); ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_data ); + + ALLOC1_INTERFACE_END(_param->_nb_bypass_write); } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -29,71 +30,55 @@ delete in_NRESET; - // -----[ Interface "Write_queue_in" ]-------------------------------- - delete in_WRITE_QUEUE_IN_VAL ; - delete out_WRITE_QUEUE_IN_ACK ; - if (_param->_have_port_context_id) - delete in_WRITE_QUEUE_IN_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete in_WRITE_QUEUE_IN_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete in_WRITE_QUEUE_IN_OOO_ENGINE_ID; - if (_param->_have_port_rob_ptr ) - delete in_WRITE_QUEUE_IN_PACKET_ID ; -// delete in_WRITE_QUEUE_IN_OPERATION ; -// delete in_WRITE_QUEUE_IN_TYPE ; - delete in_WRITE_QUEUE_IN_WRITE_RD ; - delete in_WRITE_QUEUE_IN_NUM_REG_RD ; - delete in_WRITE_QUEUE_IN_DATA_RD ; - delete in_WRITE_QUEUE_IN_WRITE_RE ; - delete in_WRITE_QUEUE_IN_NUM_REG_RE ; - delete in_WRITE_QUEUE_IN_DATA_RE ; - delete in_WRITE_QUEUE_IN_EXCEPTION ; - delete in_WRITE_QUEUE_IN_NO_SEQUENCE ; - delete in_WRITE_QUEUE_IN_ADDRESS ; - - // -----[ Interface "Write_queue_out" ]------------------------------- - delete out_WRITE_QUEUE_OUT_VAL ; - delete in_WRITE_QUEUE_OUT_ACK ; - if (_param->_have_port_context_id) - delete out_WRITE_QUEUE_OUT_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete out_WRITE_QUEUE_OUT_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete out_WRITE_QUEUE_OUT_OOO_ENGINE_ID; - if (_param->_have_port_rob_ptr ) - delete out_WRITE_QUEUE_OUT_PACKET_ID ; -// delete out_WRITE_QUEUE_OUT_OPERATION ; -// delete out_WRITE_QUEUE_OUT_TYPE ; - delete out_WRITE_QUEUE_OUT_FLAGS ; - delete out_WRITE_QUEUE_OUT_EXCEPTION ; - delete out_WRITE_QUEUE_OUT_NO_SEQUENCE ; - delete out_WRITE_QUEUE_OUT_ADDRESS ; - delete out_WRITE_QUEUE_OUT_DATA ; - - // -----[ Interface "gpr_write" ]------------------------------------- - delete [] out_GPR_WRITE_VAL ; - delete [] in_GPR_WRITE_ACK ; - if (_param->_have_port_ooo_engine_id) - delete [] out_GPR_WRITE_OOO_ENGINE_ID ; - delete [] out_GPR_WRITE_NUM_REG ; - delete [] out_GPR_WRITE_DATA ; - - // -----[ Interface "spr_write" ]------------------------------------- - delete [] out_SPR_WRITE_VAL ; - delete [] in_SPR_WRITE_ACK ; - if (_param->_have_port_ooo_engine_id) - delete [] out_SPR_WRITE_OOO_ENGINE_ID ; - delete [] out_SPR_WRITE_NUM_REG ; - delete [] out_SPR_WRITE_DATA ; - - // -----[ Interface "bypass_write" ]---------------------------------- - if (_param->_have_port_ooo_engine_id) - delete [] out_BYPASS_WRITE_OOO_ENGINE_ID ; - delete [] out_BYPASS_WRITE_GPR_VAL ; - delete [] out_BYPASS_WRITE_GPR_NUM_REG ; - delete [] out_BYPASS_WRITE_GPR_DATA ; - delete [] out_BYPASS_WRITE_SPR_VAL ; - delete [] out_BYPASS_WRITE_SPR_NUM_REG ; - delete [] out_BYPASS_WRITE_SPR_DATA ; + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_VAL ,1); + DELETE0_SIGNAL(out_WRITE_QUEUE_IN_ACK ,1); + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_FRONT_END_ID ,_param->_size_front_end_id ); + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_OOO_ENGINE_ID ,_param->_size_ooo_engine_id ); + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_PACKET_ID ,_param->_size_rob_ptr ); +// DELETE0_SIGNAL( in_WRITE_QUEUE_IN_OPERATION ,_param->_size_operation ); +// DELETE0_SIGNAL( in_WRITE_QUEUE_IN_TYPE ,_param->_size_type ); + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_WRITE_RD ,1 ); + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_NUM_REG_RD ,_param->_size_general_register ); + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_DATA_RD ,_param->_size_general_data ); + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_WRITE_RE ,1 ); + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_NUM_REG_RE ,_param->_size_special_register ); + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_DATA_RE ,_param->_size_special_data ); + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_EXCEPTION ,_param->_size_exception ); + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_NO_SEQUENCE ,1 ); + DELETE0_SIGNAL( in_WRITE_QUEUE_IN_ADDRESS ,_param->_size_instruction_address); + + DELETE0_SIGNAL(out_WRITE_QUEUE_OUT_VAL ,1); + DELETE0_SIGNAL( in_WRITE_QUEUE_OUT_ACK ,1); + DELETE0_SIGNAL(out_WRITE_QUEUE_OUT_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL(out_WRITE_QUEUE_OUT_FRONT_END_ID ,_param->_size_front_end_id ); + DELETE0_SIGNAL(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,_param->_size_ooo_engine_id); + DELETE0_SIGNAL(out_WRITE_QUEUE_OUT_PACKET_ID ,_param->_size_rob_ptr ); +// DELETE0_SIGNAL(out_WRITE_QUEUE_OUT_OPERATION ,_param->_size_operation ); +// DELETE0_SIGNAL(out_WRITE_QUEUE_OUT_TYPE ,_param->_size_type ); + DELETE0_SIGNAL(out_WRITE_QUEUE_OUT_FLAGS ,_param->_size_special_data ); + DELETE0_SIGNAL(out_WRITE_QUEUE_OUT_EXCEPTION ,_param->_size_exception ); + DELETE0_SIGNAL(out_WRITE_QUEUE_OUT_NO_SEQUENCE ,1 ); + DELETE0_SIGNAL(out_WRITE_QUEUE_OUT_ADDRESS ,_param->_size_instruction_address); + DELETE0_SIGNAL(out_WRITE_QUEUE_OUT_DATA ,_param->_size_general_data ); + + DELETE1_SIGNAL(out_GPR_WRITE_VAL , _param->_nb_gpr_write,1); + DELETE1_SIGNAL( in_GPR_WRITE_ACK , _param->_nb_gpr_write,1); + DELETE1_SIGNAL(out_GPR_WRITE_OOO_ENGINE_ID, _param->_nb_gpr_write,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL(out_GPR_WRITE_NUM_REG , _param->_nb_gpr_write,_param->_size_general_register); + DELETE1_SIGNAL(out_GPR_WRITE_DATA , _param->_nb_gpr_write,_param->_size_general_data ); + + DELETE1_SIGNAL(out_SPR_WRITE_VAL , _param->_nb_spr_write,1); + DELETE1_SIGNAL( in_SPR_WRITE_ACK , _param->_nb_spr_write,1); + DELETE1_SIGNAL(out_SPR_WRITE_OOO_ENGINE_ID, _param->_nb_spr_write,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL(out_SPR_WRITE_NUM_REG , _param->_nb_spr_write,_param->_size_special_register); + DELETE1_SIGNAL(out_SPR_WRITE_DATA , _param->_nb_spr_write,_param->_size_special_data ); + + DELETE1_SIGNAL(out_BYPASS_WRITE_OOO_ENGINE_ID,_param->_nb_bypass_write,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL(out_BYPASS_WRITE_GPR_VAL ,_param->_nb_bypass_write,1 ); + DELETE1_SIGNAL(out_BYPASS_WRITE_GPR_NUM_REG ,_param->_nb_bypass_write,_param->_size_general_register); + DELETE1_SIGNAL(out_BYPASS_WRITE_GPR_DATA ,_param->_nb_bypass_write,_param->_size_general_data ); + DELETE1_SIGNAL(out_BYPASS_WRITE_SPR_VAL ,_param->_nb_bypass_write,1 ); + DELETE1_SIGNAL(out_BYPASS_WRITE_SPR_NUM_REG ,_param->_nb_bypass_write,_param->_size_special_register); + DELETE1_SIGNAL(out_BYPASS_WRITE_SPR_DATA ,_param->_nb_bypass_write,_param->_size_special_data ); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp (revision 112) @@ -57,47 +57,51 @@ // -----[ Interface "write_unit_in" ]-------------------------------- { - ALLOC_INTERFACE ("write_unit_in", IN, WEST, "Input of write_unit"); - - ALLOC_VALACK_IN ( in_WRITE_UNIT_IN_VAL,VAL); - ALLOC_VALACK_OUT(out_WRITE_UNIT_IN_ACK,ACK); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); -// ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); -// ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC0_INTERFACE_BEGIN("write_unit_in", IN, WEST, "Input of write_unit"); + + ALLOC0_VALACK_IN ( in_WRITE_UNIT_IN_VAL,VAL); + ALLOC0_VALACK_OUT(out_WRITE_UNIT_IN_ACK,ACK); + ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); + ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); +// ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); +// ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data ); + ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); + ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + + ALLOC0_INTERFACE_END(); } // -----[ Interface "write_unit_out" ]------------------------------- { - ALLOC_INTERFACE ("write_unit_out", OUT, EAST, "Output of write_unit"); - - ALLOC_VALACK_OUT(out_WRITE_UNIT_OUT_VAL,VAL); - ALLOC_VALACK_IN ( in_WRITE_UNIT_OUT_ACK,ACK); - ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); - ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); - ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); -// ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); -// ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); - ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_FLAGS ,"flags" ,Tspecial_data_t,_param->_size_special_data ); - ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); - ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); - ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); + ALLOC0_INTERFACE_BEGIN("write_unit_out", OUT, EAST, "Output of write_unit"); + + ALLOC0_VALACK_OUT(out_WRITE_UNIT_OUT_VAL,VAL); + ALLOC0_VALACK_IN ( in_WRITE_UNIT_OUT_ACK,ACK); + ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); +// ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); +// ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_FLAGS ,"flags" ,Tspecial_data_t,_param->_size_special_data ); + ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); + ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); + + ALLOC0_INTERFACE_END(); } // -----[ Interface "gpr_write" ]------------------------------------- { - ALLOC1_INTERFACE("gpr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_gpr_write); + ALLOC1_INTERFACE_BEGIN("gpr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_gpr_write); ALLOC1_VALACK_OUT(out_GPR_WRITE_VAL,VAL); @@ -106,9 +110,11 @@ ALLOC1_SIGNAL_OUT(out_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); ALLOC1_SIGNAL_OUT(out_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_write); } // -----[ Interface "spr_write" ]------------------------------------- { - ALLOC1_INTERFACE("spr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_spr_write); + ALLOC1_INTERFACE_BEGIN("spr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_spr_write); ALLOC1_VALACK_OUT(out_SPR_WRITE_VAL,VAL); @@ -117,9 +123,11 @@ ALLOC1_SIGNAL_OUT(out_SPR_WRITE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); ALLOC1_SIGNAL_OUT(out_SPR_WRITE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data ); + + ALLOC1_INTERFACE_END(_param->_nb_spr_write); } // -----[ Interface "bypass_write" ]---------------------------------- { - ALLOC1_INTERFACE("bypass_write", OUT, NORTH ,"Output of internal write_unit", _param->_nb_bypass_write); + ALLOC1_INTERFACE_BEGIN("bypass_write", OUT, NORTH ,"Output of internal write_unit", _param->_nb_bypass_write); ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); @@ -130,6 +138,7 @@ ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_register); ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_data ); - } - + + ALLOC1_INTERFACE_END(_param->_nb_bypass_write); + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -28,73 +29,57 @@ delete in_NRESET; - // -----[ Interface "write_unit_in" ]-------------------------------- - delete in_WRITE_UNIT_IN_VAL ; - delete out_WRITE_UNIT_IN_ACK ; - if (_param->_have_port_context_id) - delete in_WRITE_UNIT_IN_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete in_WRITE_UNIT_IN_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete in_WRITE_UNIT_IN_OOO_ENGINE_ID; - if (_param->_have_port_rob_ptr) - delete in_WRITE_UNIT_IN_PACKET_ID ; -// delete in_WRITE_UNIT_IN_OPERATION ; -// delete in_WRITE_UNIT_IN_TYPE ; - delete in_WRITE_UNIT_IN_WRITE_RD ; - delete in_WRITE_UNIT_IN_NUM_REG_RD ; - delete in_WRITE_UNIT_IN_DATA_RD ; - delete in_WRITE_UNIT_IN_WRITE_RE ; - delete in_WRITE_UNIT_IN_NUM_REG_RE ; - delete in_WRITE_UNIT_IN_DATA_RE ; - delete in_WRITE_UNIT_IN_EXCEPTION ; - delete in_WRITE_UNIT_IN_NO_SEQUENCE ; - delete in_WRITE_UNIT_IN_ADDRESS ; + DELETE0_SIGNAL( in_WRITE_UNIT_IN_VAL ,1); + DELETE0_SIGNAL(out_WRITE_UNIT_IN_ACK ,1); + DELETE0_SIGNAL( in_WRITE_UNIT_IN_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL( in_WRITE_UNIT_IN_FRONT_END_ID ,_param->_size_front_end_id ); + DELETE0_SIGNAL( in_WRITE_UNIT_IN_OOO_ENGINE_ID,_param->_size_ooo_engine_id ); + DELETE0_SIGNAL( in_WRITE_UNIT_IN_PACKET_ID ,_param->_size_rob_ptr ); +// DELETE0_SIGNAL( in_WRITE_UNIT_IN_OPERATION ,_param->_size_operation ); +// DELETE0_SIGNAL( in_WRITE_UNIT_IN_TYPE ,_param->_size_type ); + DELETE0_SIGNAL( in_WRITE_UNIT_IN_WRITE_RD ,1 ); + DELETE0_SIGNAL( in_WRITE_UNIT_IN_NUM_REG_RD ,_param->_size_general_register ); + DELETE0_SIGNAL( in_WRITE_UNIT_IN_DATA_RD ,_param->_size_general_data ); + DELETE0_SIGNAL( in_WRITE_UNIT_IN_WRITE_RE ,1 ); + DELETE0_SIGNAL( in_WRITE_UNIT_IN_NUM_REG_RE ,_param->_size_special_register ); + DELETE0_SIGNAL( in_WRITE_UNIT_IN_DATA_RE ,_param->_size_special_data ); + DELETE0_SIGNAL( in_WRITE_UNIT_IN_EXCEPTION ,_param->_size_exception ); + DELETE0_SIGNAL( in_WRITE_UNIT_IN_NO_SEQUENCE ,1 ); + DELETE0_SIGNAL( in_WRITE_UNIT_IN_ADDRESS ,_param->_size_instruction_address); + + DELETE0_SIGNAL(out_WRITE_UNIT_OUT_VAL ,1); + DELETE0_SIGNAL( in_WRITE_UNIT_OUT_ACK ,1); + DELETE0_SIGNAL(out_WRITE_UNIT_OUT_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL(out_WRITE_UNIT_OUT_FRONT_END_ID ,_param->_size_front_end_id ); + DELETE0_SIGNAL(out_WRITE_UNIT_OUT_OOO_ENGINE_ID,_param->_size_ooo_engine_id); + DELETE0_SIGNAL(out_WRITE_UNIT_OUT_PACKET_ID ,_param->_size_rob_ptr ); +// DELETE0_SIGNAL(out_WRITE_UNIT_OUT_OPERATION ,_param->_size_operation ); +// DELETE0_SIGNAL(out_WRITE_UNIT_OUT_TYPE ,_param->_size_type ); + DELETE0_SIGNAL(out_WRITE_UNIT_OUT_FLAGS ,_param->_size_special_data ); + DELETE0_SIGNAL(out_WRITE_UNIT_OUT_EXCEPTION ,_param->_size_exception ); + DELETE0_SIGNAL(out_WRITE_UNIT_OUT_NO_SEQUENCE ,1 ); + DELETE0_SIGNAL(out_WRITE_UNIT_OUT_ADDRESS ,_param->_size_instruction_address); + DELETE0_SIGNAL(out_WRITE_UNIT_OUT_DATA ,_param->_size_general_data ); + + DELETE1_SIGNAL(out_GPR_WRITE_VAL , _param->_nb_gpr_write,1); + DELETE1_SIGNAL( in_GPR_WRITE_ACK , _param->_nb_gpr_write,1); + DELETE1_SIGNAL(out_GPR_WRITE_OOO_ENGINE_ID, _param->_nb_gpr_write,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL(out_GPR_WRITE_NUM_REG , _param->_nb_gpr_write,_param->_size_general_register); + DELETE1_SIGNAL(out_GPR_WRITE_DATA , _param->_nb_gpr_write,_param->_size_general_data ); + + DELETE1_SIGNAL(out_SPR_WRITE_VAL , _param->_nb_spr_write,1); + DELETE1_SIGNAL( in_SPR_WRITE_ACK , _param->_nb_spr_write,1); + DELETE1_SIGNAL(out_SPR_WRITE_OOO_ENGINE_ID, _param->_nb_spr_write,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL(out_SPR_WRITE_NUM_REG , _param->_nb_spr_write,_param->_size_special_register); + DELETE1_SIGNAL(out_SPR_WRITE_DATA , _param->_nb_spr_write,_param->_size_special_data ); + + DELETE1_SIGNAL(out_BYPASS_WRITE_OOO_ENGINE_ID, _param->_nb_bypass_write,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL(out_BYPASS_WRITE_GPR_VAL , _param->_nb_bypass_write,1 ); + DELETE1_SIGNAL(out_BYPASS_WRITE_GPR_NUM_REG , _param->_nb_bypass_write,_param->_size_general_register); + DELETE1_SIGNAL(out_BYPASS_WRITE_GPR_DATA , _param->_nb_bypass_write,_param->_size_general_data ); + DELETE1_SIGNAL(out_BYPASS_WRITE_SPR_VAL , _param->_nb_bypass_write,1 ); + DELETE1_SIGNAL(out_BYPASS_WRITE_SPR_NUM_REG , _param->_nb_bypass_write,_param->_size_special_register); + DELETE1_SIGNAL(out_BYPASS_WRITE_SPR_DATA , _param->_nb_bypass_write,_param->_size_special_data ); + } - // -----[ Interface "write_unit_out" ]------------------------------- - delete out_WRITE_UNIT_OUT_VAL ; - delete in_WRITE_UNIT_OUT_ACK ; - if (_param->_have_port_context_id) - delete out_WRITE_UNIT_OUT_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete out_WRITE_UNIT_OUT_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete out_WRITE_UNIT_OUT_OOO_ENGINE_ID; - if (_param->_have_port_rob_ptr) - delete out_WRITE_UNIT_OUT_PACKET_ID ; -// delete out_WRITE_UNIT_OUT_OPERATION ; -// delete out_WRITE_UNIT_OUT_TYPE ; - delete out_WRITE_UNIT_OUT_FLAGS ; - delete out_WRITE_UNIT_OUT_EXCEPTION ; - delete out_WRITE_UNIT_OUT_NO_SEQUENCE ; - delete out_WRITE_UNIT_OUT_ADDRESS ; - delete out_WRITE_UNIT_OUT_DATA ; - - // -----[ Interface "gpr_write" ]------------------------------------- - delete [] out_GPR_WRITE_VAL ; - delete [] in_GPR_WRITE_ACK ; - if (_param->_have_port_ooo_engine_id) - delete [] out_GPR_WRITE_OOO_ENGINE_ID ; - delete [] out_GPR_WRITE_NUM_REG ; - delete [] out_GPR_WRITE_DATA ; - - // -----[ Interface "spr_write" ]------------------------------------- - delete [] out_SPR_WRITE_VAL ; - delete [] in_SPR_WRITE_ACK ; - if (_param->_have_port_ooo_engine_id) - delete [] out_SPR_WRITE_OOO_ENGINE_ID ; - delete [] out_SPR_WRITE_NUM_REG ; - delete [] out_SPR_WRITE_DATA ; - - // -----[ Interface "bypass_write" ]---------------------------------- - if (_param->_have_port_ooo_engine_id) - delete [] out_BYPASS_WRITE_OOO_ENGINE_ID ; - delete [] out_BYPASS_WRITE_GPR_VAL ; - delete [] out_BYPASS_WRITE_GPR_NUM_REG ; - delete [] out_BYPASS_WRITE_GPR_DATA ; - delete [] out_BYPASS_WRITE_SPR_VAL ; - delete [] out_BYPASS_WRITE_SPR_NUM_REG ; - delete [] out_BYPASS_WRITE_SPR_DATA ; - - } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_allocation.cpp (revision 112) @@ -58,5 +58,5 @@ // ~~~~~[ Interface "execute_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("execute_unit_out", IN, EAST, "Output of execution_unit", _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + ALLOC2_INTERFACE_BEGIN("execute_unit_out", IN, EAST, "Output of execution_unit", _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); _ALLOC2_VALACK_IN ( in_EXECUTE_UNIT_OUT_VAL,VAL, _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); @@ -77,9 +77,11 @@ _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address, _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); } // ~~~~~[ Interface "write_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("write_unit_in", OUT, WEST, "Input of write_unit", _param->_nb_write_unit); + ALLOC1_INTERFACE_BEGIN("write_unit_in", OUT, WEST, "Input of write_unit", _param->_nb_write_unit); ALLOC1_VALACK_OUT(out_WRITE_UNIT_IN_VAL,VAL); @@ -100,4 +102,6 @@ ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + + ALLOC1_INTERFACE_END(_param->_nb_write_unit); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -105,13 +109,5 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - _destination = new std::list ** [_param->_nb_execute_unit]; - for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - { - _destination [i] = new std::list * [_param->_nb_execute_unit_port[i]]; - for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) - { - _destination [i][j] = new std::list [_param->_nb_thread]; - } - } + ALLOC3(_destination,std::list,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1],_param->_nb_thread); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_deallocation.cpp (revision 112) @@ -65,6 +65,7 @@ DELETE1_SIGNAL(out_WRITE_UNIT_IN_ADDRESS , _param->_nb_write_unit,_param->_size_general_data ); - delete [] _destination; + DELETE3(_destination,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1],_param->_nb_thread); } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_allocation.cpp (revision 112) @@ -57,5 +57,5 @@ // ~~~~~[ Interface "read_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("read_unit_out", IN, EAST, "Output of read_unit",_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_INTERFACE_BEGIN("read_unit_out", IN, EAST, "Output of read_unit",_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); _ALLOC2_VALACK_IN ( in_READ_UNIT_OUT_VAL,VAL,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); @@ -78,8 +78,10 @@ _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); } // ~~~~~[ Interface "execute_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("execute_unit_in", OUT, WEST, "Input of execute_unit", _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + ALLOC2_INTERFACE_BEGIN("execute_unit_in", OUT, WEST, "Input of execute_unit", _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); _ALLOC2_VALACK_OUT(out_EXECUTE_UNIT_IN_VAL,VAL, _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); @@ -102,4 +104,6 @@ _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_DATA_RB ,"DATA_RB" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_NUM_REG_RD ,"NUM_REG_RD" ,Tgeneral_address_t,_param->_size_general_register , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + + ALLOC2_INTERFACE_END(_param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); } @@ -107,13 +111,5 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - _destination = new std::list ** [_param->_nb_read_unit]; - for (uint32_t i=0; i<_param->_nb_read_unit; i++) - { - _destination [i] = new std::list * [_param->_nb_thread]; - for (uint32_t j=0; j<_param->_nb_thread; j++) - { - _destination [i][j] = new std::list [_param->_nb_type]; - } - } + ALLOC3(_destination,std::list,_param->_nb_read_unit,_param->_nb_thread,_param->_nb_type);; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_deallocation.cpp (revision 112) @@ -69,5 +69,5 @@ DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_NUM_REG_RD , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_general_register ); - delete [] _destination; + DELETE3(_destination,_param->_nb_read_unit,_param->_nb_thread,_param->_nb_type);; } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_allocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/include/Register_unit_Glue.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -50,353 +51,157 @@ out_CONST_1 = interface->set_signal_out ("const_1",1); - // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_GPR_READ_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_read]; - out_GPR_READ_ACK = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_read]; - if (_param->_have_port_ooo_engine_id == true) - in_GPR_READ_OOO_ENGINE_ID = new SC_IN (Tcontext_t ) * [_param->_nb_gpr_read]; - out_GPR_READ_DATA = new SC_OUT(Tgeneral_data_t ) * [_param->_nb_gpr_read]; - out_GPR_READ_DATA_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_read]; - - out_GPR_READ_REGISTERFILE_VAL = new SC_OUT(Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_GPR_READ_REGISTERFILE_ACK = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_GPR_READ_REGISTERFILE_DATA = new SC_IN (Tgeneral_data_t ) ** [_param->_nb_ooo_engine]; - - out_GPR_READ_STATUS_VAL = new SC_OUT(Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_GPR_READ_STATUS_ACK = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_GPR_READ_STATUS_DATA_VAL = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - out_GPR_READ_REGISTERFILE_VAL [i] = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_read]; - in_GPR_READ_REGISTERFILE_ACK [i] = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_read]; - in_GPR_READ_REGISTERFILE_DATA [i] = new SC_IN (Tgeneral_data_t ) * [_param->_nb_gpr_read]; - - out_GPR_READ_STATUS_VAL [i] = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_read]; - in_GPR_READ_STATUS_ACK [i] = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_read]; - in_GPR_READ_STATUS_DATA_VAL [i] = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_read]; - } - - for (uint32_t j=0; j<_param->_nb_gpr_read; j++) - { - Interface_fifo * interface = _interfaces->set_interface("gpr_read_"+toString(j) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to read generalist register" -#endif - ); - - in_GPR_READ_VAL [j] = interface->set_signal_valack_in (VAL); - out_GPR_READ_ACK [j] = interface->set_signal_valack_out (ACK); - if (_param->_have_port_ooo_engine_id == true) - in_GPR_READ_OOO_ENGINE_ID [j] = interface->set_signal_in ("ooo_engine_id", _param->_size_ooo_engine_id); - out_GPR_READ_DATA [j] = interface->set_signal_out ("data" , _param->_size_general_data); - out_GPR_READ_DATA_VAL [j] = interface->set_signal_out ("data_val" , 1); - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - { - Interface_fifo * interface = _interfaces->set_interface("gpr_read_registerfile_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to read generalist register - from/to register file" -#endif - ); - - out_GPR_READ_REGISTERFILE_VAL [i][j] = interface->set_signal_valack_out (VAL); - in_GPR_READ_REGISTERFILE_ACK [i][j] = interface->set_signal_valack_in (ACK); - in_GPR_READ_REGISTERFILE_DATA [i][j] = interface->set_signal_in ("data" , _param->_size_general_data); - } - { - Interface_fifo * interface = _interfaces->set_interface("gpr_read_status_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to read generalist register - from/to status" -#endif - ); - - - out_GPR_READ_STATUS_VAL [i][j] = interface->set_signal_valack_out (VAL); - in_GPR_READ_STATUS_ACK [i][j] = interface->set_signal_valack_in (ACK); - in_GPR_READ_STATUS_DATA_VAL [i][j] = interface->set_signal_in ("data_val" , 1); - } - } - } - - // ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_SPR_READ_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_read]; - out_SPR_READ_ACK = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_read]; - if (_param->_have_port_ooo_engine_id == true) - in_SPR_READ_OOO_ENGINE_ID = new SC_IN (Tcontext_t ) * [_param->_nb_spr_read]; - out_SPR_READ_DATA = new SC_OUT(Tspecial_data_t ) * [_param->_nb_spr_read]; - out_SPR_READ_DATA_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_read]; - - out_SPR_READ_REGISTERFILE_VAL = new SC_OUT(Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_SPR_READ_REGISTERFILE_ACK = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_SPR_READ_REGISTERFILE_DATA = new SC_IN (Tspecial_data_t ) ** [_param->_nb_ooo_engine]; - - out_SPR_READ_STATUS_VAL = new SC_OUT(Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_SPR_READ_STATUS_ACK = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_SPR_READ_STATUS_DATA_VAL = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - out_SPR_READ_REGISTERFILE_VAL [i] = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_read]; - in_SPR_READ_REGISTERFILE_ACK [i] = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_read]; - in_SPR_READ_REGISTERFILE_DATA [i] = new SC_IN (Tspecial_data_t ) * [_param->_nb_spr_read]; - - out_SPR_READ_STATUS_VAL [i] = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_read]; - in_SPR_READ_STATUS_ACK [i] = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_read]; - in_SPR_READ_STATUS_DATA_VAL [i] = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_read]; - } - - for (uint32_t j=0; j<_param->_nb_spr_read; j++) - { - Interface_fifo * interface = _interfaces->set_interface("spr_read_"+toString(j) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to read special register" -#endif - ); - - in_SPR_READ_VAL [j] = interface->set_signal_valack_in (VAL); - out_SPR_READ_ACK [j] = interface->set_signal_valack_out (ACK); - if (_param->_have_port_ooo_engine_id == true) - in_SPR_READ_OOO_ENGINE_ID [j] = interface->set_signal_in ("ooo_engine_id", _param->_size_ooo_engine_id); - out_SPR_READ_DATA [j] = interface->set_signal_out ("data" , _param->_size_special_data); - out_SPR_READ_DATA_VAL [j] = interface->set_signal_out ("data_val" , 1); - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - { - Interface_fifo * interface = _interfaces->set_interface("spr_read_registerfile_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to read special register - from/to register file" -#endif - ); - - out_SPR_READ_REGISTERFILE_VAL [i][j] = interface->set_signal_valack_out (VAL); - in_SPR_READ_REGISTERFILE_ACK [i][j] = interface->set_signal_valack_in (ACK); - in_SPR_READ_REGISTERFILE_DATA [i][j] = interface->set_signal_in ("data" , _param->_size_special_data); - } - { - Interface_fifo * interface = _interfaces->set_interface("spr_read_status_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to read special register - from/to status" -#endif - ); - - - out_SPR_READ_STATUS_VAL [i][j] = interface->set_signal_valack_out (VAL); - in_SPR_READ_STATUS_ACK [i][j] = interface->set_signal_valack_in (ACK); - in_SPR_READ_STATUS_DATA_VAL [i][j] = interface->set_signal_in ("data_val" , 1); - } - } - } - - // ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_GPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_write]; - out_GPR_WRITE_ACK = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_write]; - if (_param->_have_port_ooo_engine_id == true) - in_GPR_WRITE_OOO_ENGINE_ID = new SC_IN (Tcontext_t ) * [_param->_nb_gpr_write]; - - out_GPR_WRITE_REGISTERFILE_VAL = new SC_OUT(Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_GPR_WRITE_REGISTERFILE_ACK = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - - out_GPR_WRITE_STATUS_VAL = new SC_OUT(Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_GPR_WRITE_STATUS_ACK = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - out_GPR_WRITE_REGISTERFILE_VAL [i] = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_write]; - in_GPR_WRITE_REGISTERFILE_ACK [i] = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_write]; - - out_GPR_WRITE_STATUS_VAL [i] = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_write]; - in_GPR_WRITE_STATUS_ACK [i] = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_write]; - } - - for (uint32_t j=0; j<_param->_nb_gpr_write; j++) - { - Interface_fifo * interface = _interfaces->set_interface("gpr_write_"+toString(j) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to write generalist register" -#endif - ); - - in_GPR_WRITE_VAL [j] = interface->set_signal_valack_in (VAL); - out_GPR_WRITE_ACK [j] = interface->set_signal_valack_out (ACK); - if (_param->_have_port_ooo_engine_id == true) - in_GPR_WRITE_OOO_ENGINE_ID [j] = interface->set_signal_in ("ooo_engine_id", _param->_size_ooo_engine_id); - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - { - Interface_fifo * interface = _interfaces->set_interface("gpr_write_registerfile_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to write generalist register - from/to register file" -#endif - ); - - out_GPR_WRITE_REGISTERFILE_VAL [i][j] = interface->set_signal_valack_out (VAL); - in_GPR_WRITE_REGISTERFILE_ACK [i][j] = interface->set_signal_valack_in (ACK); - } - { - Interface_fifo * interface = _interfaces->set_interface("gpr_write_status_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to write generalist register - from/to status" -#endif - ); - - - out_GPR_WRITE_STATUS_VAL [i][j] = interface->set_signal_valack_out (VAL); - in_GPR_WRITE_STATUS_ACK [i][j] = interface->set_signal_valack_in (ACK); - } - } - } - - // ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_SPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_write]; - out_SPR_WRITE_ACK = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_write]; - if (_param->_have_port_ooo_engine_id == true) - in_SPR_WRITE_OOO_ENGINE_ID = new SC_IN (Tcontext_t ) * [_param->_nb_spr_write]; - - out_SPR_WRITE_REGISTERFILE_VAL = new SC_OUT(Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_SPR_WRITE_REGISTERFILE_ACK = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - - out_SPR_WRITE_STATUS_VAL = new SC_OUT(Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_SPR_WRITE_STATUS_ACK = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - out_SPR_WRITE_REGISTERFILE_VAL [i] = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_write]; - in_SPR_WRITE_REGISTERFILE_ACK [i] = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_write]; - - out_SPR_WRITE_STATUS_VAL [i] = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_write]; - in_SPR_WRITE_STATUS_ACK [i] = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_write]; - } - - for (uint32_t j=0; j<_param->_nb_spr_write; j++) - { - Interface_fifo * interface = _interfaces->set_interface("spr_write_"+toString(j) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to write special register" -#endif - ); - - in_SPR_WRITE_VAL [j] = interface->set_signal_valack_in (VAL); - out_SPR_WRITE_ACK [j] = interface->set_signal_valack_out (ACK); - if (_param->_have_port_ooo_engine_id == true) - in_SPR_WRITE_OOO_ENGINE_ID [j] = interface->set_signal_in ("ooo_engine_id", _param->_size_ooo_engine_id); - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - { - Interface_fifo * interface = _interfaces->set_interface("spr_write_registerfile_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to write special register - from/to register file" -#endif - ); - - out_SPR_WRITE_REGISTERFILE_VAL [i][j] = interface->set_signal_valack_out (VAL); - in_SPR_WRITE_REGISTERFILE_ACK [i][j] = interface->set_signal_valack_in (ACK); - } - { - Interface_fifo * interface = _interfaces->set_interface("spr_write_status_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to write special register - from/to status" -#endif - ); - - - out_SPR_WRITE_STATUS_VAL [i][j] = interface->set_signal_valack_out (VAL); - in_SPR_WRITE_STATUS_ACK [i][j] = interface->set_signal_valack_in (ACK); - } - } - } - - // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_INSERT_ROB_VAL = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - out_INSERT_ROB_ACK = new SC_OUT(Tcontrol_t) ** [_param->_nb_ooo_engine]; - in_INSERT_ROB_RD_USE = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - in_INSERT_ROB_RE_USE = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - out_INSERT_ROB_GPR_STATUS_VAL = new SC_OUT(Tcontrol_t) ** [_param->_nb_ooo_engine]; - in_INSERT_ROB_GPR_STATUS_ACK = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - out_INSERT_ROB_SPR_STATUS_VAL = new SC_OUT(Tcontrol_t) ** [_param->_nb_ooo_engine]; - in_INSERT_ROB_SPR_STATUS_ACK = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x=_param->_nb_inst_insert_rob [i]; - - in_INSERT_ROB_VAL [i] = new SC_IN (Tcontrol_t) * [x]; - out_INSERT_ROB_ACK [i] = new SC_OUT(Tcontrol_t) * [x]; - in_INSERT_ROB_RD_USE [i] = new SC_IN (Tcontrol_t) * [x]; - in_INSERT_ROB_RE_USE [i] = new SC_IN (Tcontrol_t) * [x]; - out_INSERT_ROB_GPR_STATUS_VAL [i] = new SC_OUT(Tcontrol_t) * [x]; - in_INSERT_ROB_GPR_STATUS_ACK [i] = new SC_IN (Tcontrol_t) * [x]; - out_INSERT_ROB_SPR_STATUS_VAL [i] = new SC_OUT(Tcontrol_t) * [x]; - in_INSERT_ROB_SPR_STATUS_ACK [i] = new SC_IN (Tcontrol_t) * [x]; - - for (uint32_t j=0; jset_interface("insert_rob_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,WEST - ,"Interface to update status (insert)" -#endif - ); - - in_INSERT_ROB_VAL [i][j] = interface->set_signal_valack_in (VAL); - out_INSERT_ROB_ACK [i][j] = interface->set_signal_valack_out(ACK); - in_INSERT_ROB_RD_USE [i][j] = interface->set_signal_in ("rd_use", 1); - in_INSERT_ROB_RE_USE [i][j] = interface->set_signal_in ("re_use", 1); - } - { - Interface_fifo * interface = _interfaces->set_interface("insert_rob_gpr_status_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,EAST - ,"Interface to update status (insert)" -#endif - ); - - out_INSERT_ROB_GPR_STATUS_VAL [i][j] = interface->set_signal_valack_out(VAL); - in_INSERT_ROB_GPR_STATUS_ACK [i][j] = interface->set_signal_valack_in (ACK); - } - { - Interface_fifo * interface = _interfaces->set_interface("insert_rob_spr_status_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,EAST - ,"Interface to update status (insert)" -#endif - ); - - out_INSERT_ROB_SPR_STATUS_VAL [i][j] = interface->set_signal_valack_out(VAL); - in_INSERT_ROB_SPR_STATUS_ACK [i][j] = interface->set_signal_valack_in (ACK); - } - } - } + // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("gpr_read",IN,NORTH,_("Interface to read generalist register"),_param->_nb_gpr_read); + + ALLOC1_VALACK_IN ( in_GPR_READ_VAL ,VAL); + ALLOC1_VALACK_OUT(out_GPR_READ_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_GPR_READ_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t , _param->_size_ooo_engine_id); + ALLOC1_SIGNAL_OUT(out_GPR_READ_DATA ,"data" ,Tgeneral_data_t, _param->_size_general_data); + ALLOC1_SIGNAL_OUT(out_GPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t , 1); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_read); + } + + { + ALLOC2_INTERFACE_BEGIN("gpr_read_registerfile",IN,NORTH,_("Interface to read generalist register - from/to register file"),_param->_nb_ooo_engine,_param->_nb_gpr_read); + + ALLOC2_VALACK_OUT(out_GPR_READ_REGISTERFILE_VAL ,VAL); + ALLOC2_VALACK_IN ( in_GPR_READ_REGISTERFILE_ACK ,ACK); + ALLOC2_SIGNAL_IN ( in_GPR_READ_REGISTERFILE_DATA,"data",Tgeneral_data_t,_param->_size_general_data); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_gpr_read); + } + + { + ALLOC2_INTERFACE_BEGIN("gpr_read_status",IN,NORTH,_("Interface to read generalist register - from/to register file"),_param->_nb_ooo_engine,_param->_nb_gpr_read); + + ALLOC2_VALACK_OUT(out_GPR_READ_STATUS_VAL ,VAL); + ALLOC2_VALACK_IN ( in_GPR_READ_STATUS_ACK ,ACK); + ALLOC2_SIGNAL_IN ( in_GPR_READ_STATUS_DATA_VAL,"data_val",Tcontrol_t,1); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_gpr_read); + } + + // ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("spr_read",IN,NORTH,_("Interface to read generalist register"),_param->_nb_spr_read); + + ALLOC1_VALACK_IN ( in_SPR_READ_VAL ,VAL); + ALLOC1_VALACK_OUT(out_SPR_READ_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_SPR_READ_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t , _param->_size_ooo_engine_id); + ALLOC1_SIGNAL_OUT(out_SPR_READ_DATA ,"data" ,Tspecial_data_t, _param->_size_special_data); + ALLOC1_SIGNAL_OUT(out_SPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t , 1); + + ALLOC1_INTERFACE_END(_param->_nb_spr_read); + } + + { + ALLOC2_INTERFACE_BEGIN("spr_read_registerfile",IN,NORTH,_("Interface to read generalist register - from/to register file"),_param->_nb_ooo_engine,_param->_nb_spr_read); + + ALLOC2_VALACK_OUT(out_SPR_READ_REGISTERFILE_VAL ,VAL); + ALLOC2_VALACK_IN ( in_SPR_READ_REGISTERFILE_ACK ,ACK); + ALLOC2_SIGNAL_IN ( in_SPR_READ_REGISTERFILE_DATA,"data",Tspecial_data_t,_param->_size_special_data); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_spr_read); + } + + { + ALLOC2_INTERFACE_BEGIN("spr_read_status",IN,NORTH,_("Interface to read generalist register - from/to status"),_param->_nb_ooo_engine,_param->_nb_spr_read); + + ALLOC2_VALACK_OUT(out_SPR_READ_STATUS_VAL ,VAL); + ALLOC2_VALACK_IN ( in_SPR_READ_STATUS_ACK ,ACK); + ALLOC2_SIGNAL_IN ( in_SPR_READ_STATUS_DATA_VAL,"data_val",Tcontrol_t,1); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_spr_read); + } + + // ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("gpr_write",IN,NORTH,_("Interface to write generalist register"),_param->_nb_gpr_write); + + ALLOC1_VALACK_IN ( in_GPR_WRITE_VAL ,VAL); + ALLOC1_VALACK_OUT(out_GPR_WRITE_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t, _param->_size_ooo_engine_id); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_write); + } + + { + ALLOC2_INTERFACE_BEGIN("gpr_write_registerfile",IN,NORTH,_("Interface to write generalist register - from/to registerfile"),_param->_nb_ooo_engine,_param->_nb_gpr_write); + + ALLOC2_VALACK_OUT(out_GPR_WRITE_REGISTERFILE_VAL,VAL); + ALLOC2_VALACK_IN ( in_GPR_WRITE_REGISTERFILE_ACK,ACK); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_gpr_write); + } + + { + ALLOC2_INTERFACE_BEGIN("gpr_write_status",IN,NORTH,_("Interface to write generalist register - from/to status"),_param->_nb_ooo_engine,_param->_nb_gpr_write); + + ALLOC2_VALACK_OUT(out_GPR_WRITE_STATUS_VAL,VAL); + ALLOC2_VALACK_IN ( in_GPR_WRITE_STATUS_ACK,ACK); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_gpr_write); + } + + // ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("spr_write",IN,NORTH,_("Interface to write generalist register"),_param->_nb_spr_write); + + ALLOC1_VALACK_IN ( in_SPR_WRITE_VAL ,VAL); + ALLOC1_VALACK_OUT(out_SPR_WRITE_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t, _param->_size_ooo_engine_id); + + ALLOC1_INTERFACE_END(_param->_nb_spr_write); + } + + { + ALLOC2_INTERFACE_BEGIN("spr_write_registerfile",IN,NORTH,_("Interface to write generalist register - from/to registerfile"),_param->_nb_ooo_engine,_param->_nb_spr_write); + + ALLOC2_VALACK_OUT(out_SPR_WRITE_REGISTERFILE_VAL,VAL); + ALLOC2_VALACK_IN ( in_SPR_WRITE_REGISTERFILE_ACK,ACK); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_spr_write); + } + + { + ALLOC2_INTERFACE_BEGIN("spr_write_status",IN,NORTH,_("Interface to write generalist register - from/to status"),_param->_nb_ooo_engine,_param->_nb_spr_write); + + ALLOC2_VALACK_OUT(out_SPR_WRITE_STATUS_VAL,VAL); + ALLOC2_VALACK_IN ( in_SPR_WRITE_STATUS_ACK,ACK); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_spr_write); + } + + // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE_BEGIN("insert_rob",IN,WEST,_("Interface to update status (insert)"),_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + + _ALLOC2_VALACK_IN ( in_INSERT_ROB_VAL ,VAL ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + _ALLOC2_VALACK_OUT(out_INSERT_ROB_ACK ,ACK ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RD_USE,"rd_use",Tcontrol_t, 1,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RE_USE,"re_use",Tcontrol_t, 1,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + } + + { + ALLOC2_INTERFACE_BEGIN("insert_rob_gpr_status",IN,WEST,_("Interface to update status (insert)"),_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + + _ALLOC2_VALACK_OUT(out_INSERT_ROB_GPR_STATUS_VAL,VAL,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + _ALLOC2_VALACK_IN ( in_INSERT_ROB_GPR_STATUS_ACK,ACK,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + } + + { + ALLOC2_INTERFACE_BEGIN("insert_rob_spr_status",IN,WEST,_("Interface to update status (insert)"),_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + + _ALLOC2_VALACK_OUT(out_INSERT_ROB_SPR_STATUS_VAL,VAL,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + _ALLOC2_VALACK_IN ( in_INSERT_ROB_SPR_STATUS_ACK,ACK,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + } // // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/include/Register_unit_Glue.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -26,90 +27,69 @@ { //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) - delete in_CLOCK ; + delete in_CLOCK ; //#endif - delete in_NRESET; + delete in_NRESET; + delete out_CONST_0; + delete out_CONST_1; - // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_GPR_READ_VAL ; - delete [] out_GPR_READ_ACK ; - if (_param->_have_port_ooo_engine_id == true) - delete [] in_GPR_READ_OOO_ENGINE_ID ; - delete [] out_GPR_READ_DATA ; - delete [] out_GPR_READ_DATA_VAL ; + DELETE1_SIGNAL( in_GPR_READ_VAL ,_param->_nb_gpr_read,1 ); + DELETE1_SIGNAL(out_GPR_READ_ACK ,_param->_nb_gpr_read,1 ); + DELETE1_SIGNAL( in_GPR_READ_OOO_ENGINE_ID ,_param->_nb_gpr_read,_param->_size_ooo_engine_id); + DELETE1_SIGNAL(out_GPR_READ_DATA ,_param->_nb_gpr_read,_param->_size_general_data); + DELETE1_SIGNAL(out_GPR_READ_DATA_VAL ,_param->_nb_gpr_read,1); + + DELETE2_SIGNAL(out_GPR_READ_REGISTERFILE_VAL ,_param->_nb_ooo_engine,_param->_nb_gpr_read,1 ); + DELETE2_SIGNAL( in_GPR_READ_REGISTERFILE_ACK ,_param->_nb_ooo_engine,_param->_nb_gpr_read,1 ); + DELETE2_SIGNAL( in_GPR_READ_REGISTERFILE_DATA,_param->_nb_ooo_engine,_param->_nb_gpr_read,_param->_size_general_data); - delete [] out_GPR_READ_REGISTERFILE_VAL ; - delete [] in_GPR_READ_REGISTERFILE_ACK ; - delete [] in_GPR_READ_REGISTERFILE_DATA ; + DELETE2_SIGNAL(out_GPR_READ_STATUS_VAL ,_param->_nb_ooo_engine,_param->_nb_gpr_read,1 ); + DELETE2_SIGNAL( in_GPR_READ_STATUS_ACK ,_param->_nb_ooo_engine,_param->_nb_gpr_read,1 ); + DELETE2_SIGNAL( in_GPR_READ_STATUS_DATA_VAL,_param->_nb_ooo_engine,_param->_nb_gpr_read,1); - delete [] out_GPR_READ_STATUS_VAL ; - delete [] in_GPR_READ_STATUS_ACK ; - delete [] in_GPR_READ_STATUS_DATA_VAL ; + DELETE1_SIGNAL( in_SPR_READ_VAL ,_param->_nb_spr_read,1 ); + DELETE1_SIGNAL(out_SPR_READ_ACK ,_param->_nb_spr_read,1 ); + DELETE1_SIGNAL( in_SPR_READ_OOO_ENGINE_ID ,_param->_nb_spr_read,_param->_size_ooo_engine_id); + DELETE1_SIGNAL(out_SPR_READ_DATA ,_param->_nb_spr_read,_param->_size_special_data); + DELETE1_SIGNAL(out_SPR_READ_DATA_VAL ,_param->_nb_spr_read,1); + + DELETE2_SIGNAL(out_SPR_READ_REGISTERFILE_VAL ,_param->_nb_ooo_engine,_param->_nb_spr_read,1 ); + DELETE2_SIGNAL( in_SPR_READ_REGISTERFILE_ACK ,_param->_nb_ooo_engine,_param->_nb_spr_read,1 ); + DELETE2_SIGNAL( in_SPR_READ_REGISTERFILE_DATA,_param->_nb_ooo_engine,_param->_nb_spr_read,_param->_size_special_data); + + DELETE2_SIGNAL(out_SPR_READ_STATUS_VAL ,_param->_nb_ooo_engine,_param->_nb_spr_read,1 ); + DELETE2_SIGNAL( in_SPR_READ_STATUS_ACK ,_param->_nb_ooo_engine,_param->_nb_spr_read,1 ); + DELETE2_SIGNAL( in_SPR_READ_STATUS_DATA_VAL,_param->_nb_ooo_engine,_param->_nb_spr_read,1); + + DELETE1_SIGNAL( in_GPR_WRITE_VAL ,_param->_nb_gpr_write,1 ); + DELETE1_SIGNAL(out_GPR_WRITE_ACK ,_param->_nb_gpr_write,1 ); + DELETE1_SIGNAL( in_GPR_WRITE_OOO_ENGINE_ID,_param->_nb_gpr_write,_param->_size_ooo_engine_id); + + DELETE2_SIGNAL(out_GPR_WRITE_REGISTERFILE_VAL,_param->_nb_ooo_engine,_param->_nb_gpr_write,1 ); + DELETE2_SIGNAL( in_GPR_WRITE_REGISTERFILE_ACK,_param->_nb_ooo_engine,_param->_nb_gpr_write,1 ); - // ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_SPR_READ_VAL ; - delete [] out_SPR_READ_ACK ; - if (_param->_have_port_ooo_engine_id == true) - delete [] in_SPR_READ_OOO_ENGINE_ID ; - delete [] out_SPR_READ_DATA ; - delete [] out_SPR_READ_DATA_VAL ; + DELETE2_SIGNAL(out_GPR_WRITE_STATUS_VAL,_param->_nb_ooo_engine,_param->_nb_gpr_write,1 ); + DELETE2_SIGNAL( in_GPR_WRITE_STATUS_ACK,_param->_nb_ooo_engine,_param->_nb_gpr_write,1 ); - delete [] out_SPR_READ_REGISTERFILE_VAL ; - delete [] in_SPR_READ_REGISTERFILE_ACK ; - delete [] in_SPR_READ_REGISTERFILE_DATA ; + DELETE1_SIGNAL( in_SPR_WRITE_VAL ,_param->_nb_spr_write,1 ); + DELETE1_SIGNAL(out_SPR_WRITE_ACK ,_param->_nb_spr_write,1 ); + DELETE1_SIGNAL( in_SPR_WRITE_OOO_ENGINE_ID,_param->_nb_spr_write,_param->_size_ooo_engine_id); - delete [] out_SPR_READ_STATUS_VAL ; - delete [] in_SPR_READ_STATUS_ACK ; - delete [] in_SPR_READ_STATUS_DATA_VAL ; + DELETE2_SIGNAL(out_SPR_WRITE_REGISTERFILE_VAL,_param->_nb_ooo_engine,_param->_nb_spr_write,1 ); + DELETE2_SIGNAL( in_SPR_WRITE_REGISTERFILE_ACK,_param->_nb_ooo_engine,_param->_nb_spr_write,1 ); - // ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_GPR_WRITE_VAL ; - delete [] out_GPR_WRITE_ACK ; - if (_param->_have_port_ooo_engine_id == true) - delete [] in_GPR_WRITE_OOO_ENGINE_ID ; + DELETE2_SIGNAL(out_SPR_WRITE_STATUS_VAL,_param->_nb_ooo_engine,_param->_nb_spr_write,1 ); + DELETE2_SIGNAL( in_SPR_WRITE_STATUS_ACK,_param->_nb_ooo_engine,_param->_nb_spr_write,1 ); - delete [] out_GPR_WRITE_REGISTERFILE_VAL ; - delete [] in_GPR_WRITE_REGISTERFILE_ACK ; + DELETE2_SIGNAL( in_INSERT_ROB_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1); + DELETE2_SIGNAL(out_INSERT_ROB_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1); + DELETE2_SIGNAL( in_INSERT_ROB_RD_USE,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1); + DELETE2_SIGNAL( in_INSERT_ROB_RE_USE,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1); - delete [] out_GPR_WRITE_STATUS_VAL ; - delete [] in_GPR_WRITE_STATUS_ACK ; + DELETE2_SIGNAL(out_INSERT_ROB_GPR_STATUS_VAL,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1); + DELETE2_SIGNAL( in_INSERT_ROB_GPR_STATUS_ACK,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1); - // ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_SPR_WRITE_VAL ; - delete [] out_SPR_WRITE_ACK ; - if (_param->_have_port_ooo_engine_id == true) - delete [] in_SPR_WRITE_OOO_ENGINE_ID ; - - delete [] out_SPR_WRITE_REGISTERFILE_VAL ; - delete [] in_SPR_WRITE_REGISTERFILE_ACK ; - - delete [] out_SPR_WRITE_STATUS_VAL ; - delete [] in_SPR_WRITE_STATUS_ACK ; - - // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_INSERT_ROB_VAL ; - delete [] out_INSERT_ROB_ACK ; - delete [] in_INSERT_ROB_RD_USE ; - delete [] in_INSERT_ROB_RE_USE ; - delete [] out_INSERT_ROB_GPR_STATUS_VAL ; - delete [] in_INSERT_ROB_GPR_STATUS_ACK ; - delete [] out_INSERT_ROB_SPR_STATUS_VAL ; - delete [] in_INSERT_ROB_SPR_STATUS_ACK ; - -// // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -// delete [] in_RETIRE_ROB_VAL ; -// delete [] out_RETIRE_ROB_ACK ; -// delete [] in_RETIRE_ROB_RD_OLD_USE ; -// delete [] in_RETIRE_ROB_RD_NEW_USE ; -// delete [] in_RETIRE_ROB_RE_OLD_USE ; -// delete [] in_RETIRE_ROB_RE_NEW_USE ; -// delete [] out_RETIRE_ROB_GPR_STATUS_OLD_VAL ; -// delete [] out_RETIRE_ROB_GPR_STATUS_NEW_VAL ; -// delete [] in_RETIRE_ROB_GPR_STATUS_OLD_ACK ; -// delete [] in_RETIRE_ROB_GPR_STATUS_NEW_ACK ; -// delete [] out_RETIRE_ROB_SPR_STATUS_OLD_VAL ; -// delete [] out_RETIRE_ROB_SPR_STATUS_NEW_VAL ; -// delete [] in_RETIRE_ROB_SPR_STATUS_OLD_ACK ; -// delete [] in_RETIRE_ROB_SPR_STATUS_NEW_ACK ; + DELETE2_SIGNAL(out_INSERT_ROB_SPR_STATUS_VAL,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1); + DELETE2_SIGNAL( in_INSERT_ROB_SPR_STATUS_ACK,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_allocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/include/Register_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -52,150 +53,70 @@ // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_GPR_READ_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_read]; - out_GPR_READ_ACK = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_read]; - if (_param->_have_port_ooo_engine_id == true) - in_GPR_READ_OOO_ENGINE_ID = new SC_IN (Tcontext_t ) * [_param->_nb_gpr_read]; - in_GPR_READ_NUM_REG = new SC_IN (Tgeneral_address_t) * [_param->_nb_gpr_read]; - out_GPR_READ_DATA = new SC_OUT(Tgeneral_data_t ) * [_param->_nb_gpr_read]; - out_GPR_READ_DATA_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_read]; - - for (uint32_t i=0; i<_param->_nb_gpr_read; i++) - { - Interface_fifo * interface = _interfaces->set_interface("gpr_read_"+toString(i) -#ifdef POSITION - ,IN - ,NORTH - ,"Interface to read the register file" -#endif - ); - - in_GPR_READ_VAL [i]= interface->set_signal_valack_in (VAL); - out_GPR_READ_ACK [i]= interface->set_signal_valack_out (ACK); - if (_param->_have_port_ooo_engine_id == true) - in_GPR_READ_OOO_ENGINE_ID [i]= interface->set_signal_in ("ooo_engine_id" , _param->_size_ooo_engine_id); - in_GPR_READ_NUM_REG [i]= interface->set_signal_in ("num_reg" , _param->_size_gpr_address); - out_GPR_READ_DATA [i]= interface->set_signal_out ("data" , _param->_size_general_data); - out_GPR_READ_DATA_VAL [i]= interface->set_signal_out ("data_val" , 1); - } + { + ALLOC1_INTERFACE_BEGIN("gpr_read",IN,NORTH,_("Interface to read the register file"),_param->_nb_gpr_read); + + ALLOC1_VALACK_IN ( in_GPR_READ_VAL ,VAL); + ALLOC1_VALACK_OUT(out_GPR_READ_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_GPR_READ_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_IN ( in_GPR_READ_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_gpr_address); + ALLOC1_SIGNAL_OUT(out_GPR_READ_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + ALLOC1_SIGNAL_OUT(out_GPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_read); + } // ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_GPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_write]; - out_GPR_WRITE_ACK = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_write]; - if (_param->_have_port_ooo_engine_id == true) - in_GPR_WRITE_OOO_ENGINE_ID = new SC_IN (Tcontext_t ) * [_param->_nb_gpr_write]; - in_GPR_WRITE_NUM_REG = new SC_IN (Tgeneral_address_t) * [_param->_nb_gpr_write]; - in_GPR_WRITE_DATA = new SC_IN (Tgeneral_data_t ) * [_param->_nb_gpr_write]; - - for (uint32_t i=0; i<_param->_nb_gpr_write; i++) - { - Interface_fifo * interface = _interfaces->set_interface("gpr_write_"+toString(i) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to write the register file" -#endif - ); - - in_GPR_WRITE_VAL [i]= interface->set_signal_valack_in (VAL); - out_GPR_WRITE_ACK [i]= interface->set_signal_valack_out (ACK); - if (_param->_have_port_ooo_engine_id == true) - in_GPR_WRITE_OOO_ENGINE_ID [i]= interface->set_signal_in ("ooo_engine_id" , _param->_size_ooo_engine_id); - in_GPR_WRITE_NUM_REG [i]= interface->set_signal_in ("num_reg" , _param->_size_gpr_address); - in_GPR_WRITE_DATA [i]= interface->set_signal_in ("data" , _param->_size_general_data); - } + { + ALLOC1_INTERFACE_BEGIN("gpr_write",IN,NORTH,_("Interface to write the register file"),_param->_nb_gpr_write); + + ALLOC1_VALACK_IN ( in_GPR_WRITE_VAL ,VAL); + ALLOC1_VALACK_OUT(out_GPR_WRITE_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_IN ( in_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_gpr_address); + ALLOC1_SIGNAL_IN ( in_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + + ALLOC1_INTERFACE_END(_param->_nb_gpr_write); + } // ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_SPR_READ_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_read]; - out_SPR_READ_ACK = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_read]; - if (_param->_have_port_ooo_engine_id == true) - in_SPR_READ_OOO_ENGINE_ID = new SC_IN (Tcontext_t ) * [_param->_nb_spr_read]; - in_SPR_READ_NUM_REG = new SC_IN (Tspecial_address_t) * [_param->_nb_spr_read]; - out_SPR_READ_DATA = new SC_OUT(Tspecial_data_t ) * [_param->_nb_spr_read]; - out_SPR_READ_DATA_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_read]; - - for (uint32_t i=0; i<_param->_nb_spr_read; i++) - { - Interface_fifo * interface = _interfaces->set_interface("spr_read_"+toString(i) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to read the register file" -#endif - ); - - in_SPR_READ_VAL [i]= interface->set_signal_valack_in (VAL); - out_SPR_READ_ACK [i]= interface->set_signal_valack_out (ACK); - if (_param->_have_port_ooo_engine_id == true) - in_SPR_READ_OOO_ENGINE_ID [i]= interface->set_signal_in ("ooo_engine_id" , _param->_size_ooo_engine_id); - in_SPR_READ_NUM_REG [i]= interface->set_signal_in ("num_reg" , _param->_size_spr_address); - out_SPR_READ_DATA [i]= interface->set_signal_out ("data" , _param->_size_special_data); - out_SPR_READ_DATA_VAL [i]= interface->set_signal_out ("data_val" , 1); - } + { + ALLOC1_INTERFACE_BEGIN("spr_read",IN,NORTH,_("Interface to read the register file"),_param->_nb_spr_read); + + ALLOC1_VALACK_IN ( in_SPR_READ_VAL ,VAL); + ALLOC1_VALACK_OUT(out_SPR_READ_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_SPR_READ_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_IN ( in_SPR_READ_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_spr_address); + ALLOC1_SIGNAL_OUT(out_SPR_READ_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data); + ALLOC1_SIGNAL_OUT(out_SPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_spr_read); + } // ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_SPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_write]; - out_SPR_WRITE_ACK = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_write]; - if (_param->_have_port_ooo_engine_id == true) - in_SPR_WRITE_OOO_ENGINE_ID = new SC_IN (Tcontext_t ) * [_param->_nb_spr_write]; - in_SPR_WRITE_NUM_REG = new SC_IN (Tspecial_address_t) * [_param->_nb_spr_write]; - in_SPR_WRITE_DATA = new SC_IN (Tspecial_data_t ) * [_param->_nb_spr_write]; - - for (uint32_t i=0; i<_param->_nb_spr_write; i++) - { - Interface_fifo * interface = _interfaces->set_interface("spr_write_"+toString(i) -#ifdef POSITION - ,IN - ,NORTH, - "Interface to write the register file" -#endif - ); - - in_SPR_WRITE_VAL [i]= interface->set_signal_valack_in (VAL); - out_SPR_WRITE_ACK [i]= interface->set_signal_valack_out (ACK); - if (_param->_have_port_ooo_engine_id == true) - in_SPR_WRITE_OOO_ENGINE_ID [i]= interface->set_signal_in ("ooo_engine_id" , _param->_size_ooo_engine_id); - in_SPR_WRITE_NUM_REG [i]= interface->set_signal_in ("num_reg" , _param->_size_spr_address); - in_SPR_WRITE_DATA [i]= interface->set_signal_in ("data" , _param->_size_special_data); - } - - // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_INSERT_ROB_VAL = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - out_INSERT_ROB_ACK = new SC_OUT(Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_INSERT_ROB_RD_USE = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_INSERT_ROB_RD_NUM_REG = new SC_IN (Tgeneral_address_t) ** [_param->_nb_ooo_engine]; - in_INSERT_ROB_RE_USE = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_INSERT_ROB_RE_NUM_REG = new SC_IN (Tspecial_address_t) ** [_param->_nb_ooo_engine]; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x=_param->_nb_inst_insert_rob [i]; - - in_INSERT_ROB_VAL [i] = new SC_IN (Tcontrol_t ) * [x]; - out_INSERT_ROB_ACK [i] = new SC_OUT(Tcontrol_t ) * [x]; - in_INSERT_ROB_RD_USE [i] = new SC_IN (Tcontrol_t ) * [x]; - in_INSERT_ROB_RD_NUM_REG [i] = new SC_IN (Tgeneral_address_t) * [x]; - in_INSERT_ROB_RE_USE [i] = new SC_IN (Tcontrol_t ) * [x]; - in_INSERT_ROB_RE_NUM_REG [i] = new SC_IN (Tspecial_address_t) * [x]; - - for (uint32_t j=0; jset_interface("insert_rob_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,WEST - ,"Interface to update status (insert)" -#endif - ); - - - in_INSERT_ROB_VAL [i][j] = interface->set_signal_valack_in (VAL); - out_INSERT_ROB_ACK [i][j] = interface->set_signal_valack_out (ACK); - in_INSERT_ROB_RD_USE [i][j] = interface->set_signal_in ("rd_use" , 1); - in_INSERT_ROB_RD_NUM_REG [i][j] = interface->set_signal_in ("rd_num_reg", _param->_size_gpr_address); - in_INSERT_ROB_RE_USE [i][j] = interface->set_signal_in ("re_use" , 1); - in_INSERT_ROB_RE_NUM_REG [i][j] = interface->set_signal_in ("re_num_reg", _param->_size_spr_address); - - } - } + { + ALLOC1_INTERFACE_BEGIN("spr_write",IN,NORTH,_("Interface to write the register file"),_param->_nb_spr_write); + + ALLOC1_VALACK_IN ( in_SPR_WRITE_VAL ,VAL); + ALLOC1_VALACK_OUT(out_SPR_WRITE_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_IN ( in_SPR_WRITE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_spr_address); + ALLOC1_SIGNAL_IN ( in_SPR_WRITE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data); + + ALLOC1_INTERFACE_END(_param->_nb_spr_write); + } + + // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE_BEGIN("insert_rob",IN,WEST,_("Interface to update status (insert)"),_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + + _ALLOC2_VALACK_IN ( in_INSERT_ROB_VAL ,VAL ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + _ALLOC2_VALACK_OUT(out_INSERT_ROB_ACK ,ACK ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RD_USE ,"rd_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RD_NUM_REG,"rd_num_reg",Tgeneral_address_t,_param->_size_gpr_address,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RE_USE ,"re_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RE_NUM_REG,"re_num_reg",Tspecial_address_t,_param->_size_spr_address,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]); + } // // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/include/Register_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -24,41 +25,40 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { -//#if defined(STATISTICS) or defined(VHDL_TESTBENCH) - delete in_CLOCK ; -//#endif - delete in_NRESET; + delete in_CLOCK ; + delete in_NRESET; - delete [] in_GPR_READ_VAL ; - delete [] out_GPR_READ_ACK ; - if (_param->_have_port_ooo_engine_id == true) - delete [] in_GPR_READ_OOO_ENGINE_ID ; - delete [] in_GPR_READ_NUM_REG ; - delete [] out_GPR_READ_DATA ; - delete [] out_GPR_READ_DATA_VAL ; - delete [] in_GPR_WRITE_VAL ; - delete [] out_GPR_WRITE_ACK ; - if (_param->_have_port_ooo_engine_id == true) - delete [] in_GPR_WRITE_OOO_ENGINE_ID ; - delete [] in_GPR_WRITE_NUM_REG ; - delete [] in_GPR_WRITE_DATA ; - delete [] in_SPR_READ_VAL ; - delete [] out_SPR_READ_ACK ; - if (_param->_have_port_ooo_engine_id == true) - delete [] in_SPR_READ_OOO_ENGINE_ID ; - delete [] in_SPR_READ_NUM_REG ; - delete [] out_SPR_READ_DATA ; - delete [] out_SPR_READ_DATA_VAL ; - delete [] in_SPR_WRITE_VAL ; - delete [] out_SPR_WRITE_ACK ; - if (_param->_have_port_ooo_engine_id == true) - delete [] in_SPR_WRITE_OOO_ENGINE_ID ; - delete [] in_SPR_WRITE_NUM_REG ; - delete [] in_SPR_WRITE_DATA ; - delete [] in_INSERT_ROB_VAL ; - delete [] out_INSERT_ROB_ACK ; - delete [] in_INSERT_ROB_RD_USE ; - delete [] in_INSERT_ROB_RD_NUM_REG ; - delete [] in_INSERT_ROB_RE_USE ; - delete [] in_INSERT_ROB_RE_NUM_REG ; + DELETE1_SIGNAL( in_GPR_READ_VAL ,_param->_nb_gpr_read,1); + DELETE1_SIGNAL(out_GPR_READ_ACK ,_param->_nb_gpr_read,1); + DELETE1_SIGNAL( in_GPR_READ_OOO_ENGINE_ID ,_param->_nb_gpr_read,_param->_size_ooo_engine_id); + DELETE1_SIGNAL( in_GPR_READ_NUM_REG ,_param->_nb_gpr_read,_param->_size_gpr_address); + DELETE1_SIGNAL(out_GPR_READ_DATA ,_param->_nb_gpr_read,_param->_size_general_data); + DELETE1_SIGNAL(out_GPR_READ_DATA_VAL ,_param->_nb_gpr_read,1); + + DELETE1_SIGNAL( in_GPR_WRITE_VAL ,_param->_nb_gpr_write,1); + DELETE1_SIGNAL(out_GPR_WRITE_ACK ,_param->_nb_gpr_write,1); + DELETE1_SIGNAL( in_GPR_WRITE_OOO_ENGINE_ID,_param->_nb_gpr_write,_param->_size_ooo_engine_id); + DELETE1_SIGNAL( in_GPR_WRITE_NUM_REG ,_param->_nb_gpr_write,_param->_size_gpr_address); + DELETE1_SIGNAL( in_GPR_WRITE_DATA ,_param->_nb_gpr_write,_param->_size_general_data); + + DELETE1_SIGNAL( in_SPR_READ_VAL ,_param->_nb_spr_read,1); + DELETE1_SIGNAL(out_SPR_READ_ACK ,_param->_nb_spr_read,1); + DELETE1_SIGNAL( in_SPR_READ_OOO_ENGINE_ID ,_param->_nb_spr_read,_param->_size_ooo_engine_id); + DELETE1_SIGNAL( in_SPR_READ_NUM_REG ,_param->_nb_spr_read,_param->_size_spr_address); + DELETE1_SIGNAL(out_SPR_READ_DATA ,_param->_nb_spr_read,_param->_size_special_data); + DELETE1_SIGNAL(out_SPR_READ_DATA_VAL ,_param->_nb_spr_read,1); + + DELETE1_SIGNAL( in_SPR_WRITE_VAL ,_param->_nb_spr_write,1); + DELETE1_SIGNAL(out_SPR_WRITE_ACK ,_param->_nb_spr_write,1); + DELETE1_SIGNAL( in_SPR_WRITE_OOO_ENGINE_ID,_param->_nb_spr_write,_param->_size_ooo_engine_id); + DELETE1_SIGNAL( in_SPR_WRITE_NUM_REG ,_param->_nb_spr_write,_param->_size_spr_address); + DELETE1_SIGNAL( in_SPR_WRITE_DATA ,_param->_nb_spr_write,_param->_size_special_data); + + DELETE2_SIGNAL( in_INSERT_ROB_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1); + DELETE2_SIGNAL(out_INSERT_ROB_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1); + DELETE2_SIGNAL( in_INSERT_ROB_RD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1); + DELETE2_SIGNAL( in_INSERT_ROB_RD_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],_param->_size_gpr_address); + DELETE2_SIGNAL( in_INSERT_ROB_RE_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1); + DELETE2_SIGNAL( in_INSERT_ROB_RE_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],_param->_size_spr_address); + // delete [] in_RETIRE_ROB_VAL ; // delete [] out_RETIRE_ROB_ACK ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp (revision 112) @@ -55,5 +55,5 @@ // ~~~~~[ Interface "execute_loop_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("execute_loop_in", IN, EAST, "Operation's Input", _param->_nb_read_unit); + ALLOC1_INTERFACE_BEGIN("execute_loop_in", IN, EAST, "Operation's Input", _param->_nb_read_unit); ALLOC1_VALACK_IN ( in_EXECUTE_LOOP_IN_VAL,VAL); @@ -66,5 +66,4 @@ ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type); ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); - if (_param->_have_port_load_queue_ptr) ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr); ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1); @@ -80,8 +79,10 @@ ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); + + ALLOC1_INTERFACE_END(param->_nb_read_unit); } // ~~~~~[ Interface "execute_loop_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("execute_loop_out",OUT, EAST, "Operation's Output", _param->_nb_write_unit); + ALLOC1_INTERFACE_BEGIN("execute_loop_out",OUT, EAST, "Operation's Output", _param->_nb_write_unit); ALLOC1_VALACK_OUT(out_EXECUTE_LOOP_OUT_VAL,VAL); @@ -98,8 +99,10 @@ ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data); + + ALLOC1_INTERFACE_END(_param->_nb_write_unit); } // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("dcache_req",OUT, NORTH, "Data cache port : request", _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + ALLOC2_INTERFACE_BEGIN("dcache_req",OUT, NORTH, "Data cache port : request", _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); _ALLOC2_VALACK_OUT(out_DCACHE_REQ_VAL,VAL, _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); @@ -110,8 +113,11 @@ _ALLOC2_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); _ALLOC2_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_general_data , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_load_store_unit, _param->_nb_cache_port[it1]); } + // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("dcache_rsp",IN, NORTH, "Data cache port : respons", _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + ALLOC2_INTERFACE_BEGIN("dcache_rsp",IN, NORTH, "Data cache port : respons", _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); _ALLOC2_VALACK_IN ( in_DCACHE_RSP_VAL,VAL, _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); @@ -121,8 +127,11 @@ _ALLOC2_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_general_data , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); _ALLOC2_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t,_param->_size_dcache_error , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_load_store_unit, _param->_nb_cache_port[it1]); } + // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("insert_rob",IN, EAST, "Rename's stage : insert a new instruction in the Re Order Buffer",_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + ALLOC2_INTERFACE_BEGIN("insert_rob",IN, EAST, "Rename's stage : insert a new instruction in the Re Order Buffer",_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); _ALLOC2_VALACK_IN ( in_INSERT_ROB_VAL,VAL,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); @@ -133,5 +142,8 @@ _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RE_USE ,"re_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RE_NUM_REG,"re_num_reg",Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); } + // // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // { Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 112) @@ -66,15 +66,15 @@ ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ," in_DECOD_EVENT_ADDRESS_EPCR ",Taddress_t ,_param->_nb_decod_unit); - ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t ); - ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t ); - ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t); - ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t ); - ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ," in_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); - ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ," in_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t); ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); @@ -147,17 +147,17 @@ INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit); - INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_VAL ); - INSTANCE_SC_SIGNAL (_Context_State,out_COMMIT_EVENT_ACK ); + INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_VAL ); + INSTANCE0_SC_SIGNAL(_Context_State,out_COMMIT_EVENT_ACK ); if (_param->_have_port_context_id) - INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_CONTEXT_ID ); + INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_CONTEXT_ID ); if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_DEPTH ); - INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_TYPE ); - INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT ); - INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS ); - INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); - INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR ); - INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); - INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR ); + INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_DEPTH ); + INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_TYPE ); + INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT ); + INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); + INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR ); + INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); + INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR ); INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); @@ -196,7 +196,6 @@ INSTANCE1_SC_SIGNAL(_Context_State,out_CONTEXT_DECOD_ENABLE ,_param->_nb_context ); - for (uint32_t i=0; i<_param->_nb_context; i++) - if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL(_Context_State, in_DEPTH_MIN [i]); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Context_State, in_DEPTH_MIN ,_param->_nb_context ); INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_IEE ,_param->_nb_context ); @@ -1324,15 +1323,15 @@ DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit); DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit); - DELETE_SC_SIGNAL ( in_COMMIT_EVENT_VAL ); - DELETE_SC_SIGNAL (out_COMMIT_EVENT_ACK ); - DELETE_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ); - DELETE_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH ); - DELETE_SC_SIGNAL ( in_COMMIT_EVENT_TYPE ); - DELETE_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ); - DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ); - DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); - DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ); - DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); - DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_VAL ); + DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ACK ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_TYPE ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ); DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp (revision 112) @@ -58,5 +58,5 @@ // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("branch_event", IN,SOUTH, "branch_event", _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("branch_event", IN,SOUTH, _("branch_event"), _param->_nb_context); ALLOC1_VALACK_IN ( in_BRANCH_EVENT_VAL ,VAL); @@ -68,9 +68,11 @@ ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_ADDRESS_DEST_VAL ,"address_dest_val" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_instruction_address); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "decod_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("decod_event",IN ,SOUTH, _("Decod Interface"), _param->_nb_decod_unit); + ALLOC1_INTERFACE_BEGIN("decod_event",IN ,SOUTH, _("Decod Interface"), _param->_nb_decod_unit); ALLOC1_VALACK_IN ( in_DECOD_EVENT_VAL ,VAL); @@ -82,26 +84,30 @@ ALLOC1_SIGNAL_IN ( in_DECOD_EVENT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_DECOD_EVENT_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); + + ALLOC1_INTERFACE_END(_param->_nb_decod_unit); } // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("commit_event",IN ,EAST, _("Interface with the Re Order Buffer")); - - ALLOC_VALACK_IN ( in_COMMIT_EVENT_VAL ,VAL); - ALLOC_VALACK_OUT (out_COMMIT_EVENT_ACK ,ACK); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"address_epcr_val",Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"address_eear" ,Tgeneral_data_t ,_param->_size_general_data); + ALLOC0_INTERFACE_BEGIN("commit_event",IN ,EAST, _("Interface with the Re Order Buffer")); + + ALLOC0_VALACK_IN ( in_COMMIT_EVENT_VAL ,VAL); + ALLOC0_VALACK_OUT(out_COMMIT_EVENT_ACK ,ACK); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"address_epcr_val",Tcontrol_t ,1); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"address_eear" ,Tgeneral_data_t ,_param->_size_general_data); + + ALLOC0_INTERFACE_END(); } // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("branch_complete",IN ,NORTH, _("Interface with the prediction_unit."), _param->_nb_inst_branch_complete); + ALLOC1_INTERFACE_BEGIN("branch_complete",IN ,NORTH, _("Interface with the prediction_unit."), _param->_nb_inst_branch_complete); ALLOC1_VALACK_IN ( in_BRANCH_COMPLETE_VAL ,VAL); @@ -113,18 +119,22 @@ // ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address); // ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_instruction_address); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_complete); } // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("nb_inst",IN ,EAST, _("Interface to count in fligt present instruction."),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("nb_inst",IN ,EAST, _("Interface to count in fligt present instruction."),_param->_nb_context); ALLOC1_SIGNAL_IN ( in_NB_INST_DECOD_ALL ,"decod_all" ,Tcounter_t ,_param->_size_nb_inst_decod); ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_ALL ,"commit_all",Tcounter_t ,_param->_size_nb_inst_commit); ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_MEM ,"commit_mem",Tcounter_t ,_param->_size_nb_inst_commit); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("event",OUT,WEST, _("An event occure : change PC address."), _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("event",OUT,WEST, _("An event occure : change PC address."), _param->_nb_context); ALLOC1_VALACK_OUT(out_EVENT_VAL ,VAL); @@ -137,9 +147,10 @@ ALLOC1_SIGNAL_OUT(out_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("spr_event",OUT,WEST, _("An exception occure : write \"exception PC\"."), _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("spr_event",OUT,WEST, _("An exception occure : write \"exception PC\"."), _param->_nb_context); ALLOC1_VALACK_OUT(out_SPR_EVENT_VAL ,VAL); @@ -150,18 +161,24 @@ ALLOC1_SIGNAL_OUT(out_SPR_EVENT_SR_DSX ,"sr_dsx" ,Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_SPR_EVENT_SR_TO_ESR ,"sr_to_esr",Tcontrol_t,1); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("context",OUT,SOUTH, _("To decod."), _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("context",OUT,SOUTH, _("To decod."), _param->_nb_context); ALLOC1_SIGNAL_OUT(out_CONTEXT_DECOD_ENABLE ,"decod_enable",Tcontrol_t,1); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("depth",IN ,NORTH, _("From prediction_unit."), _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("depth",IN ,NORTH, _("From prediction_unit."), _param->_nb_context); ALLOC1_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t,_param->_size_depth); + + ALLOC1_INTERFACE_END(_param->_nb_context); } @@ -169,15 +186,19 @@ // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("spr",IN,EAST,_("Interface with the special registerFile"),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("spr",IN,EAST,_("Interface with the special registerFile"),_param->_nb_context); ALLOC1_SIGNAL_IN ( in_SPR_SR_IEE ,"SR_IEE",Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_SPR_SR_EPH ,"SR_EPH",Tcontrol_t,1); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("interrupt",IN,NORTH,_("Interrupt Exception"),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("interrupt",IN,NORTH,_("Interrupt Exception"),_param->_nb_context); ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE ,"ENABLE",Tcontrol_t,1); + + ALLOC1_INTERFACE_END(_param->_nb_context); } @@ -186,21 +207,22 @@ // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - reg_STATE = new context_state_t [_param->_nb_context]; - reg_EVENT_ADDRESS = new Taddress_t [_param->_nb_context]; - reg_EVENT_ADDRESS_EPCR = new Taddress_t [_param->_nb_context]; - reg_EVENT_ADDRESS_EPCR_VAL = new Tcontrol_t [_param->_nb_context]; - reg_EVENT_ADDRESS_EEAR = new Taddress_t [_param->_nb_context]; - reg_EVENT_ADDRESS_EEAR_VAL = new Tcontrol_t [_param->_nb_context]; - reg_EVENT_IS_DELAY_SLOT = new Tcontrol_t [_param->_nb_context]; - reg_EVENT_IS_DS_TAKE = new Tcontrol_t [_param->_nb_context]; - reg_EVENT_DEPTH = new Tdepth_t [_param->_nb_context]; - reg_INTERRUPT_ENABLE = new Tcontrol_t [_param->_nb_context]; + ALLOC1(reg_STATE ,context_state_t,_param->_nb_context); + ALLOC1(reg_EVENT_ADDRESS ,Taddress_t ,_param->_nb_context); + ALLOC1(reg_EVENT_ADDRESS_EPCR ,Taddress_t ,_param->_nb_context); + ALLOC1(reg_EVENT_ADDRESS_EPCR_VAL,Tcontrol_t ,_param->_nb_context); + ALLOC1(reg_EVENT_ADDRESS_EEAR ,Taddress_t ,_param->_nb_context); + ALLOC1(reg_EVENT_ADDRESS_EEAR_VAL,Tcontrol_t ,_param->_nb_context); + ALLOC1(reg_EVENT_IS_DELAY_SLOT ,Tcontrol_t ,_param->_nb_context); + ALLOC1(reg_EVENT_IS_DS_TAKE ,Tcontrol_t ,_param->_nb_context); + ALLOC1(reg_EVENT_DEPTH ,Tdepth_t ,_param->_nb_context); + ALLOC1(reg_INTERRUPT_ENABLE ,Tcontrol_t ,_param->_nb_context); // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - internal_BRANCH_EVENT_ACK = new Tcontrol_t [_param->_nb_context]; - internal_DECOD_EVENT_ACK = new Tcontrol_t [_param->_nb_decod_unit]; - internal_BRANCH_COMPLETE_ACK = new Tcontrol_t [_param->_nb_inst_branch_complete]; - internal_EVENT_VAL = new Tcontrol_t [_param->_nb_context]; - internal_SPR_EVENT_VAL = new Tcontrol_t [_param->_nb_context]; + + ALLOC1(internal_BRANCH_EVENT_ACK ,Tcontrol_t,_param->_nb_context); + ALLOC1(internal_DECOD_EVENT_ACK ,Tcontrol_t,_param->_nb_decod_unit); + ALLOC1(internal_BRANCH_COMPLETE_ACK,Tcontrol_t,_param->_nb_inst_branch_complete); + ALLOC1(internal_EVENT_VAL ,Tcontrol_t,_param->_nb_context); + ALLOC1(internal_SPR_EVENT_VAL ,Tcontrol_t,_param->_nb_context); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp (revision 112) @@ -46,15 +46,15 @@ DELETE1_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit,_param->_size_instruction_address); - DELETE_SIGNAL ( in_COMMIT_EVENT_VAL ,1); - DELETE_SIGNAL (out_COMMIT_EVENT_ACK ,1); - DELETE_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ,_param->_size_context_id); - DELETE_SIGNAL ( in_COMMIT_EVENT_DEPTH ,_param->_size_depth); - DELETE_SIGNAL ( in_COMMIT_EVENT_TYPE ,_param->_size_event_type); - DELETE_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ,1); - DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS ,_param->_size_instruction_address); - DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,_param->_size_instruction_address); - DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address); - DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,_param->_size_instruction_address); - DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ,1); + DELETE0_SIGNAL( in_COMMIT_EVENT_VAL ,1); + DELETE0_SIGNAL(out_COMMIT_EVENT_ACK ,1); + DELETE0_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ,_param->_size_context_id); + DELETE0_SIGNAL( in_COMMIT_EVENT_DEPTH ,_param->_size_depth); + DELETE0_SIGNAL( in_COMMIT_EVENT_TYPE ,_param->_size_event_type); + DELETE0_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ,1); + DELETE0_SIGNAL( in_COMMIT_EVENT_ADDRESS ,_param->_size_instruction_address); + DELETE0_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,_param->_size_instruction_address); + DELETE0_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address); + DELETE0_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,_param->_size_instruction_address); + DELETE0_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ,1); DELETE1_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1); @@ -98,20 +98,21 @@ // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] reg_STATE ; - delete [] reg_EVENT_ADDRESS ; - delete [] reg_EVENT_ADDRESS_EPCR ; - delete [] reg_EVENT_ADDRESS_EPCR_VAL; - delete [] reg_EVENT_ADDRESS_EEAR ; - delete [] reg_EVENT_ADDRESS_EEAR_VAL; - delete [] reg_EVENT_IS_DELAY_SLOT ; - delete [] reg_EVENT_IS_DS_TAKE ; - delete [] reg_EVENT_DEPTH ; - delete [] reg_INTERRUPT_ENABLE ; + DELETE1(reg_STATE ,_param->_nb_context); + DELETE1(reg_EVENT_ADDRESS ,_param->_nb_context); + DELETE1(reg_EVENT_ADDRESS_EPCR ,_param->_nb_context); + DELETE1(reg_EVENT_ADDRESS_EPCR_VAL,_param->_nb_context); + DELETE1(reg_EVENT_ADDRESS_EEAR ,_param->_nb_context); + DELETE1(reg_EVENT_ADDRESS_EEAR_VAL,_param->_nb_context); + DELETE1(reg_EVENT_IS_DELAY_SLOT ,_param->_nb_context); + DELETE1(reg_EVENT_IS_DS_TAKE ,_param->_nb_context); + DELETE1(reg_EVENT_DEPTH ,_param->_nb_context); + DELETE1(reg_INTERRUPT_ENABLE ,_param->_nb_context); // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] internal_BRANCH_EVENT_ACK ; - delete [] internal_DECOD_EVENT_ACK ; - delete [] internal_EVENT_VAL ; - delete [] internal_SPR_EVENT_VAL ; + DELETE1(internal_BRANCH_EVENT_ACK ,_param->_nb_context); + DELETE1(internal_DECOD_EVENT_ACK ,_param->_nb_decod_unit); + DELETE1(internal_BRANCH_COMPLETE_ACK,_param->_nb_inst_branch_complete); + DELETE1(internal_EVENT_VAL ,_param->_nb_context); + DELETE1(internal_SPR_EVENT_VAL ,_param->_nb_context); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp (revision 112) @@ -104,12 +104,12 @@ ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH_VAL ," in_CONTEXT_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context); - ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t ); - ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t ); - ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t ); - ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t ); - ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t ); + ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t ); + ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t ); + ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t ); + ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t ); /******************************************************** @@ -135,8 +135,8 @@ { if (_param->_have_port_inst_ifetch_ptr) - INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR [i]); + INSTANCE0_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR [i]); // if (_param->_have_port_branch_update_prediction_id) if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]); + INSTANCE0_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]); } @@ -188,15 +188,15 @@ for (uint32_t i=0; i<_param->_nb_context; i++) if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH [i]); - INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_VAL ); - INSTANCE_SC_SIGNAL (_Decod, in_CONTEXT_EVENT_ACK ); + INSTANCE0_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH [i]); + INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_VAL ); + INSTANCE0_SC_SIGNAL(_Decod, in_CONTEXT_EVENT_ACK ); if (_param->_have_port_context_id) - INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_CONTEXT_ID ); + INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_CONTEXT_ID ); if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_DEPTH ); - INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_TYPE ); - INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_IS_DELAY_SLOT ); - INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS ); - INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS_EPCR ); + INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_DEPTH ); + INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_TYPE ); + INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_IS_DELAY_SLOT ); + INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_ADDRESS_EPCR ); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Parameters.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Parameters.h (revision 112) @@ -23,4 +23,20 @@ namespace decod { + const uint32_t nb_opcod_type = 14; + const uint32_t tab_opcod_type [] = {MAX_OPCOD_0, + MAX_OPCOD_1 , + MAX_OPCOD_2 , + MAX_OPCOD_3 , + MAX_OPCOD_4 , + MAX_OPCOD_5 , + MAX_OPCOD_6 , + MAX_OPCOD_7 , + MAX_OPCOD_8 , + MAX_OPCOD_9 , + MAX_OPCOD_10, + MAX_OPCOD_11, + MAX_OPCOD_12, + MAX_OPCOD_13}; + class Parameters : public morpheo::behavioural::Parameters { @@ -37,5 +53,5 @@ public : bool ** _instruction_implemeted ; //[nb_context][nb_instruction] public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void); - + public : uint32_t _max_nb_inst_fetch; //public : uint32_t _size_address_inst; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp (revision 112) @@ -58,5 +58,5 @@ // ~~~~~[ Interface : "ifetch" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("ifetch", IN, WEST, "Instruction's bundle", _param->_nb_context, _param->_nb_inst_fetch[it1]); + ALLOC2_INTERFACE_BEGIN("ifetch", IN, WEST, _("Instruction's bundle"), _param->_nb_context, _param->_nb_inst_fetch[it1]); @@ -64,8 +64,11 @@ _ALLOC2_VALACK_OUT(out_IFETCH_ACK ,ACK, _param->_nb_context, _param->_nb_inst_fetch[it1]); _ALLOC2_SIGNAL_IN ( in_IFETCH_INSTRUCTION,"instruction", Tinstruction_t, _param->_size_instruction,_param->_nb_context, _param->_nb_inst_fetch[it1]); - } - { - ALLOC1_INTERFACE("ifetch", IN, WEST, "Instruction's bundle", _param->_nb_context); + + ALLOC2_INTERFACE_END(_param->_nb_context, _param->_nb_inst_fetch[it1]); + } + { + ALLOC1_INTERFACE_BEGIN("ifetch", IN, WEST, _("Instruction's bundle"), _param->_nb_context); + ALLOC1_SIGNAL_IN (in_IFETCH_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS ,"address" ,Tgeneral_address_t ,_param->_size_instruction_address ); @@ -75,9 +78,11 @@ ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); ALLOC1_SIGNAL_IN (in_IFETCH_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("decod", OUT, EAST, "Instructiont decoded", _param->_nb_inst_decod); + ALLOC1_INTERFACE_BEGIN("decod", OUT, EAST, _("Instructiont decoded"), _param->_nb_inst_decod); ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL); @@ -107,9 +112,11 @@ ALLOC1_SIGNAL_OUT(out_DECOD_EXCEPTION_USE,"exception_use",Texception_t ,_param->_size_exception_use ); ALLOC1_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_decod ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_decod); } // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("predict",OUT,NORTH,"Decod a branch -> inform the branch predictor.",_param->_nb_inst_decod); + ALLOC1_INTERFACE_BEGIN("predict",OUT,NORTH,_("Decod a branch -> inform the branch predictor."),_param->_nb_inst_decod); ALLOC1_VALACK_OUT(out_PREDICT_VAL ,VAL); @@ -125,27 +132,33 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_IN ( in_PREDICT_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_decod); } // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("context", IN, NORTH, "context's information", _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("context", IN, NORTH, _("context's information"), _param->_nb_context); ALLOC1_SIGNAL_IN (in_CONTEXT_DECOD_ENABLE,"decod_enable",Tcontrol_t,1); ALLOC1_SIGNAL_IN (in_CONTEXT_DEPTH_VAL ,"depth_val" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN (in_CONTEXT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "context_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("context_event", OUT, NORTH, "context's evenement"); - - ALLOC_VALACK_OUT(out_CONTEXT_EVENT_VAL ,VAL); - ALLOC_VALACK_IN ( in_CONTEXT_EVENT_ACK ,ACK); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_instruction_address); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Tgeneral_data_t,_param->_size_instruction_address); + ALLOC0_INTERFACE_BEGIN("context_event", OUT, NORTH, _("context's evenement")); + + ALLOC0_VALACK_OUT(out_CONTEXT_EVENT_VAL ,VAL); + ALLOC0_VALACK_IN ( in_CONTEXT_EVENT_ACK ,ACK); + ALLOC0_SIGNAL_OUT(out_CONTEXT_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_OUT(out_CONTEXT_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); + ALLOC0_SIGNAL_OUT(out_CONTEXT_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); + ALLOC0_SIGNAL_OUT(out_CONTEXT_EVENT_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Tgeneral_data_t,_param->_size_instruction_address); + + ALLOC0_INTERFACE_END(); } @@ -154,13 +167,13 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - reg_CONTEXT_ADDRESS_PREVIOUS = new Tgeneral_data_t [_param->_nb_context]; - reg_CONTEXT_IS_DELAY_SLOT = new Tcontrol_t [_param->_nb_context]; - - internal_CONTEXT_HAVE_TRANSACTION = new Tcontrol_t [_param->_nb_context]; - internal_CONTEXT_ADDRESS_PREVIOUS = new Tgeneral_data_t [_param->_nb_context]; - internal_CONTEXT_IS_DELAY_SLOT = new Tcontrol_t [_param->_nb_context]; + ALLOC1(reg_CONTEXT_ADDRESS_PREVIOUS ,Tgeneral_data_t,_param->_nb_context); + ALLOC1(reg_CONTEXT_IS_DELAY_SLOT ,Tcontrol_t ,_param->_nb_context); + + ALLOC1(internal_CONTEXT_HAVE_TRANSACTION ,Tcontrol_t ,_param->_nb_context); + ALLOC1(internal_CONTEXT_ADDRESS_PREVIOUS ,Tgeneral_data_t,_param->_nb_context); + ALLOC1(internal_CONTEXT_IS_DELAY_SLOT ,Tcontrol_t ,_param->_nb_context); #ifdef STATISTICS - internal_DECOD_VAL = new Tcontrol_t [_param->_nb_inst_decod]; + ALLOC1(internal_DECOD_VAL ,Tcontrol_t ,_param->_nb_inst_decod); #endif } @@ -174,36 +187,15 @@ _param->_nb_context_select); - const uint32_t nb_opcod_type = 14; - const uint32_t tab_opcod_type [] = {MAX_OPCOD_0, - MAX_OPCOD_1 , - MAX_OPCOD_2 , - MAX_OPCOD_3 , - MAX_OPCOD_4 , - MAX_OPCOD_5 , - MAX_OPCOD_6 , - MAX_OPCOD_7 , - MAX_OPCOD_8 , - MAX_OPCOD_9 , - MAX_OPCOD_10, - MAX_OPCOD_11, - MAX_OPCOD_12, - MAX_OPCOD_13}; - - _function_decod = new function_decod_t *** [_param->_nb_context]; - _function_custom = new function_decod_t *** [_param->_nb_context]; + ALLOC3(_function_decod ,function_decod_t *,_param->_nb_context,nb_opcod_type,tab_opcod_type[it2]); + ALLOC3(_function_custom,function_decod_t *,_param->_nb_context,nb_opcod_type,tab_opcod_type[it2]); + for (uint32_t i=0; i<_param->_nb_context; i++) { - _function_decod [i] = new function_decod_t ** [nb_opcod_type]; - _function_custom [i] = new function_decod_t ** [nb_opcod_type]; for (uint32_t j=0; j_nb_context]; + ALLOC0(_decod_instruction,decod_instruction_t); + ALLOC1(_decod_param,decod_param_t *,_param->_nb_context); + for (uint32_t i=0; i<_param->_nb_context; i++) _decod_param [i] = new decod_param_t (_param->_size_general_data, Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp (revision 112) @@ -85,24 +85,22 @@ DELETE1_SIGNAL(in_CONTEXT_DEPTH , _param->_nb_context,_param->_size_depth); - DELETE_SIGNAL (out_CONTEXT_EVENT_VAL ,1); - DELETE_SIGNAL ( in_CONTEXT_EVENT_ACK ,1); - DELETE_SIGNAL (out_CONTEXT_EVENT_CONTEXT_ID ,_param->_size_context_id ); - DELETE_SIGNAL (out_CONTEXT_EVENT_DEPTH ,_param->_size_depth ); - DELETE_SIGNAL (out_CONTEXT_EVENT_TYPE ,_param->_size_event_type ); - DELETE_SIGNAL (out_CONTEXT_EVENT_IS_DELAY_SLOT,1 ); - DELETE_SIGNAL (out_CONTEXT_EVENT_ADDRESS ,_param->_size_instruction_address); - DELETE_SIGNAL (out_CONTEXT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address); + DELETE0_SIGNAL(out_CONTEXT_EVENT_VAL ,1); + DELETE0_SIGNAL( in_CONTEXT_EVENT_ACK ,1); + DELETE0_SIGNAL(out_CONTEXT_EVENT_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL(out_CONTEXT_EVENT_DEPTH ,_param->_size_depth ); + DELETE0_SIGNAL(out_CONTEXT_EVENT_TYPE ,_param->_size_event_type ); + DELETE0_SIGNAL(out_CONTEXT_EVENT_IS_DELAY_SLOT,1 ); + DELETE0_SIGNAL(out_CONTEXT_EVENT_ADDRESS ,_param->_size_instruction_address); + DELETE0_SIGNAL(out_CONTEXT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address); - - delete reg_CONTEXT_ADDRESS_PREVIOUS ; - delete [] reg_CONTEXT_IS_DELAY_SLOT ; - - delete [] internal_CONTEXT_HAVE_TRANSACTION ; - delete [] internal_CONTEXT_ADDRESS_PREVIOUS ; - delete [] internal_CONTEXT_IS_DELAY_SLOT ; - + DELETE1(reg_CONTEXT_ADDRESS_PREVIOUS ,_param->_nb_context); + DELETE1(reg_CONTEXT_IS_DELAY_SLOT ,_param->_nb_context); + DELETE1(internal_CONTEXT_HAVE_TRANSACTION ,_param->_nb_context); + DELETE1(internal_CONTEXT_ADDRESS_PREVIOUS ,_param->_nb_context); + DELETE1(internal_CONTEXT_IS_DELAY_SLOT ,_param->_nb_context); + #ifdef STATISTICS - delete [] internal_DECOD_VAL; + DELETE1(internal_DECOD_VAL ,_param->_nb_inst_decod); #endif } @@ -111,21 +109,12 @@ delete _priority; - - const uint32_t nb_opcod_type = 14; + DELETE3(_function_decod ,_param->_nb_context,nb_opcod_type,tab_opcod_type[it2]); + DELETE3(_function_custom ,_param->_nb_context,nb_opcod_type,tab_opcod_type[it2]); + DELETE0(_decod_instruction); for (uint32_t i=0; i<_param->_nb_context; i++) - { - for (uint32_t j=0; j_nb_context); + delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h (revision 112) @@ -10,4 +10,5 @@ #include "Behavioural/include/Types.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -58,29 +59,29 @@ _nb_inst (nb_inst) { - _val = new Tcontrol_t [_nb_inst]; - _context_id = new Tcontext_t [_nb_inst]; - _depth = new Tdepth_t [_nb_inst]; - _type = new Ttype_t [_nb_inst]; - _operation = new Toperation_t [_nb_inst]; - _no_execute = new Tcontrol_t [_nb_inst]; - _is_delay_slot = new Tcontrol_t [_nb_inst]; + ALLOC1(_val ,Tcontrol_t ,_nb_inst); + ALLOC1(_context_id ,Tcontext_t ,_nb_inst); + ALLOC1(_depth ,Tdepth_t ,_nb_inst); + ALLOC1(_type ,Ttype_t ,_nb_inst); + ALLOC1(_operation ,Toperation_t ,_nb_inst); + ALLOC1(_no_execute ,Tcontrol_t ,_nb_inst); + ALLOC1(_is_delay_slot ,Tcontrol_t ,_nb_inst); #ifdef DEBUG - _address = new Tgeneral_data_t [_nb_inst]; + ALLOC1(_address ,Tgeneral_data_t ,_nb_inst); #endif - _address_next = new Tgeneral_data_t [_nb_inst]; - _has_immediat = new Tcontrol_t [_nb_inst]; - _immediat = new Tgeneral_data_t [_nb_inst]; - _read_ra = new Tcontrol_t [_nb_inst]; - _num_reg_ra = new Tgeneral_address_t [_nb_inst]; - _read_rb = new Tcontrol_t [_nb_inst]; - _num_reg_rb = new Tgeneral_address_t [_nb_inst]; - _read_rc = new Tcontrol_t [_nb_inst]; - _num_reg_rc = new Tspecial_address_t [_nb_inst]; - _write_rd = new Tcontrol_t [_nb_inst]; - _num_reg_rd = new Tgeneral_address_t [_nb_inst]; - _write_re = new Tcontrol_t [_nb_inst]; - _num_reg_re = new Tspecial_address_t [_nb_inst]; - _exception_use = new Texception_t [_nb_inst]; - _exception = new Texception_t [_nb_inst]; + ALLOC1(_address_next ,Tgeneral_data_t ,_nb_inst); + ALLOC1(_has_immediat ,Tcontrol_t ,_nb_inst); + ALLOC1(_immediat ,Tgeneral_data_t ,_nb_inst); + ALLOC1(_read_ra ,Tcontrol_t ,_nb_inst); + ALLOC1(_num_reg_ra ,Tgeneral_address_t ,_nb_inst); + ALLOC1(_read_rb ,Tcontrol_t ,_nb_inst); + ALLOC1(_num_reg_rb ,Tgeneral_address_t ,_nb_inst); + ALLOC1(_read_rc ,Tcontrol_t ,_nb_inst); + ALLOC1(_num_reg_rc ,Tspecial_address_t ,_nb_inst); + ALLOC1(_write_rd ,Tcontrol_t ,_nb_inst); + ALLOC1(_num_reg_rd ,Tgeneral_address_t ,_nb_inst); + ALLOC1(_write_re ,Tcontrol_t ,_nb_inst); + ALLOC1(_num_reg_re ,Tspecial_address_t ,_nb_inst); + ALLOC1(_exception_use ,Texception_t ,_nb_inst); + ALLOC1(_exception ,Texception_t ,_nb_inst); for (uint32_t i=0; i<_nb_inst; i++) @@ -90,29 +91,29 @@ public : ~decod_queue_entry_t (void) { - delete [] _val ; - delete [] _context_id ; - delete [] _depth ; - delete [] _type ; - delete [] _operation ; - delete [] _no_execute ; - delete [] _is_delay_slot ; + DELETE1(_val ,_nb_inst); + DELETE1(_context_id ,_nb_inst); + DELETE1(_depth ,_nb_inst); + DELETE1(_type ,_nb_inst); + DELETE1(_operation ,_nb_inst); + DELETE1(_no_execute ,_nb_inst); + DELETE1(_is_delay_slot ,_nb_inst); #ifdef DEBUG - delete [] _address ; + DELETE1(_address ,_nb_inst); #endif - delete [] _address_next ; - delete [] _has_immediat ; - delete [] _immediat ; - delete [] _read_ra ; - delete [] _num_reg_ra ; - delete [] _read_rb ; - delete [] _num_reg_rb ; - delete [] _read_rc ; - delete [] _num_reg_rc ; - delete [] _write_rd ; - delete [] _num_reg_rd ; - delete [] _write_re ; - delete [] _num_reg_re ; - delete [] _exception_use ; - delete [] _exception ; + DELETE1(_address_next ,_nb_inst); + DELETE1(_has_immediat ,_nb_inst); + DELETE1(_immediat ,_nb_inst); + DELETE1(_read_ra ,_nb_inst); + DELETE1(_num_reg_ra ,_nb_inst); + DELETE1(_read_rb ,_nb_inst); + DELETE1(_num_reg_rb ,_nb_inst); + DELETE1(_read_rc ,_nb_inst); + DELETE1(_num_reg_rc ,_nb_inst); + DELETE1(_write_rd ,_nb_inst); + DELETE1(_num_reg_rd ,_nb_inst); + DELETE1(_write_re ,_nb_inst); + DELETE1(_num_reg_re ,_nb_inst); + DELETE1(_exception_use ,_nb_inst); + DELETE1(_exception ,_nb_inst); } }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp (revision 112) @@ -57,5 +57,5 @@ // ~~~~~[ Interface : "decod_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("decod_in",IN ,WEST,"Input of decod_queue", _param->_nb_inst_decod); + ALLOC1_INTERFACE_BEGIN("decod_in",IN ,WEST,_("Input of decod_queue"), _param->_nb_inst_decod); ALLOC1_VALACK_IN ( in_DECOD_IN_VAL ,VAL); @@ -85,9 +85,11 @@ ALLOC1_SIGNAL_IN ( in_DECOD_IN_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use ); ALLOC1_SIGNAL_IN ( in_DECOD_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_decod ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_decod); } // ~~~~~[ Interface : "decod_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("decod_out",OUT,EAST,"Output of decod_queue", _param->_nb_inst_decod); + ALLOC1_INTERFACE_BEGIN("decod_out",OUT,EAST,_("Output of decod_queue"), _param->_nb_inst_decod); ALLOC1_VALACK_OUT(out_DECOD_OUT_VAL ,VAL); @@ -117,20 +119,26 @@ ALLOC1_SIGNAL_OUT(out_DECOD_OUT_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use ); ALLOC1_SIGNAL_OUT(out_DECOD_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_decod ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_decod); } // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("depth",IN ,NORTH,"Depth", _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("depth",IN ,NORTH,_("Depth"), _param->_nb_context); ALLOC1_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_IN ( in_DEPTH_FULL ,"full" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("nb_inst",OUT,NORTH,"Instruction's number", _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("nb_inst",OUT,NORTH,_("Instruction's number"), _param->_nb_context); ALLOC1_SIGNAL_OUT(out_NB_INST_ALL ,"all" ,Tcontext_t ,_param->_size_nb_inst_decod); + + ALLOC1_INTERFACE_END(_param->_nb_context); } @@ -140,13 +148,14 @@ switch (_param->_queue_scheme) { - case DECOD_QUEUE_SCHEME_ONE_FIFO : reg_QUEUE = new std::list; break; + case DECOD_QUEUE_SCHEME_ONE_FIFO : ALLOC0(reg_QUEUE,std::list); break; case DECOD_QUEUE_SCHEME_MULTI_FIFO : ALLOC1(reg_QUEUE,std::list,_param->_nb_bank); break; } - reg_NB_INST = new uint32_t [_param->_nb_context]; + + ALLOC1(reg_NB_INST,uint32_t,_param->_nb_context); // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - internal_DECOD_IN_ACK = new Tcontrol_t [_param->_nb_inst_decod]; - internal_DECOD_OUT_VAL = new Tcontrol_t [_param->_nb_inst_decod]; - internal_DECOD_OUT_ACK = new Tcontrol_t [_param->_nb_inst_decod]; + ALLOC1(internal_DECOD_IN_ACK ,Tcontrol_t,_param->_nb_inst_decod); + ALLOC1(internal_DECOD_OUT_VAL,Tcontrol_t,_param->_nb_inst_decod); + ALLOC1(internal_DECOD_OUT_ACK,Tcontrol_t,_param->_nb_inst_decod); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp (revision 112) @@ -92,13 +92,34 @@ switch (_param->_queue_scheme) { - case DECOD_QUEUE_SCHEME_ONE_FIFO : delete reg_QUEUE; break; - case DECOD_QUEUE_SCHEME_MULTI_FIFO : DELETE1(reg_QUEUE,_param->_nb_bank); break; - } - delete [] reg_NB_INST; + case DECOD_QUEUE_SCHEME_ONE_FIFO : + { + while (not reg_QUEUE->empty()) + { + delete reg_QUEUE->front(); + reg_QUEUE->pop_front(); + } + + DELETE0(reg_QUEUE); + break; + } + case DECOD_QUEUE_SCHEME_MULTI_FIFO : + { + for (uint32_t i=0; i<_param->_nb_bank; ++i) + while (not reg_QUEUE[i].empty()) + { + delete reg_QUEUE[i].front(); + reg_QUEUE[i].pop_front(); + } + + DELETE1(reg_QUEUE,_param->_nb_bank); break; + } + } + + DELETE1(reg_NB_INST ,_param->_nb_context); // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] internal_DECOD_IN_ACK ; - delete [] internal_DECOD_OUT_VAL; - delete [] internal_DECOD_OUT_ACK; + DELETE1(internal_DECOD_IN_ACK ,_param->_nb_inst_decod); + DELETE1(internal_DECOD_OUT_VAL,_param->_nb_inst_decod); + DELETE1(internal_DECOD_OUT_ACK,_param->_nb_inst_decod); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_multi_fifo_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_multi_fifo_transition.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_multi_fifo_transition.cpp (revision 112) @@ -28,5 +28,9 @@ { for (uint32_t i=0; i<_param->_nb_bank; ++i) - reg_QUEUE[i].clear(); + while (not reg_QUEUE[i].empty()) + { + delete reg_QUEUE[i].front(); + reg_QUEUE[i].pop_front(); + } for (uint32_t i=0; i<_param->_nb_context; i++) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_one_fifo_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_one_fifo_transition.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_one_fifo_transition.cpp (revision 112) @@ -27,5 +27,9 @@ if (PORT_READ(in_NRESET) == 0) { - reg_QUEUE->clear(); + while (not reg_QUEUE->empty()) + { + delete reg_QUEUE->front(); + reg_QUEUE->pop_front(); + } for (uint32_t i=0; i<_param->_nb_context; i++) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp (revision 112) @@ -115,12 +115,12 @@ ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context); - ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t ); - ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t ); - ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t ); - ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t ); - ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); - ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t ); - ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t ); + ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t ); + ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t ); + ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t ); + ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t ); /******************************************************** @@ -144,7 +144,7 @@ { if (_param->_have_port_inst_ifetch_ptr) - INSTANCE_SC_SIGNAL(_Decod_unit,in_IFETCH_INST_IFETCH_PTR[i]); + INSTANCE0_SC_SIGNAL(_Decod_unit,in_IFETCH_INST_IFETCH_PTR[i]); if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL(_Decod_unit,in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]); + INSTANCE0_SC_SIGNAL(_Decod_unit,in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]); } @@ -210,14 +210,14 @@ INSTANCE1_SC_SIGNAL(_Decod_unit, in_CONTEXT_DEPTH ,_param->_nb_context); - INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_VAL ); - INSTANCE_SC_SIGNAL( _Decod_unit, in_CONTEXT_EVENT_ACK ); + INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_VAL ); + INSTANCE0_SC_SIGNAL( _Decod_unit, in_CONTEXT_EVENT_ACK ); if (_param->_have_port_context_id) - INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_CONTEXT_ID ); + INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_CONTEXT_ID ); if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_DEPTH ); - INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_TYPE ); - INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_IS_DELAY_SLOT ); - INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_ADDRESS ); - INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_ADDRESS_EPCR ); + INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_DEPTH ); + INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_TYPE ); + INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_IS_DELAY_SLOT ); + INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_ADDRESS ); + INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_ADDRESS_EPCR ); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -538,12 +538,12 @@ DELETE1_SC_SIGNAL( in_CONTEXT_DEPTH ,_param->_nb_context); - DELETE_SC_SIGNAL( out_CONTEXT_EVENT_VAL ); - DELETE_SC_SIGNAL( in_CONTEXT_EVENT_ACK ); - DELETE_SC_SIGNAL( out_CONTEXT_EVENT_CONTEXT_ID ); - DELETE_SC_SIGNAL( out_CONTEXT_EVENT_DEPTH ); - DELETE_SC_SIGNAL( out_CONTEXT_EVENT_TYPE ); - DELETE_SC_SIGNAL( out_CONTEXT_EVENT_IS_DELAY_SLOT ); - DELETE_SC_SIGNAL( out_CONTEXT_EVENT_ADDRESS ); - DELETE_SC_SIGNAL( out_CONTEXT_EVENT_ADDRESS_EPCR ); + DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_VAL ); + DELETE0_SC_SIGNAL( in_CONTEXT_EVENT_ACK ); + DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_CONTEXT_ID ); + DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_DEPTH ); + DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_TYPE ); + DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_IS_DELAY_SLOT ); + DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_ADDRESS ); + DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_ADDRESS_EPCR ); } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp (revision 112) @@ -58,13 +58,14 @@ // ~~~~~[ Interface : "ifetch" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("ifetch", IN, WEST, "Instruction's bundle", _param->_nb_context, _param->_nb_inst_fetch[it1]); - + ALLOC2_INTERFACE_BEGIN("ifetch", IN, WEST, _("Instruction's bundle"), _param->_nb_context, _param->_nb_inst_fetch[it1]); _ALLOC2_VALACK_IN ( in_IFETCH_VAL ,VAL, _param->_nb_context, _param->_nb_inst_fetch[it1]); _ALLOC2_VALACK_OUT(out_IFETCH_ACK ,ACK, _param->_nb_context, _param->_nb_inst_fetch[it1]); _ALLOC2_SIGNAL_IN ( in_IFETCH_INSTRUCTION,"instruction", Tinstruction_t, _param->_size_instruction,_param->_nb_context, _param->_nb_inst_fetch[it1]); - } - { - ALLOC1_INTERFACE("ifetch", IN, WEST, "Instruction's bundle", _param->_nb_context); + + ALLOC2_INTERFACE_END(_param->_nb_context, _param->_nb_inst_fetch[it1]); + } + { + ALLOC1_INTERFACE_BEGIN("ifetch", IN, WEST, _("Instruction's bundle"), _param->_nb_context); ALLOC1_SIGNAL_IN (in_IFETCH_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); @@ -75,9 +76,11 @@ ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); ALLOC1_SIGNAL_IN (in_IFETCH_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("decod", OUT, EAST, "Instructiont decoded", _param->_nb_inst_decod); + ALLOC1_INTERFACE_BEGIN("decod", OUT, EAST, _("Instruction decoded"), _param->_nb_inst_decod); ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL); @@ -107,9 +110,11 @@ ALLOC1_SIGNAL_OUT(out_DECOD_EXCEPTION_USE,"exception_use",Texception_t ,_param->_size_exception_use ); ALLOC1_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_decod ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_decod); } // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("predict",OUT,NORTH,"Decod a branch -> inform the branch predictor.",_param->_nb_inst_decod); + ALLOC1_INTERFACE_BEGIN("predict",OUT,NORTH,_("Decod a branch -> inform the branch predictor."),_param->_nb_inst_decod); ALLOC1_VALACK_OUT(out_PREDICT_VAL ,VAL); @@ -125,43 +130,53 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_IN ( in_PREDICT_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ); - } - + + ALLOC1_INTERFACE_END(_param->_nb_inst_decod); + } + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("depth",IN ,NORTH,"Depth", _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("depth",IN ,NORTH,_("Depth"), _param->_nb_context); ALLOC1_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_IN ( in_DEPTH_FULL ,"full" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("nb_inst",OUT,NORTH,"Instruction's number", _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("nb_inst",OUT,NORTH,_("Instruction's number"), _param->_nb_context); ALLOC1_SIGNAL_OUT(out_NB_INST_DECOD_ALL ,"decod_all" ,Tcontext_t ,_param->_size_nb_inst_decod); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("context", IN, NORTH, "context's information", _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("context", IN, NORTH, _("context's information"), _param->_nb_context); ALLOC1_SIGNAL_IN (in_CONTEXT_DECOD_ENABLE,"decod_enable",Tcontrol_t,1); ALLOC1_SIGNAL_IN (in_CONTEXT_DEPTH_VAL ,"depth_val" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN (in_CONTEXT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "context_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("context_event", OUT, NORTH, "context's evenement"); - - ALLOC_VALACK_OUT(out_CONTEXT_EVENT_VAL ,VAL); - ALLOC_VALACK_IN ( in_CONTEXT_EVENT_ACK ,ACK); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_instruction_address); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Tgeneral_data_t,_param->_size_instruction_address); + ALLOC0_INTERFACE_BEGIN("context_event", OUT, NORTH, _("context's evenement")); + + ALLOC0_VALACK_OUT(out_CONTEXT_EVENT_VAL ,VAL); + ALLOC0_VALACK_IN ( in_CONTEXT_EVENT_ACK ,ACK); + ALLOC0_SIGNAL_OUT(out_CONTEXT_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_OUT(out_CONTEXT_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); + ALLOC0_SIGNAL_OUT(out_CONTEXT_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); + ALLOC0_SIGNAL_OUT(out_CONTEXT_EVENT_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Tgeneral_data_t,_param->_size_instruction_address); + + ALLOC0_INTERFACE_END(); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp (revision 112) @@ -89,12 +89,12 @@ DELETE1_SIGNAL(in_CONTEXT_DEPTH ,_param->_nb_context,_param->_size_depth); - DELETE_SIGNAL(out_CONTEXT_EVENT_VAL ,1); - DELETE_SIGNAL( in_CONTEXT_EVENT_ACK ,1); - DELETE_SIGNAL(out_CONTEXT_EVENT_CONTEXT_ID ,_param->_size_context_id ); - DELETE_SIGNAL(out_CONTEXT_EVENT_DEPTH ,_param->_size_depth ); - DELETE_SIGNAL(out_CONTEXT_EVENT_TYPE ,_param->_size_event_type ); - DELETE_SIGNAL(out_CONTEXT_EVENT_IS_DELAY_SLOT ,1 ); - DELETE_SIGNAL(out_CONTEXT_EVENT_ADDRESS ,_param->_size_instruction_address); - DELETE_SIGNAL(out_CONTEXT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address); + DELETE0_SIGNAL(out_CONTEXT_EVENT_VAL ,1); + DELETE0_SIGNAL( in_CONTEXT_EVENT_ACK ,1); + DELETE0_SIGNAL(out_CONTEXT_EVENT_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL(out_CONTEXT_EVENT_DEPTH ,_param->_size_depth ); + DELETE0_SIGNAL(out_CONTEXT_EVENT_TYPE ,_param->_size_event_type ); + DELETE0_SIGNAL(out_CONTEXT_EVENT_IS_DELAY_SLOT ,1 ); + DELETE0_SIGNAL(out_CONTEXT_EVENT_ADDRESS ,_param->_size_instruction_address); + DELETE0_SIGNAL(out_CONTEXT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp (revision 112) @@ -182,6 +182,6 @@ if (_param->_have_port_depth) { - INSTANCE_SC_SIGNAL(_Front_end_Glue,out_DEPTH_DECOD_UNIT_MIN [i][j]); - INSTANCE_SC_SIGNAL(_Front_end_Glue,out_CONTEXT_DECOD_UNIT_DEPTH [i][j]); + INSTANCE0_SC_SIGNAL(_Front_end_Glue,out_DEPTH_DECOD_UNIT_MIN [i][j]); + INSTANCE0_SC_SIGNAL(_Front_end_Glue,out_CONTEXT_DECOD_UNIT_DEPTH [i][j]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp (revision 112) @@ -58,20 +58,24 @@ // ~~~~~[ Interface : "ifetch" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("ifetch",OUT,SOUTH,_("ifetch"),_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + ALLOC2_INTERFACE_BEGIN("ifetch",OUT,SOUTH,_("ifetch"),_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); _ALLOC2_SIGNAL_OUT(out_IFETCH_DECOD_UNIT_CONTEXT_ID ,"DECOD_UNIT_CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + ALLOC2_INTERFACE_END(_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); } // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("decod",OUT,EAST,_("decod"),_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_INTERFACE_BEGIN("decod",OUT,EAST,_("decod"),_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_OUT(out_DECOD_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_DECOD_DECOD_UNIT_CONTEXT_ID ,"DECOD_UNIT_CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); } // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("branch_complete",IN,EAST,_("branch_complete"),_param->_nb_inst_branch_complete); + ALLOC1_INTERFACE_BEGIN("branch_complete",IN,EAST,_("branch_complete"),_param->_nb_inst_branch_complete); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_VAL ,"VAL" ,Tcontrol_t ,1); @@ -86,9 +90,11 @@ ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_CONTEXT_STATE_ACK ,"CONTEXT_STATE_ACK" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_CONTEXT_STATE_MISS_PREDICTION ,"CONTEXT_STATE_MISS_PREDICTION" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_complete); } // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("event",OUT,EAST,_("event"),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("event",OUT,EAST,_("event"),_param->_nb_context); ALLOC1_SIGNAL_OUT (out_EVENT_VAL ,"VAL" ,Tcontrol_t ,1); @@ -120,9 +126,11 @@ ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_DEPTH ,"CONTEXT_STATE_DEPTH" ,Tdepth_t ,_param->_size_depth); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("depth",OUT,EAST,_("depth"),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("depth",OUT,EAST,_("depth"),_param->_nb_context); // ALLOC1_SIGNAL_OUT (out_DEPTH_CURRENT ,"CURRENT" ,Tdepth_t ,_param->_size_depth ); @@ -138,7 +146,9 @@ ALLOC1_SIGNAL_OUT (out_DEPTH_CONTEXT_STATE_MIN ,"CONTEXT_STATE_MIN" ,Tdepth_t ,_param->_size_depth ); + + ALLOC1_INTERFACE_END(_param->_nb_context); } { - ALLOC2_INTERFACE("depth",OUT,EAST,_("depth"),_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + ALLOC2_INTERFACE_BEGIN("depth",OUT,EAST,_("depth"),_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); // _ALLOC2_SIGNAL_OUT(out_DEPTH_DECOD_UNIT_CURRENT ,"DECOD_UNIT_CURRENT" ,Tdepth_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); @@ -146,21 +156,27 @@ _ALLOC2_SIGNAL_OUT(out_DEPTH_DECOD_UNIT_MAX ,"DECOD_UNIT_MAX" ,Tdepth_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); _ALLOC2_SIGNAL_OUT(out_DEPTH_DECOD_UNIT_FULL ,"DECOD_UNIT_FULL" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + ALLOC2_INTERFACE_END(_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); } // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("context",OUT,EAST,_("context"),_param->_nb_decod_unit,_param->_translate_context_id_from_decod_unit[it1].size()); + ALLOC2_INTERFACE_BEGIN("context",OUT,EAST,_("context"),_param->_nb_decod_unit,_param->_translate_context_id_from_decod_unit[it1].size()); _ALLOC2_SIGNAL_OUT(out_CONTEXT_DECOD_UNIT_DEPTH_VAL ,"DECOD_UNIT_DEPTH_VAL" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); _ALLOC2_SIGNAL_OUT(out_CONTEXT_DECOD_UNIT_DEPTH ,"DECOD_UNIT_DEPTH" ,Tdepth_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + ALLOC2_INTERFACE_END(_param->_nb_decod_unit,_param->_translate_context_id_from_decod_unit[it1].size()); } // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("nb_inst",OUT,EAST,_("nb inst"),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("nb_inst",OUT,EAST,_("nb inst"),_param->_nb_context); ALLOC1_SIGNAL_OUT(out_NB_INST_DECOD_ALL ,"DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod); ALLOC1_SIGNAL_IN ( in_NB_INST_DECOD_UNIT_DECOD_ALL ,"DECOD_UNIT_DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod); ALLOC1_SIGNAL_OUT(out_NB_INST_CONTEXT_STATE_DECOD_ALL ,"CONTEXT_STATE_DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod); + + ALLOC1_INTERFACE_END(_param->_nb_context); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp (revision 112) @@ -51,29 +51,29 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC_SC_SIGNAL (out_ADDRESS_VAL ,"out_ADDRESS_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_ADDRESS_ACK ," in_ADDRESS_ACK ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS ,"out_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t); + ALLOC0_SC_SIGNAL (out_ADDRESS_VAL ,"out_ADDRESS_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL ( in_ADDRESS_ACK ," in_ADDRESS_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS ,"out_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t); ALLOC1_SC_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,"out_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); - ALLOC_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR ,"out_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); - ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_STATE ,"out_ADDRESS_BRANCH_STATE ",Tbranch_state_t ); - ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); - ALLOC_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t); - ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t); - ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t); - ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ); + ALLOC0_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR ,"out_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); + ALLOC0_SC_SIGNAL (out_ADDRESS_BRANCH_STATE ,"out_ADDRESS_BRANCH_STATE ",Tbranch_state_t ); + ALLOC0_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); + ALLOC0_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t); + ALLOC0_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t); + ALLOC0_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ); + ALLOC0_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t); + ALLOC0_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ); ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); - ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); -//ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_IS_CURRENT ," in_PREDICT_BRANCH_IS_CURRENT ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); - ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); - ALLOC_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t); - ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Tgeneral_address_t); - ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL ," in_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t ); + ALLOC0_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); +//ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_IS_CURRENT ," in_PREDICT_BRANCH_IS_CURRENT ",Tcontrol_t ); + ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); + ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); + ALLOC0_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t); + ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Tgeneral_address_t); + ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL ," in_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL ( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t ); /******************************************************** @@ -86,33 +86,33 @@ (*(_Address_management->in_NRESET)) (*(in_NRESET)); - INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_VAL ); - INSTANCE_SC_SIGNAL (_Address_management, in_ADDRESS_ACK ); - INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS ); + INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_VAL ); + INSTANCE0_SC_SIGNAL (_Address_management, in_ADDRESS_ACK ); + INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS ); INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction); if (_param->_have_port_inst_ifetch_ptr) - INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR ); - INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE ); + INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR ); + INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE ); if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID); - INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_VAL ); - INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_ACK ); - INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS ); - INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT ); - INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE ); - INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT ); - INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE ); + INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID); + INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_VAL ); + INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_ACK ); + INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS ); + INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT ); + INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE ); + INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT ); + INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE ); INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction); if (_param->_have_port_inst_ifetch_ptr) - INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR ); -//INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_IS_CURRENT ); - INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE ); + INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR ); +//INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_IS_CURRENT ); + INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE ); if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); - INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_VAL ); - INSTANCE_SC_SIGNAL (_Address_management,out_EVENT_ACK ); - INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS ); - INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT ); - INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT_VAL ); - INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_IS_DS_TAKE ); + INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); + INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_VAL ); + INSTANCE0_SC_SIGNAL (_Address_management,out_EVENT_ACK ); + INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS ); + INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT ); + INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT_VAL ); + INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_IS_DS_TAKE ); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp (revision 112) @@ -16,6 +16,4 @@ namespace ifetch_unit { namespace address_management { - - #undef FUNCTION @@ -58,52 +56,62 @@ // ~~~~~[ Interface : "address" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("address", OUT, SOUTH, "Access at request icache."); + ALLOC0_INTERFACE_BEGIN("address", OUT, SOUTH, _("Access at request icache.")); - ALLOC_VALACK_OUT (out_ADDRESS_VAL ,VAL); - ALLOC_VALACK_IN ( in_ADDRESS_ACK ,ACK); - ALLOC_SIGNAL_OUT (out_ADDRESS_INSTRUCTION_ADDRESS ,"instruction_address" ,Tgeneral_address_t,_param->_size_instruction_address ); - ALLOC_SIGNAL_OUT (out_ADDRESS_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr ); - ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); - ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); + ALLOC0_VALACK_OUT (out_ADDRESS_VAL ,VAL); + ALLOC0_VALACK_IN ( in_ADDRESS_ACK ,ACK); + ALLOC0_SIGNAL_OUT (out_ADDRESS_INSTRUCTION_ADDRESS ,"instruction_address" ,Tgeneral_address_t,_param->_size_instruction_address ); + ALLOC0_SIGNAL_OUT (out_ADDRESS_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr ); + ALLOC0_SIGNAL_OUT (out_ADDRESS_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); + ALLOC0_SIGNAL_OUT (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); + + ALLOC0_INTERFACE_END(); } { - ALLOC1_INTERFACE("address", OUT, SOUTH, "Access at request icache.",_param->_nb_instruction); + ALLOC1_INTERFACE_BEGIN("address", OUT, SOUTH, _("Access at request icache."),_param->_nb_instruction); ALLOC1_SIGNAL_OUT(out_ADDRESS_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_instruction); } // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("predict", IN, NORTH, "Request the prediction unit."); + ALLOC0_INTERFACE_BEGIN("predict", IN, NORTH, _("Request the prediction unit.")); - ALLOC_VALACK_OUT (out_PREDICT_VAL ,VAL); - ALLOC_VALACK_IN ( in_PREDICT_ACK ,ACK); - ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address); - ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address); - ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address); - ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); -// ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_IS_CURRENT ,"branch_is_current" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); - ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); - ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); + ALLOC0_VALACK_OUT (out_PREDICT_VAL ,VAL); + ALLOC0_VALACK_IN ( in_PREDICT_ACK ,ACK); + ALLOC0_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); +// ALLOC0_SIGNAL_IN ( in_PREDICT_BRANCH_IS_CURRENT ,"branch_is_current" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); + ALLOC0_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); + ALLOC0_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); + + ALLOC0_INTERFACE_END(); } { - ALLOC1_INTERFACE("predict", IN, NORTH, "Request the prediction unit.",_param->_nb_instruction); + ALLOC1_INTERFACE_BEGIN("predict", IN, NORTH, _("Request the prediction unit."),_param->_nb_instruction); ALLOC1_SIGNAL_IN (in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_instruction); } // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("event", IN, SOUTH, "Event (miss, exception ...)"); + ALLOC0_INTERFACE_BEGIN("event", IN, SOUTH, _("Event (miss, exception ...)")); - ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL); - ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK); - ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); - ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address); - ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"address_next_val",Tcontrol_t,1); - ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1); + ALLOC0_VALACK_IN ( in_EVENT_VAL ,VAL); + ALLOC0_VALACK_OUT(out_EVENT_ACK ,ACK); + ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"address_next_val",Tcontrol_t,1); + ALLOC0_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1); + + ALLOC0_INTERFACE_END(); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -27,44 +28,37 @@ delete in_CLOCK ; delete in_NRESET; - - delete out_ADDRESS_VAL ; - delete in_ADDRESS_ACK ; - delete out_ADDRESS_INSTRUCTION_ADDRESS ; - delete [] out_ADDRESS_INSTRUCTION_ENABLE ; - if (_param->_have_port_inst_ifetch_ptr) - delete out_ADDRESS_INST_IFETCH_PTR ; - delete out_ADDRESS_BRANCH_STATE ; - if (_param->_have_port_depth) - delete out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID; - delete out_PREDICT_VAL ; - delete in_PREDICT_ACK ; - delete out_PREDICT_PC_PREVIOUS ; - delete out_PREDICT_PC_CURRENT ; - delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ; - delete in_PREDICT_PC_NEXT ; - delete in_PREDICT_PC_NEXT_IS_DS_TAKE ; - delete [] in_PREDICT_INSTRUCTION_ENABLE ; - if (_param->_have_port_inst_ifetch_ptr) - delete in_PREDICT_INST_IFETCH_PTR ; -// delete in_PREDICT_BRANCH_IS_CURRENT ; - delete in_PREDICT_BRANCH_STATE ; - if (_param->_have_port_depth) - delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID; - delete in_EVENT_VAL ; - delete out_EVENT_ACK ; - delete in_EVENT_ADDRESS ; - delete in_EVENT_ADDRESS_NEXT ; - delete in_EVENT_ADDRESS_NEXT_VAL ; - delete in_EVENT_IS_DS_TAKE ; - - // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - if (usage_is_set(_usage,USE_SYSTEMC)) - { - delete reg_PC_ACCESS_INSTRUCTION_ENABLE ; - delete reg_PC_CURRENT_INSTRUCTION_ENABLE; - delete reg_PC_NEXT_INSTRUCTION_ENABLE ; - } + + DELETE0_SIGNAL(out_ADDRESS_VAL ,1); + DELETE0_SIGNAL( in_ADDRESS_ACK ,1); + DELETE0_SIGNAL(out_ADDRESS_INSTRUCTION_ADDRESS ,_param->_size_instruction_address ); + DELETE0_SIGNAL(out_ADDRESS_INST_IFETCH_PTR ,_param->_size_inst_ifetch_ptr ); + DELETE0_SIGNAL(out_ADDRESS_BRANCH_STATE ,_param->_size_branch_state ); + DELETE0_SIGNAL(out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth); + DELETE1_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,1,_param->_nb_instruction); + + DELETE0_SIGNAL(out_PREDICT_VAL ,1); + DELETE0_SIGNAL( in_PREDICT_ACK ,1); + DELETE0_SIGNAL(out_PREDICT_PC_PREVIOUS ,_param->_size_instruction_address); + DELETE0_SIGNAL(out_PREDICT_PC_CURRENT ,_param->_size_instruction_address); + DELETE0_SIGNAL(out_PREDICT_PC_CURRENT_IS_DS_TAKE ,1); + DELETE0_SIGNAL( in_PREDICT_PC_NEXT ,_param->_size_instruction_address); + DELETE0_SIGNAL( in_PREDICT_PC_NEXT_IS_DS_TAKE ,1); +// DELETE0_SIGNAL( in_PREDICT_BRANCH_IS_CURRENT ,1); + DELETE0_SIGNAL( in_PREDICT_BRANCH_STATE ,_param->_size_branch_state); + DELETE0_SIGNAL( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth); + DELETE0_SIGNAL( in_PREDICT_INST_IFETCH_PTR ,_param->_size_inst_ifetch_ptr); + DELETE1_SIGNAL(in_PREDICT_INSTRUCTION_ENABLE ,1,_param->_nb_instruction); + + DELETE0_SIGNAL( in_EVENT_VAL ,1); + DELETE0_SIGNAL(out_EVENT_ACK ,1); + DELETE0_SIGNAL( in_EVENT_ADDRESS ,_param->_size_instruction_address); + DELETE0_SIGNAL( in_EVENT_ADDRESS_NEXT ,_param->_size_instruction_address); + DELETE0_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL,1); + DELETE0_SIGNAL( in_EVENT_IS_DS_TAKE ,1); + + DELETE1(reg_PC_ACCESS_INSTRUCTION_ENABLE ,_param->_nb_instruction); + DELETE1(reg_PC_CURRENT_INSTRUCTION_ENABLE,_param->_nb_instruction); + DELETE1(reg_PC_NEXT_INSTRUCTION_ENABLE ,_param->_nb_instruction); } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp (revision 112) @@ -68,27 +68,27 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC_SC_SIGNAL ( in_ADDRESS_VAL ," in_ADDRESS_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_ADDRESS_ACK ,"out_ADDRESS_ACK ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_ADDRESS_IFETCH_QUEUE_ID ,"out_ADDRESS_IFETCH_QUEUE_ID ",Tifetch_queue_ptr_t ); + ALLOC0_SC_SIGNAL( in_ADDRESS_VAL ," in_ADDRESS_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_ADDRESS_ACK ,"out_ADDRESS_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_ADDRESS_IFETCH_QUEUE_ID ,"out_ADDRESS_IFETCH_QUEUE_ID ",Tifetch_queue_ptr_t ); ALLOC1_SC_SIGNAL( in_ADDRESS_INSTRUCTION_ENABLE ," in_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); - ALLOC_SC_SIGNAL ( in_ADDRESS_INSTRUCTION_ADDRESS ," in_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t ); - ALLOC_SC_SIGNAL ( in_ADDRESS_INST_IFETCH_PTR ," in_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); - ALLOC_SC_SIGNAL ( in_ADDRESS_BRANCH_STATE ," in_ADDRESS_BRANCH_STATE ",Tbranch_state_t ); - ALLOC_SC_SIGNAL ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID," in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); + ALLOC0_SC_SIGNAL( in_ADDRESS_INSTRUCTION_ADDRESS ," in_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t ); + ALLOC0_SC_SIGNAL( in_ADDRESS_INST_IFETCH_PTR ," in_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); + ALLOC0_SC_SIGNAL( in_ADDRESS_BRANCH_STATE ," in_ADDRESS_BRANCH_STATE ",Tbranch_state_t ); + ALLOC0_SC_SIGNAL( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID," in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_instruction); ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_instruction); ALLOC1_SC_SIGNAL(out_DECOD_INSTRUCTION ,"out_DECOD_INSTRUCTION ",Tinstruction_t ,_param->_nb_instruction); - ALLOC_SC_SIGNAL (out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_address_t ); - ALLOC_SC_SIGNAL (out_DECOD_INST_IFETCH_PTR ,"out_DECOD_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); - ALLOC_SC_SIGNAL (out_DECOD_BRANCH_STATE ,"out_DECOD_BRANCH_STATE ",Tbranch_state_t ); - ALLOC_SC_SIGNAL (out_DECOD_BRANCH_UPDATE_PREDICTION_ID ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ); - ALLOC_SC_SIGNAL (out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Tprediction_ptr_t ); - ALLOC_SC_SIGNAL ( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ); + ALLOC0_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_address_t ); + ALLOC0_SC_SIGNAL(out_DECOD_INST_IFETCH_PTR ,"out_DECOD_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); + ALLOC0_SC_SIGNAL(out_DECOD_BRANCH_STATE ,"out_DECOD_BRANCH_STATE ",Tbranch_state_t ); + ALLOC0_SC_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ); + ALLOC0_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Tprediction_ptr_t ); + ALLOC0_SC_SIGNAL( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ); ALLOC1_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_instruction); - ALLOC_SC_SIGNAL ( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ); - ALLOC_SC_SIGNAL ( in_EVENT_RESET_VAL ," in_EVENT_RESET_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_EVENT_RESET_ACK ,"out_EVENT_RESET_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ); + ALLOC0_SC_SIGNAL( in_EVENT_RESET_VAL ," in_EVENT_RESET_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_EVENT_RESET_ACK ,"out_EVENT_RESET_ACK ",Tcontrol_t ); /******************************************************** @@ -101,33 +101,33 @@ (*(_Ifetch_queue->in_NRESET)) (*(in_NRESET)); - INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_VAL ); - INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_ACK ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_VAL ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_ADDRESS_ACK ); if (_param->_have_port_ifetch_queue_ptr) - INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_IFETCH_QUEUE_ID ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_ADDRESS_IFETCH_QUEUE_ID ); INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction); - INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INSTRUCTION_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ADDRESS ); if (_param->_have_port_inst_ifetch_ptr) - INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INST_IFETCH_PTR ); - INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_STATE ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INST_IFETCH_PTR ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_BRANCH_STATE ); if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID); + INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID); INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_VAL ,_param->_nb_instruction); INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_DECOD_ACK ,_param->_nb_instruction); INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_INSTRUCTION ,_param->_nb_instruction); - INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_ADDRESS ); if (_param->_have_port_inst_ifetch_ptr) - INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_INST_IFETCH_PTR ); - INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_STATE ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_INST_IFETCH_PTR ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_BRANCH_STATE ); if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_UPDATE_PREDICTION_ID ); - INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_EXCEPTION ); - INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_VAL ); - INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ICACHE_RSP_ACK ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_BRANCH_UPDATE_PREDICTION_ID ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_EXCEPTION ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_VAL ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_ICACHE_RSP_ACK ); if (_param->_have_port_ifetch_queue_ptr) - INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_PACKET_ID ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_PACKET_ID ); INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_instruction); - INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_ERROR ); - INSTANCE_SC_SIGNAL (_Ifetch_queue, in_EVENT_RESET_VAL ); - INSTANCE_SC_SIGNAL (_Ifetch_queue,out_EVENT_RESET_ACK ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_ERROR ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_EVENT_RESET_VAL ); + INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_EVENT_RESET_ACK ); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp (revision 112) @@ -48,5 +48,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -58,60 +58,73 @@ // ~~~~~[ Interface : "address" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("address", IN, NORTH, "Transaction with PC management."); + ALLOC0_INTERFACE_BEGIN("address", IN, NORTH, "Transaction with PC management."); - ALLOC_VALACK_IN ( in_ADDRESS_VAL ,VAL); - ALLOC_VALACK_OUT(out_ADDRESS_ACK ,ACK); - ALLOC_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS ,"instruction_address" ,Tgeneral_address_t ,_param->_size_instruction_address ); - ALLOC_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr); - ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); - ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); - ALLOC_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID ,"ifetch_queue_id" ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr); + ALLOC0_VALACK_IN ( in_ADDRESS_VAL ,VAL); + ALLOC0_VALACK_OUT(out_ADDRESS_ACK ,ACK); + ALLOC0_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS ,"instruction_address" ,Tgeneral_address_t ,_param->_size_instruction_address ); + ALLOC0_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr); + ALLOC0_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); + ALLOC0_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); + ALLOC0_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID ,"ifetch_queue_id" ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr); + ALLOC0_INTERFACE_END(); } { - ALLOC1_INTERFACE("address", IN, NORTH, "Transaction with PC management.",_param->_nb_instruction); + ALLOC1_INTERFACE_BEGIN("address", IN, NORTH, _("Transaction with PC management."),_param->_nb_instruction); ALLOC1_SIGNAL_IN( in_ADDRESS_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_instruction); } // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage.",_param->_nb_instruction); + ALLOC1_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage."),_param->_nb_instruction); ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL); ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK); ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION,"instruction",Tinstruction_t,_param->_size_instruction); + + ALLOC1_INTERFACE_END(_param->_nb_instruction); } { - ALLOC_INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage."); + ALLOC0_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage.")); - ALLOC_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address ); - ALLOC_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr ); - ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); - ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); - ALLOC_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); + ALLOC0_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address ); + ALLOC0_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr ); + ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); + ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); + ALLOC0_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); + + ALLOC0_INTERFACE_END(); } // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("icache_rsp", IN, WEST, "Respons from Instruction Cache."); + ALLOC0_INTERFACE_BEGIN("icache_rsp", IN, WEST, _("Respons from Instruction Cache.")); - ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); - ALLOC_VALACK_OUT(out_ICACHE_RSP_ACK ,ACK); - ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr); - ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t,_param->_size_icache_error); + ALLOC0_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); + ALLOC0_VALACK_OUT(out_ICACHE_RSP_ACK ,ACK); + ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr); + ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t,_param->_size_icache_error); + + ALLOC0_INTERFACE_END(); } { - ALLOC1_INTERFACE("icache_rsp", IN, WEST, "Respons from Instruction Cache.",_param->_nb_instruction); + ALLOC1_INTERFACE_BEGIN("icache_rsp", IN, WEST, _("Respons from Instruction Cache."),_param->_nb_instruction); ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction); + + ALLOC1_INTERFACE_END(_param->_nb_instruction); } // ~~~~~[ Interface "event_reset" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("event_reset", IN, NORTH, "An event occure and reset queue."); + ALLOC0_INTERFACE_BEGIN("event_reset", IN, NORTH, _("An event occure and reset queue.")); - ALLOC_VALACK_IN ( in_EVENT_RESET_VAL,VAL); - ALLOC_VALACK_OUT(out_EVENT_RESET_ACK,ACK); + ALLOC0_VALACK_IN ( in_EVENT_RESET_VAL,VAL); + ALLOC0_VALACK_OUT(out_EVENT_RESET_ACK,ACK); + + ALLOC0_INTERFACE_END(); } @@ -119,5 +132,5 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - internal_DECOD_VAL = new Tcontrol_t [_param->_nb_instruction]; + ALLOC1(internal_DECOD_VAL,Tcontrol_t,_param->_nb_instruction); _queue = new ifetch_queue_entry_t * [_param->_size_queue]; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -28,33 +29,30 @@ delete in_NRESET; - delete in_ADDRESS_VAL ; - delete out_ADDRESS_ACK ; - if (_param->_have_port_ifetch_queue_ptr) - delete out_ADDRESS_IFETCH_QUEUE_ID ; - delete [] in_ADDRESS_INSTRUCTION_ENABLE ; - delete in_ADDRESS_INSTRUCTION_ADDRESS ; - if (_param->_have_port_inst_ifetch_ptr) - delete in_ADDRESS_INST_IFETCH_PTR ; - delete in_ADDRESS_BRANCH_STATE ; - if (_param->_have_port_depth) - delete in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID; - delete [] out_DECOD_VAL ; - delete [] in_DECOD_ACK ; - delete [] out_DECOD_INSTRUCTION ; - delete out_DECOD_ADDRESS ; - if (_param->_have_port_inst_ifetch_ptr) - delete out_DECOD_INST_IFETCH_PTR ; - delete out_DECOD_BRANCH_STATE ; - if (_param->_have_port_depth) - delete out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; - delete out_DECOD_EXCEPTION ; - delete in_ICACHE_RSP_VAL ; - delete out_ICACHE_RSP_ACK ; - if (_param->_have_port_ifetch_queue_ptr) - delete in_ICACHE_RSP_PACKET_ID ; - delete [] in_ICACHE_RSP_INSTRUCTION ; - delete in_ICACHE_RSP_ERROR ; - delete in_EVENT_RESET_VAL ; - delete out_EVENT_RESET_ACK ; + DELETE0_SIGNAL( in_ADDRESS_VAL ,1); + DELETE0_SIGNAL(out_ADDRESS_ACK ,1); + DELETE0_SIGNAL( in_ADDRESS_INSTRUCTION_ADDRESS ,_param->_size_instruction_address); + DELETE0_SIGNAL( in_ADDRESS_INST_IFETCH_PTR ,_param->_size_inst_ifetch_ptr); + DELETE0_SIGNAL( in_ADDRESS_BRANCH_STATE ,_param->_size_branch_state ); + DELETE0_SIGNAL( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth ); + DELETE0_SIGNAL(out_ADDRESS_IFETCH_QUEUE_ID ,_param->_size_ifetch_queue_ptr); + DELETE1_SIGNAL( in_ADDRESS_INSTRUCTION_ENABLE ,1,_param->_nb_instruction); + + DELETE1_SIGNAL(out_DECOD_VAL ,1,_param->_nb_instruction); + DELETE1_SIGNAL( in_DECOD_ACK ,1,_param->_nb_instruction); + DELETE1_SIGNAL(out_DECOD_INSTRUCTION ,_param->_size_instruction,_param->_nb_instruction); + DELETE0_SIGNAL(out_DECOD_ADDRESS ,_param->_size_instruction_address); + DELETE0_SIGNAL(out_DECOD_INST_IFETCH_PTR ,_param->_size_inst_ifetch_ptr ); + DELETE0_SIGNAL(out_DECOD_BRANCH_STATE ,_param->_size_branch_state ); + DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth ); + DELETE0_SIGNAL(out_DECOD_EXCEPTION ,_param->_size_exception_ifetch); + + DELETE0_SIGNAL( in_ICACHE_RSP_VAL ,1); + DELETE0_SIGNAL(out_ICACHE_RSP_ACK ,1); + DELETE0_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param->_size_ifetch_queue_ptr); + DELETE0_SIGNAL( in_ICACHE_RSP_ERROR ,_param->_size_icache_error); + DELETE1_SIGNAL( in_ICACHE_RSP_INSTRUCTION,_param->_size_instruction,_param->_nb_instruction); + + DELETE0_SIGNAL( in_EVENT_RESET_VAL,1); + DELETE0_SIGNAL(out_EVENT_RESET_ACK,1); } @@ -62,5 +60,8 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - delete internal_DECOD_VAL; + DELETE1(internal_DECOD_VAL,_param->_nb_instruction); + + for (uint32_t i=0;i<_param->_size_queue; i++) + delete _queue[i]; delete [] _queue; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp (revision 112) @@ -50,20 +50,20 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC_SC_SIGNAL(out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t); - ALLOC_SC_SIGNAL( in_ICACHE_REQ_ADDRESS_VAL," in_ICACHE_REQ_ADDRESS_VAL",Tcontrol_t); - ALLOC_SC_SIGNAL(out_ICACHE_REQ_QUEUE_VAL ,"out_ICACHE_REQ_QUEUE_VAL ",Tcontrol_t); - ALLOC_SC_SIGNAL( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t); - ALLOC_SC_SIGNAL(out_ICACHE_REQ_ADDRESS_ACK,"out_ICACHE_REQ_ADDRESS_ACK",Tcontrol_t); - ALLOC_SC_SIGNAL( in_ICACHE_REQ_QUEUE_ACK ," in_ICACHE_REQ_QUEUE_ACK ",Tcontrol_t); - ALLOC_SC_SIGNAL(out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t); - ALLOC_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Taddress_t); - ALLOC_SC_SIGNAL( in_ICACHE_REQ_ADDRESS_ADDRESS," in_ICACHE_REQ_ADDRESS_ADDRESS",Taddress_t); - ALLOC_SC_SIGNAL(out_ICACHE_REQ_QUEUE_ADDRESS ,"out_ICACHE_REQ_QUEUE_ADDRESS ",Taddress_t); - ALLOC_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t); - ALLOC_SC_SIGNAL(out_EVENT_ADDRESS_VAL ,"out_EVENT_ADDRESS_VAL ",Tcontrol_t); - ALLOC_SC_SIGNAL(out_EVENT_QUEUE_VAL ,"out_EVENT_QUEUE_VAL ",Tcontrol_t); - ALLOC_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t); - ALLOC_SC_SIGNAL( in_EVENT_ADDRESS_ACK ," in_EVENT_ADDRESS_ACK ",Tcontrol_t); - ALLOC_SC_SIGNAL( in_EVENT_QUEUE_ACK ," in_EVENT_QUEUE_ACK ",Tcontrol_t); + ALLOC0_SC_SIGNAL(out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t); + ALLOC0_SC_SIGNAL( in_ICACHE_REQ_ADDRESS_VAL," in_ICACHE_REQ_ADDRESS_VAL",Tcontrol_t); + ALLOC0_SC_SIGNAL(out_ICACHE_REQ_QUEUE_VAL ,"out_ICACHE_REQ_QUEUE_VAL ",Tcontrol_t); + ALLOC0_SC_SIGNAL( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t); + ALLOC0_SC_SIGNAL(out_ICACHE_REQ_ADDRESS_ACK,"out_ICACHE_REQ_ADDRESS_ACK",Tcontrol_t); + ALLOC0_SC_SIGNAL( in_ICACHE_REQ_QUEUE_ACK ," in_ICACHE_REQ_QUEUE_ACK ",Tcontrol_t); + ALLOC0_SC_SIGNAL(out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t); + ALLOC0_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Taddress_t); + ALLOC0_SC_SIGNAL( in_ICACHE_REQ_ADDRESS_ADDRESS," in_ICACHE_REQ_ADDRESS_ADDRESS",Taddress_t); + ALLOC0_SC_SIGNAL(out_ICACHE_REQ_QUEUE_ADDRESS ,"out_ICACHE_REQ_QUEUE_ADDRESS ",Taddress_t); + ALLOC0_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t); + ALLOC0_SC_SIGNAL(out_EVENT_ADDRESS_VAL ,"out_EVENT_ADDRESS_VAL ",Tcontrol_t); + ALLOC0_SC_SIGNAL(out_EVENT_QUEUE_VAL ,"out_EVENT_QUEUE_VAL ",Tcontrol_t); + ALLOC0_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t); + ALLOC0_SC_SIGNAL( in_EVENT_ADDRESS_ACK ," in_EVENT_ADDRESS_ACK ",Tcontrol_t); + ALLOC0_SC_SIGNAL( in_EVENT_QUEUE_ACK ," in_EVENT_QUEUE_ACK ",Tcontrol_t); /******************************************************** @@ -76,20 +76,20 @@ (*(_Ifetch_unit_Glue->in_NRESET)) (*(in_NRESET)); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_VAL ); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ADDRESS_VAL); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_QUEUE_VAL ); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ACK ); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_ADDRESS_ACK); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_QUEUE_ACK ); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_ADDRESS ); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ADDRESS_ADDRESS); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_QUEUE_ADDRESS ); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_TYPE ); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_VAL ); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_EVENT_ADDRESS_VAL ); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_EVENT_QUEUE_VAL ); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_EVENT_ACK ); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_ADDRESS_ACK ); - INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_QUEUE_ACK ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_VAL ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ADDRESS_VAL); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_QUEUE_VAL ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ACK ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_ADDRESS_ACK); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_QUEUE_ACK ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ADDRESS_ADDRESS); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_QUEUE_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_TYPE ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_VAL ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_EVENT_ADDRESS_VAL ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_EVENT_QUEUE_VAL ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue,out_EVENT_ACK ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_ADDRESS_ACK ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_QUEUE_ACK ); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp (revision 112) @@ -48,5 +48,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -58,28 +58,32 @@ // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("icache_req",OUT, WEST, "Instruction Cache request."); + ALLOC0_INTERFACE_BEGIN("icache_req",OUT, WEST, "Instruction Cache request."); - ALLOC_SIGNAL_OUT(out_ICACHE_REQ_VAL ,"val" ,Tcontrol_t,1); - ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_VAL ,"address_val" ,Tcontrol_t,1); - ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_VAL ,"queue_val" ,Tcontrol_t,1); - ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ACK ,"ack" ,Tcontrol_t,1); - ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS_ACK ,"address_ack" ,Tcontrol_t,1); - ALLOC_SIGNAL_IN ( in_ICACHE_REQ_QUEUE_ACK ,"queue_ack" ,Tcontrol_t,1); - ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t,_param->_size_icache_type); - ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); - ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_ADDRESS,"address_address",Taddress_t,_param->_size_instruction_address); - ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_ADDRESS ,"queue_address" ,Taddress_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_VAL ,"val" ,Tcontrol_t,1); + ALLOC0_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_VAL ,"address_val" ,Tcontrol_t,1); + ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_VAL ,"queue_val" ,Tcontrol_t,1); + ALLOC0_SIGNAL_IN ( in_ICACHE_REQ_ACK ,"ack" ,Tcontrol_t,1); + ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS_ACK ,"address_ack" ,Tcontrol_t,1); + ALLOC0_SIGNAL_IN ( in_ICACHE_REQ_QUEUE_ACK ,"queue_ack" ,Tcontrol_t,1); + ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t,_param->_size_icache_type); + ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_ADDRESS,"address_address",Taddress_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_ADDRESS ,"queue_address" ,Taddress_t,_param->_size_instruction_address); + + ALLOC0_INTERFACE_END(); } // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("event",IN, EAST, "Event interface."); + ALLOC0_INTERFACE_BEGIN("event",IN, EAST, _("Event interface.")); - ALLOC_SIGNAL_IN ( in_EVENT_VAL ,"val" ,Tcontrol_t,1); - ALLOC_SIGNAL_OUT(out_EVENT_ADDRESS_VAL,"address_val",Tcontrol_t,1); - ALLOC_SIGNAL_OUT(out_EVENT_QUEUE_VAL ,"queue_val" ,Tcontrol_t,1); - ALLOC_SIGNAL_OUT(out_EVENT_ACK ,"ack" ,Tcontrol_t,1); - ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_ACK,"address_ack",Tcontrol_t,1); - ALLOC_SIGNAL_IN ( in_EVENT_QUEUE_ACK ,"queue_ack" ,Tcontrol_t,1); + ALLOC0_SIGNAL_IN ( in_EVENT_VAL ,"val" ,Tcontrol_t,1); + ALLOC0_SIGNAL_OUT(out_EVENT_ADDRESS_VAL,"address_val",Tcontrol_t,1); + ALLOC0_SIGNAL_OUT(out_EVENT_QUEUE_VAL ,"queue_val" ,Tcontrol_t,1); + ALLOC0_SIGNAL_OUT(out_EVENT_ACK ,"ack" ,Tcontrol_t,1); + ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_ACK,"address_ack",Tcontrol_t,1); + ALLOC0_SIGNAL_IN ( in_EVENT_QUEUE_ACK ,"queue_ack" ,Tcontrol_t,1); + + ALLOC0_INTERFACE_END(); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Ifetch_unit_Glue.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -28,23 +29,22 @@ delete in_NRESET; - delete out_ICACHE_REQ_VAL ; - delete in_ICACHE_REQ_ADDRESS_VAL ; - delete out_ICACHE_REQ_QUEUE_VAL ; - delete in_ICACHE_REQ_ACK ; - delete out_ICACHE_REQ_ADDRESS_ACK ; - delete in_ICACHE_REQ_QUEUE_ACK ; - delete out_ICACHE_REQ_TYPE ; - delete out_ICACHE_REQ_ADDRESS ; - delete in_ICACHE_REQ_ADDRESS_ADDRESS ; - delete out_ICACHE_REQ_QUEUE_ADDRESS ; - - delete in_EVENT_VAL ; - delete out_EVENT_ADDRESS_VAL ; - delete out_EVENT_QUEUE_VAL ; - delete out_EVENT_ACK ; - delete in_EVENT_ADDRESS_ACK ; - delete in_EVENT_QUEUE_ACK ; + DELETE0_SIGNAL(out_ICACHE_REQ_VAL ,1); + DELETE0_SIGNAL( in_ICACHE_REQ_ADDRESS_VAL ,1); + DELETE0_SIGNAL(out_ICACHE_REQ_QUEUE_VAL ,1); + DELETE0_SIGNAL( in_ICACHE_REQ_ACK ,1); + DELETE0_SIGNAL(out_ICACHE_REQ_ADDRESS_ACK ,1); + DELETE0_SIGNAL( in_ICACHE_REQ_QUEUE_ACK ,1); + DELETE0_SIGNAL(out_ICACHE_REQ_TYPE ,_param->_size_icache_type); + DELETE0_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param->_size_instruction_address); + DELETE0_SIGNAL( in_ICACHE_REQ_ADDRESS_ADDRESS,_param->_size_instruction_address); + DELETE0_SIGNAL(out_ICACHE_REQ_QUEUE_ADDRESS ,_param->_size_instruction_address); + + DELETE0_SIGNAL( in_EVENT_VAL ,1); + DELETE0_SIGNAL(out_EVENT_ADDRESS_VAL,1); + DELETE0_SIGNAL(out_EVENT_QUEUE_VAL ,1); + DELETE0_SIGNAL(out_EVENT_ACK ,1); + DELETE0_SIGNAL( in_EVENT_ADDRESS_ACK,1); + DELETE0_SIGNAL( in_EVENT_QUEUE_ACK ,1); } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config.cfg (revision 112) @@ -1,4 +1,4 @@ Ifetch_unit -1 8 *2 # _size_queue +8 16 *2 # _size_queue 1 8 *2 # _nb_instruction 1 1 *2 # _size_branch_update_prediction Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp (revision 112) @@ -66,42 +66,42 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC_SC_SIGNAL (out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t ); -//ALLOC_SC_SIGNAL (out_ICACHE_REQ_THREAD_ID ,"out_ICACHE_REQ_THREAD_ID ",Tcontext_t ); - ALLOC_SC_SIGNAL (out_ICACHE_REQ_PACKET_ID ,"out_ICACHE_REQ_PACKET_ID ",Tpacket_t ); - ALLOC_SC_SIGNAL (out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Ticache_instruction_t); - ALLOC_SC_SIGNAL (out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t ); - ALLOC_SC_SIGNAL ( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ); -//ALLOC_SC_SIGNAL ( in_ICACHE_RSP_THREAD_ID ," in_ICACHE_RSP_THREAD_ID ",Tcontext_t ); - ALLOC_SC_SIGNAL ( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ); + ALLOC0_SC_SIGNAL(out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t ); +//ALLOC0_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,"out_ICACHE_REQ_THREAD_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,"out_ICACHE_REQ_PACKET_ID ",Tpacket_t ); + ALLOC0_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Ticache_instruction_t); + ALLOC0_SC_SIGNAL(out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t ); + ALLOC0_SC_SIGNAL( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ); +//ALLOC0_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ," in_ICACHE_RSP_THREAD_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ); ALLOC1_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_instruction); - ALLOC_SC_SIGNAL ( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ); - ALLOC_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t ); - ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t ); - ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t ); - ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ); + ALLOC0_SC_SIGNAL(out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t ); + ALLOC0_SC_SIGNAL(out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t ); + ALLOC0_SC_SIGNAL(out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t ); + ALLOC0_SC_SIGNAL( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ); ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); - ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); - ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); - ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); + ALLOC0_SC_SIGNAL( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); + ALLOC0_SC_SIGNAL( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); + ALLOC0_SC_SIGNAL( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_instruction); ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_instruction); ALLOC1_SC_SIGNAL(out_DECOD_INSTRUCTION ,"out_DECOD_INSTRUCTION ",Tinstruction_t ,_param->_nb_instruction); -//ALLOC_SC_SIGNAL (out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ); - ALLOC_SC_SIGNAL (out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_address_t ); - ALLOC_SC_SIGNAL (out_DECOD_INST_IFETCH_PTR ,"out_DECOD_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); - ALLOC_SC_SIGNAL (out_DECOD_BRANCH_STATE ,"out_DECOD_BRANCH_STATE ",Tbranch_state_t ); - ALLOC_SC_SIGNAL (out_DECOD_BRANCH_UPDATE_PREDICTION_ID ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ); - ALLOC_SC_SIGNAL (out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ); - ALLOC_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t ); - ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Tgeneral_address_t ); - ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL ," in_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t ); +//ALLOC0_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_address_t ); + ALLOC0_SC_SIGNAL(out_DECOD_INST_IFETCH_PTR ,"out_DECOD_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); + ALLOC0_SC_SIGNAL(out_DECOD_BRANCH_STATE ,"out_DECOD_BRANCH_STATE ",Tbranch_state_t ); + ALLOC0_SC_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ); + ALLOC0_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ); + ALLOC0_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t ); + ALLOC0_SC_SIGNAL( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Tgeneral_address_t ); + ALLOC0_SC_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL ," in_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t ); /******************************************************** @@ -114,48 +114,48 @@ (*(_Ifetch_unit->in_NRESET)) (*(in_NRESET)); - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_VAL ); - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_REQ_ACK ); -//INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_THREAD_ID ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_ICACHE_REQ_VAL ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_ICACHE_REQ_ACK ); +//INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_ICACHE_REQ_THREAD_ID ); if (_param->_have_port_ifetch_queue_ptr) - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_PACKET_ID ); - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_ADDRESS ); - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_TYPE ); - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_VAL ); - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_RSP_ACK ); -//INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_THREAD_ID ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_ICACHE_REQ_PACKET_ID ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_ICACHE_REQ_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_ICACHE_REQ_TYPE ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_VAL ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_ICACHE_RSP_ACK ); +//INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_THREAD_ID ); if (_param->_have_port_ifetch_queue_ptr) - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_PACKET_ID ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_PACKET_ID ); INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_instruction); - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_ERROR ); - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_VAL ); - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_ACK ); - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_PREVIOUS ); - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_CURRENT ); - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_CURRENT_IS_DS_TAKE ); - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_PC_NEXT ); - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_PC_NEXT_IS_DS_TAKE ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_ERROR ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_PREDICT_VAL ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_PREDICT_ACK ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_PREDICT_PC_PREVIOUS ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_PREDICT_PC_CURRENT ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_PREDICT_PC_CURRENT_IS_DS_TAKE ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_PREDICT_PC_NEXT ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_PREDICT_PC_NEXT_IS_DS_TAKE ); INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction); if (_param->_have_port_inst_ifetch_ptr) - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_INST_IFETCH_PTR ); - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_STATE ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_PREDICT_INST_IFETCH_PTR ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_PREDICT_BRANCH_STATE ); if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); INSTANCE1_SC_SIGNAL(_Ifetch_unit,out_DECOD_VAL ,_param->_nb_instruction); INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_DECOD_ACK ,_param->_nb_instruction); INSTANCE1_SC_SIGNAL(_Ifetch_unit,out_DECOD_INSTRUCTION ,_param->_nb_instruction); -//INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_CONTEXT_ID ); - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_ADDRESS ); +//INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_DECOD_CONTEXT_ID ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_DECOD_ADDRESS ); if (_param->_have_port_inst_ifetch_ptr) - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_INST_IFETCH_PTR ); - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_STATE ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_DECOD_INST_IFETCH_PTR ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_DECOD_BRANCH_STATE ); if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_UPDATE_PREDICTION_ID ); - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_EXCEPTION ); - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_VAL ); - INSTANCE_SC_SIGNAL (_Ifetch_unit,out_EVENT_ACK ); - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS ); - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS_NEXT ); - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS_NEXT_VAL ); - INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_IS_DS_TAKE ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_DECOD_BRANCH_UPDATE_PREDICTION_ID ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_DECOD_EXCEPTION ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_EVENT_VAL ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit,out_EVENT_ACK ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_EVENT_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_EVENT_ADDRESS_NEXT ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_EVENT_ADDRESS_NEXT_VAL ); + INSTANCE0_SC_SIGNAL(_Ifetch_unit, in_EVENT_IS_DS_TAKE ); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp (revision 112) @@ -47,5 +47,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -57,80 +57,96 @@ // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("icache_req",OUT, WEST, _("Instruction cache request.")); - - ALLOC_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL); - ALLOC_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK); - //ALLOC_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t ,_param->_size_context_id ); - ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr ); - ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_instruction_address ); - ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type); + ALLOC0_INTERFACE_BEGIN("icache_req",OUT, WEST, _("Instruction cache request.")); + + ALLOC0_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL); + ALLOC0_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK); + //ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr ); + ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_instruction_address ); + ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type); + + ALLOC0_INTERFACE_END(); } // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons.")); - - ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); - ALLOC_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK); - //ALLOC_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ifetch_queue_ptr ); - ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error); - } - { - ALLOC1_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_instruction); + ALLOC0_INTERFACE_BEGIN("icache_rsp",IN , WEST, _("Instruction cache respons.")); + + ALLOC0_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); + ALLOC0_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK); + //ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ifetch_queue_ptr ); + ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error); + + ALLOC0_INTERFACE_END(); + } + { + ALLOC1_INTERFACE_BEGIN("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_instruction); ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction ); + + ALLOC1_INTERFACE_END(_param->_nb_instruction); } // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("predict",OUT, NORTH, _("Predict the next pc.")); - - ALLOC_VALACK_OUT (out_PREDICT_VAL ,VAL); - ALLOC_VALACK_IN ( in_PREDICT_ACK ,ACK); - ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address); - ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address); - ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address); - ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); - ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); - ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); - } - { - ALLOC1_INTERFACE("predict",IN , NORTH, _("Predict the next pc."),_param->_nb_instruction); + ALLOC0_INTERFACE_BEGIN("predict",OUT, NORTH, _("Predict the next pc.")); + + ALLOC0_VALACK_OUT (out_PREDICT_VAL ,VAL); + ALLOC0_VALACK_IN ( in_PREDICT_ACK ,ACK); + ALLOC0_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); + ALLOC0_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); + ALLOC0_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); + + ALLOC0_INTERFACE_END(); + } + { + ALLOC1_INTERFACE_BEGIN("predict",IN , NORTH, _("Predict the next pc."),_param->_nb_instruction); ALLOC1_SIGNAL_IN ( in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_instruction); } // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit.")); - - //ALLOC_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); - ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); - ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); - ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); - ALLOC_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); - } - { - ALLOC1_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction); + ALLOC0_INTERFACE_BEGIN("decod",OUT , EAST, _("Send bundle to the decod unit.")); + + //ALLOC0_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC0_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); + ALLOC0_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); + ALLOC0_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); + ALLOC0_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); + + ALLOC0_INTERFACE_END(); + } + { + ALLOC1_INTERFACE_BEGIN("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction); ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL); ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK); ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION ,"instruction" ,Tinstruction_t ,_param->_size_instruction); + + ALLOC1_INTERFACE_END(_param->_nb_instruction); } // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("event",IN , NORTH, _("Event interface.")); - - ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL); - ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK); - ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); - ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address); - ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t,1); - ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1); + ALLOC0_INTERFACE_BEGIN("event",IN , NORTH, _("Event interface.")); + + ALLOC0_VALACK_IN ( in_EVENT_VAL ,VAL); + ALLOC0_VALACK_OUT(out_EVENT_ACK ,ACK); + ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t,1); + ALLOC0_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1); + + ALLOC0_INTERFACE_END(); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -27,53 +28,48 @@ delete in_NRESET; - delete out_ICACHE_REQ_VAL ; - delete in_ICACHE_REQ_ACK ; - //delete out_ICACHE_REQ_THREAD_ID ; - if (_param->_have_port_ifetch_queue_ptr) - delete out_ICACHE_REQ_PACKET_ID ; - delete out_ICACHE_REQ_ADDRESS ; - delete out_ICACHE_REQ_TYPE ; + DELETE0_SIGNAL(out_ICACHE_REQ_VAL ,1); + DELETE0_SIGNAL( in_ICACHE_REQ_ACK ,1); +// DELETE0_SIGNAL(out_ICACHE_REQ_THREAD_ID,_param->_size_context_id ); + DELETE0_SIGNAL(out_ICACHE_REQ_PACKET_ID,_param->_size_ifetch_queue_ptr ); + DELETE0_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param->_size_instruction_address ); + DELETE0_SIGNAL(out_ICACHE_REQ_TYPE ,_param->_size_icache_type); - delete in_ICACHE_RSP_VAL ; - delete out_ICACHE_RSP_ACK ; - //delete in_ICACHE_RSP_THREAD_ID ; - if (_param->_have_port_ifetch_queue_ptr) - delete in_ICACHE_RSP_PACKET_ID ; - delete [] in_ICACHE_RSP_INSTRUCTION ; - delete in_ICACHE_RSP_ERROR ; + DELETE0_SIGNAL( in_ICACHE_RSP_VAL ,1); + DELETE0_SIGNAL(out_ICACHE_RSP_ACK ,1); + // DELETE0_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_param->_size_context_id ); + DELETE0_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param->_size_ifetch_queue_ptr ); + DELETE0_SIGNAL( in_ICACHE_RSP_ERROR ,_param->_size_icache_error); + DELETE1_SIGNAL( in_ICACHE_RSP_INSTRUCTION,_param->_size_instruction,_param->_nb_instruction); - delete out_PREDICT_VAL ; - delete in_PREDICT_ACK ; - delete out_PREDICT_PC_PREVIOUS ; - delete out_PREDICT_PC_CURRENT ; - delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ; - delete in_PREDICT_PC_NEXT ; - delete in_PREDICT_PC_NEXT_IS_DS_TAKE ; - delete [] in_PREDICT_INSTRUCTION_ENABLE ; - if (_param->_have_port_inst_ifetch_ptr) - delete in_PREDICT_INST_IFETCH_PTR ; - delete in_PREDICT_BRANCH_STATE ; - if (_param->_have_port_depth) - delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ; + DELETE0_SIGNAL(out_PREDICT_VAL ,1); + DELETE0_SIGNAL( in_PREDICT_ACK ,1); + DELETE0_SIGNAL(out_PREDICT_PC_PREVIOUS ,_param->_size_instruction_address); + DELETE0_SIGNAL(out_PREDICT_PC_CURRENT ,_param->_size_instruction_address); + DELETE0_SIGNAL(out_PREDICT_PC_CURRENT_IS_DS_TAKE ,1); + DELETE0_SIGNAL( in_PREDICT_PC_NEXT ,_param->_size_instruction_address); + DELETE0_SIGNAL( in_PREDICT_PC_NEXT_IS_DS_TAKE ,1); + DELETE0_SIGNAL( in_PREDICT_INST_IFETCH_PTR ,_param->_size_inst_ifetch_ptr); + DELETE0_SIGNAL( in_PREDICT_BRANCH_STATE ,_param->_size_branch_state); + DELETE0_SIGNAL( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth); + DELETE1_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ,1,_param->_nb_instruction); - delete [] out_DECOD_VAL ; - delete [] in_DECOD_ACK ; - delete [] out_DECOD_INSTRUCTION ; - //delete out_DECOD_CONTEXT_ID ; - delete out_DECOD_ADDRESS ; - if (_param->_have_port_inst_ifetch_ptr) - delete out_DECOD_INST_IFETCH_PTR ; - delete out_DECOD_BRANCH_STATE ; - if (_param->_have_port_depth) - delete out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; - delete out_DECOD_EXCEPTION ; + // DELETE0_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_size_context_id); + DELETE0_SIGNAL(out_DECOD_ADDRESS ,_param->_size_instruction_address); + DELETE0_SIGNAL(out_DECOD_INST_IFETCH_PTR ,_param->_size_inst_ifetch_ptr); + DELETE0_SIGNAL(out_DECOD_BRANCH_STATE ,_param->_size_branch_state); + DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth); + DELETE0_SIGNAL(out_DECOD_EXCEPTION ,_param->_size_exception_ifetch); + DELETE1_SIGNAL(out_DECOD_VAL ,1,_param->_nb_instruction); + DELETE1_SIGNAL( in_DECOD_ACK ,1,_param->_nb_instruction); + DELETE1_SIGNAL(out_DECOD_INSTRUCTION ,_param->_size_instruction,_param->_nb_instruction); - delete in_EVENT_VAL ; - delete out_EVENT_ACK ; - delete in_EVENT_ADDRESS ; - delete in_EVENT_ADDRESS_NEXT ; - delete in_EVENT_ADDRESS_NEXT_VAL ; - delete in_EVENT_IS_DS_TAKE ; + DELETE0_SIGNAL( in_EVENT_VAL ,1); + DELETE0_SIGNAL(out_EVENT_ACK ,1); + DELETE0_SIGNAL( in_EVENT_ADDRESS ,_param->_size_instruction_address); + DELETE0_SIGNAL( in_EVENT_ADDRESS_NEXT ,_param->_size_instruction_address); + DELETE0_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL ,1); + DELETE0_SIGNAL( in_EVENT_IS_DS_TAKE ,1); } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete _component_address_management; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_allocation.cpp (revision 112) @@ -49,5 +49,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -60,5 +60,5 @@ { { - ALLOC1_INTERFACE("predict", IN, WEST, "predict",_param->_nb_inst_predict); + ALLOC1_INTERFACE_BEGIN("predict", IN, WEST, _("predict"),_param->_nb_inst_predict); ALLOC1_SIGNAL_IN ( in_PREDICT_VAL , "val" ,Tcontrol_t , 1); @@ -84,7 +84,9 @@ ALLOC1_SIGNAL_IN ( in_PREDICT_VICTIM_VICTIM , "victim_victim" ,Tptr_t , _param->_size_victim); } + + ALLOC1_INTERFACE_END(_param->_nb_inst_predict); } { - ALLOC2_INTERFACE("predict", IN, WEST, "predict",_param->_nb_inst_predict, _param->_associativity); + ALLOC2_INTERFACE_BEGIN("predict", IN, WEST, _("predict"),_param->_nb_inst_predict, _param->_associativity); ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_HIT ,"register_hit" ,Tcontrol_t ,1); @@ -94,4 +96,6 @@ ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_LAST_TAKE ,"register_last_take" ,Tcontrol_t ,1); ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_IS_ACCURATE ,"register_is_accurate" ,Tcontrol_t ,1); + + ALLOC2_INTERFACE_END(_param->_nb_inst_predict, _param->_associativity); } } @@ -99,5 +103,5 @@ // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("decod", IN, WEST, "decod",_param->_nb_inst_decod); + ALLOC1_INTERFACE_BEGIN("decod", IN, WEST, _("decod"),_param->_nb_inst_decod); ALLOC1_SIGNAL_IN ( in_DECOD_VAL ,"val" ,Tcontrol_t ,1); @@ -115,9 +119,11 @@ ALLOC1_SIGNAL_OUT(out_DECOD_VICTIM_ADDRESS,"victim_address",Tgeneral_data_t,_param->_size_victim_address); } + + ALLOC1_INTERFACE_END(_param->_nb_inst_decod); } // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("update", IN, WEST, "update",_param->_nb_inst_update); + ALLOC1_INTERFACE_BEGIN("update", IN, WEST, _("update"),_param->_nb_inst_update); ALLOC1_SIGNAL_IN ( in_UPDATE_VAL ,"val" ,Tcontrol_t ,1); @@ -135,4 +141,6 @@ ALLOC1_SIGNAL_OUT(out_UPDATE_VICTIM_ADDRESS,"victim_address",Tgeneral_data_t,_param->_size_victim_address); } + + ALLOC1_INTERFACE_END(_param->_nb_inst_update); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/include/Branch_Target_Buffer_Glue.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -29,58 +30,61 @@ delete in_NRESET; - delete [] in_PREDICT_VAL ; - delete [] out_PREDICT_ACK ; - delete [] out_PREDICT_HIT ; - delete [] out_PREDICT_ADDRESS_SRC ; - delete [] out_PREDICT_ADDRESS_DEST ; - delete [] out_PREDICT_CONDITION ; - delete [] out_PREDICT_LAST_TAKE ; - delete [] out_PREDICT_IS_ACCURATE ; - delete [] out_PREDICT_REGISTER_VAL ; - delete [] in_PREDICT_REGISTER_ACK ; - delete [] in_PREDICT_REGISTER_HIT ; - delete [] in_PREDICT_REGISTER_ADDRESS_SRC ; - delete [] in_PREDICT_REGISTER_ADDRESS_DEST ; - delete [] in_PREDICT_REGISTER_CONDITION ; - delete [] in_PREDICT_REGISTER_LAST_TAKE ; - delete [] in_PREDICT_REGISTER_IS_ACCURATE ; + DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_inst_predict, 1); + DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_inst_predict, 1); + DELETE1_SIGNAL(out_PREDICT_HIT ,_param->_nb_inst_predict, 1); + DELETE1_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_predict, _param->_size_instruction_address); + DELETE1_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_predict, _param->_size_instruction_address); + DELETE1_SIGNAL(out_PREDICT_CONDITION ,_param->_nb_inst_predict, _param->_size_branch_condition); + DELETE1_SIGNAL(out_PREDICT_LAST_TAKE ,_param->_nb_inst_predict, 1); + DELETE1_SIGNAL(out_PREDICT_IS_ACCURATE ,_param->_nb_inst_predict, 1); + DELETE1_SIGNAL(out_PREDICT_REGISTER_VAL ,_param->_nb_inst_predict, 1); + DELETE1_SIGNAL( in_PREDICT_REGISTER_ACK ,_param->_nb_inst_predict, 1); if (_param->_have_port_victim) { - delete [] in_PREDICT_SORT_VAL ; - delete [] in_PREDICT_SORT_INDEX ; - delete [] out_PREDICT_VICTIM_VAL ; - delete [] in_PREDICT_VICTIM_ACK ; - delete [] out_PREDICT_VICTIM_HIT ; - if (not _param->_is_full_associative) - delete [] out_PREDICT_VICTIM_ADDRESS ; - delete [] out_PREDICT_VICTIM_INDEX ; - delete [] in_PREDICT_VICTIM_VICTIM ; + DELETE1_SIGNAL( in_PREDICT_SORT_VAL ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_SORT_INDEX ,_param->_nb_inst_predict,_param->_size_victim); + + DELETE1_SIGNAL(out_PREDICT_VICTIM_VAL ,_param->_nb_inst_predict, 1); + DELETE1_SIGNAL( in_PREDICT_VICTIM_ACK ,_param->_nb_inst_predict, 1); + DELETE1_SIGNAL(out_PREDICT_VICTIM_HIT ,_param->_nb_inst_predict, 1); + DELETE1_SIGNAL(out_PREDICT_VICTIM_ADDRESS,_param->_nb_inst_predict, _param->_size_victim_address); + DELETE1_SIGNAL(out_PREDICT_VICTIM_INDEX ,_param->_nb_inst_predict, _param->_size_victim); + DELETE1_SIGNAL( in_PREDICT_VICTIM_VICTIM ,_param->_nb_inst_predict, _param->_size_victim); } - delete [] in_DECOD_VAL ; - delete [] out_DECOD_ACK ; - if (not _param->_is_full_associative) - delete [] in_DECOD_ADDRESS_SRC ; - delete [] out_DECOD_REGISTER_VAL ; - delete [] in_DECOD_REGISTER_ACK ; - if (_param->_have_port_victim) - { - delete [] out_DECOD_VICTIM_VAL ; - delete [] in_DECOD_VICTIM_ACK ; - if (not _param->_is_full_associative) - delete [] out_DECOD_VICTIM_ADDRESS ; - } - delete [] in_UPDATE_VAL ; - delete [] out_UPDATE_ACK ; - if (not _param->_is_full_associative) - delete [] in_UPDATE_ADDRESS_SRC ; - delete [] out_UPDATE_REGISTER_VAL ; - delete [] in_UPDATE_REGISTER_ACK ; - if (_param->_have_port_victim) - { - delete [] out_UPDATE_VICTIM_VAL ; - delete [] in_UPDATE_VICTIM_ACK ; - if (not _param->_is_full_associative) - delete [] out_UPDATE_VICTIM_ADDRESS ; - } + + DELETE2_SIGNAL( in_PREDICT_REGISTER_HIT ,_param->_nb_inst_predict, _param->_associativity,1); + DELETE2_SIGNAL( in_PREDICT_REGISTER_ADDRESS_SRC ,_param->_nb_inst_predict, _param->_associativity,_param->_size_instruction_address); + DELETE2_SIGNAL( in_PREDICT_REGISTER_ADDRESS_DEST,_param->_nb_inst_predict, _param->_associativity,_param->_size_instruction_address); + DELETE2_SIGNAL( in_PREDICT_REGISTER_CONDITION ,_param->_nb_inst_predict, _param->_associativity,_param->_size_branch_condition); + DELETE2_SIGNAL( in_PREDICT_REGISTER_LAST_TAKE ,_param->_nb_inst_predict, _param->_associativity,1); + DELETE2_SIGNAL( in_PREDICT_REGISTER_IS_ACCURATE ,_param->_nb_inst_predict, _param->_associativity,1); + + DELETE1_SIGNAL( in_DECOD_VAL ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL(out_DECOD_ACK ,_param->_nb_inst_decod,1); + if (not _param->_is_full_associative) + DELETE1_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_instruction_address); + + DELETE1_SIGNAL(out_DECOD_REGISTER_VAL ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_REGISTER_ACK ,_param->_nb_inst_decod,1); + if (_param->_have_port_victim) + { + DELETE1_SIGNAL(out_DECOD_VICTIM_VAL ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_VICTIM_ACK ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL(out_DECOD_VICTIM_ADDRESS,_param->_nb_inst_decod,_param->_size_victim_address); + } + + DELETE1_SIGNAL( in_UPDATE_VAL ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update,1); + if (not _param->_is_full_associative) + DELETE1_SIGNAL( in_UPDATE_ADDRESS_SRC ,_param->_nb_inst_update,_param->_size_instruction_address); + DELETE1_SIGNAL(out_UPDATE_REGISTER_VAL ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_REGISTER_ACK ,_param->_nb_inst_update,1); + if (_param->_have_port_victim) + { + DELETE1_SIGNAL(out_UPDATE_VICTIM_VAL ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_VICTIM_ACK ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_VICTIM_ADDRESS,_param->_nb_inst_update,_param->_size_victim_address); + } + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp (revision 112) @@ -49,5 +49,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -59,5 +59,5 @@ // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("predict", IN, SOUTH, "Compute next pc.", _param->_nb_inst_predict); + ALLOC1_INTERFACE_BEGIN("predict", IN, SOUTH, _("Compute next pc."), _param->_nb_inst_predict); ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); @@ -66,19 +66,22 @@ ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address); - { - ALLOC2_INTERFACE("predict", OUT, SOUTH, "Compute next pc.", _param->_nb_inst_predict, _param->_associativity); - - ALLOC2_SIGNAL_OUT(out_PREDICT_HIT ,"hit" ,Tcontrol_t ,1); - ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); - ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t ,_param->_size_instruction_address); - ALLOC2_SIGNAL_OUT(out_PREDICT_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_state); - ALLOC2_SIGNAL_OUT(out_PREDICT_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); - ALLOC2_SIGNAL_OUT(out_PREDICT_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); - } + ALLOC1_INTERFACE_END(_param->_nb_inst_predict); + } + { + ALLOC2_INTERFACE_BEGIN("predict", OUT, SOUTH, _("Compute next pc."), _param->_nb_inst_predict, _param->_associativity); + + ALLOC2_SIGNAL_OUT(out_PREDICT_HIT ,"hit" ,Tcontrol_t ,1); + ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); + ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t ,_param->_size_instruction_address); + ALLOC2_SIGNAL_OUT(out_PREDICT_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_state); + ALLOC2_SIGNAL_OUT(out_PREDICT_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); + ALLOC2_SIGNAL_OUT(out_PREDICT_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); + + ALLOC2_INTERFACE_END(_param->_nb_inst_predict, _param->_associativity); } // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("decod", IN, SOUTH, "decod instruction", _param->_nb_inst_decod); + ALLOC1_INTERFACE_BEGIN("decod", IN, SOUTH, _("decod instruction"), _param->_nb_inst_decod); ALLOC1_VALACK_IN ( in_DECOD_VAL ,VAL); @@ -97,9 +100,11 @@ ALLOC1_SIGNAL_IN ( in_DECOD_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_decod); } // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("update", IN, SOUTH, "update instruction", _param->_nb_inst_update); + ALLOC1_INTERFACE_BEGIN("update", IN, SOUTH, _("update instruction"), _param->_nb_inst_update); ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); @@ -117,4 +122,6 @@ ALLOC1_SIGNAL_IN ( in_UPDATE_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_UPDATE_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_update); } @@ -122,17 +129,15 @@ { // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - reg_BTB = new btb_entry_t * [_param->_size_bank]; - for (uint32_t i=0; i<_param->_size_bank; i++) - reg_BTB [i] = new btb_entry_t [_param->_associativity]; + ALLOC2(reg_BTB,btb_entry_t,_param->_size_bank,_param->_associativity); - internal_DECOD_ACK = new Tcontrol_t [_param->_nb_inst_decod]; - internal_DECOD_HIT = new Tcontrol_t [_param->_nb_inst_decod]; - internal_DECOD_NUM_BANK = new uint32_t [_param->_nb_inst_decod]; - internal_DECOD_NUM_ENTRY = new uint32_t [_param->_nb_inst_decod]; + ALLOC1(internal_DECOD_ACK ,Tcontrol_t,_param->_nb_inst_decod ); + ALLOC1(internal_DECOD_HIT ,Tcontrol_t,_param->_nb_inst_decod ); + ALLOC1(internal_DECOD_NUM_BANK ,uint32_t ,_param->_nb_inst_decod ); + ALLOC1(internal_DECOD_NUM_ENTRY ,uint32_t ,_param->_nb_inst_decod ); - internal_UPDATE_ACK = new Tcontrol_t [_param->_nb_inst_update]; - internal_UPDATE_HIT = new Tcontrol_t [_param->_nb_inst_update]; - internal_UPDATE_NUM_BANK = new uint32_t [_param->_nb_inst_update]; - internal_UPDATE_NUM_ENTRY = new uint32_t [_param->_nb_inst_update]; + ALLOC1(internal_UPDATE_ACK ,Tcontrol_t,_param->_nb_inst_update); + ALLOC1(internal_UPDATE_HIT ,Tcontrol_t,_param->_nb_inst_update); + ALLOC1(internal_UPDATE_NUM_BANK ,uint32_t ,_param->_nb_inst_update); + ALLOC1(internal_UPDATE_NUM_ENTRY,uint32_t ,_param->_nb_inst_update); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Branch_Target_Buffer_Register.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -29,58 +30,56 @@ delete in_NRESET; - delete [] in_PREDICT_VAL ; - delete [] out_PREDICT_ACK ; - if (_param->_have_port_context_id) - delete [] in_PREDICT_CONTEXT_ID ; - delete [] in_PREDICT_ADDRESS ; - delete [] out_PREDICT_HIT ; - delete [] out_PREDICT_ADDRESS_SRC ; - delete [] out_PREDICT_ADDRESS_DEST ; - delete [] out_PREDICT_CONDITION ; - delete [] out_PREDICT_LAST_TAKE ; - delete [] out_PREDICT_IS_ACCURATE ; - delete [] in_DECOD_VAL ; - delete [] out_DECOD_ACK ; - if (_param->_have_port_victim) - { - delete [] out_DECOD_HIT ; - delete [] out_DECOD_HIT_INDEX ; - delete [] in_DECOD_VICTIM ; - } - if (_param->_have_port_context_id) - delete [] in_DECOD_CONTEXT_ID ; - delete [] in_DECOD_ADDRESS_SRC ; - delete [] in_DECOD_ADDRESS_DEST ; - delete [] in_DECOD_CONDITION ; - delete [] in_DECOD_LAST_TAKE ; - delete [] in_DECOD_MISS_PREDICTION ; - delete [] in_DECOD_IS_ACCURATE ; - delete [] in_UPDATE_VAL ; - delete [] out_UPDATE_ACK ; - if (_param->_have_port_victim) - { - delete [] out_UPDATE_HIT ; - delete [] out_UPDATE_HIT_INDEX ; - delete [] in_UPDATE_VICTIM ; - } - if (_param->_have_port_context_id) - delete [] in_UPDATE_CONTEXT_ID ; - delete [] in_UPDATE_ADDRESS_SRC ; - delete [] in_UPDATE_ADDRESS_DEST ; - delete [] in_UPDATE_CONDITION ; - delete [] in_UPDATE_LAST_TAKE ; - delete [] in_UPDATE_MISS_PREDICTION; + DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict,_param->_size_context_id); + DELETE1_SIGNAL( in_PREDICT_ADDRESS ,_param->_nb_inst_predict,_param->_size_instruction_address); + DELETE2_SIGNAL(out_PREDICT_HIT , _param->_nb_inst_predict, _param->_associativity,1); + DELETE2_SIGNAL(out_PREDICT_ADDRESS_SRC , _param->_nb_inst_predict, _param->_associativity,_param->_size_instruction_address); + DELETE2_SIGNAL(out_PREDICT_ADDRESS_DEST, _param->_nb_inst_predict, _param->_associativity,_param->_size_instruction_address); + DELETE2_SIGNAL(out_PREDICT_CONDITION , _param->_nb_inst_predict, _param->_associativity,_param->_size_branch_state); + DELETE2_SIGNAL(out_PREDICT_LAST_TAKE , _param->_nb_inst_predict, _param->_associativity,1); + DELETE2_SIGNAL(out_PREDICT_IS_ACCURATE , _param->_nb_inst_predict, _param->_associativity,1); + + DELETE1_SIGNAL( in_DECOD_VAL , _param->_nb_inst_decod,1); + DELETE1_SIGNAL(out_DECOD_ACK , _param->_nb_inst_decod,1); + if (_param->_have_port_victim) + { + DELETE1_SIGNAL(out_DECOD_HIT , _param->_nb_inst_decod,1); + DELETE1_SIGNAL(out_DECOD_HIT_INDEX , _param->_nb_inst_decod,_param->_size_victim); + DELETE1_SIGNAL( in_DECOD_VICTIM , _param->_nb_inst_decod,_param->_size_victim); + } + DELETE1_SIGNAL( in_DECOD_CONTEXT_ID , _param->_nb_inst_decod,_param->_size_context_id); + DELETE1_SIGNAL( in_DECOD_ADDRESS_SRC , _param->_nb_inst_decod,_param->_size_instruction_address); + DELETE1_SIGNAL( in_DECOD_ADDRESS_DEST , _param->_nb_inst_decod,_param->_size_instruction_address); + DELETE1_SIGNAL( in_DECOD_CONDITION , _param->_nb_inst_decod,_param->_size_branch_state); + DELETE1_SIGNAL( in_DECOD_LAST_TAKE , _param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_MISS_PREDICTION, _param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_IS_ACCURATE , _param->_nb_inst_decod,1); + + DELETE1_SIGNAL( in_UPDATE_VAL , _param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_ACK , _param->_nb_inst_update,1); + if (_param->_have_port_victim) + { + DELETE1_SIGNAL(out_UPDATE_HIT , _param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_HIT_INDEX , _param->_nb_inst_update,_param->_size_victim); + DELETE1_SIGNAL( in_UPDATE_VICTIM , _param->_nb_inst_update,_param->_size_victim); + } + DELETE1_SIGNAL( in_UPDATE_CONTEXT_ID , _param->_nb_inst_update,_param->_size_context_id); + DELETE1_SIGNAL( in_UPDATE_ADDRESS_SRC , _param->_nb_inst_update,_param->_size_instruction_address); + DELETE1_SIGNAL( in_UPDATE_ADDRESS_DEST , _param->_nb_inst_update,_param->_size_instruction_address); + DELETE1_SIGNAL( in_UPDATE_CONDITION , _param->_nb_inst_update,_param->_size_branch_state); + DELETE1_SIGNAL( in_UPDATE_LAST_TAKE , _param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_MISS_PREDICTION, _param->_nb_inst_update,1); + + DELETE2(reg_BTB ,_param->_size_bank,_param->_associativity); - delete [] reg_BTB; - - delete [] internal_DECOD_ACK ; - delete [] internal_DECOD_HIT ; - delete [] internal_DECOD_NUM_BANK ; - delete [] internal_DECOD_NUM_ENTRY ; - - delete [] internal_UPDATE_ACK ; - delete [] internal_UPDATE_HIT ; - delete [] internal_UPDATE_NUM_BANK ; - delete [] internal_UPDATE_NUM_ENTRY; + DELETE1(internal_DECOD_ACK ,_param->_nb_inst_decod ); + DELETE1(internal_DECOD_HIT ,_param->_nb_inst_decod ); + DELETE1(internal_DECOD_NUM_BANK ,_param->_nb_inst_decod ); + DELETE1(internal_DECOD_NUM_ENTRY ,_param->_nb_inst_decod ); + DELETE1(internal_UPDATE_ACK ,_param->_nb_inst_update); + DELETE1(internal_UPDATE_HIT ,_param->_nb_inst_update); + DELETE1(internal_UPDATE_NUM_BANK ,_param->_nb_inst_update); + DELETE1(internal_UPDATE_NUM_ENTRY,_param->_nb_inst_update); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp (revision 112) @@ -49,5 +49,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -59,5 +59,5 @@ // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("predict", IN, SOUTH, "Predict (next pc) interface", _param->_nb_inst_predict); + ALLOC1_INTERFACE_BEGIN("predict", IN, SOUTH, _("Predict (next pc) interface"), _param->_nb_inst_predict); ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); @@ -71,9 +71,11 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_PREDICT_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(param->_nb_inst_predict); } // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("decod", IN, SOUTH, "Decod Interface", _param->_nb_inst_decod); + ALLOC1_INTERFACE_BEGIN("decod", IN, SOUTH, _("Decod Interface"), _param->_nb_inst_decod); ALLOC1_VALACK_IN ( in_DECOD_VAL ,VAL); @@ -86,9 +88,11 @@ ALLOC1_SIGNAL_IN ( in_DECOD_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_decod); } // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("update", IN, SOUTH, "Update interface", _param->_nb_inst_update); + ALLOC1_INTERFACE_BEGIN("update", IN, SOUTH, _("Update interface"), _param->_nb_inst_update); ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); @@ -100,4 +104,6 @@ ALLOC1_SIGNAL_IN ( in_UPDATE_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_UPDATE_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_update); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/include/Branch_Target_Buffer.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -28,36 +29,33 @@ delete in_NRESET; - delete [] in_PREDICT_VAL ; - delete [] out_PREDICT_ACK ; - if (_param->_have_port_context_id) - delete [] in_PREDICT_CONTEXT_ID ; - delete [] in_PREDICT_ADDRESS ; - delete [] out_PREDICT_HIT ; - delete [] out_PREDICT_ADDRESS_SRC ; - delete [] out_PREDICT_ADDRESS_DEST ; - delete [] out_PREDICT_CONDITION ; - delete [] out_PREDICT_LAST_TAKE ; - delete [] out_PREDICT_IS_ACCURATE ; + DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict,_param->_size_context_id); + DELETE1_SIGNAL( in_PREDICT_ADDRESS ,_param->_nb_inst_predict,_param->_size_instruction_address); + DELETE1_SIGNAL(out_PREDICT_HIT ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_predict,_param->_size_instruction_address); + DELETE1_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_predict,_param->_size_instruction_address); + DELETE1_SIGNAL(out_PREDICT_CONDITION ,_param->_nb_inst_predict,_param->_size_branch_condition); + DELETE1_SIGNAL(out_PREDICT_LAST_TAKE ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL(out_PREDICT_IS_ACCURATE ,_param->_nb_inst_predict,1); - delete [] in_DECOD_VAL ; - delete [] out_DECOD_ACK ; - if (_param->_have_port_context_id) - delete [] in_DECOD_CONTEXT_ID ; - delete [] in_DECOD_ADDRESS_SRC ; - delete [] in_DECOD_ADDRESS_DEST ; - delete [] in_DECOD_CONDITION ; - delete [] in_DECOD_LAST_TAKE ; - delete [] in_DECOD_MISS_PREDICTION ; - delete [] in_DECOD_IS_ACCURATE ; + DELETE1_SIGNAL( in_DECOD_VAL ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL(out_DECOD_ACK ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod,_param->_size_context_id); + DELETE1_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_instruction_address); + DELETE1_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_inst_decod,_param->_size_instruction_address); + DELETE1_SIGNAL( in_DECOD_CONDITION ,_param->_nb_inst_decod,_param->_size_branch_condition); + DELETE1_SIGNAL( in_DECOD_LAST_TAKE ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_MISS_PREDICTION ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod,1); - delete [] in_UPDATE_VAL ; - delete [] out_UPDATE_ACK ; - if (_param->_have_port_context_id) - delete [] in_UPDATE_CONTEXT_ID ; - delete [] in_UPDATE_ADDRESS_SRC ; - delete [] in_UPDATE_ADDRESS_DEST ; - delete [] in_UPDATE_CONDITION ; - delete [] in_UPDATE_LAST_TAKE ; - delete [] in_UPDATE_MISS_PREDICTION; + DELETE1_SIGNAL( in_UPDATE_VAL ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_CONTEXT_ID ,_param->_nb_inst_update,_param->_size_context_id); + DELETE1_SIGNAL( in_UPDATE_ADDRESS_SRC ,_param->_nb_inst_update,_param->_size_instruction_address); + DELETE1_SIGNAL( in_UPDATE_ADDRESS_DEST ,_param->_nb_inst_update,_param->_size_instruction_address); + DELETE1_SIGNAL( in_UPDATE_CONDITION ,_param->_nb_inst_update,_param->_size_branch_condition); + DELETE1_SIGNAL( in_UPDATE_LAST_TAKE ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_MISS_PREDICTION,_param->_nb_inst_update,1); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/src/test.cpp (revision 112) @@ -51,26 +51,28 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t,_param->_nb_inst_predict); - ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t,_param->_nb_inst_predict); - ALLOC1_SC_SIGNAL( in_PREDICT_ADDRESS_SRC ," in_PREDICT_ADDRESS_SRC ",Taddress_t,_param->_nb_inst_predict); - ALLOC1_SC_SIGNAL( in_PREDICT_STATIC ," in_PREDICT_STATIC ",Tcontrol_t,_param->_nb_inst_predict); - ALLOC1_SC_SIGNAL( in_PREDICT_LAST_TAKE ," in_PREDICT_LAST_TAKE ",Tcontrol_t,_param->_nb_inst_predict); - ALLOC1_SC_SIGNAL(out_PREDICT_HISTORY ,"out_PREDICT_HISTORY ",Thistory_t,_param->_nb_inst_predict); - ALLOC1_SC_SIGNAL(out_PREDICT_DIRECTION ,"out_PREDICT_DIRECTION ",Tcontrol_t,_param->_nb_inst_predict); - ALLOC1_SC_SIGNAL(out_PREDICT_PREDICTOR_VAL ,"out_PREDICT_PREDICTOR_VAL ",Tcontrol_t,_param->_nb_inst_predict); - ALLOC1_SC_SIGNAL( in_PREDICT_PREDICTOR_ACK ," in_PREDICT_PREDICTOR_ACK ",Tcontrol_t,_param->_nb_inst_predict); - ALLOC1_SC_SIGNAL(out_PREDICT_PREDICTOR_ADDRESS_SRC,"out_PREDICT_PREDICTOR_ADDRESS_SRC",Taddress_t,_param->_nb_inst_predict); - ALLOC1_SC_SIGNAL( in_PREDICT_PREDICTOR_HISTORY ," in_PREDICT_PREDICTOR_HISTORY ",Thistory_t,_param->_nb_inst_predict); - ALLOC1_SC_SIGNAL( in_PREDICT_PREDICTOR_DIRECTION ," in_PREDICT_PREDICTOR_DIRECTION ",Tcontrol_t,_param->_nb_inst_predict); - ALLOC1_SC_SIGNAL( in_UPDATE_VAL ," in_UPDATE_VAL ",Tcontrol_t,_param->_nb_inst_update); - ALLOC1_SC_SIGNAL(out_UPDATE_ACK ,"out_UPDATE_ACK ",Tcontrol_t,_param->_nb_inst_update); - ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS ," in_UPDATE_ADDRESS ",Taddress_t,_param->_nb_inst_update); - ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY ," in_UPDATE_HISTORY ",Thistory_t,_param->_nb_inst_update); - ALLOC1_SC_SIGNAL( in_UPDATE_DIRECTION ," in_UPDATE_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); - ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_VAL ,"out_UPDATE_PREDICTOR_VAL ",Tcontrol_t,_param->_nb_inst_update); - ALLOC1_SC_SIGNAL( in_UPDATE_PREDICTOR_ACK ," in_UPDATE_PREDICTOR_ACK ",Tcontrol_t,_param->_nb_inst_update); - ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_ADDRESS ,"out_UPDATE_PREDICTOR_ADDRESS ",Taddress_t,_param->_nb_inst_update); - ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_HISTORY ,"out_UPDATE_PREDICTOR_HISTORY ",Thistory_t,_param->_nb_inst_update); - ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_DIRECTION ,"out_UPDATE_PREDICTOR_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t,_param->_nb_inst_predict); + ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t,_param->_nb_inst_predict); + ALLOC1_SC_SIGNAL( in_PREDICT_ADDRESS_SRC ," in_PREDICT_ADDRESS_SRC ",Taddress_t,_param->_nb_inst_predict); + ALLOC1_SC_SIGNAL( in_PREDICT_STATIC ," in_PREDICT_STATIC ",Tcontrol_t,_param->_nb_inst_predict); + ALLOC1_SC_SIGNAL( in_PREDICT_LAST_TAKE ," in_PREDICT_LAST_TAKE ",Tcontrol_t,_param->_nb_inst_predict); + ALLOC1_SC_SIGNAL(out_PREDICT_HISTORY ,"out_PREDICT_HISTORY ",Thistory_t,_param->_nb_inst_predict); + ALLOC1_SC_SIGNAL(out_PREDICT_DIRECTION ,"out_PREDICT_DIRECTION ",Tcontrol_t,_param->_nb_inst_predict); + ALLOC1_SC_SIGNAL(out_PREDICT_PREDICTOR_VAL ,"out_PREDICT_PREDICTOR_VAL ",Tcontrol_t,_param->_nb_inst_predict); + ALLOC1_SC_SIGNAL( in_PREDICT_PREDICTOR_ACK ," in_PREDICT_PREDICTOR_ACK ",Tcontrol_t,_param->_nb_inst_predict); + ALLOC1_SC_SIGNAL(out_PREDICT_PREDICTOR_ADDRESS_SRC ,"out_PREDICT_PREDICTOR_ADDRESS_SRC ",Taddress_t,_param->_nb_inst_predict); + ALLOC1_SC_SIGNAL( in_PREDICT_PREDICTOR_HISTORY ," in_PREDICT_PREDICTOR_HISTORY ",Thistory_t,_param->_nb_inst_predict); + ALLOC1_SC_SIGNAL( in_PREDICT_PREDICTOR_DIRECTION ," in_PREDICT_PREDICTOR_DIRECTION ",Tcontrol_t,_param->_nb_inst_predict); + ALLOC1_SC_SIGNAL( in_UPDATE_VAL ," in_UPDATE_VAL ",Tcontrol_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL(out_UPDATE_ACK ,"out_UPDATE_ACK ",Tcontrol_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS ," in_UPDATE_ADDRESS ",Taddress_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY ," in_UPDATE_HISTORY ",Thistory_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL( in_UPDATE_DIRECTION ," in_UPDATE_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL( in_UPDATE_PREDICTION_IFETCH ," in_UPDATE_PREDICTION_IFETCH ",Tcontrol_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_VAL ,"out_UPDATE_PREDICTOR_VAL ",Tcontrol_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL( in_UPDATE_PREDICTOR_ACK ," in_UPDATE_PREDICTOR_ACK ",Tcontrol_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_ADDRESS ,"out_UPDATE_PREDICTOR_ADDRESS ",Taddress_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_HISTORY ,"out_UPDATE_PREDICTOR_HISTORY ",Thistory_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_DIRECTION ,"out_UPDATE_PREDICTOR_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_PREDICTION_IFETCH ,"out_UPDATE_PREDICTOR_PREDICTION_IFETCH ",Tcontrol_t,_param->_nb_inst_update); /******************************************************** @@ -83,36 +85,38 @@ (*(_Direction_Glue->in_NRESET)) (*(in_NRESET)); - INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_VAL ,_param->_nb_inst_predict); - INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_ACK ,_param->_nb_inst_predict); - INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_ADDRESS_SRC ,_param->_nb_inst_predict); - INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_STATIC ,_param->_nb_inst_predict); - INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_LAST_TAKE ,_param->_nb_inst_predict); - if (_param->_have_port_history) - INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_HISTORY ,_param->_nb_inst_predict); - INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_DIRECTION ,_param->_nb_inst_predict); - if (_param->_have_component_meta_predictor) - { - INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_PREDICTOR_VAL ,_param->_nb_inst_predict); - INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_PREDICTOR_ACK ,_param->_nb_inst_predict); - INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_PREDICTOR_ADDRESS_SRC,_param->_nb_inst_predict); - if (_param->_have_port_history) - INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_PREDICTOR_HISTORY ,_param->_nb_inst_predict); - INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_PREDICTOR_DIRECTION ,_param->_nb_inst_predict); - } - - INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_VAL ,_param->_nb_inst_update ); - INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_ACK ,_param->_nb_inst_update ); - INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_ADDRESS ,_param->_nb_inst_update ); - if (_param->_have_port_history) - INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_HISTORY ,_param->_nb_inst_update ); - INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_DIRECTION ,_param->_nb_inst_update ); - if (_param->_have_component_meta_predictor) - { - INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_VAL ,_param->_nb_inst_update ); - INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_PREDICTOR_ACK ,_param->_nb_inst_update ); - INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_ADDRESS ,_param->_nb_inst_update ); - if (_param->_have_port_history) - INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_HISTORY ,_param->_nb_inst_update ); - INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_DIRECTION ,_param->_nb_inst_update ); + INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_VAL ,_param->_nb_inst_predict); + INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_ACK ,_param->_nb_inst_predict); + INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_ADDRESS_SRC ,_param->_nb_inst_predict); + INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_STATIC ,_param->_nb_inst_predict); + INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_LAST_TAKE ,_param->_nb_inst_predict); + if (_param->_have_port_history) + INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_HISTORY ,_param->_nb_inst_predict); + INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_DIRECTION ,_param->_nb_inst_predict); + if (_param->_have_component_meta_predictor) + { + INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_PREDICTOR_VAL ,_param->_nb_inst_predict); + INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_PREDICTOR_ACK ,_param->_nb_inst_predict); + INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_PREDICTOR_ADDRESS_SRC ,_param->_nb_inst_predict); + if (_param->_have_port_history) + INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_PREDICTOR_HISTORY ,_param->_nb_inst_predict); + INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_PREDICTOR_DIRECTION ,_param->_nb_inst_predict); + } + + INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_VAL ,_param->_nb_inst_update ); + INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_ACK ,_param->_nb_inst_update ); + INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_ADDRESS ,_param->_nb_inst_update ); + if (_param->_have_port_history) + INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_HISTORY ,_param->_nb_inst_update ); + INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_DIRECTION ,_param->_nb_inst_update ); + INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_PREDICTION_IFETCH ,_param->_nb_inst_update ); + if (_param->_have_component_meta_predictor) + { + INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_VAL ,_param->_nb_inst_update ); + INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_PREDICTOR_ACK ,_param->_nb_inst_update ); + INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_ADDRESS ,_param->_nb_inst_update ); + if (_param->_have_port_history) + INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_HISTORY ,_param->_nb_inst_update ); + INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_DIRECTION ,_param->_nb_inst_update ); + INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_PREDICTION_IFETCH ,_param->_nb_inst_update ); } @@ -163,4 +167,5 @@ in_UPDATE_HISTORY [i]->write(range(rand(),_param->_size_history)); in_UPDATE_DIRECTION [i]->write(rand()%2); + in_UPDATE_PREDICTION_IFETCH [i]->write(rand()%2); in_UPDATE_PREDICTOR_ACK [i]->write(rand()%2); } @@ -228,9 +233,10 @@ case PREDICTOR_CUSTOM : { - TEST(Tcontrol_t,out_UPDATE_ACK [i]->read(), in_UPDATE_PREDICTOR_ACK [i]->read()); - TEST(Tcontrol_t,out_UPDATE_PREDICTOR_VAL [i]->read(), in_UPDATE_VAL [i]->read()); - TEST(Taddress_t,out_UPDATE_PREDICTOR_ADDRESS [i]->read(), in_UPDATE_ADDRESS [i]->read()); - TEST(Thistory_t,out_UPDATE_PREDICTOR_HISTORY [i]->read(), in_UPDATE_HISTORY [i]->read()); - TEST(Tcontrol_t,out_UPDATE_PREDICTOR_DIRECTION [i]->read(), in_UPDATE_DIRECTION [i]->read()); + TEST(Tcontrol_t,out_UPDATE_ACK [i]->read(), in_UPDATE_PREDICTOR_ACK [i]->read()); + TEST(Tcontrol_t,out_UPDATE_PREDICTOR_VAL [i]->read(), in_UPDATE_VAL [i]->read()); + TEST(Taddress_t,out_UPDATE_PREDICTOR_ADDRESS [i]->read(), in_UPDATE_ADDRESS [i]->read()); + TEST(Thistory_t,out_UPDATE_PREDICTOR_HISTORY [i]->read(), in_UPDATE_HISTORY [i]->read()); + TEST(Tcontrol_t,out_UPDATE_PREDICTOR_DIRECTION [i]->read(), in_UPDATE_DIRECTION [i]->read()); + TEST(Tcontrol_t,out_UPDATE_PREDICTOR_PREDICTION_IFETCH[i]->read(), in_UPDATE_PREDICTION_IFETCH [i]->read()); break; @@ -281,4 +287,5 @@ delete [] in_UPDATE_HISTORY ; delete [] in_UPDATE_DIRECTION ; + delete [] in_UPDATE_PREDICTION_IFETCH ; delete [] out_UPDATE_PREDICTOR_VAL ; delete [] in_UPDATE_PREDICTOR_ACK ; @@ -286,4 +293,5 @@ delete [] out_UPDATE_PREDICTOR_HISTORY ; delete [] out_UPDATE_PREDICTOR_DIRECTION ; + delete [] out_UPDATE_PREDICTOR_PREDICTION_IFETCH; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/include/Direction_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/include/Direction_Glue.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/include/Direction_Glue.h (revision 112) @@ -79,15 +79,17 @@ // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t) ** in_UPDATE_VAL ; - public : SC_OUT(Tcontrol_t) ** out_UPDATE_ACK ; - public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ; - public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ; - public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ; + public : SC_IN (Tcontrol_t) ** in_UPDATE_VAL ; + public : SC_OUT(Tcontrol_t) ** out_UPDATE_ACK ; + public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ; + public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ; + public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ; + public : SC_IN (Tcontrol_t) ** in_UPDATE_PREDICTION_IFETCH ; - public : SC_OUT(Tcontrol_t) ** out_UPDATE_PREDICTOR_VAL ; - public : SC_IN (Tcontrol_t) ** in_UPDATE_PREDICTOR_ACK ; - public : SC_OUT(Taddress_t) ** out_UPDATE_PREDICTOR_ADDRESS ; - public : SC_OUT(Thistory_t) ** out_UPDATE_PREDICTOR_HISTORY ; - public : SC_OUT(Tcontrol_t) ** out_UPDATE_PREDICTOR_DIRECTION; + public : SC_OUT(Tcontrol_t) ** out_UPDATE_PREDICTOR_VAL ; + public : SC_IN (Tcontrol_t) ** in_UPDATE_PREDICTOR_ACK ; + public : SC_OUT(Taddress_t) ** out_UPDATE_PREDICTOR_ADDRESS ; + public : SC_OUT(Thistory_t) ** out_UPDATE_PREDICTOR_HISTORY ; + public : SC_OUT(Tcontrol_t) ** out_UPDATE_PREDICTOR_DIRECTION ; + public : SC_OUT(Tcontrol_t) ** out_UPDATE_PREDICTOR_PREDICTION_IFETCH; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue.cpp (revision 112) @@ -215,9 +215,11 @@ // sensitive << (*(in_CLOCK)).neg(); // don't use internal register for (uint32_t i=0; i<_param->_nb_inst_update; i++) - sensitive << (*(in_UPDATE_VAL [i])) - << (*(in_UPDATE_PREDICTOR_ACK [i])) - << (*(in_UPDATE_ADDRESS [i])) - << (*(in_UPDATE_HISTORY [i])) - << (*(in_UPDATE_DIRECTION [i])); + sensitive << (*(in_UPDATE_VAL [i])) + << (*(in_UPDATE_PREDICTOR_ACK [i])) + << (*(in_UPDATE_ADDRESS [i])) + << (*(in_UPDATE_HISTORY [i])) + << (*(in_UPDATE_DIRECTION [i])) + << (*(in_UPDATE_PREDICTION_IFETCH [i])) + ; # ifdef SYSTEMCASS_SPECIFIC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_allocation.cpp (revision 112) @@ -59,5 +59,5 @@ // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("predict", IN, SOUTH, "predict's interface", _param->_nb_inst_predict); + ALLOC1_INTERFACE_BEGIN("predict", IN, SOUTH, _("predict's interface"), _param->_nb_inst_predict); ALLOC1_SIGNAL_IN ( in_PREDICT_VAL ,"val" ,Tcontrol_t,1); @@ -68,6 +68,7 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_HISTORY ,"history" ,Thistory_t,_param->_size_history); ALLOC1_SIGNAL_OUT(out_PREDICT_DIRECTION ,"direction" ,Tcontrol_t,1); - if (_param->_have_component_meta_predictor) - { + + if (_param->_have_component_meta_predictor) + { ALLOC1_SIGNAL_OUT(out_PREDICT_PREDICTOR_VAL ,"predictor_val" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_PREDICT_PREDICTOR_ACK ,"predictor_ack" ,Tcontrol_t,1); @@ -76,23 +77,30 @@ ALLOC1_SIGNAL_IN ( in_PREDICT_PREDICTOR_DIRECTION ,"predictor_direction" ,Tcontrol_t,1); } + + ALLOC1_INTERFACE_END(_param->_nb_inst_predict); } // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("update", IN, SOUTH, "update's interface", _param->_nb_inst_update); + ALLOC1_INTERFACE_BEGIN("update", IN, SOUTH, _("update's interface"), _param->_nb_inst_update); - ALLOC1_SIGNAL_IN ( in_UPDATE_VAL ,"val" ,Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_UPDATE_ACK ,"ack" ,Tcontrol_t,1); - ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); - ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"history" ,Thistory_t,_param->_size_history); - ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION ,"direction" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_UPDATE_VAL ,"val" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_UPDATE_ACK ,"ack" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"history" ,Thistory_t,_param->_size_history); + ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION ,"direction" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_UPDATE_PREDICTION_IFETCH ,"prediction_ifetch" ,Tcontrol_t,1); + if (_param->_have_component_meta_predictor) { - ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_VAL ,"predictor_val" ,Tcontrol_t,1); - ALLOC1_SIGNAL_IN ( in_UPDATE_PREDICTOR_ACK ,"predictor_ack" ,Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_ADDRESS ,"predictor_address" ,Taddress_t,_param->_size_instruction_address); - ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_HISTORY ,"predictor_history" ,Thistory_t,_param->_size_history); - ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_DIRECTION,"predictor_direction",Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_VAL ,"predictor_val" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_UPDATE_PREDICTOR_ACK ,"predictor_ack" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_ADDRESS ,"predictor_address" ,Taddress_t,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_HISTORY ,"predictor_history" ,Thistory_t,_param->_size_history); + ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_DIRECTION ,"predictor_direction" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_PREDICTION_IFETCH,"predictor_prediction_ifetch",Tcontrol_t,1); } + + ALLOC1_INTERFACE_END(_param->_nb_inst_update); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/include/Direction_Glue.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -29,39 +30,38 @@ delete in_NRESET; - delete [] in_PREDICT_VAL ; - delete [] out_PREDICT_ACK ; - delete [] in_PREDICT_ADDRESS_SRC ; - delete [] in_PREDICT_STATIC ; - delete [] in_PREDICT_LAST_TAKE ; - if (_param->_have_port_history) - delete [] out_PREDICT_HISTORY ; - delete [] out_PREDICT_DIRECTION ; - if (_param->_have_component_meta_predictor) - { - delete [] out_PREDICT_PREDICTOR_VAL ; - delete [] in_PREDICT_PREDICTOR_ACK ; - delete [] out_PREDICT_PREDICTOR_ADDRESS_SRC; - if (_param->_have_port_history) - delete [] in_PREDICT_PREDICTOR_HISTORY ; - delete [] in_PREDICT_PREDICTOR_DIRECTION ; - } - delete [] in_UPDATE_VAL ; - delete [] out_UPDATE_ACK ; - delete [] in_UPDATE_ADDRESS ; - if (_param->_have_port_history) - delete [] in_UPDATE_HISTORY ; - delete [] in_UPDATE_DIRECTION ; - if (_param->_have_component_meta_predictor) - { - delete [] out_UPDATE_PREDICTOR_VAL ; - delete [] in_UPDATE_PREDICTOR_ACK ; - delete [] out_UPDATE_PREDICTOR_ADDRESS ; - if (_param->_have_port_history) - delete [] out_UPDATE_PREDICTOR_HISTORY ; - delete [] out_UPDATE_PREDICTOR_DIRECTION; - } + DELETE1_SIGNAL( in_PREDICT_VAL , _param->_nb_inst_predict,1); + DELETE1_SIGNAL(out_PREDICT_ACK , _param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_ADDRESS_SRC , _param->_nb_inst_predict,_param->_size_instruction_address); + DELETE1_SIGNAL( in_PREDICT_STATIC , _param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_LAST_TAKE , _param->_nb_inst_predict,1); + DELETE1_SIGNAL(out_PREDICT_HISTORY , _param->_nb_inst_predict,_param->_size_history); + DELETE1_SIGNAL(out_PREDICT_DIRECTION , _param->_nb_inst_predict,1); + if (_param->_have_component_meta_predictor) + { + DELETE1_SIGNAL(out_PREDICT_PREDICTOR_VAL , _param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_PREDICTOR_ACK , _param->_nb_inst_predict,1); + DELETE1_SIGNAL(out_PREDICT_PREDICTOR_ADDRESS_SRC, _param->_nb_inst_predict,_param->_size_instruction_address); + DELETE1_SIGNAL( in_PREDICT_PREDICTOR_HISTORY , _param->_nb_inst_predict,_param->_size_history); + DELETE1_SIGNAL( in_PREDICT_PREDICTOR_DIRECTION , _param->_nb_inst_predict,1); + } + + DELETE1_SIGNAL( in_UPDATE_VAL ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update,_param->_size_instruction_address); + DELETE1_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update,_param->_size_history); + DELETE1_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_PREDICTION_IFETCH ,_param->_nb_inst_update,1); + if (_param->_have_component_meta_predictor) + { + DELETE1_SIGNAL(out_UPDATE_PREDICTOR_VAL ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_PREDICTOR_ACK ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_PREDICTOR_ADDRESS ,_param->_nb_inst_update,_param->_size_instruction_address); + DELETE1_SIGNAL(out_UPDATE_PREDICTOR_HISTORY ,_param->_nb_inst_update,_param->_size_history); + DELETE1_SIGNAL(out_UPDATE_PREDICTOR_DIRECTION ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_PREDICTOR_PREDICTION_IFETCH,_param->_nb_inst_update,1); + } } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_genMealy_update.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_genMealy_update.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_genMealy_update.cpp (revision 112) @@ -28,9 +28,10 @@ for (uint32_t i=0; i<_param->_nb_inst_update; i++) { - PORT_WRITE(out_UPDATE_PREDICTOR_VAL [i], PORT_READ(in_UPDATE_VAL [i])); - PORT_WRITE(out_UPDATE_ACK [i], PORT_READ(in_UPDATE_PREDICTOR_ACK [i])); - PORT_WRITE(out_UPDATE_PREDICTOR_ADDRESS [i], PORT_READ(in_UPDATE_ADDRESS [i])); - PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [i], PORT_READ(in_UPDATE_HISTORY [i])); - PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [i], PORT_READ(in_UPDATE_DIRECTION [i])); + PORT_WRITE(out_UPDATE_PREDICTOR_VAL [i], PORT_READ(in_UPDATE_VAL [i])); + PORT_WRITE(out_UPDATE_ACK [i], PORT_READ(in_UPDATE_PREDICTOR_ACK [i])); + PORT_WRITE(out_UPDATE_PREDICTOR_ADDRESS [i], PORT_READ(in_UPDATE_ADDRESS [i])); + PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [i], PORT_READ(in_UPDATE_HISTORY [i])); + PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [i], PORT_READ(in_UPDATE_DIRECTION [i])); + PORT_WRITE(out_UPDATE_PREDICTOR_PREDICTION_IFETCH [i], PORT_READ(in_UPDATE_PREDICTION_IFETCH [i])); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/src/test.cpp (revision 112) @@ -64,8 +64,10 @@ ALLOC1_SC_SIGNAL(out_UPDATE_ACK ,"out_UPDATE_ACK ",Tcontrol_t,_param->_nb_inst_update); ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY ," in_UPDATE_HISTORY ",Thistory_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY_VAL ," in_UPDATE_HISTORY_VAL ",Tcontrol_t,_param->_nb_inst_update); ALLOC1_SC_SIGNAL( in_UPDATE_DIRECTION ," in_UPDATE_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); ALLOC2_SC_SIGNAL(out_UPDATE_PREDICTOR_VAL ,"out_UPDATE_PREDICTOR_VAL ",Tcontrol_t,_param->_nb_predictor,_param->_nb_inst_update); ALLOC2_SC_SIGNAL( in_UPDATE_PREDICTOR_ACK ," in_UPDATE_PREDICTOR_ACK ",Tcontrol_t,_param->_nb_predictor,_param->_nb_inst_update); ALLOC2_SC_SIGNAL(out_UPDATE_PREDICTOR_HISTORY ,"out_UPDATE_PREDICTOR_HISTORY ",Thistory_t,_param->_nb_predictor,_param->_nb_inst_update); + ALLOC2_SC_SIGNAL(out_UPDATE_PREDICTOR_HISTORY_VAL ,"out_UPDATE_PREDICTOR_HISTORY_VAL ",Tcontrol_t,_param->_nb_predictor,_param->_nb_inst_update); ALLOC2_SC_SIGNAL(out_UPDATE_PREDICTOR_DIRECTION ,"out_UPDATE_PREDICTOR_DIRECTION ",Tcontrol_t,_param->_nb_predictor,_param->_nb_inst_update); ALLOC2_SC_SIGNAL(out_UPDATE_PREDICTOR_MISS ,"out_UPDATE_PREDICTOR_MISS ",Tcontrol_t,_param->_nb_predictor,_param->_nb_inst_update); @@ -100,4 +102,5 @@ INSTANCE1_SC_SIGNAL(_Meta_Predictor_Glue,out_UPDATE_ACK ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Meta_Predictor_Glue, in_UPDATE_HISTORY ,_param->_nb_inst_update); + INSTANCE1_SC_SIGNAL(_Meta_Predictor_Glue, in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Meta_Predictor_Glue, in_UPDATE_DIRECTION ,_param->_nb_inst_update); @@ -105,4 +108,5 @@ INSTANCE2_SC_SIGNAL(_Meta_Predictor_Glue, in_UPDATE_PREDICTOR_ACK ,_param->_nb_predictor,_param->_nb_inst_update); INSTANCE2_SC_SIGNAL(_Meta_Predictor_Glue,out_UPDATE_PREDICTOR_HISTORY ,_param->_nb_predictor,_param->_nb_inst_update); + INSTANCE2_SC_SIGNAL(_Meta_Predictor_Glue,out_UPDATE_PREDICTOR_HISTORY_VAL ,_param->_nb_predictor,_param->_nb_inst_update); INSTANCE2_SC_SIGNAL(_Meta_Predictor_Glue,out_UPDATE_PREDICTOR_DIRECTION ,_param->_nb_predictor,_param->_nb_inst_update); for (uint32_t i=0; i<_param->_nb_predictor; ++i) @@ -169,4 +173,5 @@ DELETE1_SC_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update); DELETE1_SC_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update); + DELETE1_SC_SIGNAL( in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update); DELETE1_SC_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h (revision 112) @@ -83,4 +83,5 @@ public : SC_OUT(Tcontrol_t) ** out_UPDATE_ACK ;// [nb_inst_update] public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ;// [nb_inst_update] + public : SC_IN (Tcontrol_t) ** in_UPDATE_HISTORY_VAL ;// [nb_inst_update] public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ;// [nb_inst_update] @@ -88,4 +89,5 @@ public : SC_IN (Tcontrol_t) *** in_UPDATE_PREDICTOR_ACK ;//[nb_predictor][nb_inst_update] public : SC_OUT(Thistory_t) *** out_UPDATE_PREDICTOR_HISTORY ;//[nb_predictor][nb_inst_update] + public : SC_OUT(Tcontrol_t) *** out_UPDATE_PREDICTOR_HISTORY_VAL ;//[nb_predictor][nb_inst_update] public : SC_OUT(Tcontrol_t) *** out_UPDATE_PREDICTOR_DIRECTION ;//[nb_predictor][nb_inst_update] public : SC_OUT(Tcontrol_t) *** out_UPDATE_PREDICTOR_MISS ;//[nb_predictor][nb_inst_update] // if update_on_prediction Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue.cpp (revision 112) @@ -101,6 +101,7 @@ // sensitive << (*(in_CLOCK)).neg(); // don't need internal register for (uint32_t i=0; i<_param->_nb_inst_update; ++i) - sensitive << (*(in_UPDATE_HISTORY [i])) - << (*(in_UPDATE_DIRECTION [i])); + sensitive << (*(in_UPDATE_HISTORY [i])) + << (*(in_UPDATE_HISTORY_VAL [i])) + << (*(in_UPDATE_DIRECTION [i])); # ifdef SYSTEMCASS_SPECIFIC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_allocation.cpp (revision 112) @@ -61,5 +61,5 @@ // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("predict",IN,NORTH,_("Predict next address"),_param->_nb_inst_predict); + ALLOC1_INTERFACE_BEGIN("predict",IN,NORTH,_("Predict next address"),_param->_nb_inst_predict); ALLOC1_SIGNAL_IN ( in_PREDICT_VAL ,"VAL" ,Tcontrol_t,1); @@ -67,8 +67,10 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_HISTORY ,"HISTORY" ,Thistory_t,_param->_size_history); ALLOC1_SIGNAL_OUT(out_PREDICT_DIRECTION ,"DIRECTION" ,Tcontrol_t,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_predict); } { - ALLOC2_INTERFACE("predict_predictor",IN,NORTH,_("Predict next address"),_param->_nb_predictor,_param->_nb_inst_predict); + ALLOC2_INTERFACE_BEGIN("predict_predictor",IN,NORTH,_("Predict next address"),_param->_nb_predictor,_param->_nb_inst_predict); ALLOC2_SIGNAL_OUT(out_PREDICT_PREDICTOR_VAL ,"VAL" ,Tcontrol_t,1); @@ -78,23 +80,31 @@ ALLOC2_SIGNAL_OUT(out_PREDICT_PREDICTOR_DIRECTION_VAL,"DIRECTION_VAL",Tcontrol_t,(_param->_predictor_update_on_prediction [it1])?1:0); ALLOC2_SIGNAL_OUT(out_PREDICT_PREDICTOR_DIRECTION ,"DIRECTION" ,Tcontrol_t,(_param->_predictor_update_on_prediction [it1])?1:0); + + ALLOC2_INTERFACE_END(_param->_nb_predictor,_param->_nb_inst_predict); } // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("update",IN,NORTH,_("Update predictor"),_param->_nb_inst_update); + ALLOC1_INTERFACE_BEGIN("update",IN,NORTH,_("Update predictor"),_param->_nb_inst_update); ALLOC1_SIGNAL_IN ( in_UPDATE_VAL ,"VAL" ,Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_UPDATE_ACK ,"ACK" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"HISTORY" ,Thistory_t,_param->_size_history); + ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY_VAL ,"HISTORY_VAL" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION ,"DIRECTION" ,Tcontrol_t,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_update); } { - ALLOC2_INTERFACE("update_predictor",IN,NORTH,_("Update predictor"),_param->_nb_predictor,_param->_nb_inst_update); + ALLOC2_INTERFACE_BEGIN("update_predictor",IN,NORTH,_("Update predictor"),_param->_nb_predictor,_param->_nb_inst_update); ALLOC2_SIGNAL_OUT(out_UPDATE_PREDICTOR_VAL ,"VAL" ,Tcontrol_t,1); ALLOC2_SIGNAL_IN ( in_UPDATE_PREDICTOR_ACK ,"ACK" ,Tcontrol_t,1); ALLOC2_SIGNAL_OUT(out_UPDATE_PREDICTOR_HISTORY ,"HISTORY" ,Thistory_t,_param->_predictor_size_history[it1]); + ALLOC2_SIGNAL_OUT(out_UPDATE_PREDICTOR_HISTORY_VAL ,"HISTORY_VAL" ,Tcontrol_t,1); ALLOC2_SIGNAL_OUT(out_UPDATE_PREDICTOR_DIRECTION ,"DIRECTION" ,Tcontrol_t,1); ALLOC2_SIGNAL_OUT(out_UPDATE_PREDICTOR_MISS ,"MISS" ,Tcontrol_t,(_param->_predictor_update_on_prediction [it1])?1:0); + + ALLOC2_INTERFACE_END(_param->_nb_predictor,_param->_nb_inst_update); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_deallocation.cpp (revision 112) @@ -46,4 +46,5 @@ DELETE1_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update,1); DELETE1_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update,_param->_size_history); + DELETE1_SIGNAL( in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update,1); DELETE1_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update,1); @@ -51,4 +52,5 @@ DELETE2_SIGNAL( in_UPDATE_PREDICTOR_ACK ,_param->_nb_predictor,_param->_nb_inst_update,1); DELETE2_SIGNAL(out_UPDATE_PREDICTOR_HISTORY ,_param->_nb_predictor,_param->_nb_inst_update,_param->_predictor_size_history[it1]); + DELETE2_SIGNAL(out_UPDATE_PREDICTOR_HISTORY_VAL ,_param->_nb_predictor,_param->_nb_inst_update,1); DELETE2_SIGNAL(out_UPDATE_PREDICTOR_DIRECTION ,_param->_nb_predictor,_param->_nb_inst_update,1); DELETE2_SIGNAL(out_UPDATE_PREDICTOR_MISS ,_param->_nb_predictor,_param->_nb_inst_update,(_param->_predictor_update_on_prediction [it1])?1:0); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_update.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_update.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_update.cpp (revision 112) @@ -29,6 +29,7 @@ for (uint32_t i=0; i<_param->_nb_inst_update; ++i) { - Thistory_t history = PORT_READ(in_UPDATE_HISTORY [i]); - Tcontrol_t direction = PORT_READ(in_UPDATE_DIRECTION [i]); + Thistory_t history = PORT_READ(in_UPDATE_HISTORY [i]); + Tcontrol_t history_val = PORT_READ(in_UPDATE_HISTORY_VAL [i]); + Tcontrol_t direction = PORT_READ(in_UPDATE_DIRECTION [i]); switch (_param->_nb_predictor) @@ -38,8 +39,9 @@ Thistory_t history_0 = history; Tcontrol_t direction_old_0 = (history_0>>_param->_predictor_history_shift_msb[0])&1; - PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [0][i],history_0); - PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [0][i],direction); + PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [0][i],history_0); + PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY_VAL [0][i],history_val); + PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [0][i],direction); if (_param->_predictor_update_on_prediction [0]) - PORT_WRITE(out_UPDATE_PREDICTOR_MISS [0][i],direction xor direction_old_0); + PORT_WRITE(out_UPDATE_PREDICTOR_MISS [0][i],direction xor direction_old_0); break; @@ -83,18 +85,22 @@ (not direction and direction_old_0)); - PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [0][i],direction); - PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [1][i],direction); - PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [2][i],direction_new_2); + PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [0][i],direction); + PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [1][i],direction); + PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [2][i],direction_new_2); if (_param->_predictor_update_on_prediction [0]) - PORT_WRITE(out_UPDATE_PREDICTOR_MISS [0][i],direction xor direction_old_0); + PORT_WRITE(out_UPDATE_PREDICTOR_MISS [0][i],direction xor direction_old_0); if (_param->_predictor_update_on_prediction [1]) - PORT_WRITE(out_UPDATE_PREDICTOR_MISS [1][i],direction xor direction_old_1); + PORT_WRITE(out_UPDATE_PREDICTOR_MISS [1][i],direction xor direction_old_1); if (_param->_predictor_update_on_prediction [2]) - PORT_WRITE(out_UPDATE_PREDICTOR_MISS [2][i],direction_new_2 xor direction_old_2); + PORT_WRITE(out_UPDATE_PREDICTOR_MISS [2][i],direction_new_2 xor direction_old_2); - PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [0][i],history_0); - PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [1][i],history_1); - PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [2][i],history_2); + PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [0][i],history_0); + PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [1][i],history_1); + PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [2][i],history_2); + + PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY_VAL [0][i],history_val); + PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY_VAL [1][i],history_val); + PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY_VAL [2][i],history_val); break; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/SelfTest/src/test.cpp (revision 112) @@ -60,4 +60,5 @@ ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS ," in_UPDATE_ADDRESS ",Taddress_t,_param->_nb_inst_update); ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY ," in_UPDATE_HISTORY ",Thistory_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY_VAL ," in_UPDATE_HISTORY_VAL ",Tcontrol_t,_param->_nb_inst_update); ALLOC1_SC_SIGNAL( in_UPDATE_DIRECTION ," in_UPDATE_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); @@ -81,4 +82,5 @@ INSTANCE1_SC_SIGNAL(_Meta_Predictor, in_UPDATE_ADDRESS ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Meta_Predictor, in_UPDATE_HISTORY ,_param->_nb_inst_update); + INSTANCE1_SC_SIGNAL(_Meta_Predictor, in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Meta_Predictor, in_UPDATE_DIRECTION ,_param->_nb_inst_update); @@ -137,4 +139,5 @@ DELETE1_SC_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update); DELETE1_SC_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update); + DELETE1_SC_SIGNAL( in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update); DELETE1_SC_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/test.cpp (revision 112) @@ -63,4 +63,5 @@ ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS ," in_UPDATE_ADDRESS ",Taddress_t,_param->_nb_inst_update); ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY ," in_UPDATE_HISTORY ",Thistory_t,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY_VAL ," in_UPDATE_HISTORY_VAL ",Tcontrol_t,_param->_nb_inst_update); ALLOC1_SC_SIGNAL( in_UPDATE_DIRECTION ," in_UPDATE_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); ALLOC1_SC_SIGNAL( in_UPDATE_MISS ," in_UPDATE_MISS ",Tcontrol_t,_param->_nb_inst_update); @@ -90,4 +91,5 @@ INSTANCE1_SC_SIGNAL(_Two_Level_Branch_Predictor, in_UPDATE_ADDRESS ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Two_Level_Branch_Predictor, in_UPDATE_HISTORY ,_param->_nb_inst_update); + INSTANCE1_SC_SIGNAL(_Two_Level_Branch_Predictor, in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Two_Level_Branch_Predictor, in_UPDATE_DIRECTION ,_param->_nb_inst_update); if (_param->_update_on_prediction) @@ -155,11 +157,12 @@ { bool val = ((rand()%2)write(val); - in_UPDATE_DIRECTION [port]->write(0); + in_UPDATE_VAL [port]->write(val); + in_UPDATE_DIRECTION [port]->write(0); if (_param->_update_on_prediction) - in_UPDATE_MISS [port]->write(1); // miss - in_UPDATE_HISTORY [port]->write(0); - in_UPDATE_ADDRESS [port]->write(bht_num_reg); + in_UPDATE_MISS [port]->write(1); // miss + in_UPDATE_HISTORY [port]->write(0); + in_UPDATE_HISTORY_VAL [port]->write(0); + in_UPDATE_ADDRESS [port]->write(bht_num_reg); SC_START(0); @@ -185,11 +188,12 @@ { bool val = ((rand()%2)write(val); - in_UPDATE_DIRECTION [port]->write(0); + in_UPDATE_VAL [port]->write(val); + in_UPDATE_DIRECTION [port]->write(0); if (_param->_update_on_prediction) - in_UPDATE_MISS [port]->write(1); // miss - in_UPDATE_HISTORY [port]->write(i<<_param->_bht_history_rshift); - in_UPDATE_ADDRESS [port]->write(pht_num_bank<<_param->_pht_address_bank_rshift); + in_UPDATE_MISS [port]->write(1); // miss + in_UPDATE_HISTORY [port]->write(i<<_param->_bht_history_rshift); + in_UPDATE_HISTORY_VAL [port]->write(1); + in_UPDATE_ADDRESS [port]->write(pht_num_bank<<_param->_pht_address_bank_rshift); SC_START(0); @@ -241,4 +245,5 @@ DELETE1_SC_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update); DELETE1_SC_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update); + DELETE1_SC_SIGNAL( in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update); DELETE1_SC_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update); DELETE1_SC_SIGNAL( in_UPDATE_MISS ,_param->_nb_inst_update); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h (revision 112) @@ -59,4 +59,10 @@ public : Taddress_t _pht_address_bank_rshift ; + public : Thistory_t _bht_init_take ; + public : Thistory_t _bht_init_ntake ; + + public : Thistory_t _pht_init_take ; + public : Thistory_t _pht_init_ntake ; + //-----[ methods ]----------------------------------------------------------- public : Parameters (uint32_t nb_inst_predict , Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h (revision 112) @@ -80,4 +80,5 @@ public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ;//[nb_inst_update] public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ;//[nb_inst_update] + public : SC_IN (Tcontrol_t) ** in_UPDATE_HISTORY_VAL ;//[nb_inst_update] public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ;//[nb_inst_update] public : SC_IN (Tcontrol_t) ** in_UPDATE_MISS ;//[nb_inst_update] // if update_on_prediction Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Parameters.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Parameters.cpp (revision 112) @@ -44,6 +44,6 @@ _bht_nb_shifter = (have_bht)?(bht_nb_shifter ):0; _have_pht = have_pht ; - _pht_size_counter = (have_pht)?(pht_size_counter ):0; - _pht_nb_counter = (have_pht)?(pht_nb_counter ):0; + _pht_size_counter = (have_pht)?(pht_size_counter):0; + _pht_nb_counter = (have_pht)?(pht_nb_counter ):0; _pht_size_address_share = (have_bht and have_pht)?(pht_size_address_share):0; _update_on_prediction = update_on_prediction ; @@ -54,6 +54,9 @@ test(); + // history to update_prediction_table : + // MSB : pht_history + // LSB : bht_history + _size_history = _bht_size_shifter + _pht_size_counter; - _bht_history_mask = gen_mask(_bht_size_shifter); _bht_history_rshift = 0; @@ -67,4 +70,14 @@ log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * _pht_history_rshift : %d",_pht_history_rshift); + _bht_init_take = (Thistory_t)(-1)&_bht_history_mask; + _bht_init_ntake = 0; + _pht_init_take = (1<<(_pht_size_counter-1)); // size = 4 : 1000/2 + _pht_init_ntake = _pht_init_take-1; // size = 4 : 0111/2 + + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * _bht_init_take : 0x%x",_bht_init_take ); + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * _bht_init_ntake : 0x%x",_bht_init_ntake); + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * _pht_init_take : 0x%x",_pht_init_take ); + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * _pht_init_ntake : 0x%x",_pht_init_ntake); + if (_have_bht) { Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_allocation.cpp (revision 112) @@ -59,5 +59,5 @@ // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("predict",IN,WEST,_("Predict direction interface"),_param->_nb_inst_predict); + ALLOC1_INTERFACE_BEGIN("predict",IN,WEST,_("Predict direction interface"),_param->_nb_inst_predict); ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); @@ -71,9 +71,11 @@ ALLOC1_SIGNAL_IN ( in_PREDICT_DIRECTION ,"DIRECTION" ,Tcontrol_t,1 ); } + + ALLOC1_INTERFACE_END(_param->_nb_inst_predict); } // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("update",IN,WEST,_("Update direction interface"),_param->_nb_inst_update); + ALLOC1_INTERFACE_BEGIN("update",IN,WEST,_("Update direction interface"),_param->_nb_inst_update); ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); @@ -81,8 +83,13 @@ ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"ADDRESS" ,Taddress_t,_param->_size_address); ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"HISTORY" ,Thistory_t,_param->_size_history); + ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY_VAL ,"HISTORY_VAL" ,Tcontrol_t,1 ); ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION ,"DIRECTION" ,Tcontrol_t,1 ); if (_param->_update_on_prediction) ALLOC1_SIGNAL_IN ( in_UPDATE_MISS ,"MISS" ,Tcontrol_t,1 ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_update); } + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ if (usage_is_set(_usage,USE_SYSTEMC)) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_deallocation.cpp (revision 112) @@ -46,4 +46,5 @@ DELETE1_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update,_param->_size_address); DELETE1_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update,_param->_size_history); + DELETE1_SIGNAL( in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update,1 ); DELETE1_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update,1 ); if (_param->_update_on_prediction) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_transition.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_transition.cpp (revision 112) @@ -90,16 +90,24 @@ { log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * UPDATE [%d]",i); + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * miss : %d",PORT_READ(in_UPDATE_MISS [i])); + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * update_on_predict: %d",_param->_update_on_prediction); // Update if // * update_on_prediction and miss // * not update_on_prediction - if (not _param->_update_on_prediction or (_param->_update_on_prediction and PORT_READ(in_UPDATE_MISS [i]))) - { - Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); - Thistory_t history = PORT_READ(in_UPDATE_HISTORY [i]); - Tcontrol_t direction = PORT_READ(in_UPDATE_DIRECTION [i])&1; + Tcontrol_t history_val = PORT_READ(in_UPDATE_HISTORY_VAL [i]); + + if (not _param->_update_on_prediction or + (_param->_update_on_prediction and PORT_READ(in_UPDATE_MISS [i])) or + not history_val // static_prediction + ) + { + Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); + Thistory_t history = PORT_READ(in_UPDATE_HISTORY [i]); + Tcontrol_t direction = PORT_READ(in_UPDATE_DIRECTION [i])&1; log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * address : %.8x",address); log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * direction : %d",direction); + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * history_val : %d",direction); Thistory_t pht_bht_history = 0; @@ -107,16 +115,20 @@ if (_param->_have_bht) { + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht"); + Thistory_t bht_history = (history>>_param->_bht_history_rshift)&_param->_bht_history_mask; Thistory_t bht_num_reg = address & _param->_bht_address_mask; + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_history (old): %x",bht_history); + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_num_reg : %x",bht_num_reg); + + // BHT : shift register + if (not history_val) + bht_history = (direction)?_param->_bht_init_take:_param->_bht_init_ntake; + else + bht_history = ((bht_history<<1) | direction)&_param->_bht_history_mask ; + pht_bht_history = bht_history; - - log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_history (old): %x",bht_history); - log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_num_reg : %x",bht_num_reg); - - // BHT : shift register - - bht_history = ((bht_history<<1) | direction)&_param->_bht_history_mask ; - log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_history (new): %x",bht_history); + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_history (new): %x",bht_history); reg_BHT [bht_num_reg] = bht_history; } @@ -124,17 +136,22 @@ if (_param->_have_pht) { + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht"); + Thistory_t pht_history = (history>>_param->_pht_history_rshift)&_param->_pht_history_mask; Thistory_t pht_num_reg = pht_bht_history xor ((address&_param->_pht_address_share_mask)<<_param->_pht_address_share_lshift); Thistory_t pht_num_bank= (address>>_param->_pht_address_bank_rshift)&_param->_pht_address_bank_mask; - log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_history (old): %x",pht_bht_history); - log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_history (old): %x",pht_history); - log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_num_reg : %x",pht_num_reg); - log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_num_bank : %x",pht_num_bank); + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_history (old): %x",pht_bht_history); + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_history (old): %x",pht_history); + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_num_reg : %x",pht_num_reg); + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_num_bank : %x",pht_num_bank); // PHT : saturation counter - pht_history = (direction==1)?((pht_history<_param->_pht_counter_max)?(pht_history+1):(pht_history)):((pht_history>0)?(pht_history-1):(pht_history)); - - log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_history (new): %x",pht_history); + if (not history_val) + pht_history = (direction)?_param->_pht_init_take:_param->_pht_init_ntake; + else + pht_history = (direction==1)?((pht_history<_param->_pht_counter_max)?(pht_history+1):(pht_history)):((pht_history>0)?(pht_history-1):(pht_history)); + + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_history (new): %x",pht_history); reg_PHT [pht_num_bank][pht_num_reg] = pht_history; @@ -145,5 +162,5 @@ #if defined(DEBUG) and DEBUG_Two_Level_Branch_Predictor and (DEBUG >= DEBUG_TRACE) - if (0) + if (1) { log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * Dump Two_Level_Branch_Predictor"); @@ -180,20 +197,27 @@ for (uint32_t num_bank=0; num_bank <_param->_pht_nb_bank; ++num_bank) { - log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," [%.4d]",num_bank); - - for (uint32_t i=0; i<_param->_pht_size_bank; i+=limit) - { - std::string str = ""; + if (_param->_pht_size_bank == 1) + { + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," [%.4d][0000] %4x",num_bank,reg_PHT[num_bank][0]); + } + else + { + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," [%.4d]",num_bank); - for (uint32_t j=0; j_pht_size_bank; i+=limit) { - uint32_t index = i+j; - if (index >= _param->_pht_nb_counter) - break; - else - str+=toString("[%.4d] %.4x ",index,reg_PHT[num_bank][index]); + std::string str = ""; + + for (uint32_t j=0; j= _param->_pht_size_bank) + break; + else + str+=toString("[%.4d] %.4x ",index,reg_PHT[num_bank][index]); + } + + log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," %s",str.c_str()); } - - log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," %s",str.c_str()); } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/include/Meta_Predictor.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/include/Meta_Predictor.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/include/Meta_Predictor.h (revision 112) @@ -80,4 +80,5 @@ public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ;//[nb_inst_update] public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ;//[nb_inst_update] + public : SC_IN (Tcontrol_t) ** in_UPDATE_HISTORY_VAL ;//[nb_inst_update] public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ;//[nb_inst_update] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_allocation.cpp (revision 112) @@ -58,5 +58,5 @@ // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("predict",IN,WEST,_("Predict direction interface"),_param->_nb_inst_predict); + ALLOC1_INTERFACE_BEGIN("predict",IN,WEST,_("Predict direction interface"),_param->_nb_inst_predict); ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); @@ -65,9 +65,11 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_DIRECTION ,"DIRECTION" ,Tcontrol_t,1 ); ALLOC1_SIGNAL_OUT(out_PREDICT_HISTORY ,"HISTORY" ,Thistory_t,_param->_size_history); + + ALLOC1_INTERFACE_END(_param->_nb_inst_predict); } // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("update",IN,WEST,_("Update direction interface"),_param->_nb_inst_update); + ALLOC1_INTERFACE_BEGIN("update",IN,WEST,_("Update direction interface"),_param->_nb_inst_update); ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); @@ -75,5 +77,8 @@ ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"ADDRESS" ,Taddress_t,_param->_size_address); ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"HISTORY" ,Thistory_t,_param->_size_history); + ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY_VAL ,"HISTORY_VAL" ,Tcontrol_t,1 ); ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION ,"DIRECTION" ,Tcontrol_t,1 ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_update); } @@ -218,4 +223,6 @@ COMPONENT_MAP(_component,src , "in_UPDATE_" +toString(j)+"_HISTORY" , dest,"out_UPDATE_PREDICTOR_"+toString(i)+"_"+toString(j)+"_HISTORY" ); + COMPONENT_MAP(_component,src , "in_UPDATE_" +toString(j)+"_HISTORY_VAL" , + dest,"out_UPDATE_PREDICTOR_"+toString(i)+"_"+toString(j)+"_HISTORY_VAL" ); if (_param->_predictor_update_on_prediction [i]) COMPONENT_MAP(_component,src , "in_UPDATE_" +toString(j)+"_MISS" , @@ -286,19 +293,22 @@ #endif - PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_VAL" , - dest, "in_UPDATE_"+toString(i)+"_VAL" ); - PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_ACK" , - dest,"out_UPDATE_"+toString(i)+"_ACK" ); - PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_HISTORY" , - dest, "in_UPDATE_"+toString(i)+"_HISTORY" ); - PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_DIRECTION", - dest, "in_UPDATE_"+toString(i)+"_DIRECTION"); - } - - // out_UPDATE_PREDICTOR_VAL -> two_level_branch_predictor. in_UPDATE_PREDICTOR_VAL - // in_UPDATE_PREDICTOR_ACK -> two_level_branch_predictor.out_UPDATE_PREDICTOR_ACK - // out_UPDATE_PREDICTOR_HISTORY -> two_level_branch_predictor. in_UPDATE_PREDICTOR_HISTORY - // out_UPDATE_PREDICTOR_DIRECTION -> two_level_branch_predictor. in_UPDATE_PREDICTOR_DIRECTION - // out_UPDATE_PREDICTOR_MISS -> two_level_branch_predictor. in_UPDATE_PREDICTOR_MISS + PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_VAL" , + dest, "in_UPDATE_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_ACK" , + dest,"out_UPDATE_"+toString(i)+"_ACK" ); + PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_HISTORY" , + dest, "in_UPDATE_"+toString(i)+"_HISTORY" ); + PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_HISTORY_VAL", + dest, "in_UPDATE_"+toString(i)+"_HISTORY_VAL"); + PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_DIRECTION" , + dest, "in_UPDATE_"+toString(i)+"_DIRECTION" ); + } + + // out_UPDATE_PREDICTOR_VAL -> two_level_branch_predictor. in_UPDATE_PREDICTOR_VAL + // in_UPDATE_PREDICTOR_ACK -> two_level_branch_predictor.out_UPDATE_PREDICTOR_ACK + // out_UPDATE_PREDICTOR_HISTORY -> two_level_branch_predictor. in_UPDATE_PREDICTOR_HISTORY + // out_UPDATE_PREDICTOR_HISTORY_VAL-> two_level_branch_predictor. in_UPDATE_PREDICTOR_HISTORY + // out_UPDATE_PREDICTOR_DIRECTION -> two_level_branch_predictor. in_UPDATE_PREDICTOR_DIRECTION + // out_UPDATE_PREDICTOR_MISS -> two_level_branch_predictor. in_UPDATE_PREDICTOR_MISS } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_deallocation.cpp (revision 112) @@ -40,4 +40,5 @@ DELETE1_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update,_param->_size_address); DELETE1_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update,_param->_size_history); + DELETE1_SIGNAL( in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update,1 ); DELETE1_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update,1 ); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Parameters.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Parameters.cpp (revision 112) @@ -64,4 +64,8 @@ if (_have_meta_predictor) _predictor_update_on_prediction [_nb_predictor-1] = false; + +// // All predictor can't update on prediction .... +// for (uint32_t i=0; i<_nb_predictor; ++i) +// _predictor_update_on_prediction [i] = false; _param_two_level_branch_predictor = new morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::direction::meta_predictor::two_level_branch_predictor::Parameters * [_nb_predictor]; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Direction.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Direction.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Direction.h (revision 112) @@ -63,18 +63,19 @@ // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t) ** in_PREDICT_VAL ; - public : SC_OUT(Tcontrol_t) ** out_PREDICT_ACK ; - public : SC_IN (Taddress_t) ** in_PREDICT_ADDRESS_SRC; - public : SC_IN (Tcontrol_t) ** in_PREDICT_STATIC ; - public : SC_IN (Tcontrol_t) ** in_PREDICT_LAST_TAKE ; - public : SC_OUT(Thistory_t) ** out_PREDICT_HISTORY ; - public : SC_OUT(Tcontrol_t) ** out_PREDICT_DIRECTION ; + public : SC_IN (Tcontrol_t) ** in_PREDICT_VAL ; + public : SC_OUT(Tcontrol_t) ** out_PREDICT_ACK ; + public : SC_IN (Taddress_t) ** in_PREDICT_ADDRESS_SRC ; + public : SC_IN (Tcontrol_t) ** in_PREDICT_STATIC ; + public : SC_IN (Tcontrol_t) ** in_PREDICT_LAST_TAKE ; + public : SC_OUT(Thistory_t) ** out_PREDICT_HISTORY ; + public : SC_OUT(Tcontrol_t) ** out_PREDICT_DIRECTION ; // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t) ** in_UPDATE_VAL ; - public : SC_OUT(Tcontrol_t) ** out_UPDATE_ACK ; - public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ; - public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ; - public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ; + public : SC_IN (Tcontrol_t) ** in_UPDATE_VAL ; + public : SC_OUT(Tcontrol_t) ** out_UPDATE_ACK ; + public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ; + public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ; + public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ; + public : SC_IN (Tcontrol_t) ** in_UPDATE_PREDICTION_IFETCH; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_allocation.cpp (revision 112) @@ -49,5 +49,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -59,5 +59,5 @@ // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("predict", IN, SOUTH, "Interface predict",_param->_nb_inst_predict); + ALLOC1_INTERFACE_BEGIN("predict", IN, SOUTH, _("Interface predict"),_param->_nb_inst_predict); ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); @@ -68,15 +68,20 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_HISTORY ,"history" ,Thistory_t,_param->_size_history); ALLOC1_SIGNAL_OUT(out_PREDICT_DIRECTION ,"direction" ,Tcontrol_t,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_predict); } // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("update", IN, SOUTH, "Interface update",_param->_nb_inst_update); - - ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); - ALLOC1_VALACK_OUT(out_UPDATE_ACK ,ACK); - ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); - ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"history" ,Thistory_t,_param->_size_history); - ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION,"direction",Tcontrol_t,1); + ALLOC1_INTERFACE_BEGIN("update", IN, SOUTH, _("Interface update"),_param->_nb_inst_update); + + ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); + ALLOC1_VALACK_OUT(out_UPDATE_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"history" ,Thistory_t,_param->_size_history); + ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION ,"direction" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_UPDATE_PREDICTION_IFETCH,"prediction_ifetch",Tcontrol_t,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_update); } @@ -183,4 +188,6 @@ COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_HISTORY" , dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_HISTORY" ); + COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_HISTORY_VAL" , + dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_PREDICTION_IFETCH"); } } @@ -212,25 +219,25 @@ #endif - PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_VAL" , - dest, "in_PREDICT_"+toString(i)+"_VAL" ); - PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_ACK" , - dest,"out_PREDICT_"+toString(i)+"_ACK" ); - PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_ADDRESS_SRC", - dest, "in_PREDICT_"+toString(i)+"_ADDRESS_SRC"); - PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_STATIC" , - dest, "in_PREDICT_"+toString(i)+"_STATIC" ); - PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_LAST_TAKE" , - dest, "in_PREDICT_"+toString(i)+"_LAST_TAKE" ); - if (_param->_have_port_history) - PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_HISTORY" , - dest,"out_PREDICT_"+toString(i)+"_HISTORY" ); - PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_DIRECTION" , - dest,"out_PREDICT_"+toString(i)+"_DIRECTION" ); - -// PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_PREDICTOR_VAL" ,dest,"out_PREDICT_"+toString(i)+"_PREDICTOR_VAL" ); -// PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_PREDICTOR_ACK" ,dest, "in_PREDICT_"+toString(i)+"_PREDICTOR_ACK" ); -// PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_PREDICTOR_ADDRESS_SRC",dest,"out_PREDICT_"+toString(i)+"_PREDICTOR_ADDRESS_SRC"); -// PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_PREDICTOR_HISTORY" ,dest, "in_PREDICT_"+toString(i)+"_PREDICTOR_HISTORY" ); -// PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_PREDICTOR_DIRECTION" ,dest, "in_PREDICT_"+toString(i)+"_PREDICTOR_DIRECTION" ); + PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_VAL" , + dest, "in_PREDICT_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_ACK" , + dest,"out_PREDICT_"+toString(i)+"_ACK" ); + PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_ADDRESS_SRC" , + dest, "in_PREDICT_"+toString(i)+"_ADDRESS_SRC" ); + PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_STATIC" , + dest, "in_PREDICT_"+toString(i)+"_STATIC" ); + PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_LAST_TAKE" , + dest, "in_PREDICT_"+toString(i)+"_LAST_TAKE" ); + if (_param->_have_port_history) + PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_HISTORY" , + dest,"out_PREDICT_"+toString(i)+"_HISTORY" ); + PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_DIRECTION" , + dest,"out_PREDICT_"+toString(i)+"_DIRECTION" ); + +// PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_PREDICTOR_VAL" ,dest,"out_PREDICT_"+toString(i)+"_PREDICTOR_VAL" ); +// PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_PREDICTOR_ACK" ,dest, "in_PREDICT_"+toString(i)+"_PREDICTOR_ACK" ); +// PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_PREDICTOR_ADDRESS_SRC" ,dest,"out_PREDICT_"+toString(i)+"_PREDICTOR_ADDRESS_SRC" ); +// PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_PREDICTOR_HISTORY" ,dest, "in_PREDICT_"+toString(i)+"_PREDICTOR_HISTORY" ); +// PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_PREDICTOR_DIRECTION" ,dest, "in_PREDICT_"+toString(i)+"_PREDICTOR_DIRECTION" ); } @@ -243,20 +250,25 @@ #endif - PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_VAL" , - dest, "in_UPDATE_"+toString(i)+"_VAL" ); - PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_ACK" , - dest,"out_UPDATE_"+toString(i)+"_ACK" ); - PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_ADDRESS" , - dest, "in_UPDATE_"+toString(i)+"_ADDRESS" ); + PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_VAL" , + dest, "in_UPDATE_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_ACK" , + dest,"out_UPDATE_"+toString(i)+"_ACK" ); + PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_ADDRESS" , + dest, "in_UPDATE_"+toString(i)+"_ADDRESS" ); if (_param->_have_port_history) - PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_HISTORY" , - dest, "in_UPDATE_"+toString(i)+"_HISTORY" ); - PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_DIRECTION", - dest, "in_UPDATE_"+toString(i)+"_DIRECTION"); -// PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_VAL" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_VAL" ); -// PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_PREDICTOR_ACK" ,dest, "in_UPDATE_"+toString(i)+"_PREDICTOR_ACK" ); -// PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_ADDRESS" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_ADDRESS" ); -// PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_HISTORY" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_HISTORY" ); -// PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_DIRECTION",dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_DIRECTION"); + PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_HISTORY" , + dest, "in_UPDATE_"+toString(i)+"_HISTORY" ); + PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_DIRECTION" , + dest, "in_UPDATE_"+toString(i)+"_DIRECTION" ); + PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_PREDICTION_IFETCH", + dest, "in_UPDATE_"+toString(i)+"_PREDICTION_IFETCH"); + +// PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_VAL" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_VAL" ); +// PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_PREDICTOR_ACK" ,dest, "in_UPDATE_"+toString(i)+"_PREDICTOR_ACK" ); +// PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_ADDRESS" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_ADDRESS" ); +// PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_HISTORY" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_HISTORY" ); +// PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_DIRECTION" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_DIRECTION" ); +// PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_PREDICTION_IFETCH",dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_PREDICTION_IFETCH"); + } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Direction.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -28,18 +29,18 @@ delete in_NRESET; - delete [] in_PREDICT_VAL ; - delete [] out_PREDICT_ACK ; - delete [] in_PREDICT_ADDRESS_SRC ; - delete [] in_PREDICT_STATIC ; - delete [] in_PREDICT_LAST_TAKE ; - if (_param->_have_port_history) - delete [] out_PREDICT_HISTORY ; - delete [] out_PREDICT_DIRECTION ; - delete [] in_UPDATE_VAL ; - delete [] out_UPDATE_ACK ; - delete [] in_UPDATE_ADDRESS ; - if (_param->_have_port_history) - delete [] in_UPDATE_HISTORY ; - delete [] in_UPDATE_DIRECTION ; + DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_ADDRESS_SRC,_param->_nb_inst_predict,_param->_size_instruction_address); + DELETE1_SIGNAL( in_PREDICT_STATIC ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_LAST_TAKE ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL(out_PREDICT_HISTORY ,_param->_nb_inst_predict,_param->_size_history); + DELETE1_SIGNAL(out_PREDICT_DIRECTION ,_param->_nb_inst_predict,1); + + DELETE1_SIGNAL( in_UPDATE_VAL ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update,_param->_size_instruction_address); + DELETE1_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update,_param->_size_history); + DELETE1_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_PREDICTION_IFETCH,_param->_nb_inst_update,1); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp (revision 112) @@ -208,7 +208,7 @@ { if (_param->_have_port_inst_ifetch_ptr) - INSTANCE_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_INST_IFETCH_PTR [i]); + INSTANCE0_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_INST_IFETCH_PTR [i]); if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]); + INSTANCE0_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]); } @@ -350,9 +350,9 @@ // if (_param->_have_port_depth) // { -// INSTANCE_SC_SIGNAL(_Prediction_unit_Glue, in_DEPTH_UPT_TAIL [i]); -// INSTANCE_SC_SIGNAL(_Prediction_unit_Glue,out_DEPTH_TAIL [i]); +// INSTANCE0_SC_SIGNAL(_Prediction_unit_Glue, in_DEPTH_UPT_TAIL [i]); +// INSTANCE0_SC_SIGNAL(_Prediction_unit_Glue,out_DEPTH_TAIL [i]); // } -// INSTANCE_SC_SIGNAL(_Prediction_unit_Glue, in_DEPTH_UPT_NB_BRANCH [i]); -// INSTANCE_SC_SIGNAL(_Prediction_unit_Glue,out_DEPTH_NB_BRANCH [i]); +// INSTANCE0_SC_SIGNAL(_Prediction_unit_Glue, in_DEPTH_UPT_NB_BRANCH [i]); +// INSTANCE0_SC_SIGNAL(_Prediction_unit_Glue,out_DEPTH_NB_BRANCH [i]); // } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_allocation.cpp (revision 112) @@ -47,5 +47,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -58,5 +58,5 @@ { { - ALLOC1_INTERFACE("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("predict",IN,SOUTH,_("Interface with ifetch unit"),_param->_nb_context); ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); @@ -70,12 +70,17 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); - } - { - ALLOC2_INTERFACE("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context,_param->_nb_instruction[it1]); + + ALLOC1_INTERFACE_END(_param->_nb_context); + } + { + ALLOC2_INTERFACE_BEGIN("predict",IN,SOUTH,_("Interface with ifetch unit"),_param->_nb_context,_param->_nb_instruction[it1]); + _ALLOC2_SIGNAL_OUT(out_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1,_param->_nb_context,_param->_nb_instruction[it1]); - } - - { - ALLOC1_INTERFACE("predict_btb",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); + + ALLOC2_INTERFACE_END(_param->_nb_context,_param->_nb_instruction[it1]); + } + + { + ALLOC1_INTERFACE_BEGIN("predict_btb",OUT,NORTH,_("Interface with ifetch unit"),_param->_nb_inst_branch_predict); ALLOC1_VALACK_OUT(out_PREDICT_BTB_VAL ,VAL); @@ -89,8 +94,10 @@ // ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); - } - - { - ALLOC1_INTERFACE("predict_dir",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_predict); + } + + { + ALLOC1_INTERFACE_BEGIN("predict_dir",OUT,NORTH,_("Interface with ifetch unit"),_param->_nb_inst_branch_predict); ALLOC1_VALACK_OUT(out_PREDICT_DIR_VAL ,VAL); @@ -101,8 +108,10 @@ // ALLOC1_SIGNAL_IN ( in_PREDICT_DIR_HISTORY ,"history" ,Thistory_t ,_param->_size_history); ALLOC1_SIGNAL_IN ( in_PREDICT_DIR_DIRECTION ,"direction" ,Tcontrol_t ,1); - } - - { - ALLOC1_INTERFACE("predict_ras",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_predict); + } + + { + ALLOC1_INTERFACE_BEGIN("predict_ras",OUT,NORTH,_("Interface with ifetch unit"),_param->_nb_inst_branch_predict); ALLOC1_VALACK_OUT(out_PREDICT_RAS_VAL ,VAL); @@ -114,8 +123,10 @@ ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_ADDRESS_POP ,"address_pop" ,Taddress_t ,_param->_size_instruction_address); // ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_INDEX ,"index" ,Tptr_t ,_param->_size_ras_index); - } - - { - ALLOC1_INTERFACE("predict_upt",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_predict); + } + + { + ALLOC1_INTERFACE_BEGIN("predict_upt",OUT,NORTH,_("Interface with ifetch unit"),_param->_nb_inst_branch_predict); ALLOC1_VALACK_OUT(out_PREDICT_UPT_VAL ,VAL); @@ -131,4 +142,6 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); // ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_size_ras_index); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_predict); } } @@ -137,5 +150,5 @@ { { - ALLOC2_INTERFACE("decod",IN,SOUTH,"Interface with decod unit",_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_INTERFACE_BEGIN("decod",IN,SOUTH,_("Interface with decod unit"),_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); _ALLOC2_VALACK_IN ( in_DECOD_VAL ,VAL,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); @@ -150,8 +163,10 @@ _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_OUT(out_DECOD_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); - } - - { - ALLOC1_INTERFACE("decod_btb",OUT,NORTH,"Interface with decod unit",_param->_nb_inst_branch_decod); + + ALLOC2_INTERFACE_END(_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + } + + { + ALLOC1_INTERFACE_BEGIN("decod_btb",OUT,NORTH,_("Interface with decod unit"),_param->_nb_inst_branch_decod); ALLOC1_VALACK_OUT(out_DECOD_BTB_VAL ,VAL); @@ -164,8 +179,10 @@ ALLOC1_SIGNAL_OUT(out_DECOD_BTB_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_DECOD_BTB_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); - } - - { - ALLOC1_INTERFACE("decod_ras",OUT,NORTH,"Interface with decod unit",_param->_nb_inst_branch_decod); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_decod); + } + + { + ALLOC1_INTERFACE_BEGIN("decod_ras",OUT,NORTH,_("Interface with decod unit"),_param->_nb_inst_branch_decod); ALLOC1_VALACK_OUT(out_DECOD_RAS_VAL ,VAL); @@ -178,8 +195,10 @@ // ALLOC1_SIGNAL_IN ( in_DECOD_RAS_INDEX ,"index" ,Tptr_t ,_param->_size_ras_index); ALLOC1_SIGNAL_OUT(out_DECOD_RAS_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); - } - - { - ALLOC1_INTERFACE("decod_upt",OUT,NORTH,"Interface with decod unit",_param->_nb_inst_branch_decod); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_decod); + } + + { + ALLOC1_INTERFACE_BEGIN("decod_upt",OUT,NORTH,_("Interface with decod unit"),_param->_nb_inst_branch_decod); ALLOC1_VALACK_OUT(out_DECOD_UPT_VAL ,VAL); @@ -197,4 +216,6 @@ ALLOC1_SIGNAL_OUT(out_DECOD_UPT_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_DECOD_UPT_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_decod); } } @@ -203,5 +224,5 @@ { { - ALLOC1_INTERFACE("update_btb",OUT,SOUTH,"Interface with update unit",_param->_nb_inst_branch_update); + ALLOC1_INTERFACE_BEGIN("update_btb",OUT,SOUTH,_("Interface with update unit"),_param->_nb_inst_branch_update); ALLOC1_VALACK_OUT(out_UPDATE_BTB_VAL ,VAL); @@ -213,8 +234,10 @@ // ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); // ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); - } - - { - ALLOC1_INTERFACE("update_dir",OUT,NORTH,"Interface with update unit",_param->_nb_inst_branch_update); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_update); + } + + { + ALLOC1_INTERFACE_BEGIN("update_dir",OUT,NORTH,_("Interface with update unit"),_param->_nb_inst_branch_update); ALLOC1_VALACK_OUT(out_UPDATE_DIR_VAL ,VAL); @@ -223,8 +246,10 @@ // ALLOC1_SIGNAL_OUT(out_UPDATE_DIR_HISTORY ,"history" ,Thistory_t ,_param->_size_history); // ALLOC1_SIGNAL_OUT(out_UPDATE_DIR_DIRECTION ,"direction" ,Tcontrol_t ,1); - } - - { - ALLOC1_INTERFACE("update_ras",OUT,NORTH,"Interface with update unit",_param->_nb_inst_branch_update); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_update); + } + + { + ALLOC1_INTERFACE_BEGIN("update_ras",OUT,NORTH,_("Interface with update unit"),_param->_nb_inst_branch_update); ALLOC1_VALACK_OUT(out_UPDATE_RAS_VAL ,VAL); @@ -236,8 +261,10 @@ // ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); // ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_PREDICTION_IFETCH ,"prediction_ifetch" ,Tcontrol_t ,1); - } - - { - ALLOC1_INTERFACE("update_upt",IN ,NORTH,"Interface with update unit",_param->_nb_inst_branch_update); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_update); + } + + { + ALLOC1_INTERFACE_BEGIN("update_upt",IN ,NORTH,_("Interface with update unit"),_param->_nb_inst_branch_update); ALLOC1_VALACK_IN ( in_UPDATE_UPT_VAL ,VAL); @@ -257,4 +284,6 @@ // ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_size_ras_index); // ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_RAS_PREDICTION_IFETCH,"ras_prediction_ifetch",Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_update); } } @@ -262,5 +291,5 @@ // // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // { -// ALLOC1_INTERFACE("depth",IN,NORTH,"Interface with depth",_param->_nb_context); +// ALLOC1_INTERFACE_BEGIN("depth",IN,NORTH,_("Interface with depth"),_param->_nb_context); // // ALLOC1_SIGNAL_IN ( in_DEPTH_UPT_NB_BRANCH,"upt_nb_branch",Tdepth_t,_param->_size_depth+1); @@ -268,4 +297,6 @@ // ALLOC1_SIGNAL_OUT(out_DEPTH_NB_BRANCH ,"nb_branch" ,Tdepth_t,_param->_size_depth+1); // ALLOC1_SIGNAL_OUT(out_DEPTH_TAIL ,"tail" ,Tdepth_t,_param->_size_depth); +// +// ALLOC1_INTERFACE_END(_param->_nb_context); // } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp (revision 112) @@ -46,5 +46,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -56,5 +56,5 @@ // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("predict", IN, SOUTH, "predict's interface", _param->_nb_inst_predict); + ALLOC1_INTERFACE_BEGIN("predict", IN, SOUTH, _("predict's interface"), _param->_nb_inst_predict); ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); @@ -66,9 +66,11 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_POP ,"address_pop" ,Taddress_t,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_PREDICT_INDEX ,"index" ,Tptr_t ,_param->_size_index); + + ALLOC1_INTERFACE_END(_param->_nb_inst_predict); } // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("decod", IN, SOUTH, "decod's interface", _param->_nb_inst_decod); + ALLOC1_INTERFACE_BEGIN("decod", IN, SOUTH, _("decod's interface"), _param->_nb_inst_decod); ALLOC1_VALACK_IN ( in_DECOD_VAL ,VAL); @@ -81,9 +83,11 @@ ALLOC1_SIGNAL_OUT(out_DECOD_INDEX ,"index" ,Tptr_t ,_param->_size_index); ALLOC1_SIGNAL_IN ( in_DECOD_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_decod); } // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("update", IN, SOUTH, "update's interface", _param->_nb_inst_update); + ALLOC1_INTERFACE_BEGIN("update", IN, SOUTH, _("update's interface"), _param->_nb_inst_update); ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); @@ -96,4 +100,6 @@ ALLOC1_SIGNAL_IN ( in_UPDATE_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_UPDATE_PREDICTION_IFETCH,"prediction_ifetch",Tcontrol_t,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_update); } @@ -101,22 +107,19 @@ { // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ALLOC2(reg_stack ,ras_entry_t,_param->_nb_context,_param->_size_queue [it1]); - reg_stack = new ras_entry_t * [_param->_nb_context]; - for (uint32_t i=0; i<_param->_nb_context; i++) - reg_stack [i] = new ras_entry_t [_param->_size_queue [i]]; + ALLOC1(reg_TOP ,Tptr_t ,_param->_nb_context); +// ALLOC1(reg_BOTTOM ,Tptr_t ,_param->_nb_context); + ALLOC1(reg_NB_ELT ,Tptr_t ,_param->_nb_context); - reg_TOP = new Tptr_t [_param->_nb_context]; -// reg_BOTTOM = new Tptr_t [_param->_nb_context]; - reg_NB_ELT = new Tptr_t [_param->_nb_context]; + ALLOC1(reg_PREDICT_TOP ,Tptr_t ,_param->_nb_context); +// ALLOC1(reg_PREDICT_BOTTOM ,Tptr_t ,_param->_nb_context); + ALLOC1(reg_PREDICT_NB_ELT ,Tptr_t ,_param->_nb_context); - reg_PREDICT_TOP = new Tptr_t [_param->_nb_context]; -// reg_PREDICT_BOTTOM = new Tptr_t [_param->_nb_context]; - reg_PREDICT_NB_ELT = new Tptr_t [_param->_nb_context]; - - internal_PREDICT_ACK = new Tcontrol_t [_param->_nb_inst_predict]; - internal_PREDICT_HIT = new Tcontrol_t [_param->_nb_inst_predict]; - internal_DECOD_ACK = new Tcontrol_t [_param->_nb_inst_decod ]; - internal_DECOD_HIT = new Tcontrol_t [_param->_nb_inst_decod ]; - internal_UPDATE_ACK = new Tcontrol_t [_param->_nb_inst_update ]; + ALLOC1(internal_PREDICT_ACK ,Tcontrol_t ,_param->_nb_inst_predict); + ALLOC1(internal_PREDICT_HIT ,Tcontrol_t ,_param->_nb_inst_predict); + ALLOC1(internal_DECOD_ACK ,Tcontrol_t ,_param->_nb_inst_decod ); + ALLOC1(internal_DECOD_HIT ,Tcontrol_t ,_param->_nb_inst_decod ); + ALLOC1(internal_UPDATE_ACK ,Tcontrol_t ,_param->_nb_inst_update ); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp (revision 112) @@ -59,20 +59,19 @@ // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - for (uint32_t i=0; i<_param->_nb_context; i++) - delete [] reg_stack [i]; - delete [] reg_stack; - delete [] reg_TOP; -// delete [] reg_BOTTOM; - delete [] reg_NB_ELT; - delete [] reg_PREDICT_TOP; -// delete [] reg_PREDICT_BOTTOM; - delete [] reg_PREDICT_NB_ELT; - - delete [] internal_PREDICT_ACK; - delete [] internal_PREDICT_HIT; - delete [] internal_DECOD_ACK; - delete [] internal_DECOD_HIT; - delete [] internal_UPDATE_ACK; + DELETE2(reg_stack ,_param->_nb_context,_param->_size_queue [it1]); + + DELETE1(reg_TOP ,_param->_nb_context); +// DELETE1(reg_BOTTOM ,_param->_nb_context); + DELETE1(reg_NB_ELT ,_param->_nb_context); + + DELETE1(reg_PREDICT_TOP ,_param->_nb_context); +// DELETE1(reg_PREDICT_BOTTOM ,_param->_nb_context); + DELETE1(reg_PREDICT_NB_ELT ,_param->_nb_context); + + DELETE1(internal_PREDICT_ACK ,_param->_nb_inst_predict); + DELETE1(internal_PREDICT_HIT ,_param->_nb_inst_predict); + DELETE1(internal_DECOD_ACK ,_param->_nb_inst_decod ); + DELETE1(internal_DECOD_HIT ,_param->_nb_inst_decod ); + DELETE1(internal_UPDATE_ACK ,_param->_nb_inst_update ); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 112) @@ -126,4 +126,5 @@ ALLOC1_SC_SIGNAL(out_UPDATE_MISS_PREDICTION ,"out_UPDATE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_update); ALLOC1_SC_SIGNAL(out_UPDATE_DIRECTION_GOOD ,"out_UPDATE_DIRECTION_GOOD ",Tcontrol_t ,_param->_nb_inst_update); + ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTION_IFETCH ,"out_UPDATE_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update); ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_update); ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,"out_UPDATE_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_update); @@ -137,5 +138,4 @@ ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update); ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update); - ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update); ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); @@ -223,4 +223,5 @@ INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update); + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_PREDICTION_IFETCH ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_VAL ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update); @@ -235,5 +236,4 @@ INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update); - INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context); @@ -575,4 +575,5 @@ TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); + TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition)); if (update_btb(it_upt->condition)) @@ -593,5 +594,4 @@ TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); - TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); } ++ it_upt; @@ -906,5 +906,5 @@ TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); - TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); + TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); } ++ it_upt; @@ -1281,5 +1281,5 @@ TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address); TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index); - TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); + TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); } } @@ -1353,5 +1353,5 @@ TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); - TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); + TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); } ++ it_upt; @@ -1888,5 +1888,5 @@ TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address); TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index); - TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); + TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); } } @@ -1976,5 +1976,5 @@ TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); - TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); + TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); } @@ -2103,5 +2103,5 @@ TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); - TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); + TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); } @@ -2544,5 +2544,5 @@ TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address); TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index); - TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); + TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); } } @@ -2637,5 +2637,5 @@ TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); - TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); + TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); } // -- it_upt; @@ -2763,5 +2763,5 @@ TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); - TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); + TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); } @@ -2870,4 +2870,5 @@ delete [] out_UPDATE_MISS_PREDICTION ; delete [] out_UPDATE_DIRECTION_GOOD ; + delete [] out_UPDATE_PREDICTION_IFETCH ; delete [] out_UPDATE_BTB_VAL ; delete [] out_UPDATE_BTB_ADDRESS_SRC ; @@ -2881,5 +2882,4 @@ delete [] out_UPDATE_RAS_ADDRESS ; delete [] out_UPDATE_RAS_INDEX ; - delete [] out_UPDATE_RAS_PREDICTION_IFETCH; DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h (revision 112) @@ -88,5 +88,7 @@ public : Tcontrol_t _ifetch_prediction; // not in ufpt + // to branchement_log_file public : bool _retire_ok ; + public : bool _miss_prediction ; }; @@ -115,5 +117,5 @@ #define pop_ras(cond) ((cond == BRANCH_CONDITION_READ_STACK )) -#define need_update(cond) update_ras(cond) +#define need_update(cond) (update_ras(cond) or update_dir(cond)) }; // end namespace update_prediction_table Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 112) @@ -130,4 +130,5 @@ public : SC_OUT(Tcontrol_t ) ** out_UPDATE_MISS_PREDICTION ; //[nb_inst_update] public : SC_OUT(Tcontrol_t ) ** out_UPDATE_DIRECTION_GOOD ; //[nb_inst_update] + public : SC_OUT(Tcontrol_t ) ** out_UPDATE_PREDICTION_IFETCH ; //[nb_inst_update] public : SC_OUT(Tcontrol_t ) ** out_UPDATE_BTB_VAL ; //[nb_inst_update] public : SC_OUT(Taddress_t ) ** out_UPDATE_BTB_ADDRESS_SRC ; //[nb_inst_update] @@ -141,5 +142,4 @@ public : SC_OUT(Taddress_t ) ** out_UPDATE_RAS_ADDRESS ; //[nb_inst_update] public : SC_OUT(Tptr_t ) ** out_UPDATE_RAS_INDEX ; //[nb_inst_update] - public : SC_OUT(Tcontrol_t ) ** out_UPDATE_RAS_PREDICTION_IFETCH ; //[nb_inst_update] // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -183,7 +183,8 @@ private : bool * reg_EVENT_VAL ; //[nb_context] private : uint32_t * reg_EVENT_UPT_PTR ; //[nb_context] + private : bool * reg_EVENT_UPT_FULL ; //[nb_context] private : event_state_t * reg_EVENT_STATE ; //[nb_context] - private : event_source_t * reg_EVENT_SOURCE ; //[nb_context] + private : bool * reg_EVENT_IS_BRANCH ; //[nb_context] private : Tdepth_t * reg_EVENT_DEPTH ; //[nb_context] private : Taddress_t * reg_EVENT_ADDRESS_SRC ; //[nb_context] // Address branch Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 112) @@ -48,5 +48,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -58,5 +58,5 @@ // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("predict", IN,SOUTH, "predict", _param->_nb_inst_predict); + ALLOC1_INTERFACE_BEGIN("predict", IN,SOUTH, _("predict"), _param->_nb_inst_predict); ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); @@ -72,9 +72,11 @@ ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_max_size_ras_index); + + ALLOC1_INTERFACE_END(_param->_nb_inst_predict); } // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("decod", IN,SOUTH, "decod", _param->_nb_inst_decod); + ALLOC1_INTERFACE_BEGIN("decod", IN,SOUTH, _("decod"), _param->_nb_inst_decod); ALLOC1_VALACK_IN ( in_DECOD_VAL ,VAL); @@ -93,9 +95,11 @@ ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_DECOD_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_decod); } // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("branch_complete", IN,SOUTH, "branch_complete", _param->_nb_inst_branch_complete); + ALLOC1_INTERFACE_BEGIN("branch_complete", IN,SOUTH, _("branch_complete"), _param->_nb_inst_branch_complete); ALLOC1_VALACK_IN ( in_BRANCH_COMPLETE_VAL ,VAL); @@ -109,9 +113,11 @@ // ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_instruction_address); // ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_instruction_address); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_complete); } // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("branch_event", IN,SOUTH, "branch_event", _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("branch_event", IN,SOUTH, _("branch_event"), _param->_nb_context); ALLOC1_VALACK_OUT(out_BRANCH_EVENT_VAL ,VAL); @@ -123,9 +129,11 @@ ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,"address_dest_val",Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_instruction_address); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("update",OUT,SOUTH, "update", _param->_nb_inst_update); + ALLOC1_INTERFACE_BEGIN("update",OUT,SOUTH, "update", _param->_nb_inst_update); ALLOC1_VALACK_OUT(out_UPDATE_VAL ,VAL); @@ -134,4 +142,5 @@ ALLOC1_SIGNAL_OUT(out_UPDATE_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_UPDATE_DIRECTION_GOOD ,"direction_good" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTION_IFETCH ,"prediction_ifetch" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_VAL ,"btb_val" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_instruction_address); @@ -145,10 +154,11 @@ ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_max_size_ras_index); - ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_PREDICTION_IFETCH,"ras_prediction_ifetch",Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_update); } // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("event", IN,SOUTH,"event", _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("event", IN,SOUTH,_("event"), _param->_nb_context); ALLOC1_VALACK_IN ( in_EVENT_VAL ,VAL); @@ -156,9 +166,12 @@ ALLOC1_SIGNAL_IN ( in_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH ,"depth",Tdepth_t ,_param->_size_depth ); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("depth",OUT,SOUTH, "depth", _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("depth",OUT,SOUTH, _("depth"), _param->_nb_context); + ALLOC1_SIGNAL_OUT(out_DEPTH_VAL ,"VAL" ,Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_DEPTH_CURRENT,"CURRENT",Tdepth_t ,_param->_size_depth); @@ -166,4 +179,6 @@ ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_OUT(out_DEPTH_FULL ,"FULL" ,Tcontrol_t,1); + + ALLOC1_INTERFACE_END(_param->_nb_context); } @@ -209,7 +224,8 @@ ALLOC1(reg_EVENT_VAL ,bool ,_param->_nb_context); ALLOC1(reg_EVENT_UPT_PTR ,uint32_t ,_param->_nb_context); + ALLOC1(reg_EVENT_UPT_FULL ,bool ,_param->_nb_context); ALLOC1(reg_EVENT_STATE ,event_state_t ,_param->_nb_context); - ALLOC1(reg_EVENT_SOURCE ,event_source_t,_param->_nb_context); + ALLOC1(reg_EVENT_IS_BRANCH ,bool ,_param->_nb_context); ALLOC1(reg_EVENT_DEPTH ,Tdepth_t ,_param->_nb_context); ALLOC1(reg_EVENT_ADDRESS_SRC ,Taddress_t ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 112) @@ -29,54 +29,46 @@ delete in_NRESET; - // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_PREDICT_VAL ; - delete [] out_PREDICT_ACK ; - if (_param->_have_port_context_id) - delete [] in_PREDICT_CONTEXT_ID ; - delete [] in_PREDICT_BTB_ADDRESS_SRC ; - delete [] in_PREDICT_BTB_ADDRESS_DEST ; - delete [] in_PREDICT_BTB_CONDITION ; - delete [] in_PREDICT_BTB_LAST_TAKE ; - delete [] in_PREDICT_BTB_IS_ACCURATE ; - if (_param->_have_port_history) - delete [] in_PREDICT_DIR_HISTORY ; - delete [] in_PREDICT_RAS_ADDRESS ; - delete [] in_PREDICT_RAS_INDEX ; - if (_param->_have_port_depth) - delete [] out_PREDICT_UPDATE_PREDICTION_ID; - - // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_DECOD_VAL ; - delete [] out_DECOD_ACK ; - if (_param->_have_port_context_id) - delete [] in_DECOD_CONTEXT_ID ; - delete [] in_DECOD_BTB_ADDRESS_SRC ; - delete [] in_DECOD_BTB_ADDRESS_DEST ; - delete [] in_DECOD_BTB_CONDITION ; - delete [] in_DECOD_BTB_LAST_TAKE ; - delete [] in_DECOD_RAS_ADDRESS ; - delete [] in_DECOD_RAS_INDEX ; - delete [] in_DECOD_MISS_IFETCH ; - delete [] in_DECOD_MISS_DECOD ; - if (_param->_have_port_depth) - delete [] in_DECOD_UPDATE_PREDICTION_ID ; -// if (_param->_have_port_depth) -// delete [] out_DECOD_DEPTH ; - delete [] in_DECOD_IS_ACCURATE ; - delete [] out_DECOD_CAN_CONTINUE ; - - // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_BRANCH_COMPLETE_VAL ; - delete [] out_BRANCH_COMPLETE_ACK ; - if (_param->_have_port_context_id) - delete [] in_BRANCH_COMPLETE_CONTEXT_ID ; - if (_param->_have_port_depth) - delete [] in_BRANCH_COMPLETE_DEPTH ; - delete [] in_BRANCH_COMPLETE_ADDRESS ; - delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ; - delete [] out_BRANCH_COMPLETE_MISS_PREDICTION; -// delete [] out_BRANCH_COMPLETE_TAKE ; -// delete [] out_BRANCH_COMPLETE_ADDRESS_SRC ; -// delete [] out_BRANCH_COMPLETE_ADDRESS_DEST ; + // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict,_param->_size_context_id); + DELETE1_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID,_param->_nb_inst_predict,_param->_size_depth); + DELETE1_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_predict,_param->_size_instruction_address); + DELETE1_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_predict,_param->_size_instruction_address); + DELETE1_SIGNAL( in_PREDICT_BTB_CONDITION ,_param->_nb_inst_predict,_param->_size_branch_condition); + DELETE1_SIGNAL( in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_BTB_IS_ACCURATE ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_DIR_HISTORY ,_param->_nb_inst_predict,_param->_size_history); + DELETE1_SIGNAL( in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict,_param->_size_instruction_address); + DELETE1_SIGNAL( in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict,_param->_max_size_ras_index); + + // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + DELETE1_SIGNAL( in_DECOD_VAL ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL(out_DECOD_ACK ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod,_param->_size_context_id); + DELETE1_SIGNAL( in_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_instruction_address); + DELETE1_SIGNAL( in_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_decod,_param->_size_instruction_address); + DELETE1_SIGNAL( in_DECOD_BTB_CONDITION ,_param->_nb_inst_decod,_param->_size_branch_condition); + DELETE1_SIGNAL( in_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_RAS_ADDRESS ,_param->_nb_inst_decod,_param->_size_instruction_address); + DELETE1_SIGNAL( in_DECOD_RAS_INDEX ,_param->_nb_inst_decod,_param->_max_size_ras_index); + DELETE1_SIGNAL( in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_MISS_DECOD ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID,_param->_nb_inst_decod,_param->_size_depth); +// DELETE1_SIGNAL(out_DECOD_DEPTH ,_param->_nb_inst_decod,_param->_size_depth); + DELETE1_SIGNAL( in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL(out_DECOD_CAN_CONTINUE ,_param->_nb_inst_decod,1); + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + DELETE1_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete,_param->_size_context_id); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1); +// DELETE1_SIGNAL(out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete,1); +// DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); +// DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -90,24 +82,22 @@ DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); - // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] out_UPDATE_VAL ; - delete [] in_UPDATE_ACK ; - if (_param->_have_port_context_id) - delete [] out_UPDATE_CONTEXT_ID ; - delete [] out_UPDATE_MISS_PREDICTION ; - delete [] out_UPDATE_DIRECTION_GOOD ; - delete [] out_UPDATE_BTB_VAL ; - delete [] out_UPDATE_BTB_ADDRESS_SRC ; - delete [] out_UPDATE_BTB_ADDRESS_DEST ; - delete [] out_UPDATE_BTB_CONDITION ; - delete [] out_UPDATE_DIR_VAL ; - if (_param->_have_port_history) - delete [] out_UPDATE_DIR_HISTORY ; - delete [] out_UPDATE_RAS_VAL ; - delete [] out_UPDATE_RAS_FLUSH ; - delete [] out_UPDATE_RAS_PUSH ; - delete [] out_UPDATE_RAS_ADDRESS ; - delete [] out_UPDATE_RAS_INDEX ; - delete [] out_UPDATE_RAS_PREDICTION_IFETCH; + // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + DELETE1_SIGNAL(out_UPDATE_VAL ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_ACK ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_CONTEXT_ID ,_param->_nb_inst_update,_param->_size_context_id); + DELETE1_SIGNAL(out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_PREDICTION_IFETCH ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_BTB_VAL ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update,_param->_size_instruction_address); + DELETE1_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_update,_param->_size_instruction_address); + DELETE1_SIGNAL(out_UPDATE_BTB_CONDITION ,_param->_nb_inst_update,_param->_size_branch_condition); + DELETE1_SIGNAL(out_UPDATE_DIR_VAL ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update,_param->_size_history); + DELETE1_SIGNAL(out_UPDATE_RAS_VAL ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_RAS_PUSH ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update,_param->_size_instruction_address); + DELETE1_SIGNAL(out_UPDATE_RAS_INDEX ,_param->_nb_inst_update,_param->_max_size_ras_index); // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -162,7 +152,8 @@ DELETE1(reg_EVENT_VAL ,_param->_nb_context); DELETE1(reg_EVENT_UPT_PTR ,_param->_nb_context); + DELETE1(reg_EVENT_UPT_FULL ,_param->_nb_context); DELETE1(reg_EVENT_STATE ,_param->_nb_context); - DELETE1(reg_EVENT_SOURCE ,_param->_nb_context); + DELETE1(reg_EVENT_IS_BRANCH ,_param->_nb_context); DELETE1(reg_EVENT_DEPTH ,_param->_nb_context); DELETE1(reg_EVENT_ADDRESS_SRC ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp (revision 112) @@ -98,4 +98,5 @@ Tcontrol_t miss_prediction ; Tcontrol_t direction_good ; + Tcontrol_t prediction_ifetch ; Tcontrol_t btb_val ; Taddress_t btb_address_src ; @@ -109,5 +110,4 @@ Taddress_t ras_address ; Tptr_t ras_index ; - Tcontrol_t ras_prediction_ifetch; // Test if update fetch prediction table need update port @@ -133,10 +133,11 @@ miss_prediction = 1; // direction_good = ; + prediction_ifetch = 1; btb_val = 0; // don't update btb (is update by the event branch) -// btb_address_src = ; -// btb_address_dest = ; -// btb_condition = ; - dir_val = 0; // don't update btb (is update by the event branch (if conditionnal branch)) -// dir_history = ; +// btb_address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ; +// btb_address_dest = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest; +// btb_condition = condition; + dir_val = update_ras(condition); + dir_history = reg_UPDATE_PREDICTION_TABLE [context][depth]._history; // repop/ repush data -> don't corrupt ras ras_val = update_ras(condition); @@ -145,5 +146,4 @@ ras_address = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._address_ras; ras_index = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._index_ras; - ras_prediction_ifetch = 1; internal_UPDATE_FROM_UFPT [i] = true; @@ -200,9 +200,11 @@ miss_prediction = (state != UPDATE_PREDICTION_STATE_OK); direction_good = reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take ; + prediction_ifetch = ifetch; btb_val = state_is_ok_ko and update_btb(condition); btb_address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ; btb_address_dest = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest; btb_condition = condition; - dir_val = state_is_ok_ko and update_dir(condition) and ifetch; // if not ifetch, then static prediction + dir_val = // state_is_ok_ko and + update_dir(condition); // if not ifetch, then static prediction dir_history = reg_UPDATE_PREDICTION_TABLE [context][depth]._history ; ras_val = update_ras(condition); // repop/ repush data -> don't corrupt ras @@ -213,5 +215,4 @@ ras_address = (ras_flush)?(reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src+2):reg_UPDATE_PREDICTION_TABLE [context][depth]._address_ras; ras_index = reg_UPDATE_PREDICTION_TABLE [context][depth]._index_ras; - ras_prediction_ifetch = ifetch; internal_UPDATE_FROM_UFPT [i] = false; @@ -257,4 +258,5 @@ PORT_WRITE(out_UPDATE_MISS_PREDICTION [i],miss_prediction ); PORT_WRITE(out_UPDATE_DIRECTION_GOOD [i],direction_good ); + PORT_WRITE(out_UPDATE_PREDICTION_IFETCH [i],prediction_ifetch ); PORT_WRITE(out_UPDATE_BTB_VAL [i],btb_val ); PORT_WRITE(out_UPDATE_BTB_ADDRESS_SRC [i],btb_address_src ); @@ -269,5 +271,4 @@ PORT_WRITE(out_UPDATE_RAS_ADDRESS [i],ras_address ); PORT_WRITE(out_UPDATE_RAS_INDEX [i],ras_index ); - PORT_WRITE(out_UPDATE_RAS_PREDICTION_IFETCH [i],ras_prediction_ifetch); } } @@ -290,4 +291,17 @@ } } + else + { + for (uint32_t i=0; i<_param->_nb_inst_update; i++) + { + internal_UPDATE_VAL [i] = 0; + internal_UPDATE_VAL_WITHOUT_ACK [i] = 0; + } + for (uint32_t i=0; i<_param->_nb_context; i++) + { + internal_BRANCH_EVENT_VAL [i] = 0; + } + } + log_end(Update_Prediction_Table,FUNCTION); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 112) @@ -53,4 +53,5 @@ reg_EVENT_VAL [i] = false; reg_EVENT_STATE [i] = EVENT_STATE_OK; + reg_EVENT_IS_BRANCH [i] = true; } } @@ -100,4 +101,8 @@ // Test if state is end // if (end_ok or end_ko) + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state is STATE_END : %d",end); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (before) : %d",reg_UPT_BOTTOM [i]); + if (end) { @@ -108,8 +113,12 @@ branchement_log_file [num_thread] << std::hex - << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src << " " - << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest << " " + << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src << " " + << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest << " " << std::dec - << reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take << " " + << reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take << " - " + << "[" << sc_simulation_time() << "] " << " " + << reg_UPDATE_PREDICTION_TABLE [i][bottom]._miss_prediction << " " + << reg_UPDATE_PREDICTION_TABLE [i][bottom]._ifetch_prediction << " " + << "(" << (uint32_t)reg_UPDATE_PREDICTION_TABLE [i][bottom]._condition << ")" << std::endl; } @@ -128,23 +137,38 @@ // if (bottom = reg_UPT_UPDATE [i]) // reg_UPT_UPDATE [i] = reg_UPT_BOTTOM [i]; - - if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom)) + }// @@@ + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (after ) : %d",reg_UPT_BOTTOM [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d",reg_EVENT_VAL [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d",reg_EVENT_UPT_PTR [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d",reg_EVENT_UPT_FULL[i]); + + if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom)) + { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * END EVENT"); + + if ((reg_EVENT_IS_BRANCH [i] == false) and (reg_EVENT_UPT_FULL [i] == false)) + reg_EVENT_STATE[i] = EVENT_STATE_OK; + + if ((reg_EVENT_IS_BRANCH [i] == true) or (reg_EVENT_UPT_FULL [i] == false)) { - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * END EVENT"); - - reg_EVENT_VAL [i] = false; - reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i]; - reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i]; - - if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i]) - reg_UPT_EMPTY [i] = false; - - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); + reg_EVENT_VAL [i] = false; +// reg_EVENT_IS_BRANCH [i] = true; + reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i]; + reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i]; + + if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i]) + reg_UPT_EMPTY [i] = false; } + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); + } + + if (end) + reg_EVENT_UPT_FULL [i] = false; } } @@ -245,4 +269,5 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context); reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; +// reg_EVENT_SOURCE[context] = EVENT_SOURCE_UFPT; } else @@ -251,9 +276,9 @@ reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT; } - reg_EVENT_SOURCE [context] = EVENT_SOURCE_UFPT; // Flush UPFT flush_UFPT [context] = true; + reg_EVENT_IS_BRANCH [context] = true; reg_EVENT_DEPTH [context] = upt_ptr_write; reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State @@ -357,5 +382,5 @@ (internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context])) { - Tdepth_t depth = internal_UPDATE_DEPTH [i]; + Tdepth_t depth = internal_UPDATE_DEPTH [i]; log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); @@ -369,13 +394,21 @@ // if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) if ((--reg_UFPT_NB_UPDATE [context])==0) - switch (reg_EVENT_STATE [context]) - { - case EVENT_STATE_MISS_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break; - // impossible to have an update on ufpt and reg_upt_update>reg_upt_top - case EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT ; break; - case EVENT_STATE_EVENT_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_OK ; break; - case EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: reg_EVENT_STATE [context] = EVENT_STATE_EVENT_FLUSH_UPT; break; - default : break; - } + { + switch (reg_EVENT_STATE [context]) + { + case EVENT_STATE_MISS_FLUSH_UFPT : + { + reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; +// reg_EVENT_SOURCE[context] = EVENT_SOURCE_UFPT; + + break; + } + // impossible to have an update on ufpt and reg_upt_update>reg_upt_top + case EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT ; break; + case EVENT_STATE_EVENT_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_OK ; break; + case EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: reg_EVENT_STATE [context] = EVENT_STATE_EVENT_FLUSH_UPT; break; + default : break; + } + } log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); @@ -405,5 +438,7 @@ { log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table"); - + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (before) : %d",reg_UPT_UPDATE [context]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str()); + // Change state #ifdef DEBUG_TEST @@ -430,5 +465,8 @@ if (ok or ko) - reg_UPDATE_PREDICTION_TABLE [context][depth]._retire_ok = true; + { + reg_UPDATE_PREDICTION_TABLE [context][depth]._retire_ok = true; + reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_prediction = ko; + } // Have an update, test the state to transiste to the good state @@ -444,6 +482,9 @@ reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO; - reg_EVENT_VAL [context] = true; - reg_EVENT_UPT_PTR [context] = depth; + reg_EVENT_VAL [context] = true; + reg_EVENT_UPT_PTR [context] = depth; +// reg_EVENT_UPT_FULL [context] = 0; +// reg_EVENT_UPT_FULL [i] = (not reg_UPT_EMPTY [i] and (bottom == reg_UPT_TOP [i])); + #ifdef STATISTICS @@ -473,13 +514,18 @@ // Update pointer // * if update RAS : update pointer is decreaste until it equal at top pointer + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * internal_UPDATE_RAS [%d] : %d",i,internal_UPDATE_RAS [i]); + if (internal_UPDATE_RAS [i]) { // if end_event, restart too bottom, else decrease pointer bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]); + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * end_event : %d",end_event); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",reg_UPT_BOTTOM[context]); - reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1); if (end_event) { -// reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context]; + reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1); +// reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context]; if (reg_EVENT_STATE [context] == EVENT_STATE_EVENT_FLUSH_UPT) @@ -488,5 +534,8 @@ } else - reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; + { + reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; +// reg_EVENT_SOURCE[context] = EVENT_SOURCE_UPT; + } } else @@ -497,4 +546,6 @@ else { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * next update"); + // increase pointer reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context]; @@ -502,6 +553,9 @@ // Free the branch with no accurate ? - if ( (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko) + if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko) reg_IS_ACCURATE [context] = true; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (after ) : %d",reg_UPT_UPDATE[context]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str()); } } @@ -513,5 +567,4 @@ reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context; } - // =================================================================== @@ -533,7 +586,8 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str()); if (miss) @@ -546,4 +600,7 @@ event_state_t event_state = reg_EVENT_STATE [context]; upt_state_t event_top = reg_UPDATE_PREDICTION_TABLE [context][top]._state; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * event_top : %s",toString(event_top).c_str()); + bool previous_ufpt_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or (event_state == EVENT_STATE_MISS_FLUSH_UFPT ) or @@ -551,14 +608,15 @@ (event_state == EVENT_STATE_EVENT_FLUSH_UFPT )); - bool previous_upt_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or - (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or - (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or - (event_state == EVENT_STATE_EVENT_FLUSH_UPT ) or - (event_top == UPDATE_PREDICTION_STATE_END_KO ) or - (event_top == UPDATE_PREDICTION_STATE_KO ) -// (event_state == EVENT_STATE_WAIT_END_EVENT ) or -// ((event_state == EVENT_STATE_UPDATE_CONTEXT ) and -// (reg_EVENT_SOURCE [context] == EVENT_SOURCE_UPT)) - ); + bool previous_upt_event = (false + or (event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) + or (event_state == EVENT_STATE_MISS_FLUSH_UPT ) + or (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) + or (event_state == EVENT_STATE_EVENT_FLUSH_UPT ) + or (event_top == UPDATE_PREDICTION_STATE_END_KO ) + or (event_top == UPDATE_PREDICTION_STATE_KO ) +// or (event_state == EVENT_STATE_WAIT_END_EVENT ) +// or ((event_state == EVENT_STATE_UPDATE_CONTEXT ) +// and (reg_EVENT_SOURCE [context] == EVENT_SOURCE_UPT)) + ); // bool update_ras = (new_update != depth); @@ -568,8 +626,9 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_upt_event : %d",previous_upt_event); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_ufpt_event : %d",previous_ufpt_event); - + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [context]); + // Have a miss !!! // Flush UPFT - flush_UFPT [context] = not previous_ufpt_event; + flush_UFPT [context] |= not previous_ufpt_event; if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END) @@ -587,5 +646,5 @@ reg_UPT_TOP [context] = depth; // reg_UPT_TOP_EVENT [context] = top; - + if (not previous_upt_event) { @@ -604,4 +663,5 @@ // Have already update predictor reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_END; + reg_UPT_UPDATE [context] = new_update; break; } @@ -649,8 +709,9 @@ } } - reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT; +// reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT; // else no update + reg_EVENT_IS_BRANCH [context] = true; reg_EVENT_DEPTH [context] = depth; reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State @@ -675,4 +736,6 @@ } + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str()); + // In all case : update good_take reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take; @@ -686,4 +749,5 @@ reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr; } + // =================================================================== @@ -779,67 +843,47 @@ // Flush UPT - Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_EVENT_DEPTH [i]):0; - uint32_t top = reg_UPT_TOP [i]; - uint32_t bottom = reg_UPT_BOTTOM [i]; - uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; -// bool empty = reg_UPT_EMPTY [i]; - + uint32_t bottom = reg_UPT_BOTTOM [i]; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",bottom); + +// event_state_t event_state = reg_EVENT_STATE [i]; +// bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or +// (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or +// (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or +// (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); + + bool find = false; // have slot to update ??? + Tdepth_t top = bottom; + Tdepth_t update = bottom; + bool empty = reg_UPT_EMPTY [i]; + + // flush all slot, because this event is in head of rob + for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j) + { + Tdepth_t x = (bottom+j)%_param->_size_upt_queue[i]; + + if ((reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_END) and + (reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY)) + { + find = true; // find a not empty slot + reg_UPDATE_PREDICTION_TABLE [i][x]._state = UPDATE_PREDICTION_STATE_EVENT; + reg_UPDATE_PREDICTION_TABLE [i][x]._retire_ok = false; + update = x; + } + + if (reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY) + top = x+1; + } + + top = top%_param->_size_upt_queue[i]; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); - - event_state_t event_state = reg_EVENT_STATE [i]; - bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or - (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or - (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or - (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); - - bool find = false; // have slot to update ??? - Tdepth_t depth_new = depth; - - // flush all slot after the event - for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; - j!=top; - j=(j+1)%_param->_size_upt_queue[i]) - if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and - (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)) - { - find = true; - reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; - reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok = false; - } - else - if (not find) // while state == end or empty - depth_new ++; - - if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and - (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY)) - { - find = true; - reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; - reg_UPDATE_PREDICTION_TABLE [i][depth]._retire_ok = false; - - } - else - // while state == end or empty - depth = (depth_new+1)%_param->_size_upt_queue[i]; - - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth_new : %d",depth_new); // Test if have update slot if (find) { -// // flush all slot after the event -// for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; -// j!=top; -// j=(j+1)%_param->_size_upt_queue[i]) -// reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; - -// reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; - - // reg_UPT_BOTTOM [i]; // TODO : special case : event is an exception on branch, also depth is not valid - reg_UPT_TOP [i] = depth; // depth is again valid + reg_UPT_TOP [i] = top; // depth is again valid reg_UPT_TOP_EVENT [i] = top; @@ -847,12 +891,5 @@ reg_UPT_EMPTY [i] = true; } - - bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); - bool update_ras = find and ((top != depth) or full); - - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); - - if (not previous_update_ras and update_ras) - reg_UPT_UPDATE [i] = new_update; + reg_UPT_UPDATE [i] = update; // new state : @@ -862,20 +899,36 @@ // * ok : nothing // * ko : flush upt - reg_EVENT_VAL [i] = true; - reg_EVENT_UPT_PTR [i] = depth; - + reg_EVENT_VAL [i] = find; + reg_EVENT_IS_BRANCH [i] = false; + reg_EVENT_UPT_PTR [i] = top; + reg_EVENT_UPT_FULL [i] = (not empty and (bottom == reg_UPT_TOP [i])); + reg_EVENT_DEPTH [i] = top; +// reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State +// reg_EVENT_ADDRESS_DEST_VAL[i] = good_take; +// reg_EVENT_ADDRESS_DEST [i] = good_addr; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d",reg_EVENT_VAL [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d",reg_EVENT_UPT_PTR [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d",reg_EVENT_UPT_FULL [i]); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); -// if (reg_UFPT_NB_NEED_UPDATE [i] > 0) + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]); + if ( (reg_UFPT_NB_NEED_UPDATE [i] > 0) or (reg_UFPT_NB_UPDATE [i] > 0)) { - if (update_ras) + if (find) { - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (branch_complete - miss)",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (event - find)",i); reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT; } else { - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (branch_complete - miss)",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (event - not find)",i); +// reg_EVENT_VAL [i] = false; + reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT; } @@ -883,9 +936,8 @@ else { -// if (not previous_update_ras) - if (update_ras) + if (find) { // have ras prediction ? - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (branch_complete - miss)",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (event - find)",i); reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT; @@ -894,5 +946,7 @@ { // special case : nothing - reg_EVENT_VAL [i] = false; + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (event - not find)",i); + +// reg_EVENT_VAL [i] = false; reg_EVENT_STATE [i] = EVENT_STATE_OK; @@ -902,8 +956,134 @@ // else no update - reg_EVENT_DEPTH [i] = depth; -// reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State -// reg_EVENT_ADDRESS_DEST_VAL[i] = good_take; -// reg_EVENT_ADDRESS_DEST [i] = good_addr; +// Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_EVENT_DEPTH [i]):0; +// uint32_t top = reg_UPT_TOP [i]; +// uint32_t bottom = reg_UPT_BOTTOM [i]; +// uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; +// // bool empty = reg_UPT_EMPTY [i]; + +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); + +// event_state_t event_state = reg_EVENT_STATE [i]; +// bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or +// (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or +// (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or +// (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); + +// bool find = false; // have slot to update ??? +// Tdepth_t depth_new = depth; + +// // flush all slot, because this event is in head of rob +// for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; +// //uint32_t j=bottom; +// j!=top; +// j=(j+1)%_param->_size_upt_queue[i]) +// if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and +// (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)) +// { +// find = true; +// reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; +// reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok = false; +// } +// else +// if (not find) // while state == end or empty +// depth_new ++; + +// if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and +// (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY)) +// { +// find = true; +// reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; +// reg_UPDATE_PREDICTION_TABLE [i][depth]._retire_ok = false; + +// } +// else +// // while state == end or empty +// depth = (depth_new+1)%_param->_size_upt_queue[i]; + +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find); +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth_new : %d",depth_new); + +// // Test if have update slot +// if (find) +// { +// // // flush all slot after the event +// // for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; +// // j!=top; +// // j=(j+1)%_param->_size_upt_queue[i]) +// // reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; + +// // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; + +// // reg_UPT_BOTTOM [i]; +// // TODO : special case : event is an exception on branch, also depth is not valid +// reg_UPT_TOP [i] = depth; // depth is again valid +// reg_UPT_TOP_EVENT [i] = top; + +// if (bottom == reg_UPT_TOP [i]) +// reg_UPT_EMPTY [i] = true; +// } + +// bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); +// bool update_ras = find and ((top != depth) or full); + +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); + +// if (not previous_update_ras and update_ras) +// reg_UPT_UPDATE [i] = new_update; + +// // new state : +// // * test if ufpt is empty +// // * ok : flush upft and upt +// // * ko : test if have previous flush upt +// // * ok : nothing +// // * ko : flush upt +// reg_EVENT_VAL [i] = update_ras; +// reg_EVENT_UPT_PTR [i] = depth; + +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); +// // if (reg_UFPT_NB_NEED_UPDATE [i] > 0) +// if ( (reg_UFPT_NB_NEED_UPDATE [i] > 0) or +// (reg_UFPT_NB_UPDATE [i] > 0)) +// { +// if (update_ras) +// { +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (branch_complete - miss)",i); +// reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT; +// } +// else +// { +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (branch_complete - miss)",i); +// // reg_EVENT_VAL [i] = false; + +// reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT; +// } +// } +// else +// { +// // if (not previous_update_ras) +// if (update_ras) +// { +// // have ras prediction ? +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (branch_complete - miss)",i); + +// reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT; +// } +// else +// { +// // special case : nothing +// // reg_EVENT_VAL [i] = false; + +// reg_EVENT_STATE [i] = EVENT_STATE_OK; +// } +// } + +// // else no update + +// reg_EVENT_DEPTH [i] = depth; +// // reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State +// // reg_EVENT_ADDRESS_DEST_VAL[i] = good_take; +// // reg_EVENT_ADDRESS_DEST [i] = good_addr; break; @@ -994,6 +1174,7 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d" ,reg_EVENT_VAL [i]); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d" ,reg_EVENT_UPT_FULL [i]); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_SOURCE : %s" ,toString(reg_EVENT_SOURCE[i]).c_str()); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_IS_BRANCH : %d" ,reg_EVENT_IS_BRANCH [i]); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp (revision 112) @@ -45,5 +45,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -56,5 +56,5 @@ { { - ALLOC1_INTERFACE("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("predict",IN,SOUTH,_("Interface with ifetch unit"),_param->_nb_context); ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); @@ -68,8 +68,13 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); + + ALLOC1_INTERFACE_END(_param->_nb_context); } { - ALLOC2_INTERFACE("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context,_param->_nb_instruction[it1]); + ALLOC2_INTERFACE_BEGIN("predict",IN,SOUTH,_("Interface with ifetch unit"),_param->_nb_context,_param->_nb_instruction[it1]); + _ALLOC2_SIGNAL_OUT(out_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1,_param->_nb_context,_param->_nb_instruction[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_context,_param->_nb_instruction[it1]); } } @@ -78,5 +83,5 @@ { { - ALLOC2_INTERFACE("decod",IN,SOUTH,"Interface with decod unit",_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_INTERFACE_BEGIN("decod",IN,SOUTH,_("Interface with decod unit"),_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); _ALLOC2_VALACK_IN ( in_DECOD_VAL ,VAL,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); @@ -91,4 +96,7 @@ _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_OUT(out_DECOD_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + + + ALLOC2_INTERFACE_END(_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); } } @@ -96,5 +104,5 @@ // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("branch_complete", IN,SOUTH, "branch_complete", _param->_nb_inst_branch_complete); + ALLOC1_INTERFACE_BEGIN("branch_complete", IN,SOUTH, _("branch_complete"), _param->_nb_inst_branch_complete); ALLOC1_VALACK_IN ( in_BRANCH_COMPLETE_VAL ,VAL); @@ -108,9 +116,11 @@ // ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_address); // ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_address); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_complete); } // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("branch_event", IN,SOUTH, "branch_event", _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("branch_event", IN,SOUTH, _("branch_event"), _param->_nb_context); ALLOC1_VALACK_OUT(out_BRANCH_EVENT_VAL ,VAL); @@ -122,9 +132,11 @@ ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,"address_dest_val",Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_address); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("depth",OUT,SOUTH,"Interface with depth",_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("depth",OUT,SOUTH,_("Interface with depth"),_param->_nb_context); ALLOC1_SIGNAL_OUT(out_DEPTH_VAL ,"val" ,Tcontrol_t,1); @@ -133,9 +145,11 @@ ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_OUT(out_DEPTH_FULL ,"full" ,Tcontrol_t,1); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("event", IN,SOUTH,"event", _param->_nb_context); + ALLOC1_INTERFACE_BEGIN("event", IN,SOUTH,_("event"), _param->_nb_context); ALLOC1_VALACK_IN ( in_EVENT_VAL ,VAL); @@ -143,4 +157,6 @@ ALLOC1_SIGNAL_IN ( in_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH ,"depth",Tdepth_t ,_param->_size_depth ); + + ALLOC1_INTERFACE_END(_param->_nb_context); } @@ -421,5 +437,6 @@ COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_DIRECTION", dest,"out_UPDATE_"+toString(i)+ "_DIRECTION_GOOD"); - + COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_PREDICTION_IFETCH", + dest,"out_UPDATE_"+toString(i)+ "_PREDICTION_IFETCH"); } } @@ -532,5 +549,5 @@ dest,"out_UPDATE_"+toString(i)+ "_MISS_PREDICTION" ); COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_PREDICTION_IFETCH", - dest,"out_UPDATE_"+toString(i)+"_RAS_PREDICTION_IFETCH"); + dest,"out_UPDATE_"+toString(i)+ "_PREDICTION_IFETCH"); } } @@ -656,5 +673,5 @@ //in_UPDATE_UPT_RAS_FLUSH - component_map return_address_stack //in_UPDATE_UPT_RAS_INDEX - component_map return_address_stack - //in_UPDATE_UPT_RAS_PREDICTION_IFETCH - component_map return_address_stack + //in_UPDATE_UPT_PREDICTION_IFETCH - component_map return_address_stack, direction } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 112) @@ -58,5 +58,5 @@ // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("icache_req",OUT, WEST, _("Instruction cache request."),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("icache_req",OUT, WEST, _("Instruction cache request."),_param->_nb_context); ALLOC1_VALACK_OUT (out_ICACHE_REQ_VAL ,VAL); @@ -66,9 +66,11 @@ ALLOC1_SIGNAL_OUT (out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_instruction_address ); ALLOC1_SIGNAL_OUT (out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type ); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_context); ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); @@ -77,15 +79,18 @@ ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ifetch_queue_ptr ); ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error ); - } - { - ALLOC2_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons.",_param->_nb_context,_param->_nb_inst_fetch[it1]); + + ALLOC1_INTERFACE_END(_param->_nb_context); + } + { + ALLOC2_INTERFACE_BEGIN("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_context,_param->_nb_inst_fetch[it1]); _ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction" ,Ticache_instruction_t,_param->_size_instruction ,_param->_nb_context,_param->_nb_inst_fetch[it1]); - } - + + ALLOC2_INTERFACE_END(_param->_nb_context,_param->_nb_inst_fetch[it1]); + } // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("decod",OUT,EAST,_("Decoded instruction, send to ooo_engine"),_param->_sum_inst_decod); + ALLOC1_INTERFACE_BEGIN("decod",OUT,EAST,_("Decoded instruction, send to ooo_engine"),_param->_sum_inst_decod); ALLOC1_VALACK_OUT (out_DECOD_VAL , VAL); @@ -115,9 +120,11 @@ ALLOC1_SIGNAL_OUT (out_DECOD_EXCEPTION_USE ,"EXCEPTION_USE" ,Texception_t ,_param->_size_exception_use ); ALLOC1_SIGNAL_OUT (out_DECOD_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ); + + ALLOC1_INTERFACE_END(_param->_sum_inst_decod); } // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("branch_complete",IN,EAST,_("Branch commit"),_param->_nb_inst_branch_complete); + ALLOC1_INTERFACE_BEGIN("branch_complete",IN,EAST,_("Branch commit"),_param->_nb_inst_branch_complete); ALLOC1_VALACK_IN ( in_BRANCH_COMPLETE_VAL , VAL); @@ -128,26 +135,30 @@ ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_MISS_PREDICTION ,"MISS_PREDICTION" ,Tcontrol_t ,1 ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_complete); } // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("commit_event",IN,EAST,_("Out Of Order engine have an event")); - - ALLOC_VALACK_IN ( in_COMMIT_EVENT_VAL , VAL); - ALLOC_VALACK_OUT (out_COMMIT_EVENT_ACK , ACK); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_TYPE ,"TYPE" ,Tevent_type_t ,_param->_size_event_type); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"ADDRESS_EPCR_VAL" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC0_INTERFACE_BEGIN("commit_event",IN,EAST,_("Out Of Order engine have an event")); + + ALLOC0_VALACK_IN ( in_COMMIT_EVENT_VAL , VAL); + ALLOC0_VALACK_OUT (out_COMMIT_EVENT_ACK , ACK); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_TYPE ,"TYPE" ,Tevent_type_t ,_param->_size_event_type); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"ADDRESS_EPCR_VAL" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data ); + + ALLOC0_INTERFACE_END(); } // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("event",OUT,EAST,_("Event interface"),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("event",OUT,EAST,_("Event interface"),_param->_nb_context); ALLOC1_VALACK_OUT (out_EVENT_VAL , VAL); @@ -157,9 +168,11 @@ ALLOC1_SIGNAL_OUT (out_EVENT_ADDRESS_NEXT_VAL ,"ADDRESS_NEXT_VAL" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT (out_EVENT_IS_DS_TAKE ,"IS_DS_TAKE" ,Tcontrol_t ,1 ); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("spr_event",OUT,EAST,_("Event interface with the special registerFile"),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("spr_event",OUT,EAST,_("Event interface with the special registerFile"),_param->_nb_context); ALLOC1_VALACK_OUT (out_SPR_EVENT_VAL , VAL); @@ -170,37 +183,47 @@ ALLOC1_SIGNAL_OUT (out_SPR_EVENT_SR_DSX ,"SR_DSX" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT (out_SPR_EVENT_SR_TO_ESR ,"SR_TO_ESR" ,Tcontrol_t ,1 ); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("nb_inst",IN,EAST,_("Instruction number"),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("nb_inst",IN,EAST,_("Instruction number"),_param->_nb_context); ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_ALL ,"COMMIT_ALL" ,Tcounter_t ,_param->_size_nb_inst_commit); ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_MEM ,"COMMIT_MEM" ,Tcounter_t ,_param->_size_nb_inst_commit); ALLOC1_SIGNAL_OUT (out_NB_INST_DECOD_ALL ,"DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod ); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("depth",OUT,EAST,_("Interface depth"),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("depth",OUT,EAST,_("Interface depth"),_param->_nb_context); ALLOC1_SIGNAL_OUT (out_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_OUT (out_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_OUT (out_DEPTH_FULL ,"FULL" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("spr",IN,EAST,_("Interface with the special registerFile"),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("spr",IN,EAST,_("Interface with the special registerFile"),_param->_nb_context); ALLOC1_SIGNAL_IN ( in_SPR_SR_IEE ,"SR_IEE" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_SPR_SR_EPH ,"SR_EPH" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_context); } // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("interrupt",IN,NORTH,_("Interrupt Exception"),_param->_nb_context); + ALLOC1_INTERFACE_BEGIN("interrupt",IN,NORTH,_("Interrupt Exception"),_param->_nb_context); ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE ,"ENABLE" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_context); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp (revision 112) @@ -76,15 +76,15 @@ DELETE1_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1 ); - DELETE_SIGNAL ( in_COMMIT_EVENT_VAL , 1); - DELETE_SIGNAL (out_COMMIT_EVENT_ACK , 1); - DELETE_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ,_param->_size_context_id); - DELETE_SIGNAL ( in_COMMIT_EVENT_DEPTH ,_param->_size_depth ); - DELETE_SIGNAL ( in_COMMIT_EVENT_TYPE ,_param->_size_event_type); - DELETE_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ,1 ); - DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS ,_param->_size_instruction_address ); - DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,1 ); - DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address ); - DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,1 ); - DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ,_param->_size_instruction_address ); + DELETE0_SIGNAL( in_COMMIT_EVENT_VAL , 1); + DELETE0_SIGNAL(out_COMMIT_EVENT_ACK , 1); + DELETE0_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ,_param->_size_context_id); + DELETE0_SIGNAL( in_COMMIT_EVENT_DEPTH ,_param->_size_depth ); + DELETE0_SIGNAL( in_COMMIT_EVENT_TYPE ,_param->_size_event_type); + DELETE0_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ,1 ); + DELETE0_SIGNAL( in_COMMIT_EVENT_ADDRESS ,_param->_size_instruction_address ); + DELETE0_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,1 ); + DELETE0_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address ); + DELETE0_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,1 ); + DELETE0_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ,_param->_size_instruction_address ); DELETE1_SIGNAL(out_EVENT_VAL ,_param->_nb_context, 1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp (revision 112) @@ -153,16 +153,16 @@ ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,"out_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete); - ALLOC_SC_SIGNAL (out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ); - ALLOC_SC_SIGNAL (out_UPDATE_FRONT_END_ID ,"out_UPDATE_FRONT_END_ID ",Tcontext_t ); - ALLOC_SC_SIGNAL (out_UPDATE_DEPTH ,"out_UPDATE_DEPTH ",Tdepth_t ); - ALLOC_SC_SIGNAL (out_UPDATE_TYPE ,"out_UPDATE_TYPE ",Tevent_type_t ); - ALLOC_SC_SIGNAL (out_UPDATE_IS_DELAY_SLOT ,"out_UPDATE_IS_DELAY_SLOT ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS ,"out_UPDATE_ADDRESS ",Taddress_t ); - ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR_VAL ,"out_UPDATE_ADDRESS_EPCR_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR ,"out_UPDATE_ADDRESS_EPCR ",Taddress_t ); - ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ,"out_UPDATE_ADDRESS_EEAR_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR ,"out_UPDATE_ADDRESS_EEAR ",Tgeneral_data_t ); + ALLOC0_SC_SIGNAL(out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL(out_UPDATE_FRONT_END_ID ,"out_UPDATE_FRONT_END_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL(out_UPDATE_DEPTH ,"out_UPDATE_DEPTH ",Tdepth_t ); + ALLOC0_SC_SIGNAL(out_UPDATE_TYPE ,"out_UPDATE_TYPE ",Tevent_type_t ); + ALLOC0_SC_SIGNAL(out_UPDATE_IS_DELAY_SLOT ,"out_UPDATE_IS_DELAY_SLOT ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS ,"out_UPDATE_ADDRESS ",Taddress_t ); + ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS_EPCR_VAL ,"out_UPDATE_ADDRESS_EPCR_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS_EPCR ,"out_UPDATE_ADDRESS_EPCR ",Taddress_t ); + ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS_EEAR_VAL ,"out_UPDATE_ADDRESS_EEAR_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS_EEAR ,"out_UPDATE_ADDRESS_EEAR ",Tgeneral_data_t ); ALLOC2_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); @@ -304,19 +304,19 @@ INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Commit_unit, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); - INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_VAL ); - INSTANCE_SC_SIGNAL (_Commit_unit, in_UPDATE_ACK ); + INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_VAL ); + INSTANCE0_SC_SIGNAL(_Commit_unit, in_UPDATE_ACK ); if (_param->_have_port_context_id) - INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_CONTEXT_ID ); + INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_CONTEXT_ID ); if (_param->_have_port_front_end_id) - INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_FRONT_END_ID ); + INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_FRONT_END_ID ); if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_DEPTH ); - INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_TYPE ); - INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_IS_DELAY_SLOT ); - INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS ); - INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EPCR_VAL ); - INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EPCR ); - INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EEAR_VAL ); - INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EEAR ); + INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_DEPTH ); + INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_TYPE ); + INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_IS_DELAY_SLOT ); + INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EPCR_VAL ); + INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EPCR ); + INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EEAR_VAL ); + INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EEAR ); INSTANCE2_SC_SIGNAL(_Commit_unit, in_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); @@ -708,16 +708,16 @@ DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); - DELETE_SC_SIGNAL (out_UPDATE_VAL ); - DELETE_SC_SIGNAL ( in_UPDATE_ACK ); - DELETE_SC_SIGNAL (out_UPDATE_CONTEXT_ID ); - DELETE_SC_SIGNAL (out_UPDATE_FRONT_END_ID ); - DELETE_SC_SIGNAL (out_UPDATE_DEPTH ); - DELETE_SC_SIGNAL (out_UPDATE_TYPE ); - DELETE_SC_SIGNAL (out_UPDATE_IS_DELAY_SLOT ); - DELETE_SC_SIGNAL (out_UPDATE_ADDRESS ); - DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR_VAL ); - DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR ); - DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ); - DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR ); + DELETE0_SC_SIGNAL(out_UPDATE_VAL ); + DELETE0_SC_SIGNAL( in_UPDATE_ACK ); + DELETE0_SC_SIGNAL(out_UPDATE_CONTEXT_ID ); + DELETE0_SC_SIGNAL(out_UPDATE_FRONT_END_ID ); + DELETE0_SC_SIGNAL(out_UPDATE_DEPTH ); + DELETE0_SC_SIGNAL(out_UPDATE_TYPE ); + DELETE0_SC_SIGNAL(out_UPDATE_IS_DELAY_SLOT ); + DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS ); + DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS_EPCR_VAL ); + DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS_EPCR ); + DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS_EEAR_VAL ); + DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS_EEAR ); DELETE2_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 112) @@ -238,4 +238,5 @@ private : Tevent_state_t ** reg_EVENT_STATE ;//[nb_front_end][nb_context] private : bool ** reg_EVENT_FLUSH ;//[nb_front_end][nb_context] + private : bool ** reg_EVENT_STOP ;//[nb_front_end][nb_context] //private : Taddress_t ** reg_PC_PREVIOUS ;//[nb_front_end][nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h (revision 112) @@ -35,5 +35,7 @@ ROB_STORE_HEAD_KO , // ROB_OTHER_WAIT_END , // - ROB_MISS_WAIT_END , // + + ROB_EVENT_WAIT_END , // + ROB_END_OK_SPECULATIVE , // ROB_END_OK , // @@ -49,4 +51,5 @@ ROB_END_EXCEPTION_UPDATE , // ROB_END_EXCEPTION // + } rob_state_t; @@ -121,5 +124,5 @@ case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO : return "ROB_STORE_HEAD_KO" ; break; case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END : return "ROB_OTHER_WAIT_END" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_MISS_WAIT_END : return "ROB_MISS_WAIT_END" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EVENT_WAIT_END : return "ROB_EVENT_WAIT_END" ; break; case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK_SPECULATIVE : return "ROB_END_OK_SPECULATIVE" ; break; case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK : return "ROB_END_OK" ; break; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp (revision 112) @@ -118,13 +118,13 @@ # ifdef SYSTEMCASS_SPECIFIC // List dependency information - for (uint32_t i=0; i<_param->_nb_rename_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) - for (uint32_t x=0; x<_param->_nb_rename_unit; x++) - for (uint32_t y=0; y<_param->_nb_inst_insert[x]; y++) - { - (*(out_INSERT_ACK [i][j])) (*(in_INSERT_VAL [x][y])); - if (_param->_have_port_rob_ptr) - (*(out_INSERT_PACKET_ID [i][j])) (*(in_INSERT_VAL [x][y])); - } +// for (uint32_t i=0; i<_param->_nb_rename_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) +// for (uint32_t x=0; x<_param->_nb_rename_unit; x++) +// for (uint32_t y=0; y<_param->_nb_inst_insert[x]; y++) +// { +// (*(out_INSERT_ACK [i][j])) (*(in_INSERT_VAL [x][y])); +// if (_param->_have_port_rob_ptr) +// (*(out_INSERT_PACKET_ID [i][j])) (*(in_INSERT_VAL [x][y])); +// } # endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 112) @@ -58,5 +58,5 @@ // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("insert", IN, SOUTH, _("Interface with rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_INTERFACE_BEGIN("insert", IN, SOUTH, _("Interface with rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); _ALLOC2_VALACK_IN ( in_INSERT_VAL ,VAL,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); @@ -96,9 +96,11 @@ _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); } // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("retire",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_INTERFACE_BEGIN("retire",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); _ALLOC2_VALACK_OUT(out_RETIRE_VAL ,VAL,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); @@ -125,18 +127,22 @@ _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); } // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("retire_event",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("retire_event",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_VAL ,VAL,_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_ACK ,ACK,_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state ,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); } // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("commit",IN,EAST,_("End of execute."),_param->_nb_inst_commit); + ALLOC1_INTERFACE_BEGIN("commit",IN,EAST,_("End of execute."),_param->_nb_inst_commit); ALLOC1_VALACK_IN ( in_COMMIT_VAL ,VAL); @@ -152,9 +158,11 @@ // ALLOC1_SIGNAL_OUT(out_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register+_param->_size_rename_unit_id); ALLOC1_SIGNAL_OUT(out_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); + + ALLOC1_INTERFACE_END(_param->_nb_inst_commit); } // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("reexecute",OUT,EAST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_reexecute); + ALLOC1_INTERFACE_BEGIN("reexecute",OUT,EAST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_reexecute); ALLOC1_VALACK_OUT(out_REEXECUTE_VAL ,VAL); @@ -166,9 +174,11 @@ ALLOC1_SIGNAL_OUT(out_REEXECUTE_TYPE ,"type" ,Ttype_t ,_param->_size_type); ALLOC1_SIGNAL_OUT(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); + + ALLOC1_INTERFACE_END(_param->_nb_inst_reexecute); } // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("branch_complete",OUT,WEST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_branch_complete); + ALLOC1_INTERFACE_BEGIN("branch_complete",OUT,WEST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_branch_complete); ALLOC1_VALACK_OUT(out_BRANCH_COMPLETE_VAL ,VAL); @@ -181,27 +191,31 @@ ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_complete); } // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("update", OUT, WEST,_("Interface with to Context State.")); - - ALLOC_VALACK_OUT(out_UPDATE_VAL ,VAL); - ALLOC_VALACK_IN ( in_UPDATE_ACK ,ACK); - ALLOC_SIGNAL_OUT(out_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC_SIGNAL_OUT(out_UPDATE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); - ALLOC_SIGNAL_OUT(out_UPDATE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); - ALLOC_SIGNAL_OUT(out_UPDATE_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type); - ALLOC_SIGNAL_OUT(out_UPDATE_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); - ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); - ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR_VAL ,"address_epcr_val",Tcontrol_t ,1); - ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); - ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); - ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR ,"address_eear" ,Tgeneral_data_t ,_param->_size_general_data); + ALLOC0_INTERFACE_BEGIN("update", OUT, WEST,_("Interface with to Context State.")); + + ALLOC0_VALACK_OUT(out_UPDATE_VAL ,VAL); + ALLOC0_VALACK_IN ( in_UPDATE_ACK ,ACK); + ALLOC0_SIGNAL_OUT(out_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC0_SIGNAL_OUT(out_UPDATE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); + ALLOC0_SIGNAL_OUT(out_UPDATE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); + ALLOC0_SIGNAL_OUT(out_UPDATE_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type); + ALLOC0_SIGNAL_OUT(out_UPDATE_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); + ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR_VAL ,"address_epcr_val",Tcontrol_t ,1); + ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); + ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); + ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR ,"address_eear" ,Tgeneral_data_t ,_param->_size_general_data); + + ALLOC0_INTERFACE_END(); } // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("event",IN,WEST,_("Interface with Context State (event)."),_param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("event",IN,WEST,_("Interface with Context State (event)."),_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_VALACK_IN ( in_EVENT_VAL , VAL ,_param->_nb_front_end, _param->_nb_context[it1]); @@ -211,22 +225,28 @@ _ALLOC2_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"ADDRESS_NEXT_VAL",Tcontrol_t,1 ,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"IS_DS_TAKE" ,Tcontrol_t,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("nb_inst",OUT,WEST,_("Interface with Context State (synchronization)."),_param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("nb_inst",OUT,WEST,_("Interface with Context State (synchronization)."),_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_ALL ,"commit_all",Tcounter_t ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_MEM ,"commit_mem",Tcounter_t ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_NB_INST_DECOD_ALL ,"decod_all" ,Tcounter_t ,_param->_size_nb_inst_decod ,_param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL ,"full" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } @@ -234,12 +254,14 @@ // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("spr_read",IN ,EAST,_("Interface with special register file (read)."),_param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("spr_read",IN ,EAST,_("Interface with special register file (read)."),_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_SPR_READ_SR_OVE ,"sr_ove" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("spr_write",OUT,EAST,_("Interface with special register file (write)."),_param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("spr_write",OUT,EAST,_("Interface with special register file (write)."),_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_VALACK_OUT(out_SPR_WRITE_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); @@ -251,4 +273,6 @@ _ALLOC2_SIGNAL_OUT(out_SPR_WRITE_SR_OV_VAL ,"sr_ov_val" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_OUT(out_SPR_WRITE_SR_OV ,"sr_ov" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } @@ -289,4 +313,5 @@ ALLOC2(reg_EVENT_STATE ,Tevent_state_t,_param->_nb_front_end,_param->_nb_context [it1]); ALLOC2(reg_EVENT_FLUSH ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); + ALLOC2(reg_EVENT_STOP ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); // ALLOC2(reg_PC_PREVIOUS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 112) @@ -124,16 +124,16 @@ DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1); - DELETE_SIGNAL (out_UPDATE_VAL ,1 ); - DELETE_SIGNAL ( in_UPDATE_ACK ,1 ); - DELETE_SIGNAL (out_UPDATE_CONTEXT_ID ,_param->_size_context_id ); - DELETE_SIGNAL (out_UPDATE_FRONT_END_ID ,_param->_size_front_end_id); - DELETE_SIGNAL (out_UPDATE_DEPTH ,_param->_size_depth ); - DELETE_SIGNAL (out_UPDATE_TYPE ,_param->_size_event_type ); - DELETE_SIGNAL (out_UPDATE_IS_DELAY_SLOT ,1 ); - DELETE_SIGNAL (out_UPDATE_ADDRESS ,_param->_size_instruction_address ); - DELETE_SIGNAL (out_UPDATE_ADDRESS_EPCR_VAL ,1 ); - DELETE_SIGNAL (out_UPDATE_ADDRESS_EPCR ,_param->_size_instruction_address ); - DELETE_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ,1 ); - DELETE_SIGNAL (out_UPDATE_ADDRESS_EEAR ,_param->_size_instruction_address ); + DELETE0_SIGNAL(out_UPDATE_VAL ,1 ); + DELETE0_SIGNAL( in_UPDATE_ACK ,1 ); + DELETE0_SIGNAL(out_UPDATE_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL(out_UPDATE_FRONT_END_ID ,_param->_size_front_end_id); + DELETE0_SIGNAL(out_UPDATE_DEPTH ,_param->_size_depth ); + DELETE0_SIGNAL(out_UPDATE_TYPE ,_param->_size_event_type ); + DELETE0_SIGNAL(out_UPDATE_IS_DELAY_SLOT ,1 ); + DELETE0_SIGNAL(out_UPDATE_ADDRESS ,_param->_size_instruction_address ); + DELETE0_SIGNAL(out_UPDATE_ADDRESS_EPCR_VAL ,1 ); + DELETE0_SIGNAL(out_UPDATE_ADDRESS_EPCR ,_param->_size_instruction_address ); + DELETE0_SIGNAL(out_UPDATE_ADDRESS_EEAR_VAL ,1 ); + DELETE0_SIGNAL(out_UPDATE_ADDRESS_EEAR ,_param->_size_instruction_address ); DELETE2_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1 ); @@ -194,4 +194,5 @@ DELETE2(reg_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context [it1]); DELETE2(reg_EVENT_FLUSH ,_param->_nb_front_end,_param->_nb_context [it1]); + DELETE2(reg_EVENT_STOP ,_param->_nb_front_end,_param->_nb_context [it1]); // DELETE2(reg_PC_PREVIOUS ,_param->_nb_front_end,_param->_nb_context [it1]); DELETE2(reg_PC_CURRENT ,_param->_nb_front_end,_param->_nb_context [it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp (revision 112) @@ -30,6 +30,11 @@ #endif bool can_rename_select [_param->_nb_rename_unit]; - - // Initialisation + bool event_stop; + +// Initialisation + event_stop = false; // one signal for all context. + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + event_stop |= reg_EVENT_STOP [i][j]; for (uint32_t i=0; i<_param->_nb_bank; i++) { @@ -52,64 +57,67 @@ // log_printf(TRACE,Commit_unit,FUNCTION," * reg_NUM_BANK_TAIL : %d",reg_NUM_BANK_TAIL); - std::list * select_insert = _priority_insert ->select(); // same select for all insert - std::list::iterator it=select_insert ->begin(); - - // Scan all bank ... - for (uint32_t i=0; i<_param->_nb_bank; i++) + if (not event_stop) { - // compute the bank number (num_bank_tail is the older write slot) - uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank; - -// log_printf(TRACE,Commit_unit,FUNCTION," * BANK : %d", num_bank); -// log_printf(TRACE,Commit_unit,FUNCTION," * val : %d", internal_BANK_INSERT_VAL [num_bank]); -// log_printf(TRACE,Commit_unit,FUNCTION," * full : %d", bank_full [num_bank]); - - // Scan all insert interface to find a valid transaction - while (it!=select_insert ->end()) - { - uint32_t num_rename_unit = it->grp; - uint32_t num_inst_insert = it->elt; - - it++; - - log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]", num_rename_unit,num_inst_insert); -// log_printf(TRACE,Commit_unit,FUNCTION," * INSERT_VAL : %d", PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert])); - log_printf(TRACE,Commit_unit,FUNCTION," * can_rename_select : %d", can_rename_select [num_rename_unit]); - - // Test if have instruction - // -> rename_unit_glue test the in-order insert !!!!! - if (can_rename_select [num_rename_unit] // and -// PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert]) - ) - { - log_printf(TRACE,Commit_unit,FUNCTION," * have instruction"); - log_printf(TRACE,Commit_unit,FUNCTION," * bank_full : %d",bank_full [num_bank]); - - // test if bank is not busy (full or previous access) - if (not bank_full [num_bank]) - { - // find !!! - insert_ack [num_rename_unit][num_inst_insert] = true; - - Tpacket_t packet_id = ((num_bank << _param->_shift_num_bank) | reg_BANK_PTR [num_bank]); - + std::list * select_insert = _priority_insert ->select(); // same select for all insert + std::list::iterator it=select_insert ->begin(); + + // Scan all bank ... + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + // compute the bank number (num_bank_tail is the older write slot) + uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank; + +// log_printf(TRACE,Commit_unit,FUNCTION," * BANK : %d", num_bank); +// log_printf(TRACE,Commit_unit,FUNCTION," * val : %d", internal_BANK_INSERT_VAL [num_bank]); +// log_printf(TRACE,Commit_unit,FUNCTION," * full : %d", bank_full [num_bank]); + + // Scan all insert interface to find a valid transaction + while (it!=select_insert ->end()) + { + uint32_t num_rename_unit = it->grp; + uint32_t num_inst_insert = it->elt; + + it++; + + log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]", num_rename_unit,num_inst_insert); +// log_printf(TRACE,Commit_unit,FUNCTION," * INSERT_VAL : %d", PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert])); + log_printf(TRACE,Commit_unit,FUNCTION," * can_rename_select : %d", can_rename_select [num_rename_unit]); + + // Test if have instruction + // -> rename_unit_glue test the in-order insert !!!!! + if (can_rename_select [num_rename_unit] // and +// PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert]) + ) + { + log_printf(TRACE,Commit_unit,FUNCTION," * have instruction"); + log_printf(TRACE,Commit_unit,FUNCTION," * bank_full : %d",bank_full [num_bank]); + + // test if bank is not busy (full or previous access) + if (not bank_full [num_bank]) + { + // find !!! + insert_ack [num_rename_unit][num_inst_insert] = true; + + Tpacket_t packet_id = ((num_bank << _param->_shift_num_bank) | reg_BANK_PTR [num_bank]); + #ifdef SYSTEMC_VHDL_COMPATIBILITY - insert_packet_id [num_rename_unit][num_inst_insert] = packet_id; + insert_packet_id [num_rename_unit][num_inst_insert] = packet_id; #else - if (_param->_have_port_rob_ptr ) - PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id); + if (_param->_have_port_rob_ptr ) + PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id); #endif - internal_BANK_INSERT_VAL [num_bank] = true; - internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit; - internal_BANK_INSERT_NUM_INST [num_bank] = num_inst_insert; - - break; - } - } + internal_BANK_INSERT_VAL [num_bank] = true; + internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit; + internal_BANK_INSERT_NUM_INST [num_bank] = num_inst_insert; + + break; + } + } - // is a valid instruction, but it's not send at a bank - // ... invalid this rename_unit (because, insert in_order) - can_rename_select [num_rename_unit] = false; - } + // is a valid instruction, but it's not send at a bank + // ... invalid this rename_unit (because, insert in_order) + can_rename_select [num_rename_unit] = false; + } + } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp (revision 112) @@ -76,102 +76,101 @@ PORT_READ(in_RETIRE_ACK [x][y])) // not busy { - rob_state_t state = entry->state; - - if ((state == ROB_END_OK ) or - (state == ROB_END_KO ) or - (state == ROB_END_BRANCH_MISS) or - (state == ROB_END_LOAD_MISS ) or - (state == ROB_END_MISS )// or -// (state == ROB_END_EXCEPTION) - ) - { - Tcontext_t front_end_id = entry->front_end_id; - Tcontext_t context_id = entry->context_id; - Tcontrol_t write_re = entry->write_re; - Tspecial_address_t num_reg_re_log = entry->num_reg_re_log; - - // if state is ok, when write flags in the SR regsiters - bool spr_write_ack = true; - - // Write in SR the good flag - if ((state == ROB_END_OK ) and write_re) - // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE - { - spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]); - - // retire_ack is set !!! - spr_write_val [front_end_id][context_id] = 1; - - Tspecial_data_t flags = entry->flags; - - switch (num_reg_re_log) - { - case SPR_LOGIC_SR_F : - { - spr_write_sr_f_val [front_end_id][context_id] = 1; - spr_write_sr_f [front_end_id][context_id] = (flags & FLAG_F )!=0; - - break; - } - case SPR_LOGIC_SR_CY_OV : - { - spr_write_sr_cy_val [front_end_id][context_id] = 1; - spr_write_sr_ov_val [front_end_id][context_id] = 1; - spr_write_sr_cy [front_end_id][context_id] = (flags & FLAG_CY)!=0; - spr_write_sr_ov [front_end_id][context_id] = (flags & FLAG_OV)!=0; - - break; - } - default : - { + rob_state_t state = entry->state; + if ((state == ROB_END_OK ) or + (state == ROB_END_KO ) or + (state == ROB_END_BRANCH_MISS) or + (state == ROB_END_LOAD_MISS ) or + (state == ROB_END_MISS )// or +// (state == ROB_END_EXCEPTION) + ) + { + Tcontrol_t write_re = entry->write_re; + Tspecial_address_t num_reg_re_log = entry->num_reg_re_log; + Tcontext_t front_end_id = entry->front_end_id; + Tcontext_t context_id = entry->context_id; + + // if state is ok, when write flags in the SR regsiters + bool spr_write_ack = true; + + // Write in SR the good flag + if ((state == ROB_END_OK ) and write_re) + // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE + { + spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]); + + // retire_ack is set !!! + spr_write_val [front_end_id][context_id] = 1; + + Tspecial_data_t flags = entry->flags; + + switch (num_reg_re_log) + { + case SPR_LOGIC_SR_F : + { + spr_write_sr_f_val [front_end_id][context_id] = 1; + spr_write_sr_f [front_end_id][context_id] = (flags & FLAG_F )!=0; + + break; + } + case SPR_LOGIC_SR_CY_OV : + { + spr_write_sr_cy_val [front_end_id][context_id] = 1; + spr_write_sr_ov_val [front_end_id][context_id] = 1; + spr_write_sr_cy [front_end_id][context_id] = (flags & FLAG_CY)!=0; + spr_write_sr_ov [front_end_id][context_id] = (flags & FLAG_OV)!=0; + + break; + } + default : + { #ifdef DEBUG_TEST - throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n")); + throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n")); #endif - } - } - } - - // find an instruction can be retire, and in order - - if (spr_write_ack) - { - retire_val [x][y] = 1; - num_inst_retire [x] ++; - internal_BANK_RETIRE_VAL [num_bank] = true; - } - - internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x; - internal_BANK_RETIRE_NUM_INST [num_bank] = y; - - if (_param->_have_port_front_end_id) - PORT_WRITE(out_RETIRE_FRONT_END_ID [x][y], front_end_id ); - if (_param->_have_port_context_id) - PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id ); -// PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id ); - PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue ); - PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue ); - PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write); - if (_param->_have_port_load_queue_ptr) - PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE [x][y], entry->load_queue_ptr_write ); - PORT_WRITE(out_RETIRE_READ_RA [x][y], entry->read_ra ); - PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY [x][y], entry->num_reg_ra_phy ); - PORT_WRITE(out_RETIRE_READ_RB [x][y], entry->read_rb ); - PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY [x][y], entry->num_reg_rb_phy ); - PORT_WRITE(out_RETIRE_READ_RC [x][y], entry->read_rc ); - PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY [x][y], entry->num_reg_rc_phy ); - PORT_WRITE(out_RETIRE_WRITE_RD [x][y], entry->write_rd ); - PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG [x][y], entry->num_reg_rd_log ); - PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD [x][y], entry->num_reg_rd_phy_old ); - PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW [x][y], entry->num_reg_rd_phy_new ); - PORT_WRITE(out_RETIRE_WRITE_RE [x][y], write_re ); - PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG [x][y], num_reg_re_log ); - PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD [x][y], entry->num_reg_re_phy_old ); - PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW [x][y], entry->num_reg_re_phy_new ); - - // Event -> rob must be manage this event - if ((state == ROB_END_BRANCH_MISS) or - (state == ROB_END_LOAD_MISS)) - can_retire [x] = false; - } + } + } + } + + // find an instruction can be retire, and in order + + if (spr_write_ack) + { + retire_val [x][y] = 1; + num_inst_retire [x] ++; + internal_BANK_RETIRE_VAL [num_bank] = true; + } + + internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x; + internal_BANK_RETIRE_NUM_INST [num_bank] = y; + + if (_param->_have_port_front_end_id) + PORT_WRITE(out_RETIRE_FRONT_END_ID [x][y], front_end_id ); + if (_param->_have_port_context_id) + PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id ); +// PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id ); + PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue ); + PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue ); + PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write); + if (_param->_have_port_load_queue_ptr) + PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE [x][y], entry->load_queue_ptr_write ); + PORT_WRITE(out_RETIRE_READ_RA [x][y], entry->read_ra ); + PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY [x][y], entry->num_reg_ra_phy ); + PORT_WRITE(out_RETIRE_READ_RB [x][y], entry->read_rb ); + PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY [x][y], entry->num_reg_rb_phy ); + PORT_WRITE(out_RETIRE_READ_RC [x][y], entry->read_rc ); + PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY [x][y], entry->num_reg_rc_phy ); + PORT_WRITE(out_RETIRE_WRITE_RD [x][y], entry->write_rd ); + PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG [x][y], entry->num_reg_rd_log ); + PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD [x][y], entry->num_reg_rd_phy_old ); + PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW [x][y], entry->num_reg_rd_phy_new ); + PORT_WRITE(out_RETIRE_WRITE_RE [x][y], write_re ); + PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG [x][y], num_reg_re_log ); + PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD [x][y], entry->num_reg_re_phy_old ); + PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW [x][y], entry->num_reg_re_phy_new ); + + // Event -> rob must be manage this event + if ((state == ROB_END_BRANCH_MISS) or + (state == ROB_END_LOAD_MISS)) + can_retire [x] = false; + } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 112) @@ -49,4 +49,5 @@ reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; reg_EVENT_FLUSH [i][j] = false; + reg_EVENT_STOP [i][j] = false; // reg_PC_PREVIOUS [i][j] = (0x100-4)>>2; @@ -90,4 +91,5 @@ reg_EVENT_STATE [i][j] = EVENT_STATE_END; reg_EVENT_FLUSH [i][j] = false; + //reg_EVENT_STOP [i][j] = false; } break; @@ -324,5 +326,5 @@ case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;} // Store KO - case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} + case ROB_EVENT_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} // Store OK, Load and other instruction case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_LOAD_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE); break;} @@ -333,4 +335,8 @@ } } + + if ((have_exception or have_miss_speculation) and + (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0)) + reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; // update Re Order Buffer @@ -364,4 +370,5 @@ log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); + log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",num_bank ); #ifdef DEBUG_TEST @@ -381,4 +388,5 @@ log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id ); log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); + log_printf(TRACE,Commit_unit,FUNCTION," * rob_ptr : %d",((num_bank << _param->_shift_num_bank) | entry->ptr)); log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread ); log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); @@ -406,11 +414,12 @@ // throw ERRORMORPHEO(FUNCTION,toString(_("Retire : Instruction's address_next (%.8x) is different of commit_unit's address_next (%.8x)"),entry->address_next,reg_PC_NEXT [front_end_id][context_id])); } - + if ((state == ROB_END_BRANCH_MISS) or (state == ROB_END_LOAD_MISS)) - { - reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; - reg_EVENT_FLUSH [front_end_id][context_id] = true; - } + { + reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; + reg_EVENT_FLUSH [front_end_id][context_id] = true; + reg_EVENT_STOP [front_end_id][context_id] = false; + } #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true) @@ -475,5 +484,5 @@ { case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; } - case ROB_STORE_HEAD_KO : {state = ROB_MISS_WAIT_END ; break; } + case ROB_STORE_HEAD_KO : {state = ROB_EVENT_WAIT_END; break; } default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));} } @@ -500,6 +509,12 @@ throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n")); #endif - - entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE; + Tcontrol_t miss = PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]); + + entry->state = (miss)?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE; + + if (miss and (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0)) + reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; + + // entry->state = ROB_END_OK_SPECULATIVE; } @@ -612,25 +627,25 @@ switch (state) { - case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} - case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} + case ROB_BRANCH_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} + case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} case ROB_END_BRANCH_MISS : - case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} + case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} case ROB_END_LOAD_MISS_UPDATE : case ROB_END_LOAD_MISS : - case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} - case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} + case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} + case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO ; break;} //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} - case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} + case ROB_OTHER_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} case ROB_END_OK : - case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} + case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} case ROB_END_KO : - case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} + case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} case ROB_END_EXCEPTION_UPDATE : case ROB_END_EXCEPTION : - case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} + case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} // don't change case ROB_STORE_HEAD_KO : {break;} - case ROB_MISS_WAIT_END : {break;} + case ROB_EVENT_WAIT_END : {break;} case ROB_END_MISS : {break;} @@ -671,5 +686,5 @@ case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} - default : {break;} // else, no change + default : {break;} // else, no change } } @@ -701,4 +716,5 @@ log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s",toString(reg_EVENT_STATE [i][j]).c_str()); log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]); + log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STOP : %d",reg_EVENT_STOP [i][j]); log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : %d",reg_NB_INST_COMMIT_ALL[i][j]); log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_MEM : %d",reg_NB_INST_COMMIT_MEM[i][j]); @@ -784,5 +800,5 @@ // or (entry->state == ROB_STORE_HEAD_KO ) // or (entry->state == ROB_OTHER_WAIT_END ) -// or (entry->state == ROB_MISS_WAIT_END ) +// or (entry->state == ROB_EVENT_WAIT_END ) // or (entry->state == ROB_END_OK_SPECULATIVE ) or (entry->state == ROB_END_OK ) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp (revision 112) @@ -59,5 +59,5 @@ // ~~~~~[ Interface : "issue_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("issue_in", IN, WEST, _("Rename_out / Insert Rob interface"),_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + ALLOC2_INTERFACE_BEGIN("issue_in", IN, WEST, _("Rename_out / Insert Rob interface"),_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); _ALLOC2_VALACK_IN ( in_ISSUE_IN_VAL ,VAL,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); @@ -82,9 +82,11 @@ _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); } // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("reexecute", IN, NORTH, _("Instruction reexecute (store head/ spr access)"),_param->_nb_inst_reexecute); + ALLOC1_INTERFACE_BEGIN("reexecute", IN, NORTH, _("Instruction reexecute (store head/ spr access)"),_param->_nb_inst_reexecute); ALLOC1_VALACK_IN ( in_REEXECUTE_VAL ,VAL); @@ -109,9 +111,11 @@ ALLOC1_SIGNAL_IN ( in_REEXECUTE_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_REEXECUTE_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); + + ALLOC1_INTERFACE_END(_param->_nb_inst_reexecute); } // ~~~~~[ Interface : "issue_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("issue_out",OUT, EAST, _("Go to issue network"),_param->_nb_inst_issue); + ALLOC1_INTERFACE_BEGIN("issue_out",OUT, EAST, _("Go to issue network"),_param->_nb_inst_issue); ALLOC1_VALACK_OUT(out_ISSUE_OUT_VAL ,VAL); @@ -136,4 +140,6 @@ ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); + + ALLOC1_INTERFACE_END(_param->_nb_inst_issue); } @@ -141,5 +147,5 @@ { // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - _issue_queue = new std::list [_param->_nb_bank]; + ALLOC1(_issue_queue ,std::list,_param->_nb_bank); // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp (revision 112) @@ -95,5 +95,5 @@ // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] _issue_queue; + DELETE1(_issue_queue ,_param->_nb_bank); // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp (revision 112) @@ -58,13 +58,15 @@ // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("rename",IN, SOUTH,_("rename's interface"),_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_INTERFACE_BEGIN("rename",IN, SOUTH,_("rename's interface"),_param->_nb_front_end,_param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_OUT(out_RENAME_RENAME_UNIT_FRONT_END_ID ,"RENAME_UNIT_FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_inst_decod[it1]); } // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("insert",OUT, WEST,_("insert's interface"),_param->_sum_inst_insert); + ALLOC1_INTERFACE_BEGIN("insert",OUT, WEST,_("insert's interface"),_param->_sum_inst_insert); ALLOC1_SIGNAL_OUT (out_INSERT_VAL ,"VAL" ,Tcontrol_t ,1 ); @@ -74,8 +76,10 @@ ALLOC1_SIGNAL_OUT (out_INSERT_RE_USE ,"RE_USE" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT (out_INSERT_RE_NUM_REG ,"RE_NUM_REG" ,Tspecial_address_t ,_param->_size_special_register); - } - - { - ALLOC2_INTERFACE("insert",IN, EAST,_("insert's interface"),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + + ALLOC1_INTERFACE_END(_param->_sum_inst_insert); + } + + { + ALLOC2_INTERFACE_BEGIN("insert",IN, EAST,_("insert's interface"),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_VAL ,"RENAME_UNIT_VAL" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); @@ -146,9 +150,11 @@ _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_WRITE_RE ,"ISSUE_QUEUE_WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_NUM_REG_RE ,"ISSUE_QUEUE_NUM_REG_RE" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); } // // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // { -// ALLOC1_INTERFACE("retire",OUT, WEST,_("retire's interface"),_param->_sum_inst_retire); +// ALLOC1_INTERFACE_BEGIN("retire",OUT, WEST,_("retire's interface"),_param->_sum_inst_retire); // ALLOC1_SIGNAL_OUT (out_RETIRE_VAL ,"VAL" ,Tcontrol_t ,1 ); @@ -162,8 +168,10 @@ // ALLOC1_SIGNAL_OUT (out_RETIRE_RE_NEW_USE ,"RE_NEW_USE" ,Tcontrol_t ,1 ); // ALLOC1_SIGNAL_OUT (out_RETIRE_RE_NEW_NUM_REG ,"RE_NEW_NUM_REG" ,Tspecial_address_t ,_param->_size_special_register); + +// ALLOC1_INTERFACE_END(_param->_sum_inst_retire); // } // { -// ALLOC2_INTERFACE("retire",IN, EAST,_("retire's interface"),_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_INTERFACE_BEGIN("retire",IN, EAST,_("retire's interface"),_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); // _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_VAL ,"RENAME_UNIT_VAL" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); @@ -188,9 +196,11 @@ // _ALLOC2_SIGNAL_IN ( in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ,"COMMIT_UNIT_NUM_REG_RE_PHY_NEW" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); // _ALLOC2_SIGNAL_IN ( in_RETIRE_COMMIT_UNIT_EVENT_STATE ,"COMMIT_UNIT_EVENT_STATE" ,Tevent_state_t ,_param->_size_event_state ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + +// ALLOC2_INTERFACE_END(_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); // } // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("spr",IN, NORTH,_("spr's interface"),_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("spr",IN, NORTH,_("spr's interface"),_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_SIGNAL_OUT(out_SPR_SR_IEE ,"SR_IEE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); @@ -199,4 +209,6 @@ _ALLOC2_SIGNAL_OUT(out_SPR_COMMIT_UNIT_SR_OVE ,"COMMIT_UNIT_SR_OVE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_SPR_SPECIAL_REGISTER_UNIT_SR ,"SPECIAL_REGISTER_UNIT_SR" ,Tspr_t ,_param->_size_spr ,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp (revision 112) @@ -58,5 +58,5 @@ // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("execute_loop", IN, EAST, _("Instruction executed from execute_loop"),_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_INTERFACE_BEGIN("execute_loop", IN, EAST, _("Instruction executed from execute_loop"),_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); _ALLOC2_VALACK_IN ( in_EXECUTE_LOOP_VAL ,VAL,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); @@ -72,9 +72,11 @@ _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); } // ~~~~~[ Interface "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("commit",OUT,WEST, _("Instruction executed to Re Order Buffer"),_param->_nb_inst_commit); + ALLOC1_INTERFACE_BEGIN("commit",OUT,WEST, _("Instruction executed to Re Order Buffer"),_param->_nb_inst_commit); ALLOC1_VALACK_OUT(out_COMMIT_VAL ,VAL); @@ -91,9 +93,11 @@ ALLOC1_SIGNAL_OUT(out_COMMIT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t ,_param->_size_general_register); + + ALLOC1_INTERFACE_END(_param->_nb_inst_commit); } // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("spr",OUT,EAST, _("Access to Special Register"), _param->_nb_inst_reexecute); + ALLOC1_INTERFACE_BEGIN("spr",OUT,EAST, _("Access to Special Register"), _param->_nb_inst_reexecute); ALLOC1_VALACK_OUT(out_SPR_VAL ,VAL); @@ -107,9 +111,11 @@ ALLOC1_SIGNAL_IN ( in_SPR_RDATA ,"rdata" ,Tspr_t ,_param->_size_spr); ALLOC1_SIGNAL_IN ( in_SPR_INVALID ,"invalid" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_reexecute); } // ~~~~~[ Interface : "reexecute_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("reexecute_rob", IN,EAST, _("Instruction reexecuted by the Re Order Buffer (Store head)"), _param->_nb_inst_reexecute); + ALLOC1_INTERFACE_BEGIN("reexecute_rob", IN,EAST, _("Instruction reexecuted by the Re Order Buffer (Store head)"), _param->_nb_inst_reexecute); ALLOC1_VALACK_IN ( in_REEXECUTE_ROB_VAL ,VAL); @@ -121,31 +127,35 @@ ALLOC1_SIGNAL_IN ( in_REEXECUTE_ROB_TYPE ,"type" ,Ttype_t ,_param->_size_type); ALLOC1_SIGNAL_IN ( in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE ,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); + + ALLOC1_INTERFACE_END(_param->_nb_inst_reexecute); } // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("reexecute",OUT,SOUTH, _("Instruction reexecute, send at the issue_queue"), _param->_nb_inst_reexecute); + ALLOC1_INTERFACE_BEGIN("reexecute",OUT,SOUTH, _("Instruction reexecute, send at the issue_queue"), _param->_nb_inst_reexecute); ALLOC1_VALACK_OUT(out_REEXECUTE_VAL ,VAL); ALLOC1_VALACK_IN ( in_REEXECUTE_ACK ,ACK); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_TYPE ,"type" ,Ttype_t ,_param->_size_type ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); + + ALLOC1_INTERFACE_END(_param->_nb_inst_reexecute); } @@ -153,17 +163,17 @@ { // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - _reexecute_queue = new std::list [_param->_nb_bank]; + ALLOC1(_reexecute_queue ,std::list,_param->_nb_bank); // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - internal_QUEUE_PUSH = new Tcontrol_t [_param->_nb_bank]; - internal_QUEUE_NUM_EXECUTE_LOOP = new uint32_t [_param->_nb_bank]; - internal_QUEUE_NUM_INST_EXECUTE = new uint32_t [_param->_nb_bank]; - internal_QUEUE_NUM_INST_COMMIT = new uint32_t [_param->_nb_bank]; - internal_QUEUE_INFO = new info_t [_param->_nb_bank]; - internal_SPR_VAL = new Tcontrol_t [_param->_nb_inst_reexecute]; - internal_REEXECUTE_ROB_ACK = new Tcontrol_t [_param->_nb_inst_reexecute]; - internal_REEXECUTE_VAL = new Tcontrol_t [_param->_nb_inst_reexecute]; + ALLOC1(internal_QUEUE_PUSH ,Tcontrol_t,_param->_nb_bank); + ALLOC1(internal_QUEUE_NUM_EXECUTE_LOOP ,uint32_t ,_param->_nb_bank); + ALLOC1(internal_QUEUE_NUM_INST_EXECUTE ,uint32_t ,_param->_nb_bank); + ALLOC1(internal_QUEUE_NUM_INST_COMMIT ,uint32_t ,_param->_nb_bank); + ALLOC1(internal_QUEUE_INFO ,info_t ,_param->_nb_bank); + ALLOC1(internal_SPR_VAL ,Tcontrol_t,_param->_nb_inst_reexecute); + ALLOC1(internal_REEXECUTE_ROB_ACK ,Tcontrol_t,_param->_nb_inst_reexecute); + ALLOC1(internal_REEXECUTE_VAL ,Tcontrol_t,_param->_nb_inst_reexecute); #ifdef STATISTICS - internal_COMMIT_VAL = new Tcontrol_t [_param->_nb_inst_commit]; + ALLOC1(internal_COMMIT_VAL ,Tcontrol_t,_param->_nb_inst_commit); #endif } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_deallocation.cpp (revision 112) @@ -105,20 +105,20 @@ delete entry; } - delete [] _reexecute_queue; + DELETE1(_reexecute_queue ,_param->_nb_bank); // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] internal_QUEUE_PUSH ; - delete [] internal_QUEUE_NUM_EXECUTE_LOOP; - delete [] internal_QUEUE_NUM_INST_EXECUTE; - delete [] internal_QUEUE_NUM_INST_COMMIT ; - delete [] internal_QUEUE_INFO ; - delete [] internal_SPR_VAL ; - delete [] internal_REEXECUTE_ROB_ACK ; - delete [] internal_REEXECUTE_VAL ; + DELETE1(internal_QUEUE_PUSH ,_param->_nb_bank); + DELETE1(internal_QUEUE_NUM_EXECUTE_LOOP ,_param->_nb_bank); + DELETE1(internal_QUEUE_NUM_INST_EXECUTE ,_param->_nb_bank); + DELETE1(internal_QUEUE_NUM_INST_COMMIT ,_param->_nb_bank); + DELETE1(internal_QUEUE_INFO ,_param->_nb_bank); + DELETE1(internal_SPR_VAL ,_param->_nb_inst_reexecute); + DELETE1(internal_REEXECUTE_ROB_ACK ,_param->_nb_inst_reexecute); + DELETE1(internal_REEXECUTE_VAL ,_param->_nb_inst_reexecute); #ifdef STATISTICS - delete [] internal_COMMIT_VAL ; + DELETE1(internal_COMMIT_VAL ,_param->_nb_inst_commit); #endif } - + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp (revision 112) @@ -58,5 +58,5 @@ // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("insert", IN, EAST, "insert to the re order buffer an instruction", _param->_nb_inst_insert); + ALLOC1_INTERFACE_BEGIN("insert", IN, EAST, _("insert to the re order buffer an instruction"), _param->_nb_inst_insert); ALLOC1_VALACK_IN ( in_INSERT_VAL ,VAL); @@ -68,9 +68,11 @@ ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_insert); } // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("retire", IN, EAST, "retire from the re order buffer an instruction", _param->_nb_inst_retire); + ALLOC1_INTERFACE_BEGIN("retire", IN, EAST, _("retire from the re order buffer an instruction"), _param->_nb_inst_retire); ALLOC1_VALACK_IN ( in_RETIRE_VAL ,VAL); @@ -84,29 +86,25 @@ ALLOC1_SIGNAL_IN ( in_RETIRE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); ALLOC1_SIGNAL_IN ( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_retire); } if (usage_is_set(_usage,USE_SYSTEMC)) { - reg_STORE_QUEUE_PTR_WRITE = new Tlsq_ptr_t [_param->_nb_load_store_queue]; - reg_STORE_QUEUE_USE = new bool * [_param->_nb_load_store_queue]; - reg_STORE_QUEUE_NB_USE = new Tlsq_ptr_t [_param->_nb_load_store_queue]; - reg_LOAD_QUEUE_PTR_WRITE = new Tlsq_ptr_t [_param->_nb_load_store_queue]; - reg_LOAD_QUEUE_USE = new bool * [_param->_nb_load_store_queue]; - - for (uint32_t i=0; i<_param->_nb_load_store_queue; i++) - { - reg_STORE_QUEUE_USE [i] = new bool [_param->_size_store_queue [i]]; - reg_LOAD_QUEUE_USE [i] = new bool [_param->_size_load_queue [i]]; - } + ALLOC1(reg_STORE_QUEUE_PTR_WRITE ,Tlsq_ptr_t ,_param->_nb_load_store_queue); + ALLOC2(reg_STORE_QUEUE_USE ,bool ,_param->_nb_load_store_queue,_param->_size_store_queue [it1]); + ALLOC1(reg_STORE_QUEUE_NB_USE ,Tlsq_ptr_t ,_param->_nb_load_store_queue); + ALLOC1(reg_LOAD_QUEUE_PTR_WRITE ,Tlsq_ptr_t ,_param->_nb_load_store_queue); + ALLOC2(reg_LOAD_QUEUE_USE ,bool ,_param->_nb_load_store_queue,_param->_size_load_queue [it1]); - internal_INSERT_ACK = new Tcontrol_t [_param->_nb_inst_insert]; - internal_INSERT_OPERATION_USE = new operation_use_t [_param->_nb_inst_insert]; - internal_INSERT_LSQ = new uint32_t [_param->_nb_inst_insert]; - internal_INSERT_PTR = new Tlsq_ptr_t [_param->_nb_inst_insert]; + ALLOC1(internal_INSERT_ACK ,Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1(internal_INSERT_OPERATION_USE ,operation_use_t,_param->_nb_inst_insert); + ALLOC1(internal_INSERT_LSQ ,uint32_t ,_param->_nb_inst_insert); + ALLOC1(internal_INSERT_PTR ,Tlsq_ptr_t ,_param->_nb_inst_insert); - internal_RETIRE_ACK = new Tcontrol_t [_param->_nb_inst_retire]; - internal_RETIRE_OPERATION_USE = new operation_use_t [_param->_nb_inst_retire]; - internal_RETIRE_LSQ = new uint32_t [_param->_nb_inst_retire]; - internal_RETIRE_PTR = new Tlsq_ptr_t [_param->_nb_inst_retire]; + ALLOC1(internal_RETIRE_ACK ,Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1(internal_RETIRE_OPERATION_USE ,operation_use_t,_param->_nb_inst_retire); + ALLOC1(internal_RETIRE_LSQ ,uint32_t ,_param->_nb_inst_retire); + ALLOC1(internal_RETIRE_PTR ,Tlsq_ptr_t ,_param->_nb_inst_retire); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -28,45 +29,39 @@ delete in_NRESET; - // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_INSERT_VAL ; - delete [] out_INSERT_ACK ; - if (_param->_have_port_front_end_id) - delete [] in_INSERT_FRONT_END_ID ; - if (_param->_have_port_context_id) - delete [] in_INSERT_CONTEXT_ID ; - delete [] in_INSERT_TYPE ; - delete [] in_INSERT_OPERATION ; - delete [] out_INSERT_STORE_QUEUE_PTR_WRITE; - if (_param->_have_port_load_queue_ptr) - delete [] out_INSERT_LOAD_QUEUE_PTR_WRITE ; - - // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_RETIRE_VAL ; - delete [] out_RETIRE_ACK ; - if (_param->_have_port_front_end_id) - delete [] in_RETIRE_FRONT_END_ID ; - if (_param->_have_port_context_id) - delete [] in_RETIRE_CONTEXT_ID ; -// delete [] in_RETIRE_TYPE ; -// delete [] in_RETIRE_OPERATION ; - delete [] in_RETIRE_USE_STORE_QUEUE ; - delete [] in_RETIRE_USE_LOAD_QUEUE ; - delete [] in_RETIRE_STORE_QUEUE_PTR_WRITE; - if (_param->_have_port_load_queue_ptr) - delete [] in_RETIRE_LOAD_QUEUE_PTR_WRITE ; + DELETE1_SIGNAL( in_INSERT_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id ); + DELETE1_SIGNAL( in_INSERT_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); + DELETE1_SIGNAL( in_INSERT_TYPE ,_param->_nb_inst_insert,_param->_size_type ); + DELETE1_SIGNAL( in_INSERT_OPERATION ,_param->_nb_inst_insert,_param->_size_operation ); + DELETE1_SIGNAL(out_INSERT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_insert,_param->_size_store_queue_ptr); + DELETE1_SIGNAL(out_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_insert,_param->_size_load_queue_ptr ); - delete [] reg_STORE_QUEUE_PTR_WRITE ; - delete [] reg_STORE_QUEUE_USE ; - delete [] reg_STORE_QUEUE_NB_USE ; - delete [] reg_LOAD_QUEUE_PTR_WRITE ; - delete [] reg_LOAD_QUEUE_USE ; - delete [] internal_INSERT_ACK ; - delete [] internal_INSERT_OPERATION_USE; - delete [] internal_INSERT_LSQ ; - delete [] internal_INSERT_PTR ; - delete [] internal_RETIRE_ACK ; - delete [] internal_RETIRE_OPERATION_USE; - delete [] internal_RETIRE_LSQ ; - delete [] internal_RETIRE_PTR ; + DELETE1_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_RETIRE_FRONT_END_ID ,_param->_nb_inst_retire,_param->_size_front_end_id ); + DELETE1_SIGNAL( in_RETIRE_CONTEXT_ID ,_param->_nb_inst_retire,_param->_size_context_id ); +// DELETE1_SIGNAL( in_RETIRE_TYPE ,_param->_nb_inst_retire,_param->_size_type ); +// DELETE1_SIGNAL( in_RETIRE_OPERATION ,_param->_nb_inst_retire,_param->_size_operation ); + DELETE1_SIGNAL( in_RETIRE_USE_STORE_QUEUE ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_RETIRE_USE_LOAD_QUEUE ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_RETIRE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire,_param->_size_store_queue_ptr); + DELETE1_SIGNAL( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire,_param->_size_load_queue_ptr ); + + DELETE1(reg_STORE_QUEUE_PTR_WRITE ,_param->_nb_load_store_queue); + DELETE2(reg_STORE_QUEUE_USE ,_param->_nb_load_store_queue,_param->_size_store_queue [it1]); + DELETE1(reg_STORE_QUEUE_NB_USE ,_param->_nb_load_store_queue); + DELETE1(reg_LOAD_QUEUE_PTR_WRITE ,_param->_nb_load_store_queue); + DELETE2(reg_LOAD_QUEUE_USE ,_param->_nb_load_store_queue,_param->_size_load_queue [it1]); + + DELETE1(internal_INSERT_ACK ,_param->_nb_inst_insert); + DELETE1(internal_INSERT_OPERATION_USE ,_param->_nb_inst_insert); + DELETE1(internal_INSERT_LSQ ,_param->_nb_inst_insert); + DELETE1(internal_INSERT_PTR ,_param->_nb_inst_insert); + + DELETE1(internal_RETIRE_ACK ,_param->_nb_inst_retire); + DELETE1(internal_RETIRE_OPERATION_USE ,_param->_nb_inst_retire); + DELETE1(internal_RETIRE_LSQ ,_param->_nb_inst_retire); + DELETE1(internal_RETIRE_PTR ,_param->_nb_inst_retire); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_allocation.cpp (revision 112) @@ -49,5 +49,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -58,8 +58,8 @@ // ~~~~~[ Interface "rename_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("rename_in", IN, EAST, "Registers before near dependency checking", _param->_nb_inst_insert); + ALLOC1_INTERFACE_BEGIN("rename_in", IN, EAST, _("Registers before near dependency checking"), _param->_nb_inst_insert); -// ALLOC1_VALACK_IN ( in_RENAME_IN_VAL ,VAL); -// ALLOC1_VALACK_OUT(out_RENAME_IN_ACK ,ACK); +// ALLOC1_VALACK_IN ( in_RENAME_IN_VAL ,VAL); +// ALLOC1_VALACK_OUT(out_RENAME_IN_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_RENAME_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); ALLOC1_SIGNAL_IN ( in_RENAME_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); @@ -81,12 +81,14 @@ ALLOC1_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register ); ALLOC1_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_insert); } // ~~~~~[ Interface "rename_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("rename_out", OUT, WEST, "Registers after near dependency checking", _param->_nb_inst_insert); + ALLOC1_INTERFACE_BEGIN("rename_out", OUT, WEST, _("Registers after near dependency checking"), _param->_nb_inst_insert); -// ALLOC1_VALACK_OUT(out_RENAME_OUT_VAL ,VAL); -// ALLOC1_VALACK_IN ( in_RENAME_OUT_ACK ,ACK); +// ALLOC1_VALACK_OUT(out_RENAME_OUT_VAL ,VAL); +// ALLOC1_VALACK_IN ( in_RENAME_OUT_ACK ,ACK); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); @@ -108,4 +110,6 @@ ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_insert); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/include/Dependency_checking_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -29,51 +30,47 @@ delete in_NRESET; -// delete [] in_RENAME_IN_VAL ; -// delete [] out_RENAME_IN_ACK ; - if (_param->_have_port_front_end_id) - delete [] in_RENAME_IN_FRONT_END_ID ; - if (_param->_have_port_context_id) - delete [] in_RENAME_IN_CONTEXT_ID ; - delete [] in_RENAME_IN_READ_RA ; - delete [] in_RENAME_IN_NUM_REG_RA_LOG ; - delete [] in_RENAME_IN_NUM_REG_RA_PHY ; - delete [] in_RENAME_IN_READ_RB ; - delete [] in_RENAME_IN_NUM_REG_RB_LOG ; - delete [] in_RENAME_IN_NUM_REG_RB_PHY ; - delete [] in_RENAME_IN_READ_RC ; - delete [] in_RENAME_IN_NUM_REG_RC_LOG ; - delete [] in_RENAME_IN_NUM_REG_RC_PHY ; - delete [] in_RENAME_IN_WRITE_RD ; - delete [] in_RENAME_IN_NUM_REG_RD_LOG ; - delete [] in_RENAME_IN_NUM_REG_RD_PHY_OLD ; - delete [] in_RENAME_IN_NUM_REG_RD_PHY_NEW ; - delete [] in_RENAME_IN_WRITE_RE ; - delete [] in_RENAME_IN_NUM_REG_RE_LOG ; - delete [] in_RENAME_IN_NUM_REG_RE_PHY_OLD ; - delete [] in_RENAME_IN_NUM_REG_RE_PHY_NEW ; +// DELETE1_SIGNAL( in_RENAME_IN_VAL ,_param->_nb_inst_insert,1); +// DELETE1_SIGNAL(out_RENAME_IN_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_RENAME_IN_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id ); + DELETE1_SIGNAL( in_RENAME_IN_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); + DELETE1_SIGNAL( in_RENAME_IN_READ_RA ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RA_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL( in_RENAME_IN_READ_RB ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RB_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL( in_RENAME_IN_READ_RC ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RC_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register ); + DELETE1_SIGNAL( in_RENAME_IN_WRITE_RD ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RD_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL( in_RENAME_IN_WRITE_RE ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RE_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert,_param->_size_special_register ); + DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert,_param->_size_special_register ); -// delete [] out_RENAME_OUT_VAL ; -// delete [] in_RENAME_OUT_ACK ; - if (_param->_have_port_front_end_id) - delete [] out_RENAME_OUT_FRONT_END_ID ; - if (_param->_have_port_context_id) - delete [] out_RENAME_OUT_CONTEXT_ID ; - delete [] out_RENAME_OUT_READ_RA ; - delete [] out_RENAME_OUT_NUM_REG_RA_LOG ; - delete [] out_RENAME_OUT_NUM_REG_RA_PHY ; - delete [] out_RENAME_OUT_READ_RB ; - delete [] out_RENAME_OUT_NUM_REG_RB_LOG ; - delete [] out_RENAME_OUT_NUM_REG_RB_PHY ; - delete [] out_RENAME_OUT_READ_RC ; - delete [] out_RENAME_OUT_NUM_REG_RC_LOG ; - delete [] out_RENAME_OUT_NUM_REG_RC_PHY ; - delete [] out_RENAME_OUT_WRITE_RD ; - delete [] out_RENAME_OUT_NUM_REG_RD_LOG ; - delete [] out_RENAME_OUT_NUM_REG_RD_PHY_OLD; - delete [] out_RENAME_OUT_NUM_REG_RD_PHY_NEW; - delete [] out_RENAME_OUT_WRITE_RE ; - delete [] out_RENAME_OUT_NUM_REG_RE_LOG ; - delete [] out_RENAME_OUT_NUM_REG_RE_PHY_OLD; - delete [] out_RENAME_OUT_NUM_REG_RE_PHY_NEW; +// DELETE1_SIGNAL(out_RENAME_OUT_VAL ,_param->_nb_inst_insert,1); +// DELETE1_SIGNAL( in_RENAME_OUT_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_RENAME_OUT_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id ); + DELETE1_SIGNAL(out_RENAME_OUT_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); + DELETE1_SIGNAL(out_RENAME_OUT_READ_RA ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RA_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_RENAME_OUT_READ_RB ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RB_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_RENAME_OUT_READ_RC ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RC_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register ); + DELETE1_SIGNAL(out_RENAME_OUT_WRITE_RD ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RD_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_RENAME_OUT_WRITE_RE ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RE_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert,_param->_size_special_register ); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert,_param->_size_special_register ); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_allocation.cpp (revision 112) @@ -49,5 +49,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -58,5 +58,5 @@ // ~~~~~[ interface : "pop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("pop", IN, NORTH, "New destination register", _param->_nb_pop); + ALLOC1_INTERFACE_BEGIN("pop", IN, NORTH, _("New destination register"), _param->_nb_pop); ALLOC1_VALACK_IN ( in_POP_VAL ,VAL); @@ -66,38 +66,45 @@ ALLOC1_SIGNAL_IN ( in_POP_SPR_VAL ,"spr_val" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_POP_SPR_NUM_REG,"spr_num_reg",Tspecial_address_t,_param->_size_special_register); + + ALLOC1_INTERFACE_END(_param->_nb_pop); } // ~~~~~[ interface : "push_gpr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("push_gpr", IN, NORTH, "General register free", _param->_nb_push); + ALLOC1_INTERFACE_BEGIN("push_gpr", IN, NORTH, _("General register free"), _param->_nb_push); ALLOC1_VALACK_IN ( in_PUSH_GPR_VAL ,VAL); ALLOC1_VALACK_OUT(out_PUSH_GPR_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_PUSH_GPR_NUM_REG,"num_reg",Tgeneral_address_t,_param->_size_general_register); + + ALLOC1_INTERFACE_END(_param->_nb_push); } // ~~~~~[ interface : "push_spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("push_spr", IN, NORTH, "General register free", _param->_nb_push); + ALLOC1_INTERFACE_BEGIN("push_spr", IN, NORTH, _("General register free"), _param->_nb_push); ALLOC1_VALACK_IN ( in_PUSH_SPR_VAL ,VAL); ALLOC1_VALACK_OUT(out_PUSH_SPR_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_PUSH_SPR_NUM_REG,"num_reg",Tspecial_address_t,_param->_size_special_register); + + ALLOC1_INTERFACE_END(_param->_nb_push); } if (usage_is_set(_usage,USE_SYSTEMC)) { - _gpr_list = new std::list [_param->_nb_bank]; - _spr_list = new std::list [_param->_nb_bank]; + ALLOC1(_gpr_list,std::list,_param->_nb_bank); + ALLOC1(_spr_list,std::list,_param->_nb_bank); - internal_POP_ACK = new Tcontrol_t [_param->_nb_pop]; - internal_POP_GPR_BANK = new uint32_t [_param->_nb_pop]; - internal_POP_SPR_BANK = new uint32_t [_param->_nb_pop]; + ALLOC1(internal_POP_ACK ,Tcontrol_t,_param->_nb_pop); + ALLOC1(internal_POP_GPR_BANK ,uint32_t ,_param->_nb_pop); + ALLOC1(internal_POP_SPR_BANK ,uint32_t ,_param->_nb_pop); - internal_PUSH_GPR_ACK = new Tcontrol_t [_param->_nb_push]; - internal_PUSH_SPR_ACK = new Tcontrol_t [_param->_nb_push]; - internal_PUSH_GPR_BANK = new uint32_t [_param->_nb_push]; - internal_PUSH_SPR_BANK = new uint32_t [_param->_nb_push]; + ALLOC1(internal_PUSH_GPR_ACK ,Tcontrol_t,_param->_nb_push); + ALLOC1(internal_PUSH_SPR_ACK ,Tcontrol_t,_param->_nb_push); + ALLOC1(internal_PUSH_GPR_BANK,uint32_t ,_param->_nb_push); + ALLOC1(internal_PUSH_SPR_BANK,uint32_t ,_param->_nb_push); } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ _priority_gpr = new generic::priority::Priority (_name+"_priority_gpr", Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Free_List_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -29,30 +30,30 @@ delete in_NRESET; - delete [] in_POP_VAL ; - delete [] out_POP_ACK ; - delete [] in_POP_GPR_VAL ; - delete [] out_POP_GPR_NUM_REG; - delete [] in_POP_SPR_VAL ; - delete [] out_POP_SPR_NUM_REG; + DELETE1_SIGNAL( in_POP_VAL ,_param->_nb_pop,1); + DELETE1_SIGNAL(out_POP_ACK ,_param->_nb_pop,1); + DELETE1_SIGNAL( in_POP_GPR_VAL ,_param->_nb_pop,1 ); + DELETE1_SIGNAL(out_POP_GPR_NUM_REG ,_param->_nb_pop,_param->_size_general_register); + DELETE1_SIGNAL( in_POP_SPR_VAL ,_param->_nb_pop,1 ); + DELETE1_SIGNAL(out_POP_SPR_NUM_REG ,_param->_nb_pop,_param->_size_special_register); - delete [] in_PUSH_GPR_VAL ; - delete [] out_PUSH_GPR_ACK ; - delete [] in_PUSH_GPR_NUM_REG; + DELETE1_SIGNAL( in_PUSH_GPR_VAL ,_param->_nb_push,1); + DELETE1_SIGNAL(out_PUSH_GPR_ACK ,_param->_nb_push,1); + DELETE1_SIGNAL( in_PUSH_GPR_NUM_REG,_param->_nb_push,_param->_size_general_register); - delete [] in_PUSH_SPR_VAL ; - delete [] out_PUSH_SPR_ACK ; - delete [] in_PUSH_SPR_NUM_REG; + DELETE1_SIGNAL( in_PUSH_SPR_VAL ,_param->_nb_push,1); + DELETE1_SIGNAL(out_PUSH_SPR_ACK ,_param->_nb_push,1); + DELETE1_SIGNAL( in_PUSH_SPR_NUM_REG,_param->_nb_push,_param->_size_special_register); - delete [] _gpr_list; - delete [] _spr_list; - - delete [] internal_POP_ACK ; - delete [] internal_POP_GPR_BANK; - delete [] internal_POP_SPR_BANK; - - delete [] internal_PUSH_GPR_ACK ; - delete [] internal_PUSH_SPR_ACK ; - delete [] internal_PUSH_GPR_BANK; - delete [] internal_PUSH_SPR_BANK; + DELETE1(_gpr_list ,_param->_nb_bank); + DELETE1(_spr_list ,_param->_nb_bank); + + DELETE1(internal_POP_ACK ,_param->_nb_pop); + DELETE1(internal_POP_GPR_BANK ,_param->_nb_pop); + DELETE1(internal_POP_SPR_BANK ,_param->_nb_pop); + + DELETE1(internal_PUSH_GPR_ACK ,_param->_nb_push); + DELETE1(internal_PUSH_SPR_ACK ,_param->_nb_push); + DELETE1(internal_PUSH_GPR_BANK,_param->_nb_push); + DELETE1(internal_PUSH_SPR_BANK,_param->_nb_push); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp (revision 112) @@ -51,5 +51,6 @@ #ifdef STATISTICS - (*_stat_nb_inst_pop) ++; + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_inst_pop) ++; #endif @@ -57,5 +58,6 @@ { #ifdef STATISTICS - (*_stat_nb_inst_pop_gpr) ++; + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_inst_pop_gpr) ++; #endif _gpr_list [internal_POP_GPR_BANK[i]].pop_front(); @@ -65,5 +67,6 @@ { #ifdef STATISTICS - (*_stat_nb_inst_pop_spr) ++; + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_inst_pop_spr) ++; #endif _spr_list [internal_POP_SPR_BANK[i]].pop_front(); @@ -82,5 +85,6 @@ #ifdef STATISTICS - (*_stat_nb_inst_push_gpr) ++; + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_inst_push_gpr) ++; #endif @@ -98,5 +102,6 @@ #ifdef STATISTICS - (*_stat_nb_inst_push_spr) ++; + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_inst_push_spr) ++; #endif @@ -105,6 +110,8 @@ #ifdef STATISTICS - for (uint32_t i=0; i<_param->_nb_bank; ++i) - { + if (usage_is_set(_usage,USE_STATISTICS)) + for (uint32_t i=0; i<_param->_nb_bank; ++i) + { + (*(_stat_bank_gpr_nb_elt [i])) += _gpr_list[i].size(); (*(_stat_bank_spr_nb_elt [i])) += _spr_list[i].size(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp (revision 112) @@ -89,4 +89,5 @@ ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE_RD_PHY_OLD,"out_RETIRE_RESTORE_RD_PHY_OLD",Tcontrol_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE_RE_PHY_OLD,"out_RETIRE_RESTORE_RE_PHY_OLD",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE ,"out_RETIRE_RESTORE ",Tcontrol_t ,_param->_nb_inst_retire); ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_VAL ," in_RETIRE_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); @@ -147,4 +148,5 @@ INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE ,_param->_nb_inst_retire); INSTANCE2_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); @@ -540,4 +542,5 @@ delete [] out_RETIRE_RESTORE_RD_PHY_OLD; delete [] out_RETIRE_RESTORE_RE_PHY_OLD; + delete [] out_RETIRE_RESTORE ; DELETE2_SC_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h (revision 112) @@ -104,4 +104,5 @@ public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RESTORE_RD_PHY_OLD;//[nb_inst_retire] public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RESTORE_RE_PHY_OLD;//[nb_inst_retire] + public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RESTORE ;//[nb_inst_retire] // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -126,4 +127,7 @@ private : bool *** internal_rat_gpr_update_table; //[nb_front_end][nb_context][nb_general_register_logic] private : bool *** internal_rat_spr_update_table; //[nb_front_end][nb_context][nb_special_register_logic] + public : Tcontrol_t * internal_RETIRE_RESTORE_RD_PHY_OLD;//[nb_inst_retire] + public : Tcontrol_t * internal_RETIRE_RESTORE_RE_PHY_OLD;//[nb_inst_retire] + #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp (revision 112) @@ -59,5 +59,5 @@ // ~~~~~[ Interface "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("rename",IN,EAST,"Input to rename source logical register", _param->_nb_inst_insert); + ALLOC1_INTERFACE_BEGIN("rename",IN,EAST,_("Input to rename source logical register"), _param->_nb_inst_insert); ALLOC1_VALACK_IN ( in_RENAME_VAL , VAL); @@ -75,9 +75,11 @@ ALLOC1_SIGNAL_OUT(out_RENAME_NUM_REG_RD_PHY_OLD,"num_reg_rd_phy_old",Tgeneral_address_t,_param->_size_general_register); ALLOC1_SIGNAL_OUT(out_RENAME_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register); + + ALLOC1_INTERFACE_END(_param->_nb_inst_insert); } // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("insert",IN,NORTH,"Input to rename destination logical register", _param->_nb_inst_insert); + ALLOC1_INTERFACE_BEGIN("insert",IN,NORTH,_("Input to rename destination logical register"), _param->_nb_inst_insert); ALLOC1_VALACK_IN ( in_INSERT_VAL ,VAL); @@ -91,9 +93,11 @@ ALLOC1_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY,"num_reg_rd_phy",Tgeneral_address_t,_param->_size_general_register); ALLOC1_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY,"num_reg_re_phy",Tspecial_address_t,_param->_size_special_register); + + ALLOC1_INTERFACE_END(_param->_nb_inst_insert); } // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("retire",IN,NORTH,"Input to update on event", _param->_nb_inst_retire); + ALLOC1_INTERFACE_BEGIN("retire",IN,NORTH,_("Input to update on event"), _param->_nb_inst_retire); ALLOC1_VALACK_IN ( in_RETIRE_VAL ,VAL); @@ -109,13 +113,18 @@ ALLOC1_SIGNAL_OUT(out_RETIRE_RESTORE_RD_PHY_OLD,"restore_rd_phy_old",Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_RETIRE_RESTORE_RE_PHY_OLD,"restore_re_phy_old",Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_RETIRE_RESTORE ,"restore" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_retire); } // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } @@ -127,30 +136,13 @@ ALLOC2(internal_RETIRE_EVENT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); - rat_gpr = new Tgeneral_address_t ** [_param->_nb_front_end]; - rat_spr = new Tspecial_address_t ** [_param->_nb_front_end]; - rat_gpr_update_table = new bool ** [_param->_nb_front_end]; - rat_spr_update_table = new bool ** [_param->_nb_front_end]; - internal_rat_gpr_update_table = new bool ** [_param->_nb_front_end]; - internal_rat_spr_update_table = new bool ** [_param->_nb_front_end]; + ALLOC3(rat_gpr ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); + ALLOC3(rat_spr ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); + ALLOC3(rat_gpr_update_table ,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); + ALLOC3(rat_spr_update_table ,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); + ALLOC3(internal_rat_gpr_update_table,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); + ALLOC3(internal_rat_spr_update_table,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); - for (uint32_t i=0; i<_param->_nb_front_end; i++) - { - rat_gpr [i] = new Tgeneral_address_t * [_param->_nb_context[i]]; - rat_spr [i] = new Tspecial_address_t * [_param->_nb_context[i]]; - rat_gpr_update_table [i] = new bool * [_param->_nb_context[i]]; - rat_spr_update_table [i] = new bool * [_param->_nb_context[i]]; - internal_rat_gpr_update_table [i] = new bool * [_param->_nb_context[i]]; - internal_rat_spr_update_table [i] = new bool * [_param->_nb_context[i]]; - - for (uint32_t j=0; j<_param->_nb_context[i]; j++) - { - rat_gpr [i][j] = new Tgeneral_address_t [_param->_nb_general_register_logic]; - rat_spr [i][j] = new Tspecial_address_t [_param->_nb_special_register_logic]; - rat_gpr_update_table [i][j] = new bool [_param->_nb_general_register_logic]; - rat_spr_update_table [i][j] = new bool [_param->_nb_special_register_logic]; - internal_rat_gpr_update_table [i][j] = new bool [_param->_nb_general_register_logic]; - internal_rat_spr_update_table [i][j] = new bool [_param->_nb_special_register_logic]; - } - } + ALLOC1(internal_RETIRE_RESTORE_RD_PHY_OLD,Tcontrol_t,_param->_nb_inst_retire); + ALLOC1(internal_RETIRE_RESTORE_RE_PHY_OLD,Tcontrol_t,_param->_nb_inst_retire); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp (revision 112) @@ -30,48 +30,47 @@ delete in_NRESET; - delete [] in_RENAME_VAL ; - delete [] out_RENAME_ACK ; - if (_param->_have_port_front_end_id) - delete [] in_RENAME_FRONT_END_ID ; - if (_param->_have_port_context_id) - delete [] in_RENAME_CONTEXT_ID ; - delete [] in_RENAME_NUM_REG_RA_LOG ; - delete [] in_RENAME_NUM_REG_RB_LOG ; - delete [] in_RENAME_NUM_REG_RC_LOG ; - delete [] in_RENAME_NUM_REG_RD_LOG ; - delete [] in_RENAME_NUM_REG_RE_LOG ; - delete [] out_RENAME_NUM_REG_RA_PHY ; - delete [] out_RENAME_NUM_REG_RB_PHY ; - delete [] out_RENAME_NUM_REG_RC_PHY ; - delete [] out_RENAME_NUM_REG_RD_PHY_OLD; - delete [] out_RENAME_NUM_REG_RE_PHY_OLD; + DELETE1_SIGNAL( in_RENAME_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_RENAME_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_RENAME_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id); + DELETE1_SIGNAL( in_RENAME_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); + DELETE1_SIGNAL( in_RENAME_NUM_REG_RA_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_RENAME_NUM_REG_RB_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_RENAME_NUM_REG_RC_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL( in_RENAME_NUM_REG_RD_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_RENAME_NUM_REG_RE_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_RENAME_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register); + DELETE1_SIGNAL(out_RENAME_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register); + DELETE1_SIGNAL(out_RENAME_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register); + DELETE1_SIGNAL(out_RENAME_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert,_param->_size_general_register); + DELETE1_SIGNAL(out_RENAME_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert,_param->_size_special_register); - delete [] in_INSERT_VAL ; - delete [] out_INSERT_ACK ; -// if (_param->_have_port_front_end_id) -// delete [] in_INSERT_FRONT_END_ID ; -// if (_param->_have_port_context_id) -// delete [] in_INSERT_CONTEXT_ID ; - delete [] in_INSERT_WRITE_RD ; - delete [] in_INSERT_WRITE_RE ; - delete [] in_INSERT_NUM_REG_RD_LOG ; - delete [] in_INSERT_NUM_REG_RE_LOG ; - delete [] in_INSERT_NUM_REG_RD_PHY ; - delete [] in_INSERT_NUM_REG_RE_PHY ; + DELETE1_SIGNAL( in_INSERT_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_ACK ,_param->_nb_inst_insert,1); +// DELETE1_SIGNAL( in_INSERT_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id); +// DELETE1_SIGNAL( in_INSERT_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); + DELETE1_SIGNAL( in_INSERT_WRITE_RD ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_WRITE_RE ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_NUM_REG_RD_LOG,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_INSERT_NUM_REG_RE_LOG,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL( in_INSERT_NUM_REG_RD_PHY,_param->_nb_inst_insert,_param->_size_general_register); + DELETE1_SIGNAL( in_INSERT_NUM_REG_RE_PHY,_param->_nb_inst_insert,_param->_size_special_register); - delete [] in_RETIRE_VAL ; - delete [] out_RETIRE_ACK ; - if (_param->_have_port_front_end_id) - delete [] in_RETIRE_FRONT_END_ID ; - if (_param->_have_port_context_id) - delete [] in_RETIRE_CONTEXT_ID ; - delete [] in_RETIRE_WRITE_RD ; - delete [] in_RETIRE_WRITE_RE ; - delete [] in_RETIRE_NUM_REG_RD_LOG ; - delete [] in_RETIRE_NUM_REG_RE_LOG ; - delete [] in_RETIRE_NUM_REG_RD_PHY_OLD; - delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; - delete [] out_RETIRE_RESTORE_RD_PHY_OLD; - delete [] out_RETIRE_RESTORE_RE_PHY_OLD; + DELETE1_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_RETIRE_FRONT_END_ID ,_param->_nb_inst_retire,_param->_size_front_end_id); + DELETE1_SIGNAL( in_RETIRE_CONTEXT_ID ,_param->_nb_inst_retire,_param->_size_context_id ); + DELETE1_SIGNAL( in_RETIRE_WRITE_RD ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_RETIRE_WRITE_RE ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_LOG ,_param->_nb_inst_retire,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_LOG ,_param->_nb_inst_retire,_param->_size_special_register_logic); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire,_param->_size_general_register); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire,_param->_size_special_register); + DELETE1_SIGNAL(out_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_RESTORE ,_param->_nb_inst_retire,1); + + DELETE2_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL(out_RETIRE_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state); DELETE1(internal_RENAME_ACK ,_param->_nb_inst_insert); @@ -80,14 +79,13 @@ DELETE2(internal_RETIRE_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); - DELETE2_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); - DELETE2_SIGNAL(out_RETIRE_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1],1); - DELETE2_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state); + DELETE3(rat_gpr ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); + DELETE3(rat_spr ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); + DELETE3(rat_gpr_update_table ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); + DELETE3(rat_spr_update_table ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); + DELETE3(internal_rat_gpr_update_table,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); + DELETE3(internal_rat_spr_update_table,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); - delete [] rat_gpr ; - delete [] rat_spr ; - delete [] rat_gpr_update_table; - delete [] rat_spr_update_table; - delete [] internal_rat_gpr_update_table; - delete [] internal_rat_spr_update_table; + DELETE1(internal_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire); + DELETE1(internal_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp (revision 112) @@ -31,9 +31,16 @@ { // An event occure - bool no_event = not (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) and (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)); + // bool event = (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) != EVENT_STATE_NO_EVENT); + bool reset_update_table = (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and // always ack + (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)); + + // not event -> update_table == 1 -> always update + // event -> update_table and not reset for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k) - internal_rat_gpr_update_table [i][j][k] = rat_gpr_update_table [i][j][k] and no_event; + internal_rat_gpr_update_table [i][j][k] = // not event or + (rat_gpr_update_table [i][j][k] and not reset_update_table); for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k) - internal_rat_spr_update_table [i][j][k] = rat_spr_update_table [i][j][k] and no_event; + internal_rat_spr_update_table [i][j][k] = // not event or + (rat_spr_update_table [i][j][k] and not reset_update_table); } @@ -50,7 +57,8 @@ Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; + Tcontrol_t restore = (PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) != EVENT_STATE_NO_EVENT); // Test if event -> need restore ? - if (PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) != EVENT_STATE_NO_EVENT) + if (restore) { log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Have event"); @@ -82,7 +90,11 @@ log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore_re_phy_old : %d",retire_restore_re_phy_old); } + + internal_RETIRE_RESTORE_RD_PHY_OLD[i] = retire_restore_rd_phy_old; + internal_RETIRE_RESTORE_RE_PHY_OLD[i] = retire_restore_re_phy_old; - PORT_WRITE(out_RETIRE_RESTORE_RD_PHY_OLD[i], retire_restore_rd_phy_old); - PORT_WRITE(out_RETIRE_RESTORE_RE_PHY_OLD[i], retire_restore_re_phy_old); + PORT_WRITE(out_RETIRE_RESTORE_RD_PHY_OLD[i], internal_RETIRE_RESTORE_RD_PHY_OLD[i]); + PORT_WRITE(out_RETIRE_RESTORE_RE_PHY_OLD[i], internal_RETIRE_RESTORE_RE_PHY_OLD[i]); + PORT_WRITE(out_RETIRE_RESTORE [i], restore); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp (revision 112) @@ -125,16 +125,23 @@ log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * event_state : %d",event_state); - if (event_state != EVENT_STATE_NO_EVENT) - { +// if (event_state != EVENT_STATE_NO_EVENT) +// { // Test if write and have not a previous update if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1) { Tgeneral_address_t rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); - + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * retire RD"); log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * rd_log : %d",rd_log); -// if (RETIRE_RESTORE_RD_PHY_OLD [i]) - if (rat_gpr_update_table [front_end_id][context_id][rd_log] == 0) +// #ifdef DEBUG_TEST +// if (not (internal_RETIRE_RESTORE_RD_PHY_OLD [i] and ( (rat_gpr_update_table [front_end_id][context_id][rd_log] == 0)) and (event_state != EVENT_STATE_NO_EVENT))) +// throw ERRORMORPHEO(FUNCTION,toString(_("restore_rd_phy_old [%d] = %d, but rat_gpr_update_table[%d][%d][%d] = %d\n"), +// i,internal_RETIRE_RESTORE_RD_PHY_OLD [i], +// front_end_id,context_id,rd_log,rat_gpr_update_table [front_end_id][context_id][rd_log])); +// #endif + + if (internal_RETIRE_RESTORE_RD_PHY_OLD [i]) +// if (rat_gpr_update_table [front_end_id][context_id][rd_log] == 0) { rat_gpr [front_end_id][context_id][rd_log] = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); @@ -150,6 +157,13 @@ log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * re_log : %d",re_log); -// if (RETIRE_RESTORE_RE_PHY_OLD [i]) - if (rat_spr_update_table [front_end_id][context_id][re_log] == 0) +// #ifdef DEBUG_TEST +// if (not (internal_RETIRE_RESTORE_RE_PHY_OLD [i] and ((rat_spr_update_table [front_end_id][context_id][re_log] == 0) and (event_state != EVENT_STATE_NO_EVENT)))) +// throw ERRORMORPHEO(FUNCTION,toString(_("restore_re_phy_old [%d] = %d, but rat_spr_update_table[%d][%d][%d] = %d\n"), +// i,internal_RETIRE_RESTORE_RE_PHY_OLD [i], +// front_end_id,context_id,re_log,rat_spr_update_table [front_end_id][context_id][re_log])); +// #endif + + if (internal_RETIRE_RESTORE_RE_PHY_OLD [i]) +// if (rat_spr_update_table [front_end_id][context_id][re_log] == 0) { rat_spr [front_end_id][context_id][re_log] = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); @@ -157,5 +171,5 @@ } } - } +// } } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp (revision 112) @@ -49,5 +49,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -59,5 +59,5 @@ // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("insert",OUT, EAST, "insert's interface", _param->_nb_inst_insert); + ALLOC1_INTERFACE_BEGIN("insert",OUT, EAST, _("insert's interface"), _param->_nb_inst_insert); ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_VAL ,"rename_val" ,Tcontrol_t,1); @@ -122,9 +122,11 @@ ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_OLD ,"NUM_REG_RE_PHY_OLD" ,Tspecial_address_t,_param->_size_special_register ); ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_NEW ,"NUM_REG_RE_PHY_NEW" ,Tspecial_address_t,_param->_size_special_register ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_insert); } // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("retire", IN, WEST, "retire's interface", _param->_nb_inst_retire); + ALLOC1_INTERFACE_BEGIN("retire", IN, WEST, _("retire's interface"), _param->_nb_inst_retire); ALLOC1_SIGNAL_IN ( in_RETIRE_VAL ,"val" ,Tcontrol_t,1); @@ -134,8 +136,11 @@ ALLOC1_SIGNAL_OUT(out_RETIRE_STAT_LIST_VAL,"stat_list_val",Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_RETIRE_STAT_LIST_ACK,"stat_list_ack",Tcontrol_t,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_retire); } #ifdef STATISTICS - ALLOC1(internal_INSERT_RENAME_ACK, Tcontrol_t,_param->_nb_inst_insert); + if (usage_is_set(_usage,USE_SYSTEMC)) + ALLOC1(internal_INSERT_RENAME_ACK, Tcontrol_t,_param->_nb_inst_insert); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-min.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-min.cfg (revision 112) @@ -8,3 +8,2 @@ 1 1 *4 #nb_reg_free 1 1 *2 #nb_bank -1 1 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1.cfg (revision 112) @@ -8,3 +8,2 @@ 1 4 *4 #nb_reg_free 8 8 *2 #nb_bank -1 2 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1a.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1a.cfg (revision 112) @@ -8,3 +8,2 @@ 1 4 *4 #nb_reg_free 8 8 *2 #nb_bank -1 2 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4a.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4a.cfg (revision 112) @@ -11,3 +11,2 @@ 4 4 *4 #nb_reg_free 8 8 *2 #nb_bank -2 2 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4b.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4b.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4b.cfg (revision 112) @@ -8,3 +8,2 @@ 4 4 *4 #nb_reg_free 8 8 *2 #nb_bank -2 2 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4c.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4c.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4c.cfg (revision 112) @@ -9,3 +9,2 @@ 4 4 *4 #nb_reg_free 8 8 *2 #nb_bank -2 2 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4d.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4d.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4d.cfg (revision 112) @@ -9,3 +9,2 @@ 4 4 *4 #nb_reg_free 8 8 *2 #nb_bank -2 2 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/src/main.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/src/main.cpp (revision 112) @@ -8,5 +8,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/include/test.h" -#define NB_PARAMS 8 +#define NB_PARAMS 7 void usage (int argc, char * argv[]) @@ -22,5 +22,5 @@ err (_(" * nb_reg_free (uint32_t)\n")); err (_(" * nb_bank (uint32_t)\n")); - err (_(" * size_read_counter (uint32_t)\n")); +// err (_(" * size_read_counter (uint32_t)\n")); exit (1); @@ -51,5 +51,5 @@ uint32_t _nb_reg_free = atoi(argv[x++]); uint32_t _nb_bank = atoi(argv[x++]); - uint32_t _size_read_counter = atoi(argv[x++]); +// uint32_t _size_read_counter = atoi(argv[x++]); int _return = EXIT_SUCCESS; @@ -65,5 +65,5 @@ _nb_reg_free , _nb_bank , - _size_read_counter , +// _size_read_counter , true //is_toplevel ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_mono_thread.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_mono_thread.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_mono_thread.cfg (revision 112) @@ -8,3 +8,2 @@ 1 4 *2 #_nb_reg_free 4 4 *2 #_nb_bank -2 2 +1 #_size_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_multi_thread.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_multi_thread.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_multi_thread.cfg (revision 112) @@ -9,3 +9,2 @@ 4 4 *2 #_nb_reg_free 4 8 *2 #_nb_bank -2 4 *2 #_size_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/main.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/main.cpp (revision 112) @@ -8,5 +8,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/include/test.h" -#define NB_PARAMS 8 +#define NB_PARAMS 7 void usage (int argc, char * argv[]) @@ -22,5 +22,4 @@ err (_(" * nb_reg_free (uint32_t)\n")); err (_(" * nb_bank (uint32_t)\n")); - err (_(" * size_counter (uint32_t)\n")); exit (1); @@ -55,5 +54,4 @@ uint32_t _nb_reg_free = atoi(argv[x++]); uint32_t _nb_bank = atoi(argv[x++]); - uint32_t _size_counter = atoi(argv[x++]); try @@ -68,5 +66,4 @@ _nb_reg_free , _nb_bank , - _size_counter , true //is_toplevel ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/test.cpp (revision 112) @@ -75,4 +75,5 @@ ALLOC1_SC_SIGNAL( in_RETIRE_VAL ," in_RETIRE_VAL ",Tcontrol_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL(out_RETIRE_ACK ,"out_RETIRE_ACK ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_RESTORE ," in_RETIRE_RESTORE ",Tcontrol_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_READ_RA ," in_RETIRE_READ_RA ",Tcontrol_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ," in_RETIRE_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_retire); @@ -121,4 +122,5 @@ INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_VAL ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_RETIRE_ACK ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_RESTORE ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_READ_RA ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire); @@ -234,6 +236,7 @@ TEST(bool, true,((gpr_status[reg]._is_free == 0) and (gpr_status[reg]._is_link == 0) and - (gpr_status[reg]._is_valid == 1) and - (gpr_status[reg]._counter == 0))); + (gpr_status[reg]._is_valid == 1)// and +// (gpr_status[reg]._counter == 0) + )); gpr_status[reg]._is_free = 1; @@ -254,6 +257,7 @@ TEST(bool, true,((spr_status[reg]._is_free == 0) and (spr_status[reg]._is_link == 0) and - (spr_status[reg]._is_valid == 1) and - (spr_status[reg]._counter == 0))); + (spr_status[reg]._is_valid == 1)// and +// (spr_status[reg]._counter == 0) + )); spr_status[reg]._is_free = 1; @@ -301,7 +305,7 @@ Tspecial_address_t re = (it_spr != free_list_spr.end())?*it_spr:0; - Tcontrol_t read_ra = (gpr_status_insert[ra]._is_link) and (gpr_status_insert[ra]._counter < _param->_max_reader); - Tcontrol_t read_rb = (gpr_status_insert[rb]._is_link) and (gpr_status_insert[rb]._counter < _param->_max_reader); - Tcontrol_t read_rc = (spr_status_insert[rc]._is_link) and (spr_status_insert[rc]._counter < _param->_max_reader); + Tcontrol_t read_ra = (gpr_status_insert[ra]._is_link); // and (gpr_status_insert[ra]._counter < _param->_max_reader); + Tcontrol_t read_rb = (gpr_status_insert[rb]._is_link); // and (gpr_status_insert[rb]._counter < _param->_max_reader); + Tcontrol_t read_rc = (spr_status_insert[rc]._is_link); // and (spr_status_insert[rc]._counter < _param->_max_reader); Tcontrol_t write_rd = (it_gpr != free_list_gpr.end()); Tcontrol_t write_re = (it_spr != free_list_spr.end()); @@ -341,7 +345,7 @@ Tspecial_address_t re_new = (rand()%(_param->_nb_special_register )) ; - Tcontrol_t read_ra = (gpr_status_retire[ra]._is_link) and (gpr_status_retire[ra]._counter > 0); - Tcontrol_t read_rb = (gpr_status_retire[rb]._is_link) and (gpr_status_retire[rb]._counter > 0); - Tcontrol_t read_rc = (spr_status_retire[rc]._is_link) and (spr_status_retire[rc]._counter > 0); + Tcontrol_t read_ra = (gpr_status_retire[ra]._is_link); // and (gpr_status_retire[ra]._counter > 0); + Tcontrol_t read_rb = (gpr_status_retire[rb]._is_link); // and (gpr_status_retire[rb]._counter > 0); + Tcontrol_t read_rc = (spr_status_retire[rc]._is_link); // and (spr_status_retire[rc]._counter > 0); Tcontrol_t write_rd = ( (gpr_status_retire[rd_old]._is_link ) and (gpr_status_retire[rd_old]._is_valid) and @@ -355,5 +359,6 @@ in_RETIRE_VAL [i]->write((rand()%100) < percent_transaction_retire); in_RETIRE_READ_RA [i]->write(read_ra ); - in_RETIRE_NUM_REG_RA_PHY [i]->write(ra); + in_RETIRE_RESTORE [i]->write(0); + in_RETIRE_NUM_REG_RA_PHY [i]->write(ra); in_RETIRE_READ_RB [i]->write(read_rb ); in_RETIRE_NUM_REG_RB_PHY [i]->write(rb); @@ -502,4 +507,5 @@ if (in_RETIRE_VAL [i]->read() and out_RETIRE_ACK [i]->read()) { + Tcontrol_t restore = in_RETIRE_RESTORE [i]->read(); Tcontrol_t read_ra = in_RETIRE_READ_RA [i]->read(); Tgeneral_address_t ra = in_RETIRE_NUM_REG_RA_PHY [i]->read(); @@ -518,4 +524,5 @@ LABEL("RETIRE [%d] - Accepted",i); + LABEL(" * restore : %d",restore); LABEL(" * read_ra : %d",read_ra ); LABEL(" * reg_ra : %d",ra ); @@ -575,9 +582,18 @@ if (write_rd) { - if (restore_rd_old) + if (restore) { - gpr_status[rd_old]._is_link = 1; - gpr_status[rd_new]._is_link = 0; - gpr_status[rd_new]._is_valid = 1; + if (restore_rd_old) + { + gpr_status[rd_old]._is_link = 1; + gpr_status[rd_new]._is_link = 0; + gpr_status[rd_new]._is_valid = 1; + } + else + { + gpr_status[rd_old]._is_link = 0; + gpr_status[rd_new]._is_link = 0; + gpr_status[rd_new]._is_valid = 1; + } } else @@ -586,4 +602,5 @@ gpr_status[rd_new]._is_valid = 1; } + } if (write_re) @@ -619,6 +636,7 @@ TEST(bool, true,((gpr_status[reg]._is_free == 0) and (gpr_status[reg]._is_link == 0) and - (gpr_status[reg]._is_valid == 1) and - (gpr_status[reg]._counter == 0))); + (gpr_status[reg]._is_valid == 1)// and +// (gpr_status[reg]._counter == 0) + )); gpr_status[reg]._is_free = 1; @@ -639,6 +657,7 @@ TEST(bool, true,((spr_status[reg]._is_free == 0) and (spr_status[reg]._is_link == 0) and - (spr_status[reg]._is_valid == 1) and - (spr_status[reg]._counter == 0))); + (spr_status[reg]._is_valid == 1)// and +// (spr_status[reg]._counter == 0) + )); spr_status[reg]._is_free = 1; @@ -678,4 +697,5 @@ delete [] in_RETIRE_VAL ; delete [] out_RETIRE_ACK ; + delete [] in_RETIRE_RESTORE ; delete [] in_RETIRE_READ_RA ; delete [] in_RETIRE_NUM_REG_RA_PHY ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Parameters.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Parameters.h (revision 112) @@ -34,10 +34,10 @@ public : uint32_t _nb_reg_free ; public : uint32_t _nb_bank ; - public : uint32_t _size_counter ; +//public : uint32_t _size_counter ; //public : uint32_t _size_general_register ; //public : uint32_t _size_special_register ; - public : uint32_t _max_reader ; +//public : uint32_t _max_reader ; public : uint32_t _nb_gpr_use_init ; public : uint32_t _nb_spr_use_init ; @@ -63,5 +63,5 @@ uint32_t nb_reg_free , uint32_t nb_bank , - uint32_t size_counter , +// uint32_t size_counter , bool is_toplevel=false ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h (revision 112) @@ -79,4 +79,5 @@ public : SC_IN (Tcontrol_t ) ** in_RETIRE_VAL ;//[nb_inst_retire] public : SC_OUT(Tcontrol_t ) ** out_RETIRE_ACK ;//[nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_RESTORE ;//[nb_inst_retire] public : SC_IN (Tcontrol_t ) ** in_RETIRE_READ_RA ;//[nb_inst_retire] public : SC_IN (Tgeneral_address_t) ** in_RETIRE_NUM_REG_RA_PHY ;//[nb_inst_retire] @@ -110,8 +111,8 @@ private : stat_list_entry_t ** spr_stat_list; //[nb_bank][nb_general_register_by_bank] + private : uint32_t reg_GPR_PTR_FREE; + private : uint32_t reg_SPR_PTR_FREE; + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - private : uint32_t internal_GPR_PTR_FREE; - private : uint32_t internal_SPR_PTR_FREE; - private : Tcontrol_t * internal_INSERT_ACK ;//[nb_inst_insert] private : Tcontrol_t * internal_RETIRE_ACK ;//[nb_inst_retire] @@ -154,5 +155,5 @@ public : void transition (void); public : void genMoore (void); - public : void genMealy (void); +//public : void genMealy (void); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Types.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Types.h (revision 112) @@ -25,6 +25,6 @@ public : bool _is_free ; // set = is present in free list public : bool _is_link ; // set = is present in rat - public : bool _is_valid; // set = an instruction have write in this register - public : uint32_t _counter ; // number of register that must read this register +//public : bool _is_valid; // set = an instruction have write in this register +//public : uint32_t _counter ; // number of register that must read this register public : stat_list_entry_t (void) {}; @@ -35,42 +35,46 @@ _is_free = 0; _is_link = is_link; - _is_valid = 1; - _counter = 0; +// _is_valid = 1; +// _counter = 0; } - public : void insert_read (void) - { - _counter ++; - } +// public : void insert_read (void) +// { +// _counter ++; +// } + public : void insert_write (void) { _is_free = 0; _is_link = 1; - _is_valid = 0; +// _is_valid = 0; } - public : void retire_read (void) +// public : void retire_read (void) +// { +// _counter --; +// } + + public : void retire_write_old (bool restore, bool restore_old) { - _counter --; + // restore restore_old is_link + // 0 x 0 - normal case : unallocate + // 1 0 0 - event and previous update + // 1 1 1 - event and first update + + _is_link = restore and restore_old; } - public : void retire_write_old (bool restore_old) + public : void retire_write_new (bool restore, bool restore_old) { - if (not restore_old) - { - _is_link = 0; - } - // else nothing - } + // restore restore_old is_link + // 0 x 1 - normal case : allocate + // 1 x 0 - event, need restore oldest register - public : void retire_write_new (bool restore_old) - { - if (restore_old) - { - _is_link = 0; - } + if (restore) + _is_link = 0; // in all case - _is_valid = 1; +// _is_valid = 1; } @@ -80,15 +84,16 @@ } - public : bool can_insert_read (uint32_t max_reader) - { - return ((_counter+1) < max_reader); - } +// public : bool can_insert_read (uint32_t max_reader) +// { +// return ((_counter+1) < max_reader); +// } public : bool can_free (void) { return ((_is_free == 0) and - (_is_link == 0) and -// (_is_valid == 1) and // if is_link <- 0, then retire_write_old or reset - (_counter == 0)); + (_is_link == 0) // and +// (_is_valid == 1) and // if is_link <- 0, then retire_write_old or reset +// (_counter == 0) + ); } @@ -97,7 +102,8 @@ { output << x._is_free << " " - << x._is_link << " " - << x._is_valid << " " - << x._counter; + << x._is_link // << " " +// << x._is_valid << " " +// << x._counter + ; return output; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Parameters.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Parameters.cpp (revision 112) @@ -29,5 +29,5 @@ uint32_t nb_reg_free , uint32_t nb_bank , - uint32_t size_counter , +// uint32_t size_counter , bool is_toplevel) { @@ -42,7 +42,7 @@ _nb_reg_free = nb_reg_free ; _nb_bank = nb_bank ; - _size_counter = size_counter ; +// _size_counter = size_counter ; - _max_reader = 1<_nb_inst_insert; i++) + { + internal_INSERT_ACK[i] = 1; + PORT_WRITE(out_INSERT_ACK[i], internal_INSERT_ACK[i]); + } for (uint32_t i=0; i<_param->_nb_inst_retire; i++) { @@ -101,30 +106,30 @@ # endif - log_printf(INFO,Stat_List_unit,FUNCTION,"Method - genMealy"); +// log_printf(INFO,Stat_List_unit,FUNCTION,"Method - genMealy"); - SC_METHOD (genMealy); - dont_initialize (); - sensitive << (*(in_CLOCK)).neg(); // need internal register - for (uint32_t i=0; i<_param->_nb_inst_insert; i++) - sensitive << (*(in_INSERT_READ_RA [i])) - << (*(in_INSERT_NUM_REG_RA_PHY [i])) - << (*(in_INSERT_READ_RB [i])) - << (*(in_INSERT_NUM_REG_RB_PHY [i])) - << (*(in_INSERT_READ_RC [i])) - << (*(in_INSERT_NUM_REG_RC_PHY [i])); +// SC_METHOD (genMealy); +// dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // need internal register +// for (uint32_t i=0; i<_param->_nb_inst_insert; i++) +// sensitive << (*(in_INSERT_READ_RA [i])) +// << (*(in_INSERT_NUM_REG_RA_PHY [i])) +// << (*(in_INSERT_READ_RB [i])) +// << (*(in_INSERT_NUM_REG_RB_PHY [i])) +// << (*(in_INSERT_READ_RC [i])) +// << (*(in_INSERT_NUM_REG_RC_PHY [i])); -# ifdef SYSTEMCASS_SPECIFIC - // List dependency information +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information - for (uint32_t i=0; i<_param->_nb_inst_insert; i++) - { - (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RA [i])); - (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RA_PHY [i])); - (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RB [i])); - (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RB_PHY [i])); - (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RC [i])); - (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RC_PHY [i])); - } -# endif +// for (uint32_t i=0; i<_param->_nb_inst_insert; i++) +// { +// (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RA [i])); +// (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RA_PHY [i])); +// (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RB [i])); +// (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RB_PHY [i])); +// (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RC [i])); +// (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RC_PHY [i])); +// } +// # endif #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_allocation.cpp (revision 112) @@ -49,5 +49,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -58,5 +58,5 @@ // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("insert",IN,SOUTH,"Insert a renaming result",_param->_nb_inst_insert); + ALLOC1_INTERFACE_BEGIN("insert",IN,SOUTH,_("Insert a renaming result"),_param->_nb_inst_insert); ALLOC1_VALACK_IN ( in_INSERT_VAL ,VAL); @@ -72,12 +72,15 @@ ALLOC1_SIGNAL_IN ( in_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register); + + ALLOC1_INTERFACE_END(_param->_nb_inst_insert); } // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("retire",IN,NORTH,"Retire a renaming result",_param->_nb_inst_retire); + ALLOC1_INTERFACE_BEGIN("retire",IN,NORTH,_("Retire a renaming result"),_param->_nb_inst_retire); ALLOC1_VALACK_IN ( in_RETIRE_VAL ,VAL); ALLOC1_VALACK_OUT(out_RETIRE_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_RETIRE_RESTORE ,"restore" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register); @@ -94,22 +97,28 @@ ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register); ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register); + + ALLOC1_INTERFACE_END(_param->_nb_inst_retire); } // ~~~~~[ interface : "push_gpr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("push_gpr",OUT,SOUTH,"Free a general register",_param->_nb_reg_free); + ALLOC1_INTERFACE_BEGIN("push_gpr",OUT,SOUTH,_("Free a general register"),_param->_nb_reg_free); ALLOC1_VALACK_OUT(out_PUSH_GPR_VAL ,VAL); ALLOC1_VALACK_IN ( in_PUSH_GPR_ACK ,ACK); ALLOC1_SIGNAL_OUT(out_PUSH_GPR_NUM_REG,"num_reg",Tgeneral_address_t,_param->_size_general_register); + + ALLOC1_INTERFACE_END(_param->_nb_reg_free); } // ~~~~~[ interface : "push_spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("push_spr",OUT,SOUTH,"Free a special register",_param->_nb_reg_free); + ALLOC1_INTERFACE_BEGIN("push_spr",OUT,SOUTH,_("Free a special register"),_param->_nb_reg_free); ALLOC1_VALACK_OUT(out_PUSH_SPR_VAL ,VAL); ALLOC1_VALACK_IN ( in_PUSH_SPR_ACK ,ACK); ALLOC1_SIGNAL_OUT(out_PUSH_SPR_NUM_REG,"num_reg",Tspecial_address_t,_param->_size_special_register); + + ALLOC1_INTERFACE_END(_param->_nb_reg_free); } @@ -117,19 +126,12 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - gpr_stat_list = new stat_list_entry_t * [_param->_nb_bank]; - spr_stat_list = new stat_list_entry_t * [_param->_nb_bank]; - - for (uint32_t i=0; i<_param->_nb_bank; i++) - { - gpr_stat_list [i] = new stat_list_entry_t [_param->_nb_general_register_by_bank]; - spr_stat_list [i] = new stat_list_entry_t [_param->_nb_special_register_by_bank]; - } - - internal_INSERT_ACK = new Tcontrol_t [_param->_nb_inst_insert]; - internal_RETIRE_ACK = new Tcontrol_t [_param->_nb_inst_retire]; - internal_PUSH_GPR_VAL = new Tcontrol_t [_param->_nb_reg_free]; - internal_PUSH_GPR_NUM_BANK = new uint32_t [_param->_nb_reg_free]; - internal_PUSH_SPR_VAL = new Tcontrol_t [_param->_nb_reg_free]; - internal_PUSH_SPR_NUM_BANK = new uint32_t [_param->_nb_reg_free]; + ALLOC2(gpr_stat_list,stat_list_entry_t,_param->_nb_bank,_param->_nb_general_register_by_bank); + ALLOC2(spr_stat_list,stat_list_entry_t,_param->_nb_bank,_param->_nb_special_register_by_bank); + ALLOC1(internal_INSERT_ACK ,Tcontrol_t,_param->_nb_inst_insert); + ALLOC1(internal_RETIRE_ACK ,Tcontrol_t,_param->_nb_inst_retire); + ALLOC1(internal_PUSH_GPR_VAL ,Tcontrol_t,_param->_nb_reg_free); + ALLOC1(internal_PUSH_GPR_NUM_BANK,uint32_t ,_param->_nb_reg_free); + ALLOC1(internal_PUSH_SPR_VAL ,Tcontrol_t,_param->_nb_reg_free); + ALLOC1(internal_PUSH_SPR_NUM_BANK,uint32_t ,_param->_nb_reg_free); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -29,55 +30,52 @@ delete in_NRESET; - delete [] in_INSERT_VAL ; - delete [] out_INSERT_ACK ; - delete [] in_INSERT_READ_RA ; - delete [] in_INSERT_NUM_REG_RA_PHY ; - delete [] in_INSERT_READ_RB ; - delete [] in_INSERT_NUM_REG_RB_PHY ; - delete [] in_INSERT_READ_RC ; - delete [] in_INSERT_NUM_REG_RC_PHY ; - delete [] in_INSERT_WRITE_RD ; - delete [] in_INSERT_NUM_REG_RD_PHY_NEW; - delete [] in_INSERT_WRITE_RE ; - delete [] in_INSERT_NUM_REG_RE_PHY_NEW; + DELETE1_SIGNAL( in_INSERT_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_READ_RA ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register); + DELETE1_SIGNAL( in_INSERT_READ_RB ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register); + DELETE1_SIGNAL( in_INSERT_READ_RC ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register); + DELETE1_SIGNAL( in_INSERT_WRITE_RD ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_INSERT_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert,_param->_size_general_register); + DELETE1_SIGNAL( in_INSERT_WRITE_RE ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_INSERT_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert,_param->_size_special_register); - delete [] in_RETIRE_VAL ; - delete [] out_RETIRE_ACK ; - delete [] in_RETIRE_READ_RA ; - delete [] in_RETIRE_NUM_REG_RA_PHY ; - delete [] in_RETIRE_READ_RB ; - delete [] in_RETIRE_NUM_REG_RB_PHY ; - delete [] in_RETIRE_READ_RC ; - delete [] in_RETIRE_NUM_REG_RC_PHY ; - delete [] in_RETIRE_WRITE_RD ; - delete [] in_RETIRE_RESTORE_RD_PHY_OLD; - delete [] in_RETIRE_NUM_REG_RD_PHY_OLD; - delete [] in_RETIRE_NUM_REG_RD_PHY_NEW; - delete [] in_RETIRE_WRITE_RE ; - delete [] in_RETIRE_RESTORE_RE_PHY_OLD; - delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; - delete [] in_RETIRE_NUM_REG_RE_PHY_NEW; + DELETE1_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_RETIRE_RESTORE ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_READ_RA ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire,_param->_size_general_register); + DELETE1_SIGNAL( in_RETIRE_READ_RB ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RB_PHY ,_param->_nb_inst_retire,_param->_size_general_register); + DELETE1_SIGNAL( in_RETIRE_READ_RC ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RC_PHY ,_param->_nb_inst_retire,_param->_size_special_register); + DELETE1_SIGNAL( in_RETIRE_WRITE_RD ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire,_param->_size_general_register); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW,_param->_nb_inst_retire,_param->_size_general_register); + DELETE1_SIGNAL( in_RETIRE_WRITE_RE ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire,_param->_size_special_register); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire,_param->_size_special_register); - delete [] out_PUSH_GPR_VAL ; - delete [] in_PUSH_GPR_ACK ; + DELETE1_SIGNAL(out_PUSH_GPR_VAL ,_param->_nb_reg_free,1); + DELETE1_SIGNAL( in_PUSH_GPR_ACK ,_param->_nb_reg_free,1); + DELETE1_SIGNAL(out_PUSH_GPR_NUM_REG,_param->_nb_reg_free,_param->_size_general_register); - delete [] out_PUSH_GPR_NUM_REG ; - delete [] out_PUSH_SPR_VAL ; - delete [] in_PUSH_SPR_ACK ; - delete [] out_PUSH_SPR_NUM_REG ; - - // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - delete [] gpr_stat_list; - delete [] spr_stat_list; - - delete [] internal_INSERT_ACK ; - delete [] internal_RETIRE_ACK ; - delete [] internal_PUSH_GPR_VAL ; - delete [] internal_PUSH_GPR_NUM_BANK; - delete [] internal_PUSH_SPR_VAL ; - delete [] internal_PUSH_SPR_NUM_BANK; + DELETE1_SIGNAL(out_PUSH_SPR_VAL ,_param->_nb_reg_free,1); + DELETE1_SIGNAL( in_PUSH_SPR_ACK ,_param->_nb_reg_free,1); + DELETE1_SIGNAL(out_PUSH_SPR_NUM_REG,_param->_nb_reg_free,_param->_size_special_register); + + DELETE2(gpr_stat_list ,_param->_nb_bank,_param->_nb_general_register_by_bank); + DELETE2(spr_stat_list ,_param->_nb_bank,_param->_nb_special_register_by_bank); + DELETE1(internal_INSERT_ACK ,_param->_nb_inst_insert); + DELETE1(internal_RETIRE_ACK ,_param->_nb_inst_retire); + DELETE1(internal_PUSH_GPR_VAL ,_param->_nb_reg_free); + DELETE1(internal_PUSH_GPR_NUM_BANK,_param->_nb_reg_free); + DELETE1(internal_PUSH_SPR_VAL ,_param->_nb_reg_free); + DELETE1(internal_PUSH_SPR_NUM_BANK,_param->_nb_reg_free); } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMealy.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMealy.cpp (revision 112) @@ -19,45 +19,45 @@ -#undef FUNCTION -#define FUNCTION "Stat_List_unit::genMealy" - void Stat_List_unit::genMealy (void) - { - log_begin(Stat_List_unit,FUNCTION); - log_function(Stat_List_unit,FUNCTION,_name.c_str()); +// #undef FUNCTION +// #define FUNCTION "Stat_List_unit::genMealy" +// void Stat_List_unit::genMealy (void) +// { +// log_begin(Stat_List_unit,FUNCTION); +// log_function(Stat_List_unit,FUNCTION,_name.c_str()); - for (uint32_t i=0; i<_param->_nb_inst_insert; i++) - { - bool ack = true; +// for (uint32_t i=0; i<_param->_nb_inst_insert; i++) +// { +// bool ack = true; - if (PORT_READ(in_INSERT_READ_RA [i])) - { - Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); - uint32_t bank = num_reg >> _param->_shift_gpr; - uint32_t reg = num_reg & _param->_mask_gpr ; - ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader); - } +// if (PORT_READ(in_INSERT_READ_RA [i])) +// { +// Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); +// uint32_t bank = num_reg >> _param->_shift_gpr; +// uint32_t reg = num_reg & _param->_mask_gpr ; +// ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader); +// } - if (PORT_READ(in_INSERT_READ_RB [i])) - { - Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); - uint32_t bank = num_reg >> _param->_shift_gpr; - uint32_t reg = num_reg & _param->_mask_gpr ; - ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader); - } +// if (PORT_READ(in_INSERT_READ_RB [i])) +// { +// Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); +// uint32_t bank = num_reg >> _param->_shift_gpr; +// uint32_t reg = num_reg & _param->_mask_gpr ; +// ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader); +// } - if (PORT_READ(in_INSERT_READ_RC [i])) - { - Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); - uint32_t bank = num_reg >> _param->_shift_spr; - uint32_t reg = num_reg & _param->_mask_spr ; - ack &= spr_stat_list [bank][reg].can_insert_read(_param->_max_reader); - } +// if (PORT_READ(in_INSERT_READ_RC [i])) +// { +// Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); +// uint32_t bank = num_reg >> _param->_shift_spr; +// uint32_t reg = num_reg & _param->_mask_spr ; +// ack &= spr_stat_list [bank][reg].can_insert_read(_param->_max_reader); +// } - internal_INSERT_ACK [i] = ack; - PORT_WRITE(out_INSERT_ACK [i], ack); - } +// internal_INSERT_ACK [i] = ack; +// PORT_WRITE(out_INSERT_ACK [i], ack); +// } - log_end(Stat_List_unit,FUNCTION); - }; +// log_end(Stat_List_unit,FUNCTION); +// }; }; // end namespace stat_list_unit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMoore.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMoore.cpp (revision 112) @@ -26,6 +26,6 @@ log_function(Stat_List_unit,FUNCTION,_name.c_str()); - uint32_t gpr_ptr = internal_GPR_PTR_FREE; - uint32_t spr_ptr = internal_SPR_PTR_FREE; + uint32_t gpr_ptr = reg_GPR_PTR_FREE; + uint32_t spr_ptr = reg_SPR_PTR_FREE; for (uint32_t i=0; i<_param->_nb_reg_free; i++) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp (revision 112) @@ -38,6 +38,6 @@ spr_stat_list [i][j].reset((spr++)<_param->_nb_spr_use_init); } - internal_GPR_PTR_FREE = 0; - internal_SPR_PTR_FREE = 0; + reg_GPR_PTR_FREE = 0; + reg_SPR_PTR_FREE = 0; } else @@ -51,36 +51,36 @@ log_printf(TRACE,Stat_List_unit,FUNCTION," * INSERT [%d]",i); - if (PORT_READ(in_INSERT_READ_RA [i])) - { - Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); - - log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); - - uint32_t bank = num_reg >> _param->_shift_gpr; - uint32_t reg = num_reg & _param->_mask_gpr ; - gpr_stat_list [bank][reg].insert_read(); - } - - if (PORT_READ(in_INSERT_READ_RB [i])) - { - Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); - - log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg); - - uint32_t bank = num_reg >> _param->_shift_gpr; - uint32_t reg = num_reg & _param->_mask_gpr ; - gpr_stat_list [bank][reg].insert_read(); - } - - if (PORT_READ(in_INSERT_READ_RC [i])) - { - Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); - - log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); - - uint32_t bank = num_reg >> _param->_shift_spr; - uint32_t reg = num_reg & _param->_mask_spr ; - spr_stat_list [bank][reg].insert_read(); - } +// if (PORT_READ(in_INSERT_READ_RA [i])) +// { +// Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); + +// log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); + +// uint32_t bank = num_reg >> _param->_shift_gpr; +// uint32_t reg = num_reg & _param->_mask_gpr ; +// gpr_stat_list [bank][reg].insert_read(); +// } + +// if (PORT_READ(in_INSERT_READ_RB [i])) +// { +// Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); + +// log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg); + +// uint32_t bank = num_reg >> _param->_shift_gpr; +// uint32_t reg = num_reg & _param->_mask_gpr ; +// gpr_stat_list [bank][reg].insert_read(); +// } + +// if (PORT_READ(in_INSERT_READ_RC [i])) +// { +// Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); + +// log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); + +// uint32_t bank = num_reg >> _param->_shift_spr; +// uint32_t reg = num_reg & _param->_mask_spr ; +// spr_stat_list [bank][reg].insert_read(); +// } if (PORT_READ(in_INSERT_WRITE_RD [i])) @@ -88,5 +88,5 @@ Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [i]); - log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg : %d",num_reg); + log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg new : %d",num_reg); uint32_t bank = num_reg >> _param->_shift_gpr; @@ -97,7 +97,7 @@ if (PORT_READ(in_INSERT_WRITE_RE [i])) { - Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]); - - log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg : %d",num_reg); + Tspecial_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg new : %d",num_reg); uint32_t bank = num_reg >> _param->_shift_spr; @@ -115,36 +115,40 @@ log_printf(TRACE,Stat_List_unit,FUNCTION," * RETIRE [%d]",i); - if (PORT_READ(in_RETIRE_READ_RA [i])) - { - Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RA_PHY [i]); - - log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); - - uint32_t bank = num_reg >> _param->_shift_gpr; - uint32_t reg = num_reg & _param->_mask_gpr ; - gpr_stat_list [bank][reg].retire_read(); - } - - if (PORT_READ(in_RETIRE_READ_RB [i])) - { - Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RB_PHY [i]); - - log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RD - num_reg : %d",num_reg); - - uint32_t bank = num_reg >> _param->_shift_gpr; - uint32_t reg = num_reg & _param->_mask_gpr ; - gpr_stat_list [bank][reg].retire_read(); - } - - if (PORT_READ(in_RETIRE_READ_RC [i])) - { - Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RC_PHY [i]); - - log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); - - uint32_t bank = num_reg >> _param->_shift_spr; - uint32_t reg = num_reg & _param->_mask_spr ; - spr_stat_list [bank][reg].retire_read(); - } + Tcontrol_t restore = PORT_READ(in_RETIRE_RESTORE [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * restore : %d",restore); + +// if (PORT_READ(in_RETIRE_READ_RA [i])) +// { +// Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RA_PHY [i]); + +// log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); + +// uint32_t bank = num_reg >> _param->_shift_gpr; +// uint32_t reg = num_reg & _param->_mask_gpr ; +// gpr_stat_list [bank][reg].retire_read(); +// } + +// if (PORT_READ(in_RETIRE_READ_RB [i])) +// { +// Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RB_PHY [i]); + +// log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg); + +// uint32_t bank = num_reg >> _param->_shift_gpr; +// uint32_t reg = num_reg & _param->_mask_gpr ; +// gpr_stat_list [bank][reg].retire_read(); +// } + +// if (PORT_READ(in_RETIRE_READ_RC [i])) +// { +// Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RC_PHY [i]); + +// log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); + +// uint32_t bank = num_reg >> _param->_shift_spr; +// uint32_t reg = num_reg & _param->_mask_spr ; +// spr_stat_list [bank][reg].retire_read(); +// } if (PORT_READ(in_RETIRE_WRITE_RD [i])) @@ -157,18 +161,18 @@ Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); - log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg_old : %d",num_reg); + log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_old : %d",num_reg); uint32_t bank = num_reg >> _param->_shift_gpr; uint32_t reg = num_reg & _param->_mask_gpr ; - gpr_stat_list [bank][reg].retire_write_old(restore_old); + gpr_stat_list [bank][reg].retire_write_old(restore, restore_old); } { Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); - log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg_new : %d",num_reg); + log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_new : %d",num_reg); uint32_t bank = num_reg >> _param->_shift_gpr; uint32_t reg = num_reg & _param->_mask_gpr ; - gpr_stat_list [bank][reg].retire_write_new(restore_old); + gpr_stat_list [bank][reg].retire_write_new(restore, restore_old); } } @@ -181,20 +185,20 @@ { - Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); - - log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg_new : %d",num_reg); + Tspecial_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_old : %d",num_reg); uint32_t bank = num_reg >> _param->_shift_spr; uint32_t reg = num_reg & _param->_mask_spr ; - spr_stat_list [bank][reg].retire_write_old(restore_old); + spr_stat_list [bank][reg].retire_write_old(restore, restore_old); } { - Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); - - log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg_new : %d",num_reg); + Tspecial_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_new : %d",num_reg); uint32_t bank = num_reg >> _param->_shift_spr; uint32_t reg = num_reg & _param->_mask_spr ; - spr_stat_list [bank][reg].retire_write_new(restore_old); + spr_stat_list [bank][reg].retire_write_new(restore, restore_old); } } @@ -207,5 +211,5 @@ // ===================================================== if (internal_PUSH_GPR_VAL [i] and PORT_READ(in_PUSH_GPR_ACK [i])) - gpr_stat_list[internal_PUSH_GPR_NUM_BANK [i]][internal_GPR_PTR_FREE].free(); + gpr_stat_list[internal_PUSH_GPR_NUM_BANK [i]][reg_GPR_PTR_FREE].free(); // ===================================================== @@ -213,36 +217,81 @@ // ===================================================== if (internal_PUSH_SPR_VAL [i] and PORT_READ(in_PUSH_SPR_ACK [i])) - spr_stat_list[internal_PUSH_SPR_NUM_BANK [i]][internal_SPR_PTR_FREE].free(); + spr_stat_list[internal_PUSH_SPR_NUM_BANK [i]][reg_SPR_PTR_FREE].free(); } // Update pointer - internal_GPR_PTR_FREE = ((internal_GPR_PTR_FREE==0)?_param->_nb_general_register_by_bank:internal_GPR_PTR_FREE)-1; - internal_SPR_PTR_FREE = ((internal_SPR_PTR_FREE==0)?_param->_nb_special_register_by_bank:internal_SPR_PTR_FREE)-1; + reg_GPR_PTR_FREE = ((reg_GPR_PTR_FREE==0)?_param->_nb_general_register_by_bank:reg_GPR_PTR_FREE)-1; + reg_SPR_PTR_FREE = ((reg_SPR_PTR_FREE==0)?_param->_nb_special_register_by_bank:reg_SPR_PTR_FREE)-1; } #if (DEBUG >= DEBUG_TRACE) - log_printf(TRACE,Stat_List_unit,FUNCTION," * Dump Stat List"); - for (uint32_t i=0; i<_param->_nb_bank; i++) - for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) - log_printf(TRACE,Stat_List_unit,FUNCTION," * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, valid %.1d, counter %.4d", - i, - j, - (i<<_param->_shift_gpr)|j, - gpr_stat_list[i][j]._is_free, - gpr_stat_list[i][j]._is_link, - gpr_stat_list[i][j]._is_valid, - gpr_stat_list[i][j]._counter); - for (uint32_t i=0; i<_param->_nb_bank; i++) - for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) - log_printf(TRACE,Stat_List_unit,FUNCTION," * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, valid %.1d, counter %.4d", - i, - j, - (i<<_param->_shift_spr)|j, - spr_stat_list[i][j]._is_free, - spr_stat_list[i][j]._is_link, - spr_stat_list[i][j]._is_valid, - spr_stat_list[i][j]._counter); + { + log_printf(TRACE,Stat_List_unit,FUNCTION," * Dump Stat List"); + log_printf(TRACE,Stat_List_unit,FUNCTION," * reg_GPR_PTR_FREE : %d",reg_GPR_PTR_FREE); + log_printf(TRACE,Stat_List_unit,FUNCTION," * reg_SPR_PTR_FREE : %d",reg_SPR_PTR_FREE); + + for (uint32_t i=0; i<_param->_nb_bank; i++) + for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) + log_printf(TRACE,Stat_List_unit,FUNCTION," * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d", + i, + j, + (i<<_param->_shift_gpr)|j, + gpr_stat_list[i][j]._is_free, + gpr_stat_list[i][j]._is_link// , +// gpr_stat_list[i][j]._is_valid, +// gpr_stat_list[i][j]._counter + ); + for (uint32_t i=0; i<_param->_nb_bank; i++) + for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) + log_printf(TRACE,Stat_List_unit,FUNCTION," * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d", + i, + j, + (i<<_param->_shift_spr)|j, + spr_stat_list[i][j]._is_free, + spr_stat_list[i][j]._is_link// , +// spr_stat_list[i][j]._is_valid, +// spr_stat_list[i][j]._counter + ); + } #endif + +#ifdef DEBUG_TEST +# if 0 + { + uint32_t size_rob = 64; + uint32_t nb_context = 1; + + { + uint32_t nb_is_link = 0; + uint32_t nb_reg = 32; + for (uint32_t i=0; i<_param->_nb_bank; i++) + for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) + if (gpr_stat_list[i][j]._is_link) + nb_is_link ++; + + log_printf(TRACE,Stat_List_unit,FUNCTION," * nb_GPR_IS_LINK : %d",nb_is_link); + + if (nb_is_link > size_rob+nb_context*nb_reg) + throw ERRORMORPHEO(FUNCTION,toString(_("They are %d linked gpr register, but max is size_rob+nb_context*%d = %d+%d*%d = %d"),nb_is_link,nb_reg,size_rob,nb_context,nb_reg,size_rob+nb_context*nb_reg)); + } + + { + uint32_t nb_is_link = 0; + uint32_t nb_reg = 2; + for (uint32_t i=0; i<_param->_nb_bank; i++) + for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) + if (spr_stat_list[i][j]._is_link) + nb_is_link ++; + + log_printf(TRACE,Stat_List_unit,FUNCTION," * nb_SPR_IS_LINK : %d",nb_is_link); + + if (nb_is_link > size_rob+nb_context*nb_reg) + throw ERRORMORPHEO(FUNCTION,toString(_("They are %d linked spr register, but max is size_rob+nb_context*%d = %d+%d*%d = %d"),nb_is_link,nb_reg,size_rob,nb_context,nb_reg,size_rob+nb_context*nb_reg)); + } + } +# endif +#endif + #if defined(STATISTICS) or defined(VHDL_TESTBENCH) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Parameters.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Parameters.h (revision 112) @@ -38,5 +38,5 @@ public : uint32_t _nb_reg_free ; public : uint32_t _nb_bank ; - public : uint32_t _size_read_counter ; +//public : uint32_t _size_read_counter ; //public : uint32_t _size_front_end_id ; @@ -62,5 +62,5 @@ uint32_t nb_reg_free , uint32_t nb_bank , - uint32_t size_read_counter , +// uint32_t size_read_counter , bool is_toplevel=false); // public : Parameters (Parameters & param) ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters.cpp (revision 112) @@ -28,5 +28,5 @@ uint32_t nb_reg_free , uint32_t nb_bank , - uint32_t size_read_counter , +// uint32_t size_read_counter , bool is_toplevel) { @@ -41,5 +41,5 @@ _nb_reg_free = nb_reg_free ; _nb_bank = nb_bank ; - _size_read_counter = size_read_counter ; +// _size_read_counter = size_read_counter ; uint32_t size_general_register = log2(nb_general_register); @@ -83,6 +83,7 @@ _nb_inst_retire , _nb_reg_free , - _nb_bank , - _size_read_counter ); + _nb_bank // , +// _size_read_counter + ); _param_register_translation_unit_glue = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::register_translation_unit_glue::Parameters Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters_print.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters_print.cpp (revision 112) @@ -34,5 +34,5 @@ xml.singleton_begin("nb_reg_free "); xml.attribut("value",toString(_nb_reg_free )); xml.singleton_end(); xml.singleton_begin("nb_bank "); xml.attribut("value",toString(_nb_bank )); xml.singleton_end(); - xml.singleton_begin("size_read_counter "); xml.attribut("value",toString(_size_read_counter )); xml.singleton_end(); +// xml.singleton_begin("size_read_counter "); xml.attribut("value",toString(_size_read_counter )); xml.singleton_end(); for (uint32_t i=0;i<_nb_front_end; i++) { Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp (revision 112) @@ -58,5 +58,5 @@ // ~~~~~[ Interface "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("rename", IN, EAST, "Instruction with logical register", _param->_nb_inst_insert); + ALLOC1_INTERFACE_BEGIN("rename", IN, EAST, _("Instruction with logical register"), _param->_nb_inst_insert); ALLOC1_VALACK_IN ( in_RENAME_VAL ,VAL); @@ -74,9 +74,11 @@ ALLOC1_SIGNAL_IN ( in_RENAME_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_RENAME_NUM_REG_RE_LOG,"num_reg_re_log",Tspecial_address_t,_param->_size_special_register_logic); + + ALLOC1_INTERFACE_END(_param->_nb_inst_insert); } // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("insert",OUT,WEST , "Instruction with physical register", _param->_nb_inst_insert); + ALLOC1_INTERFACE_BEGIN("insert",OUT,WEST , _("Instruction with physical register"), _param->_nb_inst_insert); ALLOC1_VALACK_OUT(out_INSERT_VAL ,VAL); @@ -101,9 +103,12 @@ ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register ); ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_insert); } // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("retire",IN ,NORTH, "Retire instruction, update renaming structure.", _param->_nb_inst_retire); + ALLOC1_INTERFACE_BEGIN("retire",IN ,NORTH, _("Retire instruction, update renaming structure."), _param->_nb_inst_retire); + ALLOC1_VALACK_IN ( in_RETIRE_VAL ,VAL); ALLOC1_VALACK_OUT(out_RETIRE_ACK ,ACK); @@ -124,13 +129,17 @@ ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register ); ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_retire); } // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } @@ -362,4 +371,6 @@ COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RESTORE_RE_PHY_OLD", dest, "in_RETIRE_"+toString(i)+"_RESTORE_RE_PHY_OLD"); + COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RESTORE" , + dest, "in_RETIRE_"+toString(i)+"_RESTORE" ); } @@ -671,4 +682,5 @@ // in_RETIRE_RESTORE_RD_PHY_OLD - register_address_translation_unit.out_RETIRE_RESTORE_RD_PHY_OLD // in_RETIRE_RESTORE_RE_PHY_OLD - register_address_translation_unit.out_RETIRE_RESTORE_RE_PHY_OLD + // in_RETIRE_RESTORE - register_address_translation_unit.out_RETIRE_RESTORE dest = _name+"_register_translation_unit_glue"; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp (revision 112) @@ -29,65 +29,59 @@ delete in_NRESET; - delete [] in_RENAME_VAL ; - delete [] out_RENAME_ACK ; - if (_param->_have_port_front_end_id) - delete [] in_RENAME_FRONT_END_ID ; - if (_param->_have_port_context_id) - delete [] in_RENAME_CONTEXT_ID ; - delete [] in_RENAME_READ_RA ; - delete [] in_RENAME_NUM_REG_RA_LOG ; - delete [] in_RENAME_READ_RB ; - delete [] in_RENAME_NUM_REG_RB_LOG ; - delete [] in_RENAME_READ_RC ; - delete [] in_RENAME_NUM_REG_RC_LOG ; - delete [] in_RENAME_WRITE_RD ; - delete [] in_RENAME_NUM_REG_RD_LOG ; - delete [] in_RENAME_WRITE_RE ; - delete [] in_RENAME_NUM_REG_RE_LOG ; + DELETE1_SIGNAL( in_RENAME_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_RENAME_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_RENAME_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id ); + DELETE1_SIGNAL( in_RENAME_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); + DELETE1_SIGNAL( in_RENAME_READ_RA ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_RENAME_NUM_REG_RA_LOG,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_RENAME_READ_RB ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_RENAME_NUM_REG_RB_LOG,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_RENAME_READ_RC ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_RENAME_NUM_REG_RC_LOG,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL( in_RENAME_WRITE_RD ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_RENAME_NUM_REG_RD_LOG,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_RENAME_WRITE_RE ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_RENAME_NUM_REG_RE_LOG,_param->_nb_inst_insert,_param->_size_special_register_logic); - delete [] out_INSERT_VAL ; - delete [] in_INSERT_ACK ; - if (_param->_have_port_front_end_id) - delete [] out_INSERT_FRONT_END_ID ; - if (_param->_have_port_context_id) - delete [] out_INSERT_CONTEXT_ID ; - delete [] out_INSERT_READ_RA ; - delete [] out_INSERT_NUM_REG_RA_LOG ; - delete [] out_INSERT_NUM_REG_RA_PHY ; - delete [] out_INSERT_READ_RB ; - delete [] out_INSERT_NUM_REG_RB_LOG ; - delete [] out_INSERT_NUM_REG_RB_PHY ; - delete [] out_INSERT_READ_RC ; - delete [] out_INSERT_NUM_REG_RC_LOG ; - delete [] out_INSERT_NUM_REG_RC_PHY ; - delete [] out_INSERT_WRITE_RD ; - delete [] out_INSERT_NUM_REG_RD_LOG ; - delete [] out_INSERT_NUM_REG_RD_PHY_OLD; - delete [] out_INSERT_NUM_REG_RD_PHY_NEW; - delete [] out_INSERT_WRITE_RE ; - delete [] out_INSERT_NUM_REG_RE_LOG ; - delete [] out_INSERT_NUM_REG_RE_PHY_OLD; - delete [] out_INSERT_NUM_REG_RE_PHY_NEW; + DELETE1_SIGNAL(out_INSERT_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id ); + DELETE1_SIGNAL(out_INSERT_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); + DELETE1_SIGNAL(out_INSERT_READ_RA ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RA_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_READ_RB ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RB_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_READ_RC ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RC_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register ); + DELETE1_SIGNAL(out_INSERT_WRITE_RD ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RD_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_WRITE_RE ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RE_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert,_param->_size_special_register ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert,_param->_size_special_register ); - delete [] in_RETIRE_VAL ; - delete [] out_RETIRE_ACK ; - if (_param->_have_port_front_end_id) - delete [] in_RETIRE_FRONT_END_ID ; - if (_param->_have_port_context_id) - delete [] in_RETIRE_CONTEXT_ID ; - delete [] in_RETIRE_READ_RA ; - delete [] in_RETIRE_NUM_REG_RA_PHY ; - delete [] in_RETIRE_READ_RB ; - delete [] in_RETIRE_NUM_REG_RB_PHY ; - delete [] in_RETIRE_READ_RC ; - delete [] in_RETIRE_NUM_REG_RC_PHY ; - delete [] in_RETIRE_WRITE_RD ; - delete [] in_RETIRE_NUM_REG_RD_LOG ; - delete [] in_RETIRE_NUM_REG_RD_PHY_OLD; - delete [] in_RETIRE_NUM_REG_RD_PHY_NEW; - delete [] in_RETIRE_WRITE_RE ; - delete [] in_RETIRE_NUM_REG_RE_LOG ; - delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; - delete [] in_RETIRE_NUM_REG_RE_PHY_NEW; + DELETE1_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_RETIRE_FRONT_END_ID ,_param->_nb_inst_retire,_param->_size_front_end_id ); + DELETE1_SIGNAL( in_RETIRE_CONTEXT_ID ,_param->_nb_inst_retire,_param->_size_context_id ); + DELETE1_SIGNAL( in_RETIRE_READ_RA ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire,_param->_size_general_register ); + DELETE1_SIGNAL( in_RETIRE_READ_RB ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RB_PHY ,_param->_nb_inst_retire,_param->_size_general_register ); + DELETE1_SIGNAL( in_RETIRE_READ_RC ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RC_PHY ,_param->_nb_inst_retire,_param->_size_special_register ); + DELETE1_SIGNAL( in_RETIRE_WRITE_RD ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_LOG ,_param->_nb_inst_retire,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire,_param->_size_general_register ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW,_param->_nb_inst_retire,_param->_size_general_register ); + DELETE1_SIGNAL( in_RETIRE_WRITE_RE ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_LOG ,_param->_nb_inst_retire,_param->_size_special_register_logic); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire,_param->_size_special_register ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire,_param->_size_special_register ); DELETE2_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp (revision 112) @@ -58,5 +58,5 @@ // ~~~~~[ Interface : "rename_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("rename_in", IN, EAST, "output of decod's stage", _param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_INTERFACE_BEGIN("rename_in", IN, EAST, _("output of decod's stage"), _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_VALACK_IN ( in_RENAME_IN_VAL ,VAL, _param->_nb_front_end, _param->_nb_inst_decod[it1]); @@ -87,9 +87,11 @@ _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_inst_decod[it1]); } // ~~~~~[ Interface : "rename_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("rename_out", IN, EAST, "output of decod's stage", _param->_nb_inst_rename); + ALLOC1_INTERFACE_BEGIN("rename_out", IN, EAST, _("output of decod's stage"), _param->_nb_inst_rename); ALLOC1_VALACK_OUT(out_RENAME_OUT_VAL ,VAL); @@ -120,11 +122,15 @@ ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_rename); } // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp (revision 112) @@ -29,65 +29,63 @@ delete in_NRESET; - delete [] in_RENAME_IN_VAL ; - delete [] out_RENAME_IN_ACK ; - if (_param->_have_port_front_end_id) - delete [] in_RENAME_IN_FRONT_END_ID ; - if (_param->_have_port_context_id) - delete [] in_RENAME_IN_CONTEXT_ID ; - if (_param->_have_port_depth) - delete [] in_RENAME_IN_DEPTH ; - delete [] in_RENAME_IN_TYPE ; - delete [] in_RENAME_IN_OPERATION ; - delete [] in_RENAME_IN_NO_EXECUTE ; - delete [] in_RENAME_IN_IS_DELAY_SLOT ; + DELETE2_SIGNAL( in_RENAME_IN_VAL ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1); + DELETE2_SIGNAL(out_RENAME_IN_ACK ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1); + DELETE2_SIGNAL( in_RENAME_IN_FRONT_END_ID ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_front_end_id ); + DELETE2_SIGNAL( in_RENAME_IN_CONTEXT_ID ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_context_id ); + DELETE2_SIGNAL( in_RENAME_IN_DEPTH ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_depth ); + DELETE2_SIGNAL( in_RENAME_IN_TYPE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_type ); + DELETE2_SIGNAL( in_RENAME_IN_OPERATION ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_operation ); + DELETE2_SIGNAL( in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); #ifdef DEBUG - delete [] in_RENAME_IN_ADDRESS ; + DELETE2_SIGNAL( in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_instruction_address ); #endif - delete [] in_RENAME_IN_ADDRESS_NEXT ; - delete [] in_RENAME_IN_HAS_IMMEDIAT ; - delete [] in_RENAME_IN_IMMEDIAT ; - delete [] in_RENAME_IN_READ_RA ; - delete [] in_RENAME_IN_NUM_REG_RA ; - delete [] in_RENAME_IN_READ_RB ; - delete [] in_RENAME_IN_NUM_REG_RB ; - delete [] in_RENAME_IN_READ_RC ; - delete [] in_RENAME_IN_NUM_REG_RC ; - delete [] in_RENAME_IN_WRITE_RD ; - delete [] in_RENAME_IN_NUM_REG_RD ; - delete [] in_RENAME_IN_WRITE_RE ; - delete [] in_RENAME_IN_NUM_REG_RE ; - delete [] in_RENAME_IN_EXCEPTION_USE ; - delete [] in_RENAME_IN_EXCEPTION ; + DELETE2_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_instruction_address ); + DELETE2_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_RENAME_IN_READ_RA ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RA ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_register_logic); + DELETE2_SIGNAL( in_RENAME_IN_READ_RB ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RB ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_register_logic); + DELETE2_SIGNAL( in_RENAME_IN_READ_RC ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RC ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_special_register_logic); + DELETE2_SIGNAL( in_RENAME_IN_WRITE_RD ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RD ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_register_logic); + DELETE2_SIGNAL( in_RENAME_IN_WRITE_RE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_special_register_logic); + DELETE2_SIGNAL( in_RENAME_IN_EXCEPTION_USE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_exception_use ); + DELETE2_SIGNAL( in_RENAME_IN_EXCEPTION ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_exception ); + + DELETE1_SIGNAL(out_RENAME_OUT_VAL ,_param->_nb_inst_rename,1); + DELETE1_SIGNAL( in_RENAME_OUT_ACK ,_param->_nb_inst_rename,1); + DELETE1_SIGNAL(out_RENAME_OUT_FRONT_END_ID ,_param->_nb_inst_rename,_param->_size_front_end_id ); + DELETE1_SIGNAL(out_RENAME_OUT_CONTEXT_ID ,_param->_nb_inst_rename,_param->_size_context_id ); + DELETE1_SIGNAL(out_RENAME_OUT_DEPTH ,_param->_nb_inst_rename,_param->_size_depth ); + DELETE1_SIGNAL(out_RENAME_OUT_TYPE ,_param->_nb_inst_rename,_param->_size_type ); + DELETE1_SIGNAL(out_RENAME_OUT_OPERATION ,_param->_nb_inst_rename,_param->_size_operation ); + DELETE1_SIGNAL(out_RENAME_OUT_NO_EXECUTE ,_param->_nb_inst_rename,1 ); + DELETE1_SIGNAL(out_RENAME_OUT_IS_DELAY_SLOT ,_param->_nb_inst_rename,1 ); +#ifdef DEBUG + DELETE1_SIGNAL(out_RENAME_OUT_ADDRESS ,_param->_nb_inst_rename,_param->_size_instruction_address ); +#endif + DELETE1_SIGNAL(out_RENAME_OUT_ADDRESS_NEXT ,_param->_nb_inst_rename,_param->_size_instruction_address ); + DELETE1_SIGNAL(out_RENAME_OUT_HAS_IMMEDIAT ,_param->_nb_inst_rename,1 ); + DELETE1_SIGNAL(out_RENAME_OUT_IMMEDIAT ,_param->_nb_inst_rename,_param->_size_general_data ); + DELETE1_SIGNAL(out_RENAME_OUT_READ_RA ,_param->_nb_inst_rename,1 ); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RA ,_param->_nb_inst_rename,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_RENAME_OUT_READ_RB ,_param->_nb_inst_rename,1 ); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RB ,_param->_nb_inst_rename,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_RENAME_OUT_READ_RC ,_param->_nb_inst_rename,1 ); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RC ,_param->_nb_inst_rename,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_RENAME_OUT_WRITE_RD ,_param->_nb_inst_rename,1 ); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RD ,_param->_nb_inst_rename,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_RENAME_OUT_WRITE_RE ,_param->_nb_inst_rename,1 ); + DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RE ,_param->_nb_inst_rename,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_RENAME_OUT_EXCEPTION_USE ,_param->_nb_inst_rename,_param->_size_exception_use ); + DELETE1_SIGNAL(out_RENAME_OUT_EXCEPTION ,_param->_nb_inst_rename,_param->_size_exception ); - delete [] out_RENAME_OUT_VAL ; - delete [] in_RENAME_OUT_ACK ; - if (_param->_have_port_front_end_id) - delete [] out_RENAME_OUT_FRONT_END_ID ; - if (_param->_have_port_context_id) - delete [] out_RENAME_OUT_CONTEXT_ID ; - if (_param->_have_port_depth) - delete [] out_RENAME_OUT_DEPTH ; - delete [] out_RENAME_OUT_TYPE ; - delete [] out_RENAME_OUT_OPERATION ; -#ifdef DEBUG - delete [] out_RENAME_OUT_ADDRESS ; -#endif - delete [] out_RENAME_OUT_ADDRESS_NEXT ; - delete [] out_RENAME_OUT_HAS_IMMEDIAT ; - delete [] out_RENAME_OUT_IMMEDIAT ; - delete [] out_RENAME_OUT_READ_RA ; - delete [] out_RENAME_OUT_NUM_REG_RA ; - delete [] out_RENAME_OUT_READ_RB ; - delete [] out_RENAME_OUT_NUM_REG_RB ; - delete [] out_RENAME_OUT_READ_RC ; - delete [] out_RENAME_OUT_NUM_REG_RC ; - delete [] out_RENAME_OUT_WRITE_RD ; - delete [] out_RENAME_OUT_NUM_REG_RD ; - delete [] out_RENAME_OUT_WRITE_RE ; - delete [] out_RENAME_OUT_NUM_REG_RE ; - delete [] out_RENAME_OUT_EXCEPTION_USE; + DELETE2_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state); + } - DELETE2_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state); - } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete _priority; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp (revision 112) @@ -52,5 +52,5 @@ log_printf(TRACE,Rename_select,FUNCTION," * front_end[%d].inst_decod[%d]",x,y); - log_printf(TRACE,Rename_select,FUNCTION," * rename_in_val : %d",PORT_READ(in_RENAME_IN_VAL[x][y])); + log_printf(TRACE,Rename_select,FUNCTION," * in_RENAME_OUT_VAL : %d",PORT_READ(in_RENAME_IN_VAL[x][y])); log_printf(TRACE,Rename_select,FUNCTION," * previous_transaction : %d",previous_transaction[x]); @@ -63,5 +63,5 @@ ack [x][y] = PORT_READ(in_RENAME_OUT_ACK [i]); - log_printf(TRACE,Rename_select,FUNCTION," * rename_out_ack : %d",PORT_READ(in_RENAME_OUT_ACK[i])); + log_printf(TRACE,Rename_select,FUNCTION," * in_RENAME_OUT_ACK : %d",PORT_READ(in_RENAME_OUT_ACK[i])); Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_IN_FRONT_END_ID [x][y]):0; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp (revision 112) @@ -59,5 +59,5 @@ // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("insert",OUT,NORTH,_("Insert interface"),_param->_nb_inst_insert); + ALLOC1_INTERFACE_BEGIN("insert",OUT,NORTH,_("Insert interface"),_param->_nb_inst_insert); // ALLOC1_SIGNAL_OUT(out_INSERT_VAL ,"VAL" ,Tcontrol_t ,1); @@ -68,5 +68,5 @@ ALLOC1_SIGNAL_OUT(out_INSERT_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation); ALLOC1_SIGNAL_OUT(out_INSERT_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data); -// ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION_USE ,"EXCEPTION_USE" ,Texception_t ,_param->_size_exception_use); +// ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION_USE ,"EXCEPTION_USE" ,Texception_t ,_param->_size_exception_use); ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception); ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_NEW ,"NUM_REG_RE_PHY_NEW" ,Tspecial_address_t,_param->_size_special_register); @@ -78,5 +78,5 @@ ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_OPERATION ,"RENAME_SELECT_OPERATION" ,Toperation_t ,_param->_size_operation); ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_IMMEDIAT ,"RENAME_SELECT_IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data); -// ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_EXCEPTION_USE ,"RENAME_SELECT_EXCEPTION_USE" ,Texception_t ,_param->_size_exception_use); +// ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_EXCEPTION_USE ,"RENAME_SELECT_EXCEPTION_USE" ,Texception_t ,_param->_size_exception_use); ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_EXCEPTION ,"RENAME_SELECT_EXCEPTION" ,Texception_t ,_param->_size_exception); ALLOC1_SIGNAL_OUT(out_INSERT_REGISTER_TRANSLATION_VAL ,"REGISTER_TRANSLATION_VAL" ,Tcontrol_t ,1); @@ -91,9 +91,11 @@ ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_STORE_QUEUE_POINTER_TYPE ,"LOAD_STORE_QUEUE_POINTER_TYPE" ,Ttype_t ,_param->_size_type); ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_STORE_QUEUE_POINTER_OPERATION ,"LOAD_STORE_QUEUE_POINTER_OPERATION" ,Toperation_t ,_param->_size_operation); + + ALLOC1_INTERFACE_END(_param->_nb_inst_insert); } // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("retire",OUT,NORTH,_("Retire interface"),_param->_nb_inst_retire); + ALLOC1_INTERFACE_BEGIN("retire",OUT,NORTH,_("Retire interface"),_param->_nb_inst_retire); ALLOC1_SIGNAL_IN ( in_RETIRE_VAL ,"VAL" ,Tcontrol_t ,1); @@ -105,10 +107,15 @@ ALLOC1_SIGNAL_OUT(out_RETIRE_REGISTER_TRANSLATION_VAL ,"REGISTER_TRANSLATION_VAL" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_RETIRE_REGISTER_TRANSLATION_ACK ,"REGISTER_TRANSLATION_ACK" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_retire); } + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("spr_read",IN ,NORTH,_("SPR read"),_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("spr_read",IN ,NORTH,_("SPR read"),_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_SPR_READ_SR ,"SR" ,Tspr_t ,_param->_size_spr,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-min.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-min.cfg (revision 112) @@ -19,3 +19,2 @@ 1 1 +1 # nb_reg_free 1 1 +1 # nb_bank -1 1 +1 # size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_1a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_1a.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_1a.cfg (revision 112) @@ -19,3 +19,2 @@ 2 2 +1 # nb_reg_free 4 8 *2 # nb_bank -4 4 +1 # size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4a.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4a.cfg (revision 112) @@ -22,3 +22,2 @@ 2 2 +1 # nb_reg_free 8 8 *2 # nb_bank -4 4 +1 # size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4b.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4b.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4b.cfg (revision 112) @@ -25,3 +25,2 @@ 2 2 +1 # nb_reg_free 8 8 *2 # nb_bank -4 4 +1 # size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp (revision 112) @@ -8,5 +8,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/include/test.h" -#define NB_PARAMS 14 +#define NB_PARAMS 13 void usage (int argc, char * argv[]) @@ -33,5 +33,5 @@ err (_(" * nb_reg_free (uint32_t )\n")); err (_(" * nb_bank (uint32_t )\n")); - err (_(" * size_read_counter (uint32_t )\n")); +// err (_(" * size_read_counter (uint32_t )\n")); exit (1); @@ -103,5 +103,5 @@ uint32_t _nb_reg_free = fromString(argv[x++]); uint32_t _nb_bank = fromString(argv[x++]); - uint32_t _size_read_counter = fromString(argv[x++]); +// uint32_t _size_read_counter = fromString(argv[x++]); int _return = EXIT_SUCCESS; @@ -128,5 +128,5 @@ _nb_reg_free , _nb_bank , - _size_read_counter , +// _size_read_counter , true //is_toplevel ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Parameters.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Parameters.h (revision 112) @@ -47,5 +47,5 @@ public : uint32_t _nb_reg_free ; public : uint32_t _nb_bank ; - public : uint32_t _size_read_counter ; +// public : uint32_t _size_read_counter ; //public : uint32_t _size_front_end_id ; @@ -87,5 +87,5 @@ uint32_t nb_reg_free , uint32_t nb_bank , - uint32_t size_read_counter , +// uint32_t size_read_counter , bool is_toplevel=false ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters.cpp (revision 112) @@ -38,5 +38,5 @@ uint32_t nb_reg_free , uint32_t nb_bank , - uint32_t size_read_counter , +// uint32_t size_read_counter , bool is_toplevel) { @@ -61,5 +61,5 @@ _nb_reg_free = nb_reg_free ; _nb_bank = nb_bank ; - _size_read_counter = size_read_counter ; +// _size_read_counter = size_read_counter ; uint32_t size_special_register = log2(_nb_special_register); @@ -91,6 +91,6 @@ _nb_inst_retire , _nb_reg_free , - _nb_bank , - _size_read_counter + _nb_bank // , +// _size_read_counter ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters_print.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters_print.cpp (revision 112) @@ -39,5 +39,5 @@ xml.singleton_begin("nb_reg_free "); xml.attribut("value",toString(_nb_reg_free )); xml.singleton_end(); xml.singleton_begin("nb_bank "); xml.attribut("value",toString(_nb_bank )); xml.singleton_end(); - xml.singleton_begin("size_read_counter "); xml.attribut("value",toString(_size_read_counter )); xml.singleton_end(); +// xml.singleton_begin("size_read_counter "); xml.attribut("value",toString(_size_read_counter )); xml.singleton_end(); for (uint32_t i=0;i<_nb_front_end; i++) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp (revision 112) @@ -58,5 +58,5 @@ // ~~~~~[ Interface : "rename_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("rename_in", IN, EAST, "output of decod's stage", _param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_INTERFACE_BEGIN("rename_in", IN, EAST, _("output of decod's stage"), _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_VALACK_IN ( in_RENAME_IN_VAL ,VAL, _param->_nb_front_end, _param->_nb_inst_decod[it1]); @@ -87,9 +87,11 @@ _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_inst_decod[it1]); } // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("insert",OUT,WEST , "Instruction with physical register", _param->_nb_inst_insert); + ALLOC1_INTERFACE_BEGIN("insert",OUT,WEST , _("Instruction with physical register"), _param->_nb_inst_insert); ALLOC1_VALACK_OUT(out_INSERT_VAL ,VAL); @@ -129,9 +131,11 @@ ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ); ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_insert); } // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("retire",IN ,NORTH, "Retire instruction, update renaming structure.", _param->_nb_inst_retire); + ALLOC1_INTERFACE_BEGIN("retire",IN ,NORTH, _("Retire instruction, update renaming structure."), _param->_nb_inst_retire); ALLOC1_VALACK_IN ( in_RETIRE_VAL ,VAL); @@ -159,20 +163,26 @@ ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ); ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_retire); } // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("spr_read", IN,NORTH, _("Special register"), _param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("spr_read", IN,NORTH, _("Special register"), _param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN (in_SPR_READ_SR ,"sr",Tspr_t ,_param->_size_spr, _param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg (revision 112) @@ -51,5 +51,4 @@ 1 1 +1 # nb_reg_free [0] [nb_rename_unit] 1 1 +1 # nb_rename_unit_bank [0] [nb_rename_unit] -1 1 +1 # size_read_counter [0] [nb_rename_unit] 1 1 +1 # nb_load_store_queue [0] [nb_rename_unit] 2 2 +1 # size_store_queue [0][0] [nb_rename_unit][nb_load_store_queue] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp (revision 112) @@ -67,5 +67,5 @@ err (_(" * nb_reg_free [nb_rename_unit] (uint32_t )\n")); err (_(" * nb_rename_unit_bank [nb_rename_unit] (uint32_t )\n")); - err (_(" * size_read_counter [nb_rename_unit] (uint32_t )\n")); +// err (_(" * size_read_counter [nb_rename_unit] (uint32_t )\n")); err (_(" * nb_load_store_queue [nb_rename_unit] (uint32_t )\n")); err (_(" * size_store_queue [nb_rename_unit][nb_load_store_queue] (uint32_t )\n")); @@ -110,5 +110,5 @@ _nb_inst_decod [i] = fromString(argv[x++]); - if (argc <= static_cast(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+12*_nb_rename_unit+_nb_execute_loop)) + if (argc <= static_cast(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+10*_nb_rename_unit+_nb_execute_loop)) usage (argc, argv); @@ -160,5 +160,5 @@ } - if (argc <= static_cast(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+11*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue)) + if (argc <= static_cast(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+10*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue)) usage (argc, argv); @@ -195,5 +195,5 @@ uint32_t * _nb_reg_free = new uint32_t [_nb_rename_unit]; uint32_t * _nb_rename_unit_bank = new uint32_t [_nb_rename_unit]; - uint32_t * _size_read_counter = new uint32_t [_nb_rename_unit]; +// uint32_t * _size_read_counter = new uint32_t [_nb_rename_unit]; uint32_t * _nb_load_store_queue = new uint32_t [_nb_rename_unit]; @@ -212,6 +212,6 @@ for (uint32_t i=0; i<_nb_rename_unit; i++) _nb_rename_unit_bank [i] = fromString(argv[x++]); - for (uint32_t i=0; i<_nb_rename_unit; i++) - _size_read_counter [i] = fromString(argv[x++]); +// for (uint32_t i=0; i<_nb_rename_unit; i++) +// _size_read_counter [i] = fromString(argv[x++]); for (uint32_t i=0; i<_nb_rename_unit; i++) { @@ -220,5 +220,5 @@ } - if (argc != static_cast(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+11*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue+3*_sum_nb_load_store_queue)) + if (argc != static_cast(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+10*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue+3*_sum_nb_load_store_queue)) usage (argc, argv); @@ -327,5 +327,5 @@ _nb_reg_free , _nb_rename_unit_bank , - _size_read_counter , +// _size_read_counter , _nb_load_store_queue , _size_store_queue , @@ -391,5 +391,5 @@ delete [] _nb_load_store_queue ; - delete [] _size_read_counter ; +// delete [] _size_read_counter ; delete [] _nb_rename_unit_bank ; delete [] _nb_reg_free ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp (revision 112) @@ -143,16 +143,16 @@ ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ," in_BRANCH_COMPLETE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_branch_complete); - ALLOC_SC_SIGNAL (out_COMMIT_EVENT_VAL ,"out_COMMIT_EVENT_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ACK ," in_COMMIT_EVENT_ACK ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_COMMIT_EVENT_FRONT_END_ID ,"out_COMMIT_EVENT_FRONT_END_ID ",Tcontext_t ); - ALLOC_SC_SIGNAL (out_COMMIT_EVENT_CONTEXT_ID ,"out_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t ); - ALLOC_SC_SIGNAL (out_COMMIT_EVENT_DEPTH ,"out_COMMIT_EVENT_DEPTH ",Tdepth_t ); - ALLOC_SC_SIGNAL (out_COMMIT_EVENT_TYPE ,"out_COMMIT_EVENT_TYPE ",Tevent_type_t ); - ALLOC_SC_SIGNAL (out_COMMIT_EVENT_IS_DELAY_SLOT ,"out_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS ,"out_COMMIT_EVENT_ADDRESS ",Taddress_t ); - ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"out_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ,"out_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); - ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"out_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR ,"out_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t ); + ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_VAL ,"out_COMMIT_EVENT_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ACK ," in_COMMIT_EVENT_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ID ,"out_COMMIT_EVENT_FRONT_END_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_CONTEXT_ID ,"out_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_DEPTH ,"out_COMMIT_EVENT_DEPTH ",Tdepth_t ); + ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_TYPE ,"out_COMMIT_EVENT_TYPE ",Tevent_type_t ); + ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_IS_DELAY_SLOT ,"out_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS ,"out_COMMIT_EVENT_ADDRESS ",Taddress_t ); + ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"out_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR ,"out_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); + ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"out_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR ,"out_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t ); ALLOC2_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); @@ -294,19 +294,19 @@ INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); - INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_VAL ); - INSTANCE_SC_SIGNAL (_OOO_Engine, in_COMMIT_EVENT_ACK ); + INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_VAL ); + INSTANCE0_SC_SIGNAL(_OOO_Engine, in_COMMIT_EVENT_ACK ); if (_param->_have_port_front_end_id) - INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_FRONT_END_ID ); + INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_FRONT_END_ID ); if (_param->_have_port_context_id) - INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_CONTEXT_ID ); + INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_CONTEXT_ID ); if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_DEPTH ); - INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_TYPE ); - INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_IS_DELAY_SLOT ); - INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS ); - INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EPCR_VAL ); - INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EPCR ); - INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EEAR_VAL ); - INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EEAR ); + INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_DEPTH ); + INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_TYPE ); + INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_IS_DELAY_SLOT ); + INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS ); + INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EPCR_VAL ); + INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EPCR ); + INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EEAR_VAL ); + INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EEAR ); INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); @@ -472,16 +472,16 @@ DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); - DELETE_SC_SIGNAL (out_COMMIT_EVENT_VAL ); - DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ACK ); - DELETE_SC_SIGNAL (out_COMMIT_EVENT_FRONT_END_ID ); - DELETE_SC_SIGNAL (out_COMMIT_EVENT_CONTEXT_ID ); - DELETE_SC_SIGNAL (out_COMMIT_EVENT_DEPTH ); - DELETE_SC_SIGNAL (out_COMMIT_EVENT_TYPE ); - DELETE_SC_SIGNAL (out_COMMIT_EVENT_IS_DELAY_SLOT ); - DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS ); - DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR_VAL ); - DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ); - DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ); - DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR ); + DELETE0_SC_SIGNAL(out_COMMIT_EVENT_VAL ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ACK ); + DELETE0_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ID ); + DELETE0_SC_SIGNAL(out_COMMIT_EVENT_CONTEXT_ID ); + DELETE0_SC_SIGNAL(out_COMMIT_EVENT_DEPTH ); + DELETE0_SC_SIGNAL(out_COMMIT_EVENT_TYPE ); + DELETE0_SC_SIGNAL(out_COMMIT_EVENT_IS_DELAY_SLOT ); + DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS ); + DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR_VAL ); + DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR ); + DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR_VAL ); + DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR ); DELETE2_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp (revision 112) @@ -58,5 +58,5 @@ // ~~~~~[ Interface : "spr_access" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("spr_access",IN,WEST, _("Access from reexecute_unit"), _param->_nb_inst_reexecute); + ALLOC1_INTERFACE_BEGIN("spr_access",IN,WEST, _("Access from reexecute_unit"), _param->_nb_inst_reexecute); ALLOC1_VALACK_IN ( in_SPR_ACCESS_VAL ,VAL); @@ -70,16 +70,20 @@ ALLOC1_SIGNAL_OUT(out_SPR_ACCESS_RDATA ,"rdata" ,Tspr_t ,_param->_size_spr); ALLOC1_SIGNAL_OUT(out_SPR_ACCESS_INVALID ,"invalid" ,Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_inst_reexecute); } // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("spr_read",OUT,WEST, _("Output for a spr bit field."), _param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("spr_read",OUT,WEST, _("Output for a spr bit field."), _param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_OUT(out_SPR_READ_SR ,"sr",Tspr_t,_param->_size_spr, _param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } // ~~~~~[ Interface : "spr_commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("spr_commit",IN,WEST, _("Commit instruction to change SR's flags."), _param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("spr_commit",IN,WEST, _("Commit instruction to change SR's flags."), _param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_VALACK_IN ( in_SPR_COMMIT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); @@ -91,9 +95,11 @@ _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_OV_VAL ,"sr_ov_val" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_OV ,"sr_ov" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("spr_event",IN,WEST, _("Event change a lot of exception."), _param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("spr_event",IN,WEST, _("Event change a lot of exception."), _param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_VALACK_IN ( in_SPR_EVENT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); @@ -104,4 +110,6 @@ _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_DSX ,"SR_DSX" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_TO_ESR ,"SR_TO_ESR" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); } @@ -109,12 +117,7 @@ { // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - internal_SPR_ACCESS_ACK = new Tcontrol_t [_param->_nb_inst_reexecute]; - internal_SPR_COMMIT_ACK = new Tcontrol_t * [_param->_nb_front_end]; - internal_SPR_EVENT_ACK = new Tcontrol_t * [_param->_nb_front_end]; - for (uint32_t i=0; i<_param->_nb_front_end; i++) - { - internal_SPR_COMMIT_ACK [i] = new Tcontrol_t [_param->_nb_context [i]]; - internal_SPR_EVENT_ACK [i] = new Tcontrol_t [_param->_nb_context [i]]; - } + ALLOC1(internal_SPR_ACCESS_ACK ,Tcontrol_t,_param->_nb_inst_reexecute); + ALLOC2(internal_SPR_COMMIT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context [it1]); + ALLOC2(internal_SPR_EVENT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context [it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp (revision 112) @@ -59,12 +59,7 @@ // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] internal_SPR_ACCESS_ACK; - for (uint32_t i=0; i<_param->_nb_front_end; i++) - { - delete [] internal_SPR_COMMIT_ACK [i]; - delete [] internal_SPR_EVENT_ACK [i]; - } - delete [] internal_SPR_COMMIT_ACK; - delete [] internal_SPR_EVENT_ACK; + DELETE1(internal_SPR_ACCESS_ACK ,_param->_nb_inst_reexecute); + DELETE2(internal_SPR_COMMIT_ACK ,_param->_nb_front_end,_param->_nb_context [it1]); + DELETE2(internal_SPR_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context [it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h (revision 112) @@ -76,5 +76,5 @@ public : uint32_t * _nb_reg_free ;//[nb_rename_unit] public : uint32_t * _nb_rename_unit_bank ;//[nb_rename_unit] - public : uint32_t * _size_read_counter ;//[nb_rename_unit] +// public : uint32_t * _size_read_counter ;//[nb_rename_unit] public : uint32_t * _nb_load_store_queue ;//[nb_rename_unit] public : uint32_t ** _size_store_queue ;//[nb_rename_unit][nb_load_store_queue] @@ -173,5 +173,5 @@ uint32_t * nb_reg_free ,//[nb_rename_unit] uint32_t * nb_rename_unit_bank ,//[nb_rename_unit] - uint32_t * size_read_counter ,//[nb_rename_unit] +// uint32_t * size_read_counter ,//[nb_rename_unit] uint32_t * nb_load_store_queue ,//[nb_rename_unit] uint32_t ** size_store_queue ,//[nb_rename_unit][nb_load_store_queue] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 112) @@ -55,5 +55,5 @@ // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("rename",IN,WEST,_("Instruction from front_end."),_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_INTERFACE_BEGIN("rename",IN,WEST,_("Instruction from front_end."),_param->_nb_front_end,_param->_nb_inst_decod[it1]); _ALLOC2_VALACK_IN ( in_RENAME_VAL , VAL ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); @@ -84,9 +84,11 @@ _ALLOC2_SIGNAL_IN ( in_RENAME_EXCEPTION_USE ,"EXCEPTION_USE" ,Texception_t ,_param->_size_exception_use ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_inst_decod[it1]); } // ~~~~~[ Interface : "issue" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("issue",OUT,EAST,_("Instruction to execute_loop"),_param->_nb_inst_issue); + ALLOC1_INTERFACE_BEGIN("issue",OUT,EAST,_("Instruction to execute_loop"),_param->_nb_inst_issue); ALLOC1_VALACK_OUT (out_ISSUE_VAL , VAL ); @@ -111,9 +113,11 @@ ALLOC1_SIGNAL_OUT (out_ISSUE_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT (out_ISSUE_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_issue); } // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("execute_loop",IN,EAST,_("Instruction executed, from execute_loop."),_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_INTERFACE_BEGIN("execute_loop",IN,EAST,_("Instruction executed, from execute_loop."),_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); _ALLOC2_VALACK_IN ( in_EXECUTE_LOOP_VAL , VAL ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); @@ -129,9 +133,11 @@ _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_DATA ,"DATA" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); } // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("insert",OUT,EAST,_("Interface with RegisterFile's stat-list (insert Re-Order-Buffer)."),_param->_sum_inst_insert); + ALLOC1_INTERFACE_BEGIN("insert",OUT,EAST,_("Interface with RegisterFile's stat-list (insert Re-Order-Buffer)."),_param->_sum_inst_insert); ALLOC1_VALACK_OUT (out_INSERT_VAL , VAL); @@ -141,9 +147,11 @@ ALLOC1_SIGNAL_OUT (out_INSERT_RE_USE ,"RE_USE" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT (out_INSERT_RE_NUM_REG ,"RE_NUM_REG" ,Tspecial_address_t,_param->_size_special_register ); + + ALLOC1_INTERFACE_END(_param->_sum_inst_insert); } // // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // { -// ALLOC1_INTERFACE("retire",OUT,EAST,_("Interface with RegisterFile's stat-list (retire Re-Order-Buffer)."),_param->_sum_inst_retire); +// ALLOC1_INTERFACE_BEGIN("retire",OUT,EAST,_("Interface with RegisterFile's stat-list (retire Re-Order-Buffer)."),_param->_sum_inst_retire); // ALLOC1_VALACK_OUT (out_RETIRE_VAL , VAL); @@ -157,9 +165,11 @@ // ALLOC1_SIGNAL_OUT (out_RETIRE_RE_NEW_USE ,"RE_NEW_USE" ,Tcontrol_t ,1 ); // ALLOC1_SIGNAL_OUT (out_RETIRE_RE_NEW_NUM_REG ,"RE_NEW_NUM_REG" ,Tspecial_address_t,_param->_size_special_register ); + +// ALLOC1_INTERFACE_END(_param->_sum_inst_retire); // } // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("branch_complete",OUT,WEST,_("Instruction to execute_loop"),_param->_nb_inst_branch_complete); + ALLOC1_INTERFACE_BEGIN("branch_complete",OUT,WEST,_("Instruction to execute_loop"),_param->_nb_inst_branch_complete); ALLOC1_VALACK_OUT (out_BRANCH_COMPLETE_VAL , VAL); @@ -171,27 +181,31 @@ ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION ,"MISS_PREDICTION" ,Tcontrol_t ,1 ); + + ALLOC1_INTERFACE_END(_param->_nb_inst_branch_complete); } // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("commit_event",OUT,WEST,_("Commit an event (exception).")); - - ALLOC_VALACK_OUT (out_COMMIT_EVENT_VAL , VAL); - ALLOC_VALACK_IN ( in_COMMIT_EVENT_ACK , ACK); - ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ); - ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ); - ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); - ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_TYPE ,"TYPE" ,Tevent_type_t ,_param->_size_event_type ); - ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); - ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"ADDRESS_EPCR_VAL" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); - ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC0_INTERFACE_BEGIN("commit_event",OUT,WEST,_("Commit an event (exception).")); + + ALLOC0_VALACK_OUT(out_COMMIT_EVENT_VAL , VAL); + ALLOC0_VALACK_IN ( in_COMMIT_EVENT_ACK , ACK); + ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ); + ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); + ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_TYPE ,"TYPE" ,Tevent_type_t ,_param->_size_event_type ); + ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); + ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"ADDRESS_EPCR_VAL" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); + ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); + ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data ); + + ALLOC0_INTERFACE_END(); } // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("event",IN,WEST,_("Event from context_state."),_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("event",IN,WEST,_("Event from context_state."),_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_VALACK_IN ( in_EVENT_VAL , VAL ,_param->_nb_front_end,_param->_nb_context[it1]); @@ -201,9 +215,11 @@ _ALLOC2_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"ADDRESS_NEXT_VAL" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"IS_DS_TAKE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); } // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("spr_event",IN,WEST,_("Exception : save spr and set a lot of special register."),_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("spr_event",IN,WEST,_("Exception : save spr and set a lot of special register."),_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_VALACK_IN ( in_SPR_EVENT_VAL , VAL ,_param->_nb_front_end,_param->_nb_context[it1]); @@ -214,30 +230,38 @@ _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_DSX ,"SR_DSX" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_TO_ESR ,"SR_TO_ESR" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); } // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("nb_inst",OUT,WEST,_("Internal number instruction."),_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("nb_inst",OUT,WEST,_("Internal number instruction."),_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_ALL ,"COMMIT_ALL" ,Tcounter_t ,_param->_size_nb_inst_commit ,_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_MEM ,"COMMIT_MEM" ,Tcounter_t ,_param->_size_nb_inst_commit ,_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_NB_INST_DECOD_ALL ,"DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod ,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); } // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL ,"FULL" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); } // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("spr",OUT,WEST,_("SPR"),_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_INTERFACE_BEGIN("spr",OUT,WEST,_("SPR"),_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_SIGNAL_OUT(out_SPR_SR_IEE ,"SR_IEE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); _ALLOC2_SIGNAL_OUT(out_SPR_SR_EPH ,"SR_EPH" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp (revision 112) @@ -117,16 +117,16 @@ DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1 ); - DELETE_SIGNAL (out_COMMIT_EVENT_VAL , 1); - DELETE_SIGNAL ( in_COMMIT_EVENT_ACK , 1); - DELETE_SIGNAL (out_COMMIT_EVENT_FRONT_END_ID ,_param->_size_front_end_id ); - DELETE_SIGNAL (out_COMMIT_EVENT_CONTEXT_ID ,_param->_size_context_id ); - DELETE_SIGNAL (out_COMMIT_EVENT_DEPTH ,_param->_size_depth ); - DELETE_SIGNAL (out_COMMIT_EVENT_TYPE ,_param->_size_event_type ); - DELETE_SIGNAL (out_COMMIT_EVENT_IS_DELAY_SLOT ,1 ); - DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS ,_param->_size_general_data ); - DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,1 ); - DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_general_data ); - DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,1 ); - DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR ,_param->_size_general_data ); + DELETE0_SIGNAL(out_COMMIT_EVENT_VAL , 1); + DELETE0_SIGNAL( in_COMMIT_EVENT_ACK , 1); + DELETE0_SIGNAL(out_COMMIT_EVENT_FRONT_END_ID ,_param->_size_front_end_id ); + DELETE0_SIGNAL(out_COMMIT_EVENT_CONTEXT_ID ,_param->_size_context_id ); + DELETE0_SIGNAL(out_COMMIT_EVENT_DEPTH ,_param->_size_depth ); + DELETE0_SIGNAL(out_COMMIT_EVENT_TYPE ,_param->_size_event_type ); + DELETE0_SIGNAL(out_COMMIT_EVENT_IS_DELAY_SLOT ,1 ); + DELETE0_SIGNAL(out_COMMIT_EVENT_ADDRESS ,_param->_size_general_data ); + DELETE0_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,1 ); + DELETE0_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_general_data ); + DELETE0_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,1 ); + DELETE0_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR ,_param->_size_general_data ); DELETE2_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp (revision 112) @@ -63,5 +63,5 @@ uint32_t * nb_reg_free ,//[nb_rename_unit] uint32_t * nb_rename_unit_bank ,//[nb_rename_unit] - uint32_t * size_read_counter ,//[nb_rename_unit] +// uint32_t * size_read_counter ,//[nb_rename_unit] uint32_t * nb_load_store_queue ,//[nb_rename_unit] uint32_t ** size_store_queue ,//[nb_rename_unit][nb_load_store_queue] @@ -119,5 +119,5 @@ _nb_reg_free = nb_reg_free ; _nb_rename_unit_bank = nb_rename_unit_bank ; - _size_read_counter = size_read_counter ; +// _size_read_counter = size_read_counter ; _nb_load_store_queue = nb_load_store_queue ; _size_store_queue = size_store_queue ; @@ -238,6 +238,7 @@ _nb_special_register [i], _nb_reg_free [i], - _nb_rename_unit_bank [i], - _size_read_counter [i] + _nb_rename_unit_bank [i]// , +// _size_read_counter [i] + ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp (revision 112) @@ -81,6 +81,6 @@ for (uint32_t i=0; i<_nb_rename_unit; ++i) str+= toString(MSG_INFORMATION)+" * nb_rename_unit_bank ["+toString(i)+"] : "+toString(_nb_rename_unit_bank [i])+"\n";//[nb_rename_unit] - for (uint32_t i=0; i<_nb_rename_unit; ++i) - str+= toString(MSG_INFORMATION)+" * size_read_counter ["+toString(i)+"] : "+toString(_size_read_counter [i])+"\n";//[nb_rename_unit] +// for (uint32_t i=0; i<_nb_rename_unit; ++i) +// str+= toString(MSG_INFORMATION)+" * size_read_counter ["+toString(i)+"] : "+toString(_size_read_counter [i])+"\n";//[nb_rename_unit] for (uint32_t i=0; i<_nb_rename_unit; ++i) str+= toString(MSG_INFORMATION)+" * nb_load_store_queue ["+toString(i)+"] : "+toString(_nb_load_store_queue [i])+"\n";//[nb_rename_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-min.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-min.cfg (revision 112) @@ -25,5 +25,4 @@ 1 1 +1 # nb_reg_free [0] [nb_rename_bloc] 1 1 +1 # nb_rename_unit_bank [0] [nb_rename_bloc] -1 1 +1 # size_read_counter [0] [nb_rename_bloc] 1 1 +1 # nb_read_bloc 1 1 +1 # size_read_queue [0] [nb_read_bloc] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-w1a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-w1a.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-w1a.cfg (revision 112) @@ -25,5 +25,4 @@ 1 1 +1 # nb_reg_free [0] [nb_rename_bloc] 1 1 +1 # nb_rename_unit_bank [0] [nb_rename_bloc] -4 4 +1 # size_read_counter [0] [nb_rename_bloc] 1 1 +1 # nb_read_bloc 4 4 +1 # size_read_queue [0] [nb_read_bloc] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/main.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/main.cpp (revision 112) @@ -45,5 +45,5 @@ err (_(" * nb_reg_free [nb_rename_bloc] (uint32_t )\n")); err (_(" * nb_rename_unit_bank [nb_rename_bloc] (uint32_t )\n")); - err (_(" * size_read_counter [nb_rename_bloc] (uint32_t )\n")); +// err (_(" * size_read_counter [nb_rename_bloc] (uint32_t )\n")); err (_(" * nb_read_bloc (uint32_t )\n")); @@ -209,5 +209,5 @@ uint32_t * _nb_reg_free ;//[nb_rename_bloc] uint32_t * _nb_rename_unit_bank ;//[nb_rename_bloc] - uint32_t * _size_read_counter ;//[nb_rename_bloc] +// uint32_t * _size_read_counter ;//[nb_rename_bloc] // Read bloc @@ -374,5 +374,5 @@ SELFTEST0(_nb_rename_bloc ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+10*_nb_rename_bloc)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+9*_nb_rename_bloc)) usage (argc, argv); @@ -386,5 +386,5 @@ SELFTEST1(_nb_reg_free ,uint32_t ,argv,x,_nb_rename_bloc); SELFTEST1(_nb_rename_unit_bank ,uint32_t ,argv,x,_nb_rename_bloc); - SELFTEST1(_size_read_counter ,uint32_t ,argv,x,_nb_rename_bloc); +// SELFTEST1(_size_read_counter ,uint32_t ,argv,x,_nb_rename_bloc); // Read bloc @@ -392,5 +392,5 @@ SELFTEST0(_nb_read_bloc ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+9*_nb_rename_bloc+3*_nb_read_bloc)) usage (argc, argv); @@ -403,5 +403,5 @@ SELFTEST0(_nb_write_bloc ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+9*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc)) usage (argc, argv); @@ -414,5 +414,5 @@ SELFTEST0(_nb_load_store_unit ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+9*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit)) usage (argc, argv); @@ -431,5 +431,5 @@ SELFTEST0(_nb_functionnal_unit ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+9*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit)) usage (argc, argv); @@ -474,5 +474,5 @@ SELFTEST0(_nb_front_end ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+9*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end)) usage (argc, argv); @@ -501,5 +501,5 @@ SELFTEST0(_nb_ooo_engine ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+19*_nb_ooo_engine)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+9*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+19*_nb_ooo_engine)) usage (argc, argv); @@ -529,5 +529,5 @@ SELFTEST0(_nb_execute_loop ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+19*_nb_ooo_engine+11*_nb_execute_loop)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+9*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+19*_nb_ooo_engine+11*_nb_execute_loop)) usage (argc, argv); @@ -547,5 +547,5 @@ printf(" * Link\n"); - if (argc < static_cast(2+NB_PARAMS+6*_nb_thread+6*_nb_decod_bloc+11*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+19*_nb_ooo_engine+11*_nb_execute_loop)) + if (argc < static_cast(2+NB_PARAMS+6*_nb_thread+6*_nb_decod_bloc+10*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+19*_nb_ooo_engine+11*_nb_execute_loop)) usage (argc, argv); @@ -601,5 +601,5 @@ _sum_cache_port += _nb_cache_port[i]; - if (argc != static_cast(2+NB_PARAMS+6*_nb_thread+6*_nb_decod_bloc+11*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+19*_nb_ooo_engine+11*_nb_execute_loop+ + if (argc != static_cast(2+NB_PARAMS+6*_nb_thread+6*_nb_decod_bloc+10*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+19*_nb_ooo_engine+11*_nb_execute_loop+ 3*_nb_thread+_nb_front_end+_sum_inst_issue*_nb_read_bloc+_nb_load_store_unit*(_nb_read_bloc+_nb_write_bloc+_nb_thread)+_nb_functionnal_unit*(_nb_read_bloc+_nb_write_bloc)+_sum_cache_port)) usage (argc, argv); @@ -657,5 +657,5 @@ _nb_reg_free , _nb_rename_unit_bank , - _size_read_counter , +// _size_read_counter , _nb_read_bloc , Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h (revision 112) @@ -69,5 +69,5 @@ public : uint32_t * _nb_reg_free ;//[nb_rename_bloc] public : uint32_t * _nb_rename_unit_bank ;//[nb_rename_bloc] - public : uint32_t * _size_read_counter ;//[nb_rename_bloc] +//public : uint32_t * _size_read_counter ;//[nb_rename_bloc] // Read bloc @@ -250,5 +250,5 @@ public : uint32_t ** _ooo_engine_nb_reg_free ;//[nb_ooo_engine][nb_rename_unit] public : uint32_t ** _ooo_engine_nb_rename_unit_bank ;//[nb_ooo_engine][nb_rename_unit] - public : uint32_t ** _ooo_engine_size_read_counter ;//[nb_ooo_engine][nb_rename_unit] +// public : uint32_t ** _ooo_engine_size_read_counter ;//[nb_ooo_engine][nb_rename_unit] public : bool *** _ooo_engine_table_routing ;//[nb_ooo_engine][nb_rename_unit][nb_inst_issue] public : bool *** _ooo_engine_table_issue_type ;//[nb_ooo_engine][nb_inst_issue][nb_type] @@ -381,5 +381,5 @@ uint32_t * nb_reg_free ,//[nb_rename_bloc] uint32_t * nb_rename_unit_bank ,//[nb_rename_bloc] - uint32_t * size_read_counter ,//[nb_rename_bloc] +// uint32_t * size_read_counter ,//[nb_rename_bloc] // Read bloc Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp (revision 112) @@ -55,5 +55,5 @@ // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("icache_req",WEST,OUT,_("Request to instruction cache"),_param->_nb_icache_port); + ALLOC1_INTERFACE_BEGIN("icache_req",WEST,OUT,_("Request to instruction cache"),_param->_nb_icache_port); ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL); @@ -63,9 +63,11 @@ ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_address_t ,_param->_size_icache_address ); ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type ); + + ALLOC1_INTERFACE_END(_param->_nb_icache_port); } // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port); + ALLOC1_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port); ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); @@ -74,14 +76,18 @@ ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_icache_packet_id); ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error); + + ALLOC1_INTERFACE_END(_param->_nb_icache_port); } { - ALLOC2_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + ALLOC2_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); _ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_param->_size_instruction,_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + + ALLOC2_INTERFACE_END(_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); } // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("dcache_req", OUT, NORTH, _("Request to data cache"),_param->_nb_dcache_port); + ALLOC1_INTERFACE_BEGIN("dcache_req", OUT, NORTH, _("Request to data cache"),_param->_nb_dcache_port); ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,VAL); @@ -92,9 +98,11 @@ ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_dcache_data); ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type); + + ALLOC1_INTERFACE_END(_param->_nb_dcache_port); } // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("dcache_rsp", IN , NORTH, _("Respons from data cache"),_param->_nb_dcache_port); + ALLOC1_INTERFACE_BEGIN("dcache_rsp", IN , NORTH, _("Respons from data cache"),_param->_nb_dcache_port); ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,VAL); @@ -104,11 +112,15 @@ ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_dcache_data); ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t ,_param->_size_dcache_error); + + ALLOC1_INTERFACE_END(_param->_nb_dcache_port); } // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("interrupt", IN , NORTH, _("Interruption line"),_param->_nb_thread); + ALLOC1_INTERFACE_BEGIN("interrupt", IN , NORTH, _("Interruption line"),_param->_nb_thread); ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE ,"enable",Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_param->_nb_thread); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp (revision 112) @@ -59,4 +59,11 @@ // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + DELETE0(_component_glue); + DELETE0(_component_dcache_access); + DELETE0(_component_icache_access); + DELETE1(_component_execute_loop, _param->_nb_execute_loop); + DELETE1(_component_ooo_engine , _param->_nb_ooo_engine); + DELETE1(_component_front_end , _param->_nb_front_end); + delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp (revision 112) @@ -107,5 +107,5 @@ uint32_t * nb_reg_free ,//[nb_rename_bloc] uint32_t * nb_rename_unit_bank ,//[nb_rename_bloc] - uint32_t * size_read_counter ,//[nb_rename_bloc] +// uint32_t * size_read_counter ,//[nb_rename_bloc] // Read bloc @@ -262,5 +262,5 @@ _nb_reg_free = nb_reg_free ; _nb_rename_unit_bank = nb_rename_unit_bank ; - _size_read_counter = size_read_counter ; +// _size_read_counter = size_read_counter ; _nb_read_bloc = nb_read_bloc ; @@ -974,5 +974,5 @@ ALLOC2(_ooo_engine_nb_reg_free ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); ALLOC2(_ooo_engine_nb_rename_unit_bank ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); - ALLOC2(_ooo_engine_size_read_counter ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); +// ALLOC2(_ooo_engine_size_read_counter ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); for (uint32_t i=0; i<_nb_ooo_engine; ++i) @@ -997,5 +997,5 @@ _ooo_engine_nb_reg_free [i][j] = _nb_reg_free [num_rename_bloc]; _ooo_engine_nb_rename_unit_bank [i][j] = _nb_rename_unit_bank [num_rename_bloc]; - _ooo_engine_size_read_counter [i][j] = _size_read_counter [num_rename_bloc]; +// _ooo_engine_size_read_counter [i][j] = _size_read_counter [num_rename_bloc]; } } @@ -1918,5 +1918,5 @@ _ooo_engine_nb_reg_free [i], _ooo_engine_nb_rename_unit_bank [i], - _ooo_engine_size_read_counter [i], +// _ooo_engine_size_read_counter [i], _ooo_engine_nb_load_store_unit [i], _ooo_engine_size_store_queue [i], @@ -2134,4 +2134,5 @@ DELETE4(_ooo_engine_implement_group ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2],NB_GROUP); DELETE3(_ooo_engine_link_load_store_unit_with_context ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2]); + DELETE3(_ooo_engine_nb_inst_memory ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]); DELETE3(_ooo_engine_size_load_queue ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]); DELETE3(_ooo_engine_size_store_queue ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]); @@ -2142,5 +2143,5 @@ DELETE3(_ooo_engine_table_routing ,_nb_ooo_engine,_nb_rename_unit[it1],_nb_inst_issue[it1]); DELETE4(_network_table_dispatch ,_nb_ooo_engine,_nb_inst_issue[it1],_nb_execute_loop,_nb_read_unit[it3]); - DELETE2(_ooo_engine_size_read_counter ,_nb_ooo_engine,_nb_rename_unit[it1]); +// DELETE2(_ooo_engine_size_read_counter ,_nb_ooo_engine,_nb_rename_unit[it1]); DELETE2(_ooo_engine_nb_rename_unit_bank ,_nb_ooo_engine,_nb_rename_unit[it1]); DELETE2(_ooo_engine_nb_reg_free ,_nb_ooo_engine,_nb_rename_unit[it1]); @@ -2151,8 +2152,10 @@ DELETE2(_ooo_engine_rename_select_priority ,_nb_ooo_engine,_nb_rename_unit[it1]); DELETE2(_ooo_engine_nb_inst_retire ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE1(_ooo_engine_nb_inst_insert_rob ,_nb_ooo_engine); DELETE2(_ooo_engine_nb_inst_insert ,_nb_ooo_engine,_nb_rename_unit[it1]); DELETE2(_ooo_engine_link_rename_unit_with_front_end ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]); DELETE3(_ooo_engine_nb_branch_speculated ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2]); DELETE2(_ooo_engine_nb_inst_execute ,_nb_ooo_engine,_ooo_engine_nb_execute_loop[it1]); + DELETE3(_ooo_engine_translate_num_context_to_num_thread ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2]); DELETE2(_ooo_engine_nb_inst_decod ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]); DELETE2(_ooo_engine_nb_context ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp (revision 112) @@ -81,5 +81,5 @@ str+= toString(MSG_INFORMATION)+" * nb_reg_free : "+toString(_nb_reg_free [i])+"\n"; str+= toString(MSG_INFORMATION)+" * nb_rename_unit_bank : "+toString(_nb_rename_unit_bank [i])+"\n"; - str+= toString(MSG_INFORMATION)+" * size_read_counter : "+toString(_size_read_counter [i])+"\n"; +// str+= toString(MSG_INFORMATION)+" * size_read_counter : "+toString(_size_read_counter [i])+"\n"; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/Makefile (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/Makefile (revision 112) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libComparator.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/Makefile.defs (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/Makefile.defs (revision 112) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/Makefile.deps (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/Makefile.deps (revision 112) @@ -0,0 +1,38 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Comparator = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Comparator_DIR = $(DIR_MORPHEO)/Behavioural/Generic/Comparator + +#-----[ Library ]------------------------------------------ + +Comparator_LIBRARY = -lComparator \ + $(Behavioural_LIBRARY) + +Comparator_DIR_LIBRARY = -L$(Comparator_DIR)/lib \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Comparator_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) --directory=$(Comparator_DIR) --makefile=Makefile; + +Comparator_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) --directory=$(Comparator_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/Makefile (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/Makefile (revision 112) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Comparator_LIBRARY) + +DIR_LIBRARY = $(Comparator_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Comparator_library + +library_clean : Comparator_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/configuration.cfg (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/configuration.cfg (revision 112) @@ -0,0 +1,4 @@ +Comparator +32 32 *2 # size_data +0 1 +1 # is_signed +0 5 +1 # type Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/include/test.h (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/include/test.h (revision 112) @@ -0,0 +1,28 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Generic/Comparator/include/Comparator.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::generic; + +using namespace morpheo::behavioural::generic::comparator; + +void test (string name, + morpheo::behavioural::generic::comparator::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/src/main.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/src/main.cpp (revision 112) @@ -0,0 +1,81 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Comparator/SelfTest/include/test.h" +#include "Behavioural/include/Selftest.h" + +#define NB_PARAMS 3 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * size_data (uint32_t )\n")); + err (_(" * is_signed (bool )\n")); + err (_(" * type (Tcomparator_scheme_t)\n")); + + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc != static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + uint32_t _size_data; + bool _is_signed; + Tcomparator_scheme_t _type; + + SELFTEST0(_size_data,uint32_t ,argv,x); + SELFTEST0(_is_signed,bool ,argv,x); + SELFTEST0(_type ,Tcomparator_scheme_t,argv,x); + + string name = argv[x++]; + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::generic::comparator::Parameters * param = new morpheo::behavioural::generic::comparator::Parameters + ( + _size_data, + _is_signed, + _type , + true //is_toplevel + ); + + msg(_("%s"),param->print(0).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Comparator : no error"); + else + TEST_KO("Comparator : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/src/test.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/src/test.cpp (revision 112) @@ -0,0 +1,113 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Generic/Comparator/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +void test (string name, + morpheo::behavioural::generic::comparator::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + + if (setlocale (LC_ALL, "") == NULL) + msg(_("setlocale ko.\n")); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Comparator * _Comparator = new Comparator + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Comparator.\n"),name.c_str()); + + (*(_Comparator->in_CLOCK)) (*(in_CLOCK)); + (*(_Comparator->in_NRESET)) (*(in_NRESET)); + + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + } +#endif + + delete _Comparator; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/Comparator.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/Comparator.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/Comparator.tex (revision 112) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/Makefile (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/Makefile (revision 112) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/sty/header.sty (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/sty/header.sty (revision 112) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Comparator} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/01_introduction.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/01_introduction.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/02_features.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/02_features.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/03_description.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/03_description.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/04_pinout.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/04_pinout.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/05_parameters.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/05_parameters.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/06_performance.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/06_performance.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/07_details.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/07_details.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/08_history.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/08_history.tex (revision 112) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/root.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/doc/tex/root.tex (revision 112) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/include/Comparator.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/include/Comparator.h (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/include/Comparator.h (revision 112) @@ -0,0 +1,131 @@ +#ifndef morpheo_behavioural_generic_comparator_Comparator_h +#define morpheo_behavioural_generic_comparator_Comparator_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Generic/Comparator/include/Parameters.h" +#include "Behavioural/Generic/Comparator/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { + +namespace generic { +namespace comparator { + + + class Comparator +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface : "compare" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tdata_t ) * in_COMPARE_DATA_0; + public : SC_IN (Tdata_t ) * in_COMPARE_DATA_1; + public : SC_OUT(Tcontrol_t) * in_COMPARE_TEST ; + + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Comparator); +#endif + public : Comparator + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Comparator (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + public : void transition (void); +//public : void genMoore (void); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/include/Parameters.h (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/include/Parameters.h (revision 112) @@ -0,0 +1,51 @@ +#ifndef morpheo_behavioural_generic_comparator_Parameters_h +#define morpheo_behavioural_generic_comparator_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Parameters.h" +#include "Behavioural/Generic/Comparator/include/Types.h" +#include "Common/include/Debug.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : uint32_t _size_data; + public : bool _is_signed; + public : Tcomparator_scheme_t _type; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t size_data, + bool is_signed, + Tcomparator_scheme_t type , + bool is_toplevel=false); +//public : Parameters (Parameters & param) ; + public : ~Parameters (void); + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::generic::comparator::Parameters & x); + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/include/Types.h (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/include/Types.h (revision 112) @@ -0,0 +1,80 @@ +#ifndef morpheo_behavioural_generic_comparator_Types_h +#define morpheo_behavioural_generic_comparator_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + +typedef enum + { + COMPARATOR_EQUAL , + COMPARATOR_NOT_EQUAL , + COMPARATOR_GREATER , + COMPARATOR_GREATER_OR_EQUAL, + COMPARATOR_LESS , + COMPARATOR_LESS_OR_EQUAL + } Tcomparator_scheme_t; + + typedef Tgeneral_data_t Tdata_t; + +}; // end namespace comparator +}; // end namespace generic +}; // end namespace behavioural + + template<> inline std::string toString(const morpheo::behavioural::generic::comparator::Tcomparator_scheme_t& x) + { + switch (x) + { + case morpheo::behavioural::generic::comparator::COMPARATOR_EQUAL : return "equal" ; break; + case morpheo::behavioural::generic::comparator::COMPARATOR_NOT_EQUAL : return "not_equal" ; break; + case morpheo::behavioural::generic::comparator::COMPARATOR_GREATER : return "greater" ; break; + case morpheo::behavioural::generic::comparator::COMPARATOR_GREATER_OR_EQUAL : return "greater_or_equal"; break; + case morpheo::behavioural::generic::comparator::COMPARATOR_LESS : return "less" ; break; + case morpheo::behavioural::generic::comparator::COMPARATOR_LESS_OR_EQUAL : return "less_or_equal" ; break; + default : return ""; break; + } + }; + + template<> inline morpheo::behavioural::generic::comparator::Tcomparator_scheme_t fromString(const std::string& x) + { + if ((x.compare(toString(static_cast(morpheo::behavioural::generic::comparator::COMPARATOR_EQUAL))) == 0) or + (x.compare("equal") == 0)) + return morpheo::behavioural::generic::comparator::COMPARATOR_EQUAL; + + if ((x.compare(toString(static_cast(morpheo::behavioural::generic::comparator::COMPARATOR_NOT_EQUAL))) == 0) or + (x.compare("not_equal") == 0)) + return morpheo::behavioural::generic::comparator::COMPARATOR_NOT_EQUAL; + + if ((x.compare(toString(static_cast(morpheo::behavioural::generic::comparator::COMPARATOR_GREATER))) == 0) or + (x.compare("greater") == 0)) + return morpheo::behavioural::generic::comparator::COMPARATOR_GREATER; + + if ((x.compare(toString(static_cast(morpheo::behavioural::generic::comparator::COMPARATOR_GREATER_OR_EQUAL))) == 0) or + (x.compare("greater_or_equal") == 0)) + return morpheo::behavioural::generic::comparator::COMPARATOR_GREATER_OR_EQUAL; + + if ((x.compare(toString(static_cast(morpheo::behavioural::generic::comparator::COMPARATOR_LESS))) == 0) or + (x.compare("less") == 0)) + return morpheo::behavioural::generic::comparator::COMPARATOR_LESS; + + if ((x.compare(toString(static_cast(morpheo::behavioural::generic::comparator::COMPARATOR_LESS_OR_EQUAL))) == 0) or + (x.compare("less_or_equal") == 0)) + return morpheo::behavioural::generic::comparator::COMPARATOR_LESS_OR_EQUAL; + + throw (ErrorMorpheo (" : Unknow string : \""+x+"\"")); + }; + + +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator.cpp (revision 112) @@ -0,0 +1,117 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Comparator/include/Comparator.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + +#undef FUNCTION +#define FUNCTION "Comparator::Comparator" + Comparator::Comparator + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::generic::comparator::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Comparator,FUNCTION); + + usage_environment(_usage); + + log_printf(INFO,Comparator,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Comparator,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Comparator,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,Comparator,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +// log_printf(INFO,Comparator,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + +// SC_METHOD (genMoore); +// dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // need internal register + +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information +// # endif + +#endif + } + log_end(Comparator,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Comparator::~Comparator" + Comparator::~Comparator (void) + { + log_begin(Comparator,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Comparator,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(Comparator,FUNCTION); + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_allocation.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_allocation.cpp (revision 112) @@ -0,0 +1,69 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Comparator/include/Comparator.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + + +#undef FUNCTION +#define FUNCTION "Comparator::allocation" + void Comparator::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Comparator,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Comparator" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Comparator,FUNCTION); + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_deallocation.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_deallocation.cpp (revision 112) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Comparator/include/Comparator.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + +#undef FUNCTION +#define FUNCTION "Comparator::deallocation" + void Comparator::deallocation (void) + { + log_begin(Comparator,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete _component; + + log_end(Comparator,FUNCTION); + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_end_cycle.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_end_cycle.cpp (revision 112) @@ -0,0 +1,43 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Comparator/include/Comparator.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + +#undef FUNCTION +#define FUNCTION "Comparator::end_cycle" +void Comparator::end_cycle () + { + log_begin(Comparator,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Comparator,FUNCTION); + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_statistics_allocation.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_statistics_allocation.cpp (revision 112) @@ -0,0 +1,35 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Comparator/include/Comparator.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + +#undef FUNCTION +#define FUNCTION "Comparator::statistics_allocation" + void Comparator::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Comparator,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Comparator", + param_statistics); + + log_end(Comparator,FUNCTION); + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_statistics_deallocation.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_statistics_deallocation.cpp (revision 112) @@ -0,0 +1,35 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Comparator/include/Comparator.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + +#undef FUNCTION +#define FUNCTION "Comparator::statistics_deallocation" + void Comparator::statistics_deallocation (void) + { + log_begin(Comparator,FUNCTION); + + log_printf(INFO,Comparator,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(Comparator,FUNCTION); + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_transition.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_transition.cpp (revision 112) @@ -0,0 +1,35 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Comparator/include/Comparator.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + +#undef FUNCTION +#define FUNCTION "Comparator::transition" + void Comparator::transition (void) + { + log_begin(Comparator,FUNCTION); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Comparator,FUNCTION); + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_vhdl.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_vhdl.cpp (revision 112) @@ -0,0 +1,44 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Comparator/include/Comparator.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + +#undef FUNCTION +#define FUNCTION "Comparator::vhdl" + void Comparator::vhdl (void) + { + log_begin(Comparator,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Comparator,FUNCTION); + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_vhdl_body.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_vhdl_body.cpp (revision 112) @@ -0,0 +1,31 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Comparator/include/Comparator.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + +#undef FUNCTION +#define FUNCTION "Comparator::vhdl_body" + void Comparator::vhdl_body (Vhdl * & vhdl) + { + log_begin(Comparator,FUNCTION); + vhdl->set_body (""); + log_end(Comparator,FUNCTION); + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_vhdl_declaration.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_vhdl_declaration.cpp (revision 112) @@ -0,0 +1,30 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Comparator/include/Comparator.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + +#undef FUNCTION +#define FUNCTION "Comparator::vhdl_declaration" + void Comparator::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(Comparator,FUNCTION); + log_end(Comparator,FUNCTION); + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Parameters.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Parameters.cpp (revision 112) @@ -0,0 +1,68 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Comparator/include/Parameters.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + +#undef FUNCTION +#define FUNCTION "Comparator::Parameters" + Parameters::Parameters (uint32_t size_data, + bool is_signed, + Tcomparator_scheme_t type , + bool is_toplevel) + { + log_begin(Comparator,FUNCTION); + + _size_data = size_data; + _is_signed = is_signed; + _type = type ; + + test(); + + if (is_toplevel) + { + copy(); + } + + log_end(Comparator,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Comparator::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Comparator,FUNCTION); +// test(); +// log_end(Comparator,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Comparator::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Comparator,FUNCTION); + log_end(Comparator,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Comparator::copy" + void Parameters::copy (void) + { + log_begin(Comparator,FUNCTION); + log_end(Comparator,FUNCTION); + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Parameters_msg_error.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Parameters_msg_error.cpp (revision 112) @@ -0,0 +1,35 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Generic/Comparator/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + +#undef FUNCTION +#define FUNCTION "Comparator::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Comparator,FUNCTION); + + Parameters_test test ("Comparator"); + + log_end(Comparator,FUNCTION); + + return test; + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Parameters_print.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Parameters_print.cpp (revision 112) @@ -0,0 +1,52 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Comparator/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace comparator { + + +#undef FUNCTION +#define FUNCTION "Comparator::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Comparator,FUNCTION); + + XML xml ("comparator"); + + xml.balise_open("comparator"); +// xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end(); + xml.balise_close(); + + log_end(Comparator,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "Comparator::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::generic::comparator::Parameters & x) + { + log_begin(Comparator,FUNCTION); + + output_stream << x.print(0); + + log_end(Comparator,FUNCTION); + + return output_stream; + }; + +}; // end namespace comparator +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/include/test.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/include/test.h (revision 112) @@ -14,4 +14,5 @@ #include +#include "Common/include/Time.h" #include "Behavioural/Generic/Counter/include/Counter.h" Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/test.cpp (revision 112) @@ -80,4 +80,6 @@ } + Time * _time = new Time(); + /******************************************************** * Simulation - Begin @@ -147,4 +149,6 @@ ********************************************************/ + delete _time; + cout << "<" << name << "> ............ Stop Simulation" << endl; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_allocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/Counter/include/Counter.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -34,5 +35,5 @@ , IN , SOUTH - , "Generalist interface" + , _("Generalist interface") #endif ); @@ -43,25 +44,14 @@ // ~~~~~[ Interface : "counter" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - { - in_COUNTER_DATA = new SC_IN (Tdata_t) * [_param._nb_port]; - in_COUNTER_ADDSUB= new SC_IN (Tcontrol_t) * [_param._nb_port]; - out_COUNTER_DATA = new SC_OUT(Tdata_t) * [_param._nb_port]; - - for (uint32_t i=0; i<_param._nb_port; i++) - { - Interface_fifo * interface = _interfaces->set_interface("counter_"+toString(i) -#ifdef POSITION - , IN - , SOUTH - , "Counter interface" -#endif - ); + { + ALLOC1_INTERFACE_BEGIN("counter", IN, SOUTH, _("Counter interface"), _param._nb_port); - in_COUNTER_DATA [i] = interface->set_signal_in ("data" , _param._size_data); - in_COUNTER_ADDSUB [i] = interface->set_signal_in ("addsub", 1 ); - out_COUNTER_DATA [i] = interface->set_signal_out ("data" , _param._size_data); - } - } + ALLOC1_SIGNAL_IN ( in_COUNTER_DATA ,"data" ,Tdata_t ,_param._size_data); + ALLOC1_SIGNAL_IN ( in_COUNTER_ADDSUB,"addsub",Tcontrol_t,1 ); + ALLOC1_SIGNAL_OUT(out_COUNTER_DATA ,"data" ,Tdata_t ,_param._size_data); + ALLOC1_INTERFACE_END(_param._nb_port); + } + #ifdef POSITION if (usage_is_set(_usage,USE_POSITION)) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/Counter/include/Counter.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -23,7 +24,7 @@ delete in_NRESET; - delete [] in_COUNTER_DATA ; - delete [] in_COUNTER_ADDSUB; - delete [] out_COUNTER_DATA ; + DELETE1_SIGNAL( in_COUNTER_DATA , _param._nb_port,_param._size_data); + DELETE1_SIGNAL( in_COUNTER_ADDSUB, _param._nb_port,1 ); + DELETE1_SIGNAL(out_COUNTER_DATA , _param._nb_port,_param._size_data); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/Makefile (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/Makefile (revision 112) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libDivider.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/Makefile.defs (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/Makefile.defs (revision 112) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/Makefile.deps (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/Makefile.deps (revision 112) @@ -0,0 +1,38 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Divider = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Divider_DIR = $(DIR_MORPHEO)/Behavioural/Generic/Divider + +#-----[ Library ]------------------------------------------ + +Divider_LIBRARY = -lDivider \ + $(Behavioural_LIBRARY) + +Divider_DIR_LIBRARY = -L$(Divider_DIR)/lib \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Divider_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) --directory=$(Divider_DIR) --makefile=Makefile; + +Divider_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) --directory=$(Divider_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/Makefile (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/Makefile (revision 112) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Divider_LIBRARY) + +DIR_LIBRARY = $(Divider_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Divider_library + +library_clean : Divider_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/configuration.cfg (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/configuration.cfg (revision 112) @@ -0,0 +1,1 @@ +Divider Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/include/test.h (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/include/test.h (revision 112) @@ -0,0 +1,28 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Generic/Divider/include/Divider.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::generic; + +using namespace morpheo::behavioural::generic::divider; + +void test (string name, + morpheo::behavioural::generic::divider::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/src/main.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/src/main.cpp (revision 112) @@ -0,0 +1,66 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Divider/SelfTest/include/test.h" + +#define NB_PARAMS 0 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * ()\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc != static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::generic::divider::Parameters * param = new morpheo::behavioural::generic::divider::Parameters + ( + true //is_toplevel + ); + + msg(_("%s"),param->print(0).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Divider : no error"); + else + TEST_KO("Divider : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/src/test.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/src/test.cpp (revision 112) @@ -0,0 +1,113 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Generic/Divider/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +void test (string name, + morpheo::behavioural::generic::divider::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + + if (setlocale (LC_ALL, "") == NULL) + msg(_("setlocale ko.\n")); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Divider * _Divider = new Divider + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Divider.\n"),name.c_str()); + + (*(_Divider->in_CLOCK)) (*(in_CLOCK)); + (*(_Divider->in_NRESET)) (*(in_NRESET)); + + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + } +#endif + + delete _Divider; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/Divider.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/Divider.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/Divider.tex (revision 112) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/Makefile (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/Makefile (revision 112) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/sty/header.sty (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/sty/header.sty (revision 112) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Divider} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/01_introduction.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/01_introduction.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/02_features.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/02_features.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/03_description.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/03_description.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/04_pinout.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/04_pinout.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/05_parameters.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/05_parameters.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/06_performance.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/06_performance.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/07_details.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/07_details.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/08_history.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/08_history.tex (revision 112) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/root.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/doc/tex/root.tex (revision 112) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/include/Divider.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/include/Divider.h (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/include/Divider.h (revision 112) @@ -0,0 +1,125 @@ +#ifndef morpheo_behavioural_generic_divider_Divider_h +#define morpheo_behavioural_generic_divider_Divider_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Generic/Divider/include/Parameters.h" +#include "Behavioural/Generic/Divider/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { + +namespace generic { +namespace divider { + + + class Divider +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Divider); +#endif + public : Divider + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Divider (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + public : void transition (void); +//public : void genMoore (void); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/include/Parameters.h (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/include/Parameters.h (revision 112) @@ -0,0 +1,44 @@ +#ifndef morpheo_behavioural_generic_divider_Parameters_h +#define morpheo_behavioural_generic_divider_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (bool is_toplevel=false); +//public : Parameters (Parameters & param) ; + public : ~Parameters (void); + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::generic::divider::Parameters & x); + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/include/Types.h (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/include/Types.h (revision 112) @@ -0,0 +1,25 @@ +#ifndef morpheo_behavioural_generic_divider_Types_h +#define morpheo_behavioural_generic_divider_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider.cpp (revision 112) @@ -0,0 +1,117 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Divider/include/Divider.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + +#undef FUNCTION +#define FUNCTION "Divider::Divider" + Divider::Divider + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::generic::divider::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Divider,FUNCTION); + + usage_environment(_usage); + + log_printf(INFO,Divider,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Divider,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Divider,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,Divider,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +// log_printf(INFO,Divider,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + +// SC_METHOD (genMoore); +// dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // need internal register + +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information +// # endif + +#endif + } + log_end(Divider,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Divider::~Divider" + Divider::~Divider (void) + { + log_begin(Divider,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Divider,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(Divider,FUNCTION); + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_allocation.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_allocation.cpp (revision 112) @@ -0,0 +1,69 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Divider/include/Divider.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + + +#undef FUNCTION +#define FUNCTION "Divider::allocation" + void Divider::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Divider,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Divider" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Divider,FUNCTION); + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_deallocation.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_deallocation.cpp (revision 112) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Divider/include/Divider.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + +#undef FUNCTION +#define FUNCTION "Divider::deallocation" + void Divider::deallocation (void) + { + log_begin(Divider,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete _component; + + log_end(Divider,FUNCTION); + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_end_cycle.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_end_cycle.cpp (revision 112) @@ -0,0 +1,43 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Divider/include/Divider.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + +#undef FUNCTION +#define FUNCTION "Divider::end_cycle" +void Divider::end_cycle () + { + log_begin(Divider,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Divider,FUNCTION); + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_statistics_allocation.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_statistics_allocation.cpp (revision 112) @@ -0,0 +1,35 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Divider/include/Divider.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + +#undef FUNCTION +#define FUNCTION "Divider::statistics_allocation" + void Divider::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Divider,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Divider", + param_statistics); + + log_end(Divider,FUNCTION); + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_statistics_deallocation.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_statistics_deallocation.cpp (revision 112) @@ -0,0 +1,35 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Divider/include/Divider.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + +#undef FUNCTION +#define FUNCTION "Divider::statistics_deallocation" + void Divider::statistics_deallocation (void) + { + log_begin(Divider,FUNCTION); + + log_printf(INFO,Divider,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(Divider,FUNCTION); + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_transition.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_transition.cpp (revision 112) @@ -0,0 +1,35 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Divider/include/Divider.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + +#undef FUNCTION +#define FUNCTION "Divider::transition" + void Divider::transition (void) + { + log_begin(Divider,FUNCTION); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Divider,FUNCTION); + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_vhdl.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_vhdl.cpp (revision 112) @@ -0,0 +1,44 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Divider/include/Divider.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + +#undef FUNCTION +#define FUNCTION "Divider::vhdl" + void Divider::vhdl (void) + { + log_begin(Divider,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Divider,FUNCTION); + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_vhdl_body.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_vhdl_body.cpp (revision 112) @@ -0,0 +1,31 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Divider/include/Divider.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + +#undef FUNCTION +#define FUNCTION "Divider::vhdl_body" + void Divider::vhdl_body (Vhdl * & vhdl) + { + log_begin(Divider,FUNCTION); + vhdl->set_body (""); + log_end(Divider,FUNCTION); + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_vhdl_declaration.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Divider_vhdl_declaration.cpp (revision 112) @@ -0,0 +1,30 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Divider/include/Divider.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + +#undef FUNCTION +#define FUNCTION "Divider::vhdl_declaration" + void Divider::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(Divider,FUNCTION); + log_end(Divider,FUNCTION); + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Parameters.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Parameters.cpp (revision 112) @@ -0,0 +1,61 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Divider/include/Parameters.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + +#undef FUNCTION +#define FUNCTION "Divider::Parameters" + Parameters::Parameters (bool is_toplevel) + { + log_begin(Divider,FUNCTION); + + test(); + + if (is_toplevel) + { + copy(); + } + + log_end(Divider,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Divider::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Divider,FUNCTION); +// test(); +// log_end(Divider,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Divider::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Divider,FUNCTION); + log_end(Divider,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Divider::copy" + void Parameters::copy (void) + { + log_begin(Divider,FUNCTION); + log_end(Divider,FUNCTION); + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Parameters_msg_error.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Parameters_msg_error.cpp (revision 112) @@ -0,0 +1,35 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Generic/Divider/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + +#undef FUNCTION +#define FUNCTION "Divider::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Divider,FUNCTION); + + Parameters_test test ("Divider"); + + log_end(Divider,FUNCTION); + + return test; + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Parameters_print.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/src/Parameters_print.cpp (revision 112) @@ -0,0 +1,52 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Divider/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace divider { + + +#undef FUNCTION +#define FUNCTION "Divider::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Divider,FUNCTION); + + XML xml ("divider"); + + xml.balise_open("divider"); +// xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end(); + xml.balise_close(); + + log_end(Divider,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "Divider::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::generic::divider::Parameters & x) + { + log_begin(Divider,FUNCTION); + + output_stream << x.print(0); + + log_end(Divider,FUNCTION); + + return output_stream; + }; + +}; // end namespace divider +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/Makefile (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/Makefile (revision 112) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libMultiplier.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/Makefile.defs (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/Makefile.defs (revision 112) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/Makefile.deps (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/Makefile.deps (revision 112) @@ -0,0 +1,38 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Multiplier = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Multiplier_DIR = $(DIR_MORPHEO)/Behavioural/Generic/Multiplier + +#-----[ Library ]------------------------------------------ + +Multiplier_LIBRARY = -lMultiplier \ + $(Behavioural_LIBRARY) + +Multiplier_DIR_LIBRARY = -L$(Multiplier_DIR)/lib \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Multiplier_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) --directory=$(Multiplier_DIR) --makefile=Makefile; + +Multiplier_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) --directory=$(Multiplier_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/Makefile (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/Makefile (revision 112) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Multiplier_LIBRARY) + +DIR_LIBRARY = $(Multiplier_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Multiplier_library + +library_clean : Multiplier_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/configuration.cfg (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/configuration.cfg (revision 112) @@ -0,0 +1,1 @@ +Multiplier Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/include/test.h (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/include/test.h (revision 112) @@ -0,0 +1,28 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::generic; + +using namespace morpheo::behavioural::generic::multiplier; + +void test (string name, + morpheo::behavioural::generic::multiplier::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/src/main.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/src/main.cpp (revision 112) @@ -0,0 +1,66 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/SelfTest/include/test.h" + +#define NB_PARAMS 0 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * ()\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc != static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::generic::multiplier::Parameters * param = new morpheo::behavioural::generic::multiplier::Parameters + ( + true //is_toplevel + ); + + msg(_("%s"),param->print(0).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Multiplier : no error"); + else + TEST_KO("Multiplier : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/src/test.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/src/test.cpp (revision 112) @@ -0,0 +1,113 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Generic/Multiplier/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +void test (string name, + morpheo::behavioural::generic::multiplier::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + + if (setlocale (LC_ALL, "") == NULL) + msg(_("setlocale ko.\n")); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Multiplier * _Multiplier = new Multiplier + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Multiplier.\n"),name.c_str()); + + (*(_Multiplier->in_CLOCK)) (*(in_CLOCK)); + (*(_Multiplier->in_NRESET)) (*(in_NRESET)); + + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + } +#endif + + delete _Multiplier; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/Makefile (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/Makefile (revision 112) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/Multiplier.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/Multiplier.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/Multiplier.tex (revision 112) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/sty/header.sty (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/sty/header.sty (revision 112) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Multiplier} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/01_introduction.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/01_introduction.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/02_features.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/02_features.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/03_description.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/03_description.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/04_pinout.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/04_pinout.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/05_parameters.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/05_parameters.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/06_performance.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/06_performance.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/07_details.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/07_details.tex (revision 112) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/08_history.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/08_history.tex (revision 112) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/root.tex (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/doc/tex/root.tex (revision 112) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Multiplier.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Multiplier.h (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Multiplier.h (revision 112) @@ -0,0 +1,125 @@ +#ifndef morpheo_behavioural_generic_multiplier_Multiplier_h +#define morpheo_behavioural_generic_multiplier_Multiplier_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Generic/Multiplier/include/Parameters.h" +#include "Behavioural/Generic/Multiplier/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { + +namespace generic { +namespace multiplier { + + + class Multiplier +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Multiplier); +#endif + public : Multiplier + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Multiplier (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + public : void transition (void); +//public : void genMoore (void); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Parameters.h (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Parameters.h (revision 112) @@ -0,0 +1,44 @@ +#ifndef morpheo_behavioural_generic_multiplier_Parameters_h +#define morpheo_behavioural_generic_multiplier_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (bool is_toplevel=false); +//public : Parameters (Parameters & param) ; + public : ~Parameters (void); + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::generic::multiplier::Parameters & x); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Types.h (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Types.h (revision 112) @@ -0,0 +1,25 @@ +#ifndef morpheo_behavioural_generic_multiplier_Types_h +#define morpheo_behavioural_generic_multiplier_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier.cpp (revision 112) @@ -0,0 +1,117 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +#undef FUNCTION +#define FUNCTION "Multiplier::Multiplier" + Multiplier::Multiplier + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::generic::multiplier::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Multiplier,FUNCTION); + + usage_environment(_usage); + + log_printf(INFO,Multiplier,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Multiplier,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Multiplier,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,Multiplier,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +// log_printf(INFO,Multiplier,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + +// SC_METHOD (genMoore); +// dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // need internal register + +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information +// # endif + +#endif + } + log_end(Multiplier,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Multiplier::~Multiplier" + Multiplier::~Multiplier (void) + { + log_begin(Multiplier,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Multiplier,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_allocation.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_allocation.cpp (revision 112) @@ -0,0 +1,69 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + + +#undef FUNCTION +#define FUNCTION "Multiplier::allocation" + void Multiplier::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Multiplier,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Multiplier" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_deallocation.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_deallocation.cpp (revision 112) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +#undef FUNCTION +#define FUNCTION "Multiplier::deallocation" + void Multiplier::deallocation (void) + { + log_begin(Multiplier,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete _component; + + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_end_cycle.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_end_cycle.cpp (revision 112) @@ -0,0 +1,43 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +#undef FUNCTION +#define FUNCTION "Multiplier::end_cycle" +void Multiplier::end_cycle () + { + log_begin(Multiplier,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_statistics_allocation.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_statistics_allocation.cpp (revision 112) @@ -0,0 +1,35 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +#undef FUNCTION +#define FUNCTION "Multiplier::statistics_allocation" + void Multiplier::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Multiplier,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Multiplier", + param_statistics); + + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_statistics_deallocation.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_statistics_deallocation.cpp (revision 112) @@ -0,0 +1,35 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +#undef FUNCTION +#define FUNCTION "Multiplier::statistics_deallocation" + void Multiplier::statistics_deallocation (void) + { + log_begin(Multiplier,FUNCTION); + + log_printf(INFO,Multiplier,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_transition.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_transition.cpp (revision 112) @@ -0,0 +1,35 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +#undef FUNCTION +#define FUNCTION "Multiplier::transition" + void Multiplier::transition (void) + { + log_begin(Multiplier,FUNCTION); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl.cpp (revision 112) @@ -0,0 +1,44 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +#undef FUNCTION +#define FUNCTION "Multiplier::vhdl" + void Multiplier::vhdl (void) + { + log_begin(Multiplier,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl_body.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl_body.cpp (revision 112) @@ -0,0 +1,31 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +#undef FUNCTION +#define FUNCTION "Multiplier::vhdl_body" + void Multiplier::vhdl_body (Vhdl * & vhdl) + { + log_begin(Multiplier,FUNCTION); + vhdl->set_body (""); + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl_declaration.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl_declaration.cpp (revision 112) @@ -0,0 +1,30 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +#undef FUNCTION +#define FUNCTION "Multiplier::vhdl_declaration" + void Multiplier::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(Multiplier,FUNCTION); + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters.cpp (revision 112) @@ -0,0 +1,61 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Parameters.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +#undef FUNCTION +#define FUNCTION "Multiplier::Parameters" + Parameters::Parameters (bool is_toplevel) + { + log_begin(Multiplier,FUNCTION); + + test(); + + if (is_toplevel) + { + copy(); + } + + log_end(Multiplier,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Multiplier::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Multiplier,FUNCTION); +// test(); +// log_end(Multiplier,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Multiplier::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Multiplier,FUNCTION); + log_end(Multiplier,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Multiplier::copy" + void Parameters::copy (void) + { + log_begin(Multiplier,FUNCTION); + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters_msg_error.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters_msg_error.cpp (revision 112) @@ -0,0 +1,35 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Generic/Multiplier/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +#undef FUNCTION +#define FUNCTION "Multiplier::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Multiplier,FUNCTION); + + Parameters_test test ("Multiplier"); + + log_end(Multiplier,FUNCTION); + + return test; + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters_print.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters_print.cpp (revision 112) @@ -0,0 +1,52 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +#undef FUNCTION +#define FUNCTION "Multiplier::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Multiplier,FUNCTION); + + XML xml ("multiplier"); + + xml.balise_open("multiplier"); +// xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end(); + xml.balise_close(); + + log_end(Multiplier,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "Multiplier::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::generic::multiplier::Parameters & x) + { + log_begin(Multiplier,FUNCTION); + + output_stream << x.print(0); + + log_end(Multiplier,FUNCTION); + + return output_stream; + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp (revision 112) @@ -49,26 +49,32 @@ // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC0_INTERFACE("insert", IN, WEST, _("Interface of data write.")); + ALLOC0_INTERFACE_BEGIN("insert", IN, WEST, _("Interface of data write.")); ALLOC0_VALACK_IN ( in_INSERT_VAL ,VAL); ALLOC0_VALACK_OUT(out_INSERT_ACK ,ACK); ALLOC0_SIGNAL_IN ( in_INSERT_DATA ,"data",Tdata_t,_param->_size_data); + + ALLOC0_INTERFACE_END(); } // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC0_INTERFACE("retire", OUT, EAST, _("Interface of data read.")); + ALLOC0_INTERFACE_BEGIN("retire", OUT, EAST, _("Interface of data read.")); ALLOC0_VALACK_OUT(out_RETIRE_VAL ,VAL); ALLOC0_VALACK_IN ( in_RETIRE_ACK ,ACK); ALLOC0_SIGNAL_OUT(out_RETIRE_DATA ,"data",Tdata_t,_param->_size_data); + + ALLOC0_INTERFACE_END(); } // ~~~~~[ Interface "slot" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("slot", OUT, NORTH, _("Internal slot."),_param->_nb_port_slot); + ALLOC1_INTERFACE_BEGIN("slot", OUT, NORTH, _("Internal slot."),_param->_nb_port_slot); ALLOC1_VALACK_OUT(out_SLOT_VAL ,VAL); ALLOC1_SIGNAL_OUT(out_SLOT_DATA ,"data",Tdata_t,_param->_size_data); + + ALLOC1_INTERFACE_END(_param->_nb_port_slot); } @@ -76,5 +82,5 @@ if (_param->_have_port_ptr) { - ALLOC0_INTERFACE("ptr", OUT, SOUTH, _("Internal pointer.")); + ALLOC0_INTERFACE_BEGIN("ptr", OUT, SOUTH, _("Internal pointer.")); if (_param->_have_port_ptr_write) @@ -82,4 +88,6 @@ if (_param->_have_port_ptr_read ) ALLOC0_SIGNAL_OUT(out_PTR_READ ,"read" ,Tptr_t,_param->_size_ptr); + + ALLOC0_INTERFACE_END(); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -33,5 +34,5 @@ , IN ,SOUTH - , "Generalist interface" + ,_("Generalist interface") #endif ); @@ -40,86 +41,45 @@ in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); } + // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("read",IN,WEST,_("Interface Read"),_param->_nb_port_read); - in_READ_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read]; - out_READ_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read]; - if (_param->_have_port_address) - in_READ_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read]; - out_READ_DATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read]; + ALLOC1_VALACK_IN ( in_READ_VAL ,VAL); + ALLOC1_VALACK_OUT(out_READ_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_READ_ADDRESS,"address",Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_OUT(out_READ_DATA ,"data" ,Tdata_t ,_param->_size_word); - for (uint32_t i=0; i<_param->_nb_port_read; i++) - { - Interface_fifo * interface = _interfaces->set_interface("read_"+toString(i) -#ifdef POSITION - , IN - ,WEST - , "Interface Read" -#endif - ); - - in_READ_VAL [i] = interface->set_signal_valack_in ("val" , VAL); - out_READ_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); - if (_param->_have_port_address) - in_READ_ADDRESS [i] = interface->set_signal_in ("address", _param->_size_address); - out_READ_DATA [i] = interface->set_signal_out ("data" , _param->_size_word); - } + ALLOC1_INTERFACE_END(_param->_nb_port_read); + } // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("write",IN,EAST,_("Interface Write"),_param->_nb_port_write); - in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_write]; - out_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_write]; - if (_param->_have_port_address) - in_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_write]; - in_WRITE_DATA = new SC_IN (Tdata_t ) * [_param->_nb_port_write]; - - for (uint32_t i=0; i<_param->_nb_port_write; i++) - { - Interface_fifo * interface = _interfaces->set_interface("write_"+toString(i) -#ifdef POSITION - , IN - ,EAST - , "Interface Write" -#endif - ); + ALLOC1_VALACK_IN ( in_WRITE_VAL ,VAL); + ALLOC1_VALACK_OUT(out_WRITE_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_WRITE_ADDRESS,"address",Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_WRITE_DATA ,"data" ,Tdata_t ,_param->_size_word); - in_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); - out_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); - if (_param->_have_port_address) - in_WRITE_ADDRESS [i] = interface->set_signal_in ("address", _param->_size_address); - in_WRITE_DATA [i] = interface->set_signal_in ("data" , _param->_size_word); - } + ALLOC1_INTERFACE_END(_param->_nb_port_write); + } // ~~~~~[ Interface : "read_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("read_write",IN,WEST,_("Interface Read_Write"),_param->_nb_port_read_write); - in_READ_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read_write]; - out_READ_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read_write]; - in_READ_WRITE_RW = new SC_IN (Tcontrol_t) * [_param->_nb_port_read_write]; - if (_param->_have_port_address) - in_READ_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read_write]; - in_READ_WRITE_WDATA = new SC_IN (Tdata_t ) * [_param->_nb_port_read_write]; - out_READ_WRITE_RDATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read_write]; + ALLOC1_VALACK_IN ( in_READ_WRITE_VAL ,VAL); + ALLOC1_VALACK_OUT(out_READ_WRITE_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_READ_WRITE_RW ,"rw" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_READ_WRITE_ADDRESS,"address",Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_READ_WRITE_WDATA ,"wdata" ,Tdata_t ,_param->_size_word); + ALLOC1_SIGNAL_OUT(out_READ_WRITE_RDATA ,"rdata" ,Tdata_t ,_param->_size_word); - for (uint32_t i=0; i<_param->_nb_port_read_write; i++) - { - Interface_fifo * interface = _interfaces->set_interface("read_write_"+toString(i) -#ifdef POSITION - , IN - ,WEST - , "Interface Read_Write" -#endif - ); + ALLOC1_INTERFACE_END(_param->_nb_port_read_write); + } - in_READ_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); - out_READ_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); - in_READ_WRITE_RW [i] = interface->set_signal_valack_in ("rw" , VAL); - if (_param->_have_port_address) - in_READ_WRITE_ADDRESS [i] = interface->set_signal_in ("address", _param->_size_address); - in_READ_WRITE_WDATA [i] = interface->set_signal_in ("wdata" , _param->_size_word); - out_READ_WRITE_RDATA [i] = interface->set_signal_out ("rdata" , _param->_size_word); - } - - // ----- Register if (usage_is_set(_usage,USE_SYSTEMC)) - reg_DATA = new Tdata_t [_param->_nb_word]; + ALLOC1(reg_DATA,Tdata_t,_param->_nb_word); #ifdef POSITION Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp (revision 112) @@ -2,9 +2,10 @@ * $Id$ * - * [ Description ] + * [ Description ] * */ #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -22,29 +23,23 @@ delete in_CLOCK; delete in_NRESET; - // ----- Interface Read - delete [] in_READ_VAL ; - delete [] out_READ_ACK ; - if (_param->_have_port_address) - delete [] in_READ_ADDRESS; - delete [] out_READ_DATA ; - - // ----- Interface Write - delete [] in_WRITE_VAL ; - delete [] out_WRITE_ACK ; - if (_param->_have_port_address) - delete [] in_WRITE_ADDRESS; - delete [] in_WRITE_DATA ; - - // ----- Interface Read_Write - delete [] in_READ_WRITE_VAL ; - delete [] out_READ_WRITE_ACK ; - delete [] in_READ_WRITE_RW ; - if (_param->_have_port_address) - delete [] in_READ_WRITE_ADDRESS; - delete [] in_READ_WRITE_WDATA ; - delete [] out_READ_WRITE_RDATA ; - - // ----- Register - delete [] reg_DATA; + + DELETE1_SIGNAL( in_READ_VAL ,_param->_nb_port_read,1); + DELETE1_SIGNAL(out_READ_ACK ,_param->_nb_port_read,1); + DELETE1_SIGNAL( in_READ_ADDRESS ,_param->_nb_port_read,_param->_size_address); + DELETE1_SIGNAL(out_READ_DATA ,_param->_nb_port_read,_param->_size_word); + + DELETE1_SIGNAL( in_WRITE_VAL ,_param->_nb_port_write,1); + DELETE1_SIGNAL(out_WRITE_ACK ,_param->_nb_port_write,1); + DELETE1_SIGNAL( in_WRITE_ADDRESS,_param->_nb_port_write,_param->_size_address); + DELETE1_SIGNAL( in_WRITE_DATA ,_param->_nb_port_write,_param->_size_word); + + DELETE1_SIGNAL( in_READ_WRITE_VAL ,_param->_nb_port_read_write,1); + DELETE1_SIGNAL(out_READ_WRITE_ACK ,_param->_nb_port_read_write,1); + DELETE1_SIGNAL( in_READ_WRITE_RW ,_param->_nb_port_read_write,1); + DELETE1_SIGNAL( in_READ_WRITE_ADDRESS,_param->_nb_port_read_write,_param->_size_address); + DELETE1_SIGNAL( in_READ_WRITE_WDATA ,_param->_nb_port_read_write,_param->_size_word); + DELETE1_SIGNAL(out_READ_WRITE_RDATA ,_param->_nb_port_read_write,_param->_size_word); + + DELETE1(reg_DATA,_param->_nb_word); } }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -36,5 +37,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -43,78 +44,45 @@ in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); - // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("read",IN,WEST,_("Interface Read"),_param->_nb_port_read); - in_READ_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read]; - out_READ_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read]; - if (_param->_have_port_address == true) - in_READ_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read]; - out_READ_DATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read]; + ALLOC1_VALACK_IN ( in_READ_VAL ,VAL); + ALLOC1_VALACK_OUT(out_READ_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_READ_ADDRESS,"address",Taddress_t, _param->_size_address); + ALLOC1_SIGNAL_OUT(out_READ_DATA ,"data" ,Tdata_t , _param->_size_word); - for (uint32_t i=0; i<_param->_nb_port_read; i++) - { - Interface_fifo * interface = _interfaces->set_interface("read_"+toString(i) -#ifdef POSITION - , IN - ,WEST - , "Interface Read" -#endif - ); + ALLOC1_INTERFACE_END(_param->_nb_port_read); + } + + // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE_BEGIN("write",IN,EAST,_("Interface Write"),_param->_nb_port_write); - in_READ_VAL [i] = interface->set_signal_valack_in ("val" , VAL); - out_READ_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); - if (_param->_have_port_address == true) - in_READ_ADDRESS [i] = interface->set_signal_in ("address", static_cast(log2(_param->_nb_word))); - out_READ_DATA [i] = interface->set_signal_out ("data" , _param->_size_word); - } + ALLOC1_VALACK_IN ( in_WRITE_VAL ,VAL); + ALLOC1_VALACK_OUT(out_WRITE_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_WRITE_ADDRESS,"address",Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_WRITE_DATA ,"data" ,Tdata_t ,_param->_size_word); - // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_write]; - out_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_write]; - if (_param->_have_port_address == true) - in_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_write]; - in_WRITE_DATA = new SC_IN (Tdata_t ) * [_param->_nb_port_write]; - - for (uint32_t i=0; i<_param->_nb_port_write; i++) - { - Interface_fifo * interface = _interfaces->set_interface("write_"+toString(i) -#ifdef POSITION - , IN - ,EAST - , "Interface Write" -#endif - ); - - in_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); - out_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); - if (_param->_have_port_address == true) - in_WRITE_ADDRESS [i] = interface->set_signal_in ("address", static_cast(log2(_param->_nb_word))); - in_WRITE_DATA [i] = interface->set_signal_in ("data" , _param->_size_word); + ALLOC1_INTERFACE_END(_param->_nb_port_write); } if (usage_is_set(_usage,USE_SYSTEMC)) { - // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ALLOC2(reg_DATA,Tdata_t,_param->_nb_bank,_param->_nb_word); - reg_DATA = new Tdata_t * [_param->_nb_bank]; - - for (uint32_t i=0; i<_param->_nb_bank; i++) - { - reg_DATA [i] = new Tdata_t [_param->_nb_word]; - } - - // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - internal_WRITE_VAL = new bool [_param->_nb_port_write]; - internal_WRITE_BANK = new Taddress_t [_param->_nb_port_write]; - internal_WRITE_NUM_REG = new Taddress_t [_param->_nb_port_write]; + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ALLOC1(internal_WRITE_VAL ,bool ,_param->_nb_port_write); + ALLOC1(internal_WRITE_BANK ,Taddress_t,_param->_nb_port_write); + ALLOC1(internal_WRITE_NUM_REG,Taddress_t,_param->_nb_port_write); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - #ifdef POSITION if (usage_is_set(_usage,USE_POSITION)) _component->generate_file(); #endif - + log_printf(FUNC,RegisterFile_Multi_Banked,"allocation","End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_deallocation.cpp (revision 112) @@ -2,9 +2,10 @@ * $Id$ * - * [ Description ] + * [ Description ] * */ #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -23,26 +24,20 @@ delete in_CLOCK; delete in_NRESET; + + DELETE1_SIGNAL( in_READ_VAL ,_param->_nb_port_read,1); + DELETE1_SIGNAL(out_READ_ACK ,_param->_nb_port_read,1); + DELETE1_SIGNAL( in_READ_ADDRESS ,_param->_nb_port_read,_param->_size_address); + DELETE1_SIGNAL(out_READ_DATA ,_param->_nb_port_read,_param->_size_word); - // ----- Interface Read - delete [] in_READ_VAL ; - delete [] out_READ_ACK ; - if (_param->_have_port_address == true) - delete [] in_READ_ADDRESS; - delete [] out_READ_DATA ; + DELETE1_SIGNAL( in_WRITE_VAL ,_param->_nb_port_write,1); + DELETE1_SIGNAL(out_WRITE_ACK ,_param->_nb_port_write,1); + DELETE1_SIGNAL( in_WRITE_ADDRESS,_param->_nb_port_write,_param->_size_address); + DELETE1_SIGNAL( in_WRITE_DATA ,_param->_nb_port_write,_param->_size_word); - // ----- Interface Write - delete [] in_WRITE_VAL ; - delete [] out_WRITE_ACK ; - if (_param->_have_port_address == true) - delete [] in_WRITE_ADDRESS; - delete [] in_WRITE_DATA ; + DELETE2(reg_DATA ,_param->_nb_bank,_param->_nb_word); - // ----- Register - delete [] reg_DATA; - - // ----- Internal - delete [] internal_WRITE_VAL; - delete [] internal_WRITE_BANK; - delete [] internal_WRITE_NUM_REG; + DELETE1(internal_WRITE_VAL ,_param->_nb_port_write); + DELETE1(internal_WRITE_BANK ,_param->_nb_port_write); + DELETE1(internal_WRITE_NUM_REG ,_param->_nb_port_write); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/include/test.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/include/test.h (revision 112) @@ -15,4 +15,5 @@ #include +#include "Common/include/Time.h" #include "Behavioural/Generic/RegisterFile/include/RegisterFile.h" @@ -26,33 +27,2 @@ morpheo::behavioural::generic::registerfile::Parameters * param); -class Time -{ -private : timeval time_begin; -// private : timeval time_end; - -public : Time () - { - gettimeofday(&time_begin ,NULL); - }; - -public : ~Time () - { - cout << *this; - }; - -public : friend ostream& operator<< (ostream& output_stream, - const Time & x) - { - timeval time_end; - - gettimeofday(&time_end ,NULL); - - uint32_t nb_cycles = static_cast(sc_simulation_time()); - - double average = static_cast(nb_cycles) / static_cast(time_end.tv_sec-x.time_begin.tv_sec); - - output_stream << nb_cycles << "\t(" << average << " cycles / seconds )" << endl; - - return output_stream; - } -}; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/RegisterFile.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/RegisterFile.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/RegisterFile.h (revision 112) @@ -53,4 +53,5 @@ public : Component * _component; + private : Interfaces * _interfaces; #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_allocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h" +#include "Behavioural/include/Allocation.h" namespace morpheo{ @@ -35,5 +36,5 @@ ,IN ,WEST - ,"Generalist interface" + ,_("Generalist interface") #endif ); @@ -41,23 +42,26 @@ in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_NO); in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_NO); + + { + ALLOC1_INTERFACE_BEGIN("",IN,SOUTH,_("select interface"),_param->_nb_entity); - in_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_entity]; - if (_param->_encoding_one_hot) - out_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_entity]; + ALLOC1_SIGNAL_IN ( in_VAL ,"val" ,Tcontrol_t,1); + if (_param->_encoding_one_hot) + ALLOC1_SIGNAL_OUT(out_ACK ,"ack" ,Tcontrol_t,1); - for (uint32_t i=0; i<_param->_nb_entity; i++) - { - in_VAL [i] = interface->set_signal_in ("val_"+toString(i),1); - if (_param->_encoding_one_hot) - out_ACK [i] = interface->set_signal_out ("ack_"+toString(i),1); - } + ALLOC1_INTERFACE_END(_param->_nb_entity); + } - if (_param->_encoding_compact) - { - out_ENTITY = interface->set_signal_out ("entity" , _param->_size_entity); - out_ENTITY_ACK = interface->set_signal_out ("entity_ack", 1); - } + if (_param->_encoding_compact) + { + ALLOC0_INTERFACE_BEGIN("",OUT,SOUTH,_("select interface")); - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ALLOC0_SIGNAL_OUT(out_ENTITY ,"entity" ,Tentity_t ,_param->_size_entity); + ALLOC0_SIGNAL_OUT(out_ENTITY_ACK,"entity_ack",Tcontrol_t,1); + + ALLOC0_INTERFACE_END(); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -24,14 +25,14 @@ delete in_NRESET; - delete [] in_VAL; - if (_param->_encoding_one_hot) - delete [] out_ACK; - - if (_param->_encoding_compact) - { - delete out_ENTITY; - delete out_ENTITY_ACK; - } + DELETE1_SIGNAL( in_VAL ,_param->_nb_entity,1); + if (_param->_encoding_one_hot) + DELETE1_SIGNAL(out_ACK ,_param->_nb_entity,1); + if (_param->_encoding_compact) + { + DELETE0_SIGNAL(out_ENTITY ,_param->_size_entity); + DELETE0_SIGNAL(out_ENTITY_ACK,1); + } } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/config_rotate.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/config_rotate.cfg (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/config_rotate.cfg (revision 112) @@ -0,0 +1,7 @@ +Shifter +16 16 *4 # size_data +2 2 +1 # nb_port +0 0 +1 # shift_value +1 2 +1 # rotate +0 2 +1 # direction +0 0 +1 # carry Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/config_shift.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/config_shift.cfg (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/config_shift.cfg (revision 112) @@ -0,0 +1,7 @@ +Shifter +16 16 *4 # size_data +1 2 +1 # nb_port +0 2 +1 # shift_value +0 0 +1 # rotate +0 2 +1 # direction +0 2 +1 # carry Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration.cfg (revision 111) +++ (revision ) @@ -1,7 +1,0 @@ -Shifter -16 16 *4 # size_data -1 2 +1 # nb_port -0 2 +1 # shift_value -0 0 +1 # rotate -0 2 +1 # direction -0 2 +1 # carry Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/include/test.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/include/test.h (revision 112) @@ -14,4 +14,5 @@ #include +#include "Common/include/Time.h" #include "Behavioural/Generic/Shifter/include/Shifter.h" Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/test.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/test.cpp (revision 112) @@ -99,4 +99,6 @@ (*(_Shifter->out_SHIFTER_DATA [i])) (SHIFTER_DATA_OUT [i]); } + + Time * _time = new Time(); /******************************************************** @@ -309,4 +311,5 @@ * Simulation - End ********************************************************/ + delete _time; cout << "<" << name << "> ............ Stop Simulation" << endl; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Parameters.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Parameters.h (revision 112) @@ -29,4 +29,6 @@ public : const uint32_t _size_data_completion; public : const bool _type_completion_bool; + + public : const uint32_t _size_shift ; public : const bool _internal_direction; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters.cpp (revision 112) @@ -29,4 +29,6 @@ _size_data_completion ((carry != external_completion)?0:((_shift_value==0)?size_data:_shift_value)), _type_completion_bool (type_completion_bool), + + _size_shift (static_cast(ceil(log2(_size_data)))), _internal_direction ((direction == internal_right_shift)?_right :_left ), Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_allocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/Shifter/include/Shifter.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -33,5 +34,5 @@ , IN , SOUTH - , "Generalist interface" + , _("Generalist interface") #endif ); @@ -43,49 +44,31 @@ { - // Interface "shifter" - in_SHIFTER_DATA = new SC_IN (Tdata_t) * [_param->_nb_port]; + ALLOC1_INTERFACE_BEGIN("shifter", IN, SOUTH,_("Generalist interface"),_param->_nb_port); + + ALLOC1_SIGNAL_IN ( in_SHIFTER_DATA ,"data" ,Tdata_t ,_param->_size_data); if (_param->_shift_value == 0) - in_SHIFTER_SHIFT = new SC_IN (Tshift_t) * [_param->_nb_port]; - if (_param->_direction == external_direction) - in_SHIFTER_DIRECTION = new SC_IN (Tdirection_t) * [_param->_nb_port]; - if (_param->_rotate == external_rotate) - in_SHIFTER_TYPE = new SC_IN (Ttype_t) * [_param->_nb_port]; - if (_param->_carry == external_carry) - in_SHIFTER_CARRY = new SC_IN (Tcarry_t) * [_param->_nb_port]; - if (_param->_carry == external_completion) + ALLOC1_SIGNAL_IN ( in_SHIFTER_SHIFT ,"shift" ,Tshift_t ,_param->_size_shift); + if (_param->_direction == external_direction) + ALLOC1_SIGNAL_IN ( in_SHIFTER_DIRECTION ,"direction" ,Tdirection_t,1); + if (_param->_rotate == external_rotate) + ALLOC1_SIGNAL_IN ( in_SHIFTER_TYPE ,"type" ,Ttype_t ,1); + if (_param->_carry == external_carry) + ALLOC1_SIGNAL_IN ( in_SHIFTER_CARRY ,"carry" ,Tcarry_t ,1); + if (_param->_carry == external_completion) + { if (_param->_type_completion_bool == true) - in_SHIFTER_CARRY_IN = new SC_IN (Tcontrol_t) * [_param->_nb_port]; + { + ALLOC1_SIGNAL_IN ( in_SHIFTER_CARRY_IN ,"carry_in" ,Tcontrol_t ,1); + } else - in_SHIFTER_COMPLETION= new SC_IN (Tdata_t) * [_param->_nb_port]; - out_SHIFTER_DATA = new SC_OUT(Tdata_t) * [_param->_nb_port]; + { + ALLOC1_SIGNAL_IN ( in_SHIFTER_COMPLETION ,"completion",Tdata_t ,_param->_size_data_completion); + } + } + ALLOC1_SIGNAL_OUT(out_SHIFTER_DATA ,"data" ,Tdata_t ,_param->_size_data); - for (uint32_t i=0; i<_param->_nb_port; i++) - { - Interface_fifo * interface = _interfaces->set_interface("shifter_"+toString(i) -#ifdef POSITION - , IN - , SOUTH - , "Generalist interface" -#endif - ); - - in_SHIFTER_DATA [i] = interface->set_signal_in ("data" ,_param->_size_data); - if (_param->_shift_value == 0) - in_SHIFTER_SHIFT [i] = interface->set_signal_in ("shift" ,static_cast(ceil(log2(_param->_size_data)))); - if (_param->_direction == external_direction) - in_SHIFTER_DIRECTION [i] = interface->set_signal_in ("direction" ,1); - if (_param->_rotate == external_rotate) - in_SHIFTER_TYPE [i] = interface->set_signal_in ("type" ,1); - if (_param->_carry == external_carry) - in_SHIFTER_CARRY [i] = interface->set_signal_in ("carry" ,1); - if (_param->_carry == external_completion) - if (_param->_type_completion_bool == true) - in_SHIFTER_CARRY_IN [i] = interface->set_signal_in ("carry_in" ,1); - else - in_SHIFTER_COMPLETION [i] = interface->set_signal_in ("completion",_param->_size_data_completion); - out_SHIFTER_DATA [i] = interface->set_signal_out ("data" ,_param->_size_data); - } + ALLOC1_INTERFACE_END(_param->_nb_port); } - + #ifdef POSITION if (usage_is_set(_usage,USE_POSITION)) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/Shifter/include/Shifter.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -19,22 +20,28 @@ { #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) - delete in_CLOCK; + delete in_CLOCK; #endif - delete [] in_SHIFTER_DATA ; - if (_param->_shift_value == 0) - delete [] in_SHIFTER_SHIFT ; - if (_param->_direction == external_direction ) - delete [] in_SHIFTER_DIRECTION ; - if (_param->_rotate == external_rotate ) - delete [] in_SHIFTER_TYPE ; - if (_param->_carry == external_carry ) - delete [] in_SHIFTER_CARRY ; - if (_param->_carry == external_completion) - if (_param->_type_completion_bool == true) - delete [] in_SHIFTER_CARRY_IN ; - else - delete [] in_SHIFTER_COMPLETION; - delete [] out_SHIFTER_DATA ; + DELETE1_SIGNAL( in_SHIFTER_DATA ,_param->_nb_port,_param->_size_data); + if (_param->_shift_value == 0) + DELETE1_SIGNAL( in_SHIFTER_SHIFT ,_param->_nb_port,_param->_size_shift); + if (_param->_direction == external_direction) + DELETE1_SIGNAL( in_SHIFTER_DIRECTION ,_param->_nb_port,1); + if (_param->_rotate == external_rotate) + DELETE1_SIGNAL( in_SHIFTER_TYPE ,_param->_nb_port,1); + if (_param->_carry == external_carry) + DELETE1_SIGNAL( in_SHIFTER_CARRY ,_param->_nb_port,1); + if (_param->_carry == external_completion) + { + if (_param->_type_completion_bool == true) + { + DELETE1_SIGNAL( in_SHIFTER_CARRY_IN ,_param->_nb_port,1); + } + else + { + DELETE1_SIGNAL( in_SHIFTER_COMPLETION ,_param->_nb_port,_param->_size_data_completion); + } + } + DELETE1_SIGNAL(out_SHIFTER_DATA ,_param->_nb_port,_param->_size_data); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_declaration.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_declaration.cpp (revision 112) @@ -17,5 +17,5 @@ void Shifter::vhdl_declaration (Vhdl * & vhdl) { - uint32_t log2_size_data = static_cast(ceil(log2(_param._size_data))); + uint32_t log2_size_data = static_cast(ceil(log2(_param->_size_data))); vhdl->set_constant("cst_is_direction_left ",1,_left ); @@ -25,44 +25,44 @@ vhdl->set_constant("cst_is_carry_arithmetic",1,_arithmetic); vhdl->set_constant("cst_is_carry_logic ",1,_logic ); - vhdl->set_constant("cst_completion ",_param._size_data,"(others => '1')"); + vhdl->set_constant("cst_completion ",_param->_size_data,"(others => '1')"); - for (uint32_t i=0; i<_param._nb_port; i++) + for (uint32_t i=0; i<_param->_nb_port; i++) { - if (_param._shift_value != 0) - vhdl->set_constant("shift_"+toString(i),log2_size_data, _param._shift_value); + if (_param->_shift_value != 0) + vhdl->set_constant("shift_"+toString(i),log2_size_data, _param->_shift_value); else vhdl->set_alias ("shift_"+toString(i),std_logic(log2_size_data), "in_SHIFTER_"+toString(i)+"_SHIFT",std_logic_range(log2_size_data)); - if (_param._size_data_completion > 0) + if (_param->_size_data_completion > 0) { - vhdl->set_signal ("shifter_completion_left_"+toString(i)+" ",_param._size_data); - vhdl->set_signal ("shifter_completion_right_"+toString(i)+"",_param._size_data); - vhdl->set_signal ("mask_completion_left_"+toString(i)+" ",_param._size_data); - vhdl->set_signal ("mask_completion_right_"+toString(i)+" ",_param._size_data); + vhdl->set_signal ("shifter_completion_left_"+toString(i)+" ",_param->_size_data); + vhdl->set_signal ("shifter_completion_right_"+toString(i)+"",_param->_size_data); + vhdl->set_signal ("mask_completion_left_"+toString(i)+" ",_param->_size_data); + vhdl->set_signal ("mask_completion_right_"+toString(i)+" ",_param->_size_data); } //-----[ Shift logic Left ]-------------------------------------------- - if (_param._have_shift_logic_left) - vhdl->set_signal ("shift_logic_left_"+toString(i)+" ",_param._size_data); + if (_param->_have_shift_logic_left) + vhdl->set_signal ("shift_logic_left_"+toString(i)+" ",_param->_size_data); //-----[ Shift logic Right ]------------------------------------------- - if (_param._have_shift_logic_right) - vhdl->set_signal ("shift_logic_right_"+toString(i)+" ",_param._size_data); + if (_param->_have_shift_logic_right) + vhdl->set_signal ("shift_logic_right_"+toString(i)+" ",_param->_size_data); //-----[ Shift arithmetic Left ]--------------------------------------- - if (_param._have_shift_arithmetic_left) - vhdl->set_signal ("shift_arithmetic_left_"+toString(i)+" ",_param._size_data); + if (_param->_have_shift_arithmetic_left) + vhdl->set_signal ("shift_arithmetic_left_"+toString(i)+" ",_param->_size_data); //-----[ Shift arithmetic Right ]-------------------------------------- - if (_param._have_shift_arithmetic_right) - vhdl->set_signal ("shift_arithmetic_right_"+toString(i)+"",_param._size_data); + if (_param->_have_shift_arithmetic_right) + vhdl->set_signal ("shift_arithmetic_right_"+toString(i)+"",_param->_size_data); //-----[ Rotate Left ]------------------------------------------------- - if (_param._have_rotate_left) - vhdl->set_signal ("rotate_left_"+toString(i)+" ",_param._size_data); + if (_param->_have_rotate_left) + vhdl->set_signal ("rotate_left_"+toString(i)+" ",_param->_size_data); //-----[ Rotate Right ]------------------------------------------------ - if (_param._have_rotate_right) - vhdl->set_signal ("rotate_right_"+toString(i)+" ",_param._size_data); + if (_param->_have_rotate_right) + vhdl->set_signal ("rotate_right_"+toString(i)+" ",_param->_size_data); } }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_allocation.cpp (revision 112) @@ -53,13 +53,15 @@ // ~~~~~[ Interface : "input" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("input", IN, WEST, "List of data unsort",_param->_nb_input); + ALLOC1_INTERFACE_BEGIN("input", IN, WEST, "List of data unsort",_param->_nb_input); ALLOC1_SIGNAL_IN(in_INPUT_VAL ,"val" , Tcontrol_t, 1); ALLOC1_SIGNAL_IN(in_INPUT_DATA,"data", Tdata_t , _param->_size_data); + + ALLOC1_INTERFACE_END(_param->_nb_input); } // ~~~~~[ Interface : "output" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("output",OUT, EAST, "List of data sort",_param->_nb_output); + ALLOC1_INTERFACE_BEGIN("output",OUT, EAST, "List of data sort",_param->_nb_output); ALLOC1_SIGNAL_OUT(out_OUTPUT_VAL ,"val" ,Tcontrol_t,1); @@ -68,4 +70,6 @@ if (_param->_have_port_data_out) ALLOC1_SIGNAL_OUT(out_OUTPUT_DATA ,"data" ,Tdata_t ,_param->_size_data ); + + ALLOC1_INTERFACE_END(_param->_nb_output); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/Sort/include/Sort.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -25,12 +26,14 @@ delete in_NRESET; - delete [] in_INPUT_VAL ; - delete [] in_INPUT_DATA ; - delete [] out_OUTPUT_VAL ; - if (_param->_have_port_index_out) - delete [] out_OUTPUT_INDEX; - if (_param->_have_port_data_out) - delete [] out_OUTPUT_DATA ; + DELETE1_SIGNAL(in_INPUT_VAL ,_param->_nb_input, 1); + DELETE1_SIGNAL(in_INPUT_DATA,_param->_nb_input, _param->_size_data); + + DELETE1_SIGNAL(out_OUTPUT_VAL ,_param->_nb_output,1); + if (_param->_have_port_index_out) + DELETE1_SIGNAL(out_OUTPUT_INDEX,_param->_nb_output,_param->_size_address); + if (_param->_have_port_data_out) + DELETE1_SIGNAL(out_OUTPUT_DATA ,_param->_nb_output,_param->_size_data ); } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp (revision 112) @@ -2,5 +2,5 @@ * $Id$ * - * [ Description ] + * [ Description ] * */ @@ -28,5 +28,5 @@ _interfaces = entity->set_interfaces(); - // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { Interface_fifo * interface = _interfaces->set_interface("" @@ -40,7 +40,7 @@ } - // ~~~~~[ Interface : "access" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "access" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("access",IN,WEST, "Access", _param->_nb_access); + ALLOC1_INTERFACE_BEGIN("access",IN,WEST, "Access", _param->_nb_access); ALLOC1_VALACK_IN ( in_ACCESS_VAL ,VAL); @@ -50,17 +50,19 @@ ALLOC1_SIGNAL_IN ( in_ACCESS_ENTITY ,"entity" ,Tentity_t ,log2(_param->_nb_entity )); ALLOC1_SIGNAL_OUT(out_ACCESS_VICTIM ,"victim" ,Tentity_t ,log2(_param->_nb_entity )); + + ALLOC1_INTERFACE_END(_param->_nb_access); } if (usage_is_set(_usage,USE_SYSTEMC)) { - // -----[ Register ]--------------------------------------------------- - reg_TABLE = new entry_t * [_param->_size_table]; - - for (uint32_t i=0; i<_param->_size_table; i++) - reg_TABLE [i] = new entry_t (_param->_nb_entity); - - // -----[ Internal ]--------------------------------------------------- - internal_ACCESS_ACK = new Tcontrol_t [_param->_nb_access]; - internal_ACCESS_VICTIM = new Tentity_t [_param->_nb_access]; + // -----[ Register ]--------------------------------------------------- + reg_TABLE = new entry_t * [_param->_size_table]; + + for (uint32_t i=0; i<_param->_size_table; i++) + reg_TABLE [i] = new entry_t (_param->_nb_entity); + + // -----[ Internal ]--------------------------------------------------- + ALLOC1(internal_ACCESS_ACK ,Tcontrol_t,_param->_nb_access); + ALLOC1(internal_ACCESS_VICTIM,Tentity_t ,_param->_nb_access); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Victim_Pseudo_LRU.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -20,19 +21,15 @@ delete in_CLOCK; delete in_NRESET; - // -----[ Interface access ]------------------------------------------- - delete [] in_ACCESS_VAL ; - delete [] out_ACCESS_ACK ; - if (_param->_size_address>1) - delete [] in_ACCESS_ADDRESS; - delete [] in_ACCESS_HIT ; - delete [] in_ACCESS_ENTITY ; - delete [] out_ACCESS_VICTIM ; - - // -----[ Register ]--------------------------------------------------- - delete [] reg_TABLE; - // -----[ Internal ]--------------------------------------------------- - delete [] internal_ACCESS_ACK ; - delete [] internal_ACCESS_VICTIM; + DELETE1_SIGNAL( in_ACCESS_VAL ,_param->_nb_access,1); + DELETE1_SIGNAL(out_ACCESS_ACK ,_param->_nb_access,1); + DELETE1_SIGNAL( in_ACCESS_HIT ,_param->_nb_access,1); + DELETE1_SIGNAL( in_ACCESS_ADDRESS,_param->_nb_access,log2(_param->_size_address)); + DELETE1_SIGNAL( in_ACCESS_ENTITY ,_param->_nb_access,log2(_param->_nb_entity )); + DELETE1_SIGNAL(out_ACCESS_VICTIM ,_param->_nb_access,log2(_param->_nb_entity )); + + DELETE1(reg_TABLE ,_param->_size_table); + DELETE1(internal_ACCESS_ACK ,_param->_nb_access); + DELETE1(internal_ACCESS_VICTIM,_param->_nb_access); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim_allocation.cpp (revision 112) @@ -31,11 +31,11 @@ // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - __ALLOC_SIGNAL(in_CLOCK ,"in_CLOCK" ,SC_CLOCK ); - __ALLOC_SIGNAL(in_NRESET,"in_NRESET",SC_IN (Tcontrol_t)); + __ALLOC0_SIGNAL(in_CLOCK ,"in_CLOCK" ,SC_CLOCK ); + __ALLOC0_SIGNAL(in_NRESET,"in_NRESET",SC_IN (Tcontrol_t)); } // ~~~~~[ Interface : "Access" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - __ALLOC1_INTERFACE("ACCESS",_param->_nb_access); + __ALLOC1_INTERFACE_BEGIN("ACCESS",_param->_nb_access); __ALLOC1_SIGNAL_IN ( in_ACCESS_VAL ,"VAL" ,Tcontrol_t); @@ -46,4 +46,6 @@ __ALLOC1_SIGNAL_IN ( in_ACCESS_ENTITY ,"ENTITY" ,Tentity_t ); __ALLOC1_SIGNAL_OUT(out_ACCESS_VICTIM ,"VICTIM" ,Tentity_t ); + + __ALLOC1_INTERFACE_END(_param->_nb_access); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim_deallocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim_deallocation.cpp (revision 112) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/Victim/include/Victim.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis (revision 112) @@ -66,5 +66,6 @@ @\ $(ECHO) "Create work-space : $@"; \ - $(MODELTECH_VLIB) $@; + $(MODELTECH_VLIB) $@; \ + $(MODELTECH_VMAP) $(XILINX_CORELIB); $(DIR_LOG)/%.sim.log : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Allocation.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Allocation.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Allocation.h (revision 112) @@ -14,4 +14,7 @@ // =====[ ALLOCATION / DELETE of ARRAY ]================================= // ====================================================================== +#define ALLOC0(var,type) \ + var = new type + #define ALLOC1(var,type,s1) \ var = new type [s1] @@ -103,5 +106,6 @@ // ---------------------------------------------------------------------- -#define __ALLOC_SIGNAL(sig, name, type) \ + +#define __ALLOC0_SIGNAL(sig, name, type) \ { \ sig = new type (name); \ @@ -109,30 +113,32 @@ #ifdef POSITION -#define ALLOC_INTERFACE( name, direction, localisation, str) \ +#define ALLOC0_INTERFACE_BEGIN( name, direction, localisation, str) \ INTERFACE_PRINT(name); \ morpheo::behavioural::Interface_fifo * interface = _interfaces->set_interface( name, direction, localisation, str); #else -#define ALLOC_INTERFACE( name, direction, localisation, str) \ +#define ALLOC0_INTERFACE_BEGIN( name, direction, localisation, str) \ INTERFACE_PRINT(name); \ morpheo::behavioural::Interface_fifo * interface = _interfaces->set_interface( name); #endif -#define ALLOC_VAL_ACK_IN( sig, name, type) \ +#define ALLOC0_INTERFACE_END() + +#define ALLOC0_VAL_ACK_IN( sig, name, type) \ { \ sig = interface->set_signal_valack_in (name, type); \ } -#define ALLOC_VAL_ACK_OUT( sig, name, type) \ +#define ALLOC0_VAL_ACK_OUT( sig, name, type) \ { \ sig = interface->set_signal_valack_out(name, type); \ } -#define ALLOC_VALACK_IN( sig, type) \ +#define ALLOC0_VALACK_IN( sig, type) \ { \ sig = interface->set_signal_valack_in (type); \ } -#define ALLOC_VALACK_OUT( sig, type) \ +#define ALLOC0_VALACK_OUT( sig, type) \ { \ sig = interface->set_signal_valack_out(type); \ } -#define ALLOC_SIGNAL_IN( sig, name, type, size) \ +#define ALLOC0_SIGNAL_IN( sig, name, type, size) \ if (size > 0) \ { \ @@ -144,5 +150,5 @@ } -#define ALLOC_SIGNAL_OUT( sig, name, type, size) \ +#define ALLOC0_SIGNAL_OUT( sig, name, type, size) \ if (size > 0) \ { \ @@ -154,5 +160,5 @@ } -#define DELETE_SIGNAL( sig, size) \ +#define DELETE0_SIGNAL( sig, size) \ if (size > 0) \ { \ @@ -160,9 +166,9 @@ } -#define ALLOC_SC_SIGNAL( sig, name, type) \ +#define ALLOC0_SC_SIGNAL( sig, name, type) \ sc_signal * sig = new sc_signal (name); \ PRINT_SIGNAL_ADDRESS(name,sig); -#define INSTANCE_SC_SIGNAL(component, sig) \ +#define INSTANCE0_SC_SIGNAL(component, sig) \ { \ TEST_SIGNAL(component->sig->name(),component->sig); \ @@ -171,5 +177,5 @@ } -#define _INSTANCE_SC_SIGNAL(component, sig1,sig2) \ +#define _INSTANCE0_SC_SIGNAL(component, sig1,sig2) \ { \ TEST_SIGNAL(component->sig1->name(),component->sig1); \ @@ -178,26 +184,8 @@ } -#define DELETE_SC_SIGNAL( sig) \ +#define DELETE0_SC_SIGNAL( sig) \ { \ delete sig; \ } - - -#define __ALLOC0_SIGNAL(sig, name, type) __ALLOC_SIGNAL(sig, name, type) - -#define ALLOC0_INTERFACE( name, direction, localisation, str) ALLOC_INTERFACE( name, direction, localisation, str) - -#define ALLOC0_VAL_ACK_IN( sig, name, type) ALLOC_VAL_ACK_IN( sig, name, type) -#define ALLOC0_VAL_ACK_OUT( sig, name, type) ALLOC_VAL_ACK_OUT( sig, name, type) -#define ALLOC0_VALACK_IN( sig, type) ALLOC_VALACK_IN( sig, type) -#define ALLOC0_VALACK_OUT( sig, type) ALLOC_VALACK_OUT( sig, type) -#define ALLOC0_SIGNAL_IN( sig, name, type, size) ALLOC_SIGNAL_IN( sig, name, type, size) -#define ALLOC0_SIGNAL_OUT( sig, name, type, size) ALLOC_SIGNAL_OUT( sig, name, type, size) -#define DELETE0_SIGNAL( sig, size) DELETE_SIGNAL( sig, size) - -#define ALLOC0_SC_SIGNAL( sig, name, type) ALLOC_SC_SIGNAL( sig, name, type) -#define INSTANCE0_SC_SIGNAL(component, sig) INSTANCE_SC_SIGNAL(component, sig) -#define _INSTANCE0_SC_SIGNAL(component, sig) _INSTANCE_SC_SIGNAL(component, sig) -#define DELETE0_SC_SIGNAL( sig) DELETE_SC_SIGNAL( sig) // ---------------------------------------------------------------------- @@ -205,9 +193,11 @@ // ---------------------------------------------------------------------- -#define __ALLOC1_INTERFACE(name, x1) \ +#define __ALLOC1_INTERFACE_BEGIN(name, x1) \ INTERFACE_PRINT(name); \ const std::string interface_name = name; \ const uint32_t iterator_1 = x1; +#define __ALLOC1_INTERFACE_END(x1) + #define __ALLOC1_SIGNAL_IN( sig, name, type) \ { \ @@ -233,5 +223,5 @@ #ifdef POSITION -#define ALLOC1_INTERFACE( name, direction, localisation, str, x1) \ +#define ALLOC1_INTERFACE_BEGIN( name, direction, localisation, str, x1) \ INTERFACE_PRINT(name); \ const uint32_t iterator_1 = x1; \ @@ -245,5 +235,5 @@ } #else -#define ALLOC1_INTERFACE( name, direction, localisation, str, x1) \ +#define ALLOC1_INTERFACE_BEGIN( name, direction, localisation, str, x1) \ INTERFACE_PRINT(name); \ const uint32_t iterator_1 = x1; \ @@ -257,4 +247,6 @@ } #endif + +#define ALLOC1_INTERFACE_END(x1) #define ALLOC1_VAL_ACK_IN( sig, name, type) \ @@ -377,5 +369,5 @@ #ifdef POSITION -#define ALLOC2_INTERFACE( name, direction, localisation, str, x1, x2) \ +#define ALLOC2_INTERFACE_BEGIN( name, direction, localisation, str, x1, x2) \ INTERFACE_PRINT(name); \ uint32_t iterator_1 = 0; \ @@ -397,5 +389,5 @@ } #else -#define ALLOC2_INTERFACE( name, direction, localisation, str, x1, x2) \ +#define ALLOC2_INTERFACE_BEGIN( name, direction, localisation, str, x1, x2) \ INTERFACE_PRINT(name); \ uint32_t iterator_1 = 0; \ @@ -417,4 +409,9 @@ } #endif + +#define ALLOC2_INTERFACE_END(x1, x2) \ + for (uint32_t it1=0; it1 + +namespace morpheo { +namespace behavioural { + + typedef enum + { + MODEL_SYSTEMC, + MODEL_VHDL + } model_type_t; + + typedef struct + { + model_type_t type ; + debug_verbosity_t debug; + } model_t; + + class Model + { + private : static const model_type_t default_type = MODEL_SYSTEMC; + private : static const debug_verbosity_t default_debug = DEBUG_NONE; + + private : std::map models; + + public : Model (void); + public : ~Model (void); + public : void set_model (std::string component, model_type_t type, debug_verbosity_t debug); + public : model_type_t get_type (std::string component); + public : debug_verbosity_t get_debug (std::string component); + }; + +}; // end namespace behavioural + + template<> inline morpheo::behavioural::model_type_t fromString(const std::string& x) + { + if ( (x.compare(toString(static_cast(morpheo::behavioural::MODEL_SYSTEMC))) == 0) or + (x.compare("model_systemc") == 0) or + (x.compare("systemc") == 0) + ) + return morpheo::behavioural::MODEL_SYSTEMC; + if ( (x.compare(toString(static_cast(morpheo::behavioural::MODEL_VHDL))) == 0) or + (x.compare("model_vhdl") == 0) or + (x.compare("vhdl") == 0)) + return morpheo::behavioural::MODEL_VHDL; + throw (ERRORMORPHEO ("fromString","Unknow string : \""+x+"\"\n")); + }; + +}; // end namespace morpheo + +#endif + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/SPR_access_mode.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/SPR_access_mode.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/SPR_access_mode.h (revision 112) @@ -32,18 +32,19 @@ public : ~SPR_access_mode(); - public : spr_address_t translate_address (Tgeneral_data_t address); + public : spr_address_t translate_address (Tgeneral_data_t address); - public : bool valid (uint32_t num_group, uint32_t num_reg); - public : bool valid (spr_address_t address); - public : bool exist (uint32_t num_group, uint32_t num_reg); - public : bool exist (spr_address_t address); - public : bool read (spr_address_t address, Tcontrol_t SM, Tcontrol_t SUMRA); - public : bool write (spr_address_t address, Tcontrol_t SM, Tcontrol_t SUMRA); - - public : void implement_group (uint32_t num_group, uint32_t nb_reg); - public : uint32_t implement_group (uint32_t num_group); - public : void change_mode (uint32_t num_group, uint32_t num_reg, spr_access_mode_t new_mode); - public : void invalid_register(uint32_t num_group, uint32_t num_reg); - + public : bool valid (uint32_t num_group, uint32_t num_reg); + public : bool valid (spr_address_t address); + public : bool exist (uint32_t num_group, uint32_t num_reg); + public : bool exist (spr_address_t address); + public : bool read (spr_address_t address, Tcontrol_t SM, Tcontrol_t SUMRA); + public : bool write (spr_address_t address, Tcontrol_t SM, Tcontrol_t SUMRA); + public : spr_access_mode_t get_mode (uint32_t num_group, uint32_t num_reg); + public : spr_access_mode_t get_mode (spr_address_t address); + + public : void implement_group (uint32_t num_group, uint32_t nb_reg); + public : uint32_t implement_group (uint32_t num_group); + public : void change_mode (uint32_t num_group, uint32_t num_reg, spr_access_mode_t new_mode); + public : void invalid_register(uint32_t num_group, uint32_t num_reg); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Simulation.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Simulation.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Simulation.h (revision 112) @@ -11,5 +11,5 @@ #include "Common/include/Debug.h" - +#include "Behavioural/include/Model.h" #include #include @@ -22,4 +22,5 @@ extern double _simulation_nb_instruction; extern std::vector _simulation_nb_instruction_commited; +extern Model _model; bool simulation_test_end (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 112) @@ -10,9 +10,9 @@ #define MORPHEO_MAJOR_VERSION "0" #define MORPHEO_MINOR_VERSION "2" -#define MORPHEO_REVISION "111" +#define MORPHEO_REVISION "112" #define MORPHEO_CODENAME "Castor" -#define MORPHEO_DATE_DAY "27" -#define MORPHEO_DATE_MONTH "02" +#define MORPHEO_DATE_DAY "18" +#define MORPHEO_DATE_MONTH "03" #define MORPHEO_DATE_YEAR "2009" Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface.cpp (revision 112) @@ -70,15 +70,9 @@ log_printf(FUNC,Behavioural,"~Interface","Begin"); - if (_list_signal->empty()== false) - { - std::list::iterator i = _list_signal->begin(); - - while (i != _list_signal->end()) - { - delete (*i); - ++i; - } - } - + for (std::list::iterator it = _list_signal->begin(); + it != _list_signal->end(); + ++it) + delete (*it); + delete _list_signal; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_set_signal.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_set_signal.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_set_signal.cpp (revision 112) @@ -20,5 +20,5 @@ std::string signame = signal_name(_name, name, direction); - Signal * sig = new Signal (signame, direction, size, presence_port); + Signal * sig = new Signal (signame, direction, size, presence_port); _list_signal->push_back (sig); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces.cpp (revision 112) @@ -39,14 +39,8 @@ #endif - if (_list_interface->empty()== false) - { - std::list::iterator i = _list_interface->begin(); - - while (i != _list_interface->end()) - { - delete (*i); - ++i; - } - } + for (std::list::iterator it = _list_interface->begin(); + it!=_list_interface->end(); + ++it) + delete (*it); delete _list_interface; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Model.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Model.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Model.cpp (revision 112) @@ -0,0 +1,30 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Model.h" + +namespace morpheo { +namespace behavioural { + +#undef FUNCTION +#define FUNCTION "Model::Model" + Model::Model (void) + { + log_begin(Behavioural,FUNCTION); + log_end(Behavioural,FUNCTION); + } + +#undef FUNCTION +#define FUNCTION "Model::~Model" + Model::~Model(void) + { + log_begin(Behavioural,FUNCTION); + log_end(Behavioural,FUNCTION); + } + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Model_get_debug.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Model_get_debug.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Model_get_debug.cpp (revision 112) @@ -0,0 +1,34 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Model.h" + +namespace morpheo { +namespace behavioural { + +#undef FUNCTION +#define FUNCTION "Model::get_debug" + debug_verbosity_t Model::get_debug (std::string component) + { + log_begin(Behavioural,FUNCTION); + + debug_verbosity_t _return; + + std::map::iterator it = models.find(component); + + if (it != models.end()) + _return = it->second.debug; + else + _return = default_debug; + + log_end(Behavioural,FUNCTION); + + return _return; + } + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Model_get_type.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Model_get_type.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Model_get_type.cpp (revision 112) @@ -0,0 +1,34 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Model.h" + +namespace morpheo { +namespace behavioural { + +#undef FUNCTION +#define FUNCTION "Model::get_type" + model_type_t Model::get_type (std::string component) + { + log_begin(Behavioural,FUNCTION); + + model_type_t _return; + + std::map::iterator it = models.find(component); + + if (it != models.end()) + _return = it->second.type; + else + _return = default_type; + + log_end(Behavioural,FUNCTION); + + return _return; + } + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Model_set_model.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Model_set_model.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Model_set_model.cpp (revision 112) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Model.h" + +namespace morpheo { +namespace behavioural { + +#undef FUNCTION +#define FUNCTION "Model::get_type" + void Model::set_model (std::string component, model_type_t type, debug_verbosity_t debug) + { + log_begin(Behavioural,FUNCTION); + + model_t model; + model.type = type ; + model.debug = debug; + + models [component] = model; + + log_end(Behavioural,FUNCTION); + } + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_get_mode.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_get_mode.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_get_mode.cpp (revision 112) @@ -0,0 +1,18 @@ +#include "Behavioural/include/SPR_access_mode.h" + +namespace morpheo { +namespace behavioural { + + spr_access_mode_t SPR_access_mode::get_mode (spr_address_t address) + { + return get_mode(address._group, address._register); + } + + spr_access_mode_t SPR_access_mode::get_mode (uint32_t num_group, uint32_t num_reg) + { + return _spr_generic [num_group][num_reg]; + } + +}; // end namespace behavioural +}; // end namespace morpheo + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation.cpp (revision 112) @@ -17,4 +17,5 @@ double _simulation_nb_instruction; std::vector _simulation_nb_instruction_commited; + Model _model; void simulation_init (double nb_cycle, Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Debug.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Debug.h (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Debug.h (revision 112) @@ -34,4 +34,5 @@ #include #include +#include "Common/include/MemCheck.h" namespace morpheo { Index: trunk/IPs/systemC/processor/Morpheo/Common/include/MemCheck.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/MemCheck.h (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/MemCheck.h (revision 112) @@ -0,0 +1,22 @@ +#ifndef MEMCHECK_H +#define MEMCHECK_H +#ifdef DEBUG_MEMORY_LEAK + +#include // For size_t + +// Usurp the new operator (both scalar and array versions) +void* operator new(std::size_t, const char*, long); +void* operator new[](std::size_t, const char*, long); +#define new new (__FILE__, __LINE__) + +extern bool traceFlag; +#define TRACE_ON() traceFlag = true +#define TRACE_OFF() traceFlag = false + +extern bool activeFlag; +#define MEM_ON() activeFlag = true +#define MEM_OFF() activeFlag = false + +#endif // DEBUG_MEMORY_LEAK +#endif // MEMCHECK_H + Index: trunk/IPs/systemC/processor/Morpheo/Common/src/MemCheck.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/src/MemCheck.cpp (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Common/src/MemCheck.cpp (revision 112) @@ -0,0 +1,106 @@ +#ifdef DEBUG_MEMORY_LEAK + +#include +#include +#include +#include +using namespace std; +#undef new + +// Global flags set by macros in MemCheck.h +bool traceFlag = false; +bool activeFlag = true; + +namespace { + + // Memory map entry type + struct Info { + void* ptr; + const char* file; + long line; + }; + + // Memory map data + const size_t MAXPTRS = 10000u; + Info memMap[MAXPTRS]; + size_t nptrs = 0; + + // Searches the map for an address + int findPtr(void* p) { + for(size_t i = 0; i < nptrs; ++i) + if(memMap[i].ptr == p) + return i; + return -1; + } + + void delPtr(void* p) { + int pos = findPtr(p); + assert(pos >= 0); + // Remove pointer from map + for(size_t i = pos; i < nptrs-1; ++i) + memMap[i] = memMap[i+1]; + --nptrs; + } + + // Dummy type for static destructor + struct Sentinel { + ~Sentinel() { + if(nptrs > 0) { + printf("Leaked memory at:\n"); + for(size_t i = 0; i < nptrs; ++i) + printf("\t%p (file: %s, line %ld)\n", + memMap[i].ptr, memMap[i].file, memMap[i].line); + } + else + printf("No user memory leaks!\n"); + } + }; + + // Static dummy object + Sentinel s; + +} // End anonymous namespace + +// Overload scalar new +void* operator new(size_t siz, const char* file, long line) { + void* p = malloc(siz); + if(activeFlag) { + if(nptrs == MAXPTRS) { + printf("memory map too small (increase MAXPTRS)\n"); + exit(1); + } + memMap[nptrs].ptr = p; + memMap[nptrs].file = file; + memMap[nptrs].line = line; + ++nptrs; + } + if(traceFlag) { + printf("Allocated %u bytes at address %p ", siz, p); + printf("(file: %s, line: %ld)\n", file, line); + } + return p; +} + +// Overload array new +void* operator new[](size_t siz, const char* file, long line) { + return operator new(siz, file, line); +} + +// Override scalar delete +void operator delete(void* p) { + if(findPtr(p) >= 0) { + free(p); + assert(nptrs > 0); + delPtr(p); + if(traceFlag) + printf("Deleted memory at address %p\n", p); + } + else if(!p && activeFlag) + printf("Attempt to delete unknown pointer: %p\n", p); +} + +// Override array delete +void operator delete[](void* p) { + operator delete(p); +} +#endif // DEBUG_MEMORY_LEAK Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg (revision 112) @@ -17,5 +17,5 @@ - + @@ -34,5 +34,4 @@ - @@ -50,5 +49,5 @@ - + @@ -91,11 +90,11 @@ - - + + - - - - + + + + @@ -125,6 +124,6 @@ - - + + Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_min.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_min.cfg (revision 112) @@ -33,5 +33,4 @@ - Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_1.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_1.cfg (revision 112) @@ -33,5 +33,4 @@ - Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_2.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_2.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_2.cfg (revision 112) @@ -33,5 +33,4 @@ - Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_3.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_3.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_3.cfg (revision 112) @@ -33,5 +33,4 @@ - Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_4.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_4.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_4.cfg (revision 112) @@ -33,5 +33,4 @@ - Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_w2_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_w2_1.cfg (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_w2_1.cfg (revision 112) @@ -33,5 +33,4 @@ - Index: trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen (revision 112) @@ -40,5 +40,4 @@ - @@ -53,7 +52,7 @@ - - - + + + @@ -93,10 +92,10 @@ - + - + - + Index: trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 112) @@ -8,5 +8,5 @@ - + @@ -23,78 +23,78 @@ - - - + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Script/SelfTest.sh =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Script/SelfTest.sh (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Script/SelfTest.sh (revision 112) @@ -20,5 +20,8 @@ "Behavioural/Custom" + "Behavioural/Generic/Comparator" "Behavioural/Generic/Counter" + "Behavioural/Generic/Divider" + "Behavioural/Generic/Multiplier" "Behavioural/Generic/Priority" "Behavioural/Generic/Queue_Control" Index: trunk/IPs/systemC/processor/Morpheo/Script/distexe.sh =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Script/distexe.sh (revision 112) +++ trunk/IPs/systemC/processor/Morpheo/Script/distexe.sh (revision 112) @@ -0,0 +1,107 @@ +#!/bin/bash + +#----------------------------------------------------------- +# $Id$ +#----------------------------------------------------------- + +# Need : test, echo, cd, dirname, basename, ssh + +#-----[ distexe_usage ]------------------------------------- +function distexe_usage () +{ + echo "Usage : ${0} file [ dir ]"; + echo "Arguments : "; + echo " * file : list of command"; + echo " * dir : work directory (default is current directory)."; +# echo " * nb_process : number of process (default (and maximum) is the number of processor)"; + echo ""; + echo "Note : "; + echo " * File content list of command. Each line is execute by an host."; + echo " A line can content many shell command."; + echo " Don't forgot the final end of line (else the last command is not executed)"; + echo " example : "; + echo ' echo "export PATH=${PATH}:${HOME}/my_appli/bin; my_appli 13" > command_file.txt'; + echo ' echo "export PATH=${PATH}:${HOME}/my_appli/bin; my_appli 21" >> command_file.txt'; + echo ' echo "export PATH=${PATH}:${HOME}/my_appli/bin; my_appli 7" >> command_file.txt'; + echo ' echo "" >> command_file.txt'; + echo " * For each command, a directory (in work directory) is created : Task_X (X is the number of line in command file)."; + echo " The command is execute in this directory. (Warning, set your environment !)."; + echo " Two file is generate : \"distexe.output\" is the output (standard and error) of the execution, and \"distexe.command\" is the command lunch."; +# echo " * A command empty (no command on a line of file) is a synchronisation with all process" + echo " * The environment variable DISTEXE_HOSTS list hosts to execute command"; + echo " After each host, a number is to the number of process. It's optionnal, the default value is the number of processor."; + echo " example :"; + echo ' export DISTEXE_HOSTS="localhost/1 nod/4 gdi/2"'; + echo " * All hosts must have network file systems (per example nfs or samba)"; + echo " Work directory must be in this network file systems !"; + echo ""; + exit; +} + +#-----[ distexe_test_usage ]-------------------------------- +function distexe_test_usage () +{ + if test ${#} -ne 1 -a ${#} -ne 2; then + distexe_usage; + fi; + + if test -z "${MORPHEO_SCRIPT}"; then + echo "Environment variable MORPHEO_SCRIPT is not set"; + distexe_usage; + fi; + + if test ! -f ${1}; then + echo "File \"${1}\" is invalid"; + distexe_usage; + fi; + + if test ! -s ${1}; then + echo "File \"${1}\" is empty."; + distexe_usage; + fi; + + if test ${#} -eq 2; then + if test ! -d ${2}; then + echo "Directory \"${2}\" is invalid."; + distexe_usage; + fi; + fi; + +} + +#-----[ distexe ]------------------------------------------- +function distexe () +{ + distexe_test_usage ${*}; + + # construct file command with absolute path + cd $(dirname ${1}); + local FILE_CMD=${PWD}/$(basename ${1}); + cd -; + + # Absoulte path of work directory + local DIR_EXE; + if test ${#} -eq 2; then + cd ${2}; + DIR_EXE=${PWD}; + cd -; + else + DIR_EXE=${PWD}; + fi; + + local hosts="${DISTEXE_HOSTS}"; + + for line in ${hosts}; do + local host=$(echo ${line} | cut -d/ -f1); + local -i nb_process=$(echo ${line} | cut -d/ -f2); + + echo " * station : ${host} (${nb_process}) ... "; + + # lunch service + local cmd="export MORPHEO_SCRIPT=${MORPHEO_SCRIPT};${MORPHEO_SCRIPT}/execute_n.sh ${DIR_EXE} ${FILE_CMD} ${nb_process};"; + ssh ${host} ${cmd} & + done; +} + +#-----[ Corps ]--------------------------------------------- +distexe ${*}; Index: trunk/IPs/systemC/processor/Morpheo/Script/execute.sh =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Script/execute.sh (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Script/execute.sh (revision 112) @@ -5,17 +5,10 @@ #----------------------------------------------------------- -declare -a COMMAND; -declare -i CPT_OLD; -declare -i CPT; -declare FILE_CMD=; -declare FILE_CPT=; -declare FILE_CPU=; -declare LOCK_CPT="${HOME}/.lock-cpt"; -declare LOCK_CPU="${HOME}/.lock-cpu"; +#-----[ global variable ]----------------------------------- #-----[ lock ]---------------------------------------------- function lock () { - lockfile -1 $1; + lockfile -1 ${1}; } @@ -23,30 +16,72 @@ function unlock () { - rm -f $1; + rm -f ${1}; } -#-----[ main ]---------------------------------------------- -function main () +#-----[ my_date ]------------------------------------------- +function my_date () { - # no test, because the script execute_n have make all test - FILE_CMD=$1; - FILE_CPT=$2; - FILE_CPU=$3; + date +"%F %T"; +} - lock $LOCK_CPT; - if test ! -s $FILE_CPT; then - echo "0" > $FILE_CPT; +#-----[ execute_usage ]------------------------------------- +function execute_usage () +{ + echo "Usage : ${0} work_dir file_cmd file_cpt file_cpu"; + echo "Arguments : "; + echo " * work_dir : directory to execute command"; + echo " * file_cmd : list of command"; + echo " * file_cpt : file with the index of next command to execute"; + echo " * file_cpu : tmp file to stock the current index"; + exit; +} + +#-----[ execute_test_usage ]-------------------------------- +function execute_test_usage () +{ + if test ${#} -ne 4; then + execute_usage; fi; - unlock $LOCK_CPT; - # lit les fichiers ligne par ligne et le place dans un tableau + if test ! -d ${1}; then + echo "Directory ${1} is invalid"; + fi; +} + +#-----[ execute ]------------------------------------------- +function execute () +{ + # test_usage + execute_test_usage ${*}; + + local -a COMMAND; + local -i CPT_OLD; + local -i CPT; + local WORK_DIR=${1}; + local FILE_CMD=${2}; + local FILE_CPT=${3}; + local FILE_CPU=${4}; + local LOCK_CPT="${WORK_DIR}/.lock-cpt"; + local LOCK_CPU="${WORK_DIR}/.lock-cpu"; + local FILE_CMD="distexe.command"; + local FILE_OUT="distexe.output"; + + + # Init CPT if this thread is the first + lock ${LOCK_CPT}; + if test ! -s ${FILE_CPT}; then + echo "0" > ${FILE_CPT}; + fi; + unlock ${LOCK_CPT}; + + # read, line by line, the command file and write in array CPT=0; while read line; do - COMMAND[$CPT]="$line"; - CPT=$(($CPT+1)); - done < $1; + COMMAND[${CPT}]="${line}"; + CPT=$((${CPT}+1)); + done < ${FILE_CMD}; - echo " * <$$> {"`date +"%F %T"`"} is ready"; + echo " * <${HOSTNAME}-$$> {"$(my_date)"} is ready"; # infinite loop @@ -56,13 +91,14 @@ while test 1; do # Take a number - CPT_OLD=$CPT; + CPT_OLD=${CPT}; - lock $LOCK_CPT; - CPT=`cat $FILE_CPT`; # read the index - echo "$(($CPT+1))" > $FILE_CPT; # write the next index - unlock $LOCK_CPT; + # Read the index, and increase + lock ${LOCK_CPT}; + CPT=$(cat ${FILE_CPT}); + echo "$((${CPT}+1))" > ${FILE_CPT}; + unlock ${LOCK_CPT}; # test if this number is valid - if test $CPT -ge ${#COMMAND[*]}; then + if test ${CPT} -ge ${#COMMAND[*]}; then CPT=${#COMMAND[*]}; fi; @@ -70,46 +106,46 @@ # test if between the cpt_old and cpt, there are a synchronisation command -# local -i CPT_SYNC=$CPT_OLD; +# local -i CPT_SYNC=${CPT}_OLD; # -# while test $CPT_SYNC -lt $CPT; do -# if test -z "${COMMAND[$CPT_SYNC]}"; then -# echo " * <$$> {"`date +"%F %T"`"} synchronisation [$CPT_SYNC]"; +# while test ${CPT}_SYNC -lt ${CPT}; do +# if test -z "${COMMAND[${CPT}_SYNC]}"; then +# echo " * <${HOSTNAME}-$$> {"$(my_date)"} synchronisation [${CPT}_SYNC]"; # fi; -# CPT_SYNC=$(($CPT_SYNC+1)); +# CPT_SYNC=$((${CPT}_SYNC+1)); # done; # test if this number is valid - if test $CPT -eq ${#COMMAND[*]}; then + if test ${CPT} -eq ${#COMMAND[*]}; then break; fi; # Test if command is empty ! - if test ! -z "${COMMAND[$CPT]}"; then - local CUR_DIR=$PWD; - - mkdir "Task_$CPT" &> /dev/null; - cd "Task_$CPT" &> /dev/null; - echo " * <$$> {"`date +"%F %T"`"} execute command [$CPT] : ${COMMAND[$CPT]}"; - echo "${COMMAND[$CPT]}" > "command"; - chmod +x "command"; - eval "${COMMAND[$CPT]}" &> "output"; - cd $CUR_DIR &> /dev/null; + if test ! -z "${COMMAND[${CPT}]}"; then + local CURREN_DIR=${PWD}; + cd ${WORK_DIR} &> /dev/null; + mkdir "Task_${CPT}" &> /dev/null; + cd "Task_${CPT}" &> /dev/null; + echo " * <${HOSTNAME}-$$> {"$(my_date)"} execute command [${CPT}] : ${COMMAND[${CPT}]}"; + echo "${COMMAND[${CPT}]}" > ${FILE_CMD}; +# chmod +x ${FILE_CMD}; + eval "${COMMAND[${CPT}]}" &> ${FILE_OUT}; + cd ${CURREN_DIR} &> /dev/null; fi; done; - echo " * <$$> {"`date +"%F %T"`"} is done"; + echo " * <${HOSTNAME}-$$> {"$(my_date)"} is done"; - lock $LOCK_CPU; - CPT=`cat $FILE_CPU`; # read the index - CPT=$(($CPT-1)); - echo "$CPT" > $FILE_CPU; # write the next index - unlock $LOCK_CPU; + lock ${LOCK_CPU}; + CPT=$(cat ${FILE_CPU}); # read the index + CPT=$((${CPT}-1)); + echo "${CPT}" > ${FILE_CPU}; # write the next index + unlock ${LOCK_CPU}; - if test $CPT -eq 0; then - echo " * <$$> {"`date +"%F %T"`"} All task is executed"; - rm $FILE_CPU; + if test ${CPT} -eq 0; then + echo " * <${HOSTNAME}-$$> {"$(my_date)"} All task is executed"; + rm ${FILE_CPU}; fi; } #-----[ Corps ]--------------------------------------------- -main $*; +execute ${*}; Index: trunk/IPs/systemC/processor/Morpheo/Script/execute_n.sh =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Script/execute_n.sh (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/Script/execute_n.sh (revision 112) @@ -5,18 +5,25 @@ #----------------------------------------------------------- -#-----[ variable ]------------------------------------------ -declare -a COMMAND; -declare -i NB_PROCESS; -declare -i CPT; -declare FILE_CMD; -declare FILE_CPT; -declare FILE_CPU; -declare ID="cpu-${HOSTNAME}-$$" +#-----[ global variable ]----------------------------------- -#-----[ usage ]--------------------------------------------- -function usage () +#-----[ nb_cpu ]-------------------------------------------- +function nb_cpu () { - echo "Usage : $0 file [ nb_process ]"; + local FILE_CPUINFO=/proc/cpuinfo; + if test ! -f ${FILE_CPUINFO}; then + echo "\"${FILE_CPUINFO}\" don't exist." + usage; + fi; + + #eval "${1}=`grep -c \"processor\" ${FILE_CPUINFO}`"; + grep -c "processor" ${FILE_CPUINFO}; +} + +#-----[ execute_n_usage ]----------------------------------- +function execute_n_usage () +{ + echo "Usage : ${0} word_dir file [ nb_process ]"; echo "Arguments : "; + echo " * work_dir : directory to execute command"; echo " * file : list of command"; echo " * nb_process : number of process (default (and maximum) is the number of processor)"; @@ -25,73 +32,72 @@ echo " * This script, for each command, create a directory : Task_X (X is the number of command), and execute the command in this directory."; echo " * Two file is generate : \"output\" is the output of the execution, and \"command\" is the command lunch."; - echo " * A command empty (no command on a line of file) is a synchronisation with all process" - echo " * Don't forgot the final end of line (else the last command is not executed"; +# echo " * A command empty (no command on a line of file) is a synchronisation with all process" + echo " * Don't forgot the final end of line (else the last command is not executed)"; echo ""; exit; } -#-----[ nb_cpu ]-------------------------------------------- -function nb_cpu () +#-----[ execute_n_test_usage ]------------------------------ +function execute_n_test_usage () { - local FILE_CPUINFO=/proc/cpuinfo; - if test ! -f $FILE_CPUINFO; then - echo "\"${FILE_CPUINFO}\" don't exist." - usage; + if test ${#} -ne 2 -a ${#} -ne 3; then + execute_n_usage; fi; - eval "$1=`grep -c \"processor\" ${FILE_CPUINFO}`"; -} - -#-----[ test_usage ]---------------------------------------- -function test_usage () -{ - if test $# -ne 1 -a $# -ne 2; then - usage; + if test ! -d ${1}; then + echo "Directory ${1} is invalid"; fi; - if test ! -f $1; then - echo "File \"$1\" don't exist"; - usage; + if test -z "${MORPHEO_SCRIPT}"; then + echo "Environment variable MORPHEO_SCRIPT is not set"; + distexe_usage; fi; - if test ! -s $1; then - echo "File \"$1\" is empty"; - usage; + if test ! -f ${2}; then + echo "File \"${2}\" don't exist"; + execute_n_usage; + fi; + + if test ! -s ${2}; then + echo "File \"${2}\" is empty"; + execute_n_usage; fi; } -#-----[ main ]---------------------------------------------- -function main () +#-----[ execute_n_main ]------------------------------------ +function execute_n () { - nb_cpu NB_PROCESS; + local -i NB_PROCESS=$(nb_cpu); + local -i CPT; + local WORK_DIR=${1}; + local FILE_CMD=${2}; + local FILE_CPT; + local FILE_CPU; + local ID="cpu-${HOSTNAME}-$$" - test_usage $*; + execute_n_test_usage ${*}; - if test $# -eq 2; then - if test $2 -lt $NB_PROCESS; then - NB_PROCESS=$2; + if test ${#} -eq 2; then + if test ${3} -lt ${NB_PROCESS}; then + NB_PROCESS=${3}; fi; fi; - FILE_CMD=$1; - FILE_CPT="$HOME/control-"`basename $1`; - FILE_CPU="$HOME/$ID"; + FILE_CPT="${WORK_DIR}/control-"$(basename ${FILE_CMD}); + FILE_CPU="${WORK_DIR}/${ID}"; - echo "<$0>" ; - echo " * Initialisation ...." ; - echo " - host name : $HOSTNAME" ; - echo " - number of process : $NB_PROCESS" ; + echo " * <${HOSTNAME}> ${NB_PROCESS} process"; local -i IT_NB_PROCESS=1; local -i PID=$$; - echo "$NB_PROCESS" > $FILE_CPU; + echo "${NB_PROCESS}" > ${FILE_CPU}; # create the same number of thread that processor - while test $IT_NB_PROCESS -le $NB_PROCESS; do - execute.sh $FILE_CMD $FILE_CPT $FILE_CPU & - IT_NB_PROCESS=$(($IT_NB_PROCESS+1)); + while test ${IT_NB_PROCESS} -le ${NB_PROCESS}; do + ${MORPHEO_SCRIPT}/execute.sh ${WORK_DIR} ${FILE_CMD} ${FILE_CPT} ${FILE_CPU} & + IT_NB_PROCESS=$((${IT_NB_PROCESS}+1)); - if test "$$" -ne $PID; then + if test "$$" -ne ${PID}; then break; fi; @@ -100,3 +106,3 @@ #-----[ Corps ]--------------------------------------------- -main $*; +execute_n ${*}; Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_allocation.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_allocation.cpp (revision 112) @@ -52,5 +52,5 @@ // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("icache_req",WEST,OUT,_("Request to instruction cache"),_nb_icache_port); + ALLOC1_INTERFACE_BEGIN("icache_req",WEST,OUT,_("Request to instruction cache"),_nb_icache_port); ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL ,behavioural::VAL); @@ -60,9 +60,11 @@ ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_address_t ,_size_icache_address ); ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_size_icache_type ); + + ALLOC1_INTERFACE_END(_nb_icache_port); } // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port); + ALLOC1_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port); ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL ,behavioural::VAL); @@ -71,14 +73,18 @@ ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Ticache_packet_t ,_size_icache_packet_id); ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_size_icache_error); - } - { - ALLOC2_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port,_icache_nb_instruction[it1]); + + ALLOC1_INTERFACE_END(_nb_icache_port); + } + { + ALLOC2_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port,_icache_nb_instruction[it1]); _ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_size_icache_instruction,_nb_icache_port,_icache_nb_instruction[it1]); + + ALLOC2_INTERFACE_END(_nb_icache_port,_icache_nb_instruction[it1]); } // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("dcache_req", OUT, NORTH, _("Request to data cache"),_nb_dcache_port); + ALLOC1_INTERFACE_BEGIN("dcache_req", OUT, NORTH, _("Request to data cache"),_nb_dcache_port); ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,behavioural::VAL); @@ -89,9 +95,11 @@ ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_size_dcache_data); ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_size_dcache_type); + + ALLOC1_INTERFACE_END(_nb_dcache_port); } // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("dcache_rsp", IN , NORTH, _("Respons from data cache"),_nb_dcache_port); + ALLOC1_INTERFACE_BEGIN("dcache_rsp", IN , NORTH, _("Respons from data cache"),_nb_dcache_port); ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,behavioural::VAL); @@ -101,11 +109,15 @@ ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_size_dcache_data); ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t ,_size_dcache_error); + + ALLOC1_INTERFACE_END(_nb_dcache_port); } // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("interrupt", IN , NORTH, _("Interruption line"),_nb_thread); + ALLOC1_INTERFACE_BEGIN("interrupt", IN , NORTH, _("Interruption line"),_nb_thread); ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE ,"enable",Tcontrol_t ,1); + + ALLOC1_INTERFACE_END(_nb_thread); } Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_configuration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_configuration.cpp (revision 111) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_configuration.cpp (revision 112) @@ -72,5 +72,5 @@ param->_nb_reg_free , param->_nb_rename_unit_bank , - param->_size_read_counter , +// param->_size_read_counter , param->_nb_read_bloc , Index: trunk/Makefile.flags =================================================================== --- trunk/Makefile.flags (revision 111) +++ trunk/Makefile.flags (revision 112) @@ -24,4 +24,5 @@ # -DPRINT_COLOR \ # -DPOSITION \ +# -DDEBUG_MEMORY_LEAK \ # Flags : Index: trunk/Makefile.tools =================================================================== --- trunk/Makefile.tools (revision 111) +++ trunk/Makefile.tools (revision 112) @@ -52,5 +52,5 @@ TOUCH = touch #VALGRIND = valgrind --tool=memcheck --leak-check=yes --show-reachable=yes --leak-resolution=high -VALGRIND = valgrind --tool=memcheck +VALGRIND = valgrind --tool=memcheck --leak-check=yes # Commands to generate all documents FIG2EPS = fig2dev -L eps @@ -104,4 +104,5 @@ #-----[ xilinx ]------------------------------------------- XILINX_ENV = . $(XILINX)/settings.sh +XILINX_CORELIB = $(XILINX)/vhdl/src/XilinxCoreLib/ #-----[ Modeltech ]---------------------------------------- @@ -111,9 +112,10 @@ MODELTECH_VCOM = $(MODELTECH_ENV); $(MODELTECH_BIN)/vcom MODELTECH_VSIM = $(MODELTECH_ENV); $(MODELTECH_BIN)/vsim -c -do "run -all; quit" +MODELTECH_VMAP = $(MODELTECH_ENV); $(MODELTECH_BIN)/vmap #-----[ or1k ]--------------------------------------------- OR1K_INCDIR = -I$(OR1K)/include -OR1K_LIBDIR = -L$(OR1K)/lib -OR1K_LIBNAME = -liberty +OR1K_LIBDIR = -L$(OR1K)/lib -L$(OR1K)/lib/gcc/or32-elf/3.4.4/ +OR1K_LIBNAME = -lgcc OR1K_BIN = $(OR1K)/bin @@ -121,5 +123,5 @@ NEWLIB_INCDIR = -I$(NEWLIB)/include NEWLIB_LIBDIR = -L$(NEWLIB)/lib -NEWLIB_LIBNAME = -lor32 -lc -lm -lor32 +NEWLIB_LIBNAME = -lor32 -lm -lc -lor32 #-----[ qt ]----------------------------------------------- Index: trunk/Platforms/Test/data_test/Test_000_066.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_066.cfg (revision 112) +++ trunk/Platforms/Test/data_test/Test_000_066.cfg (revision 112) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_066/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data_test/Test_000_067.cfg =================================================================== --- trunk/Platforms/Test/data_test/Test_000_067.cfg (revision 112) +++ trunk/Platforms/Test/data_test/Test_000_067.cfg (revision 112) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg +../../Softwares/Test/Test_067/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/src/test.cpp =================================================================== --- trunk/Platforms/Test/src/test.cpp (revision 111) +++ trunk/Platforms/Test/src/test.cpp (revision 112) @@ -521,6 +521,4 @@ DELETE1_SC_SIGNAL(INTERRUPT_ENABLE ,morpheo->_nb_thread); - delete morpheo; - delete environment; @@ -530,7 +528,9 @@ delete [] nb_lock ; delete [] ramlock_address; + for (uint32_t i=0;i +#include +#include +#include "dhry.h" +#include "dhry21.h" + +/* Global Variables: */ + +Rec_Pointer Ptr_Glob, + Next_Ptr_Glob; +int Int_Glob; +Boolean Bool_Glob; +char Ch_1_Glob, + Ch_2_Glob; +int Arr_1_Glob [50]; +int Arr_2_Glob [50] [50]; + +char Reg_Define[] = "Register option selected."; + +//extern char *malloc (); +//Enumeration Func_1 (); + /* + forward declaration necessary since Enumeration may not simply be int + */ + +#ifndef ROPT +#define REG + /* REG becomes defined as empty */ + /* i.e. no register variables */ +#else +#define REG register +#endif + + +/* variables for time measurement: */ + +#define Too_Small_Time 2 + /* Measurements should last at least 2 seconds */ + +DOUBLE Begin_Time, + End_Time, + User_Time; + +DOUBLE Microseconds, + Dhrystones_Per_Second, + Vax_Mips; + +/* end of variables for time measurement */ + +int dhry21 (unsigned int NUMBER_OF_RUNS) +/*****/ + + /* main program, corresponds to procedures */ + /* Main and Proc_0 in the Ada version */ +{ + DOUBLE dtime(); + + One_Fifty Int_1_Loc; + REG One_Fifty Int_2_Loc; + One_Fifty Int_3_Loc; + REG char Ch_Index; + Enumeration Enum_Loc; + Str_30 Str_1_Loc; + Str_30 Str_2_Loc; + REG int Run_Index; + REG int Number_Of_Runs; + + FILE *Ap; + + /* Initializations */ + + if ((Ap = fopen("dhry.res","a+")) == NULL) + { + printf("Can not open dhry.res\n\n"); + exit(1); + } + + Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); + Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); + + Ptr_Glob->Ptr_Comp = Next_Ptr_Glob; + Ptr_Glob->Discr = Ident_1; + Ptr_Glob->variant.var_1.Enum_Comp = Ident_3; + Ptr_Glob->variant.var_1.Int_Comp = 40; + strcpy (Ptr_Glob->variant.var_1.Str_Comp, + "DHRYSTONE PROGRAM, SOME STRING"); + strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING"); + + Arr_2_Glob [8][7] = 10; + /* Was missing in published program. Without this statement, */ + /* Arr_2_Glob [8][7] would have an undefined value. */ + /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ + /* overflow may occur for this array element. */ + + printf ("\n"); + printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); + printf ("\n"); + + /* + if (Reg) + { + printf ("Program compiled with 'register' attribute\n"); + printf ("\n"); + } + else + { + printf ("Program compiled without 'register' attribute\n"); + printf ("\n"); + } + */ + +//********************************************************************** +// printf ("Please give the number of runs through the benchmark: "); +// { +// int n; +// scanf ("%d", &n); +// Number_Of_Runs = n; +// } +// printf ("\n"); +//********************************************************************** + + Number_Of_Runs = NUMBER_OF_RUNS; + + printf ("Execution starts, %d runs through Dhrystone\n",Number_Of_Runs); + + /***************/ + /* Start timer */ + /***************/ + + Begin_Time = dtime(); + + for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index) + { + + Proc_5(); + Proc_4(); + /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */ + Int_1_Loc = 2; + Int_2_Loc = 3; + strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING"); + Enum_Loc = Ident_2; + Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc); + /* Bool_Glob == 1 */ + while (Int_1_Loc < Int_2_Loc) /* loop body executed once */ + { + Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc; + /* Int_3_Loc == 7 */ + Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc); + /* Int_3_Loc == 7 */ + Int_1_Loc += 1; + } /* while */ + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc); + /* Int_Glob == 5 */ + Proc_1 (Ptr_Glob); + for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index) + /* loop body executed twice */ + { + if (Enum_Loc == Func_1 (Ch_Index, 'C')) + /* then, not executed */ + { + Proc_6 (Ident_1, &Enum_Loc); + strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING"); + Int_2_Loc = Run_Index; + Int_Glob = Run_Index; + } + } + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Int_2_Loc = Int_2_Loc * Int_1_Loc; + Int_1_Loc = Int_2_Loc / Int_3_Loc; + Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; + /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */ + Proc_2 (&Int_1_Loc); + /* Int_1_Loc == 5 */ + + } /* loop "for Run_Index" */ + + /**************/ + /* Stop timer */ + /**************/ + + End_Time = dtime(); + + printf ("Execution ends\n"); + /******************************************************************* + printf ("\n"); + printf ("Final values of the variables used in the benchmark:\n"); + printf ("\n"); + printf ("Int_Glob: %d\n", Int_Glob); + printf (" should be: %d\n", 5); + printf ("Bool_Glob: %d\n", Bool_Glob); + printf (" should be: %d\n", 1); + printf ("Ch_1_Glob: %c\n", Ch_1_Glob); + printf (" should be: %c\n", 'A'); + printf ("Ch_2_Glob: %c\n", Ch_2_Glob); + printf (" should be: %c\n", 'B'); + printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]); + printf (" should be: %d\n", 7); + printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); + printf (" should be: Number_Of_Runs + 10\n"); + printf ("Ptr_Glob->\n"); + printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); + printf (" should be: (implementation-dependent)\n"); + printf (" Discr: %d\n", Ptr_Glob->Discr); + printf (" should be: %d\n", 0); + printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp); + printf (" should be: %d\n", 2); + printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); + printf (" should be: %d\n", 17); + printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); + printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + printf ("Next_Ptr_Glob->\n"); + printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); + printf (" should be: (implementation-dependent), same as above\n"); + printf (" Discr: %d\n", Next_Ptr_Glob->Discr); + printf (" should be: %d\n", 0); + printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp); + printf (" should be: %d\n", 1); + printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); + printf (" should be: %d\n", 18); + printf (" Str_Comp: %s\n", Next_Ptr_Glob->variant.var_1.Str_Comp); + printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + printf ("Int_1_Loc: %d\n", Int_1_Loc); + printf (" should be: %d\n", 5); + printf ("Int_2_Loc: %d\n", Int_2_Loc); + printf (" should be: %d\n", 13); + printf ("Int_3_Loc: %d\n", Int_3_Loc); + printf (" should be: %d\n", 7); + printf ("Enum_Loc: %d\n", Enum_Loc); + printf (" should be: %d\n", 1); + printf ("Str_1_Loc: %s\n", Str_1_Loc); + printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n"); + printf ("Str_2_Loc: %s\n", Str_2_Loc); + printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n"); + printf ("\n"); + ********************************************************************/ + + User_Time = End_Time - Begin_Time; + + if (User_Time < Too_Small_Time) + { + printf ("Measured time too small to obtain meaningful results : %f\n",User_Time); + printf ("Please increase number of runs\n"); + printf ("\n"); + } + else + { + Microseconds = User_Time * Mic_secs_Per_Second / (DOUBLE) Number_Of_Runs; + Dhrystones_Per_Second = (DOUBLE) Number_Of_Runs / User_Time; + Vax_Mips = Dhrystones_Per_Second / 1757.0; + +#ifdef ROPT + printf ("Register option selected? YES\n"); +#else + printf ("Register option selected? NO\n"); + strcpy(Reg_Define, "Register option not selected."); +#endif + + printf ("Microseconds for one run through Dhrystone : %.1lf \n",Microseconds); + printf ("Dhrystones per Second : %.1lf \n",Dhrystones_Per_Second); + printf ("VAX MIPS rating : %.3lf \n",Vax_Mips); + printf ("\n"); + + fprintf(Ap,"\n"); + fprintf(Ap,"Dhrystone Benchmark, Version 2.1 (Language: C)\n"); + fprintf(Ap,"%s\n",Reg_Define); + + fprintf(Ap,"Microseconds for one loop : %.1lf\n",Microseconds); + fprintf(Ap,"Dhrystones per second : %.1lf\n",Dhrystones_Per_Second); + fprintf(Ap,"VAX MIPS rating : %.3lf\n",Vax_Mips); + } + fclose(Ap); + return 0; + +} + +void +Proc_1 (Ptr_Val_Par) +/******************/ + +REG Rec_Pointer Ptr_Val_Par; + /* executed once */ +{ + REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; + /* == Ptr_Glob_Next */ + /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ + /* corresponds to "rename" in Ada, "with" in Pascal */ + + structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); + Ptr_Val_Par->variant.var_1.Int_Comp = 5; + Next_Record->variant.var_1.Int_Comp + = Ptr_Val_Par->variant.var_1.Int_Comp; + Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; + Proc_3 (&Next_Record->Ptr_Comp); + /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp + == Ptr_Glob->Ptr_Comp */ + if (Next_Record->Discr == Ident_1) + /* then, executed */ + { + Next_Record->variant.var_1.Int_Comp = 6; + Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, + &Next_Record->variant.var_1.Enum_Comp); + Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; + Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, + &Next_Record->variant.var_1.Int_Comp); + } + else /* not executed */ + structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); +} /* Proc_1 */ + +void +Proc_2 (Int_Par_Ref) +/******************/ + /* executed once */ + /* *Int_Par_Ref == 1, becomes 4 */ + +One_Fifty *Int_Par_Ref; +{ + One_Fifty Int_Loc; + Enumeration Enum_Loc; + + Int_Loc = *Int_Par_Ref + 10; + do /* executed once */ + if (Ch_1_Glob == 'A') + /* then, executed */ + { + Int_Loc -= 1; + *Int_Par_Ref = Int_Loc - Int_Glob; + Enum_Loc = Ident_1; + } /* if */ + while (Enum_Loc != Ident_1); /* true */ +} /* Proc_2 */ + +void +Proc_3 (Ptr_Ref_Par) +/******************/ + /* executed once */ + /* Ptr_Ref_Par becomes Ptr_Glob */ + +Rec_Pointer *Ptr_Ref_Par; + +{ + if (Ptr_Glob != Null) + /* then, executed */ + *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; + Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); +} /* Proc_3 */ + +void +Proc_4 () /* without parameters */ +/*******/ + /* executed once */ +{ + Boolean Bool_Loc; + + Bool_Loc = Ch_1_Glob == 'A'; + Bool_Glob = Bool_Loc | Bool_Glob; + Ch_2_Glob = 'B'; +} /* Proc_4 */ + +void +Proc_5 () /* without parameters */ +/*******/ + /* executed once */ +{ + Ch_1_Glob = 'A'; + Bool_Glob = false; +} /* Proc_5 */ + + + /* Procedure for the assignment of structures, */ + /* if the C compiler doesn't support this feature */ +#ifdef NOSTRUCTASSIGN +memcpy (d, s, l) +register char *d; +register char *s; +register int l; +{ + while (l--) *d++ = *s++; +} +#endif Index: trunk/Softwares/Dhrystone/src/c/dhry21b.c =================================================================== --- trunk/Softwares/Dhrystone/src/c/dhry21b.c (revision 112) +++ trunk/Softwares/Dhrystone/src/c/dhry21b.c (revision 112) @@ -0,0 +1,195 @@ +/* + ************************************************************************* + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry_2.c (part 3 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * + ************************************************************************* + */ + +#include "dhry.h" +#include "dhry21.h" +#include + +#ifndef REG +#define REG + /* REG becomes defined as empty */ + /* i.e. no register variables */ +#else +#define REG register +#endif + +int Int_Glob; +char Ch_1_Glob; + +void +Proc_6 (Enum_Val_Par, Enum_Ref_Par) +/*********************************/ + /* executed once */ + /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */ + +Enumeration Enum_Val_Par; +Enumeration *Enum_Ref_Par; +{ + *Enum_Ref_Par = Enum_Val_Par; + if (! Func_3 (Enum_Val_Par)) + /* then, not executed */ + *Enum_Ref_Par = Ident_4; + switch (Enum_Val_Par) + { + case Ident_1: + *Enum_Ref_Par = Ident_1; + break; + case Ident_2: + if (Int_Glob > 100) + /* then */ + *Enum_Ref_Par = Ident_1; + else *Enum_Ref_Par = Ident_4; + break; + case Ident_3: /* executed */ + *Enum_Ref_Par = Ident_2; + break; + case Ident_4: break; + case Ident_5: + *Enum_Ref_Par = Ident_3; + break; + } /* switch */ +} /* Proc_6 */ + +void +Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref) +/**********************************************/ + /* executed three times */ + /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */ + /* Int_Par_Ref becomes 7 */ + /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */ + /* Int_Par_Ref becomes 17 */ + /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */ + /* Int_Par_Ref becomes 18 */ +One_Fifty Int_1_Par_Val; +One_Fifty Int_2_Par_Val; +One_Fifty *Int_Par_Ref; +{ + One_Fifty Int_Loc; + + Int_Loc = Int_1_Par_Val + 2; + *Int_Par_Ref = Int_2_Par_Val + Int_Loc; +} /* Proc_7 */ + +void +Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val) +/*********************************************************************/ + /* executed once */ + /* Int_Par_Val_1 == 3 */ + /* Int_Par_Val_2 == 7 */ +Arr_1_Dim Arr_1_Par_Ref; +Arr_2_Dim Arr_2_Par_Ref; +int Int_1_Par_Val; +int Int_2_Par_Val; +{ + REG One_Fifty Int_Index; + REG One_Fifty Int_Loc; + + Int_Loc = Int_1_Par_Val + 5; + Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val; + Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc]; + Arr_1_Par_Ref [Int_Loc+30] = Int_Loc; + for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index) + Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc; + Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1; + Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc]; + Int_Glob = 5; +} /* Proc_8 */ + + +Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val) +/*************************************************/ + /* executed three times */ + /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */ + /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */ + /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */ + +Capital_Letter Ch_1_Par_Val; +Capital_Letter Ch_2_Par_Val; +{ + Capital_Letter Ch_1_Loc; + Capital_Letter Ch_2_Loc; + + Ch_1_Loc = Ch_1_Par_Val; + Ch_2_Loc = Ch_1_Loc; + if (Ch_2_Loc != Ch_2_Par_Val) + /* then, executed */ + return (Ident_1); + else /* not executed */ + { + Ch_1_Glob = Ch_1_Loc; + return (Ident_2); + } +} /* Func_1 */ + + +Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref) +/*************************************************/ + /* executed once */ + /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */ + /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */ + +Str_30 Str_1_Par_Ref; +Str_30 Str_2_Par_Ref; +{ + REG One_Thirty Int_Loc; + Capital_Letter Ch_Loc ; + + Int_Loc = 2; + while (Int_Loc <= 2) /* loop body executed once */ + if (Func_1 (Str_1_Par_Ref[Int_Loc], + Str_2_Par_Ref[Int_Loc+1]) == Ident_1) + /* then, executed */ + { + Ch_Loc = 'A'; + Int_Loc += 1; + } /* if, while */ + if (Ch_Loc >= 'W' && Ch_Loc < 'Z') + /* then, not executed */ + Int_Loc = 7; + if (Ch_Loc == 'R') + /* then, not executed */ + return (true); + else /* executed */ + { + if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0) + /* then, not executed */ + { + Int_Loc += 7; + Int_Glob = Int_Loc; + return (true); + } + else /* executed */ + return (false); + } /* if Ch_Loc */ +} /* Func_2 */ + + +Boolean Func_3 (Enum_Par_Val) +/***************************/ + /* executed once */ + /* Enum_Par_Val == Ident_3 */ +Enumeration Enum_Par_Val; +{ + Enumeration Enum_Loc; + + Enum_Loc = Enum_Par_Val; + if (Enum_Loc == Ident_3) + /* then, executed */ + return (true); + else /* not executed */ + return (false); +} /* Func_3 */ Index: trunk/Softwares/Dhrystone/src/c/dtime.c =================================================================== --- trunk/Softwares/Dhrystone/src/c/dtime.c (revision 112) +++ trunk/Softwares/Dhrystone/src/c/dtime.c (revision 112) @@ -0,0 +1,497 @@ +/*****************************************************/ +/* Various timer routines. */ +/* Al Aburto, aburto@nosc.mil, 18 Feb 1997 */ +/* */ +/* t = dtime() outputs the current time in seconds. */ +/* Use CAUTION as some of these routines will mess */ +/* up when timing across the hour mark!!! */ +/* */ +/* For timing I use the 'user' time whenever */ +/* possible. Using 'user+sys' time is a separate */ +/* issue. */ +/* */ +/* Example Usage: */ +/* [timer options added here] */ +/* main() */ +/* { */ +/* double starttime,benchtime,dtime(); */ +/* */ +/* starttime = dtime(); */ +/* [routine to time] */ +/* benchtime = dtime() - starttime; */ +/* } */ +/* */ +/* [timer code below added here] */ +/*****************************************************/ + +/***************************************************************/ +/* Timer options. You MUST uncomment one of the options below */ +/* or compile, for example, with the '-DUNIX' option. */ +/***************************************************************/ +/* #define Amiga */ +/* #define UNIX */ +/* #define UNIX_Old */ +/* #define VMS */ +/* #define BORLAND_C */ +/* #define MSC */ +/* #define MAC */ +/* #define IPSC */ +/* #define FORTRAN_SEC */ +/* #define GTODay */ +/* #define CTimer */ +/* #define UXPM */ +/* #define MAC_TMgr */ +/* #define PARIX */ +/* #define POSIX */ +/* #define WIN32 */ +/* #define POSIX1 */ +/***********************/ + +/*********************************/ +/* Timer code. */ +/*********************************/ + +/***************************************************/ +/* Morpheo dtime(). */ +/***************************************************/ +#ifdef Morpheo + +#include +/* #include */ +#include "dhry.h" +/* #include "service_clock.h" */ + +extern unsigned int my_times(); + +#ifndef MHZ +#define MHZ (1000000) +#endif //!MHZ + +#ifndef FRQ +#define FRQ (1*MHZ) +#endif //!FRQ + +#ifndef DOUBLE +#define double +#endif + +DOUBLE dtime() +{ + DOUBLE q; + +/* q = (DOUBLE)(my_times())/(DOUBLE)FRQ; */ + q = (DOUBLE)(my_times()); + + return (q); +} +#endif + +/*******************/ +/* Amiga dtime() */ +/*******************/ +#ifdef Amiga +#include +#define HZ 50 + +double dtime() +{ + double q; + + struct tt + { + long days; + long minutes; + long ticks; + } tt; + + DateStamp(&tt); + + q = ((double)(tt.ticks + (tt.minutes * 60L * 50L))) / (double)HZ; + + return q; +} +#endif + +/*****************************************************/ +/* UNIX dtime(). This is the preferred UNIX timer. */ +/* Provided by: Markku Kolkka, mk59200@cc.tut.fi */ +/* HP-UX Addition by: Bo Thide', bt@irfu.se */ +/*****************************************************/ +#ifdef UNIX +#include +#include + +#ifdef hpux +#include +#define getrusage(a,b) syscall(SYS_getrusage,a,b) +#endif + +struct rusage rusage; + +double dtime() +{ + double q; + getrusage(RUSAGE_SELF,&rusage); + q = (double)(rusage.ru_utime.tv_sec); + q = q + (double)(rusage.ru_utime.tv_usec) * 1.0e-06; + return q; +} +#endif + +/***************************************************/ +/* UNIX_Old dtime(). This is the old UNIX timer. */ +/* Make sure HZ is properly defined in param.h !! */ +/***************************************************/ +#ifdef UNIX_Old +#include +#include +#include + +#ifndef HZ +#define HZ 60 +#endif + +struct tms tms; + +double dtime() +{ + double q; + + times(&tms); + + q = (double)(tms.tms_utime) / (double)HZ; + + return q; +} +#endif + +/*********************************************************/ +/* VMS dtime() for VMS systems. */ +/* Provided by: RAMO@uvphys.phys.UVic.CA */ +/* Some people have run into problems with this timer. */ +/*********************************************************/ +#ifdef VMS +#include time + +#ifndef HZ +#define HZ 100 +#endif + +struct tbuffer_t + { + int proc_user_time; + int proc_system_time; + int child_user_time; + int child_system_time; + }; + +struct tbuffer_t tms; + +double dtime() +{ + double q; + + times(&tms); + + q = (double)(tms.proc_user_time) / (double)HZ; + + return q; +} +#endif + +/******************************/ +/* BORLAND C dtime() for DOS */ +/******************************/ +#ifdef BORLAND_C +#include +#include +#include + +#define HZ 100 +struct time tnow; + +double dtime() +{ + double q; + + gettime(&tnow); + + q = 60.0 * (double)(tnow.ti_min); + q = q + (double)(tnow.ti_sec); + q = q + (double)(tnow.ti_hund)/(double)HZ; + + return q; +} +#endif + +/**************************************/ +/* Microsoft C (MSC) dtime() for DOS */ +/**************************************/ +#ifdef MSC +#include +#include + +#define HZ CLOCKS_PER_SEC +clock_t tnow; + +double dtime() +{ + double q; + + tnow = clock(); + + q = (double)tnow / (double)HZ; + + return q; +} +#endif + +/*************************************/ +/* Macintosh (MAC) Think C dtime() */ +/*************************************/ +#ifdef MAC +#include + +#define HZ 60 + +double dtime() +{ + double q; + + q = (double)clock() / (double)HZ; + + return q; +} +#endif + +/************************************************************/ +/* iPSC/860 (IPSC) dtime() for i860. */ +/* Provided by: Dan Yergeau, yergeau@gloworm.Stanford.EDU */ +/************************************************************/ +#ifdef IPSC +extern double dclock(); + +double dtime() +{ + double q; + + q = dclock(); + + return q; +} +#endif + +/**************************************************/ +/* FORTRAN dtime() for Cray type systems. */ +/* This is the preferred timer for Cray systems. */ +/**************************************************/ +#ifdef FORTRAN_SEC + +fortran double second(); + +double dtime() +{ + double q; + + second(&q); + + return q; +} +#endif + +/***********************************************************/ +/* UNICOS C dtime() for Cray UNICOS systems. Don't use */ +/* unless absolutely necessary as returned time includes */ +/* 'user+system' time. Provided by: R. Mike Dority, */ +/* dority@craysea.cray.com */ +/***********************************************************/ +#ifdef CTimer +#include + +double dtime() +{ + double q; + clock_t clock(void); + + q = (double)clock() / (double)CLOCKS_PER_SEC; + + return q; +} +#endif + +/********************************************/ +/* Another UNIX timer using gettimeofday(). */ +/* However, getrusage() is preferred. */ +/********************************************/ +#ifdef GTODay +#include + +struct timeval tnow; + +double dtime() +{ + double q; + + gettimeofday(&tnow,NULL); + q = (double)tnow.tv_sec + (double)tnow.tv_usec * 1.0e-6; + + return q; +} +#endif + +/*****************************************************/ +/* Fujitsu UXP/M timer. */ +/* Provided by: Mathew Lim, ANUSF, M.Lim@anu.edu.au */ +/*****************************************************/ +#ifdef UXPM +#include +#include +struct tmsu rusage; + +double dtime() +{ + double q; + + timesu(&rusage); + + q = (double)(rusage.tms_utime) * 1.0e-06; + + return q; +} +#endif + +/**********************************************/ +/* Macintosh (MAC_TMgr) Think C dtime() */ +/* requires Think C Language Extensions or */ +/* #include in the prefix */ +/* provided by Francis H Schiffer 3rd (fhs) */ +/* skipschiffer@genie.geis.com */ +/**********************************************/ +#ifdef MAC_TMgr +#include +#include + +static TMTask mgrTimer; +static Boolean mgrInited = false; +static double mgrClock; + +#define RMV_TIMER RmvTime( (QElemPtr)&mgrTimer ) +#define MAX_TIME 1800000000L +/* MAX_TIME limits time between calls to */ +/* dtime( ) to no more than 30 minutes */ +/* this limitation could be removed by */ +/* creating a completion routine to sum */ +/* 30 minute segments (fhs 1994 feb 9) */ + +static void Remove_timer( ) +{ + RMV_TIMER; + mgrInited = false; +} + +double dtime( ) +{ + if( mgrInited ) { + RMV_TIMER; + mgrClock += (MAX_TIME + mgrTimer.tmCount)*1.0e-6; + } else { + if( _atexit( &Remove_timer ) == 0 ) mgrInited = true; + mgrClock = 0.0; + } + + if ( mgrInited ) + { + mgrTimer.tmAddr = NULL; + mgrTimer.tmCount = 0; + mgrTimer.tmWakeUp = 0; + mgrTimer.tmReserved = 0; + InsTime( (QElemPtr)&mgrTimer ); + PrimeTime( (QElemPtr)&mgrTimer, -MAX_TIME ); + } + return( mgrClock ); +} +#endif + +/***********************************************************/ +/* Parsytec GCel timer. */ +/* Provided by: Georg Wambach, gw@informatik.uni-koeln.de */ +/***********************************************************/ +#ifdef PARIX +#include + +double dtime() +{ + double q; + + q = (double) (TimeNowHigh()) / (double) CLK_TCK_HIGH; + + return q; +} +#endif + +/************************************************/ +/* Sun Solaris POSIX dtime() routine */ +/* Provided by: Case Larsen, CTLarsen.lbl.gov */ +/************************************************/ +#ifdef POSIX +#include +#include +#include + +#ifdef __hpux +#include +#endif + +struct rusage rusage; + +double dtime() +{ + double q; + + getrusage(RUSAGE_SELF,&rusage); + + q = (double)(rusage.ru_utime.tv_sec); + q = q + (double)(rusage.ru_utime.tv_nsec) * 1.0e-09; + + return q; +} +#endif + + +/****************************************************/ +/* Windows NT (32 bit) dtime() routine */ +/* Provided by: Piers Haken, piersh@microsoft.com */ +/****************************************************/ +#ifdef WIN32 +#include + +double dtime(void) +{ + double q; + + q = (double)GetTickCount() * 1.0e-03; + + return q; +} +#endif + +/*****************************************************/ +/* Time according to POSIX.1 - */ +/* Ref: "POSIX Programmer's Guide" O'Reilly & Assoc.*/ +/*****************************************************/ +#ifdef POSIX1 +#define _POSIX_SOURCE 1 +#include +#include +#include + +struct tms tms; + +double dtime() +{ + double q; + times(&tms); + q = (double)tms.tms_utime / (double)CLK_TCK; + return q; +} +#endif Index: trunk/Softwares/Dhrystone/src/c/main.c =================================================================== --- trunk/Softwares/Dhrystone/src/c/main.c (revision 112) +++ trunk/Softwares/Dhrystone/src/c/main.c (revision 112) @@ -0,0 +1,22 @@ +// $Id$ + +//=====[ main ]================================================================= +/* + * All thread execute this routine + * Initialize the thread and attribute a Workload at each thread + */ + +#include +#include "dhry21.h" + +int main() +{ + printf("cycle : %f\n",dtime()); + +/* dhry21(100); */ + + + exit (0); + + while (1); +} Index: trunk/Softwares/Dhrystone/src/include/dhry.h =================================================================== --- trunk/Softwares/Dhrystone/src/include/dhry.h (revision 112) +++ trunk/Softwares/Dhrystone/src/include/dhry.h (revision 112) @@ -0,0 +1,405 @@ +/* + ************************************************************************* + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry.h (part 1 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * Siemens Nixdorf Inf. Syst. + * STM OS 32 + * Otto-Hahn-Ring 6 + * W-8000 Muenchen 83 + * Germany + * Phone: [+49]-89-636-42436 + * (8-17 Central European Time) + * UUCP: weicker@ztivax.uucp@unido.uucp + * Internet: weicker@ztivax.siemens.com + * + * Original Version (in Ada) published in + * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), + * pp. 1013 - 1030, together with the statistics + * on which the distribution of statements etc. is based. + * + * In this C version, the following C library functions are + * used: + * - strcpy, strcmp (inside the measurement loop) + * - printf, scanf (outside the measurement loop) + * + * Collection of Results: + * Reinhold Weicker (address see above) and + * + * Rick Richardson + * PC Research. Inc. + * 94 Apple Orchard Drive + * Tinton Falls, NJ 07724 + * Phone: (201) 834-1378 (9-17 EST) + * UUCP: ...!uunet!pcrat!rick + * + * Please send results to Rick Richardson and/or Reinhold Weicker. + * Complete information should be given on hardware and software + * used. Hardware information includes: Machine type, CPU, type and + * size of caches; for microprocessors: clock frequency, memory speed + * (number of wait states). Software information includes: Compiler + * (and runtime library) manufacturer and version, compilation + * switches, OS version. The Operating System version may give an + * indication about the compiler; Dhrystone itself performs no OS + * calls in the measurement loop. + * + * The complete output generated by the program should be mailed + * such that at least some checks for correctness can be made. + * + ************************************************************************* + * + * History: This version C/2.1 has been made for two reasons: + * + * 1) There is an obvious need for a common C version of + * Dhrystone, since C is at present the most popular system + * programming language for the class of processors + * (microcomputers, minicomputers) where Dhrystone is used + * most. There should be, as far as possible, only one C + * version of Dhrystone such that results can be compared + * without restrictions. In the past, the C versions + * distributed by Rick Richardson (Version 1.1) and by + * Reinhold Weicker had small (though not significant) + * differences. + * + * 2) As far as it is possible without changes to the + * Dhrystone statistics, optimizing compilers should be + * prevented from removing significant statements. + * + * This C version has been developed in cooperation with + * Rick Richardson (Tinton Falls, NJ), it incorporates many + * ideas from the "Version 1.1" distributed previously by + * him over the UNIX network Usenet. + * I also thank Chaim Benedelac (National Semiconductor), + * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), + * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) + * for their help with comments on earlier versions of the + * benchmark. + * + * Changes: In the initialization part, this version follows mostly + * Rick Richardson's version distributed via Usenet, not the + * version distributed earlier via floppy disk by Reinhold + * Weicker. As a concession to older compilers, names have + * been made unique within the first 8 characters. Inside the + * measurement loop, this version follows the version + * previously distributed by Reinhold Weicker. + * + * At several places in the benchmark, code has been added, + * but within the measurement loop only in branches that + * are not executed. The intention is that optimizing + * compilers should be prevented from moving code out of the + * measurement loop, or from removing code altogether. Since + * the statements that are executed within the measurement + * loop have NOT been changed, the numbers defining the + * "Dhrystone distribution" (distribution of statements, + * operand types and locality) still hold. Except for + * sophisticated optimizing compilers, execution times for + * this version should be the same as for previous versions. + * + * Since it has proven difficult to subtract the time for the + * measurement loop overhead in a correct way, the loop check + * has been made a part of the benchmark. This does have + * an impact - though a very minor one - on the distribution + * statistics which have been updated for this version. + * + * All changes within the measurement loop are described + * and discussed in the companion paper "Rationale for + * Dhrystone version 2". + * + * Because of the self-imposed limitation that the order and + * distribution of the executed statements should not be + * changed, there are still cases where optimizing compilers + * may not generate code for some statements. To a certain + * degree, this is unavoidable for small synthetic + * benchmarks. Users of the benchmark are advised to check + * code listings whether code is generated for all statements + * of Dhrystone. + * + * Version 2.1 is identical to version 2.0 distributed via + * the UNIX network Usenet in March 1988 except that it + * corrects some minor deficiencies that were found by users + * of version 2.0. The only change within the measurement + * loop is that a non-executed "else" part was added to the + * "if" statement in Func_3, and a non-executed "else" part + * removed from Proc_3. + * + ************************************************************************* + * + * Defines: The following "Defines" are possible: + * -DROPT (default: Not defined) + * As an approximation to what an average C + * programmer might do, the "register" storage class + * is applied (if enabled by -DROPT) + * - for local variables, if they are used + * (dynamically) five or more times + * - for parameters if they are used (dynamically) + * six or more times + * Note that an optimal "register" strategy is + * compiler-dependent, and that "register" + * declarations do not necessarily lead to faster + * execution. + * -DNOSTRUCTASSIGN (default: Not defined) + * Define if the C compiler does not support + * assignment of structures. + * -DNOENUMS (default: Not defined) + * Define if the C compiler does not support + * enumeration types. + * + ************************************************************************* + * + * Compilation model and measurement (IMPORTANT): + * + * This C version of Dhrystone consists of three files: + * - dhry.h (this file, containing global definitions and comments) + * - dhry_1.c (containing the code corresponding to Ada package Pack_1) + * - dhry_2.c (containing the code corresponding to Ada package Pack_2) + * + * The following "ground rules" apply for measurements: + * - Separate compilation + * - No procedure merging + * - Otherwise, compiler optimizations are allowed but should be + * indicated + * - Default results are those without register declarations + * See the companion paper "Rationale for Dhrystone Version 2" for a more + * detailed discussion of these ground rules. + * + * For 16-Bit processors (e.g. 80186, 80286), times for all compilation + * models ("small", "medium", "large" etc.) should be given if possible, + * together with a definition of these models for the compiler system + * used. + * + ************************************************************************* + * + * Dhrystone (C version) statistics: + * + * [Comment from the first distribution, updated for version 2. + * Note that because of language differences, the numbers are slightly + * different from the Ada version.] + * + * The following program contains statements of a high level programming + * language (here: C) in a distribution considered representative: + * + * assignments 52 (51.0 %) + * control statements 33 (32.4 %) + * procedure, function calls 17 (16.7 %) + * + * 103 statements are dynamically executed. The program is balanced with + * respect to the three aspects: + * + * - statement type + * - operand type + * - operand locality + * operand global, local, parameter, or constant. + * + * The combination of these three aspects is balanced only approximately. + * + * 1. Statement Type: + * ----------------- number + * + * V1 = V2 9 + * (incl. V1 = F(..) + * V = Constant 12 + * Assignment, 7 + * with array element + * Assignment, 6 + * with record component + * -- + * 34 34 + * + * X = Y +|-|"&&"|"|" Z 5 + * X = Y +|-|"==" Constant 6 + * X = X +|- 1 3 + * X = Y *|/ Z 2 + * X = Expression, 1 + * two operators + * X = Expression, 1 + * three operators + * -- + * 18 18 + * + * if .... 14 + * with "else" 7 + * without "else" 7 + * executed 3 + * not executed 4 + * for ... 7 | counted every time + * while ... 4 | the loop condition + * do ... while 1 | is evaluated + * switch ... 1 + * break 1 + * declaration with 1 + * initialization + * -- + * 34 34 + * + * P (...) procedure call 11 + * user procedure 10 + * library procedure 1 + * X = F (...) + * function call 6 + * user function 5 + * library function 1 + * -- + * 17 17 + * --- + * 103 + * + * The average number of parameters in procedure or function calls + * is 1.82 (not counting the function values as implicit parameters). + * + * + * 2. Operators + * ------------ + * number approximate + * percentage + * + * Arithmetic 32 50.8 + * + * + 21 33.3 + * - 7 11.1 + * * 3 4.8 + * / (int div) 1 1.6 + * + * Comparison 27 42.8 + * + * == 9 14.3 + * /= 4 6.3 + * > 1 1.6 + * < 3 4.8 + * >= 1 1.6 + * <= 9 14.3 + * + * Logic 4 6.3 + * + * && (AND-THEN) 1 1.6 + * | (OR) 1 1.6 + * ! (NOT) 2 3.2 + * + * -- ----- + * 63 100.1 + * + * + * 3. Operand Type (counted once per operand reference): + * --------------- + * number approximate + * percentage + * + * Integer 175 72.3 % + * Character 45 18.6 % + * Pointer 12 5.0 % + * String30 6 2.5 % + * Array 2 0.8 % + * Record 2 0.8 % + * --- ------- + * 242 100.0 % + * + * When there is an access path leading to the final operand (e.g. a + * record component), only the final data type on the access path is + * counted. + * + * + * 4. Operand Locality: + * ------------------- + * number approximate + * percentage + * + * local variable 114 47.1 % + * global variable 22 9.1 % + * parameter 45 18.6 % + * value 23 9.5 % + * reference 22 9.1 % + * function result 6 2.5 % + * constant 55 22.7 % + * --- ------- + * 242 100.0 % + * + * + * The program does not compute anything meaningful, but it is + * syntactically and semantically correct. All variables have a value + * assigned to them before they are used as a source operand. + * + * There has been no explicit effort to account for the effects of a + * cache, or to balance the use of long or short displacements for code + * or data. + * + ************************************************************************* + */ + +#ifndef DHRY_H +#define DHRY_H + +/* Compiler and system dependent definitions: */ + +#define DOUBLE float +#define Mic_secs_Per_Second 1000000.0 + +DOUBLE dtime (); + + /* Berkeley UNIX C returns process times in seconds/HZ */ + +#ifdef NOSTRUCTASSIGN +#define structassign(d, s) memcpy(&(d), &(s), sizeof(d)) +#else +#define structassign(d, s) d = s +#endif + +#ifdef NOENUM +#define Ident_1 0 +#define Ident_2 1 +#define Ident_3 2 +#define Ident_4 3 +#define Ident_5 4 + typedef int Enumeration; +#else + typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} + Enumeration; +#endif + /* for boolean and enumeration types in Ada, Pascal */ + +/* General definitions: */ + +#include + /* for strcpy, strcmp */ + +#define Null 0 + /* Value of a Null pointer */ +#define true 1 +#define false 0 + +typedef int One_Thirty; +typedef int One_Fifty; +typedef char Capital_Letter; +typedef int Boolean; +typedef char Str_30 [31]; +typedef int Arr_1_Dim [50]; +typedef int Arr_2_Dim [50] [50]; + +typedef struct record + { + struct record *Ptr_Comp; + Enumeration Discr; + union { + struct { + Enumeration Enum_Comp; + int Int_Comp; + char Str_Comp [31]; + } var_1; + struct { + Enumeration E_Comp_2; + char Str_2_Comp [31]; + } var_2; + struct { + char Ch_1_Comp; + char Ch_2_Comp; + } var_3; + } variant; + } Rec_Type, *Rec_Pointer; + +#endif //!DHRY_H Index: trunk/Softwares/Dhrystone/src/include/dhry21.h =================================================================== --- trunk/Softwares/Dhrystone/src/include/dhry21.h (revision 112) +++ trunk/Softwares/Dhrystone/src/include/dhry21.h (revision 112) @@ -0,0 +1,20 @@ +#ifndef DHRY21_H +#define DHRY21_H + +#include "dhry.h" + +int dhry21 (unsigned int); + +void Proc_1 (Rec_Pointer); +void Proc_2 (One_Fifty *); +void Proc_3 (Rec_Pointer *); +void Proc_4 (); +void Proc_5 (); +void Proc_6 (Enumeration, Enumeration*); +void Proc_7 (One_Fifty,One_Fifty,One_Fifty*); +void Proc_8 (Arr_1_Dim,Arr_2_Dim,int,int); +Enumeration Func_1 (Capital_Letter,Capital_Letter); +Boolean Func_2 (Str_30,Str_30); +Boolean Func_3 (Enumeration); + +#endif Index: trunk/Softwares/Makefile =================================================================== --- trunk/Softwares/Makefile (revision 111) +++ trunk/Softwares/Makefile (revision 112) @@ -16,4 +16,5 @@ SOFT = Minimal_soft \ + Dhrystone \ Test/* Index: trunk/Softwares/Makefile.Software =================================================================== --- trunk/Softwares/Makefile.Software (revision 111) +++ trunk/Softwares/Makefile.Software (revision 112) @@ -32,4 +32,5 @@ #-----[ To the compilation ]------------------------------------------------------ OPTIMIZE = -O2 -std=c99 -fomit-frame-pointer -fdelayed-branch -mror -mcmov -msext -mhard-mul -msoft-div -msoft-float + #Option : # -fomit-frame-pointer : n'utilise pas le pointeur de frame @@ -54,8 +55,8 @@ # Tools's option -OR32_CC_OPT = -Wall $(INCDIR) $(OPTIMIZE) -Wlong-long +OR32_CC_OPT = -Wall $(INCDIR) $(OPTIMIZE) -Wlong-long -DMorpheo # -DHAVE_LIBC OR32_AS_OPT = -OR32_LD_OPT = -T$(DIR_LDSCRIPT)/or32.ld $(LIBDIR) $(LIBNAME) +OR32_LD_OPT = -T$(DIR_LDSCRIPT)/or32.ld $(LIBDIR) $(LIBNAME) $(OR1K_LIBDIR) $(OR1K_LIBNAME) OR32_OBJDUMP_OPT = -D OR32_NM_OPT = -n @@ -81,6 +82,7 @@ $(ECHO) "List symbols : $*.x.nm"; \ $(OR32_NM) $(OR32_NM_OPT) $^ > $@.nm; \ - $(ECHO) "Display info : $*.x.txt"; \ - $(OR32_OBJDUMP) $(OR32_OBJDUMP_OPT) $@ > $@.txt; + $(ECHO) "Display info : $*.x.txt"; \ + $(OR32_OBJDUMP) $(OR32_OBJDUMP_OPT) $@ > $@.txt;\ + echo $($(GREP) "l.jal 0" $@.txt); $(DIR_OBJ)/%.o : %.s Index: trunk/Softwares/Test/Test_015/src/sys/crt0.s =================================================================== --- trunk/Softwares/Test/Test_015/src/sys/crt0.s (revision 111) +++ trunk/Softwares/Test/Test_015/src/sys/crt0.s (revision 112) @@ -38,5 +38,5 @@ l.movhi r2, hi(0x00000010) /* count max */ - l.ori r2, r2, lo(0x00000010) + l.ori r2, r2, lo(0x00000100) /**********/ Index: trunk/Softwares/Test/Test_016/src/sys/crt0.s =================================================================== --- trunk/Softwares/Test/Test_016/src/sys/crt0.s (revision 111) +++ trunk/Softwares/Test/Test_016/src/sys/crt0.s (revision 112) @@ -38,5 +38,5 @@ l.movhi r2, hi(0x00000010) /* count max */ - l.ori r2, r2, lo(0x00000010) + l.ori r2, r2, lo(0x00000100) /**********/ Index: trunk/Softwares/Test/Test_066/src/c/main.c =================================================================== --- trunk/Softwares/Test/Test_066/src/c/main.c (revision 111) +++ trunk/Softwares/Test/Test_066/src/c/main.c (revision 112) @@ -14,10 +14,8 @@ int main() { -//fprintf(stdout,"Message de Bienvenue !!!\n"); +/* printf("Hello World !!!\n"); */ - printf("Hello World !!!\n"); - - for (int i=0; i<10; ++i) - printf("i : %d",i); + for (int i=0; i<20; ++i) + printf("i : %d\n",i); exit (0); Index: trunk/Softwares/Test/Test_067/Makefile =================================================================== --- trunk/Softwares/Test/Test_067/Makefile (revision 112) +++ trunk/Softwares/Test/Test_067/Makefile (revision 112) @@ -0,0 +1,31 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + + +# common definition +DIR_SOFT = ../.. + +DIR_SRC = ./src +DIR_C = $(DIR_SRC)/c +DIR_ASM = $(DIR_SRC)/asm +DIR_SYS = $(DIR_SRC)/sys +DIR_INC = $(DIR_SRC)/include +DIR_LDSCRIPT = $(NEWLIB)/lib/ + +INCDIR = $(NEWLIB_INCDIR) -I$(DIR_INC) +LIBDIR = $(NEWLIB_LIBDIR) +LIBNAME = $(NEWLIB_LIBNAME) + +#-----[ Files ]------------------------------------------------------------------- +OBJECTS = $(NEWLIB)/lib/*.o \ + $(patsubst $(DIR_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_ASM)/*.s)) \ + $(patsubst $(DIR_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SYS)/*.s)) \ + $(patsubst $(DIR_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_C)/*.c)) + +include $(DIR_SOFT)/Makefile.Software + Index: trunk/Softwares/Test/Test_067/src/c/main.c =================================================================== --- trunk/Softwares/Test/Test_067/src/c/main.c (revision 112) +++ trunk/Softwares/Test/Test_067/src/c/main.c (revision 112) @@ -0,0 +1,29 @@ +// $Id$ + +//=====[ main ]================================================================= +/* + * All thread execute this routine + * Initialize the thread and attribute a Workload at each thread + */ + +#include +#include +#include +#include + +int main() +{ + FILE * file = fopen("Test_067.txt","w"); + + if (file == NULL) + exit (1); + + fprintf(file,"Hello World !!!\n"); + + if (fclose (file) != 0) + exit (2); + + exit (0); + + while (1); +}