Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp	(revision 114)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp	(revision 115)
@@ -20,15 +20,16 @@
 #undef  FUNCTION
 #define FUNCTION "Write_queue::Parameters"
-  Parameters::Parameters (uint32_t size_queue         ,
-			  uint32_t nb_context         ,
-			  uint32_t nb_front_end       ,
-			  uint32_t nb_ooo_engine      ,
-			  uint32_t nb_packet          ,
-			  uint32_t size_general_data  ,
-			  uint32_t nb_general_register,
-			  uint32_t size_special_data  ,
-			  uint32_t nb_special_register,
-			  uint32_t nb_bypass_write    ,
-                          bool     is_toplevel):
+  Parameters::Parameters (uint32_t              size_queue         ,
+			  uint32_t              nb_context         ,
+			  uint32_t              nb_front_end       ,
+			  uint32_t              nb_ooo_engine      ,
+			  uint32_t              nb_packet          ,
+			  uint32_t              size_general_data  ,
+			  uint32_t              nb_general_register,
+			  uint32_t              size_special_data  ,
+			  uint32_t              nb_special_register,
+			  uint32_t              nb_bypass_write    ,
+			  Twrite_queue_scheme_t queue_scheme       ,
+			  bool                  is_toplevel        ):
     behavioural::Parameters ("Write_queue")
   {
@@ -43,4 +44,5 @@
     _nb_special_register     = nb_special_register;
     _nb_bypass_write         = nb_bypass_write    ;
+    _queue_scheme            = queue_scheme       ;
 
     _nb_gpr_write            = 1;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters_print.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters_print.cpp	(revision 114)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters_print.cpp	(revision 115)
@@ -38,4 +38,5 @@
     xml.singleton_begin("nb_special_register"); xml.attribut("value",toString(_nb_special_register)); xml.singleton_end();
     xml.singleton_begin("nb_bypass_write    "); xml.attribut("value",toString(_nb_bypass_write    )); xml.singleton_end();
+    xml.singleton_begin("queue_scheme       "); xml.attribut("value",toString(_queue_scheme       )); xml.singleton_end();
     xml.balise_close();
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue.cpp	(revision 114)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue.cpp	(revision 115)
@@ -84,10 +84,27 @@
 	SC_METHOD (genMoore);
 	dont_initialize ();
-	sensitive << (*(in_CLOCK)).neg();
+	sensitive << (*(in_CLOCK)).neg(); // need internal register
 	
 # ifdef SYSTEMCASS_SPECIFIC
 	// List dependency information
 # endif    
-	
+
+	if (_param->_queue_scheme == WRITE_QUEUE_SCHEME_MEALY)
+	  {
+	log_printf(INFO,Write_queue,FUNCTION,"Method - genMealy");
+
+	SC_METHOD (genMealy);
+	dont_initialize ();
+	sensitive << (*(in_CLOCK)).neg(); // need internal register
+	for (uint32_t i=0; i<_param->_nb_gpr_write; ++i)
+	  sensitive << (*(in_GPR_WRITE_ACK [i]));
+	for (uint32_t i=0; i<_param->_nb_spr_write; ++i)
+	  sensitive << (*(in_SPR_WRITE_ACK [i]));	
+
+# ifdef SYSTEMCASS_SPECIFIC
+	// List dependency information
+# endif    
+	  }
+
 #endif
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMealy.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMealy.cpp	(revision 115)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMealy.cpp	(revision 115)
@@ -0,0 +1,106 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_write_unit {
+namespace write_unit {
+namespace write_queue {
+
+
+#undef  FUNCTION
+#define FUNCTION "Write_queue::genMealy"
+  void Write_queue::genMealy (void)
+  {
+    log_begin(Write_queue,FUNCTION);
+    log_function(Write_queue,FUNCTION,_name.c_str());
+    
+    // -----[ Interface "bypass_write" ]----------------------------------
+    // in genMoore
+    // -----[ Interface "Write_queue_in" ]--------------------------------
+    // in genMoore
+
+    bool       val      = not _queue->empty();
+    Tcontrol_t write_rd = val and _queue->front()->_write_rd;
+    Tcontrol_t write_re = val and _queue->front()->_write_re;
+
+    // -----[ Interface "gpr_write" ]-------------------------------------
+    // -----[ Interface "spr_write" ]-------------------------------------
+    {
+      internal_GPR_WRITE_VAL = val and write_rd;
+      internal_SPR_WRITE_VAL = val and write_re;
+      
+      PORT_WRITE(out_GPR_WRITE_VAL [0], internal_GPR_WRITE_VAL);
+      PORT_WRITE(out_SPR_WRITE_VAL [0], internal_SPR_WRITE_VAL);
+
+      write_rd = (write_rd)?(not PORT_READ(in_GPR_WRITE_ACK [0])):0;
+      write_re = (write_re)?(not PORT_READ(in_SPR_WRITE_ACK [0])):0;
+
+      if (val)
+	{
+	  if (_param->_have_port_ooo_engine_id)
+	  {
+	  PORT_WRITE(out_GPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id);
+	  PORT_WRITE(out_SPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id);
+	  }
+	  PORT_WRITE(out_GPR_WRITE_NUM_REG       [0], _queue->front()->_num_reg_rd);
+	  PORT_WRITE(out_GPR_WRITE_DATA          [0], _queue->front()->_data_rd   );
+	  PORT_WRITE(out_SPR_WRITE_NUM_REG       [0], _queue->front()->_num_reg_re);
+	  PORT_WRITE(out_SPR_WRITE_DATA          [0], _queue->front()->_data_re   );
+	}
+    }
+
+    // -----[ Interface "Write_queue_out" ]--------------------------------
+    {
+      Texception_t load_speculative = (_queue->front()->_exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE);
+
+      internal_WRITE_QUEUE_OUT_VAL = ((val                 ) and
+				      (not load_speculative) and
+				      (not write_rd        ) and
+				      (not write_re        ));
+      
+      PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL);
+
+      if (internal_WRITE_QUEUE_OUT_VAL)
+	{
+	  if (_param->_have_port_context_id)
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_CONTEXT_ID   , _queue->front()->_context_id   );
+	  if (_param->_have_port_front_end_id)
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_FRONT_END_ID , _queue->front()->_front_end_id );
+	  if (_param->_have_port_ooo_engine_id)
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID, _queue->front()->_ooo_engine_id);
+	  if (_param->_have_port_rob_ptr  )
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_PACKET_ID    , _queue->front()->_packet_id    );
+//    	  PORT_WRITE(out_WRITE_QUEUE_OUT_OPERATION    , _queue->front()->_operation    );
+//    	  PORT_WRITE(out_WRITE_QUEUE_OUT_TYPE         , _queue->front()->_type         );
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_FLAGS        , _queue->front()->_data_re      );
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_EXCEPTION    , _queue->front()->_exception    );
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_NO_SEQUENCE  , _queue->front()->_no_sequence  );
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_ADDRESS      , _queue->front()->_address      );
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_DATA         , _queue->front()->_data_rd      );
+	}
+    }
+
+    log_end(Write_queue,FUNCTION);
+  };
+
+}; // end namespace write_queue
+}; // end namespace write_unit
+}; // end namespace multi_write_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp	(revision 114)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp	(revision 115)
@@ -26,64 +26,4 @@
     log_function(Write_queue,FUNCTION,_name.c_str());
     
-    // -----[ Interface "Write_queue_in" ]--------------------------------
-    {
-      internal_WRITE_QUEUE_IN_ACK = _queue->size() < _param->_size_queue;
-      
-      PORT_WRITE(out_WRITE_QUEUE_IN_ACK, internal_WRITE_QUEUE_IN_ACK);
-    }
-
-    // -----[ Interface "Write_queue_out" ]--------------------------------
-    {
-      // TODO : make a genMealy version
-      internal_WRITE_QUEUE_OUT_VAL = ((not _queue->empty()           ) and
-				      (not _queue->front()->_write_rd) and
-				      (not _queue->front()->_write_re));
-      
-      PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL);
-
-      if (internal_WRITE_QUEUE_OUT_VAL)
-	{
-	  if (_param->_have_port_context_id)
-      	  PORT_WRITE(out_WRITE_QUEUE_OUT_CONTEXT_ID   , _queue->front()->_context_id   );
-	  if (_param->_have_port_front_end_id)
-      	  PORT_WRITE(out_WRITE_QUEUE_OUT_FRONT_END_ID , _queue->front()->_front_end_id );
-	  if (_param->_have_port_ooo_engine_id)
-      	  PORT_WRITE(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID, _queue->front()->_ooo_engine_id);
-	  if (_param->_have_port_rob_ptr  )
-      	  PORT_WRITE(out_WRITE_QUEUE_OUT_PACKET_ID    , _queue->front()->_packet_id    );
-//    	  PORT_WRITE(out_WRITE_QUEUE_OUT_OPERATION    , _queue->front()->_operation    );
-//    	  PORT_WRITE(out_WRITE_QUEUE_OUT_TYPE         , _queue->front()->_type         );
-      	  PORT_WRITE(out_WRITE_QUEUE_OUT_FLAGS        , _queue->front()->_data_re      );
-      	  PORT_WRITE(out_WRITE_QUEUE_OUT_EXCEPTION    , _queue->front()->_exception    );
-      	  PORT_WRITE(out_WRITE_QUEUE_OUT_NO_SEQUENCE  , _queue->front()->_no_sequence  );
-      	  PORT_WRITE(out_WRITE_QUEUE_OUT_ADDRESS      , _queue->front()->_address      );
-      	  PORT_WRITE(out_WRITE_QUEUE_OUT_DATA         , _queue->front()->_data_rd      );
-	}
-    }
-
-    // -----[ Interface "gpr_write" ]-------------------------------------
-    // -----[ Interface "spr_write" ]-------------------------------------
-    {
-      bool val = not _queue->empty();
-
-      internal_GPR_WRITE_VAL = val and _queue->front()->_write_rd;
-      internal_SPR_WRITE_VAL = val and _queue->front()->_write_re;
-      
-      PORT_WRITE(out_GPR_WRITE_VAL [0], internal_GPR_WRITE_VAL);
-      PORT_WRITE(out_SPR_WRITE_VAL [0], internal_SPR_WRITE_VAL);
-
-      if (val)
-	{
-	  if (_param->_have_port_ooo_engine_id)
-	  {
-	  PORT_WRITE(out_GPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id);
-	  PORT_WRITE(out_SPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id);
-	  }
-	  PORT_WRITE(out_GPR_WRITE_NUM_REG       [0], _queue->front()->_num_reg_rd);
-	  PORT_WRITE(out_GPR_WRITE_DATA          [0], _queue->front()->_data_rd   );
-	  PORT_WRITE(out_SPR_WRITE_NUM_REG       [0], _queue->front()->_num_reg_re);
-	  PORT_WRITE(out_SPR_WRITE_DATA          [0], _queue->front()->_data_re   );
-	}
-    }
     // -----[ Interface "bypass_write" ]----------------------------------
     {
@@ -121,4 +61,68 @@
 	}
     }
+
+    // -----[ Interface "Write_queue_in" ]--------------------------------
+    {
+      internal_WRITE_QUEUE_IN_ACK = _queue->size() < _param->_size_queue;
+      
+      PORT_WRITE(out_WRITE_QUEUE_IN_ACK, internal_WRITE_QUEUE_IN_ACK);
+    }
+
+    if (_param->_queue_scheme == WRITE_QUEUE_SCHEME_MOORE)
+      {
+    // -----[ Interface "gpr_write" ]-------------------------------------
+    // -----[ Interface "spr_write" ]-------------------------------------
+    {
+      bool val = not _queue->empty();
+
+      internal_GPR_WRITE_VAL = val and _queue->front()->_write_rd;
+      internal_SPR_WRITE_VAL = val and _queue->front()->_write_re;
+      
+      PORT_WRITE(out_GPR_WRITE_VAL [0], internal_GPR_WRITE_VAL);
+      PORT_WRITE(out_SPR_WRITE_VAL [0], internal_SPR_WRITE_VAL);
+
+      if (val)
+	{
+	  if (_param->_have_port_ooo_engine_id)
+	  {
+	  PORT_WRITE(out_GPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id);
+	  PORT_WRITE(out_SPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id);
+	  }
+	  PORT_WRITE(out_GPR_WRITE_NUM_REG       [0], _queue->front()->_num_reg_rd);
+	  PORT_WRITE(out_GPR_WRITE_DATA          [0], _queue->front()->_data_rd   );
+	  PORT_WRITE(out_SPR_WRITE_NUM_REG       [0], _queue->front()->_num_reg_re);
+	  PORT_WRITE(out_SPR_WRITE_DATA          [0], _queue->front()->_data_re   );
+	}
+    }
+
+    // -----[ Interface "Write_queue_out" ]--------------------------------
+    {
+      internal_WRITE_QUEUE_OUT_VAL = ((not _queue->empty()           ) and
+				      (not _queue->front()->_write_rd) and
+				      (not _queue->front()->_write_re));
+      
+      PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL);
+
+      if (internal_WRITE_QUEUE_OUT_VAL)
+	{
+	  if (_param->_have_port_context_id)
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_CONTEXT_ID   , _queue->front()->_context_id   );
+	  if (_param->_have_port_front_end_id)
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_FRONT_END_ID , _queue->front()->_front_end_id );
+	  if (_param->_have_port_ooo_engine_id)
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID, _queue->front()->_ooo_engine_id);
+	  if (_param->_have_port_rob_ptr  )
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_PACKET_ID    , _queue->front()->_packet_id    );
+//    	  PORT_WRITE(out_WRITE_QUEUE_OUT_OPERATION    , _queue->front()->_operation    );
+//    	  PORT_WRITE(out_WRITE_QUEUE_OUT_TYPE         , _queue->front()->_type         );
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_FLAGS        , _queue->front()->_data_re      );
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_EXCEPTION    , _queue->front()->_exception    );
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_NO_SEQUENCE  , _queue->front()->_no_sequence  );
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_ADDRESS      , _queue->front()->_address      );
+      	  PORT_WRITE(out_WRITE_QUEUE_OUT_DATA         , _queue->front()->_data_rd      );
+	}
+    }
+
+      } // end WRITE_QUEUE_SCHEME_MOORE
     log_end(Write_queue,FUNCTION);
   };
