Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Makefile.deps (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Makefile.deps (revision 116) @@ -16,4 +16,7 @@ include $(DIR_MORPHEO)/Behavioural/Custom/Makefile.deps endif +ifndef Shifter +include $(DIR_MORPHEO)/Behavioural/Generic/Shifter/Makefile.deps +endif #-----[ Library ]------------------------------------------ @@ -21,15 +24,20 @@ $(Custom_LIBRARY) \ -lFunctionnal_unit \ - $(Behavioural_LIBRARY) + $(Behavioural_LIBRARY) \ + -lFunctionnal_unit \ + $(Shifter_LIBRARY) Functionnal_unit_DIR_LIBRARY = -L$(DIR_MORPHEO)/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/lib \ - $(Custom_DIR_LIBRARY) \ - $(Behavioural_DIR_LIBRARY) + $(Custom_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) \ + $(Shifter_DIR_LIBRARY) -Functionnal_unit_DEPENDENCIES = Custom_library \ - Behavioural_library +Functionnal_unit_DEPENDENCIES = Custom_library \ + Behavioural_library \ + Shifter_library -Functionnal_unit_CLEAN = Custom_library_clean \ - Behavioural_library_clean +Functionnal_unit_CLEAN = Custom_library_clean \ + Behavioural_library_clean \ + Shifter_library_clean #-----[ Rules ]-------------------------------------------- Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h (revision 116) @@ -1,4 +1,4 @@ -#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_functionnal_unit_operation_h -#define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_functionnal_unit_operation_h +#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_functionnal_unit_operation_Operation_h +#define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_functionnal_unit_operation_Operation_h /* Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h (revision 116) @@ -1,4 +1,4 @@ -#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_functionnal_unit_Types_h -#define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_functionnal_unit_Types_h +#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_functionnal_unit_operation_Types_h +#define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_functionnal_unit_operation_Types_h /* Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp (revision 116) @@ -50,5 +50,9 @@ op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -76,5 +80,9 @@ op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -102,5 +110,9 @@ op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -140,5 +152,9 @@ op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -178,5 +194,9 @@ op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -201,5 +221,9 @@ op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -224,5 +248,9 @@ op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -243,5 +271,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -262,5 +294,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -281,5 +317,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -299,5 +339,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -320,5 +364,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -402,5 +450,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -421,5 +473,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -440,5 +496,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -459,5 +519,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -478,5 +542,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -497,5 +565,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -517,5 +589,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -537,5 +613,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -557,5 +637,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -577,5 +661,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -598,5 +686,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -619,5 +711,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -640,5 +736,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -661,5 +761,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -693,5 +797,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -725,5 +833,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -757,5 +869,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -789,5 +905,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -912,5 +1032,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -936,5 +1060,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; @@ -960,5 +1088,9 @@ op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 0; - //op->_address = 0; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + op->_address = 0; +#else + //op->_address = 0; +#endif }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/mkf.info =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/mkf.info (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/mkf.info (revision 116) @@ -0,0 +1,11 @@ + +# Functionnal_unit_0 +target_dep all Functionnal_unit_0.ngc +target_dep Functionnal_unit_0.ngc Functionnal_unit_0.prj +target_dep Functionnal_unit_0.prj Functionnal_unit_0_Pack.vhdl Functionnal_unit_0_shifter_Pack.vhdl Functionnal_unit_0_shifter.vhdl Functionnal_unit_0.vhdl + +# Functionnal_unit_1 +target_dep all Functionnal_unit_1.ngc +target_dep Functionnal_unit_1.ngc Functionnal_unit_1.prj +target_dep Functionnal_unit_1.prj Functionnal_unit_1_Pack.vhdl Functionnal_unit_1_shifter_Pack.vhdl Functionnal_unit_1_shifter.vhdl Functionnal_unit_1.vhdl + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/main.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/main.cpp (revision 116) @@ -60,5 +60,8 @@ timing[i][j]._delay = timing[i][j]._latence = 1; } - + timing[4][1]._delay = 1; + timing[4][1]._latence = 7; + timing[4][2]._delay = 1; + timing[4][2]._latence = 7; try { Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp (revision 116) @@ -238,4 +238,6 @@ transaction_in.push_back(execute_transaction(_param,0,0,0, 0,OPERATION_ALU_L_ADD ,TYPE_ALU,0,0xdeadbeef,0x12344321,0x12345678,0 ,1,63,0x24689999,1,15,0 ,EXCEPTION_NONE ,0)); + + transaction_in.push_back(execute_transaction(_param,0,0,0, 1,OPERATION_ALU_L_ADD ,TYPE_ALU,0,0xffffffff,0x12345678,0x12345678,0 ,1,56,0x2468acf0,1,3 ,0 ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 2,OPERATION_ALU_L_ADD ,TYPE_ALU,1,0x12345678,0x12345678,0xffffffff,0 ,1,56,0x2468acf0,1,3 ,0 ,EXCEPTION_NONE ,0)); @@ -245,6 +247,6 @@ transaction_in.push_back(execute_transaction(_param,0,0,0, 5,OPERATION_ALU_L_ADD ,TYPE_ALU,1,0x80000000,0x80001000,0x0 ,0 ,1,1 ,0x1000 ,1,0 ,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 6,OPERATION_ALU_L_ADD ,TYPE_ALU,1,0x7fffffff,0x00000001,0x0 ,FLAG_CY|FLAG_OV,1,1 ,0x80000000,1,0 , FLAG_OV,EXCEPTION_ALU_RANGE,0)); - - + + transaction_in.push_back(execute_transaction(_param,0,0,0, 7,OPERATION_ALU_L_ADDC ,TYPE_ALU,0,0xdeadbeef,0x12344321,0x12345678,0 ,1,63,0x24689999,1,15,0 ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 8,OPERATION_ALU_L_ADDC ,TYPE_ALU,0,0xffffffff,0x12345678,0x12345678,0 ,1,56,0x2468acf0,1,3 ,0 ,EXCEPTION_NONE ,0)); @@ -254,5 +256,5 @@ transaction_in.push_back(execute_transaction(_param,0,0,0, 12,OPERATION_ALU_L_ADDC ,TYPE_ALU,1,0x80000000,0x80001000,0x0 ,0 ,1,1 ,0x1000 ,1,0 ,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 13,OPERATION_ALU_L_ADDC ,TYPE_ALU,1,0x7fffffff,0x00000001,0x0 ,0 ,1,1 ,0x80000000,1,0 , FLAG_OV,EXCEPTION_ALU_RANGE,0)); - + transaction_in.push_back(execute_transaction(_param,0,0,0, 14,OPERATION_ALU_L_ADDC ,TYPE_ALU,0,0xdeadbeef,0x12344320,0x12345678,FLAG_CY ,1,63,0x24689999,1,15,0 ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 15,OPERATION_ALU_L_ADDC ,TYPE_ALU,0,0xffffffff,0x12345677,0x12345678,FLAG_CY ,1,56,0x2468acf0,1,3 ,0 ,EXCEPTION_NONE ,0)); @@ -262,25 +264,25 @@ transaction_in.push_back(execute_transaction(_param,0,0,0, 19,OPERATION_ALU_L_ADDC ,TYPE_ALU,1,0x80000000,0x8000000f,0x0 ,FLAG_CY ,1,1 ,0x00000010,1,0 ,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 20,OPERATION_ALU_L_ADDC ,TYPE_ALU,1,0x7fffffff,0x00000000,0x0 ,FLAG_CY ,1,1 ,0x80000000,1,0 , FLAG_OV,EXCEPTION_ALU_RANGE,0)); - - + + transaction_in.push_back(execute_transaction(_param,0,0,0, 21,OPERATION_ALU_L_AND ,TYPE_ALU,0,0xdeadbeef,0x0000ffff,0x00ff00ff,0 ,1,63,0x000000ff,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 22,OPERATION_ALU_L_OR ,TYPE_ALU,0,0xdeadbeef,0x0000ffff,0x00ff00ff,0 ,1,63,0x00ffffff,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 23,OPERATION_ALU_L_XOR ,TYPE_ALU,0,0xdeadbeef,0x0000ffff,0x00ff00ff,0 ,1,63,0x00ffff00,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); - + transaction_in.push_back(execute_transaction(_param,0,0,0, 24,OPERATION_MOVE_L_CMOV ,TYPE_MOVE,0,0x0 ,0xdeadbeef,0x12345678,0 ,1,63,0x12345678,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 25,OPERATION_MOVE_L_CMOV ,TYPE_MOVE,0,0x0 ,0xdeadbeef,0x12345678,FLAG_F ,1,63,0xdeadbeef,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 26,OPERATION_MOVE_L_MOVHI ,TYPE_MOVE,1,0xdeadbeef,0x0 ,0x0 ,FLAG_F ,1,63,0xbeef0000,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); - - + + transaction_in.push_back(execute_transaction(_param,0,0,0, 27,OPERATION_BRANCH_L_TEST_F ,TYPE_BRANCH,1,0xdeadbeef,0x0 ,0x0 ,0 ,0,63,0xbeef0000,0,15,FLAG_CY ,EXCEPTION_NONE ,0,0x00000000)); transaction_in.push_back(execute_transaction(_param,0,0,0, 28,OPERATION_BRANCH_L_TEST_F ,TYPE_BRANCH,1,0xdeadbeef,0x0 ,0x0 ,FLAG_F ,0,63,0xbeef0000,0,15,FLAG_CY ,EXCEPTION_NONE ,1,0xdeadbeef)); transaction_in.push_back(execute_transaction(_param,0,0,0, 29,OPERATION_BRANCH_L_TEST_NF ,TYPE_BRANCH,1,0xdeadbeef,0x0 ,0x0 ,FLAG_F ,0,63,0xbeef0000,0,15,FLAG_CY ,EXCEPTION_NONE ,0,0x00000000)); transaction_in.push_back(execute_transaction(_param,0,0,0, 30,OPERATION_BRANCH_L_TEST_NF ,TYPE_BRANCH,1,0xdeadbeef,0x0 ,0x0 ,0 ,0,63,0xbeef0000,0,15,FLAG_CY ,EXCEPTION_NONE ,1,0xdeadbeef)); - - + + transaction_in.push_back(execute_transaction(_param,0,0,0, 31,OPERATION_BRANCH_L_JALR ,TYPE_BRANCH,0,0xdeadbeef,0x0 ,0x12345678,0 ,0,63,0xdeadbeef,0,15,FLAG_CY ,EXCEPTION_NONE ,1,0x12345678>>2)); // jr transaction_in.push_back(execute_transaction(_param,0,0,0, 32,OPERATION_BRANCH_L_JALR ,TYPE_BRANCH,1,0xdeadbeef,0x0 ,0x12345678,0 ,1,63,0xdeadbeef<<2,0,15,FLAG_CY ,EXCEPTION_NONE ,1,0x12345678>>2)); // jal transaction_in.push_back(execute_transaction(_param,0,0,0, 33,OPERATION_BRANCH_L_JALR ,TYPE_BRANCH,1,0xdeadbeef,0x0 ,0x12345678,0 ,1,63,0xdeadbeef<<2,0,15,FLAG_CY ,EXCEPTION_NONE ,1,0x12345678>>2)); // jalr - + transaction_in.push_back(execute_transaction(_param,0,0,0, 34,OPERATION_EXTEND_L_EXTEND_S,TYPE_EXTEND,1,8 ,0x12345678,0x0 ,0 ,1,63,0x00000078,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 35,OPERATION_EXTEND_L_EXTEND_S,TYPE_EXTEND,1,16 ,0x12345678,0x0 ,0 ,1,63,0x00005678,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); @@ -296,5 +298,5 @@ transaction_in.push_back(execute_transaction(_param,0,0,0, 41,OPERATION_EXTEND_L_EXTEND_Z,TYPE_EXTEND,1,16 ,0xdeadbeef,0x0 ,0 ,1,63,0x0000beef,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 42,OPERATION_EXTEND_L_EXTEND_Z,TYPE_EXTEND,1,32 ,0xdeadbeef,0x0 ,0 ,1,63,0xdeadbeef,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); - + transaction_in.push_back(execute_transaction(_param,0,0,0, 43,OPERATION_SHIFT_L_SLL ,TYPE_SHIFT,1,0 ,0xdeadbeef,0x0 ,0 ,1,63,0xdeadbeef,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 44,OPERATION_SHIFT_L_SLL ,TYPE_SHIFT,1,4 ,0xdeadbeef,0x0 ,0 ,1,63,0xeadbeef0,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); @@ -344,5 +346,5 @@ transaction_in.push_back(execute_transaction(_param,0,0,0, 88,OPERATION_SHIFT_L_ROR ,TYPE_SHIFT,1,24 ,0x12345678,0x0 ,0 ,1,63,0x34567812,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 89,OPERATION_SHIFT_L_ROR ,TYPE_SHIFT,1,32 ,0x12345678,0x0 ,0 ,1,63,0x12345678,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); - + transaction_in.push_back(execute_transaction(_param,0,0,0, 90,OPERATION_FIND_L_FF1 ,TYPE_FIND,0,0 ,0x12345678,0x0 ,0 ,1,63,4 ,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 91,OPERATION_FIND_L_FF1 ,TYPE_FIND,0,0 ,0x0 ,0x0 ,0 ,1,63,0 ,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); @@ -355,5 +357,5 @@ transaction_in.push_back(execute_transaction(_param,0,0,0, 98,OPERATION_FIND_L_FL1 ,TYPE_FIND,0,0 ,0x1 ,0x0 ,0 ,1,63,1 ,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0, 99,OPERATION_FIND_L_FL1 ,TYPE_FIND,0,0 ,0x80000000,0x0 ,0 ,1,63,32 ,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); - + transaction_in.push_back(execute_transaction(_param,0,0,0,100,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12344321,0x1 ,0 ,1,63,0x12344320,1,15,0 ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0,101,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12345678,0xffffffff,0 ,1,56,0x12345679,1,3 ,0 ,EXCEPTION_NONE ,0)); @@ -363,5 +365,5 @@ transaction_in.push_back(execute_transaction(_param,0,0,0,105,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x80001000,0x80000000,0 ,1,1 ,0x1000 ,1,0 , FLAG_OV,EXCEPTION_ALU_RANGE,0)); transaction_in.push_back(execute_transaction(_param,0,0,0,106,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x00000001,0x7fffffff,FLAG_CY|FLAG_OV,1,1 ,0x80000002,1,0 ,FLAG_CY ,EXCEPTION_NONE ,0)); - + transaction_in.push_back(execute_transaction(_param,0,0,0,120,OPERATION_TEST_L_SFEQ ,TYPE_TEST,0,0 ,0xdead ,0xdead ,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // + == + transaction_in.push_back(execute_transaction(_param,0,0,0,121,OPERATION_TEST_L_SFEQ ,TYPE_TEST,0,0 ,0x25071959,0x21071981,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // + > + @@ -484,5 +486,5 @@ transaction_in.push_back(execute_transaction(_param,0,0,0,300,OPERATION_TEST_L_SFLTS ,TYPE_TEST,0,0 ,0x33333333,0xdeadbeef,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // + > - (in unsigned) transaction_in.push_back(execute_transaction(_param,0,0,0,301,OPERATION_TEST_L_SFLTS ,TYPE_TEST,0,0 ,0x11111111,0xdeadbeef,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // + < - (in unsigned) - + /* transaction_in.push_back(execute_transaction(_param,0,0,0,400,OPERATION_SPECIAL_L_MTSPR ,TYPE_SPECIAL,1,GROUP_ICACHE<<11, 3,0xdeadbeef,0 ,0,63,0xdeadbeef,0, 0,0 ,EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE ,0,(GROUP_ICACHE<<11)| 3)); transaction_in.push_back(execute_transaction(_param,0,0,0,401,OPERATION_SPECIAL_L_MTSPR ,TYPE_SPECIAL,1,GROUP_ICACHE<<11, 5,0xdeadbeef,0 ,0,63,0xdeadbeef,0, 0,0 ,EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE ,0,(GROUP_ICACHE<<11)| 5)); @@ -568,5 +570,5 @@ transaction_in.push_back(execute_transaction(_param,0,0,0,627,OPERATION_SPECIAL_L_MFSPR ,TYPE_SPECIAL,1,GROUP_CUSTOM_7<<11, 0,0x0 ,0 ,1,63,0xe ,0, 0,0 ,EXCEPTION_ALU_NONE ,0,(GROUP_CUSTOM_7<<11)|0)); transaction_in.push_back(execute_transaction(_param,0,0,0,628,OPERATION_SPECIAL_L_MFSPR ,TYPE_SPECIAL,1,GROUP_CUSTOM_7<<11, 0,0x0 ,0 ,1,63,0xa ,0, 0,0 ,EXCEPTION_ALU_NONE ,0,(GROUP_CUSTOM_7<<11)|0)); - + */ transaction_in.push_back(execute_transaction(_param,0,0,0,700,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x00000001,0x00000001,0 ,1,63,0x00000001,1,15,0 ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0,701,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x00002107,0x00001981,0 ,1,63,0x034a5387,1,15,0 ,EXCEPTION_NONE ,0)); @@ -574,5 +576,5 @@ transaction_in.push_back(execute_transaction(_param,0,0,0,703,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x40000000,0x00000002,0 ,1,63,0x80000000,1,15,0 ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0,704,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x40000000,0x00000004,0 ,1,63,0x00000000,1,15,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); - + transaction_in.push_back(execute_transaction(_param,0,0,0,800,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00000001,0x00000001,0 ,1,63,0x00000001,1,15,0 ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0,801,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00002107,0x00001981,0 ,1,63,0x034a5387,1,15,0 ,EXCEPTION_NONE ,0)); @@ -580,5 +582,5 @@ transaction_in.push_back(execute_transaction(_param,0,0,0,803,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x40000000,0x00000002,0 ,1,63,0x80000000,1,15,0 ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0,804,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x40000000,0x00000004,0 ,1,63,0x00000000,1,15,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); - + @@ -602,5 +604,5 @@ while (nb_transaction_out > 0) { - Tcontrol_t val = ((rand()%100) < percent_transaction_execute_in) and not transaction_in.empty(); + Tcontrol_t val = ((rand()%100) < percent_transaction_execute_in) and not transaction_in.empty() and transaction_out.empty(); in_EXECUTE_IN_VAL .write(val); in_EXECUTE_OUT_ACK.write((rand()%100) < percent_transaction_execute_out); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h (revision 116) @@ -17,10 +17,9 @@ #include "Common/include/ToString.h" #include "Common/include/Debug.h" -#include "Behavioural/include/Types.h" #include "Behavioural/include/Identification.h" -#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h" +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Types.h" #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Parameters.h" -#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h" #ifdef STATISTICS #include "Behavioural/include/Stat.h" @@ -160,4 +159,5 @@ public : void transition (void); public : void genMoore (void); + public : void genMealy (void); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Parameters.h (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Parameters.h (revision 116) @@ -11,4 +11,5 @@ #include "Common/include/Debug.h" #include "Behavioural/include/Parameters.h" +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Types.h" #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h" #include "Behavioural/Custom/include/Custom.h" @@ -38,4 +39,5 @@ //public : uint32_t _size_store_queue ; //public : uint32_t _size_load_queue ; + public : const Tfunctionnal_unit_scheme_t _functionnal_unit_scheme; public : execute_timing_t ** _timing ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Types.h (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Types.h (revision 116) @@ -0,0 +1,37 @@ +#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_functionnal_unit_Types_h +#define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_functionnal_unit_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace multi_execute_unit { +namespace execute_unit { +namespace functionnal_unit { + +typedef enum + { + FUNCTIONNAL_UNIT_SCHEME_GLOBAL_REGISTERFILE, + FUNCTIONNAL_UNIT_SCHEME_LOCAL_REGISTERFILE + } Tfunctionnal_unit_scheme_t; + +}; // end namespace functionnal_unit +}; // end namespace execute_unit +}; // end namespace multi_execute_unit +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0.vhdl =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0.vhdl (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0.vhdl (revision 116) @@ -0,0 +1,803 @@ +------------------------------------------------------------------------------- +-- File : ./Functionnal_unit_0.vhdl +-- Date : Fri Mar 13 16:20:01 2009 +-- Version : 0.2.111 - Castor +-- Comment : it's a autogenerated file, don't modify +------------------------------------------------------------------------------- + + +library ieee; + use ieee.numeric_bit.all; + use ieee.numeric_std.all; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_misc.all; +--use ieee.std_logic_signed.all; + use ieee.std_logic_unsigned.all; +--use ieee.std_logic_textio.all; + + +library work; +use work.Functionnal_unit_0_Pack.all; +use work.Functionnal_unit_0_shifter_Pack.all; + +Library XilinxCoreLib; +use XilinxCoreLib.c_compare_v9_0_comp.all; + +entity Functionnal_unit_0 is + port ( + in_CLOCK : in std_logic; + in_NRESET : in std_logic; + in_EXECUTE_IN_VAL : in std_logic; + out_EXECUTE_IN_ACK : out std_logic; + in_EXECUTE_IN_OOO_ENGINE_ID : in std_logic; + in_EXECUTE_IN_PACKET_ID : in std_logic_vector(7 downto 0); + in_EXECUTE_IN_OPERATION : in std_logic_vector(6 downto 0); + in_EXECUTE_IN_TYPE : in std_logic_vector(4 downto 0); + in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE : in std_logic_vector(1 downto 0); + in_EXECUTE_IN_HAS_IMMEDIAT : in std_logic; + in_EXECUTE_IN_IMMEDIAT : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RA : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RB : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RC : in std_logic_vector(1 downto 0); + in_EXECUTE_IN_WRITE_RD : in std_logic; + in_EXECUTE_IN_NUM_REG_RD : in std_logic_vector(4 downto 0); + in_EXECUTE_IN_WRITE_RE : in std_logic; + in_EXECUTE_IN_NUM_REG_RE : in std_logic_vector(3 downto 0); + out_EXECUTE_OUT_VAL : out std_logic; + in_EXECUTE_OUT_ACK : in std_logic; + out_EXECUTE_OUT_OOO_ENGINE_ID : out std_logic; + out_EXECUTE_OUT_PACKET_ID : out std_logic_vector(7 downto 0); + out_EXECUTE_OUT_WRITE_RD : out std_logic; + out_EXECUTE_OUT_NUM_REG_RD : out std_logic_vector(4 downto 0); + out_EXECUTE_OUT_DATA_RD : out std_logic_vector(31 downto 0); + out_EXECUTE_OUT_WRITE_RE : out std_logic; + out_EXECUTE_OUT_NUM_REG_RE : out std_logic_vector(3 downto 0); + out_EXECUTE_OUT_DATA_RE : out std_logic_vector(1 downto 0); + out_EXECUTE_OUT_EXCEPTION : out std_logic_vector(4 downto 0); + out_EXECUTE_OUT_NO_SEQUENCE : out std_logic; + out_EXECUTE_OUT_ADDRESS : out std_logic_vector(29 downto 0) + ); +end Functionnal_unit_0; + +architecture behavioural of Functionnal_unit_0 is + type Tmac is array (1 downto 0) of std_logic_vector(31 downto 0); + + signal sig_EXECUTE_IN_ACK : std_logic; + signal reg_BUSY_IN : std_logic; + signal reg_EXECUTE_IN_OOO_ENGINE_ID : std_logic; + signal reg_EXECUTE_IN_PACKET_ID : std_logic_vector(7 downto 0); + signal reg_EXECUTE_IN_OPERATION : std_logic_vector(6 downto 0); + signal reg_EXECUTE_IN_TYPE : std_logic_vector(4 downto 0); + signal reg_EXECUTE_IN_HAS_IMMEDIAT : std_logic; + signal reg_EXECUTE_IN_IMMEDIAT : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RA : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RB : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RC : std_logic_vector(1 downto 0); + signal reg_EXECUTE_IN_WRITE_RD : std_logic; + signal reg_EXECUTE_IN_NUM_REG_RD : std_logic_vector(4 downto 0); + signal reg_EXECUTE_IN_WRITE_RE : std_logic; + signal reg_EXECUTE_IN_NUM_REG_RE : std_logic_vector(3 downto 0); + signal sig_B_OPERAND : std_logic_vector(31 downto 0); + signal sig_IS_ARITH : std_logic; + signal sig_IS_LOGIC : std_logic; + signal sig_CIN_ARITH : std_logic; + signal sig_ARITH_B_OPERAND : std_logic_vector(31 downto 0); + signal sig_RES_ARITH : std_logic_vector(32 downto 0); + signal sig_A_AND_B : std_logic_vector(31 downto 0); + signal sig_A_OR_B : std_logic_vector(31 downto 0); + signal sig_A_XOR_B : std_logic_vector(31 downto 0); + signal sig_RES_LOGIC : std_logic_vector(31 downto 0); + signal sig_RES_ALU : std_logic_vector(31 downto 0); + signal sig_OVR_ALU : std_logic; + signal sig_COUT_ALU : std_logic; + signal sig_RES_MOVE : std_logic_vector(31 downto 0); + signal sig_CMOV : std_logic_vector(31 downto 0); + signal sig_MOVHI : std_logic_vector(31 downto 0); + signal sig_RES_BRANCH : std_logic_vector(31 downto 0); + signal sig_ADDR_BRANCH : std_logic_vector(29 downto 0); + signal sig_NOSQ_BRANCH : std_logic; + signal sig_RES_SHIFTER : std_logic_vector(31 downto 0); + signal sig_EXT_BYTE_S : std_logic_vector(31 downto 0); + signal sig_EXT_BYTE_Z : std_logic_vector(31 downto 0); + signal sig_EXT_HALF_WORD_S : std_logic_vector(31 downto 0); + signal sig_EXT_HALF_WORD_Z : std_logic_vector(31 downto 0); + signal sig_EXT_WORD_S : std_logic_vector(31 downto 0); + signal sig_EXT_WORD_Z : std_logic_vector(31 downto 0); + signal sig_EXT_S : std_logic_vector(31 downto 0); + signal sig_EXT_Z : std_logic_vector(31 downto 0); + signal sig_RES_EXTEND : std_logic_vector(31 downto 0); + signal sig_FF1 : std_logic_vector(5 downto 0); + signal sig_FL1 : std_logic_vector(5 downto 0); + signal sig_RES_FIND : std_logic_vector(31 downto 0); + signal sig_SPR_IS_HERE : std_logic; + signal sig_MFSPR : std_logic_vector(31 downto 0); + signal sig_MTSPR : std_logic_vector(31 downto 0); + signal sig_RES_SPECIAL : std_logic_vector(31 downto 0); + signal sig_EXECUTE_OUT_VAL : std_logic; + signal sig_EXECUTE_OUT_UPDATE : std_logic; + signal reg_BUSY_OUT : std_logic; + signal reg_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; + signal sig_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; + signal reg_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); + signal sig_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); + signal reg_EXECUTE_OUT_WRITE_RD : std_logic; + signal sig_EXECUTE_OUT_WRITE_RD : std_logic; + signal reg_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); + signal sig_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); + signal reg_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); + signal sig_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); + signal reg_EXECUTE_OUT_WRITE_RE : std_logic; + signal sig_EXECUTE_OUT_WRITE_RE : std_logic; + signal reg_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); + signal sig_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); + signal reg_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); + signal sig_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); + signal reg_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); + signal sig_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); + signal reg_EXECUTE_OUT_NO_SEQUENCE : std_logic; + signal sig_EXECUTE_OUT_NO_SEQUENCE : std_logic; + signal reg_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); + signal sig_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); + signal reg_MACLO : Tmac; + signal reg_MACHI : Tmac; + + signal sig_IS_LESS : std_logic; + signal sig_A_COMPARE : std_logic_vector(31 downto 0); + signal sig_B_COMPARE : std_logic_vector(31 downto 0); + signal sig_A_GT_B_S : std_logic; + signal sig_A_GT_B_U : std_logic; + signal sig_A_EQ_B : std_logic; + signal sig_A_GT_B : std_logic; + signal sig_A_GE_B : std_logic; + signal sig_A_NE_B : std_logic; + signal sig_IS_SIGNED : std_logic; + signal sig_FLAG_F : std_logic; + signal sig_BUSY : std_logic; + + type TFQUEUE is array (7 downto 0) of std_logic_vector(131 downto 0); + -- OOO_ENGINE_ID(1) + PACKET_ID(8) + OPERATION(7) + TYPE(5) + + -- HAS_IMMEDIAT(1) + IMMEDIAT(32) + DATA_RA(32) + DATA_RB(32) + DATA_RC(2) + + -- WRITE_RD(1) + NUM_REG_RD(5) + WRITE_RE(1) + NUM_REG_RE(4) + VALID(1) + -- = 132 BITS + signal reg_FUNCTIONAL_QUEUE : TFQUEUE; + + + + alias reg_OOO_ENGINE_ID_7 : std_logic is reg_FUNCTIONAL_QUEUE(7)(131); + alias reg_OOO_ENGINE_ID_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(131); + alias reg_OOO_ENGINE_ID_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(131); + alias reg_OOO_ENGINE_ID_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(131); + alias reg_OOO_ENGINE_ID_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(131); + alias reg_OOO_ENGINE_ID_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(131); + alias reg_OOO_ENGINE_ID_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(131); + alias reg_OOO_ENGINE_ID_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(131); + alias reg_PACKET_ID_7 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(7)(130 downto 123); + alias reg_PACKET_ID_6 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(6)(130 downto 123); + alias reg_PACKET_ID_5 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(5)(130 downto 123); + alias reg_PACKET_ID_4 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(4)(130 downto 123); + alias reg_PACKET_ID_3 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(3)(130 downto 123); + alias reg_PACKET_ID_2 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(2)(130 downto 123); + alias reg_PACKET_ID_1 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(1)(130 downto 123); + alias reg_PACKET_ID_0 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(0)(130 downto 123); + alias reg_OPERATION_7 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(7)(122 downto 116); + alias reg_OPERATION_6 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(6)(122 downto 116); + alias reg_OPERATION_5 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(5)(122 downto 116); + alias reg_OPERATION_4 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(4)(122 downto 116); + alias reg_OPERATION_3 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(3)(122 downto 116); + alias reg_OPERATION_2 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(2)(122 downto 116); + alias reg_OPERATION_1 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(1)(122 downto 116); + + alias reg_TYPE_7 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(7)(115 downto 111); + alias reg_TYPE_6 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(6)(115 downto 111); + alias reg_TYPE_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(115 downto 111); + alias reg_TYPE_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(115 downto 111); + alias reg_TYPE_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(115 downto 111); + alias reg_TYPE_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(115 downto 111); + alias reg_TYPE_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(115 downto 111); + + alias reg_HAS_IMMEDIAT_7 : std_logic is reg_FUNCTIONAL_QUEUE(7)(110); + alias reg_HAS_IMMEDIAT_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(110); + alias reg_HAS_IMMEDIAT_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(110); + alias reg_HAS_IMMEDIAT_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(110); + alias reg_HAS_IMMEDIAT_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(110); + alias reg_HAS_IMMEDIAT_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(110); + alias reg_HAS_IMMEDIAT_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(110); + + alias reg_IMMEDIAT_7 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(7)(109 downto 78); + alias reg_IMMEDIAT_6 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(6)(109 downto 78); + alias reg_IMMEDIAT_5 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(5)(109 downto 78); + alias reg_IMMEDIAT_4 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(4)(109 downto 78); + alias reg_IMMEDIAT_3 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(3)(109 downto 78); + alias reg_IMMEDIAT_2 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(2)(109 downto 78); + alias reg_IMMEDIAT_1 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(1)(109 downto 78); + + alias reg_DATA_RA_7 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(7)(77 downto 46); + alias reg_DATA_RA_6 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(6)(77 downto 46); + alias reg_DATA_RA_5 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(5)(77 downto 46); + alias reg_DATA_RA_4 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(4)(77 downto 46); + alias reg_DATA_RA_3 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(3)(77 downto 46); + alias reg_DATA_RA_2 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(2)(77 downto 46); + alias reg_DATA_RA_1 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(1)(77 downto 46); + + alias reg_DATA_RB_7 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(7)(45 downto 14); + alias reg_DATA_RB_6 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(6)(45 downto 14); + alias reg_DATA_RB_5 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(5)(45 downto 14); + alias reg_DATA_RB_4 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(4)(45 downto 14); + alias reg_DATA_RB_3 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(3)(45 downto 14); + alias reg_DATA_RB_2 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(2)(45 downto 14); + alias reg_DATA_RB_1 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(1)(45 downto 14); + + alias reg_DATA_RC_7 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(7)(13 downto 12); + alias reg_DATA_RC_6 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(6)(13 downto 12); + alias reg_DATA_RC_5 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(5)(13 downto 12); + alias reg_DATA_RC_4 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(4)(13 downto 12); + alias reg_DATA_RC_3 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(3)(13 downto 12); + alias reg_DATA_RC_2 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(2)(13 downto 12); + alias reg_DATA_RC_1 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(1)(13 downto 12); + + alias reg_WRITE_RD_7 : std_logic is reg_FUNCTIONAL_QUEUE(7)(11); + alias reg_WRITE_RD_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(11); + alias reg_WRITE_RD_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(11); + alias reg_WRITE_RD_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(11); + alias reg_WRITE_RD_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(11); + alias reg_WRITE_RD_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(11); + alias reg_WRITE_RD_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(11); + alias reg_WRITE_RD_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(11); + alias reg_NUM_REG_RD_7 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(7)(10 downto 6); + alias reg_NUM_REG_RD_6 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(6)(10 downto 6); + alias reg_NUM_REG_RD_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(10 downto 6); + alias reg_NUM_REG_RD_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(10 downto 6); + alias reg_NUM_REG_RD_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(10 downto 6); + alias reg_NUM_REG_RD_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(10 downto 6); + alias reg_NUM_REG_RD_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(10 downto 6); + alias reg_NUM_REG_RD_0 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(0)(10 downto 6); + alias reg_WRITE_RE_7 : std_logic is reg_FUNCTIONAL_QUEUE(7)(5); + alias reg_WRITE_RE_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(5); + alias reg_WRITE_RE_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(5); + alias reg_WRITE_RE_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(5); + alias reg_WRITE_RE_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(5); + alias reg_WRITE_RE_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(5); + alias reg_WRITE_RE_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(5); + alias reg_WRITE_RE_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(5); + alias reg_NUM_REG_RE_7 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(7)(4 downto 1); + alias reg_NUM_REG_RE_6 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(6)(4 downto 1); + alias reg_NUM_REG_RE_5 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(5)(4 downto 1); + alias reg_NUM_REG_RE_4 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(4)(4 downto 1); + alias reg_NUM_REG_RE_3 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(3)(4 downto 1); + alias reg_NUM_REG_RE_2 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(2)(4 downto 1); + alias reg_NUM_REG_RE_1 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(1)(4 downto 1); + alias reg_NUM_REG_RE_0 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(0)(4 downto 1); + alias reg_VALID_7 : std_logic is reg_FUNCTIONAL_QUEUE(7)(0); + alias reg_VALID_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(0); + alias reg_VALID_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(0); + alias reg_VALID_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(0); + alias reg_VALID_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(0); + alias reg_VALID_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(0); + alias reg_VALID_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(0); + alias reg_VALID_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(0); + + -- OOO_ENGINE_ID(1) + PACKET_ID(8) + OPERATION(7) + TYPE (5) + + -- HAS_IMMEDIAT (1) + DATA_RA (32) + DATA_RB (32) + DATA_RC (2) + + -- WRITE_RD(1) + NUM_REG_RD(5) + WRITE_RE(1) + NUM_REG_RE(4) + VALID(1) + -- = 100 BITS + +begin + + -- + -- ----------------------------------- + -- -- Registers + -- ----------------------------------- + -- + + process (in_CLOCK) + begin + if in_CLOCK'event and in_CLOCK = '1' then + if (in_NRESET = '0') then + reg_BUSY_IN <= '0'; + reg_BUSY_OUT <= '0'; + else + -- Input + if (sig_EXECUTE_IN_ACK = '1') then + if (in_EXECUTE_IN_OPERATION = "00100") then + reg_VALID_7 <= in_EXECUTE_IN_VAL; + reg_NUM_REG_RE_7 <= in_EXECUTE_IN_NUM_REG_RE; + reg_WRITE_RE_7 <= in_EXECUTE_IN_WRITE_RE; + reg_NUM_REG_RD_7 <= in_EXECUTE_IN_NUM_REG_RD; + reg_WRITE_RD_7 <= in_EXECUTE_IN_WRITE_RD; + reg_DATA_RC_7 <= in_EXECUTE_IN_DATA_RC; + reg_DATA_RB_7 <= in_EXECUTE_IN_DATA_RB; + reg_DATA_RA_7 <= in_EXECUTE_IN_DATA_RA; + reg_IMMEDIAT_7 <= in_EXECUTE_IN_IMMEDIAT; + reg_HAS_IMMEDIAT_7 <= in_EXECUTE_IN_HAS_IMMEDIAT; + reg_TYPE_7 <= in_EXECUTE_IN_TYPE; + reg_OPERATION_7 <= in_EXECUTE_IN_OPERATION; + reg_PACKET_ID_7 <= in_EXECUTE_IN_PACKET_ID; + reg_OOO_ENGINE_ID_7 <= in_EXECUTE_IN_OOO_ENGINE_ID; + else + reg_VALID_1 <= in_EXECUTE_IN_VAL; + reg_NUM_REG_RE_1 <= in_EXECUTE_IN_NUM_REG_RE; + reg_WRITE_RE_1 <= in_EXECUTE_IN_WRITE_RE; + reg_NUM_REG_RD_1 <= in_EXECUTE_IN_NUM_REG_RD; + reg_WRITE_RD_1 <= in_EXECUTE_IN_WRITE_RD; + reg_DATA_RC_1 <= in_EXECUTE_IN_DATA_RC; + reg_DATA_RB_1 <= in_EXECUTE_IN_DATA_RB; + reg_DATA_RA_1 <= in_EXECUTE_IN_DATA_RA; + reg_IMMEDIAT_1 <= in_EXECUTE_IN_IMMEDIAT; + reg_HAS_IMMEDIAT_1 <= in_EXECUTE_IN_HAS_IMMEDIAT; + reg_TYPE_1 <= in_EXECUTE_IN_TYPE; + reg_OPERATION_1 <= in_EXECUTE_IN_OPERATION; + reg_PACKET_ID_1 <= in_EXECUTE_IN_PACKET_ID; + reg_OOO_ENGINE_ID_1 <= in_EXECUTE_IN_OOO_ENGINE_ID; + + end if; + end if; + if (sig_EXECUTE_OUT_UPDATE = '1') then + reg_VALID_0 <= reg_VALID_1; + reg_NUM_REG_RE_0 <= reg_NUM_REG_RE_1; + reg_WRITE_RE_0 <= reg_WRITE_RE_1; + reg_NUM_REG_RD_0 <= reg_NUM_REG_RD_1; + reg_WRITE_RD_0 <= reg_WRITE_RD_1; + reg_DATA_RC_0 <= reg_DATA_RC_1; + reg_DATA_RB_0 <= reg_DATA_RB_1; + reg_DATA_RA_0 <= reg_DATA_RA_1; + reg_IMMEDIAT_0 <= reg_IMMEDIAT_1; + reg_HAS_IMMEDIAT_0 <= reg_HAS_IMMEDIAT_1; + reg_TYPE_0 <= reg_TYPE_1; + reg_OPERATION_0 <= reg_OPERATION_1; + reg_PACKET_ID_0 <= reg_PACKET_ID_1; + reg_OOO_ENGINE_ID_0 <= reg_OOO_ENGINE_ID_1; + + reg_VALID_1 <= reg_VALID_2; + reg_NUM_REG_RE_1 <= reg_NUM_REG_RE_2; + reg_WRITE_RE_1 <= reg_WRITE_RE_2; + reg_NUM_REG_RD_1 <= reg_NUM_REG_RD_2; + reg_WRITE_RD_1 <= reg_WRITE_RD_2; + reg_DATA_RC_1 <= reg_DATA_RC_2; + reg_DATA_RB_1 <= reg_DATA_RB_2; + reg_DATA_RA_1 <= reg_DATA_RA_2; + reg_IMMEDIAT_1 <= reg_IMMEDIAT_2; + reg_HAS_IMMEDIAT_1 <= reg_HAS_IMMEDIAT_2; + reg_TYPE_1 <= reg_TYPE_2; + reg_OPERATION_1 <= reg_OPERATION_2; + reg_PACKET_ID_1 <= reg_PACKET_ID_2; + reg_OOO_ENGINE_ID_1 <= reg_OOO_ENGINE_ID_2; + + reg_VALID_2 <= reg_VALID_3; + reg_NUM_REG_RE_2 <= reg_NUM_REG_RE_3; + reg_WRITE_RE_2 <= reg_WRITE_RE_3; + reg_NUM_REG_RD_2 <= reg_NUM_REG_RD_3; + reg_WRITE_RD_2 <= reg_WRITE_RD_3; + reg_DATA_RC_2 <= reg_DATA_RC_3; + reg_DATA_RB_2 <= reg_DATA_RB_3; + reg_DATA_RA_2 <= reg_DATA_RA_3; + reg_IMMEDIAT_2 <= reg_IMMEDIAT_3; + reg_HAS_IMMEDIAT_2 <= reg_HAS_IMMEDIAT_3; + reg_TYPE_2 <= reg_TYPE_3; + reg_OPERATION_2 <= reg_OPERATION_3; + reg_PACKET_ID_2 <= reg_PACKET_ID_3; + reg_OOO_ENGINE_ID_2 <= reg_OOO_ENGINE_ID_3; + + reg_VALID_3 <= reg_VALID_4; + reg_NUM_REG_RE_3 <= reg_NUM_REG_RE_4; + reg_WRITE_RE_3 <= reg_WRITE_RE_4; + reg_NUM_REG_RD_3 <= reg_NUM_REG_RD_4; + reg_WRITE_RD_3 <= reg_WRITE_RD_4; + reg_DATA_RC_3 <= reg_DATA_RC_4; + reg_DATA_RB_3 <= reg_DATA_RB_4; + reg_DATA_RA_3 <= reg_DATA_RA_4; + reg_IMMEDIAT_3 <= reg_IMMEDIAT_4; + reg_HAS_IMMEDIAT_3 <= reg_HAS_IMMEDIAT_4; + reg_TYPE_3 <= reg_TYPE_4; + reg_OPERATION_3 <= reg_OPERATION_4; + reg_PACKET_ID_3 <= reg_PACKET_ID_4; + reg_OOO_ENGINE_ID_3 <= reg_OOO_ENGINE_ID_4; + + reg_VALID_4 <= reg_VALID_5; + reg_NUM_REG_RE_4 <= reg_NUM_REG_RE_5; + reg_WRITE_RE_4 <= reg_WRITE_RE_5; + reg_NUM_REG_RD_4 <= reg_NUM_REG_RD_5; + reg_WRITE_RD_4 <= reg_WRITE_RD_5; + reg_DATA_RC_4 <= reg_DATA_RC_5; + reg_DATA_RB_4 <= reg_DATA_RB_5; + reg_DATA_RA_4 <= reg_DATA_RA_5; + reg_IMMEDIAT_4 <= reg_IMMEDIAT_5; + reg_HAS_IMMEDIAT_4 <= reg_HAS_IMMEDIAT_5; + reg_TYPE_4 <= reg_TYPE_5; + reg_OPERATION_4 <= reg_OPERATION_5; + reg_PACKET_ID_4 <= reg_PACKET_ID_5; + reg_OOO_ENGINE_ID_4 <= reg_OOO_ENGINE_ID_5; + + reg_VALID_5 <= reg_VALID_6; + reg_NUM_REG_RE_5 <= reg_NUM_REG_RE_6; + reg_WRITE_RE_5 <= reg_WRITE_RE_6; + reg_NUM_REG_RD_5 <= reg_NUM_REG_RD_6; + reg_WRITE_RD_5 <= reg_WRITE_RD_6; + reg_DATA_RC_5 <= reg_DATA_RC_6; + reg_DATA_RB_5 <= reg_DATA_RB_6; + reg_DATA_RA_5 <= reg_DATA_RA_6; + reg_IMMEDIAT_5 <= reg_IMMEDIAT_6; + reg_HAS_IMMEDIAT_5 <= reg_HAS_IMMEDIAT_6; + reg_TYPE_5 <= reg_TYPE_6; + reg_OPERATION_5 <= reg_OPERATION_6; + reg_PACKET_ID_5 <= reg_PACKET_ID_6; + reg_OOO_ENGINE_ID_5 <= reg_OOO_ENGINE_ID_6; + + reg_VALID_6 <= reg_VALID_7; + reg_NUM_REG_RE_6 <= reg_NUM_REG_RE_7; + reg_WRITE_RE_6 <= reg_WRITE_RE_7; + reg_NUM_REG_RD_6 <= reg_NUM_REG_RD_7; + reg_WRITE_RD_6 <= reg_WRITE_RD_7; + reg_DATA_RC_6 <= reg_DATA_RC_7; + reg_DATA_RB_6 <= reg_DATA_RB_7; + reg_DATA_RA_6 <= reg_DATA_RA_7; + reg_IMMEDIAT_6 <= reg_IMMEDIAT_7; + reg_HAS_IMMEDIAT_6 <= reg_HAS_IMMEDIAT_7; + reg_TYPE_6 <= reg_TYPE_7; + reg_OPERATION_6 <= reg_OPERATION_7; + reg_PACKET_ID_6 <= reg_PACKET_ID_7; + reg_OOO_ENGINE_ID_6 <= reg_OOO_ENGINE_ID_7; + end if; + end if; + end if; + end process; + + -- + -- ----------------------------------- + -- -- Insides + -- ----------------------------------- + -- + + sig_B_OPERAND <= reg_IMMEDIAT_1 when (reg_HAS_IMMEDIAT_1 = '1') else + reg_DATA_RB_1; + -- + -- ALU + -- + sig_IS_ARITH <= reg_OPERATION_1(0) or reg_OPERATION_1(1) or reg_OPERATION_1(2); + sig_IS_LOGIC <= reg_OPERATION_1(3) or reg_OPERATION_1(4) or reg_OPERATION_1(5); + sig_CIN_ARITH <= reg_DATA_RC_1(1) and reg_OPERATION_1(1); + sig_ARITH_B_OPERAND <= ((not sig_B_OPERAND) + 1) when (reg_OPERATION_1(2) = '1') else + sig_B_OPERAND; + sig_RES_ARITH <= ('0' & reg_DATA_RA_1) + ('0' & sig_ARITH_B_OPERAND) + ("000000000000000000000000000000" & sig_CIN_ARITH); + + sig_A_AND_B <= reg_DATA_RA_1 and sig_B_OPERAND; + sig_A_OR_B <= reg_DATA_RA_1 or sig_B_OPERAND; + sig_A_XOR_B <= reg_DATA_RA_1 xor sig_B_OPERAND; + + with reg_OPERATION_1 select + sig_RES_LOGIC <= + sig_A_AND_B when "0001000", + sig_A_OR_B when "0010000", + sig_A_XOR_B when "0100000", + "00000000000000000000000000000000" when others; + sig_RES_ALU <= + sig_RES_ARITH (31 downto 0) when (sig_IS_ARITH = '1') else + sig_RES_LOGIC when (sig_IS_LOGIC = '1') else + "00000000000000000000000000000000"; + + -- In ISA l.sub doesn't change carry flag. + sig_COUT_ALU <= (sig_RES_ARITH(32) and (reg_OPERATION_1(0) or reg_OPERATION_1(1))) or (reg_OPERATION_1(2) and reg_DATA_RC_1(1)); + sig_OVR_ALU <= ((sig_ARITH_B_OPERAND(31) and reg_DATA_RA_1(31) and not sig_RES_ARITH(31)) or (not sig_ARITH_B_OPERAND(31) and not reg_DATA_RA_1(31) and sig_RES_ARITH(31))) and sig_IS_ARITH; + + -- + -- MOVE + -- + sig_MOVHI <= reg_IMMEDIAT_1(15 downto 0) & "0000000000000000"; + sig_CMOV <= + reg_DATA_RA_1 when (reg_DATA_RC_1(0) = '1') else + reg_DATA_RB_1; + sig_RES_MOVE <= + sig_MOVHI when (reg_OPERATION_1(0) = '1') else + sig_CMOV when (reg_OPERATION_1(1) = '1') else + "00000000000000000000000000000000"; + + -- + -- TEST + -- + sig_IS_LESS <= reg_OPERATION_1(3); + sig_A_COMPARE <= + sig_B_OPERAND when (sig_IS_LESS = '1') else + reg_DATA_RA_1; + + sig_B_COMPARE <= + reg_DATA_RA_1 when (sig_IS_LESS = '1') else + sig_B_OPERAND; + + a_gt_b_s : c_compare_v9_0 + generic map ( + c_width => 32, + c_data_type => 0, -- 0 = signed, 1 = unsigned + c_has_a_eq_b => 0, + c_has_a_gt_b => 1) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_gt_b => sig_A_GT_B_S); + + a_gt_b_u : c_compare_v9_0 + generic map ( + c_width => 32, + c_data_type => 1, -- 0 = signed, 1 = unsigned + c_has_a_eq_b => 0, + c_has_a_gt_b => 1) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_gt_b => sig_A_GT_B_U); + + a_eq_b : c_compare_v9_0 + generic map ( -- sign doesn't matter for + -- equality test + c_width => 32, + c_has_a_eq_b => 1, + c_has_a_gt_b => 0) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_eq_b => sig_A_EQ_B); + + sig_IS_SIGNED <= reg_OPERATION_1(6); + sig_A_GT_B <= + sig_A_GT_B_S when (sig_IS_SIGNED = '1') else + sig_A_GT_B_U; + sig_A_GE_B <= sig_A_GT_B or sig_A_EQ_B; + sig_A_NE_B <= not sig_A_EQ_B; + + sig_FLAG_F <= + (sig_A_EQ_B and reg_OPERATION_1(4)) or + (sig_A_NE_B and reg_OPERATION_1(5)) or + (sig_A_GE_B and reg_OPERATION_1(0)) or + (sig_A_GT_B and reg_OPERATION_1(1)); + + + -- + -- BRANCH + -- + sig_NOSQ_BRANCH <= (reg_DATA_RC_1(0) and reg_OPERATION_1(2)) or (not reg_DATA_RC_1(0) and reg_OPERATION_1(1)) or reg_OPERATION_1(3); + sig_RES_BRANCH <= + reg_IMMEDIAT_1(29 downto 0) & "00"when (reg_OPERATION_1(3) = '1') else + "00000000000000000000000000000000"; + sig_ADDR_BRANCH <= + reg_DATA_RB_1(31 downto 2) when (reg_OPERATION_1(3) = '1') else + reg_IMMEDIAT_1(29 downto 0); + + -- + -- SHIFTER + -- + -- Instance shifter + instance_Functionnal_unit_0_shifter : Functionnal_unit_0_shifter + port map ( + in_SHIFTER_0_DATA => reg_DATA_RA_1 + , in_SHIFTER_0_SHIFT => sig_B_OPERAND(4 downto 0) + , in_SHIFTER_0_DIRECTION => reg_OPERATION_1(0) + , in_SHIFTER_0_TYPE => reg_OPERATION_1(1) + , in_SHIFTER_0_CARRY => reg_OPERATION_1(2) + ,out_SHIFTER_0_DATA => sig_RES_SHIFTER + ); + + + -- + -- EXTEND + -- + sig_EXT_BYTE_S <= + "111111111111111111111111" & reg_DATA_RA_1 (7 downto 0) when (reg_DATA_RA_1 (7) = '1') else + "000000000000000000000000" & reg_DATA_RA_1 (7 downto 0); + + sig_EXT_BYTE_Z <= + "000000000000000000000000" & reg_DATA_RA_1 (7 downto 0); + + sig_EXT_HALF_WORD_S <= + "1111111111111111" & reg_DATA_RA_1 (15 downto 0) when (reg_DATA_RA_1 (15) = '1') else + "0000000000000000" & reg_DATA_RA_1 (15 downto 0); + + sig_EXT_HALF_WORD_Z <= + "0000000000000000" & reg_DATA_RA_1 (15 downto 0); + + sig_EXT_WORD_S <= + "" & reg_DATA_RA_1 (31 downto 0) when (reg_DATA_RA_1 (31) = '1') else + "" & reg_DATA_RA_1 (31 downto 0); + + sig_EXT_WORD_Z <= + "" & reg_DATA_RA_1 (31 downto 0); + + sig_EXT_S <= + sig_EXT_BYTE_S when (reg_IMMEDIAT_1 = 8) else + sig_EXT_HALF_WORD_S when (reg_IMMEDIAT_1 = 16) else + sig_EXT_WORD_S; + + sig_EXT_Z <= + sig_EXT_BYTE_Z when (reg_IMMEDIAT_1 = 8) else + sig_EXT_HALF_WORD_Z when (reg_IMMEDIAT_1 = 16) else + sig_EXT_WORD_Z; + + sig_RES_EXTEND <= + sig_EXT_Z when (reg_OPERATION_1(0) = '1') else + sig_EXT_S; + + + -- + -- FIND + -- + sig_FF1 <= + "000001" when (reg_DATA_RA_1 (0) = '1') else + "000010" when (reg_DATA_RA_1 (1) = '1') else + "000011" when (reg_DATA_RA_1 (2) = '1') else + "000100" when (reg_DATA_RA_1 (3) = '1') else + "000101" when (reg_DATA_RA_1 (4) = '1') else + "000110" when (reg_DATA_RA_1 (5) = '1') else + "000111" when (reg_DATA_RA_1 (6) = '1') else + "001000" when (reg_DATA_RA_1 (7) = '1') else + "001001" when (reg_DATA_RA_1 (8) = '1') else + "001010" when (reg_DATA_RA_1 (9) = '1') else + "001011" when (reg_DATA_RA_1 (10) = '1') else + "001100" when (reg_DATA_RA_1 (11) = '1') else + "001101" when (reg_DATA_RA_1 (12) = '1') else + "001110" when (reg_DATA_RA_1 (13) = '1') else + "001111" when (reg_DATA_RA_1 (14) = '1') else + "010000" when (reg_DATA_RA_1 (15) = '1') else + "010001" when (reg_DATA_RA_1 (16) = '1') else + "010010" when (reg_DATA_RA_1 (17) = '1') else + "010011" when (reg_DATA_RA_1 (18) = '1') else + "010100" when (reg_DATA_RA_1 (19) = '1') else + "010101" when (reg_DATA_RA_1 (20) = '1') else + "010110" when (reg_DATA_RA_1 (21) = '1') else + "010111" when (reg_DATA_RA_1 (22) = '1') else + "011000" when (reg_DATA_RA_1 (23) = '1') else + "011001" when (reg_DATA_RA_1 (24) = '1') else + "011010" when (reg_DATA_RA_1 (25) = '1') else + "011011" when (reg_DATA_RA_1 (26) = '1') else + "011100" when (reg_DATA_RA_1 (27) = '1') else + "011101" when (reg_DATA_RA_1 (28) = '1') else + "011110" when (reg_DATA_RA_1 (29) = '1') else + "011111" when (reg_DATA_RA_1 (30) = '1') else + "100000" when (reg_DATA_RA_1 (31) = '1') else + "000000"; + + sig_FL1 <= + "100000" when (reg_DATA_RA_1 (31) = '1') else + "011111" when (reg_DATA_RA_1 (30) = '1') else + "011110" when (reg_DATA_RA_1 (29) = '1') else + "011101" when (reg_DATA_RA_1 (28) = '1') else + "011100" when (reg_DATA_RA_1 (27) = '1') else + "011011" when (reg_DATA_RA_1 (26) = '1') else + "011010" when (reg_DATA_RA_1 (25) = '1') else + "011001" when (reg_DATA_RA_1 (24) = '1') else + "011000" when (reg_DATA_RA_1 (23) = '1') else + "010111" when (reg_DATA_RA_1 (22) = '1') else + "010110" when (reg_DATA_RA_1 (21) = '1') else + "010101" when (reg_DATA_RA_1 (20) = '1') else + "010100" when (reg_DATA_RA_1 (19) = '1') else + "010011" when (reg_DATA_RA_1 (18) = '1') else + "010010" when (reg_DATA_RA_1 (17) = '1') else + "010001" when (reg_DATA_RA_1 (16) = '1') else + "010000" when (reg_DATA_RA_1 (15) = '1') else + "001111" when (reg_DATA_RA_1 (14) = '1') else + "001110" when (reg_DATA_RA_1 (13) = '1') else + "001101" when (reg_DATA_RA_1 (12) = '1') else + "001100" when (reg_DATA_RA_1 (11) = '1') else + "001011" when (reg_DATA_RA_1 (10) = '1') else + "001010" when (reg_DATA_RA_1 (9) = '1') else + "001001" when (reg_DATA_RA_1 (8) = '1') else + "001000" when (reg_DATA_RA_1 (7) = '1') else + "000111" when (reg_DATA_RA_1 (6) = '1') else + "000110" when (reg_DATA_RA_1 (5) = '1') else + "000101" when (reg_DATA_RA_1 (4) = '1') else + "000100" when (reg_DATA_RA_1 (3) = '1') else + "000011" when (reg_DATA_RA_1 (2) = '1') else + "000010" when (reg_DATA_RA_1 (1) = '1') else + "000001" when (reg_DATA_RA_1 (0) = '1') else + "000000"; + + sig_RES_FIND <= + "00000000000000000000000000"&sig_FF1 when (reg_OPERATION_1(0) = '1') else + "00000000000000000000000000"&sig_FL1; + + + -- + -- SPECIAL + -- + sig_SPR_IS_HERE <= + '1' when (sig_A_OR_B(15 downto 0) = "00101") else + '0'; + -- MFSPR + sig_MFSPR <= + reg_MACLO(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000001") else + reg_MACHI(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000010") else + "00000000000000000000000000000000"; + + + -- MTSPR + process (in_CLOCK) + begin + if in_CLOCK'event and in_CLOCK = '1' then + if (sig_SPR_IS_HERE = '1') then + if (sig_A_OR_B(10 downto 0) = "00000000001") then + reg_MACLO(0) <= reg_DATA_RB_1; + end if; + if (sig_A_OR_B(10 downto 0) = "00000000010") then + reg_MACHI(0) <= reg_DATA_RB_1; + end if; + end if; + end if; + end process; + + sig_RES_SPECIAL <= + sig_MFSPR when (reg_OPERATION_1 = "0000001") else + reg_DATA_RB_1 when (reg_OPERATION_1 = "0000010") else + "00000000000000000000000000000000"; + + -- + -- TRANSACTION + -- + sig_BUSY <= +-- reg_FUNCTIONAL_QUEUE(34)(0) when in_EXECUTE_IN_OPERATION = "" else + reg_FUNCTIONAL_QUEUE(7)(0) when in_EXECUTE_IN_OPERATION = "" else + reg_FUNCTIONAL_QUEUE(1)(0); + sig_EXECUTE_OUT_VAL <= reg_FUNCTIONAL_QUEUE(0)(0); + sig_EXECUTE_OUT_UPDATE <= not reg_FUNCTIONAL_QUEUE(0)(0) or in_EXECUTE_OUT_ACK; + sig_EXECUTE_IN_ACK <= not sig_BUSY or sig_EXECUTE_OUT_UPDATE; + + -- + -- ----------------------------------- + -- -- + -- ----------------------------------- + -- + + sig_EXECUTE_OUT_OOO_ENGINE_ID <= reg_OOO_ENGINE_ID_1; + sig_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_IN_PACKET_ID; + sig_EXECUTE_OUT_WRITE_RD <= reg_WRITE_RD_1; + sig_EXECUTE_OUT_NUM_REG_RD <= reg_NUM_REG_RD_1; + with reg_TYPE_1 select + sig_EXECUTE_OUT_DATA_RD <= + sig_RES_ALU when "00000", + sig_RES_MOVE when "00010", + sig_RES_BRANCH when "01010", + sig_RES_SHIFTER when "00001", + sig_RES_EXTEND when "00110", + sig_RES_FIND when "00111", + sig_RES_SPECIAL when "01000", + "00000000000000000000000000000000" when others; + sig_EXECUTE_OUT_WRITE_RE <= reg_WRITE_RE_1; + sig_EXECUTE_OUT_NUM_REG_RE <= reg_NUM_REG_RE_1; + with reg_TYPE_1 select + sig_EXECUTE_OUT_DATA_RE <= + sig_COUT_ALU & sig_OVR_ALU when "00000", + '0' & sig_FLAG_F when "00011", + "00" when others; + sig_EXECUTE_OUT_EXCEPTION <= + "01011" when (reg_TYPE_1 = "00000" and sig_OVR_ALU = '1') else + "10011" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000001" and sig_SPR_IS_HERE = '0') else + "10100" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000010" and sig_SPR_IS_HERE = '0') else + "00000"; + with reg_TYPE_1 select + sig_EXECUTE_OUT_NO_SEQUENCE <= + sig_NOSQ_BRANCH when "01010", + '0'when others; + with reg_TYPE_1 select + sig_EXECUTE_OUT_ADDRESS <= + sig_ADDR_BRANCH when "01010", + sig_A_OR_B(29 downto 0) when "01000", + "000000000000000000000000000000" when others; + + -- + -- ----------------------------------- + -- -- Outputs + -- ----------------------------------- + -- + + out_EXECUTE_OUT_OOO_ENGINE_ID <= reg_EXECUTE_OUT_OOO_ENGINE_ID; + out_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_OUT_PACKET_ID; + out_EXECUTE_OUT_WRITE_RD <= reg_EXECUTE_OUT_WRITE_RD; + out_EXECUTE_OUT_NUM_REG_RD <= reg_EXECUTE_OUT_NUM_REG_RD; + out_EXECUTE_OUT_DATA_RD <= reg_EXECUTE_OUT_DATA_RD; + out_EXECUTE_OUT_WRITE_RE <= reg_EXECUTE_OUT_WRITE_RE; + out_EXECUTE_OUT_NUM_REG_RE <= reg_EXECUTE_OUT_NUM_REG_RE; + out_EXECUTE_OUT_DATA_RE <= reg_EXECUTE_OUT_DATA_RE; + out_EXECUTE_OUT_EXCEPTION <= reg_EXECUTE_OUT_EXCEPTION; + out_EXECUTE_OUT_NO_SEQUENCE <= reg_EXECUTE_OUT_NO_SEQUENCE; + out_EXECUTE_OUT_ADDRESS <= reg_EXECUTE_OUT_ADDRESS; + out_EXECUTE_OUT_VAL <= sig_EXECUTE_OUT_VAL; + out_EXECUTE_IN_ACK <= sig_EXECUTE_IN_ACK; + +end behavioural; + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0.vhdl.bak =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0.vhdl.bak (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0.vhdl.bak (revision 116) @@ -0,0 +1,567 @@ +------------------------------------------------------------------------------- +-- File : ./Functionnal_unit_0.vhdl +-- Date : Fri Mar 13 16:20:01 2009 +-- Version : 0.2.111 - Castor +-- Comment : it's a autogenerated file, don't modify +------------------------------------------------------------------------------- + + +library ieee; + use ieee.numeric_bit.all; + use ieee.numeric_std.all; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_misc.all; +--use ieee.std_logic_signed.all; + use ieee.std_logic_unsigned.all; +--use ieee.std_logic_textio.all; + + +library work; +use work.Functionnal_unit_0_Pack.all; +use work.Functionnal_unit_0_shifter_Pack.all; + +Library XilinxCoreLib; +use XilinxCoreLib.c_compare_v9_0_comp.all; + +entity Functionnal_unit_0 is + port ( + in_CLOCK : in std_logic; + in_NRESET : in std_logic; + in_EXECUTE_IN_VAL : in std_logic; + out_EXECUTE_IN_ACK : out std_logic; + in_EXECUTE_IN_OOO_ENGINE_ID : in std_logic; + in_EXECUTE_IN_PACKET_ID : in std_logic_vector(7 downto 0); + in_EXECUTE_IN_OPERATION : in std_logic_vector(6 downto 0); + in_EXECUTE_IN_TYPE : in std_logic_vector(4 downto 0); + in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE : in std_logic_vector(1 downto 0); + in_EXECUTE_IN_HAS_IMMEDIAT : in std_logic; + in_EXECUTE_IN_IMMEDIAT : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RA : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RB : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RC : in std_logic_vector(1 downto 0); + in_EXECUTE_IN_WRITE_RD : in std_logic; + in_EXECUTE_IN_NUM_REG_RD : in std_logic_vector(4 downto 0); + in_EXECUTE_IN_WRITE_RE : in std_logic; + in_EXECUTE_IN_NUM_REG_RE : in std_logic_vector(3 downto 0); + out_EXECUTE_OUT_VAL : out std_logic; + in_EXECUTE_OUT_ACK : in std_logic; + out_EXECUTE_OUT_OOO_ENGINE_ID : out std_logic; + out_EXECUTE_OUT_PACKET_ID : out std_logic_vector(7 downto 0); + out_EXECUTE_OUT_WRITE_RD : out std_logic; + out_EXECUTE_OUT_NUM_REG_RD : out std_logic_vector(4 downto 0); + out_EXECUTE_OUT_DATA_RD : out std_logic_vector(31 downto 0); + out_EXECUTE_OUT_WRITE_RE : out std_logic; + out_EXECUTE_OUT_NUM_REG_RE : out std_logic_vector(3 downto 0); + out_EXECUTE_OUT_DATA_RE : out std_logic_vector(1 downto 0); + out_EXECUTE_OUT_EXCEPTION : out std_logic_vector(4 downto 0); + out_EXECUTE_OUT_NO_SEQUENCE : out std_logic; + out_EXECUTE_OUT_ADDRESS : out std_logic_vector(29 downto 0) + ); +end Functionnal_unit_0; + +architecture behavioural of Functionnal_unit_0 is + type Tmac is array (1 downto 0) of std_logic_vector(31 downto 0); + + signal sig_EXECUTE_IN_ACK : std_logic; + signal reg_BUSY_IN : std_logic; + signal reg_EXECUTE_IN_OOO_ENGINE_ID : std_logic; + signal reg_EXECUTE_IN_PACKET_ID : std_logic_vector(7 downto 0); + signal reg_EXECUTE_IN_OPERATION : std_logic_vector(6 downto 0); + signal reg_EXECUTE_IN_TYPE : std_logic_vector(4 downto 0); + signal reg_EXECUTE_IN_HAS_IMMEDIAT : std_logic; + signal reg_EXECUTE_IN_IMMEDIAT : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RA : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RB : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RC : std_logic_vector(1 downto 0); + signal reg_EXECUTE_IN_WRITE_RD : std_logic; + signal reg_EXECUTE_IN_NUM_REG_RD : std_logic_vector(4 downto 0); + signal reg_EXECUTE_IN_WRITE_RE : std_logic; + signal reg_EXECUTE_IN_NUM_REG_RE : std_logic_vector(3 downto 0); + signal sig_B_OPERAND : std_logic_vector(31 downto 0); + signal sig_IS_ARITH : std_logic; + signal sig_IS_LOGIC : std_logic; + signal sig_CIN_ARITH : std_logic; + signal sig_ARITH_B_OPERAND : std_logic_vector(31 downto 0); + signal sig_RES_ARITH : std_logic_vector(32 downto 0); + signal sig_A_AND_B : std_logic_vector(31 downto 0); + signal sig_A_OR_B : std_logic_vector(31 downto 0); + signal sig_A_XOR_B : std_logic_vector(31 downto 0); + signal sig_RES_LOGIC : std_logic_vector(31 downto 0); + signal sig_RES_ALU : std_logic_vector(31 downto 0); + signal sig_OVR_ALU : std_logic; + signal sig_COUT_ALU : std_logic; + signal sig_RES_MOVE : std_logic_vector(31 downto 0); + signal sig_CMOV : std_logic_vector(31 downto 0); + signal sig_MOVHI : std_logic_vector(31 downto 0); + signal sig_RES_BRANCH : std_logic_vector(31 downto 0); + signal sig_ADDR_BRANCH : std_logic_vector(29 downto 0); + signal sig_NOSQ_BRANCH : std_logic; + signal sig_RES_SHIFTER : std_logic_vector(31 downto 0); + signal sig_EXT_BYTE_S : std_logic_vector(31 downto 0); + signal sig_EXT_BYTE_Z : std_logic_vector(31 downto 0); + signal sig_EXT_HALF_WORD_S : std_logic_vector(31 downto 0); + signal sig_EXT_HALF_WORD_Z : std_logic_vector(31 downto 0); + signal sig_EXT_WORD_S : std_logic_vector(31 downto 0); + signal sig_EXT_WORD_Z : std_logic_vector(31 downto 0); + signal sig_EXT_S : std_logic_vector(31 downto 0); + signal sig_EXT_Z : std_logic_vector(31 downto 0); + signal sig_RES_EXTEND : std_logic_vector(31 downto 0); + signal sig_FF1 : std_logic_vector(5 downto 0); + signal sig_FL1 : std_logic_vector(5 downto 0); + signal sig_RES_FIND : std_logic_vector(31 downto 0); + signal sig_SPR_IS_HERE : std_logic; + signal sig_MFSPR : std_logic_vector(31 downto 0); + signal sig_MTSPR : std_logic_vector(31 downto 0); + signal sig_RES_SPECIAL : std_logic_vector(31 downto 0); + signal sig_EXECUTE_OUT_VAL : std_logic; + signal sig_EXECUTE_OUT_UPDATE : std_logic; + signal reg_BUSY_OUT : std_logic; + signal reg_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; + signal sig_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; + signal reg_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); + signal sig_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); + signal reg_EXECUTE_OUT_WRITE_RD : std_logic; + signal sig_EXECUTE_OUT_WRITE_RD : std_logic; + signal reg_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); + signal sig_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); + signal reg_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); + signal sig_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); + signal reg_EXECUTE_OUT_WRITE_RE : std_logic; + signal sig_EXECUTE_OUT_WRITE_RE : std_logic; + signal reg_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); + signal sig_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); + signal reg_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); + signal sig_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); + signal reg_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); + signal sig_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); + signal reg_EXECUTE_OUT_NO_SEQUENCE : std_logic; + signal sig_EXECUTE_OUT_NO_SEQUENCE : std_logic; + signal reg_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); + signal sig_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); + signal reg_MACLO : Tmac; + signal reg_MACHI : Tmac; + + signal sig_IS_LESS : std_logic; + signal sig_A_COMPARE : std_logic_vector(31 downto 0); + signal sig_B_COMPARE : std_logic_vector(31 downto 0); + signal sig_A_GT_B_S : std_logic; + signal sig_A_GT_B_U : std_logic; + signal sig_A_EQ_B : std_logic; + signal sig_A_GT_B : std_logic; + signal sig_A_GE_B : std_logic; + signal sig_A_NE_B : std_logic; + signal sig_IS_SIGNED : std_logic; + signal sig_FLAG_F : std_logic; + +-- type TFQUEUE is array (5 downto 0) of std_logic_vector(27 downto 0); + -- OOO_ENGINE_ID(1) + PACKET_ID(8) + WRITE_RD(1) + NUM_REG_RD(5) + WRITE_RE(1) + + -- NUM_REG_RE(4) + OPERATION (7) + VALID(1) = 28 bits + +begin + + -- + -- ----------------------------------- + -- -- Registers + -- ----------------------------------- + -- + + process (in_CLOCK) + begin + if in_CLOCK'event and in_CLOCK = '1' then + if (in_NRESET = '0') then + reg_BUSY_IN <= '0'; + reg_BUSY_OUT <= '0'; + else + -- Input Buffer + if (sig_EXECUTE_IN_ACK = '1') then + reg_BUSY_IN <= in_EXECUTE_IN_VAL; + reg_EXECUTE_IN_OOO_ENGINE_ID <= in_EXECUTE_IN_OOO_ENGINE_ID; + reg_EXECUTE_IN_PACKET_ID <= in_EXECUTE_IN_PACKET_ID; + reg_EXECUTE_IN_OPERATION <= in_EXECUTE_IN_OPERATION; + reg_EXECUTE_IN_TYPE <= in_EXECUTE_IN_TYPE; + reg_EXECUTE_IN_DATA_RA <= in_EXECUTE_IN_DATA_RA; + reg_EXECUTE_IN_DATA_RB <= in_EXECUTE_IN_DATA_RB; + reg_EXECUTE_IN_DATA_RC <= in_EXECUTE_IN_DATA_RC; + reg_EXECUTE_IN_HAS_IMMEDIAT <= in_EXECUTE_IN_HAS_IMMEDIAT; + reg_EXECUTE_IN_IMMEDIAT <= in_EXECUTE_IN_IMMEDIAT; + reg_EXECUTE_IN_WRITE_RD <= in_EXECUTE_IN_WRITE_RD; + reg_EXECUTE_IN_NUM_REG_RD <= in_EXECUTE_IN_NUM_REG_RD; + reg_EXECUTE_IN_WRITE_RE <= in_EXECUTE_IN_WRITE_RE; + reg_EXECUTE_IN_NUM_REG_RE <= in_EXECUTE_IN_NUM_REG_RE; + end if; + -- Output Buffer + if (sig_EXECUTE_OUT_UPDATE = '1') then + reg_BUSY_OUT <= reg_BUSY_IN; + reg_EXECUTE_OUT_OOO_ENGINE_ID <= sig_EXECUTE_OUT_OOO_ENGINE_ID; + reg_EXECUTE_OUT_PACKET_ID <= sig_EXECUTE_OUT_PACKET_ID; + reg_EXECUTE_OUT_WRITE_RD <= sig_EXECUTE_OUT_WRITE_RD; + reg_EXECUTE_OUT_NUM_REG_RD <= sig_EXECUTE_OUT_NUM_REG_RD; + reg_EXECUTE_OUT_DATA_RD <= sig_EXECUTE_OUT_DATA_RD; + reg_EXECUTE_OUT_WRITE_RE <= sig_EXECUTE_OUT_WRITE_RE; + reg_EXECUTE_OUT_NUM_REG_RE <= sig_EXECUTE_OUT_NUM_REG_RE; + reg_EXECUTE_OUT_DATA_RE <= sig_EXECUTE_OUT_DATA_RE; + reg_EXECUTE_OUT_EXCEPTION <= sig_EXECUTE_OUT_EXCEPTION; + reg_EXECUTE_OUT_NO_SEQUENCE <= sig_EXECUTE_OUT_NO_SEQUENCE; + reg_EXECUTE_OUT_ADDRESS <= sig_EXECUTE_OUT_ADDRESS; + end if; + end if; + end if; + end process; + + -- + -- ----------------------------------- + -- -- Insides + -- ----------------------------------- + -- + + sig_B_OPERAND <= reg_EXECUTE_IN_IMMEDIAT when (reg_EXECUTE_IN_HAS_IMMEDIAT = '1') else + reg_EXECUTE_IN_DATA_RB; + -- + -- ALU + -- + sig_IS_ARITH <= reg_EXECUTE_IN_OPERATION(0) or reg_EXECUTE_IN_OPERATION(1) or reg_EXECUTE_IN_OPERATION(2); + sig_IS_LOGIC <= reg_EXECUTE_IN_OPERATION(3) or reg_EXECUTE_IN_OPERATION(4) or reg_EXECUTE_IN_OPERATION(5); + sig_CIN_ARITH <= reg_EXECUTE_IN_DATA_RC(1) and reg_EXECUTE_IN_OPERATION(1); + sig_ARITH_B_OPERAND <= ((not sig_B_OPERAND) + 1) when (reg_EXECUTE_IN_OPERATION(2) = '1') else + sig_B_OPERAND; + sig_RES_ARITH <= ('0' & reg_EXECUTE_IN_DATA_RA) + ('0' & sig_ARITH_B_OPERAND) + ("000000000000000000000000000000" & sig_CIN_ARITH); + + sig_A_AND_B <= reg_EXECUTE_IN_DATA_RA and sig_B_OPERAND; + sig_A_OR_B <= reg_EXECUTE_IN_DATA_RA or sig_B_OPERAND; + sig_A_XOR_B <= reg_EXECUTE_IN_DATA_RA xor sig_B_OPERAND; + + with reg_EXECUTE_IN_OPERATION select + sig_RES_LOGIC <= + sig_A_AND_B when "0001000", + sig_A_OR_B when "0010000", + sig_A_XOR_B when "0100000", + "00000000000000000000000000000000" when others; + sig_RES_ALU <= + sig_RES_ARITH (31 downto 0) when (sig_IS_ARITH = '1') else + sig_RES_LOGIC when (sig_IS_LOGIC = '1') else + "00000000000000000000000000000000"; + + -- In ISA l.sub doesn't change carry flag. + sig_COUT_ALU <= (sig_RES_ARITH(32) and (reg_EXECUTE_IN_OPERATION(0) or reg_EXECUTE_IN_OPERATION(1))) or (reg_EXECUTE_IN_OPERATION(2) and reg_EXECUTE_IN_DATA_RC(1)); + sig_OVR_ALU <= ((sig_ARITH_B_OPERAND(31) and reg_EXECUTE_IN_DATA_RA(31) and not sig_RES_ARITH(31)) or (not sig_ARITH_B_OPERAND(31) and not reg_EXECUTE_IN_DATA_RA(31) and sig_RES_ARITH(31))) and sig_IS_ARITH; + + -- + -- MOVE + -- + sig_MOVHI <= reg_EXECUTE_IN_IMMEDIAT(15 downto 0) & "0000000000000000"; + sig_CMOV <= + reg_EXECUTE_IN_DATA_RA when (reg_EXECUTE_IN_DATA_RC(0) = '1') else + reg_EXECUTE_IN_DATA_RB; + sig_RES_MOVE <= + sig_MOVHI when (reg_EXECUTE_IN_OPERATION(0) = '1') else + sig_CMOV when (reg_EXECUTE_IN_OPERATION(1) = '1') else + "00000000000000000000000000000000"; + + -- + -- TEST + -- + sig_IS_LESS <= reg_EXECUTE_IN_OPERATION(3); + sig_A_COMPARE <= + sig_B_OPERAND when (sig_IS_LESS = '1') else + reg_EXECUTE_IN_DATA_RA; + + sig_B_COMPARE <= + reg_EXECUTE_IN_DATA_RA when (sig_IS_LESS = '1') else + sig_B_OPERAND; + + a_gt_b_s : c_compare_v9_0 + generic map ( + c_width => 32, + c_data_type => 0, -- 0 = signed, 1 = unsigned + c_has_a_eq_b => 0, + c_has_a_gt_b => 1) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_gt_b => sig_A_GT_B_S); + + a_gt_b_u : c_compare_v9_0 + generic map ( + c_width => 32, + c_data_type => 1, -- 0 = signed, 1 = unsigned + c_has_a_eq_b => 0, + c_has_a_gt_b => 1) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_gt_b => sig_A_GT_B_U); + + a_eq_b : c_compare_v9_0 + generic map ( -- sign doesn't matter for equality + c_width => 32, + c_has_a_eq_b => 1, + c_has_a_gt_b => 0) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_eq_b => sig_A_EQ_B); + + sig_IS_SIGNED <= reg_EXECUTE_IN_OPERATION(6); + sig_A_GT_B <= + sig_A_GT_B_S when (sig_IS_SIGNED = '1') else + sig_A_GT_B_U; + sig_A_GE_B <= sig_A_GT_B or sig_A_EQ_B; + sig_A_NE_B <= not sig_A_EQ_B; + + sig_FLAG_F <= + (sig_A_EQ_B and reg_EXECUTE_IN_OPERATION(4)) or + (sig_A_NE_B and reg_EXECUTE_IN_OPERATION(5)) or + (sig_A_GE_B and reg_EXECUTE_IN_OPERATION(0)) or + (sig_A_GT_B and reg_EXECUTE_IN_OPERATION(1)); + + + -- + -- BRANCH + -- + sig_NOSQ_BRANCH <= (reg_EXECUTE_IN_DATA_RC(0) and reg_EXECUTE_IN_OPERATION(2)) or (not reg_EXECUTE_IN_DATA_RC(0) and reg_EXECUTE_IN_OPERATION(1)) or reg_EXECUTE_IN_OPERATION(3); + sig_RES_BRANCH <= + reg_EXECUTE_IN_IMMEDIAT(29 downto 0) & "00"when (reg_EXECUTE_IN_OPERATION(3) = '1') else + "00000000000000000000000000000000"; + sig_ADDR_BRANCH <= + reg_EXECUTE_IN_DATA_RB(31 downto 2) when (reg_EXECUTE_IN_OPERATION(3) = '1') else + reg_EXECUTE_IN_IMMEDIAT(29 downto 0); + + -- + -- SHIFTER + -- + -- Instance shifter + instance_Functionnal_unit_0_shifter : Functionnal_unit_0_shifter + port map ( + in_SHIFTER_0_DATA => reg_EXECUTE_IN_DATA_RA + , in_SHIFTER_0_SHIFT => sig_B_OPERAND(4 downto 0) + , in_SHIFTER_0_DIRECTION => reg_EXECUTE_IN_OPERATION(0) + , in_SHIFTER_0_TYPE => reg_EXECUTE_IN_OPERATION(1) + , in_SHIFTER_0_CARRY => reg_EXECUTE_IN_OPERATION(2) + ,out_SHIFTER_0_DATA => sig_RES_SHIFTER + ); + + + -- + -- EXTEND + -- + sig_EXT_BYTE_S <= + "111111111111111111111111" & reg_EXECUTE_IN_DATA_RA (7 downto 0) when (reg_EXECUTE_IN_DATA_RA (7) = '1') else + "000000000000000000000000" & reg_EXECUTE_IN_DATA_RA (7 downto 0); + + sig_EXT_BYTE_Z <= + "000000000000000000000000" & reg_EXECUTE_IN_DATA_RA (7 downto 0); + + sig_EXT_HALF_WORD_S <= + "1111111111111111" & reg_EXECUTE_IN_DATA_RA (15 downto 0) when (reg_EXECUTE_IN_DATA_RA (15) = '1') else + "0000000000000000" & reg_EXECUTE_IN_DATA_RA (15 downto 0); + + sig_EXT_HALF_WORD_Z <= + "0000000000000000" & reg_EXECUTE_IN_DATA_RA (15 downto 0); + + sig_EXT_WORD_S <= + "" & reg_EXECUTE_IN_DATA_RA (31 downto 0) when (reg_EXECUTE_IN_DATA_RA (31) = '1') else + "" & reg_EXECUTE_IN_DATA_RA (31 downto 0); + + sig_EXT_WORD_Z <= + "" & reg_EXECUTE_IN_DATA_RA (31 downto 0); + + sig_EXT_S <= + sig_EXT_BYTE_S when (reg_EXECUTE_IN_IMMEDIAT = 8) else + sig_EXT_HALF_WORD_S when (reg_EXECUTE_IN_IMMEDIAT = 16) else + sig_EXT_WORD_S; + + sig_EXT_Z <= + sig_EXT_BYTE_Z when (reg_EXECUTE_IN_IMMEDIAT = 8) else + sig_EXT_HALF_WORD_Z when (reg_EXECUTE_IN_IMMEDIAT = 16) else + sig_EXT_WORD_Z; + + sig_RES_EXTEND <= + sig_EXT_Z when (reg_EXECUTE_IN_OPERATION(0) = '1') else + sig_EXT_S; + + + -- + -- FIND + -- + sig_FF1 <= + "000001" when (reg_EXECUTE_IN_DATA_RA (0) = '1') else + "000010" when (reg_EXECUTE_IN_DATA_RA (1) = '1') else + "000011" when (reg_EXECUTE_IN_DATA_RA (2) = '1') else + "000100" when (reg_EXECUTE_IN_DATA_RA (3) = '1') else + "000101" when (reg_EXECUTE_IN_DATA_RA (4) = '1') else + "000110" when (reg_EXECUTE_IN_DATA_RA (5) = '1') else + "000111" when (reg_EXECUTE_IN_DATA_RA (6) = '1') else + "001000" when (reg_EXECUTE_IN_DATA_RA (7) = '1') else + "001001" when (reg_EXECUTE_IN_DATA_RA (8) = '1') else + "001010" when (reg_EXECUTE_IN_DATA_RA (9) = '1') else + "001011" when (reg_EXECUTE_IN_DATA_RA (10) = '1') else + "001100" when (reg_EXECUTE_IN_DATA_RA (11) = '1') else + "001101" when (reg_EXECUTE_IN_DATA_RA (12) = '1') else + "001110" when (reg_EXECUTE_IN_DATA_RA (13) = '1') else + "001111" when (reg_EXECUTE_IN_DATA_RA (14) = '1') else + "010000" when (reg_EXECUTE_IN_DATA_RA (15) = '1') else + "010001" when (reg_EXECUTE_IN_DATA_RA (16) = '1') else + "010010" when (reg_EXECUTE_IN_DATA_RA (17) = '1') else + "010011" when (reg_EXECUTE_IN_DATA_RA (18) = '1') else + "010100" when (reg_EXECUTE_IN_DATA_RA (19) = '1') else + "010101" when (reg_EXECUTE_IN_DATA_RA (20) = '1') else + "010110" when (reg_EXECUTE_IN_DATA_RA (21) = '1') else + "010111" when (reg_EXECUTE_IN_DATA_RA (22) = '1') else + "011000" when (reg_EXECUTE_IN_DATA_RA (23) = '1') else + "011001" when (reg_EXECUTE_IN_DATA_RA (24) = '1') else + "011010" when (reg_EXECUTE_IN_DATA_RA (25) = '1') else + "011011" when (reg_EXECUTE_IN_DATA_RA (26) = '1') else + "011100" when (reg_EXECUTE_IN_DATA_RA (27) = '1') else + "011101" when (reg_EXECUTE_IN_DATA_RA (28) = '1') else + "011110" when (reg_EXECUTE_IN_DATA_RA (29) = '1') else + "011111" when (reg_EXECUTE_IN_DATA_RA (30) = '1') else + "100000" when (reg_EXECUTE_IN_DATA_RA (31) = '1') else + "000000"; + + sig_FL1 <= + "100000" when (reg_EXECUTE_IN_DATA_RA (31) = '1') else + "011111" when (reg_EXECUTE_IN_DATA_RA (30) = '1') else + "011110" when (reg_EXECUTE_IN_DATA_RA (29) = '1') else + "011101" when (reg_EXECUTE_IN_DATA_RA (28) = '1') else + "011100" when (reg_EXECUTE_IN_DATA_RA (27) = '1') else + "011011" when (reg_EXECUTE_IN_DATA_RA (26) = '1') else + "011010" when (reg_EXECUTE_IN_DATA_RA (25) = '1') else + "011001" when (reg_EXECUTE_IN_DATA_RA (24) = '1') else + "011000" when (reg_EXECUTE_IN_DATA_RA (23) = '1') else + "010111" when (reg_EXECUTE_IN_DATA_RA (22) = '1') else + "010110" when (reg_EXECUTE_IN_DATA_RA (21) = '1') else + "010101" when (reg_EXECUTE_IN_DATA_RA (20) = '1') else + "010100" when (reg_EXECUTE_IN_DATA_RA (19) = '1') else + "010011" when (reg_EXECUTE_IN_DATA_RA (18) = '1') else + "010010" when (reg_EXECUTE_IN_DATA_RA (17) = '1') else + "010001" when (reg_EXECUTE_IN_DATA_RA (16) = '1') else + "010000" when (reg_EXECUTE_IN_DATA_RA (15) = '1') else + "001111" when (reg_EXECUTE_IN_DATA_RA (14) = '1') else + "001110" when (reg_EXECUTE_IN_DATA_RA (13) = '1') else + "001101" when (reg_EXECUTE_IN_DATA_RA (12) = '1') else + "001100" when (reg_EXECUTE_IN_DATA_RA (11) = '1') else + "001011" when (reg_EXECUTE_IN_DATA_RA (10) = '1') else + "001010" when (reg_EXECUTE_IN_DATA_RA (9) = '1') else + "001001" when (reg_EXECUTE_IN_DATA_RA (8) = '1') else + "001000" when (reg_EXECUTE_IN_DATA_RA (7) = '1') else + "000111" when (reg_EXECUTE_IN_DATA_RA (6) = '1') else + "000110" when (reg_EXECUTE_IN_DATA_RA (5) = '1') else + "000101" when (reg_EXECUTE_IN_DATA_RA (4) = '1') else + "000100" when (reg_EXECUTE_IN_DATA_RA (3) = '1') else + "000011" when (reg_EXECUTE_IN_DATA_RA (2) = '1') else + "000010" when (reg_EXECUTE_IN_DATA_RA (1) = '1') else + "000001" when (reg_EXECUTE_IN_DATA_RA (0) = '1') else + "000000"; + + sig_RES_FIND <= + "00000000000000000000000000"&sig_FF1 when (reg_EXECUTE_IN_OPERATION(0) = '1') else + "00000000000000000000000000"&sig_FL1; + + + -- + -- SPECIAL + -- + sig_SPR_IS_HERE <= + '1' when (sig_A_OR_B(15 downto 0) = "00101") else + '0'; + -- MFSPR + sig_MFSPR <= + reg_MACLO(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000001") else + reg_MACHI(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000010") else + "00000000000000000000000000000000"; + + + -- MTSPR + process (in_CLOCK) + begin + if in_CLOCK'event and in_CLOCK = '1' then + if (sig_SPR_IS_HERE = '1') then + if (sig_A_OR_B(10 downto 0) = "00000000001") then + reg_MACLO(0) <= reg_EXECUTE_IN_DATA_RB; + end if; + if (sig_A_OR_B(10 downto 0) = "00000000010") then + reg_MACHI(0) <= reg_EXECUTE_IN_DATA_RB; + end if; + end if; + end if; + end process; + + sig_RES_SPECIAL <= + sig_MFSPR when (reg_EXECUTE_IN_OPERATION = "0000001") else + reg_EXECUTE_IN_DATA_RB when (reg_EXECUTE_IN_OPERATION = "0000010") else + "00000000000000000000000000000000"; + + + -- + -- TRANSACTION + -- + sig_EXECUTE_OUT_VAL <= reg_BUSY_OUT; + sig_EXECUTE_OUT_UPDATE <= not reg_BUSY_OUT or (in_EXECUTE_OUT_ACK); +-- sig_EXECUTE_OUT_UPDATE <= not reg_BUSY_OUT or (reg_BUSY_OUT and in_EXECUTE_OUT_ACK); + sig_EXECUTE_IN_ACK <= not reg_BUSY_IN or (reg_BUSY_IN and sig_EXECUTE_OUT_UPDATE); + + -- + -- ----------------------------------- + -- -- + -- ----------------------------------- + -- + + sig_EXECUTE_OUT_OOO_ENGINE_ID <= reg_EXECUTE_IN_OOO_ENGINE_ID; + sig_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_IN_PACKET_ID; + sig_EXECUTE_OUT_WRITE_RD <= reg_EXECUTE_IN_WRITE_RD; + sig_EXECUTE_OUT_NUM_REG_RD <= reg_EXECUTE_IN_NUM_REG_RD; + with reg_EXECUTE_IN_TYPE select + sig_EXECUTE_OUT_DATA_RD <= + sig_RES_ALU when "00000", + sig_RES_MOVE when "00010", + sig_RES_BRANCH when "01010", + sig_RES_SHIFTER when "00001", + sig_RES_EXTEND when "00110", + sig_RES_FIND when "00111", + sig_RES_SPECIAL when "01000", + "00000000000000000000000000000000" when others; + sig_EXECUTE_OUT_WRITE_RE <= reg_EXECUTE_IN_WRITE_RE; + sig_EXECUTE_OUT_NUM_REG_RE <= reg_EXECUTE_IN_NUM_REG_RE; + with reg_EXECUTE_IN_TYPE select + sig_EXECUTE_OUT_DATA_RE <= + sig_COUT_ALU & sig_OVR_ALU when "00000", + '0' & sig_FLAG_F when "00011", + "00" when others; + sig_EXECUTE_OUT_EXCEPTION <= + "01011" when (reg_EXECUTE_IN_TYPE = "00000" and sig_OVR_ALU = '1') else + "10011" when (reg_EXECUTE_IN_TYPE = "01000" and reg_EXECUTE_IN_OPERATION = "0000001" and sig_SPR_IS_HERE = '0') else + "10100" when (reg_EXECUTE_IN_TYPE = "01000" and reg_EXECUTE_IN_OPERATION = "0000010" and sig_SPR_IS_HERE = '0') else + "00000"; + with reg_EXECUTE_IN_TYPE select + sig_EXECUTE_OUT_NO_SEQUENCE <= + sig_NOSQ_BRANCH when "01010", + '0'when others; + with reg_EXECUTE_IN_TYPE select + sig_EXECUTE_OUT_ADDRESS <= + sig_ADDR_BRANCH when "01010", + sig_A_OR_B(29 downto 0) when "01000", + "000000000000000000000000000000" when others; + + -- + -- ----------------------------------- + -- -- Outputs + -- ----------------------------------- + -- + + out_EXECUTE_OUT_OOO_ENGINE_ID <= reg_EXECUTE_OUT_OOO_ENGINE_ID; + out_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_OUT_PACKET_ID; + out_EXECUTE_OUT_WRITE_RD <= reg_EXECUTE_OUT_WRITE_RD; + out_EXECUTE_OUT_NUM_REG_RD <= reg_EXECUTE_OUT_NUM_REG_RD; + out_EXECUTE_OUT_DATA_RD <= reg_EXECUTE_OUT_DATA_RD; + out_EXECUTE_OUT_WRITE_RE <= reg_EXECUTE_OUT_WRITE_RE; + out_EXECUTE_OUT_NUM_REG_RE <= reg_EXECUTE_OUT_NUM_REG_RE; + out_EXECUTE_OUT_DATA_RE <= reg_EXECUTE_OUT_DATA_RE; + out_EXECUTE_OUT_EXCEPTION <= reg_EXECUTE_OUT_EXCEPTION; + out_EXECUTE_OUT_NO_SEQUENCE <= reg_EXECUTE_OUT_NO_SEQUENCE; + out_EXECUTE_OUT_ADDRESS <= reg_EXECUTE_OUT_ADDRESS; + out_EXECUTE_OUT_VAL <= sig_EXECUTE_OUT_VAL; + out_EXECUTE_IN_ACK <= sig_EXECUTE_IN_ACK; + +end behavioural; + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0_07_04_09.vhdl =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0_07_04_09.vhdl (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0_07_04_09.vhdl (revision 116) @@ -0,0 +1,822 @@ +------------------------------------------------------------------------------- +-- File : ./Functionnal_unit_0.vhdl +-- Date : Fri Mar 13 16:20:01 2009 +-- Version : 0.2.111 - Castor +-- Comment : it's a autogenerated file, don't modify +------------------------------------------------------------------------------- + + +library ieee; + use ieee.numeric_bit.all; + use ieee.numeric_std.all; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_misc.all; +--use ieee.std_logic_signed.all; + use ieee.std_logic_unsigned.all; +--use ieee.std_logic_textio.all; + + +library work; +use work.Functionnal_unit_0_Pack.all; +use work.Functionnal_unit_0_shifter_Pack.all; + +Library XilinxCoreLib; +use XilinxCoreLib.c_compare_v9_0_comp.all; +use XilinxCoreLib.mult_gen_v9_0_comp.all; + +entity Functionnal_unit_0 is + port ( + in_CLOCK : in std_logic; + in_NRESET : in std_logic; + in_EXECUTE_IN_VAL : in std_logic; + out_EXECUTE_IN_ACK : out std_logic; + in_EXECUTE_IN_OOO_ENGINE_ID : in std_logic; + in_EXECUTE_IN_PACKET_ID : in std_logic_vector(7 downto 0); + in_EXECUTE_IN_OPERATION : in std_logic_vector(6 downto 0); + in_EXECUTE_IN_TYPE : in std_logic_vector(4 downto 0); + in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE : in std_logic_vector(1 downto 0); + in_EXECUTE_IN_HAS_IMMEDIAT : in std_logic; + in_EXECUTE_IN_IMMEDIAT : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RA : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RB : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RC : in std_logic_vector(1 downto 0); + in_EXECUTE_IN_WRITE_RD : in std_logic; + in_EXECUTE_IN_NUM_REG_RD : in std_logic_vector(4 downto 0); + in_EXECUTE_IN_WRITE_RE : in std_logic; + in_EXECUTE_IN_NUM_REG_RE : in std_logic_vector(3 downto 0); + out_EXECUTE_OUT_VAL : out std_logic; + in_EXECUTE_OUT_ACK : in std_logic; + out_EXECUTE_OUT_OOO_ENGINE_ID : out std_logic; + out_EXECUTE_OUT_PACKET_ID : out std_logic_vector(7 downto 0); + out_EXECUTE_OUT_WRITE_RD : out std_logic; + out_EXECUTE_OUT_NUM_REG_RD : out std_logic_vector(4 downto 0); + out_EXECUTE_OUT_DATA_RD : out std_logic_vector(31 downto 0); + out_EXECUTE_OUT_WRITE_RE : out std_logic; + out_EXECUTE_OUT_NUM_REG_RE : out std_logic_vector(3 downto 0); + out_EXECUTE_OUT_DATA_RE : out std_logic_vector(1 downto 0); + out_EXECUTE_OUT_EXCEPTION : out std_logic_vector(4 downto 0); + out_EXECUTE_OUT_NO_SEQUENCE : out std_logic; + out_EXECUTE_OUT_ADDRESS : out std_logic_vector(29 downto 0) + ); +end Functionnal_unit_0; + +architecture behavioural of Functionnal_unit_0 is + type Tmac is array (1 downto 0) of std_logic_vector(31 downto 0); + + signal sig_EXECUTE_IN_ACK : std_logic; + signal reg_EXECUTE_IN_VAL : std_logic; + signal reg_EXECUTE_IN_OOO_ENGINE_ID : std_logic; + signal reg_EXECUTE_IN_PACKET_ID : std_logic_vector(7 downto 0); + signal reg_EXECUTE_IN_OPERATION : std_logic_vector(6 downto 0); + signal reg_EXECUTE_IN_TYPE : std_logic_vector(4 downto 0); + signal reg_EXECUTE_IN_HAS_IMMEDIAT : std_logic; + signal reg_EXECUTE_IN_IMMEDIAT : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RA : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RB : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RC : std_logic_vector(1 downto 0); + signal reg_EXECUTE_IN_WRITE_RD : std_logic; + signal reg_EXECUTE_IN_NUM_REG_RD : std_logic_vector(4 downto 0); + signal reg_EXECUTE_IN_WRITE_RE : std_logic; + signal reg_EXECUTE_IN_NUM_REG_RE : std_logic_vector(3 downto 0); + signal sig_B_OPERAND : std_logic_vector(31 downto 0); + signal sig_IS_ARITH : std_logic; + signal sig_IS_LOGIC : std_logic; + signal sig_CIN_ARITH : std_logic; + signal sig_ARITH_B_OPERAND : std_logic_vector(31 downto 0); + signal sig_RES_ARITH : std_logic_vector(32 downto 0); + signal sig_A_AND_B : std_logic_vector(31 downto 0); + signal sig_A_OR_B : std_logic_vector(31 downto 0); + signal sig_A_XOR_B : std_logic_vector(31 downto 0); + signal sig_RES_LOGIC : std_logic_vector(31 downto 0); + signal sig_RES_ALU : std_logic_vector(31 downto 0); + signal sig_OVR_ALU : std_logic; + signal sig_COUT_ALU : std_logic; + signal sig_RES_MOVE : std_logic_vector(31 downto 0); + signal sig_CMOV : std_logic_vector(31 downto 0); + signal sig_MOVHI : std_logic_vector(31 downto 0); + signal sig_RES_BRANCH : std_logic_vector(31 downto 0); + signal sig_ADDR_BRANCH : std_logic_vector(29 downto 0); + signal sig_NOSQ_BRANCH : std_logic; + signal sig_RES_SHIFTER : std_logic_vector(31 downto 0); + signal sig_EXT_BYTE_S : std_logic_vector(31 downto 0); + signal sig_EXT_BYTE_Z : std_logic_vector(31 downto 0); + signal sig_EXT_HALF_WORD_S : std_logic_vector(31 downto 0); + signal sig_EXT_HALF_WORD_Z : std_logic_vector(31 downto 0); + signal sig_EXT_WORD_S : std_logic_vector(31 downto 0); + signal sig_EXT_WORD_Z : std_logic_vector(31 downto 0); + signal sig_EXT_S : std_logic_vector(31 downto 0); + signal sig_EXT_Z : std_logic_vector(31 downto 0); + signal sig_RES_EXTEND : std_logic_vector(31 downto 0); + signal sig_FF1 : std_logic_vector(5 downto 0); + signal sig_FL1 : std_logic_vector(5 downto 0); + signal sig_RES_FIND : std_logic_vector(31 downto 0); + signal sig_SPR_IS_HERE : std_logic; + signal sig_MFSPR : std_logic_vector(31 downto 0); + signal sig_MTSPR : std_logic_vector(31 downto 0); + signal sig_RES_SPECIAL : std_logic_vector(31 downto 0); + signal sig_EXECUTE_OUT_VAL : std_logic; + signal sig_UPDATE : std_logic; + signal reg_EXECUTE_OUT_VAL : std_logic; + signal reg_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; + signal sig_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; + signal reg_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); + signal sig_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); + signal reg_EXECUTE_OUT_WRITE_RD : std_logic; + signal sig_EXECUTE_OUT_WRITE_RD : std_logic; + signal reg_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); + signal sig_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); + signal reg_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); + signal sig_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); + signal reg_EXECUTE_OUT_WRITE_RE : std_logic; + signal sig_EXECUTE_OUT_WRITE_RE : std_logic; + signal reg_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); + signal sig_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); + signal reg_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); + signal sig_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); + signal reg_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); + signal sig_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); + signal reg_EXECUTE_OUT_NO_SEQUENCE : std_logic; + signal sig_EXECUTE_OUT_NO_SEQUENCE : std_logic; + signal reg_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); + signal sig_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); + signal reg_MACLO : Tmac; + signal reg_MACHI : Tmac; + + signal sig_VAL_5 : std_logic; + signal sig_VAL_0 : std_logic; + signal sig_NUM_REG_RE_0 : std_logic_vector(3 downto 0); + signal sig_WRITE_RE_0 : std_logic; + signal sig_NUM_REG_RD_0 : std_logic_vector(4 downto 0); + signal sig_WRITE_RD_0 : std_logic; + signal sig_TYPE_0 : std_logic_vector(4 downto 0); + signal sig_PACKET_ID_0 : std_logic_vector(7 downto 0); + signal sig_OOO_ENGINE_ID_0 : std_logic; + + signal sig_IS_LESS : std_logic; + signal sig_A_COMPARE : std_logic_vector(31 downto 0); + signal sig_B_COMPARE : std_logic_vector(31 downto 0); + signal sig_A_GT_B_S : std_logic; + signal sig_A_GT_B_U : std_logic; + signal sig_A_EQ_B : std_logic; + signal sig_A_GT_B : std_logic; + signal sig_A_GE_B : std_logic; + signal sig_A_NE_B : std_logic; + signal sig_IS_SIGNED : std_logic; + signal sig_FLAG_F : std_logic; + signal sig_BUSY : std_logic; + + signal sig_FULL_RES_MUL : std_logic_vector (63 downto 0); + signal sig_FULL_RES_MULU : std_logic_vector (63 downto 0); + signal sig_FULL_RES_MULS : std_logic_vector (63 downto 0); + signal sig_RES_MUL : std_logic_vector (31 downto 0); + signal sig_COUT_MUL : std_logic; + signal sig_OVR_MUL : std_logic; + + + type TFQUEUE is array (6 downto 0) of std_logic_vector(25 downto 0); + -- OOO_ENGINE_ID(1) + PACKET_ID(8) + TYPE(5) + WRITE_RD(1) + + -- NUM_REG_RD(5) + WRITE_RE(1) + NUM_REG_RE(4) + VALID(1) = 26 BITS + signal reg_FUNCTIONAL_QUEUE : TFQUEUE; + + + alias reg_OOO_ENGINE_ID_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(25); + alias reg_PACKET_ID_6 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(6)(24 downto 17); + alias reg_TYPE_6 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(6)(16 downto 12); + alias reg_WRITE_RD_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(11); + alias reg_NUM_REG_RD_6 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(6)(10 downto 6); + alias reg_WRITE_RE_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(5); + alias reg_NUM_REG_RE_6 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(6)(4 downto 1); + alias reg_VAL_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(0); + + alias reg_OOO_ENGINE_ID_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(25); + alias reg_OOO_ENGINE_ID_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(25); + alias reg_OOO_ENGINE_ID_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(25); + alias reg_OOO_ENGINE_ID_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(25); + alias reg_OOO_ENGINE_ID_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(25); + alias reg_OOO_ENGINE_ID_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(25); + alias reg_PACKET_ID_5 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(5)(24 downto 17); + alias reg_PACKET_ID_4 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(4)(24 downto 17); + alias reg_PACKET_ID_3 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(3)(24 downto 17); + alias reg_PACKET_ID_2 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(2)(24 downto 17); + alias reg_PACKET_ID_1 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(1)(24 downto 17); + alias reg_PACKET_ID_0 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(0)(24 downto 17); + alias reg_TYPE_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(16 downto 12); + alias reg_TYPE_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(16 downto 12); + alias reg_TYPE_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(16 downto 12); + alias reg_TYPE_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(16 downto 12); + alias reg_TYPE_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(16 downto 12); + alias reg_TYPE_0 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(0)(16 downto 12); + alias reg_WRITE_RD_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(11); + alias reg_WRITE_RD_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(11); + alias reg_WRITE_RD_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(11); + alias reg_WRITE_RD_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(11); + alias reg_WRITE_RD_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(11); + alias reg_WRITE_RD_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(11); + alias reg_NUM_REG_RD_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(10 downto 6); + alias reg_NUM_REG_RD_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(10 downto 6); + alias reg_NUM_REG_RD_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(10 downto 6); + alias reg_NUM_REG_RD_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(10 downto 6); + alias reg_NUM_REG_RD_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(10 downto 6); + alias reg_NUM_REG_RD_0 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(0)(10 downto 6); + alias reg_WRITE_RE_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(5); + alias reg_WRITE_RE_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(5); + alias reg_WRITE_RE_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(5); + alias reg_WRITE_RE_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(5); + alias reg_WRITE_RE_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(5); + alias reg_WRITE_RE_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(5); + alias reg_NUM_REG_RE_5 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(5)(4 downto 1); + alias reg_NUM_REG_RE_4 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(4)(4 downto 1); + alias reg_NUM_REG_RE_3 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(3)(4 downto 1); + alias reg_NUM_REG_RE_2 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(2)(4 downto 1); + alias reg_NUM_REG_RE_1 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(1)(4 downto 1); + alias reg_NUM_REG_RE_0 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(0)(4 downto 1); + alias reg_VAL_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(0); + alias reg_VAL_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(0); + alias reg_VAL_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(0); + alias reg_VAL_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(0); + alias reg_VAL_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(0); + alias reg_VAL_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(0); + +begin + + -- + -- ----------------------------------- + -- -- Registers + -- ----------------------------------- + -- + + process (in_CLOCK) + begin + if in_CLOCK'event and in_CLOCK = '1' then + if (in_NRESET = '0') then + reg_EXECUTE_IN_VAL <= '0'; + reg_EXECUTE_OUT_VAL <= '0'; + reg_FUNCTIONAL_QUEUE(0) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(1) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(2) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(3) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(4) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(5) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(6) <= (others => '0'); + else + -- Input + if (sig_EXECUTE_IN_ACK = '1') then + reg_EXECUTE_IN_VAL <= in_EXECUTE_IN_VAL; + reg_EXECUTE_IN_NUM_REG_RE <= in_EXECUTE_IN_NUM_REG_RE; + reg_EXECUTE_IN_WRITE_RE <= in_EXECUTE_IN_WRITE_RE; + reg_EXECUTE_IN_NUM_REG_RD <= in_EXECUTE_IN_NUM_REG_RD; + reg_EXECUTE_IN_WRITE_RD <= in_EXECUTE_IN_WRITE_RD; + reg_EXECUTE_IN_DATA_RC <= in_EXECUTE_IN_DATA_RC; + reg_EXECUTE_IN_DATA_RB <= in_EXECUTE_IN_DATA_RB; + reg_EXECUTE_IN_DATA_RA <= in_EXECUTE_IN_DATA_RA; + reg_EXECUTE_IN_IMMEDIAT <= in_EXECUTE_IN_IMMEDIAT; + reg_EXECUTE_IN_HAS_IMMEDIAT <= in_EXECUTE_IN_HAS_IMMEDIAT; + reg_EXECUTE_IN_TYPE <= in_EXECUTE_IN_TYPE; + reg_EXECUTE_IN_OPERATION <= in_EXECUTE_IN_OPERATION; + reg_EXECUTE_IN_PACKET_ID <= in_EXECUTE_IN_PACKET_ID; + reg_EXECUTE_IN_OOO_ENGINE_ID <= in_EXECUTE_IN_OOO_ENGINE_ID; + + reg_NUM_REG_RE_6 <= in_EXECUTE_IN_NUM_REG_RE; + reg_WRITE_RE_6 <= in_EXECUTE_IN_WRITE_RE; + reg_NUM_REG_RD_6 <= in_EXECUTE_IN_NUM_REG_RD; + reg_WRITE_RD_6 <= in_EXECUTE_IN_WRITE_RD; + reg_TYPE_6 <= in_EXECUTE_IN_TYPE; + reg_PACKET_ID_6 <= in_EXECUTE_IN_PACKET_ID; + reg_OOO_ENGINE_ID_6 <= in_EXECUTE_IN_OOO_ENGINE_ID; + + -- Pipeline + if (in_EXECUTE_IN_TYPE = "00100") then + reg_VAL_0 <= reg_VAL_1; + reg_NUM_REG_RE_0 <= reg_NUM_REG_RE_1; + reg_WRITE_RE_0 <= reg_WRITE_RE_1; + reg_NUM_REG_RD_0 <= reg_NUM_REG_RD_1; + reg_WRITE_RD_0 <= reg_WRITE_RD_1; + reg_TYPE_0 <= reg_TYPE_1; + reg_PACKET_ID_0 <= reg_PACKET_ID_1; + reg_OOO_ENGINE_ID_0 <= reg_OOO_ENGINE_ID_1; + + reg_VAL_6 <= in_EXECUTE_IN_VAL; + + else + reg_VAL_0 <= in_EXECUTE_IN_VAL; + reg_NUM_REG_RE_0 <= in_EXECUTE_IN_NUM_REG_RE; + reg_WRITE_RE_0 <= in_EXECUTE_IN_WRITE_RE; + reg_NUM_REG_RD_0 <= in_EXECUTE_IN_NUM_REG_RD; + reg_WRITE_RD_0 <= in_EXECUTE_IN_WRITE_RD; + reg_TYPE_0 <= in_EXECUTE_IN_TYPE; + reg_PACKET_ID_0 <= in_EXECUTE_IN_PACKET_ID; + reg_OOO_ENGINE_ID_0 <= in_EXECUTE_IN_OOO_ENGINE_ID; + + reg_VAL_6 <= '0'; + + end if; + end if; + if (sig_UPDATE = '1') then + + reg_VAL_1 <= reg_VAL_2; + reg_NUM_REG_RE_1 <= reg_NUM_REG_RE_2; + reg_WRITE_RE_1 <= reg_WRITE_RE_2; + reg_NUM_REG_RD_1 <= reg_NUM_REG_RD_2; + reg_WRITE_RD_1 <= reg_WRITE_RD_2; + reg_TYPE_1 <= reg_TYPE_2; + reg_PACKET_ID_1 <= reg_PACKET_ID_2; + reg_OOO_ENGINE_ID_1 <= reg_OOO_ENGINE_ID_2; + + reg_VAL_2 <= reg_VAL_3; + reg_NUM_REG_RE_2 <= reg_NUM_REG_RE_3; + reg_WRITE_RE_2 <= reg_WRITE_RE_3; + reg_NUM_REG_RD_2 <= reg_NUM_REG_RD_3; + reg_WRITE_RD_2 <= reg_WRITE_RD_3; + reg_TYPE_2 <= reg_TYPE_3; + reg_PACKET_ID_2 <= reg_PACKET_ID_3; + reg_OOO_ENGINE_ID_2 <= reg_OOO_ENGINE_ID_3; + + reg_VAL_3 <= reg_VAL_4; + reg_NUM_REG_RE_3 <= reg_NUM_REG_RE_4; + reg_WRITE_RE_3 <= reg_WRITE_RE_4; + reg_NUM_REG_RD_3 <= reg_NUM_REG_RD_4; + reg_WRITE_RD_3 <= reg_WRITE_RD_4; + reg_TYPE_3 <= reg_TYPE_4; + reg_PACKET_ID_3 <= reg_PACKET_ID_4; + reg_OOO_ENGINE_ID_3 <= reg_OOO_ENGINE_ID_4; + + reg_VAL_4 <= reg_VAL_5; + reg_NUM_REG_RE_4 <= reg_NUM_REG_RE_5; + reg_WRITE_RE_4 <= reg_WRITE_RE_5; + reg_NUM_REG_RD_4 <= reg_NUM_REG_RD_5; + reg_WRITE_RD_4 <= reg_WRITE_RD_5; + reg_TYPE_4 <= reg_TYPE_5; + reg_PACKET_ID_4 <= reg_PACKET_ID_5; + reg_OOO_ENGINE_ID_4 <= reg_OOO_ENGINE_ID_5; + + reg_VAL_5 <= reg_VAL_6; + reg_NUM_REG_RE_5 <= reg_NUM_REG_RE_6; + reg_WRITE_RE_5 <= reg_WRITE_RE_6; + reg_NUM_REG_RD_5 <= reg_NUM_REG_RD_6; + reg_WRITE_RD_5 <= reg_WRITE_RD_6; + reg_TYPE_5 <= reg_TYPE_6; + reg_PACKET_ID_5 <= reg_PACKET_ID_6; + reg_OOO_ENGINE_ID_5 <= reg_OOO_ENGINE_ID_6; + + -- Output + reg_EXECUTE_OUT_VAL <= reg_VAL_0; + reg_EXECUTE_OUT_OOO_ENGINE_ID <= sig_EXECUTE_OUT_OOO_ENGINE_ID; + reg_EXECUTE_OUT_PACKET_ID <= sig_EXECUTE_OUT_PACKET_ID; + reg_EXECUTE_OUT_WRITE_RD <= sig_EXECUTE_OUT_WRITE_RD; + reg_EXECUTE_OUT_NUM_REG_RD <= sig_EXECUTE_OUT_NUM_REG_RD; + reg_EXECUTE_OUT_DATA_RD <= sig_EXECUTE_OUT_DATA_RD; + reg_EXECUTE_OUT_WRITE_RE <= sig_EXECUTE_OUT_WRITE_RE; + reg_EXECUTE_OUT_NUM_REG_RE <= sig_EXECUTE_OUT_NUM_REG_RE; + reg_EXECUTE_OUT_DATA_RE <= sig_EXECUTE_OUT_DATA_RE; + reg_EXECUTE_OUT_EXCEPTION <= sig_EXECUTE_OUT_EXCEPTION; + reg_EXECUTE_OUT_NO_SEQUENCE <= sig_EXECUTE_OUT_NO_SEQUENCE; + reg_EXECUTE_OUT_ADDRESS <= sig_EXECUTE_OUT_ADDRESS; + end if; + end if; + end if; + end process; + + -- + -- ----------------------------------- + -- -- Insides + -- ----------------------------------- + -- + +-- sig_VAL_0 <= in_EXECUTE_IN_VAL when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_VAL_1; +-- sig_NUM_REG_RE_0 <= in_EXECUTE_IN_NUM_REG_RE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_NUM_REG_RE_1; +-- sig_WRITE_RE_0 <= in_EXECUTE_IN_WRITE_RE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_WRITE_RE_1; +-- sig_NUM_REG_RD_0 <= in_EXECUTE_IN_NUM_REG_RD when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_NUM_REG_RD_1; +-- sig_WRITE_RD_0 <= in_EXECUTE_IN_WRITE_RD when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_WRITE_RD_1; +-- sig_TYPE_0 <= in_EXECUTE_IN_TYPE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_TYPE_1; +-- sig_PACKET_ID_0 <= in_EXECUTE_IN_PACKET_ID when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_PACKET_ID_1; +-- sig_OOO_ENGINE_ID_0 <= in_EXECUTE_IN_OOO_ENGINE_ID when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_OOO_ENGINE_ID_1; + +-- sig_VAL_5 <= reg_EXECUTE_IN_VAL when (reg_EXECUTE_IN_TYPE = "00100") else +-- '0'; + + sig_B_OPERAND <= reg_EXECUTE_IN_IMMEDIAT when (reg_EXECUTE_IN_HAS_IMMEDIAT = '1') else + reg_EXECUTE_IN_DATA_RB; + -- + -- ALU + -- + sig_IS_ARITH <= reg_EXECUTE_IN_OPERATION(0) or reg_EXECUTE_IN_OPERATION(1) or reg_EXECUTE_IN_OPERATION(2); + sig_IS_LOGIC <= reg_EXECUTE_IN_OPERATION(3) or reg_EXECUTE_IN_OPERATION(4) or reg_EXECUTE_IN_OPERATION(5); + sig_CIN_ARITH <= reg_EXECUTE_IN_DATA_RC(1) and reg_EXECUTE_IN_OPERATION(1); + sig_ARITH_B_OPERAND <= ((not sig_B_OPERAND) + 1) when (reg_EXECUTE_IN_OPERATION(2) = '1') else + sig_B_OPERAND; + sig_RES_ARITH <= ('0' & reg_EXECUTE_IN_DATA_RA) + ('0' & sig_ARITH_B_OPERAND) + ("000000000000000000000000000000" & sig_CIN_ARITH); + + sig_A_AND_B <= reg_EXECUTE_IN_DATA_RA and sig_B_OPERAND; + sig_A_OR_B <= reg_EXECUTE_IN_DATA_RA or sig_B_OPERAND; + sig_A_XOR_B <= reg_EXECUTE_IN_DATA_RA xor sig_B_OPERAND; + + with reg_EXECUTE_IN_OPERATION select + sig_RES_LOGIC <= + sig_A_AND_B when "0001000", + sig_A_OR_B when "0010000", + sig_A_XOR_B when "0100000", + "00000000000000000000000000000000" when others; + sig_RES_ALU <= + sig_RES_ARITH (31 downto 0) when (sig_IS_ARITH = '1') else + sig_RES_LOGIC when (sig_IS_LOGIC = '1') else + "00000000000000000000000000000000"; + + -- In ISA l.sub doesn't change carry flag. + sig_COUT_ALU <= (sig_RES_ARITH(32) and (reg_EXECUTE_IN_OPERATION(0) or reg_EXECUTE_IN_OPERATION(1))) or (reg_EXECUTE_IN_OPERATION(2) and reg_EXECUTE_IN_DATA_RC(1)); + sig_OVR_ALU <= ((sig_ARITH_B_OPERAND(31) and reg_EXECUTE_IN_DATA_RA(31) and not sig_RES_ARITH(31)) or (not sig_ARITH_B_OPERAND(31) and not reg_EXECUTE_IN_DATA_RA(31) and sig_RES_ARITH(31))) and sig_IS_ARITH; + + -- + -- MOVE + -- + sig_MOVHI <= reg_EXECUTE_IN_IMMEDIAT(15 downto 0) & "0000000000000000"; + sig_CMOV <= + reg_EXECUTE_IN_DATA_RA when (reg_EXECUTE_IN_DATA_RC(0) = '1') else + reg_EXECUTE_IN_DATA_RB; + sig_RES_MOVE <= + sig_MOVHI when (reg_EXECUTE_IN_OPERATION(0) = '1') else + sig_CMOV when (reg_EXECUTE_IN_OPERATION(1) = '1') else + "00000000000000000000000000000000"; + + -- + -- TEST + -- + sig_IS_LESS <= reg_EXECUTE_IN_OPERATION(3); + sig_A_COMPARE <= + sig_B_OPERAND when (sig_IS_LESS = '1') else + reg_EXECUTE_IN_DATA_RA; + + sig_B_COMPARE <= + reg_EXECUTE_IN_DATA_RA when (sig_IS_LESS = '1') else + sig_B_OPERAND; + + a_gt_b_s : c_compare_v9_0 + generic map ( + c_width => 32, + c_data_type => 0, -- 0 = signed, 1 = unsigned + c_has_a_eq_b => 0, + c_has_a_gt_b => 1) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_gt_b => sig_A_GT_B_S); + + a_gt_b_u : c_compare_v9_0 + generic map ( + c_width => 32, + c_data_type => 1, -- 0 = signed, 1 = unsigned + c_has_a_eq_b => 0, + c_has_a_gt_b => 1) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_gt_b => sig_A_GT_B_U); + + a_eq_b : c_compare_v9_0 + generic map ( -- sign doesn't matter for + -- equality test + c_width => 32, + c_has_a_eq_b => 1, + c_has_a_gt_b => 0) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_eq_b => sig_A_EQ_B); + + sig_IS_SIGNED <= reg_EXECUTE_IN_OPERATION(6); + sig_A_GT_B <= + sig_A_GT_B_S when (sig_IS_SIGNED = '1') else + sig_A_GT_B_U; + sig_A_GE_B <= sig_A_GT_B or sig_A_EQ_B; + sig_A_NE_B <= not sig_A_EQ_B; + + sig_FLAG_F <= + (sig_A_EQ_B and reg_EXECUTE_IN_OPERATION(4)) or + (sig_A_NE_B and reg_EXECUTE_IN_OPERATION(5)) or + (sig_A_GE_B and reg_EXECUTE_IN_OPERATION(0)) or + (sig_A_GT_B and reg_EXECUTE_IN_OPERATION(1)); + + -- + -- MULT + -- + signed_multiplier : mult_gen_v9_0 + generic map ( + c_xdevicefamily => "virtex4", -- specifies target Xilinx FPGA name + c_a_width => 32, -- width of A port + c_a_type => 0, -- datatype of A port + c_b_width => 32, -- width of B port + c_b_type => 0, -- datatype of B port + c_out_high => 63, -- MSB of P output port (N-1 downto 0 convention) + c_mult_type => 1, -- Type of multiplier to implement + c_opt_goal => 1, -- Optimization of multiplier + c_has_ce => 1, -- Use clock enable on all registers + c_pipe_stages => 6 -- Number of register stages required + ) + port map ( + clk => in_CLOCK, + a => reg_EXECUTE_IN_DATA_RA, + b => sig_B_OPERAND, + ce => sig_UPDATE, + p => sig_FULL_RES_MULS + ); + + unsigned_multiplier : mult_gen_v9_0 + generic map ( + c_xdevicefamily => "virtex4", -- specifies target Xilinx FPGA name + c_a_width => 32, -- width of A port + c_a_type => 1, -- datatype of A port + c_b_width => 32, -- width of B port + c_b_type => 1, -- datatype of B port + c_out_high => 63, -- MSB of P output port (N-1 downto 0 convention) + c_mult_type => 1, -- Type of multiplier to implement + c_opt_goal => 1, -- Optimization of multiplier + c_has_ce => 1, -- Use clock enable on all registers + c_pipe_stages => 6 -- Number of register stages required + ) + port map ( + clk => in_CLOCK, + a => reg_EXECUTE_IN_DATA_RA, + b => sig_B_OPERAND, + ce => sig_UPDATE, + p => sig_FULL_RES_MULU + ); + + sig_FULL_RES_MUL <= + sig_FULL_RES_MULS when (reg_EXECUTE_IN_OPERATION(0) = '1') else + sig_FULL_RES_MULU; + + sig_RES_MUL <= sig_FULL_RES_MUL (31 downto 0); + + sig_COUT_MUL <= sig_FULL_RES_MUL(63) or sig_FULL_RES_MUL(62) or sig_FULL_RES_MUL(61) or sig_FULL_RES_MUL(60) or + sig_FULL_RES_MUL(59) or sig_FULL_RES_MUL(58) or sig_FULL_RES_MUL(57) or sig_FULL_RES_MUL(56) or + sig_FULL_RES_MUL(55) or sig_FULL_RES_MUL(54) or sig_FULL_RES_MUL(53) or sig_FULL_RES_MUL(52) or + sig_FULL_RES_MUL(51) or sig_FULL_RES_MUL(50) or sig_FULL_RES_MUL(49) or sig_FULL_RES_MUL(48) or + sig_FULL_RES_MUL(47) or sig_FULL_RES_MUL(46) or sig_FULL_RES_MUL(45) or sig_FULL_RES_MUL(44) or + sig_FULL_RES_MUL(43) or sig_FULL_RES_MUL(42) or sig_FULL_RES_MUL(41) or sig_FULL_RES_MUL(40) or + sig_FULL_RES_MUL(39) or sig_FULL_RES_MUL(38) or sig_FULL_RES_MUL(37) or sig_FULL_RES_MUL(36) or + sig_FULL_RES_MUL(35) or sig_FULL_RES_MUL(34) or sig_FULL_RES_MUL(33) or sig_FULL_RES_MUL(32); + + sig_OVR_MUL <= sig_COUT_MUL; + + -- + -- BRANCH + -- + sig_NOSQ_BRANCH <= (reg_EXECUTE_IN_DATA_RC(0) and reg_EXECUTE_IN_OPERATION(2)) or (not reg_EXECUTE_IN_DATA_RC(0) and reg_EXECUTE_IN_OPERATION(1)) or reg_EXECUTE_IN_OPERATION(3); + sig_RES_BRANCH <= + reg_EXECUTE_IN_IMMEDIAT(29 downto 0) & "00"when (reg_EXECUTE_IN_OPERATION(3) = '1') else + "00000000000000000000000000000000"; + sig_ADDR_BRANCH <= + reg_EXECUTE_IN_DATA_RB(31 downto 2) when (reg_EXECUTE_IN_OPERATION(3) = '1') else + reg_EXECUTE_IN_IMMEDIAT(29 downto 0); + + -- + -- SHIFTER + -- + -- Instance shifter + instance_Functionnal_unit_0_shifter : Functionnal_unit_0_shifter + port map ( + in_SHIFTER_0_DATA => reg_EXECUTE_IN_DATA_RA + , in_SHIFTER_0_SHIFT => sig_B_OPERAND(4 downto 0) + , in_SHIFTER_0_DIRECTION => reg_EXECUTE_IN_OPERATION(0) + , in_SHIFTER_0_TYPE => reg_EXECUTE_IN_OPERATION(1) + , in_SHIFTER_0_CARRY => reg_EXECUTE_IN_OPERATION(2) + ,out_SHIFTER_0_DATA => sig_RES_SHIFTER + ); + + + -- + -- EXTEND + -- + sig_EXT_BYTE_S <= + "111111111111111111111111" & reg_EXECUTE_IN_DATA_RA (7 downto 0) when (reg_EXECUTE_IN_DATA_RA (7) = '1') else + "000000000000000000000000" & reg_EXECUTE_IN_DATA_RA (7 downto 0); + + sig_EXT_BYTE_Z <= + "000000000000000000000000" & reg_EXECUTE_IN_DATA_RA (7 downto 0); + + sig_EXT_HALF_WORD_S <= + "1111111111111111" & reg_EXECUTE_IN_DATA_RA (15 downto 0) when (reg_EXECUTE_IN_DATA_RA (15) = '1') else + "0000000000000000" & reg_EXECUTE_IN_DATA_RA (15 downto 0); + + sig_EXT_HALF_WORD_Z <= + "0000000000000000" & reg_EXECUTE_IN_DATA_RA (15 downto 0); + + sig_EXT_WORD_S <= + "" & reg_EXECUTE_IN_DATA_RA (31 downto 0) when (reg_EXECUTE_IN_DATA_RA (31) = '1') else + "" & reg_EXECUTE_IN_DATA_RA (31 downto 0); + + sig_EXT_WORD_Z <= + "" & reg_EXECUTE_IN_DATA_RA (31 downto 0); + + sig_EXT_S <= + sig_EXT_BYTE_S when (reg_EXECUTE_IN_IMMEDIAT = 8) else + sig_EXT_HALF_WORD_S when (reg_EXECUTE_IN_IMMEDIAT = 16) else + sig_EXT_WORD_S; + + sig_EXT_Z <= + sig_EXT_BYTE_Z when (reg_EXECUTE_IN_IMMEDIAT = 8) else + sig_EXT_HALF_WORD_Z when (reg_EXECUTE_IN_IMMEDIAT = 16) else + sig_EXT_WORD_Z; + + sig_RES_EXTEND <= + sig_EXT_Z when (reg_EXECUTE_IN_OPERATION(0) = '1') else + sig_EXT_S; + + + -- + -- FIND + -- + sig_FF1 <= + "000001" when (reg_EXECUTE_IN_DATA_RA (0) = '1') else + "000010" when (reg_EXECUTE_IN_DATA_RA (1) = '1') else + "000011" when (reg_EXECUTE_IN_DATA_RA (2) = '1') else + "000100" when (reg_EXECUTE_IN_DATA_RA (3) = '1') else + "000101" when (reg_EXECUTE_IN_DATA_RA (4) = '1') else + "000110" when (reg_EXECUTE_IN_DATA_RA (5) = '1') else + "000111" when (reg_EXECUTE_IN_DATA_RA (6) = '1') else + "001000" when (reg_EXECUTE_IN_DATA_RA (7) = '1') else + "001001" when (reg_EXECUTE_IN_DATA_RA (8) = '1') else + "001010" when (reg_EXECUTE_IN_DATA_RA (9) = '1') else + "001011" when (reg_EXECUTE_IN_DATA_RA (10) = '1') else + "001100" when (reg_EXECUTE_IN_DATA_RA (11) = '1') else + "001101" when (reg_EXECUTE_IN_DATA_RA (12) = '1') else + "001110" when (reg_EXECUTE_IN_DATA_RA (13) = '1') else + "001111" when (reg_EXECUTE_IN_DATA_RA (14) = '1') else + "010000" when (reg_EXECUTE_IN_DATA_RA (15) = '1') else + "010001" when (reg_EXECUTE_IN_DATA_RA (16) = '1') else + "010010" when (reg_EXECUTE_IN_DATA_RA (17) = '1') else + "010011" when (reg_EXECUTE_IN_DATA_RA (18) = '1') else + "010100" when (reg_EXECUTE_IN_DATA_RA (19) = '1') else + "010101" when (reg_EXECUTE_IN_DATA_RA (20) = '1') else + "010110" when (reg_EXECUTE_IN_DATA_RA (21) = '1') else + "010111" when (reg_EXECUTE_IN_DATA_RA (22) = '1') else + "011000" when (reg_EXECUTE_IN_DATA_RA (23) = '1') else + "011001" when (reg_EXECUTE_IN_DATA_RA (24) = '1') else + "011010" when (reg_EXECUTE_IN_DATA_RA (25) = '1') else + "011011" when (reg_EXECUTE_IN_DATA_RA (26) = '1') else + "011100" when (reg_EXECUTE_IN_DATA_RA (27) = '1') else + "011101" when (reg_EXECUTE_IN_DATA_RA (28) = '1') else + "011110" when (reg_EXECUTE_IN_DATA_RA (29) = '1') else + "011111" when (reg_EXECUTE_IN_DATA_RA (30) = '1') else + "100000" when (reg_EXECUTE_IN_DATA_RA (31) = '1') else + "000000"; + + sig_FL1 <= + "100000" when (reg_EXECUTE_IN_DATA_RA (31) = '1') else + "011111" when (reg_EXECUTE_IN_DATA_RA (30) = '1') else + "011110" when (reg_EXECUTE_IN_DATA_RA (29) = '1') else + "011101" when (reg_EXECUTE_IN_DATA_RA (28) = '1') else + "011100" when (reg_EXECUTE_IN_DATA_RA (27) = '1') else + "011011" when (reg_EXECUTE_IN_DATA_RA (26) = '1') else + "011010" when (reg_EXECUTE_IN_DATA_RA (25) = '1') else + "011001" when (reg_EXECUTE_IN_DATA_RA (24) = '1') else + "011000" when (reg_EXECUTE_IN_DATA_RA (23) = '1') else + "010111" when (reg_EXECUTE_IN_DATA_RA (22) = '1') else + "010110" when (reg_EXECUTE_IN_DATA_RA (21) = '1') else + "010101" when (reg_EXECUTE_IN_DATA_RA (20) = '1') else + "010100" when (reg_EXECUTE_IN_DATA_RA (19) = '1') else + "010011" when (reg_EXECUTE_IN_DATA_RA (18) = '1') else + "010010" when (reg_EXECUTE_IN_DATA_RA (17) = '1') else + "010001" when (reg_EXECUTE_IN_DATA_RA (16) = '1') else + "010000" when (reg_EXECUTE_IN_DATA_RA (15) = '1') else + "001111" when (reg_EXECUTE_IN_DATA_RA (14) = '1') else + "001110" when (reg_EXECUTE_IN_DATA_RA (13) = '1') else + "001101" when (reg_EXECUTE_IN_DATA_RA (12) = '1') else + "001100" when (reg_EXECUTE_IN_DATA_RA (11) = '1') else + "001011" when (reg_EXECUTE_IN_DATA_RA (10) = '1') else + "001010" when (reg_EXECUTE_IN_DATA_RA (9) = '1') else + "001001" when (reg_EXECUTE_IN_DATA_RA (8) = '1') else + "001000" when (reg_EXECUTE_IN_DATA_RA (7) = '1') else + "000111" when (reg_EXECUTE_IN_DATA_RA (6) = '1') else + "000110" when (reg_EXECUTE_IN_DATA_RA (5) = '1') else + "000101" when (reg_EXECUTE_IN_DATA_RA (4) = '1') else + "000100" when (reg_EXECUTE_IN_DATA_RA (3) = '1') else + "000011" when (reg_EXECUTE_IN_DATA_RA (2) = '1') else + "000010" when (reg_EXECUTE_IN_DATA_RA (1) = '1') else + "000001" when (reg_EXECUTE_IN_DATA_RA (0) = '1') else + "000000"; + + sig_RES_FIND <= + "00000000000000000000000000"&sig_FF1 when (reg_EXECUTE_IN_OPERATION(0) = '1') else + "00000000000000000000000000"&sig_FL1; + + + -- + -- SPECIAL + -- + sig_SPR_IS_HERE <= + '1' when (sig_A_OR_B(15 downto 0) = "00101") else + '0'; + -- MFSPR + sig_MFSPR <= + reg_MACLO(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000001") else + reg_MACHI(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000010") else + "00000000000000000000000000000000"; + + + -- MTSPR + process (in_CLOCK) + begin + if in_CLOCK'event and in_CLOCK = '1' then + if (sig_SPR_IS_HERE = '1') then + if (sig_A_OR_B(10 downto 0) = "00000000001") then + reg_MACLO(0) <= reg_EXECUTE_IN_DATA_RB; + end if; + if (sig_A_OR_B(10 downto 0) = "00000000010") then + reg_MACHI(0) <= reg_EXECUTE_IN_DATA_RB; + end if; + end if; + end if; + end process; + + sig_RES_SPECIAL <= + sig_MFSPR when (reg_EXECUTE_IN_OPERATION = "0000001") else + reg_EXECUTE_IN_DATA_RB when (reg_EXECUTE_IN_OPERATION = "0000010") else + "00000000000000000000000000000000"; + + -- + -- TRANSACTION + -- + sig_BUSY <= +-- reg_FUNCTIONAL_QUEUE(34)(0) when in_EXECUTE_IN_OPERATION = "" else + reg_VAL_6 when in_EXECUTE_IN_TYPE = "00100" else + reg_VAL_0; + sig_EXECUTE_OUT_VAL <= reg_EXECUTE_OUT_VAL; + sig_UPDATE <= not reg_EXECUTE_OUT_VAL or in_EXECUTE_OUT_ACK; + sig_EXECUTE_IN_ACK <= not sig_BUSY or sig_UPDATE; + + -- + -- ----------------------------------- + -- -- Output Buffer Signals + -- ----------------------------------- + -- + + sig_EXECUTE_OUT_OOO_ENGINE_ID <= reg_OOO_ENGINE_ID_0; + sig_EXECUTE_OUT_PACKET_ID <= reg_PACKET_ID_0; + sig_EXECUTE_OUT_WRITE_RD <= reg_WRITE_RD_0; + sig_EXECUTE_OUT_NUM_REG_RD <= reg_NUM_REG_RD_0; + with reg_TYPE_0 select + sig_EXECUTE_OUT_DATA_RD <= + sig_RES_ALU when "00000", + sig_RES_MOVE when "00010", + sig_RES_BRANCH when "01010", + sig_RES_SHIFTER when "00001", + sig_RES_EXTEND when "00110", + sig_RES_FIND when "00111", + sig_RES_MUL when "00100", + sig_RES_SPECIAL when "01000", + "00000000000000000000000000000000" when others; + sig_EXECUTE_OUT_WRITE_RE <= reg_WRITE_RE_0; + sig_EXECUTE_OUT_NUM_REG_RE <= reg_NUM_REG_RE_0; + with reg_TYPE_0 select + sig_EXECUTE_OUT_DATA_RE <= + sig_COUT_ALU & sig_OVR_ALU when "00000", + sig_COUT_MUL & sig_OVR_MUL when "00100", + '0' & sig_FLAG_F when "00011", + "00" when others; + sig_EXECUTE_OUT_EXCEPTION <= + "01011" when (reg_TYPE_0 = "00000" and sig_OVR_ALU = '1') else + "01011" when (reg_TYPE_0 = "00100" and sig_OVR_MUL = '1') else +-- "10011" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000001" and sig_SPR_IS_HERE = '0') else +-- "10100" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000010" and sig_SPR_IS_HERE = '0') else + "00000"; + with reg_TYPE_0 select + sig_EXECUTE_OUT_NO_SEQUENCE <= + sig_NOSQ_BRANCH when "01010", + '0'when others; + with reg_TYPE_0 select + sig_EXECUTE_OUT_ADDRESS <= + sig_ADDR_BRANCH when "01010", + sig_A_OR_B(29 downto 0) when "01000", + "000000000000000000000000000000" when others; + + -- + -- ----------------------------------- + -- -- Outputs + -- ----------------------------------- + -- + + out_EXECUTE_OUT_OOO_ENGINE_ID <= reg_EXECUTE_OUT_OOO_ENGINE_ID; + out_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_OUT_PACKET_ID; + out_EXECUTE_OUT_WRITE_RD <= reg_EXECUTE_OUT_WRITE_RD; + out_EXECUTE_OUT_NUM_REG_RD <= reg_EXECUTE_OUT_NUM_REG_RD; + out_EXECUTE_OUT_DATA_RD <= reg_EXECUTE_OUT_DATA_RD; + out_EXECUTE_OUT_WRITE_RE <= reg_EXECUTE_OUT_WRITE_RE; + out_EXECUTE_OUT_NUM_REG_RE <= reg_EXECUTE_OUT_NUM_REG_RE; + out_EXECUTE_OUT_DATA_RE <= reg_EXECUTE_OUT_DATA_RE; + out_EXECUTE_OUT_EXCEPTION <= reg_EXECUTE_OUT_EXCEPTION; + out_EXECUTE_OUT_NO_SEQUENCE <= reg_EXECUTE_OUT_NO_SEQUENCE; + out_EXECUTE_OUT_ADDRESS <= reg_EXECUTE_OUT_ADDRESS; + out_EXECUTE_OUT_VAL <= sig_EXECUTE_OUT_VAL; + out_EXECUTE_IN_ACK <= sig_EXECUTE_IN_ACK; + +end behavioural; + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0_avec_mul_mais_pas_encore_teste.vhdl =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0_avec_mul_mais_pas_encore_teste.vhdl (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0_avec_mul_mais_pas_encore_teste.vhdl (revision 116) @@ -0,0 +1,800 @@ +------------------------------------------------------------------------------- +-- File : ./Functionnal_unit_0.vhdl +-- Date : Fri Mar 13 16:20:01 2009 +-- Version : 0.2.111 - Castor +-- Comment : it's a autogenerated file, don't modify +------------------------------------------------------------------------------- + + +library ieee; + use ieee.numeric_bit.all; + use ieee.numeric_std.all; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_misc.all; +--use ieee.std_logic_signed.all; + use ieee.std_logic_unsigned.all; +--use ieee.std_logic_textio.all; + + +library work; +use work.Functionnal_unit_0_Pack.all; +use work.Functionnal_unit_0_shifter_Pack.all; + +Library XilinxCoreLib; +use XilinxCoreLib.c_compare_v9_0_comp.all; +use XilinxCoreLib.mult_gen_v9_0_comp.all; + +entity Functionnal_unit_0 is + port ( + in_CLOCK : in std_logic; + in_NRESET : in std_logic; + in_EXECUTE_IN_VAL : in std_logic; + out_EXECUTE_IN_ACK : out std_logic; + in_EXECUTE_IN_OOO_ENGINE_ID : in std_logic; + in_EXECUTE_IN_PACKET_ID : in std_logic_vector(7 downto 0); + in_EXECUTE_IN_OPERATION : in std_logic_vector(6 downto 0); + in_EXECUTE_IN_TYPE : in std_logic_vector(4 downto 0); + in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE : in std_logic_vector(1 downto 0); + in_EXECUTE_IN_HAS_IMMEDIAT : in std_logic; + in_EXECUTE_IN_IMMEDIAT : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RA : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RB : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RC : in std_logic_vector(1 downto 0); + in_EXECUTE_IN_WRITE_RD : in std_logic; + in_EXECUTE_IN_NUM_REG_RD : in std_logic_vector(4 downto 0); + in_EXECUTE_IN_WRITE_RE : in std_logic; + in_EXECUTE_IN_NUM_REG_RE : in std_logic_vector(3 downto 0); + out_EXECUTE_OUT_VAL : out std_logic; + in_EXECUTE_OUT_ACK : in std_logic; + out_EXECUTE_OUT_OOO_ENGINE_ID : out std_logic; + out_EXECUTE_OUT_PACKET_ID : out std_logic_vector(7 downto 0); + out_EXECUTE_OUT_WRITE_RD : out std_logic; + out_EXECUTE_OUT_NUM_REG_RD : out std_logic_vector(4 downto 0); + out_EXECUTE_OUT_DATA_RD : out std_logic_vector(31 downto 0); + out_EXECUTE_OUT_WRITE_RE : out std_logic; + out_EXECUTE_OUT_NUM_REG_RE : out std_logic_vector(3 downto 0); + out_EXECUTE_OUT_DATA_RE : out std_logic_vector(1 downto 0); + out_EXECUTE_OUT_EXCEPTION : out std_logic_vector(4 downto 0); + out_EXECUTE_OUT_NO_SEQUENCE : out std_logic; + out_EXECUTE_OUT_ADDRESS : out std_logic_vector(29 downto 0) + ); +end Functionnal_unit_0; + +architecture behavioural of Functionnal_unit_0 is + type Tmac is array (1 downto 0) of std_logic_vector(31 downto 0); + + signal sig_EXECUTE_IN_ACK : std_logic; + signal reg_EXECUTE_IN_VAL : std_logic; + signal reg_EXECUTE_IN_OOO_ENGINE_ID : std_logic; + signal reg_EXECUTE_IN_PACKET_ID : std_logic_vector(7 downto 0); + signal reg_EXECUTE_IN_OPERATION : std_logic_vector(6 downto 0); + signal reg_EXECUTE_IN_TYPE : std_logic_vector(4 downto 0); + signal reg_EXECUTE_IN_HAS_IMMEDIAT : std_logic; + signal reg_EXECUTE_IN_IMMEDIAT : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RA : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RB : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RC : std_logic_vector(1 downto 0); + signal reg_EXECUTE_IN_WRITE_RD : std_logic; + signal reg_EXECUTE_IN_NUM_REG_RD : std_logic_vector(4 downto 0); + signal reg_EXECUTE_IN_WRITE_RE : std_logic; + signal reg_EXECUTE_IN_NUM_REG_RE : std_logic_vector(3 downto 0); + signal sig_B_OPERAND : std_logic_vector(31 downto 0); + signal sig_IS_ARITH : std_logic; + signal sig_IS_LOGIC : std_logic; + signal sig_CIN_ARITH : std_logic; + signal sig_ARITH_B_OPERAND : std_logic_vector(31 downto 0); + signal sig_RES_ARITH : std_logic_vector(32 downto 0); + signal sig_A_AND_B : std_logic_vector(31 downto 0); + signal sig_A_OR_B : std_logic_vector(31 downto 0); + signal sig_A_XOR_B : std_logic_vector(31 downto 0); + signal sig_RES_LOGIC : std_logic_vector(31 downto 0); + signal sig_RES_ALU : std_logic_vector(31 downto 0); + signal sig_OVR_ALU : std_logic; + signal sig_COUT_ALU : std_logic; + signal sig_RES_MOVE : std_logic_vector(31 downto 0); + signal sig_CMOV : std_logic_vector(31 downto 0); + signal sig_MOVHI : std_logic_vector(31 downto 0); + signal sig_RES_BRANCH : std_logic_vector(31 downto 0); + signal sig_ADDR_BRANCH : std_logic_vector(29 downto 0); + signal sig_NOSQ_BRANCH : std_logic; + signal sig_RES_SHIFTER : std_logic_vector(31 downto 0); + signal sig_EXT_BYTE_S : std_logic_vector(31 downto 0); + signal sig_EXT_BYTE_Z : std_logic_vector(31 downto 0); + signal sig_EXT_HALF_WORD_S : std_logic_vector(31 downto 0); + signal sig_EXT_HALF_WORD_Z : std_logic_vector(31 downto 0); + signal sig_EXT_WORD_S : std_logic_vector(31 downto 0); + signal sig_EXT_WORD_Z : std_logic_vector(31 downto 0); + signal sig_EXT_S : std_logic_vector(31 downto 0); + signal sig_EXT_Z : std_logic_vector(31 downto 0); + signal sig_RES_EXTEND : std_logic_vector(31 downto 0); + signal sig_FF1 : std_logic_vector(5 downto 0); + signal sig_FL1 : std_logic_vector(5 downto 0); + signal sig_RES_FIND : std_logic_vector(31 downto 0); + signal sig_SPR_IS_HERE : std_logic; + signal sig_MFSPR : std_logic_vector(31 downto 0); + signal sig_MTSPR : std_logic_vector(31 downto 0); + signal sig_RES_SPECIAL : std_logic_vector(31 downto 0); + signal sig_EXECUTE_OUT_VAL : std_logic; + signal sig_UPDATE : std_logic; + signal reg_EXECUTE_OUT_VAL : std_logic; + signal reg_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; + signal sig_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; + signal reg_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); + signal sig_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); + signal reg_EXECUTE_OUT_WRITE_RD : std_logic; + signal sig_EXECUTE_OUT_WRITE_RD : std_logic; + signal reg_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); + signal sig_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); + signal reg_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); + signal sig_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); + signal reg_EXECUTE_OUT_WRITE_RE : std_logic; + signal sig_EXECUTE_OUT_WRITE_RE : std_logic; + signal reg_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); + signal sig_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); + signal reg_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); + signal sig_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); + signal reg_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); + signal sig_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); + signal reg_EXECUTE_OUT_NO_SEQUENCE : std_logic; + signal sig_EXECUTE_OUT_NO_SEQUENCE : std_logic; + signal reg_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); + signal sig_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); + signal reg_MACLO : Tmac; + signal reg_MACHI : Tmac; + + signal sig_VAL_5 : std_logic; + signal sig_VAL_0 : std_logic; + signal sig_NUM_REG_RE_0 : std_logic_vector(3 downto 0); + signal sig_WRITE_RE_0 : std_logic; + signal sig_NUM_REG_RD_0 : std_logic_vector(4 downto 0); + signal sig_WRITE_RD_0 : std_logic; + signal sig_TYPE_0 : std_logic_vector(4 downto 0); + signal sig_PACKET_ID_0 : std_logic_vector(7 downto 0); + signal sig_OOO_ENGINE_ID_0 : std_logic; + + signal sig_IS_LESS : std_logic; + signal sig_A_COMPARE : std_logic_vector(31 downto 0); + signal sig_B_COMPARE : std_logic_vector(31 downto 0); + signal sig_A_GT_B_S : std_logic; + signal sig_A_GT_B_U : std_logic; + signal sig_A_EQ_B : std_logic; + signal sig_A_GT_B : std_logic; + signal sig_A_GE_B : std_logic; + signal sig_A_NE_B : std_logic; + signal sig_IS_SIGNED : std_logic; + signal sig_FLAG_F : std_logic; + signal sig_BUSY : std_logic; + + signal sig_FULL_RES_MUL : std_logic_vector (63 downto 0); + signal sig_FULL_RES_MULU : std_logic_vector (63 downto 0); + signal sig_FULL_RES_MULS : std_logic_vector (63 downto 0); + signal sig_RES_MUL : std_logic_vector (31 downto 0); + signal sig_COUT_MUL : std_logic; + signal sig_OVR_MUL : std_logic; + + + type TFQUEUE is array (5 downto 0) of std_logic_vector(25 downto 0); + -- OOO_ENGINE_ID(1) + PACKET_ID(8) + TYPE(5) + WRITE_RD(1) + + -- NUM_REG_RD(5) + WRITE_RE(1) + NUM_REG_RE(4) + VALID(1) = 26 BITS + signal reg_FUNCTIONAL_QUEUE : TFQUEUE; + + + + alias reg_OOO_ENGINE_ID_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(25); + alias reg_OOO_ENGINE_ID_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(25); + alias reg_OOO_ENGINE_ID_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(25); + alias reg_OOO_ENGINE_ID_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(25); + alias reg_OOO_ENGINE_ID_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(25); + alias reg_OOO_ENGINE_ID_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(25); + alias reg_PACKET_ID_5 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(5)(24 downto 17); + alias reg_PACKET_ID_4 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(4)(24 downto 17); + alias reg_PACKET_ID_3 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(3)(24 downto 17); + alias reg_PACKET_ID_2 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(2)(24 downto 17); + alias reg_PACKET_ID_1 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(1)(24 downto 17); + alias reg_PACKET_ID_0 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(0)(24 downto 17); + alias reg_TYPE_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(16 downto 12); + alias reg_TYPE_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(16 downto 12); + alias reg_TYPE_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(16 downto 12); + alias reg_TYPE_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(16 downto 12); + alias reg_TYPE_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(16 downto 12); + alias reg_TYPE_0 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(0)(16 downto 12); + alias reg_WRITE_RD_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(11); + alias reg_WRITE_RD_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(11); + alias reg_WRITE_RD_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(11); + alias reg_WRITE_RD_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(11); + alias reg_WRITE_RD_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(11); + alias reg_WRITE_RD_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(11); + alias reg_NUM_REG_RD_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(10 downto 6); + alias reg_NUM_REG_RD_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(10 downto 6); + alias reg_NUM_REG_RD_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(10 downto 6); + alias reg_NUM_REG_RD_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(10 downto 6); + alias reg_NUM_REG_RD_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(10 downto 6); + alias reg_NUM_REG_RD_0 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(0)(10 downto 6); + alias reg_WRITE_RE_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(5); + alias reg_WRITE_RE_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(5); + alias reg_WRITE_RE_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(5); + alias reg_WRITE_RE_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(5); + alias reg_WRITE_RE_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(5); + alias reg_WRITE_RE_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(5); + alias reg_NUM_REG_RE_5 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(5)(4 downto 1); + alias reg_NUM_REG_RE_4 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(4)(4 downto 1); + alias reg_NUM_REG_RE_3 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(3)(4 downto 1); + alias reg_NUM_REG_RE_2 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(2)(4 downto 1); + alias reg_NUM_REG_RE_1 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(1)(4 downto 1); + alias reg_NUM_REG_RE_0 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(0)(4 downto 1); + alias reg_VAL_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(0); + alias reg_VAL_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(0); + alias reg_VAL_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(0); + alias reg_VAL_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(0); + alias reg_VAL_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(0); + alias reg_VAL_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(0); + +begin + + -- + -- ----------------------------------- + -- -- Registers + -- ----------------------------------- + -- + + process (in_CLOCK) + begin + if in_CLOCK'event and in_CLOCK = '1' then + if (in_NRESET = '0') then + reg_EXECUTE_IN_VAL <= '0'; + reg_EXECUTE_OUT_VAL <= '0'; + reg_FUNCTIONAL_QUEUE(0) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(1) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(2) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(3) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(4) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(5) <= (others => '0'); + else + -- Input + if (sig_EXECUTE_IN_ACK = '1') then + reg_EXECUTE_IN_VAL <= in_EXECUTE_IN_VAL; + reg_EXECUTE_IN_NUM_REG_RE <= in_EXECUTE_IN_NUM_REG_RE; + reg_EXECUTE_IN_WRITE_RE <= in_EXECUTE_IN_WRITE_RE; + reg_EXECUTE_IN_NUM_REG_RD <= in_EXECUTE_IN_NUM_REG_RD; + reg_EXECUTE_IN_WRITE_RD <= in_EXECUTE_IN_WRITE_RD; + reg_EXECUTE_IN_DATA_RC <= in_EXECUTE_IN_DATA_RC; + reg_EXECUTE_IN_DATA_RB <= in_EXECUTE_IN_DATA_RB; + reg_EXECUTE_IN_DATA_RA <= in_EXECUTE_IN_DATA_RA; + reg_EXECUTE_IN_IMMEDIAT <= in_EXECUTE_IN_IMMEDIAT; + reg_EXECUTE_IN_HAS_IMMEDIAT <= in_EXECUTE_IN_HAS_IMMEDIAT; + reg_EXECUTE_IN_TYPE <= in_EXECUTE_IN_TYPE; + reg_EXECUTE_IN_OPERATION <= in_EXECUTE_IN_OPERATION; + reg_EXECUTE_IN_PACKET_ID <= in_EXECUTE_IN_PACKET_ID; + reg_EXECUTE_IN_OOO_ENGINE_ID <= in_EXECUTE_IN_OOO_ENGINE_ID; + + -- Pipeline + if (in_EXECUTE_IN_TYPE = "00100") then + reg_VAL_5 <= in_EXECUTE_IN_VAL; + reg_NUM_REG_RE_5 <= in_EXECUTE_IN_NUM_REG_RE; + reg_WRITE_RE_5 <= in_EXECUTE_IN_WRITE_RE; + reg_NUM_REG_RD_5 <= in_EXECUTE_IN_NUM_REG_RD; + reg_WRITE_RD_5 <= in_EXECUTE_IN_WRITE_RD; + reg_TYPE_5 <= in_EXECUTE_IN_TYPE; + reg_PACKET_ID_5 <= in_EXECUTE_IN_PACKET_ID; + reg_OOO_ENGINE_ID_5 <= in_EXECUTE_IN_OOO_ENGINE_ID; + + reg_VAL_0 <= reg_VAL_1; + reg_NUM_REG_RE_0 <= reg_NUM_REG_RE_1; + reg_WRITE_RE_0 <= reg_WRITE_RE_1; + reg_NUM_REG_RD_0 <= reg_NUM_REG_RD_1; + reg_WRITE_RD_0 <= reg_WRITE_RD_1; + reg_TYPE_0 <= reg_TYPE_1; + reg_PACKET_ID_0 <= reg_PACKET_ID_1; + reg_OOO_ENGINE_ID_0 <= reg_OOO_ENGINE_ID_1; + + else + reg_VAL_0 <= in_EXECUTE_IN_VAL; + reg_NUM_REG_RE_0 <= in_EXECUTE_IN_NUM_REG_RE; + reg_WRITE_RE_0 <= in_EXECUTE_IN_WRITE_RE; + reg_NUM_REG_RD_0 <= in_EXECUTE_IN_NUM_REG_RD; + reg_WRITE_RD_0 <= in_EXECUTE_IN_WRITE_RD; + reg_TYPE_0 <= in_EXECUTE_IN_TYPE; + reg_PACKET_ID_0 <= in_EXECUTE_IN_PACKET_ID; + reg_OOO_ENGINE_ID_0 <= in_EXECUTE_IN_OOO_ENGINE_ID; + end if; + end if; + if (sig_UPDATE = '1') then + + reg_VAL_1 <= reg_VAL_2; + reg_NUM_REG_RE_1 <= reg_NUM_REG_RE_2; + reg_WRITE_RE_1 <= reg_WRITE_RE_2; + reg_NUM_REG_RD_1 <= reg_NUM_REG_RD_2; + reg_WRITE_RD_1 <= reg_WRITE_RD_2; + reg_TYPE_1 <= reg_TYPE_2; + reg_PACKET_ID_1 <= reg_PACKET_ID_2; + reg_OOO_ENGINE_ID_1 <= reg_OOO_ENGINE_ID_2; + + reg_VAL_2 <= reg_VAL_3; + reg_NUM_REG_RE_2 <= reg_NUM_REG_RE_3; + reg_WRITE_RE_2 <= reg_WRITE_RE_3; + reg_NUM_REG_RD_2 <= reg_NUM_REG_RD_3; + reg_WRITE_RD_2 <= reg_WRITE_RD_3; + reg_TYPE_2 <= reg_TYPE_3; + reg_PACKET_ID_2 <= reg_PACKET_ID_3; + reg_OOO_ENGINE_ID_2 <= reg_OOO_ENGINE_ID_3; + + reg_VAL_3 <= reg_VAL_4; + reg_NUM_REG_RE_3 <= reg_NUM_REG_RE_4; + reg_WRITE_RE_3 <= reg_WRITE_RE_4; + reg_NUM_REG_RD_3 <= reg_NUM_REG_RD_4; + reg_WRITE_RD_3 <= reg_WRITE_RD_4; + reg_TYPE_3 <= reg_TYPE_4; + reg_PACKET_ID_3 <= reg_PACKET_ID_4; + reg_OOO_ENGINE_ID_3 <= reg_OOO_ENGINE_ID_4; + + reg_VAL_4 <= reg_VAL_5; + reg_NUM_REG_RE_4 <= reg_NUM_REG_RE_5; + reg_WRITE_RE_4 <= reg_WRITE_RE_5; + reg_NUM_REG_RD_4 <= reg_NUM_REG_RD_5; + reg_WRITE_RD_4 <= reg_WRITE_RD_5; + reg_TYPE_4 <= reg_TYPE_5; + reg_PACKET_ID_4 <= reg_PACKET_ID_5; + reg_OOO_ENGINE_ID_4 <= reg_OOO_ENGINE_ID_5; + + -- Output + reg_EXECUTE_OUT_VAL <= reg_VAL_0; + reg_EXECUTE_OUT_OOO_ENGINE_ID <= sig_EXECUTE_OUT_OOO_ENGINE_ID; + reg_EXECUTE_OUT_PACKET_ID <= sig_EXECUTE_OUT_PACKET_ID; + reg_EXECUTE_OUT_WRITE_RD <= sig_EXECUTE_OUT_WRITE_RD; + reg_EXECUTE_OUT_NUM_REG_RD <= sig_EXECUTE_OUT_NUM_REG_RD; + reg_EXECUTE_OUT_DATA_RD <= sig_EXECUTE_OUT_DATA_RD; + reg_EXECUTE_OUT_WRITE_RE <= sig_EXECUTE_OUT_WRITE_RE; + reg_EXECUTE_OUT_NUM_REG_RE <= sig_EXECUTE_OUT_NUM_REG_RE; + reg_EXECUTE_OUT_DATA_RE <= sig_EXECUTE_OUT_DATA_RE; + reg_EXECUTE_OUT_EXCEPTION <= sig_EXECUTE_OUT_EXCEPTION; + reg_EXECUTE_OUT_NO_SEQUENCE <= sig_EXECUTE_OUT_NO_SEQUENCE; + reg_EXECUTE_OUT_ADDRESS <= sig_EXECUTE_OUT_ADDRESS; + end if; + end if; + end if; + end process; + + -- + -- ----------------------------------- + -- -- Insides + -- ----------------------------------- + -- + +-- sig_VAL_0 <= in_EXECUTE_IN_VAL when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_VAL_1; +-- sig_NUM_REG_RE_0 <= in_EXECUTE_IN_NUM_REG_RE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_NUM_REG_RE_1; +-- sig_WRITE_RE_0 <= in_EXECUTE_IN_WRITE_RE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_WRITE_RE_1; +-- sig_NUM_REG_RD_0 <= in_EXECUTE_IN_NUM_REG_RD when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_NUM_REG_RD_1; +-- sig_WRITE_RD_0 <= in_EXECUTE_IN_WRITE_RD when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_WRITE_RD_1; +-- sig_TYPE_0 <= in_EXECUTE_IN_TYPE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_TYPE_1; +-- sig_PACKET_ID_0 <= in_EXECUTE_IN_PACKET_ID when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_PACKET_ID_1; +-- sig_OOO_ENGINE_ID_0 <= in_EXECUTE_IN_OOO_ENGINE_ID when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_OOO_ENGINE_ID_1; + +-- sig_VAL_5 <= reg_EXECUTE_IN_VAL when (reg_EXECUTE_IN_TYPE = "00100") else +-- '0'; + + sig_B_OPERAND <= reg_EXECUTE_IN_IMMEDIAT when (reg_EXECUTE_IN_HAS_IMMEDIAT = '1') else + reg_EXECUTE_IN_DATA_RB; + -- + -- ALU + -- + sig_IS_ARITH <= reg_EXECUTE_IN_OPERATION(0) or reg_EXECUTE_IN_OPERATION(1) or reg_EXECUTE_IN_OPERATION(2); + sig_IS_LOGIC <= reg_EXECUTE_IN_OPERATION(3) or reg_EXECUTE_IN_OPERATION(4) or reg_EXECUTE_IN_OPERATION(5); + sig_CIN_ARITH <= reg_EXECUTE_IN_DATA_RC(1) and reg_EXECUTE_IN_OPERATION(1); + sig_ARITH_B_OPERAND <= ((not sig_B_OPERAND) + 1) when (reg_EXECUTE_IN_OPERATION(2) = '1') else + sig_B_OPERAND; + sig_RES_ARITH <= ('0' & reg_EXECUTE_IN_DATA_RA) + ('0' & sig_ARITH_B_OPERAND) + ("000000000000000000000000000000" & sig_CIN_ARITH); + + sig_A_AND_B <= reg_EXECUTE_IN_DATA_RA and sig_B_OPERAND; + sig_A_OR_B <= reg_EXECUTE_IN_DATA_RA or sig_B_OPERAND; + sig_A_XOR_B <= reg_EXECUTE_IN_DATA_RA xor sig_B_OPERAND; + + with reg_EXECUTE_IN_OPERATION select + sig_RES_LOGIC <= + sig_A_AND_B when "0001000", + sig_A_OR_B when "0010000", + sig_A_XOR_B when "0100000", + "00000000000000000000000000000000" when others; + sig_RES_ALU <= + sig_RES_ARITH (31 downto 0) when (sig_IS_ARITH = '1') else + sig_RES_LOGIC when (sig_IS_LOGIC = '1') else + "00000000000000000000000000000000"; + + -- In ISA l.sub doesn't change carry flag. + sig_COUT_ALU <= (sig_RES_ARITH(32) and (reg_EXECUTE_IN_OPERATION(0) or reg_EXECUTE_IN_OPERATION(1))) or (reg_EXECUTE_IN_OPERATION(2) and reg_EXECUTE_IN_DATA_RC(1)); + sig_OVR_ALU <= ((sig_ARITH_B_OPERAND(31) and reg_EXECUTE_IN_DATA_RA(31) and not sig_RES_ARITH(31)) or (not sig_ARITH_B_OPERAND(31) and not reg_EXECUTE_IN_DATA_RA(31) and sig_RES_ARITH(31))) and sig_IS_ARITH; + + -- + -- MOVE + -- + sig_MOVHI <= reg_EXECUTE_IN_IMMEDIAT(15 downto 0) & "0000000000000000"; + sig_CMOV <= + reg_EXECUTE_IN_DATA_RA when (reg_EXECUTE_IN_DATA_RC(0) = '1') else + reg_EXECUTE_IN_DATA_RB; + sig_RES_MOVE <= + sig_MOVHI when (reg_EXECUTE_IN_OPERATION(0) = '1') else + sig_CMOV when (reg_EXECUTE_IN_OPERATION(1) = '1') else + "00000000000000000000000000000000"; + + -- + -- TEST + -- + sig_IS_LESS <= reg_EXECUTE_IN_OPERATION(3); + sig_A_COMPARE <= + sig_B_OPERAND when (sig_IS_LESS = '1') else + reg_EXECUTE_IN_DATA_RA; + + sig_B_COMPARE <= + reg_EXECUTE_IN_DATA_RA when (sig_IS_LESS = '1') else + sig_B_OPERAND; + + a_gt_b_s : c_compare_v9_0 + generic map ( + c_width => 32, + c_data_type => 0, -- 0 = signed, 1 = unsigned + c_has_a_eq_b => 0, + c_has_a_gt_b => 1) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_gt_b => sig_A_GT_B_S); + + a_gt_b_u : c_compare_v9_0 + generic map ( + c_width => 32, + c_data_type => 1, -- 0 = signed, 1 = unsigned + c_has_a_eq_b => 0, + c_has_a_gt_b => 1) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_gt_b => sig_A_GT_B_U); + + a_eq_b : c_compare_v9_0 + generic map ( -- sign doesn't matter for + -- equality test + c_width => 32, + c_has_a_eq_b => 1, + c_has_a_gt_b => 0) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_eq_b => sig_A_EQ_B); + + sig_IS_SIGNED <= reg_EXECUTE_IN_OPERATION(6); + sig_A_GT_B <= + sig_A_GT_B_S when (sig_IS_SIGNED = '1') else + sig_A_GT_B_U; + sig_A_GE_B <= sig_A_GT_B or sig_A_EQ_B; + sig_A_NE_B <= not sig_A_EQ_B; + + sig_FLAG_F <= + (sig_A_EQ_B and reg_EXECUTE_IN_OPERATION(4)) or + (sig_A_NE_B and reg_EXECUTE_IN_OPERATION(5)) or + (sig_A_GE_B and reg_EXECUTE_IN_OPERATION(0)) or + (sig_A_GT_B and reg_EXECUTE_IN_OPERATION(1)); + + -- + -- MULT + -- + signed_multiplier : mult_gen_v9_0 + generic map ( + c_xdevicefamily => "virtex4", -- specifies target Xilinx FPGA name + c_a_width => 32, -- width of A port + c_a_type => 0, -- datatype of A port + c_b_width => 32, -- width of B port + c_b_type => 0, -- datatype of B port + c_out_high => 63, -- MSB of P output port (N-1 downto 0 convention) + c_mult_type => 1, -- Type of multiplier to implement + c_opt_goal => 1, -- Optimization of multiplier + c_has_ce => 1, -- Use clock enable on all registers + c_pipe_stages => 6 -- Number of register stages required + ) + port map ( + clk => in_CLOCK, + a => reg_EXECUTE_IN_DATA_RA, + b => sig_B_OPERAND, + ce => sig_UPDATE, + p => sig_FULL_RES_MULS + ); + + unsigned_multiplier : mult_gen_v9_0 + generic map ( + c_xdevicefamily => "virtex4", -- specifies target Xilinx FPGA name + c_a_width => 32, -- width of A port + c_a_type => 1, -- datatype of A port + c_b_width => 32, -- width of B port + c_b_type => 1, -- datatype of B port + c_out_high => 63, -- MSB of P output port (N-1 downto 0 convention) + c_mult_type => 1, -- Type of multiplier to implement + c_opt_goal => 1, -- Optimization of multiplier + c_has_ce => 1, -- Use clock enable on all registers + c_pipe_stages => 6 -- Number of register stages required + ) + port map ( + clk => in_CLOCK, + a => reg_EXECUTE_IN_DATA_RA, + b => sig_B_OPERAND, + ce => sig_UPDATE, + p => sig_FULL_RES_MULU + ); + + sig_FULL_RES_MUL <= + sig_FULL_RES_MULS when (reg_EXECUTE_IN_OPERATION(0) = '1') else + sig_FULL_RES_MULU; + + sig_RES_MUL <= sig_FULL_RES_MUL (31 downto 0); + + sig_COUT_MUL <= sig_FULL_RES_MUL(63) or sig_FULL_RES_MUL(62) or sig_FULL_RES_MUL(61) or sig_FULL_RES_MUL(60) or + sig_FULL_RES_MUL(59) or sig_FULL_RES_MUL(58) or sig_FULL_RES_MUL(57) or sig_FULL_RES_MUL(56) or + sig_FULL_RES_MUL(55) or sig_FULL_RES_MUL(54) or sig_FULL_RES_MUL(53) or sig_FULL_RES_MUL(52) or + sig_FULL_RES_MUL(51) or sig_FULL_RES_MUL(50) or sig_FULL_RES_MUL(49) or sig_FULL_RES_MUL(48) or + sig_FULL_RES_MUL(47) or sig_FULL_RES_MUL(46) or sig_FULL_RES_MUL(45) or sig_FULL_RES_MUL(44) or + sig_FULL_RES_MUL(43) or sig_FULL_RES_MUL(42) or sig_FULL_RES_MUL(41) or sig_FULL_RES_MUL(40) or + sig_FULL_RES_MUL(39) or sig_FULL_RES_MUL(38) or sig_FULL_RES_MUL(37) or sig_FULL_RES_MUL(36) or + sig_FULL_RES_MUL(35) or sig_FULL_RES_MUL(34) or sig_FULL_RES_MUL(33) or sig_FULL_RES_MUL(32); + + sig_OVR_MUL <= sig_COUT_MUL; + + -- + -- BRANCH + -- + sig_NOSQ_BRANCH <= (reg_EXECUTE_IN_DATA_RC(0) and reg_EXECUTE_IN_OPERATION(2)) or (not reg_EXECUTE_IN_DATA_RC(0) and reg_EXECUTE_IN_OPERATION(1)) or reg_EXECUTE_IN_OPERATION(3); + sig_RES_BRANCH <= + reg_EXECUTE_IN_IMMEDIAT(29 downto 0) & "00"when (reg_EXECUTE_IN_OPERATION(3) = '1') else + "00000000000000000000000000000000"; + sig_ADDR_BRANCH <= + reg_EXECUTE_IN_DATA_RB(31 downto 2) when (reg_EXECUTE_IN_OPERATION(3) = '1') else + reg_EXECUTE_IN_IMMEDIAT(29 downto 0); + + -- + -- SHIFTER + -- + -- Instance shifter + instance_Functionnal_unit_0_shifter : Functionnal_unit_0_shifter + port map ( + in_SHIFTER_0_DATA => reg_EXECUTE_IN_DATA_RA + , in_SHIFTER_0_SHIFT => sig_B_OPERAND(4 downto 0) + , in_SHIFTER_0_DIRECTION => reg_EXECUTE_IN_OPERATION(0) + , in_SHIFTER_0_TYPE => reg_EXECUTE_IN_OPERATION(1) + , in_SHIFTER_0_CARRY => reg_EXECUTE_IN_OPERATION(2) + ,out_SHIFTER_0_DATA => sig_RES_SHIFTER + ); + + + -- + -- EXTEND + -- + sig_EXT_BYTE_S <= + "111111111111111111111111" & reg_EXECUTE_IN_DATA_RA (7 downto 0) when (reg_EXECUTE_IN_DATA_RA (7) = '1') else + "000000000000000000000000" & reg_EXECUTE_IN_DATA_RA (7 downto 0); + + sig_EXT_BYTE_Z <= + "000000000000000000000000" & reg_EXECUTE_IN_DATA_RA (7 downto 0); + + sig_EXT_HALF_WORD_S <= + "1111111111111111" & reg_EXECUTE_IN_DATA_RA (15 downto 0) when (reg_EXECUTE_IN_DATA_RA (15) = '1') else + "0000000000000000" & reg_EXECUTE_IN_DATA_RA (15 downto 0); + + sig_EXT_HALF_WORD_Z <= + "0000000000000000" & reg_EXECUTE_IN_DATA_RA (15 downto 0); + + sig_EXT_WORD_S <= + "" & reg_EXECUTE_IN_DATA_RA (31 downto 0) when (reg_EXECUTE_IN_DATA_RA (31) = '1') else + "" & reg_EXECUTE_IN_DATA_RA (31 downto 0); + + sig_EXT_WORD_Z <= + "" & reg_EXECUTE_IN_DATA_RA (31 downto 0); + + sig_EXT_S <= + sig_EXT_BYTE_S when (reg_EXECUTE_IN_IMMEDIAT = 8) else + sig_EXT_HALF_WORD_S when (reg_EXECUTE_IN_IMMEDIAT = 16) else + sig_EXT_WORD_S; + + sig_EXT_Z <= + sig_EXT_BYTE_Z when (reg_EXECUTE_IN_IMMEDIAT = 8) else + sig_EXT_HALF_WORD_Z when (reg_EXECUTE_IN_IMMEDIAT = 16) else + sig_EXT_WORD_Z; + + sig_RES_EXTEND <= + sig_EXT_Z when (reg_EXECUTE_IN_OPERATION(0) = '1') else + sig_EXT_S; + + + -- + -- FIND + -- + sig_FF1 <= + "000001" when (reg_EXECUTE_IN_DATA_RA (0) = '1') else + "000010" when (reg_EXECUTE_IN_DATA_RA (1) = '1') else + "000011" when (reg_EXECUTE_IN_DATA_RA (2) = '1') else + "000100" when (reg_EXECUTE_IN_DATA_RA (3) = '1') else + "000101" when (reg_EXECUTE_IN_DATA_RA (4) = '1') else + "000110" when (reg_EXECUTE_IN_DATA_RA (5) = '1') else + "000111" when (reg_EXECUTE_IN_DATA_RA (6) = '1') else + "001000" when (reg_EXECUTE_IN_DATA_RA (7) = '1') else + "001001" when (reg_EXECUTE_IN_DATA_RA (8) = '1') else + "001010" when (reg_EXECUTE_IN_DATA_RA (9) = '1') else + "001011" when (reg_EXECUTE_IN_DATA_RA (10) = '1') else + "001100" when (reg_EXECUTE_IN_DATA_RA (11) = '1') else + "001101" when (reg_EXECUTE_IN_DATA_RA (12) = '1') else + "001110" when (reg_EXECUTE_IN_DATA_RA (13) = '1') else + "001111" when (reg_EXECUTE_IN_DATA_RA (14) = '1') else + "010000" when (reg_EXECUTE_IN_DATA_RA (15) = '1') else + "010001" when (reg_EXECUTE_IN_DATA_RA (16) = '1') else + "010010" when (reg_EXECUTE_IN_DATA_RA (17) = '1') else + "010011" when (reg_EXECUTE_IN_DATA_RA (18) = '1') else + "010100" when (reg_EXECUTE_IN_DATA_RA (19) = '1') else + "010101" when (reg_EXECUTE_IN_DATA_RA (20) = '1') else + "010110" when (reg_EXECUTE_IN_DATA_RA (21) = '1') else + "010111" when (reg_EXECUTE_IN_DATA_RA (22) = '1') else + "011000" when (reg_EXECUTE_IN_DATA_RA (23) = '1') else + "011001" when (reg_EXECUTE_IN_DATA_RA (24) = '1') else + "011010" when (reg_EXECUTE_IN_DATA_RA (25) = '1') else + "011011" when (reg_EXECUTE_IN_DATA_RA (26) = '1') else + "011100" when (reg_EXECUTE_IN_DATA_RA (27) = '1') else + "011101" when (reg_EXECUTE_IN_DATA_RA (28) = '1') else + "011110" when (reg_EXECUTE_IN_DATA_RA (29) = '1') else + "011111" when (reg_EXECUTE_IN_DATA_RA (30) = '1') else + "100000" when (reg_EXECUTE_IN_DATA_RA (31) = '1') else + "000000"; + + sig_FL1 <= + "100000" when (reg_EXECUTE_IN_DATA_RA (31) = '1') else + "011111" when (reg_EXECUTE_IN_DATA_RA (30) = '1') else + "011110" when (reg_EXECUTE_IN_DATA_RA (29) = '1') else + "011101" when (reg_EXECUTE_IN_DATA_RA (28) = '1') else + "011100" when (reg_EXECUTE_IN_DATA_RA (27) = '1') else + "011011" when (reg_EXECUTE_IN_DATA_RA (26) = '1') else + "011010" when (reg_EXECUTE_IN_DATA_RA (25) = '1') else + "011001" when (reg_EXECUTE_IN_DATA_RA (24) = '1') else + "011000" when (reg_EXECUTE_IN_DATA_RA (23) = '1') else + "010111" when (reg_EXECUTE_IN_DATA_RA (22) = '1') else + "010110" when (reg_EXECUTE_IN_DATA_RA (21) = '1') else + "010101" when (reg_EXECUTE_IN_DATA_RA (20) = '1') else + "010100" when (reg_EXECUTE_IN_DATA_RA (19) = '1') else + "010011" when (reg_EXECUTE_IN_DATA_RA (18) = '1') else + "010010" when (reg_EXECUTE_IN_DATA_RA (17) = '1') else + "010001" when (reg_EXECUTE_IN_DATA_RA (16) = '1') else + "010000" when (reg_EXECUTE_IN_DATA_RA (15) = '1') else + "001111" when (reg_EXECUTE_IN_DATA_RA (14) = '1') else + "001110" when (reg_EXECUTE_IN_DATA_RA (13) = '1') else + "001101" when (reg_EXECUTE_IN_DATA_RA (12) = '1') else + "001100" when (reg_EXECUTE_IN_DATA_RA (11) = '1') else + "001011" when (reg_EXECUTE_IN_DATA_RA (10) = '1') else + "001010" when (reg_EXECUTE_IN_DATA_RA (9) = '1') else + "001001" when (reg_EXECUTE_IN_DATA_RA (8) = '1') else + "001000" when (reg_EXECUTE_IN_DATA_RA (7) = '1') else + "000111" when (reg_EXECUTE_IN_DATA_RA (6) = '1') else + "000110" when (reg_EXECUTE_IN_DATA_RA (5) = '1') else + "000101" when (reg_EXECUTE_IN_DATA_RA (4) = '1') else + "000100" when (reg_EXECUTE_IN_DATA_RA (3) = '1') else + "000011" when (reg_EXECUTE_IN_DATA_RA (2) = '1') else + "000010" when (reg_EXECUTE_IN_DATA_RA (1) = '1') else + "000001" when (reg_EXECUTE_IN_DATA_RA (0) = '1') else + "000000"; + + sig_RES_FIND <= + "00000000000000000000000000"&sig_FF1 when (reg_EXECUTE_IN_OPERATION(0) = '1') else + "00000000000000000000000000"&sig_FL1; + + + -- + -- SPECIAL + -- + sig_SPR_IS_HERE <= + '1' when (sig_A_OR_B(15 downto 0) = "00101") else + '0'; + -- MFSPR + sig_MFSPR <= + reg_MACLO(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000001") else + reg_MACHI(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000010") else + "00000000000000000000000000000000"; + + + -- MTSPR + process (in_CLOCK) + begin + if in_CLOCK'event and in_CLOCK = '1' then + if (sig_SPR_IS_HERE = '1') then + if (sig_A_OR_B(10 downto 0) = "00000000001") then + reg_MACLO(0) <= reg_EXECUTE_IN_DATA_RB; + end if; + if (sig_A_OR_B(10 downto 0) = "00000000010") then + reg_MACHI(0) <= reg_EXECUTE_IN_DATA_RB; + end if; + end if; + end if; + end process; + + sig_RES_SPECIAL <= + sig_MFSPR when (reg_EXECUTE_IN_OPERATION = "0000001") else + reg_EXECUTE_IN_DATA_RB when (reg_EXECUTE_IN_OPERATION = "0000010") else + "00000000000000000000000000000000"; + + -- + -- TRANSACTION + -- + sig_BUSY <= +-- reg_FUNCTIONAL_QUEUE(34)(0) when in_EXECUTE_IN_OPERATION = "" else + reg_VAL_5 when in_EXECUTE_IN_TYPE = "00100" else + reg_VAL_0; + sig_EXECUTE_OUT_VAL <= reg_EXECUTE_OUT_VAL; + sig_UPDATE <= not reg_EXECUTE_OUT_VAL or in_EXECUTE_OUT_ACK; + sig_EXECUTE_IN_ACK <= not sig_BUSY or sig_UPDATE; + + -- + -- ----------------------------------- + -- -- Output Buffer Signals + -- ----------------------------------- + -- + + sig_EXECUTE_OUT_OOO_ENGINE_ID <= reg_OOO_ENGINE_ID_0; + sig_EXECUTE_OUT_PACKET_ID <= reg_PACKET_ID_0; + sig_EXECUTE_OUT_WRITE_RD <= reg_WRITE_RD_0; + sig_EXECUTE_OUT_NUM_REG_RD <= reg_NUM_REG_RD_0; + with reg_TYPE_0 select + sig_EXECUTE_OUT_DATA_RD <= + sig_RES_ALU when "00000", + sig_RES_MOVE when "00010", + sig_RES_BRANCH when "01010", + sig_RES_SHIFTER when "00001", + sig_RES_EXTEND when "00110", + sig_RES_FIND when "00111", + sig_RES_MUL when "00100", + sig_RES_SPECIAL when "01000", + "00000000000000000000000000000000" when others; + sig_EXECUTE_OUT_WRITE_RE <= reg_WRITE_RE_0; + sig_EXECUTE_OUT_NUM_REG_RE <= reg_NUM_REG_RE_0; + with reg_TYPE_0 select + sig_EXECUTE_OUT_DATA_RE <= + sig_COUT_ALU & sig_OVR_ALU when "00000", + sig_COUT_MUL & sig_OVR_MUL when "00100", + '0' & sig_FLAG_F when "00011", + "00" when others; + sig_EXECUTE_OUT_EXCEPTION <= + "01011" when (reg_TYPE_0 = "00000" and sig_OVR_ALU = '1') else + "01011" when (reg_TYPE_0 = "00100" and sig_OVR_MUL = '1') else +-- "10011" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000001" and sig_SPR_IS_HERE = '0') else +-- "10100" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000010" and sig_SPR_IS_HERE = '0') else + "00000"; + with reg_TYPE_0 select + sig_EXECUTE_OUT_NO_SEQUENCE <= + sig_NOSQ_BRANCH when "01010", + '0'when others; + with reg_TYPE_0 select + sig_EXECUTE_OUT_ADDRESS <= + sig_ADDR_BRANCH when "01010", + sig_A_OR_B(29 downto 0) when "01000", + "000000000000000000000000000000" when others; + + -- + -- ----------------------------------- + -- -- Outputs + -- ----------------------------------- + -- + + out_EXECUTE_OUT_OOO_ENGINE_ID <= reg_EXECUTE_OUT_OOO_ENGINE_ID; + out_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_OUT_PACKET_ID; + out_EXECUTE_OUT_WRITE_RD <= reg_EXECUTE_OUT_WRITE_RD; + out_EXECUTE_OUT_NUM_REG_RD <= reg_EXECUTE_OUT_NUM_REG_RD; + out_EXECUTE_OUT_DATA_RD <= reg_EXECUTE_OUT_DATA_RD; + out_EXECUTE_OUT_WRITE_RE <= reg_EXECUTE_OUT_WRITE_RE; + out_EXECUTE_OUT_NUM_REG_RE <= reg_EXECUTE_OUT_NUM_REG_RE; + out_EXECUTE_OUT_DATA_RE <= reg_EXECUTE_OUT_DATA_RE; + out_EXECUTE_OUT_EXCEPTION <= reg_EXECUTE_OUT_EXCEPTION; + out_EXECUTE_OUT_NO_SEQUENCE <= reg_EXECUTE_OUT_NO_SEQUENCE; + out_EXECUTE_OUT_ADDRESS <= reg_EXECUTE_OUT_ADDRESS; + out_EXECUTE_OUT_VAL <= sig_EXECUTE_OUT_VAL; + out_EXECUTE_IN_ACK <= sig_EXECUTE_IN_ACK; + +end behavioural; + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0_avec_mul_qui_marche.vhdl =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0_avec_mul_qui_marche.vhdl (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/save/Functionnal_unit_0_avec_mul_qui_marche.vhdl (revision 116) @@ -0,0 +1,818 @@ +------------------------------------------------------------------------------- +-- File : ./Functionnal_unit_0.vhdl +-- Date : Fri Mar 13 16:20:01 2009 +-- Version : 0.2.111 - Castor +-- Comment : it's a autogenerated file, don't modify +------------------------------------------------------------------------------- + + +library ieee; + use ieee.numeric_bit.all; + use ieee.numeric_std.all; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_misc.all; +--use ieee.std_logic_signed.all; + use ieee.std_logic_unsigned.all; +--use ieee.std_logic_textio.all; + + +library work; +use work.Functionnal_unit_0_Pack.all; +use work.Functionnal_unit_0_shifter_Pack.all; + +Library XilinxCoreLib; +use XilinxCoreLib.c_compare_v9_0_comp.all; +use XilinxCoreLib.mult_gen_v9_0_comp.all; + +entity Functionnal_unit_0 is + port ( + in_CLOCK : in std_logic; + in_NRESET : in std_logic; + in_EXECUTE_IN_VAL : in std_logic; + out_EXECUTE_IN_ACK : out std_logic; + in_EXECUTE_IN_OOO_ENGINE_ID : in std_logic; + in_EXECUTE_IN_PACKET_ID : in std_logic_vector(7 downto 0); + in_EXECUTE_IN_OPERATION : in std_logic_vector(6 downto 0); + in_EXECUTE_IN_TYPE : in std_logic_vector(4 downto 0); + in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE : in std_logic_vector(1 downto 0); + in_EXECUTE_IN_HAS_IMMEDIAT : in std_logic; + in_EXECUTE_IN_IMMEDIAT : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RA : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RB : in std_logic_vector(31 downto 0); + in_EXECUTE_IN_DATA_RC : in std_logic_vector(1 downto 0); + in_EXECUTE_IN_WRITE_RD : in std_logic; + in_EXECUTE_IN_NUM_REG_RD : in std_logic_vector(4 downto 0); + in_EXECUTE_IN_WRITE_RE : in std_logic; + in_EXECUTE_IN_NUM_REG_RE : in std_logic_vector(3 downto 0); + out_EXECUTE_OUT_VAL : out std_logic; + in_EXECUTE_OUT_ACK : in std_logic; + out_EXECUTE_OUT_OOO_ENGINE_ID : out std_logic; + out_EXECUTE_OUT_PACKET_ID : out std_logic_vector(7 downto 0); + out_EXECUTE_OUT_WRITE_RD : out std_logic; + out_EXECUTE_OUT_NUM_REG_RD : out std_logic_vector(4 downto 0); + out_EXECUTE_OUT_DATA_RD : out std_logic_vector(31 downto 0); + out_EXECUTE_OUT_WRITE_RE : out std_logic; + out_EXECUTE_OUT_NUM_REG_RE : out std_logic_vector(3 downto 0); + out_EXECUTE_OUT_DATA_RE : out std_logic_vector(1 downto 0); + out_EXECUTE_OUT_EXCEPTION : out std_logic_vector(4 downto 0); + out_EXECUTE_OUT_NO_SEQUENCE : out std_logic; + out_EXECUTE_OUT_ADDRESS : out std_logic_vector(29 downto 0) + ); +end Functionnal_unit_0; + +architecture behavioural of Functionnal_unit_0 is + type Tmac is array (1 downto 0) of std_logic_vector(31 downto 0); + + signal sig_EXECUTE_IN_ACK : std_logic; + signal reg_EXECUTE_IN_VAL : std_logic; + signal reg_EXECUTE_IN_OOO_ENGINE_ID : std_logic; + signal reg_EXECUTE_IN_PACKET_ID : std_logic_vector(7 downto 0); + signal reg_EXECUTE_IN_OPERATION : std_logic_vector(6 downto 0); + signal reg_EXECUTE_IN_TYPE : std_logic_vector(4 downto 0); + signal reg_EXECUTE_IN_HAS_IMMEDIAT : std_logic; + signal reg_EXECUTE_IN_IMMEDIAT : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RA : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RB : std_logic_vector(31 downto 0); + signal reg_EXECUTE_IN_DATA_RC : std_logic_vector(1 downto 0); + signal reg_EXECUTE_IN_WRITE_RD : std_logic; + signal reg_EXECUTE_IN_NUM_REG_RD : std_logic_vector(4 downto 0); + signal reg_EXECUTE_IN_WRITE_RE : std_logic; + signal reg_EXECUTE_IN_NUM_REG_RE : std_logic_vector(3 downto 0); + signal sig_B_OPERAND : std_logic_vector(31 downto 0); + signal sig_IS_ARITH : std_logic; + signal sig_IS_LOGIC : std_logic; + signal sig_CIN_ARITH : std_logic; + signal sig_ARITH_B_OPERAND : std_logic_vector(31 downto 0); + signal sig_RES_ARITH : std_logic_vector(32 downto 0); + signal sig_A_AND_B : std_logic_vector(31 downto 0); + signal sig_A_OR_B : std_logic_vector(31 downto 0); + signal sig_A_XOR_B : std_logic_vector(31 downto 0); + signal sig_RES_LOGIC : std_logic_vector(31 downto 0); + signal sig_RES_ALU : std_logic_vector(31 downto 0); + signal sig_OVR_ALU : std_logic; + signal sig_COUT_ALU : std_logic; + signal sig_RES_MOVE : std_logic_vector(31 downto 0); + signal sig_CMOV : std_logic_vector(31 downto 0); + signal sig_MOVHI : std_logic_vector(31 downto 0); + signal sig_RES_BRANCH : std_logic_vector(31 downto 0); + signal sig_ADDR_BRANCH : std_logic_vector(29 downto 0); + signal sig_NOSQ_BRANCH : std_logic; + signal sig_RES_SHIFTER : std_logic_vector(31 downto 0); + signal sig_EXT_BYTE_S : std_logic_vector(31 downto 0); + signal sig_EXT_BYTE_Z : std_logic_vector(31 downto 0); + signal sig_EXT_HALF_WORD_S : std_logic_vector(31 downto 0); + signal sig_EXT_HALF_WORD_Z : std_logic_vector(31 downto 0); + signal sig_EXT_WORD_S : std_logic_vector(31 downto 0); + signal sig_EXT_WORD_Z : std_logic_vector(31 downto 0); + signal sig_EXT_S : std_logic_vector(31 downto 0); + signal sig_EXT_Z : std_logic_vector(31 downto 0); + signal sig_RES_EXTEND : std_logic_vector(31 downto 0); + signal sig_FF1 : std_logic_vector(5 downto 0); + signal sig_FL1 : std_logic_vector(5 downto 0); + signal sig_RES_FIND : std_logic_vector(31 downto 0); + signal sig_SPR_IS_HERE : std_logic; + signal sig_MFSPR : std_logic_vector(31 downto 0); + signal sig_MTSPR : std_logic_vector(31 downto 0); + signal sig_RES_SPECIAL : std_logic_vector(31 downto 0); + signal sig_EXECUTE_OUT_VAL : std_logic; + signal sig_UPDATE : std_logic; + signal reg_EXECUTE_OUT_VAL : std_logic; + signal reg_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; + signal sig_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; + signal reg_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); + signal sig_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); + signal reg_EXECUTE_OUT_WRITE_RD : std_logic; + signal sig_EXECUTE_OUT_WRITE_RD : std_logic; + signal reg_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); + signal sig_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); + signal reg_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); + signal sig_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); + signal reg_EXECUTE_OUT_WRITE_RE : std_logic; + signal sig_EXECUTE_OUT_WRITE_RE : std_logic; + signal reg_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); + signal sig_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); + signal reg_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); + signal sig_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); + signal reg_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); + signal sig_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); + signal reg_EXECUTE_OUT_NO_SEQUENCE : std_logic; + signal sig_EXECUTE_OUT_NO_SEQUENCE : std_logic; + signal reg_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); + signal sig_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); + signal reg_MACLO : Tmac; + signal reg_MACHI : Tmac; + + signal sig_VAL_5 : std_logic; + signal sig_VAL_0 : std_logic; + signal sig_NUM_REG_RE_0 : std_logic_vector(3 downto 0); + signal sig_WRITE_RE_0 : std_logic; + signal sig_NUM_REG_RD_0 : std_logic_vector(4 downto 0); + signal sig_WRITE_RD_0 : std_logic; + signal sig_TYPE_0 : std_logic_vector(4 downto 0); + signal sig_PACKET_ID_0 : std_logic_vector(7 downto 0); + signal sig_OOO_ENGINE_ID_0 : std_logic; + + signal sig_IS_LESS : std_logic; + signal sig_A_COMPARE : std_logic_vector(31 downto 0); + signal sig_B_COMPARE : std_logic_vector(31 downto 0); + signal sig_A_GT_B_S : std_logic; + signal sig_A_GT_B_U : std_logic; + signal sig_A_EQ_B : std_logic; + signal sig_A_GT_B : std_logic; + signal sig_A_GE_B : std_logic; + signal sig_A_NE_B : std_logic; + signal sig_IS_SIGNED : std_logic; + signal sig_FLAG_F : std_logic; + signal sig_BUSY : std_logic; + + signal sig_FULL_RES_MUL : std_logic_vector (63 downto 0); + signal sig_FULL_RES_MULU : std_logic_vector (63 downto 0); + signal sig_FULL_RES_MULS : std_logic_vector (63 downto 0); + signal sig_RES_MUL : std_logic_vector (31 downto 0); + signal sig_COUT_MUL : std_logic; + signal sig_OVR_MUL : std_logic; + + + type TFQUEUE is array (6 downto 0) of std_logic_vector(25 downto 0); + -- OOO_ENGINE_ID(1) + PACKET_ID(8) + TYPE(5) + WRITE_RD(1) + + -- NUM_REG_RD(5) + WRITE_RE(1) + NUM_REG_RE(4) + VALID(1) = 26 BITS + signal reg_FUNCTIONAL_QUEUE : TFQUEUE; + + + alias reg_OOO_ENGINE_ID_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(25); + alias reg_PACKET_ID_6 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(6)(24 downto 17); + alias reg_TYPE_6 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(6)(16 downto 12); + alias reg_WRITE_RD_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(11); + alias reg_NUM_REG_RD_6 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(6)(10 downto 6); + alias reg_WRITE_RE_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(5); + alias reg_NUM_REG_RE_6 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(6)(4 downto 1); + alias reg_VAL_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(0); + + alias reg_OOO_ENGINE_ID_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(25); + alias reg_OOO_ENGINE_ID_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(25); + alias reg_OOO_ENGINE_ID_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(25); + alias reg_OOO_ENGINE_ID_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(25); + alias reg_OOO_ENGINE_ID_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(25); + alias reg_OOO_ENGINE_ID_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(25); + alias reg_PACKET_ID_5 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(5)(24 downto 17); + alias reg_PACKET_ID_4 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(4)(24 downto 17); + alias reg_PACKET_ID_3 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(3)(24 downto 17); + alias reg_PACKET_ID_2 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(2)(24 downto 17); + alias reg_PACKET_ID_1 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(1)(24 downto 17); + alias reg_PACKET_ID_0 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(0)(24 downto 17); + alias reg_TYPE_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(16 downto 12); + alias reg_TYPE_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(16 downto 12); + alias reg_TYPE_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(16 downto 12); + alias reg_TYPE_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(16 downto 12); + alias reg_TYPE_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(16 downto 12); + alias reg_TYPE_0 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(0)(16 downto 12); + alias reg_WRITE_RD_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(11); + alias reg_WRITE_RD_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(11); + alias reg_WRITE_RD_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(11); + alias reg_WRITE_RD_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(11); + alias reg_WRITE_RD_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(11); + alias reg_WRITE_RD_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(11); + alias reg_NUM_REG_RD_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(10 downto 6); + alias reg_NUM_REG_RD_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(10 downto 6); + alias reg_NUM_REG_RD_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(10 downto 6); + alias reg_NUM_REG_RD_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(10 downto 6); + alias reg_NUM_REG_RD_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(10 downto 6); + alias reg_NUM_REG_RD_0 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(0)(10 downto 6); + alias reg_WRITE_RE_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(5); + alias reg_WRITE_RE_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(5); + alias reg_WRITE_RE_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(5); + alias reg_WRITE_RE_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(5); + alias reg_WRITE_RE_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(5); + alias reg_WRITE_RE_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(5); + alias reg_NUM_REG_RE_5 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(5)(4 downto 1); + alias reg_NUM_REG_RE_4 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(4)(4 downto 1); + alias reg_NUM_REG_RE_3 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(3)(4 downto 1); + alias reg_NUM_REG_RE_2 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(2)(4 downto 1); + alias reg_NUM_REG_RE_1 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(1)(4 downto 1); + alias reg_NUM_REG_RE_0 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(0)(4 downto 1); + alias reg_VAL_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(0); + alias reg_VAL_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(0); + alias reg_VAL_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(0); + alias reg_VAL_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(0); + alias reg_VAL_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(0); + alias reg_VAL_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(0); + +begin + + -- + -- ----------------------------------- + -- -- Registers + -- ----------------------------------- + -- + + process (in_CLOCK) + begin + if in_CLOCK'event and in_CLOCK = '1' then + if (in_NRESET = '0') then + reg_EXECUTE_IN_VAL <= '0'; + reg_EXECUTE_OUT_VAL <= '0'; + reg_FUNCTIONAL_QUEUE(0) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(1) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(2) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(3) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(4) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(5) <= (others => '0'); + reg_FUNCTIONAL_QUEUE(6) <= (others => '0'); + else + -- Input + if (sig_EXECUTE_IN_ACK = '1') then + reg_EXECUTE_IN_VAL <= in_EXECUTE_IN_VAL; + reg_EXECUTE_IN_NUM_REG_RE <= in_EXECUTE_IN_NUM_REG_RE; + reg_EXECUTE_IN_WRITE_RE <= in_EXECUTE_IN_WRITE_RE; + reg_EXECUTE_IN_NUM_REG_RD <= in_EXECUTE_IN_NUM_REG_RD; + reg_EXECUTE_IN_WRITE_RD <= in_EXECUTE_IN_WRITE_RD; + reg_EXECUTE_IN_DATA_RC <= in_EXECUTE_IN_DATA_RC; + reg_EXECUTE_IN_DATA_RB <= in_EXECUTE_IN_DATA_RB; + reg_EXECUTE_IN_DATA_RA <= in_EXECUTE_IN_DATA_RA; + reg_EXECUTE_IN_IMMEDIAT <= in_EXECUTE_IN_IMMEDIAT; + reg_EXECUTE_IN_HAS_IMMEDIAT <= in_EXECUTE_IN_HAS_IMMEDIAT; + reg_EXECUTE_IN_TYPE <= in_EXECUTE_IN_TYPE; + reg_EXECUTE_IN_OPERATION <= in_EXECUTE_IN_OPERATION; + reg_EXECUTE_IN_PACKET_ID <= in_EXECUTE_IN_PACKET_ID; + reg_EXECUTE_IN_OOO_ENGINE_ID <= in_EXECUTE_IN_OOO_ENGINE_ID; + + -- Pipeline + if (in_EXECUTE_IN_TYPE = "00100") then + reg_VAL_6 <= in_EXECUTE_IN_VAL; + reg_NUM_REG_RE_6 <= in_EXECUTE_IN_NUM_REG_RE; + reg_WRITE_RE_6 <= in_EXECUTE_IN_WRITE_RE; + reg_NUM_REG_RD_6 <= in_EXECUTE_IN_NUM_REG_RD; + reg_WRITE_RD_6 <= in_EXECUTE_IN_WRITE_RD; + reg_TYPE_6 <= in_EXECUTE_IN_TYPE; + reg_PACKET_ID_6 <= in_EXECUTE_IN_PACKET_ID; + reg_OOO_ENGINE_ID_6 <= in_EXECUTE_IN_OOO_ENGINE_ID; + + reg_VAL_0 <= reg_VAL_1; + reg_NUM_REG_RE_0 <= reg_NUM_REG_RE_1; + reg_WRITE_RE_0 <= reg_WRITE_RE_1; + reg_NUM_REG_RD_0 <= reg_NUM_REG_RD_1; + reg_WRITE_RD_0 <= reg_WRITE_RD_1; + reg_TYPE_0 <= reg_TYPE_1; + reg_PACKET_ID_0 <= reg_PACKET_ID_1; + reg_OOO_ENGINE_ID_0 <= reg_OOO_ENGINE_ID_1; + + else + reg_VAL_0 <= in_EXECUTE_IN_VAL; + reg_NUM_REG_RE_0 <= in_EXECUTE_IN_NUM_REG_RE; + reg_WRITE_RE_0 <= in_EXECUTE_IN_WRITE_RE; + reg_NUM_REG_RD_0 <= in_EXECUTE_IN_NUM_REG_RD; + reg_WRITE_RD_0 <= in_EXECUTE_IN_WRITE_RD; + reg_TYPE_0 <= in_EXECUTE_IN_TYPE; + reg_PACKET_ID_0 <= in_EXECUTE_IN_PACKET_ID; + reg_OOO_ENGINE_ID_0 <= in_EXECUTE_IN_OOO_ENGINE_ID; + end if; + end if; + if (sig_UPDATE = '1') then + + reg_VAL_1 <= reg_VAL_2; + reg_NUM_REG_RE_1 <= reg_NUM_REG_RE_2; + reg_WRITE_RE_1 <= reg_WRITE_RE_2; + reg_NUM_REG_RD_1 <= reg_NUM_REG_RD_2; + reg_WRITE_RD_1 <= reg_WRITE_RD_2; + reg_TYPE_1 <= reg_TYPE_2; + reg_PACKET_ID_1 <= reg_PACKET_ID_2; + reg_OOO_ENGINE_ID_1 <= reg_OOO_ENGINE_ID_2; + + reg_VAL_2 <= reg_VAL_3; + reg_NUM_REG_RE_2 <= reg_NUM_REG_RE_3; + reg_WRITE_RE_2 <= reg_WRITE_RE_3; + reg_NUM_REG_RD_2 <= reg_NUM_REG_RD_3; + reg_WRITE_RD_2 <= reg_WRITE_RD_3; + reg_TYPE_2 <= reg_TYPE_3; + reg_PACKET_ID_2 <= reg_PACKET_ID_3; + reg_OOO_ENGINE_ID_2 <= reg_OOO_ENGINE_ID_3; + + reg_VAL_3 <= reg_VAL_4; + reg_NUM_REG_RE_3 <= reg_NUM_REG_RE_4; + reg_WRITE_RE_3 <= reg_WRITE_RE_4; + reg_NUM_REG_RD_3 <= reg_NUM_REG_RD_4; + reg_WRITE_RD_3 <= reg_WRITE_RD_4; + reg_TYPE_3 <= reg_TYPE_4; + reg_PACKET_ID_3 <= reg_PACKET_ID_4; + reg_OOO_ENGINE_ID_3 <= reg_OOO_ENGINE_ID_4; + + reg_VAL_4 <= reg_VAL_5; + reg_NUM_REG_RE_4 <= reg_NUM_REG_RE_5; + reg_WRITE_RE_4 <= reg_WRITE_RE_5; + reg_NUM_REG_RD_4 <= reg_NUM_REG_RD_5; + reg_WRITE_RD_4 <= reg_WRITE_RD_5; + reg_TYPE_4 <= reg_TYPE_5; + reg_PACKET_ID_4 <= reg_PACKET_ID_5; + reg_OOO_ENGINE_ID_4 <= reg_OOO_ENGINE_ID_5; + + reg_VAL_5 <= reg_VAL_6; + reg_NUM_REG_RE_5 <= reg_NUM_REG_RE_6; + reg_WRITE_RE_5 <= reg_WRITE_RE_6; + reg_NUM_REG_RD_5 <= reg_NUM_REG_RD_6; + reg_WRITE_RD_5 <= reg_WRITE_RD_6; + reg_TYPE_5 <= reg_TYPE_6; + reg_PACKET_ID_5 <= reg_PACKET_ID_6; + reg_OOO_ENGINE_ID_5 <= reg_OOO_ENGINE_ID_6; + + -- Output + reg_EXECUTE_OUT_VAL <= reg_VAL_0; + reg_EXECUTE_OUT_OOO_ENGINE_ID <= sig_EXECUTE_OUT_OOO_ENGINE_ID; + reg_EXECUTE_OUT_PACKET_ID <= sig_EXECUTE_OUT_PACKET_ID; + reg_EXECUTE_OUT_WRITE_RD <= sig_EXECUTE_OUT_WRITE_RD; + reg_EXECUTE_OUT_NUM_REG_RD <= sig_EXECUTE_OUT_NUM_REG_RD; + reg_EXECUTE_OUT_DATA_RD <= sig_EXECUTE_OUT_DATA_RD; + reg_EXECUTE_OUT_WRITE_RE <= sig_EXECUTE_OUT_WRITE_RE; + reg_EXECUTE_OUT_NUM_REG_RE <= sig_EXECUTE_OUT_NUM_REG_RE; + reg_EXECUTE_OUT_DATA_RE <= sig_EXECUTE_OUT_DATA_RE; + reg_EXECUTE_OUT_EXCEPTION <= sig_EXECUTE_OUT_EXCEPTION; + reg_EXECUTE_OUT_NO_SEQUENCE <= sig_EXECUTE_OUT_NO_SEQUENCE; + reg_EXECUTE_OUT_ADDRESS <= sig_EXECUTE_OUT_ADDRESS; + end if; + end if; + end if; + end process; + + -- + -- ----------------------------------- + -- -- Insides + -- ----------------------------------- + -- + +-- sig_VAL_0 <= in_EXECUTE_IN_VAL when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_VAL_1; +-- sig_NUM_REG_RE_0 <= in_EXECUTE_IN_NUM_REG_RE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_NUM_REG_RE_1; +-- sig_WRITE_RE_0 <= in_EXECUTE_IN_WRITE_RE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_WRITE_RE_1; +-- sig_NUM_REG_RD_0 <= in_EXECUTE_IN_NUM_REG_RD when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_NUM_REG_RD_1; +-- sig_WRITE_RD_0 <= in_EXECUTE_IN_WRITE_RD when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_WRITE_RD_1; +-- sig_TYPE_0 <= in_EXECUTE_IN_TYPE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_TYPE_1; +-- sig_PACKET_ID_0 <= in_EXECUTE_IN_PACKET_ID when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_PACKET_ID_1; +-- sig_OOO_ENGINE_ID_0 <= in_EXECUTE_IN_OOO_ENGINE_ID when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else +-- reg_OOO_ENGINE_ID_1; + +-- sig_VAL_5 <= reg_EXECUTE_IN_VAL when (reg_EXECUTE_IN_TYPE = "00100") else +-- '0'; + + sig_B_OPERAND <= reg_EXECUTE_IN_IMMEDIAT when (reg_EXECUTE_IN_HAS_IMMEDIAT = '1') else + reg_EXECUTE_IN_DATA_RB; + -- + -- ALU + -- + sig_IS_ARITH <= reg_EXECUTE_IN_OPERATION(0) or reg_EXECUTE_IN_OPERATION(1) or reg_EXECUTE_IN_OPERATION(2); + sig_IS_LOGIC <= reg_EXECUTE_IN_OPERATION(3) or reg_EXECUTE_IN_OPERATION(4) or reg_EXECUTE_IN_OPERATION(5); + sig_CIN_ARITH <= reg_EXECUTE_IN_DATA_RC(1) and reg_EXECUTE_IN_OPERATION(1); + sig_ARITH_B_OPERAND <= ((not sig_B_OPERAND) + 1) when (reg_EXECUTE_IN_OPERATION(2) = '1') else + sig_B_OPERAND; + sig_RES_ARITH <= ('0' & reg_EXECUTE_IN_DATA_RA) + ('0' & sig_ARITH_B_OPERAND) + ("000000000000000000000000000000" & sig_CIN_ARITH); + + sig_A_AND_B <= reg_EXECUTE_IN_DATA_RA and sig_B_OPERAND; + sig_A_OR_B <= reg_EXECUTE_IN_DATA_RA or sig_B_OPERAND; + sig_A_XOR_B <= reg_EXECUTE_IN_DATA_RA xor sig_B_OPERAND; + + with reg_EXECUTE_IN_OPERATION select + sig_RES_LOGIC <= + sig_A_AND_B when "0001000", + sig_A_OR_B when "0010000", + sig_A_XOR_B when "0100000", + "00000000000000000000000000000000" when others; + sig_RES_ALU <= + sig_RES_ARITH (31 downto 0) when (sig_IS_ARITH = '1') else + sig_RES_LOGIC when (sig_IS_LOGIC = '1') else + "00000000000000000000000000000000"; + + -- In ISA l.sub doesn't change carry flag. + sig_COUT_ALU <= (sig_RES_ARITH(32) and (reg_EXECUTE_IN_OPERATION(0) or reg_EXECUTE_IN_OPERATION(1))) or (reg_EXECUTE_IN_OPERATION(2) and reg_EXECUTE_IN_DATA_RC(1)); + sig_OVR_ALU <= ((sig_ARITH_B_OPERAND(31) and reg_EXECUTE_IN_DATA_RA(31) and not sig_RES_ARITH(31)) or (not sig_ARITH_B_OPERAND(31) and not reg_EXECUTE_IN_DATA_RA(31) and sig_RES_ARITH(31))) and sig_IS_ARITH; + + -- + -- MOVE + -- + sig_MOVHI <= reg_EXECUTE_IN_IMMEDIAT(15 downto 0) & "0000000000000000"; + sig_CMOV <= + reg_EXECUTE_IN_DATA_RA when (reg_EXECUTE_IN_DATA_RC(0) = '1') else + reg_EXECUTE_IN_DATA_RB; + sig_RES_MOVE <= + sig_MOVHI when (reg_EXECUTE_IN_OPERATION(0) = '1') else + sig_CMOV when (reg_EXECUTE_IN_OPERATION(1) = '1') else + "00000000000000000000000000000000"; + + -- + -- TEST + -- + sig_IS_LESS <= reg_EXECUTE_IN_OPERATION(3); + sig_A_COMPARE <= + sig_B_OPERAND when (sig_IS_LESS = '1') else + reg_EXECUTE_IN_DATA_RA; + + sig_B_COMPARE <= + reg_EXECUTE_IN_DATA_RA when (sig_IS_LESS = '1') else + sig_B_OPERAND; + + a_gt_b_s : c_compare_v9_0 + generic map ( + c_width => 32, + c_data_type => 0, -- 0 = signed, 1 = unsigned + c_has_a_eq_b => 0, + c_has_a_gt_b => 1) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_gt_b => sig_A_GT_B_S); + + a_gt_b_u : c_compare_v9_0 + generic map ( + c_width => 32, + c_data_type => 1, -- 0 = signed, 1 = unsigned + c_has_a_eq_b => 0, + c_has_a_gt_b => 1) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_gt_b => sig_A_GT_B_U); + + a_eq_b : c_compare_v9_0 + generic map ( -- sign doesn't matter for + -- equality test + c_width => 32, + c_has_a_eq_b => 1, + c_has_a_gt_b => 0) + port map ( + a => sig_A_COMPARE, + b => sig_B_COMPARE, + a_eq_b => sig_A_EQ_B); + + sig_IS_SIGNED <= reg_EXECUTE_IN_OPERATION(6); + sig_A_GT_B <= + sig_A_GT_B_S when (sig_IS_SIGNED = '1') else + sig_A_GT_B_U; + sig_A_GE_B <= sig_A_GT_B or sig_A_EQ_B; + sig_A_NE_B <= not sig_A_EQ_B; + + sig_FLAG_F <= + (sig_A_EQ_B and reg_EXECUTE_IN_OPERATION(4)) or + (sig_A_NE_B and reg_EXECUTE_IN_OPERATION(5)) or + (sig_A_GE_B and reg_EXECUTE_IN_OPERATION(0)) or + (sig_A_GT_B and reg_EXECUTE_IN_OPERATION(1)); + + -- + -- MULT + -- + signed_multiplier : mult_gen_v9_0 + generic map ( + c_xdevicefamily => "virtex4", -- specifies target Xilinx FPGA name + c_a_width => 32, -- width of A port + c_a_type => 0, -- datatype of A port + c_b_width => 32, -- width of B port + c_b_type => 0, -- datatype of B port + c_out_high => 63, -- MSB of P output port (N-1 downto 0 convention) + c_mult_type => 1, -- Type of multiplier to implement + c_opt_goal => 1, -- Optimization of multiplier + c_has_ce => 1, -- Use clock enable on all registers + c_pipe_stages => 6 -- Number of register stages required + ) + port map ( + clk => in_CLOCK, + a => reg_EXECUTE_IN_DATA_RA, + b => sig_B_OPERAND, + ce => sig_UPDATE, + p => sig_FULL_RES_MULS + ); + + unsigned_multiplier : mult_gen_v9_0 + generic map ( + c_xdevicefamily => "virtex4", -- specifies target Xilinx FPGA name + c_a_width => 32, -- width of A port + c_a_type => 1, -- datatype of A port + c_b_width => 32, -- width of B port + c_b_type => 1, -- datatype of B port + c_out_high => 63, -- MSB of P output port (N-1 downto 0 convention) + c_mult_type => 1, -- Type of multiplier to implement + c_opt_goal => 1, -- Optimization of multiplier + c_has_ce => 1, -- Use clock enable on all registers + c_pipe_stages => 6 -- Number of register stages required + ) + port map ( + clk => in_CLOCK, + a => reg_EXECUTE_IN_DATA_RA, + b => sig_B_OPERAND, + ce => sig_UPDATE, + p => sig_FULL_RES_MULU + ); + + sig_FULL_RES_MUL <= + sig_FULL_RES_MULS when (reg_EXECUTE_IN_OPERATION(0) = '1') else + sig_FULL_RES_MULU; + + sig_RES_MUL <= sig_FULL_RES_MUL (31 downto 0); + + sig_COUT_MUL <= sig_FULL_RES_MUL(63) or sig_FULL_RES_MUL(62) or sig_FULL_RES_MUL(61) or sig_FULL_RES_MUL(60) or + sig_FULL_RES_MUL(59) or sig_FULL_RES_MUL(58) or sig_FULL_RES_MUL(57) or sig_FULL_RES_MUL(56) or + sig_FULL_RES_MUL(55) or sig_FULL_RES_MUL(54) or sig_FULL_RES_MUL(53) or sig_FULL_RES_MUL(52) or + sig_FULL_RES_MUL(51) or sig_FULL_RES_MUL(50) or sig_FULL_RES_MUL(49) or sig_FULL_RES_MUL(48) or + sig_FULL_RES_MUL(47) or sig_FULL_RES_MUL(46) or sig_FULL_RES_MUL(45) or sig_FULL_RES_MUL(44) or + sig_FULL_RES_MUL(43) or sig_FULL_RES_MUL(42) or sig_FULL_RES_MUL(41) or sig_FULL_RES_MUL(40) or + sig_FULL_RES_MUL(39) or sig_FULL_RES_MUL(38) or sig_FULL_RES_MUL(37) or sig_FULL_RES_MUL(36) or + sig_FULL_RES_MUL(35) or sig_FULL_RES_MUL(34) or sig_FULL_RES_MUL(33) or sig_FULL_RES_MUL(32); + + sig_OVR_MUL <= sig_COUT_MUL; + + -- + -- BRANCH + -- + sig_NOSQ_BRANCH <= (reg_EXECUTE_IN_DATA_RC(0) and reg_EXECUTE_IN_OPERATION(2)) or (not reg_EXECUTE_IN_DATA_RC(0) and reg_EXECUTE_IN_OPERATION(1)) or reg_EXECUTE_IN_OPERATION(3); + sig_RES_BRANCH <= + reg_EXECUTE_IN_IMMEDIAT(29 downto 0) & "00"when (reg_EXECUTE_IN_OPERATION(3) = '1') else + "00000000000000000000000000000000"; + sig_ADDR_BRANCH <= + reg_EXECUTE_IN_DATA_RB(31 downto 2) when (reg_EXECUTE_IN_OPERATION(3) = '1') else + reg_EXECUTE_IN_IMMEDIAT(29 downto 0); + + -- + -- SHIFTER + -- + -- Instance shifter + instance_Functionnal_unit_0_shifter : Functionnal_unit_0_shifter + port map ( + in_SHIFTER_0_DATA => reg_EXECUTE_IN_DATA_RA + , in_SHIFTER_0_SHIFT => sig_B_OPERAND(4 downto 0) + , in_SHIFTER_0_DIRECTION => reg_EXECUTE_IN_OPERATION(0) + , in_SHIFTER_0_TYPE => reg_EXECUTE_IN_OPERATION(1) + , in_SHIFTER_0_CARRY => reg_EXECUTE_IN_OPERATION(2) + ,out_SHIFTER_0_DATA => sig_RES_SHIFTER + ); + + + -- + -- EXTEND + -- + sig_EXT_BYTE_S <= + "111111111111111111111111" & reg_EXECUTE_IN_DATA_RA (7 downto 0) when (reg_EXECUTE_IN_DATA_RA (7) = '1') else + "000000000000000000000000" & reg_EXECUTE_IN_DATA_RA (7 downto 0); + + sig_EXT_BYTE_Z <= + "000000000000000000000000" & reg_EXECUTE_IN_DATA_RA (7 downto 0); + + sig_EXT_HALF_WORD_S <= + "1111111111111111" & reg_EXECUTE_IN_DATA_RA (15 downto 0) when (reg_EXECUTE_IN_DATA_RA (15) = '1') else + "0000000000000000" & reg_EXECUTE_IN_DATA_RA (15 downto 0); + + sig_EXT_HALF_WORD_Z <= + "0000000000000000" & reg_EXECUTE_IN_DATA_RA (15 downto 0); + + sig_EXT_WORD_S <= + "" & reg_EXECUTE_IN_DATA_RA (31 downto 0) when (reg_EXECUTE_IN_DATA_RA (31) = '1') else + "" & reg_EXECUTE_IN_DATA_RA (31 downto 0); + + sig_EXT_WORD_Z <= + "" & reg_EXECUTE_IN_DATA_RA (31 downto 0); + + sig_EXT_S <= + sig_EXT_BYTE_S when (reg_EXECUTE_IN_IMMEDIAT = 8) else + sig_EXT_HALF_WORD_S when (reg_EXECUTE_IN_IMMEDIAT = 16) else + sig_EXT_WORD_S; + + sig_EXT_Z <= + sig_EXT_BYTE_Z when (reg_EXECUTE_IN_IMMEDIAT = 8) else + sig_EXT_HALF_WORD_Z when (reg_EXECUTE_IN_IMMEDIAT = 16) else + sig_EXT_WORD_Z; + + sig_RES_EXTEND <= + sig_EXT_Z when (reg_EXECUTE_IN_OPERATION(0) = '1') else + sig_EXT_S; + + + -- + -- FIND + -- + sig_FF1 <= + "000001" when (reg_EXECUTE_IN_DATA_RA (0) = '1') else + "000010" when (reg_EXECUTE_IN_DATA_RA (1) = '1') else + "000011" when (reg_EXECUTE_IN_DATA_RA (2) = '1') else + "000100" when (reg_EXECUTE_IN_DATA_RA (3) = '1') else + "000101" when (reg_EXECUTE_IN_DATA_RA (4) = '1') else + "000110" when (reg_EXECUTE_IN_DATA_RA (5) = '1') else + "000111" when (reg_EXECUTE_IN_DATA_RA (6) = '1') else + "001000" when (reg_EXECUTE_IN_DATA_RA (7) = '1') else + "001001" when (reg_EXECUTE_IN_DATA_RA (8) = '1') else + "001010" when (reg_EXECUTE_IN_DATA_RA (9) = '1') else + "001011" when (reg_EXECUTE_IN_DATA_RA (10) = '1') else + "001100" when (reg_EXECUTE_IN_DATA_RA (11) = '1') else + "001101" when (reg_EXECUTE_IN_DATA_RA (12) = '1') else + "001110" when (reg_EXECUTE_IN_DATA_RA (13) = '1') else + "001111" when (reg_EXECUTE_IN_DATA_RA (14) = '1') else + "010000" when (reg_EXECUTE_IN_DATA_RA (15) = '1') else + "010001" when (reg_EXECUTE_IN_DATA_RA (16) = '1') else + "010010" when (reg_EXECUTE_IN_DATA_RA (17) = '1') else + "010011" when (reg_EXECUTE_IN_DATA_RA (18) = '1') else + "010100" when (reg_EXECUTE_IN_DATA_RA (19) = '1') else + "010101" when (reg_EXECUTE_IN_DATA_RA (20) = '1') else + "010110" when (reg_EXECUTE_IN_DATA_RA (21) = '1') else + "010111" when (reg_EXECUTE_IN_DATA_RA (22) = '1') else + "011000" when (reg_EXECUTE_IN_DATA_RA (23) = '1') else + "011001" when (reg_EXECUTE_IN_DATA_RA (24) = '1') else + "011010" when (reg_EXECUTE_IN_DATA_RA (25) = '1') else + "011011" when (reg_EXECUTE_IN_DATA_RA (26) = '1') else + "011100" when (reg_EXECUTE_IN_DATA_RA (27) = '1') else + "011101" when (reg_EXECUTE_IN_DATA_RA (28) = '1') else + "011110" when (reg_EXECUTE_IN_DATA_RA (29) = '1') else + "011111" when (reg_EXECUTE_IN_DATA_RA (30) = '1') else + "100000" when (reg_EXECUTE_IN_DATA_RA (31) = '1') else + "000000"; + + sig_FL1 <= + "100000" when (reg_EXECUTE_IN_DATA_RA (31) = '1') else + "011111" when (reg_EXECUTE_IN_DATA_RA (30) = '1') else + "011110" when (reg_EXECUTE_IN_DATA_RA (29) = '1') else + "011101" when (reg_EXECUTE_IN_DATA_RA (28) = '1') else + "011100" when (reg_EXECUTE_IN_DATA_RA (27) = '1') else + "011011" when (reg_EXECUTE_IN_DATA_RA (26) = '1') else + "011010" when (reg_EXECUTE_IN_DATA_RA (25) = '1') else + "011001" when (reg_EXECUTE_IN_DATA_RA (24) = '1') else + "011000" when (reg_EXECUTE_IN_DATA_RA (23) = '1') else + "010111" when (reg_EXECUTE_IN_DATA_RA (22) = '1') else + "010110" when (reg_EXECUTE_IN_DATA_RA (21) = '1') else + "010101" when (reg_EXECUTE_IN_DATA_RA (20) = '1') else + "010100" when (reg_EXECUTE_IN_DATA_RA (19) = '1') else + "010011" when (reg_EXECUTE_IN_DATA_RA (18) = '1') else + "010010" when (reg_EXECUTE_IN_DATA_RA (17) = '1') else + "010001" when (reg_EXECUTE_IN_DATA_RA (16) = '1') else + "010000" when (reg_EXECUTE_IN_DATA_RA (15) = '1') else + "001111" when (reg_EXECUTE_IN_DATA_RA (14) = '1') else + "001110" when (reg_EXECUTE_IN_DATA_RA (13) = '1') else + "001101" when (reg_EXECUTE_IN_DATA_RA (12) = '1') else + "001100" when (reg_EXECUTE_IN_DATA_RA (11) = '1') else + "001011" when (reg_EXECUTE_IN_DATA_RA (10) = '1') else + "001010" when (reg_EXECUTE_IN_DATA_RA (9) = '1') else + "001001" when (reg_EXECUTE_IN_DATA_RA (8) = '1') else + "001000" when (reg_EXECUTE_IN_DATA_RA (7) = '1') else + "000111" when (reg_EXECUTE_IN_DATA_RA (6) = '1') else + "000110" when (reg_EXECUTE_IN_DATA_RA (5) = '1') else + "000101" when (reg_EXECUTE_IN_DATA_RA (4) = '1') else + "000100" when (reg_EXECUTE_IN_DATA_RA (3) = '1') else + "000011" when (reg_EXECUTE_IN_DATA_RA (2) = '1') else + "000010" when (reg_EXECUTE_IN_DATA_RA (1) = '1') else + "000001" when (reg_EXECUTE_IN_DATA_RA (0) = '1') else + "000000"; + + sig_RES_FIND <= + "00000000000000000000000000"&sig_FF1 when (reg_EXECUTE_IN_OPERATION(0) = '1') else + "00000000000000000000000000"&sig_FL1; + + + -- + -- SPECIAL + -- + sig_SPR_IS_HERE <= + '1' when (sig_A_OR_B(15 downto 0) = "00101") else + '0'; + -- MFSPR + sig_MFSPR <= + reg_MACLO(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000001") else + reg_MACHI(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000010") else + "00000000000000000000000000000000"; + + + -- MTSPR + process (in_CLOCK) + begin + if in_CLOCK'event and in_CLOCK = '1' then + if (sig_SPR_IS_HERE = '1') then + if (sig_A_OR_B(10 downto 0) = "00000000001") then + reg_MACLO(0) <= reg_EXECUTE_IN_DATA_RB; + end if; + if (sig_A_OR_B(10 downto 0) = "00000000010") then + reg_MACHI(0) <= reg_EXECUTE_IN_DATA_RB; + end if; + end if; + end if; + end process; + + sig_RES_SPECIAL <= + sig_MFSPR when (reg_EXECUTE_IN_OPERATION = "0000001") else + reg_EXECUTE_IN_DATA_RB when (reg_EXECUTE_IN_OPERATION = "0000010") else + "00000000000000000000000000000000"; + + -- + -- TRANSACTION + -- + sig_BUSY <= +-- reg_FUNCTIONAL_QUEUE(34)(0) when in_EXECUTE_IN_OPERATION = "" else + reg_VAL_6 when in_EXECUTE_IN_TYPE = "00100" else + reg_VAL_0; + sig_EXECUTE_OUT_VAL <= reg_EXECUTE_OUT_VAL; + sig_UPDATE <= not reg_EXECUTE_OUT_VAL or in_EXECUTE_OUT_ACK; + sig_EXECUTE_IN_ACK <= not sig_BUSY or sig_UPDATE; + + -- + -- ----------------------------------- + -- -- Output Buffer Signals + -- ----------------------------------- + -- + + sig_EXECUTE_OUT_OOO_ENGINE_ID <= reg_OOO_ENGINE_ID_0; + sig_EXECUTE_OUT_PACKET_ID <= reg_PACKET_ID_0; + sig_EXECUTE_OUT_WRITE_RD <= reg_WRITE_RD_0; + sig_EXECUTE_OUT_NUM_REG_RD <= reg_NUM_REG_RD_0; + with reg_TYPE_0 select + sig_EXECUTE_OUT_DATA_RD <= + sig_RES_ALU when "00000", + sig_RES_MOVE when "00010", + sig_RES_BRANCH when "01010", + sig_RES_SHIFTER when "00001", + sig_RES_EXTEND when "00110", + sig_RES_FIND when "00111", + sig_RES_MUL when "00100", + sig_RES_SPECIAL when "01000", + "00000000000000000000000000000000" when others; + sig_EXECUTE_OUT_WRITE_RE <= reg_WRITE_RE_0; + sig_EXECUTE_OUT_NUM_REG_RE <= reg_NUM_REG_RE_0; + with reg_TYPE_0 select + sig_EXECUTE_OUT_DATA_RE <= + sig_COUT_ALU & sig_OVR_ALU when "00000", + sig_COUT_MUL & sig_OVR_MUL when "00100", + '0' & sig_FLAG_F when "00011", + "00" when others; + sig_EXECUTE_OUT_EXCEPTION <= + "01011" when (reg_TYPE_0 = "00000" and sig_OVR_ALU = '1') else + "01011" when (reg_TYPE_0 = "00100" and sig_OVR_MUL = '1') else +-- "10011" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000001" and sig_SPR_IS_HERE = '0') else +-- "10100" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000010" and sig_SPR_IS_HERE = '0') else + "00000"; + with reg_TYPE_0 select + sig_EXECUTE_OUT_NO_SEQUENCE <= + sig_NOSQ_BRANCH when "01010", + '0'when others; + with reg_TYPE_0 select + sig_EXECUTE_OUT_ADDRESS <= + sig_ADDR_BRANCH when "01010", + sig_A_OR_B(29 downto 0) when "01000", + "000000000000000000000000000000" when others; + + -- + -- ----------------------------------- + -- -- Outputs + -- ----------------------------------- + -- + + out_EXECUTE_OUT_OOO_ENGINE_ID <= reg_EXECUTE_OUT_OOO_ENGINE_ID; + out_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_OUT_PACKET_ID; + out_EXECUTE_OUT_WRITE_RD <= reg_EXECUTE_OUT_WRITE_RD; + out_EXECUTE_OUT_NUM_REG_RD <= reg_EXECUTE_OUT_NUM_REG_RD; + out_EXECUTE_OUT_DATA_RD <= reg_EXECUTE_OUT_DATA_RD; + out_EXECUTE_OUT_WRITE_RE <= reg_EXECUTE_OUT_WRITE_RE; + out_EXECUTE_OUT_NUM_REG_RE <= reg_EXECUTE_OUT_NUM_REG_RE; + out_EXECUTE_OUT_DATA_RE <= reg_EXECUTE_OUT_DATA_RE; + out_EXECUTE_OUT_EXCEPTION <= reg_EXECUTE_OUT_EXCEPTION; + out_EXECUTE_OUT_NO_SEQUENCE <= reg_EXECUTE_OUT_NO_SEQUENCE; + out_EXECUTE_OUT_ADDRESS <= reg_EXECUTE_OUT_ADDRESS; + out_EXECUTE_OUT_VAL <= sig_EXECUTE_OUT_VAL; + out_EXECUTE_IN_ACK <= sig_EXECUTE_IN_ACK; + +end behavioural; + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit.cpp (revision 116) @@ -84,5 +84,18 @@ SC_METHOD (genMoore); dont_initialize (); - sensitive << (*(in_CLOCK)).neg(); + sensitive << (*(in_CLOCK)).neg(); // use internal register + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Functionnal_unit,FUNCTION,"Method - genMealy"); + + SC_METHOD (genMealy); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg() // use internal register +// << (*(in_EXECUTE_IN_VAL )) + << (*(in_EXECUTE_OUT_ACK)); + # ifdef SYSTEMCASS_SPECIFIC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMealy.cpp (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMealy.cpp (revision 116) @@ -0,0 +1,53 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace multi_execute_unit { +namespace execute_unit { +namespace functionnal_unit { + + +#undef FUNCTION +#define FUNCTION "Functionnal_unit::genMealy" + void Functionnal_unit::genMealy (void) + { + log_begin(Functionnal_unit,FUNCTION); + log_function(Functionnal_unit,FUNCTION,_name.c_str()); + + { + internal_EXECUTE_OUT_VAL = (reg_BUSY_OUT and (_execute_operation_out->_timing._latence == 0)); + + PORT_WRITE(out_EXECUTE_OUT_VAL , internal_EXECUTE_OUT_VAL); + } + + { + internal_EXECUTE_IN_ACK = (not reg_BUSY_IN or + (reg_BUSY_IN and (not reg_BUSY_OUT or + (internal_EXECUTE_OUT_VAL and PORT_READ(in_EXECUTE_OUT_ACK))))); + + PORT_WRITE(out_EXECUTE_IN_ACK , internal_EXECUTE_IN_ACK); + } + + log_end(Functionnal_unit,FUNCTION); + }; + +}; // end namespace functionnal_unit +}; // end namespace execute_unit +}; // end namespace multi_execute_unit +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp (revision 116) @@ -20,5 +20,5 @@ #undef FUNCTION -#define FUNCTION "Functionnal_unit::genMealy" +#define FUNCTION "Functionnal_unit::genMoore" void Functionnal_unit::genMoore (void) { @@ -27,13 +27,4 @@ { - internal_EXECUTE_IN_ACK = not reg_BUSY_IN; - - PORT_WRITE(out_EXECUTE_IN_ACK , internal_EXECUTE_IN_ACK); - } - - { - internal_EXECUTE_OUT_VAL = reg_BUSY_OUT and (_execute_operation_out->_timing._latence == 0); - - PORT_WRITE(out_EXECUTE_OUT_VAL , internal_EXECUTE_OUT_VAL); if (_param->_have_port_context_id) PORT_WRITE(out_EXECUTE_OUT_CONTEXT_ID ,_execute_operation_out->_context_id ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp (revision 116) @@ -58,4 +58,36 @@ } + + if (reg_BUSY_IN and not reg_BUSY_OUT) +// if (not reg_BUSY_OUT_old or) + { + reg_BUSY_OUT = reg_BUSY_IN; + reg_BUSY_IN = false; + + _execute_operation_out->_timing = _execute_operation_in->_timing ; + _execute_operation_out->_context_id = _execute_operation_in->_context_id ; + _execute_operation_out->_front_end_id = _execute_operation_in->_front_end_id ; + _execute_operation_out->_ooo_engine_id = _execute_operation_in->_ooo_engine_id; + _execute_operation_out->_packet_id = _execute_operation_in->_packet_id ; + _execute_operation_out->_operation = _execute_operation_in->_operation ; + _execute_operation_out->_type = _execute_operation_in->_type ; + _execute_operation_out->_has_immediat = _execute_operation_in->_has_immediat ; + _execute_operation_out->_immediat = _execute_operation_in->_immediat ; + _execute_operation_out->_data_ra = _execute_operation_in->_data_ra ; + _execute_operation_out->_data_rb = _execute_operation_in->_data_rb ; + _execute_operation_out->_data_rc = _execute_operation_in->_data_rc ; + _execute_operation_out->_data_rd = _execute_operation_in->_data_rd ; + _execute_operation_out->_data_re = _execute_operation_in->_data_re ; + _execute_operation_out->_write_rd = _execute_operation_in->_write_rd ; + _execute_operation_out->_num_reg_rd = _execute_operation_in->_num_reg_rd ; + _execute_operation_out->_write_re = _execute_operation_in->_write_re ; + _execute_operation_out->_num_reg_re = _execute_operation_in->_num_reg_re ; + _execute_operation_out->_exception = _execute_operation_in->_exception ; + _execute_operation_out->_no_sequence = _execute_operation_in->_no_sequence ; + _execute_operation_out->_address = _execute_operation_in->_address ; + } + + + // Test if push execute_register_t * execute_register = NULL; @@ -178,31 +210,4 @@ } - if (reg_BUSY_IN and not reg_BUSY_OUT) - { - reg_BUSY_OUT = reg_BUSY_IN; - reg_BUSY_IN = false; - - _execute_operation_out->_timing = _execute_operation_in->_timing ; - _execute_operation_out->_context_id = _execute_operation_in->_context_id ; - _execute_operation_out->_front_end_id = _execute_operation_in->_front_end_id ; - _execute_operation_out->_ooo_engine_id = _execute_operation_in->_ooo_engine_id; - _execute_operation_out->_packet_id = _execute_operation_in->_packet_id ; - _execute_operation_out->_operation = _execute_operation_in->_operation ; - _execute_operation_out->_type = _execute_operation_in->_type ; - _execute_operation_out->_has_immediat = _execute_operation_in->_has_immediat ; - _execute_operation_out->_immediat = _execute_operation_in->_immediat ; - _execute_operation_out->_data_ra = _execute_operation_in->_data_ra ; - _execute_operation_out->_data_rb = _execute_operation_in->_data_rb ; - _execute_operation_out->_data_rc = _execute_operation_in->_data_rc ; - _execute_operation_out->_data_rd = _execute_operation_in->_data_rd ; - _execute_operation_out->_data_re = _execute_operation_in->_data_re ; - _execute_operation_out->_write_rd = _execute_operation_in->_write_rd ; - _execute_operation_out->_num_reg_rd = _execute_operation_in->_num_reg_rd ; - _execute_operation_out->_write_re = _execute_operation_in->_write_re ; - _execute_operation_out->_num_reg_re = _execute_operation_in->_num_reg_re ; - _execute_operation_out->_exception = _execute_operation_in->_exception ; - _execute_operation_out->_no_sequence = _execute_operation_in->_no_sequence ; - _execute_operation_out->_address = _execute_operation_in->_address ; - } // each cycle : decrease the latence @@ -210,5 +215,5 @@ _execute_operation_out->_timing._latence --; } - + #if defined(STATISTICS) or defined(VHDL_TESTBENCH) end_cycle (); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_vhdl.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_vhdl.cpp (revision 116) @@ -9,4 +9,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h" #include "Behavioural/include/Vhdl.h" +#include "Behavioural/Generic/Shifter/include/Shifter.h" namespace morpheo { @@ -25,4 +26,35 @@ { log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); + + morpheo::behavioural::generic::shifter::Parameters * param_shifter; + + param_shifter = new morpheo::behavioural::generic::shifter::Parameters + ( + _param->_size_general_data, // size_data + 1, // nb_port + 0, // shift_value + generic::shifter::external_rotate, // rotate + generic::shifter::external_direction, // direction + generic::shifter::external_carry, // carry + false // type_completion_bool + ); + + morpheo::behavioural::generic::shifter::Shifter * shifter; + + std::string shifter_name = _name + "_shifter"; + shifter = new morpheo::behavioural::generic::shifter::Shifter + (shifter_name.c_str() +#ifdef STATISTICS + ,NULL +#endif + ,param_shifter + ,USE_VHDL); + + _component->set_component(shifter->_component +#ifdef POSITION + , 50, 50, 50, 50 +#endif + , INSTANCE_LIBRARY + ); Vhdl * vhdl = new Vhdl (_name); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_vhdl_body.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_vhdl_body.cpp (revision 116) @@ -25,4 +25,410 @@ log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); vhdl->set_body (""); + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Registers "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + vhdl->set_body (""); + vhdl->set_body (0,"process (in_CLOCK)"); + vhdl->set_body (0,"begin"); + vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); + + vhdl->set_body (2,"if (in_NRESET = '0') then"); + vhdl->set_body (3,"reg_BUSY_IN <= '0';"); + vhdl->set_body (3,"reg_BUSY_OUT <= '0';"); + vhdl->set_body (2,"else"); + + vhdl->set_comment (3,"Input Buffer"); + vhdl->set_body (3,"if (sig_EXECUTE_IN_ACK = '1') then"); + vhdl->set_body (4,"reg_BUSY_IN <= in_EXECUTE_IN_VAL;"); + if(_param->_have_port_context_id) + vhdl->set_body (4,"reg_EXECUTE_IN_CONTEXT_ID <= in_EXECUTE_IN_CONTEXT_ID;"); + if(_param->_have_port_front_end_id) + vhdl->set_body (4,"reg_EXECUTE_IN_FRONT_END_ID <= in_EXECUTE_IN_FRONT_END_ID;"); + if(_param->_have_port_ooo_engine_id) + vhdl->set_body (4,"reg_EXECUTE_IN_OOO_ENGINE_ID <= in_EXECUTE_IN_OOO_ENGINE_ID;"); + if(_param->_have_port_rob_ptr) + vhdl->set_body (4,"reg_EXECUTE_IN_PACKET_ID <= in_EXECUTE_IN_PACKET_ID;"); + vhdl->set_body (4,"reg_EXECUTE_IN_OPERATION <= in_EXECUTE_IN_OPERATION;"); + vhdl->set_body (4,"reg_EXECUTE_IN_TYPE <= in_EXECUTE_IN_TYPE;"); + vhdl->set_body (4,"reg_EXECUTE_IN_DATA_RA <= in_EXECUTE_IN_DATA_RA;"); + vhdl->set_body (4,"reg_EXECUTE_IN_DATA_RB <= in_EXECUTE_IN_DATA_RB;"); + vhdl->set_body (4,"reg_EXECUTE_IN_DATA_RC <= in_EXECUTE_IN_DATA_RC;"); + vhdl->set_body (4,"reg_EXECUTE_IN_HAS_IMMEDIAT <= in_EXECUTE_IN_HAS_IMMEDIAT;"); + vhdl->set_body (4,"reg_EXECUTE_IN_IMMEDIAT <= in_EXECUTE_IN_IMMEDIAT;"); + vhdl->set_body (4,"reg_EXECUTE_IN_WRITE_RD <= in_EXECUTE_IN_WRITE_RD;"); + vhdl->set_body (4,"reg_EXECUTE_IN_NUM_REG_RD <= in_EXECUTE_IN_NUM_REG_RD;"); + vhdl->set_body (4,"reg_EXECUTE_IN_WRITE_RE <= in_EXECUTE_IN_WRITE_RE;"); + vhdl->set_body (4,"reg_EXECUTE_IN_NUM_REG_RE <= in_EXECUTE_IN_NUM_REG_RE;"); + vhdl->set_body (3,"end if;"); + + vhdl->set_comment (3,"Output Buffer"); + vhdl->set_body (3,"if (sig_EXECUTE_OUT_UPDATE = '1') then"); + vhdl->set_body (4,"reg_BUSY_OUT <= reg_BUSY_IN;"); + if(_param->_have_port_context_id) + vhdl->set_body (4,"reg_EXECUTE_OUT_CONTEXT_ID <= sig_EXECUTE_OUT_CONTEXT_ID;"); + if(_param->_have_port_front_end_id) + vhdl->set_body (4,"reg_EXECUTE_OUT_FRONT_END_ID <= sig_EXECUTE_OUT_FRONT_END_ID;"); + if(_param->_have_port_ooo_engine_id) + vhdl->set_body (4,"reg_EXECUTE_OUT_OOO_ENGINE_ID <= sig_EXECUTE_OUT_OOO_ENGINE_ID;"); + if(_param->_have_port_rob_ptr) + vhdl->set_body (4,"reg_EXECUTE_OUT_PACKET_ID <= sig_EXECUTE_OUT_PACKET_ID;"); + vhdl->set_body (4,"reg_EXECUTE_OUT_WRITE_RD <= sig_EXECUTE_OUT_WRITE_RD;"); + vhdl->set_body (4,"reg_EXECUTE_OUT_NUM_REG_RD <= sig_EXECUTE_OUT_NUM_REG_RD;"); + vhdl->set_body (4,"reg_EXECUTE_OUT_DATA_RD <= sig_EXECUTE_OUT_DATA_RD;"); + vhdl->set_body (4,"reg_EXECUTE_OUT_WRITE_RE <= sig_EXECUTE_OUT_WRITE_RE;"); + vhdl->set_body (4,"reg_EXECUTE_OUT_NUM_REG_RE <= sig_EXECUTE_OUT_NUM_REG_RE;"); + vhdl->set_body (4,"reg_EXECUTE_OUT_DATA_RE <= sig_EXECUTE_OUT_DATA_RE;"); + vhdl->set_body (4,"reg_EXECUTE_OUT_EXCEPTION <= sig_EXECUTE_OUT_EXCEPTION;"); + vhdl->set_body (4,"reg_EXECUTE_OUT_NO_SEQUENCE <= sig_EXECUTE_OUT_NO_SEQUENCE;"); + vhdl->set_body (4,"reg_EXECUTE_OUT_ADDRESS <= sig_EXECUTE_OUT_ADDRESS;"); + vhdl->set_body (3,"end if;"); + vhdl->set_body (2,"end if;"); + vhdl->set_body (1,"end if;"); + vhdl->set_body (0,"end process;"); + + vhdl->set_body (""); + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Insides "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + + vhdl->set_body (0,""); + vhdl->set_body (0,"sig_B_OPERAND <= reg_EXECUTE_IN_IMMEDIAT when (reg_EXECUTE_IN_HAS_IMMEDIAT = '1') else"); + vhdl->set_body (1,"reg_EXECUTE_IN_DATA_RB;"); + + vhdl->set_comment(0,""); + vhdl->set_comment(0,"ALU"); + vhdl->set_comment(0,""); + + vhdl->set_body (0,"sig_IS_ARITH <= reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_ADD))+") or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_ADDC))+") or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_SUB))+");"); + + vhdl->set_body (0,"sig_IS_LOGIC <= reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_AND))+") or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_OR))+") or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_XOR))+");"); + + vhdl->set_body (0,"sig_CIN_ARITH <= reg_EXECUTE_IN_DATA_RC("+toString(FLAG_POSITION_CY)+") and reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_ADDC))+");"); +// vhdl->set_body (0,"sig_CIN_ARITH <= (reg_EXECUTE_IN_DATA_RC("+toString(FLAG_POSITION_CY)+") and reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_ADDC))+")) or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_SUB))+");"); + +// vhdl->set_body (0,"sig_ARITH_B_OPERAND <= not (sig_B_OPERAND) when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_SUB))+") = '1') else"); + vhdl->set_body (0,"sig_ARITH_B_OPERAND <= ((not sig_B_OPERAND) + 1) when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_SUB))+") = '1') else"); + vhdl->set_body (1,"sig_B_OPERAND;"); + + vhdl->set_body (0,"sig_RES_ARITH <= ('0' & reg_EXECUTE_IN_DATA_RA) + ('0' & sig_ARITH_B_OPERAND) + ("+std_logic_cst(_param->_size_general_data-2,0)+" & sig_CIN_ARITH);"); + + vhdl->set_body (0,""); + vhdl->set_body (0,"sig_A_AND_B <= reg_EXECUTE_IN_DATA_RA and sig_B_OPERAND;"); + vhdl->set_body (0,"sig_A_OR_B <= reg_EXECUTE_IN_DATA_RA or sig_B_OPERAND;"); + vhdl->set_body (0,"sig_A_XOR_B <= reg_EXECUTE_IN_DATA_RA xor sig_B_OPERAND;"); + + vhdl->set_body (0,""); + vhdl->set_body (0,"with reg_EXECUTE_IN_OPERATION select"); + vhdl->set_body (0,"sig_RES_LOGIC <="); + vhdl->set_body (1,"sig_A_AND_B when "+std_logic_cst(_param->_size_operation,OPERATION_ALU_L_AND)+","); + vhdl->set_body (1,"sig_A_OR_B when "+std_logic_cst(_param->_size_operation,OPERATION_ALU_L_OR)+","); + vhdl->set_body (1,"sig_A_XOR_B when "+std_logic_cst(_param->_size_operation,OPERATION_ALU_L_XOR)+","); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data,0)+" when others;"); + + vhdl->set_body (0,"sig_RES_ALU <="); + vhdl->set_body (1,"sig_RES_ARITH ("+toString(_param->_size_general_data-1)+" downto 0) when (sig_IS_ARITH = '1') else"); + vhdl->set_body (1,"sig_RES_LOGIC when (sig_IS_LOGIC = '1') else"); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data,0)+";"); + + vhdl->set_body (0,""); + vhdl->set_comment(0,"In ISA l.sub doesn't change carry flag."); + vhdl->set_body (0,"sig_COUT_ALU <= (sig_RES_ARITH("+toString(_param->_size_general_data)+") and (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_ADD))+") or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_ADDC))+"))) or (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_SUB))+") and reg_EXECUTE_IN_DATA_RC("+toString(FLAG_POSITION_CY)+"));"); + vhdl->set_body (0,"sig_OVR_ALU <= ((sig_ARITH_B_OPERAND("+toString(_param->_size_general_data-1)+") and reg_EXECUTE_IN_DATA_RA("+toString(_param->_size_general_data-1)+") and not sig_RES_ARITH("+toString(_param->_size_general_data-1)+")) or (not sig_ARITH_B_OPERAND("+toString(_param->_size_general_data-1)+") and not reg_EXECUTE_IN_DATA_RA("+toString(_param->_size_general_data-1)+") and sig_RES_ARITH("+toString(_param->_size_general_data-1)+"))) and sig_IS_ARITH;"); + + vhdl->set_body (0,""); + vhdl->set_comment(0,""); + vhdl->set_comment(0,"MOVE"); + vhdl->set_comment(0,""); + vhdl->set_body (0,"sig_MOVHI <= reg_EXECUTE_IN_IMMEDIAT("+toString(_param->_size_general_data-17)+" downto 0) & "+std_logic_cst(16,0)+";"); + + vhdl->set_body (0,"sig_CMOV <="); + vhdl->set_body (1,"reg_EXECUTE_IN_DATA_RA when (reg_EXECUTE_IN_DATA_RC("+toString(FLAG_POSITION_F)+") = '1') else"); + vhdl->set_body (1,"reg_EXECUTE_IN_DATA_RB;"); + + vhdl->set_body (0,"sig_RES_MOVE <="); + vhdl->set_body (1,"sig_MOVHI when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_MOVE_L_MOVHI))+") = '1') else"); + vhdl->set_body (1,"sig_CMOV when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_MOVE_L_CMOV))+") = '1') else"); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data,0)+";"); + + vhdl->set_body (0,""); + vhdl->set_comment(0,""); + vhdl->set_comment(0,"BRANCH"); + vhdl->set_comment(0,""); + vhdl->set_body (0,"sig_NOSQ_BRANCH <= (reg_EXECUTE_IN_DATA_RC("+toString(FLAG_POSITION_F)+") and reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_BRANCH_L_TEST_F))+")) or (not reg_EXECUTE_IN_DATA_RC("+toString(FLAG_POSITION_F)+") and reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_BRANCH_L_TEST_NF))+")) or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_BRANCH_L_JALR))+");"); + +#ifdef SYSTEMC_VHDL_COMPATIBILITY + vhdl->set_body (0,"sig_RES_BRANCH <="); + vhdl->set_body (1,"reg_EXECUTE_IN_IMMEDIAT("+toString(_param->_size_general_data-3)+" downto 0) & "+std_logic_cst(2,0)+"when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_BRANCH_L_JALR))+") = '1') else"); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data,0)+";"); +#else + vhdl->set_body (0,"sig_RES_BRANCH <= reg_EXECUTE_IN_IMMEDIAT("+toString(_param->_size_general_data-3)+" downto 0) & "+std_logic_cst(2,0)+";"); +#endif + + vhdl->set_body (0,"sig_ADDR_BRANCH <="); + vhdl->set_body (1,"reg_EXECUTE_IN_DATA_RB("+toString(_param->_size_instruction_address+1)+" downto 2) when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_BRANCH_L_JALR))+") = '1') else"); + vhdl->set_body (1,"reg_EXECUTE_IN_IMMEDIAT("+toString(_param->_size_instruction_address-1)+" downto 0);"); + + vhdl->set_body (""); + vhdl->set_comment(0,""); + vhdl->set_comment(0,"SHIFTER"); + vhdl->set_comment(0,""); + + vhdl->set_comment(0,"Instance shifter"); + vhdl->set_body (0,"instance_"+_name+"_shifter : "+_name+"_shifter"); + vhdl->set_body (0,"port map ("); + vhdl->set_body (1," in_SHIFTER_0_DATA \t=>\treg_EXECUTE_IN_DATA_RA"); + vhdl->set_body (1,", in_SHIFTER_0_SHIFT \t=>\tsig_B_OPERAND("+toString((log2(_param->_size_general_data))-1)+" downto 0)"); + vhdl->set_body (1,", in_SHIFTER_0_DIRECTION \t=>\treg_EXECUTE_IN_OPERATION(0)"); + vhdl->set_body (1,", in_SHIFTER_0_TYPE \t=>\treg_EXECUTE_IN_OPERATION(1)"); + vhdl->set_body (1,", in_SHIFTER_0_CARRY \t=>\treg_EXECUTE_IN_OPERATION(2)"); + vhdl->set_body (1,",out_SHIFTER_0_DATA \t=>\tsig_RES_SHIFTER"); + vhdl->set_body (0,");"); + vhdl->set_body (0,""); + + vhdl->set_body (""); + vhdl->set_comment(0,""); + vhdl->set_comment(0,"EXTEND"); + vhdl->set_comment(0,""); + + vhdl->set_body (0,"sig_EXT_BYTE_S <="); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data-8,(1<<_param->_size_general_data-8)-1)+" & reg_EXECUTE_IN_DATA_RA (7 downto 0) when (reg_EXECUTE_IN_DATA_RA (7) = '1') else"); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data-8,0)+" & reg_EXECUTE_IN_DATA_RA (7 downto 0);"); + vhdl->set_body (0,""); + + vhdl->set_body (0,"sig_EXT_BYTE_Z <="); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data-8,0)+" & reg_EXECUTE_IN_DATA_RA (7 downto 0);"); + vhdl->set_body (0,""); + + vhdl->set_body (0,"sig_EXT_HALF_WORD_S <="); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data-16,(1<<_param->_size_general_data-16)-1)+" & reg_EXECUTE_IN_DATA_RA (15 downto 0) when (reg_EXECUTE_IN_DATA_RA (15) = '1') else"); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data-16,0)+" & reg_EXECUTE_IN_DATA_RA (15 downto 0);"); + vhdl->set_body (0,""); + + vhdl->set_body (0,"sig_EXT_HALF_WORD_Z <="); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data-16,0)+" & reg_EXECUTE_IN_DATA_RA (15 downto 0);"); + vhdl->set_body (0,""); + + vhdl->set_body (0,"sig_EXT_WORD_S <="); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data-32,(1<<_param->_size_general_data-32)-1)+" & reg_EXECUTE_IN_DATA_RA (31 downto 0) when (reg_EXECUTE_IN_DATA_RA (31) = '1') else"); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data-32,0)+" & reg_EXECUTE_IN_DATA_RA (31 downto 0);"); + vhdl->set_body (0,""); + + vhdl->set_body (0,"sig_EXT_WORD_Z <="); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data-32,0)+" & reg_EXECUTE_IN_DATA_RA (31 downto 0);"); + vhdl->set_body (0,""); + + vhdl->set_body (0,"sig_EXT_S <="); + vhdl->set_body (1,"sig_EXT_BYTE_S when (reg_EXECUTE_IN_IMMEDIAT = 8) else"); + vhdl->set_body (1,"sig_EXT_HALF_WORD_S when (reg_EXECUTE_IN_IMMEDIAT = 16) else"); + vhdl->set_body (1,"sig_EXT_WORD_S;"); + vhdl->set_body (0,""); + + vhdl->set_body (0,"sig_EXT_Z <="); + vhdl->set_body (1,"sig_EXT_BYTE_Z when (reg_EXECUTE_IN_IMMEDIAT = 8) else"); + vhdl->set_body (1,"sig_EXT_HALF_WORD_Z when (reg_EXECUTE_IN_IMMEDIAT = 16) else"); + vhdl->set_body (1,"sig_EXT_WORD_Z;"); + vhdl->set_body (0,""); + + vhdl->set_body (0,"sig_RES_EXTEND <="); + vhdl->set_body (1,"sig_EXT_Z when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_EXTEND_L_EXTEND_Z))+") = '1') else"); + vhdl->set_body (1,"sig_EXT_S;"); + vhdl->set_body (0,""); + + vhdl->set_body (0,""); + vhdl->set_comment(0,""); + vhdl->set_comment(0,"FIND"); + vhdl->set_comment(0,""); + + vhdl->set_body (0,"sig_FF1 <="); + for (uint32_t i=0; i<_param->_size_general_data; i++) + vhdl->set_body (1,std_logic_cst(log2(_param->_size_general_data)+1,i+1)+" \twhen (reg_EXECUTE_IN_DATA_RA ("+toString(i)+") = '1') \telse"); + vhdl->set_body (1,std_logic_cst(log2(_param->_size_general_data)+1,0)+";"); + vhdl->set_body (0,""); + + vhdl->set_body (0,"sig_FL1 <="); + for (uint32_t i=_param->_size_general_data; i>0; i--) + vhdl->set_body (1,std_logic_cst(log2(_param->_size_general_data)+1,i)+" \twhen (reg_EXECUTE_IN_DATA_RA ("+toString(i-1)+") = '1') \telse"); + vhdl->set_body (1,std_logic_cst(log2(_param->_size_general_data)+1,0)+";"); + vhdl->set_body (0,""); + + vhdl->set_body (0,"sig_RES_FIND <="); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data-log2(_param->_size_general_data)-1,0)+"&"+"sig_FF1 when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_FIND_L_FF1))+") = '1') else"); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data-log2(_param->_size_general_data)-1,0)+"&"+"sig_FL1;"); + vhdl->set_body (0,""); + + vhdl->set_body (0,""); + vhdl->set_comment(0,""); + vhdl->set_comment(0,"SPECIAL"); + vhdl->set_comment(0,""); + + vhdl->set_body (0,"sig_SPR_IS_HERE <="); + // vhdl->set_body (1,"'1' when (sig_A_OR_B("+toString(_param->_size_special_address_group+_param->_size_special_address_register-1)+" downto "+toString(_param->_size_special_address_register)+") = "+std_logic_cst(_param->_size_special_address_group,GROUP_MAC)+") else"); + vhdl->set_body (1,"'1' when (sig_A_OR_B(15 downto 0) = "+std_logic_cst(_param->_size_special_address_group,GROUP_MAC)+") else"); + vhdl->set_body (1,"'0';"); + + vhdl->set_comment(0,"MFSPR"); + vhdl->set_body (0,"sig_MFSPR <="); + vhdl->set_body (1,"reg_MACLO"+toString((_param->_have_port_context_id == 1) ? "(reg_EXECUTE_IN_CONTEXT_ID)" : "(0)")+" when (sig_SPR_IS_HERE = '1' and sig_A_OR_B("+toString(_param->_size_special_address_register-1)+" downto 0) = "+std_logic_cst(_param->_size_special_address_register,SPR_MACLO)+") else"); + vhdl->set_body (1,"reg_MACHI"+toString((_param->_have_port_context_id == 1) ? "(reg_EXECUTE_IN_CONTEXT_ID)" : "(0)")+" when (sig_SPR_IS_HERE = '1' and sig_A_OR_B("+toString(_param->_size_special_address_register-1)+" downto 0) = "+std_logic_cst(_param->_size_special_address_register,SPR_MACHI)+") else"); + vhdl->set_body (1,std_logic_cst(_param->_size_spr,0)+";"); + vhdl->set_body (0,""); + + vhdl->set_body (0,""); + + vhdl->set_comment(0,"MTSPR"); + vhdl->set_body (0,"process (in_CLOCK)"); + vhdl->set_body (0,"begin"); + vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); + vhdl->set_body (2,"if (sig_SPR_IS_HERE = '1') then"); + vhdl->set_body (3,"if (sig_A_OR_B("+toString(_param->_size_special_address_register-1)+" downto 0) = "+std_logic_cst(_param->_size_special_address_register,SPR_MACLO)+") then"); + vhdl->set_body (4,"reg_MACLO"+toString((_param->_have_port_context_id == 1) ? "(reg_EXECUTE_IN_CONTEXT_ID)" : "(0)")+" <= reg_EXECUTE_IN_DATA_RB;"); + vhdl->set_body (3,"end if;"); + vhdl->set_body (3,"if (sig_A_OR_B("+toString(_param->_size_special_address_register-1)+" downto 0) = "+std_logic_cst(_param->_size_special_address_register,SPR_MACHI)+") then"); + vhdl->set_body (4,"reg_MACHI"+toString((_param->_have_port_context_id == 1) ? "(reg_EXECUTE_IN_CONTEXT_ID)" : "(0)")+" <= reg_EXECUTE_IN_DATA_RB;"); + vhdl->set_body (3,"end if;"); + vhdl->set_body (2,"end if;"); + vhdl->set_body (1,"end if;"); + vhdl->set_body (0,"end process;"); + vhdl->set_body (0,""); + + vhdl->set_body (0,"sig_RES_SPECIAL <="); + vhdl->set_body (1,"sig_MFSPR when (reg_EXECUTE_IN_OPERATION = "+std_logic_cst(_param->_size_operation,OPERATION_SPECIAL_L_MFSPR)+") else"); + vhdl->set_body (1,"reg_EXECUTE_IN_DATA_RB when (reg_EXECUTE_IN_OPERATION = "+std_logic_cst(_param->_size_operation,OPERATION_SPECIAL_L_MTSPR)+") else"); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data,0)+";"); + vhdl->set_body (0,""); + + vhdl->set_body (0,""); + vhdl->set_comment(0,""); + vhdl->set_comment(0,"TRANSACTION"); + vhdl->set_comment(0,""); +// vhdl->set_body (0,"sig_EXECUTE_OUT_VAL <= reg_BUSY_IN;"); +// vhdl->set_body (0,"sig_EXECUTE_IN_ACK <= not reg_BUSY_IN or (reg_BUSY_IN and in_EXECUTE_OUT_ACK);"); + + vhdl->set_body (0,"sig_EXECUTE_OUT_VAL <= reg_BUSY_OUT;"); + vhdl->set_body (0,"sig_EXECUTE_OUT_UPDATE <= not reg_BUSY_OUT or (reg_BUSY_OUT and in_EXECUTE_OUT_ACK);"); + vhdl->set_body (0,"sig_EXECUTE_IN_ACK <= not reg_BUSY_IN or (reg_BUSY_IN and sig_EXECUTE_OUT_UPDATE);"); + + vhdl->set_body (""); + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + vhdl->set_body (""); + if(_param->_have_port_context_id) + vhdl->set_body (0,"sig_EXECUTE_OUT_CONTEXT_ID <= reg_EXECUTE_IN_CONTEXT_ID;"); + + if(_param->_have_port_front_end_id) + vhdl->set_body (0,"sig_EXECUTE_OUT_FRONT_END_ID <= reg_EXECUTE_IN_FRONT_END_ID;"); + + if(_param->_have_port_ooo_engine_id) + vhdl->set_body (0,"sig_EXECUTE_OUT_OOO_ENGINE_ID <= reg_EXECUTE_IN_OOO_ENGINE_ID;"); + + if(_param->_have_port_rob_ptr) + vhdl->set_body (0,"sig_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_IN_PACKET_ID;"); + + vhdl->set_body (0,"sig_EXECUTE_OUT_WRITE_RD <= reg_EXECUTE_IN_WRITE_RD;"); + + vhdl->set_body (0,"sig_EXECUTE_OUT_NUM_REG_RD <= reg_EXECUTE_IN_NUM_REG_RD;"); + + vhdl->set_body (0,"with reg_EXECUTE_IN_TYPE select"); + vhdl->set_body (0,"sig_EXECUTE_OUT_DATA_RD <="); + vhdl->set_body (1,"sig_RES_ALU when "+std_logic_cst(_param->_size_type,TYPE_ALU)+","); + vhdl->set_body (1,"sig_RES_MOVE when "+std_logic_cst(_param->_size_type,TYPE_MOVE)+","); + vhdl->set_body (1,"sig_RES_BRANCH when "+std_logic_cst(_param->_size_type,TYPE_BRANCH)+","); + vhdl->set_body (1,"sig_RES_SHIFTER when "+std_logic_cst(_param->_size_type,TYPE_SHIFT)+","); + vhdl->set_body (1,"sig_RES_EXTEND when "+std_logic_cst(_param->_size_type,TYPE_EXTEND)+","); + vhdl->set_body (1,"sig_RES_FIND when "+std_logic_cst(_param->_size_type,TYPE_FIND)+","); + vhdl->set_body (1,"sig_RES_SPECIAL when "+std_logic_cst(_param->_size_type,TYPE_SPECIAL)+","); + vhdl->set_body (1,std_logic_cst(_param->_size_general_data,0)+" when others;"); + + vhdl->set_body (0,"sig_EXECUTE_OUT_WRITE_RE <= reg_EXECUTE_IN_WRITE_RE;"); + + vhdl->set_body (0,"sig_EXECUTE_OUT_NUM_REG_RE <= reg_EXECUTE_IN_NUM_REG_RE;"); + + vhdl->set_body (0,"with reg_EXECUTE_IN_TYPE select"); + vhdl->set_body (0,"sig_EXECUTE_OUT_DATA_RE <="); + if(FLAG_POSITION_CY > FLAG_POSITION_OV) + vhdl->set_body (1,"sig_COUT_ALU & sig_OVR_ALU when "+std_logic_cst(_param->_size_type,TYPE_ALU)+","); + else + vhdl->set_body (1,"sig_OVR_ALU & sig_COUT_ALU when "+std_logic_cst(_param->_size_type,TYPE_ALU)+","); + vhdl->set_body (1,std_logic_cst(_param->_size_special_data,0)+" when others;"); + + vhdl->set_body (0,"sig_EXECUTE_OUT_EXCEPTION <="); + vhdl->set_body (1,std_logic_cst(_param->_size_exception,EXCEPTION_ALU_RANGE)+" when (reg_EXECUTE_IN_TYPE = "+std_logic_cst(_param->_size_type,TYPE_ALU)+" and sig_OVR_ALU = '1') else"); + vhdl->set_body (1,std_logic_cst(_param->_size_exception,EXCEPTION_ALU_SPR_ACCESS_MUST_READ)+" when (reg_EXECUTE_IN_TYPE = "+std_logic_cst(_param->_size_type,TYPE_SPECIAL)+" and reg_EXECUTE_IN_OPERATION = "+std_logic_cst(_param->_size_operation,OPERATION_SPECIAL_L_MFSPR)+" and sig_SPR_IS_HERE = '0') else"); + vhdl->set_body (1,std_logic_cst(_param->_size_exception,EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE)+" when (reg_EXECUTE_IN_TYPE = "+std_logic_cst(_param->_size_type,TYPE_SPECIAL)+" and reg_EXECUTE_IN_OPERATION = "+std_logic_cst(_param->_size_operation,OPERATION_SPECIAL_L_MTSPR)+" and sig_SPR_IS_HERE = '0') else"); + vhdl->set_body (1,std_logic_cst(_param->_size_exception,EXCEPTION_NONE)+";"); + + vhdl->set_body (0,"with reg_EXECUTE_IN_TYPE select"); + vhdl->set_body (0,"sig_EXECUTE_OUT_NO_SEQUENCE <="); + vhdl->set_body (1,"sig_NOSQ_BRANCH when "+std_logic_cst(_param->_size_type,TYPE_BRANCH)+","); + vhdl->set_body (1,std_logic_cst(1,0)+"when others;"); + +#ifdef SYSTEMC_VHDL_COMPATIBILITY + vhdl->set_body (0,"with reg_EXECUTE_IN_TYPE select"); + vhdl->set_body (0,"sig_EXECUTE_OUT_ADDRESS <="); + vhdl->set_body (1,"sig_ADDR_BRANCH when "+std_logic_cst(_param->_size_type,TYPE_BRANCH)+","); + vhdl->set_body (1,"sig_A_OR_B("+toString(_param->_size_instruction_address-1)+" downto 0) when "+std_logic_cst(_param->_size_type,TYPE_SPECIAL)+","); + vhdl->set_body (1,std_logic_cst(_param->_size_instruction_address,0)+" when others;"); +#else + vhdl->set_body (0,"with reg_EXECUTE_IN_TYPE select"); + vhdl->set_body (0,"sig_EXECUTE_OUT_ADDRESS <="); + vhdl->set_body (1,"sig_ADDR_BRANCH when "+std_logic_cst(_param->_size_type,TYPE_BRANCH)+","); + vhdl->set_body (1,"sig_A_OR_B when others;"); +// vhdl->set_body (0,"sig_EXECUTE_OUT_ADDRESS <= sig_ADDR_BRANCH;"); +#endif + + vhdl->set_body (""); + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Outputs "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + vhdl->set_body (""); +// if(_param->_have_port_context_id) +// vhdl->set_body (0,"out_EXECUTE_OUT_CONTEXT_ID <= sig_EXECUTE_OUT_CONTEXT_ID;"); +// if(_param->_have_port_front_end_id) +// vhdl->set_body (0,"out_EXECUTE_OUT_FRONT_END_ID <= sig_EXECUTE_OUT_FRONT_END_ID;"); +// if(_param->_have_port_ooo_engine_id) +// vhdl->set_body (0,"out_EXECUTE_OUT_OOO_ENGINE_ID <= sig_EXECUTE_OUT_OOO_ENGINE_ID;"); +// if(_param->_have_port_rob_ptr) +// vhdl->set_body (0,"out_EXECUTE_OUT_PACKET_ID <= sig_EXECUTE_OUT_PACKET_ID;"); +// vhdl->set_body (0,"out_EXECUTE_OUT_WRITE_RD <= sig_EXECUTE_OUT_WRITE_RD;"); +// vhdl->set_body (0,"out_EXECUTE_OUT_NUM_REG_RD <= sig_EXECUTE_OUT_NUM_REG_RD;"); +// vhdl->set_body (0,"out_EXECUTE_OUT_DATA_RD <= sig_EXECUTE_OUT_DATA_RD;"); +// vhdl->set_body (0,"out_EXECUTE_OUT_WRITE_RE <= sig_EXECUTE_OUT_WRITE_RE;"); +// vhdl->set_body (0,"out_EXECUTE_OUT_NUM_REG_RE <= sig_EXECUTE_OUT_NUM_REG_RE;"); +// vhdl->set_body (0,"out_EXECUTE_OUT_DATA_RE <= sig_EXECUTE_OUT_DATA_RE;"); +// vhdl->set_body (0,"out_EXECUTE_OUT_EXCEPTION <= sig_EXECUTE_OUT_EXCEPTION;"); +// vhdl->set_body (0,"out_EXECUTE_OUT_NO_SEQUENCE <= sig_EXECUTE_OUT_NO_SEQUENCE;"); +// vhdl->set_body (0,"out_EXECUTE_OUT_ADDRESS <= sig_EXECUTE_OUT_ADDRESS;"); +// vhdl->set_body (0,"out_EXECUTE_OUT_VAL <= sig_EXECUTE_OUT_VAL;"); +// vhdl->set_body (0,"out_EXECUTE_IN_ACK <= sig_EXECUTE_IN_ACK;"); + + if(_param->_have_port_context_id) + vhdl->set_body (0,"out_EXECUTE_OUT_CONTEXT_ID <= reg_EXECUTE_OUT_CONTEXT_ID;"); + if(_param->_have_port_front_end_id) + vhdl->set_body (0,"out_EXECUTE_OUT_FRONT_END_ID <= reg_EXECUTE_OUT_FRONT_END_ID;"); + if(_param->_have_port_ooo_engine_id) + vhdl->set_body (0,"out_EXECUTE_OUT_OOO_ENGINE_ID <= reg_EXECUTE_OUT_OOO_ENGINE_ID;"); + if(_param->_have_port_rob_ptr) + vhdl->set_body (0,"out_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_OUT_PACKET_ID;"); + vhdl->set_body (0,"out_EXECUTE_OUT_WRITE_RD <= reg_EXECUTE_OUT_WRITE_RD;"); + vhdl->set_body (0,"out_EXECUTE_OUT_NUM_REG_RD <= reg_EXECUTE_OUT_NUM_REG_RD;"); + vhdl->set_body (0,"out_EXECUTE_OUT_DATA_RD <= reg_EXECUTE_OUT_DATA_RD;"); + vhdl->set_body (0,"out_EXECUTE_OUT_WRITE_RE <= reg_EXECUTE_OUT_WRITE_RE;"); + vhdl->set_body (0,"out_EXECUTE_OUT_NUM_REG_RE <= reg_EXECUTE_OUT_NUM_REG_RE;"); + vhdl->set_body (0,"out_EXECUTE_OUT_DATA_RE <= reg_EXECUTE_OUT_DATA_RE;"); + vhdl->set_body (0,"out_EXECUTE_OUT_EXCEPTION <= reg_EXECUTE_OUT_EXCEPTION;"); + vhdl->set_body (0,"out_EXECUTE_OUT_NO_SEQUENCE <= reg_EXECUTE_OUT_NO_SEQUENCE;"); + vhdl->set_body (0,"out_EXECUTE_OUT_ADDRESS <= reg_EXECUTE_OUT_ADDRESS;"); + vhdl->set_body (0,"out_EXECUTE_OUT_VAL <= sig_EXECUTE_OUT_VAL;"); + vhdl->set_body (0,"out_EXECUTE_IN_ACK <= sig_EXECUTE_IN_ACK;"); + log_printf(FUNC,Functionnal_unit,FUNCTION,"End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_vhdl_declaration.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_vhdl_declaration.cpp (revision 116) @@ -24,4 +24,114 @@ { log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); + vhdl->set_signal ("sig_EXECUTE_IN_ACK",1); + + vhdl->set_signal ("reg_BUSY_IN",1); + + if(_param->_have_port_context_id) + vhdl->set_signal ("reg_EXECUTE_IN_CONTEXT_ID", _param->_size_context_id); + if(_param->_have_port_front_end_id) + vhdl->set_signal ("reg_EXECUTE_IN_FRONT_END_ID", _param->_size_front_end_id); + if(_param->_have_port_ooo_engine_id) + vhdl->set_signal ("reg_EXECUTE_IN_OOO_ENGINE_ID", _param->_size_ooo_engine_id); + if(_param->_have_port_rob_ptr) + vhdl->set_signal ("reg_EXECUTE_IN_PACKET_ID", _param->_size_rob_ptr); + vhdl->set_signal ("reg_EXECUTE_IN_OPERATION", _param->_size_operation); + vhdl->set_signal ("reg_EXECUTE_IN_TYPE", _param->_size_type); + vhdl->set_signal ("reg_EXECUTE_IN_HAS_IMMEDIAT", 1); + vhdl->set_signal ("reg_EXECUTE_IN_IMMEDIAT", _param->_size_general_data); + vhdl->set_signal ("reg_EXECUTE_IN_DATA_RA", _param->_size_general_data); + vhdl->set_signal ("reg_EXECUTE_IN_DATA_RB", _param->_size_general_data); + vhdl->set_signal ("reg_EXECUTE_IN_DATA_RC", _param->_size_special_data); + vhdl->set_signal ("reg_EXECUTE_IN_WRITE_RD", 1); + vhdl->set_signal ("reg_EXECUTE_IN_NUM_REG_RD", _param->_size_general_register); + vhdl->set_signal ("reg_EXECUTE_IN_WRITE_RE", 1); + vhdl->set_signal ("reg_EXECUTE_IN_NUM_REG_RE", _param->_size_special_register); + + vhdl->set_signal ("sig_B_OPERAND",_param->_size_general_data); + + vhdl->set_signal ("sig_IS_ARITH",1); + vhdl->set_signal ("sig_IS_LOGIC",1); + vhdl->set_signal ("sig_CIN_ARITH",1); + vhdl->set_signal ("sig_ARITH_B_OPERAND",_param->_size_general_data); + vhdl->set_signal ("sig_RES_ARITH",_param->_size_general_data+1); + vhdl->set_signal ("sig_A_AND_B",_param->_size_general_data); + vhdl->set_signal ("sig_A_OR_B",_param->_size_general_data); + vhdl->set_signal ("sig_A_XOR_B",_param->_size_general_data); + vhdl->set_signal ("sig_RES_LOGIC",_param->_size_general_data); + vhdl->set_signal ("sig_RES_ALU",_param->_size_general_data); + vhdl->set_signal ("sig_OVR_ALU",1); + vhdl->set_signal ("sig_COUT_ALU",1); + + vhdl->set_signal ("sig_RES_MOVE",_param->_size_general_data); + vhdl->set_signal ("sig_CMOV",_param->_size_general_data); + vhdl->set_signal ("sig_MOVHI",_param->_size_general_data); + + vhdl->set_signal ("sig_RES_BRANCH",_param->_size_general_data); + vhdl->set_signal ("sig_ADDR_BRANCH",_param->_size_instruction_address); + vhdl->set_signal ("sig_NOSQ_BRANCH",1); + + vhdl->set_signal ("sig_RES_SHIFTER",_param->_size_general_data); + + vhdl->set_signal ("sig_EXT_BYTE_S",_param->_size_general_data); + vhdl->set_signal ("sig_EXT_BYTE_Z",_param->_size_general_data); + vhdl->set_signal ("sig_EXT_HALF_WORD_S",_param->_size_general_data); + vhdl->set_signal ("sig_EXT_HALF_WORD_Z",_param->_size_general_data); + vhdl->set_signal ("sig_EXT_WORD_S",_param->_size_general_data); + vhdl->set_signal ("sig_EXT_WORD_Z",_param->_size_general_data); + vhdl->set_signal ("sig_EXT_S",_param->_size_general_data); + vhdl->set_signal ("sig_EXT_Z",_param->_size_general_data); + vhdl->set_signal ("sig_RES_EXTEND",_param->_size_general_data); + + vhdl->set_signal ("sig_FF1",log2(_param->_size_general_data)+1); + vhdl->set_signal ("sig_FL1",log2(_param->_size_general_data)+1); + vhdl->set_signal ("sig_RES_FIND",_param->_size_general_data); + + vhdl->set_signal ("sig_SPR_IS_HERE",1); + vhdl->set_signal ("sig_MFSPR",_param->_size_spr); + vhdl->set_signal ("sig_MTSPR",_param->_size_spr); + + vhdl->set_signal ("sig_RES_SPECIAL",_param->_size_general_data); + + + vhdl->set_signal ("sig_EXECUTE_OUT_VAL", 1); + vhdl->set_signal ("sig_EXECUTE_OUT_UPDATE", 1); + + vhdl->set_signal ("reg_BUSY_OUT",1); + + if(_param->_have_port_context_id){ + vhdl->set_signal ("reg_EXECUTE_OUT_CONTEXT_ID", _param->_size_context_id); + vhdl->set_signal ("sig_EXECUTE_OUT_CONTEXT_ID", _param->_size_context_id);} + if(_param->_have_port_front_end_id){ + vhdl->set_signal ("reg_EXECUTE_OUT_FRONT_END_ID", _param->_size_front_end_id); + vhdl->set_signal ("sig_EXECUTE_OUT_FRONT_END_ID", _param->_size_front_end_id);} + if(_param->_have_port_ooo_engine_id){ + vhdl->set_signal ("reg_EXECUTE_OUT_OOO_ENGINE_ID", _param->_size_ooo_engine_id); + vhdl->set_signal ("sig_EXECUTE_OUT_OOO_ENGINE_ID", _param->_size_ooo_engine_id);} + if(_param->_have_port_rob_ptr){ + vhdl->set_signal ("reg_EXECUTE_OUT_PACKET_ID", _param->_size_rob_ptr); + vhdl->set_signal ("sig_EXECUTE_OUT_PACKET_ID", _param->_size_rob_ptr);} + vhdl->set_signal ("reg_EXECUTE_OUT_WRITE_RD", 1); + vhdl->set_signal ("sig_EXECUTE_OUT_WRITE_RD", 1); + vhdl->set_signal ("reg_EXECUTE_OUT_NUM_REG_RD", _param->_size_general_register); + vhdl->set_signal ("sig_EXECUTE_OUT_NUM_REG_RD", _param->_size_general_register); + vhdl->set_signal ("reg_EXECUTE_OUT_DATA_RD", _param->_size_general_data); + vhdl->set_signal ("sig_EXECUTE_OUT_DATA_RD", _param->_size_general_data); + vhdl->set_signal ("reg_EXECUTE_OUT_WRITE_RE", 1); + vhdl->set_signal ("sig_EXECUTE_OUT_WRITE_RE", 1); + vhdl->set_signal ("reg_EXECUTE_OUT_NUM_REG_RE", _param->_size_special_register); + vhdl->set_signal ("sig_EXECUTE_OUT_NUM_REG_RE", _param->_size_special_register); + vhdl->set_signal ("reg_EXECUTE_OUT_DATA_RE", _param->_size_special_data); + vhdl->set_signal ("sig_EXECUTE_OUT_DATA_RE", _param->_size_special_data); + vhdl->set_signal ("reg_EXECUTE_OUT_EXCEPTION", _param->_size_exception); + vhdl->set_signal ("sig_EXECUTE_OUT_EXCEPTION", _param->_size_exception); + vhdl->set_signal ("reg_EXECUTE_OUT_NO_SEQUENCE", 1); + vhdl->set_signal ("sig_EXECUTE_OUT_NO_SEQUENCE", 1); + vhdl->set_signal ("reg_EXECUTE_OUT_ADDRESS", _param->_size_instruction_address); + vhdl->set_signal ("sig_EXECUTE_OUT_ADDRESS", _param->_size_instruction_address); + + vhdl->set_type ("Tmac","array ("+toString(_param->_nb_context)+" downto 0) of "+std_logic(_param->_size_spr)); + vhdl->set_signal ("reg_MACLO ", "Tmac"); + vhdl->set_signal ("reg_MACHI ", "Tmac"); + log_printf(FUNC,Functionnal_unit,FUNCTION,"End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp (revision 116) @@ -32,5 +32,6 @@ execute_timing_t** timing , morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), - bool is_toplevel) + bool is_toplevel): + _functionnal_unit_scheme (FUNCTIONNAL_UNIT_SCHEME_GLOBAL_REGISTERFILE) { log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_msg_error.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_msg_error.cpp (revision 116) @@ -28,13 +28,18 @@ Parameters_test test("Functionnal_unit"); - for (uint32_t i=0; i<_nb_type; i++) - for (uint32_t j=0; j<_nb_operation; j++) - if (_timing[i][j]._delay != _timing[i][j]._latence) - test.error(toString(_("For the type '%d', and the operation '%d', the delay and the latence must be equal.\n"),i,j)); +// for (uint32_t i=0; i<_nb_type; i++) +// for (uint32_t j=0; j<_nb_operation; j++) +// if (_timing[i][j]._delay != _timing[i][j]._latence) +// test.error(toString(_("For the type '%d', and the operation '%d', the delay and the latence must be equal.\n"),i,j)); + +// if ((_timing[TYPE_ALU][OPERATION_ALU_ADD]._delay != 1) or +// (_timing[TYPE_ALU][OPERATION_ALU_ADD]._latence != 1)) +// test.error(toString(_("Valid timing for operation [%d][%d] is : {%d,%d}.\n"),TYPE_ALU,OPERATION_ALU_ADD,1,1)); + if (_have_groupe_MAC and ((_timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MAC ]._latence == 0) or (_timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MACRC]._latence == 0) or (_timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MSB ]._latence == 0))) - test.error("The functionnal unit implement a MAC unit, the latence to operation OPERATION_ALU_L_MAC, OPERATION_ALU_L_MACRC and OPERATION_ALU_L_MSB must be higher than 0.\n"); + test.error(_("The functionnal unit implements a MAC unit, the latence to operation OPERATION_ALU_L_MAC, OPERATION_ALU_L_MACRC and OPERATION_ALU_L_MSB must be higher than 0.\n")); log_printf(FUNC,Functionnal_unit,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/mkf.info =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/mkf.info (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/mkf.info (revision 116) @@ -0,0 +1,31 @@ + +# Execute_queue_0 +target_dep all Execute_queue_0.ngc +target_dep Execute_queue_0.ngc Execute_queue_0.prj +target_dep Execute_queue_0.prj Execute_queue_0_Pack.vhdl Execute_queue_0_queue_Pack.vhdl Execute_queue_0_queue.vhdl Execute_queue_0.vhdl + +# Execute_queue_1 +target_dep all Execute_queue_1.ngc +target_dep Execute_queue_1.ngc Execute_queue_1.prj +target_dep Execute_queue_1.prj Execute_queue_1_Pack.vhdl Execute_queue_1_queue_Pack.vhdl Execute_queue_1_queue.vhdl Execute_queue_1.vhdl + +# Execute_queue_2 +target_dep all Execute_queue_2.ngc +target_dep Execute_queue_2.ngc Execute_queue_2.prj +target_dep Execute_queue_2.prj Execute_queue_2_Pack.vhdl Execute_queue_2_queue_Pack.vhdl Execute_queue_2_queue.vhdl Execute_queue_2.vhdl + +# Execute_queue_3 +target_dep all Execute_queue_3.ngc +target_dep Execute_queue_3.ngc Execute_queue_3.prj +target_dep Execute_queue_3.prj Execute_queue_3_Pack.vhdl Execute_queue_3_queue_Pack.vhdl Execute_queue_3_queue.vhdl Execute_queue_3.vhdl + +# Execute_queue_4 +target_dep all Execute_queue_4.ngc +target_dep Execute_queue_4.ngc Execute_queue_4.prj +target_dep Execute_queue_4.prj Execute_queue_4_Pack.vhdl Execute_queue_4_queue_Pack.vhdl Execute_queue_4_queue.vhdl Execute_queue_4.vhdl + +# Execute_queue_5 +target_dep all Execute_queue_5.ngc +target_dep Execute_queue_5.ngc Execute_queue_5.prj +target_dep Execute_queue_5.prj Execute_queue_5_Pack.vhdl Execute_queue_5_queue_Pack.vhdl Execute_queue_5_queue.vhdl Execute_queue_5.vhdl + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/doc/fig/Write_queue.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/doc/fig/Write_queue.fig (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/doc/fig/Write_queue.fig (revision 116) @@ -0,0 +1,374 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +5 1 0 1 0 -1 50 -1 -1 0.000 0 1 0 0 5887.500 9150.500 5813 9150 5888 9225 5962 9150 +5 1 0 1 0 -1 50 -1 -1 0.000 0 1 0 0 8288.000 9150.000 8213 9150 8288 9225 8363 9150 +5 1 0 1 0 -1 50 -1 -1 0.000 0 1 0 0 7087.500 9150.500 7013 9150 7088 9225 7162 9150 +6 6899 3674 7424 4199 +1 3 0 1 0 7 50 -1 -1 0.000 1 0.5236 6963 3859 62 62 6963 3859 7018 3828 +1 3 0 1 0 7 50 -1 -1 0.000 1 0.5236 7314 3769 62 62 7314 3769 7371 3739 +1 3 0 1 0 7 50 -1 -1 0.000 1 0.5236 7173 4096 62 62 7173 4096 7228 4064 +3 0 0 1 0 7 50 -1 -1 0.000 0 0 0 3 + 7018 3828 7149 3785 7254 3793 + 0.000 1.000 0.000 +3 0 0 1 0 7 50 -1 -1 0.000 0 0 0 3 + 7201 4038 7288 3934 7298 3835 + 0.000 1.000 0.000 +3 0 0 1 0 7 50 -1 -1 0.000 0 0 0 3 + 7118 4059 7020 3995 6995 3916 + 0.000 1.000 0.000 +-6 +6 9974 4798 11624 5774 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 10499 4798 10499 5699 +4 2 0 50 -1 0 10 0.0000 0 150 390 10364 5324 OUT_\001 +4 0 0 50 -1 0 8 0.0000 0 105 900 10664 5249 NO_SEQUENCE\001 +4 0 0 50 -1 0 8 0.0000 0 75 585 10664 5399 ADDRESS\001 +4 0 0 50 -1 0 8 0.0000 0 90 780 10664 5549 CONTEXT_ID\001 +4 0 0 50 -1 0 8 0.0000 0 90 930 10664 5699 FRONT_END_ID\001 +4 0 0 50 -1 0 8 0.0000 0 90 690 10664 4949 PACKET_ID\001 +4 0 0 50 -1 0 8 0.0000 0 75 705 10664 5099 EXCEPTION\001 +-6 +6 2999 5324 4574 6299 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 3449 5324 3449 6224 +4 2 0 50 -1 0 10 0.0000 0 150 255 3299 5849 IN_\001 +4 0 0 50 -1 0 8 0.0000 0 75 705 3598 5624 EXCEPTION\001 +4 0 0 50 -1 0 8 0.0000 0 105 900 3598 5774 NO_SEQUENCE\001 +4 0 0 50 -1 0 8 0.0000 0 75 585 3598 5924 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0 5 + 7349 7874 7649 7874 7649 8474 7349 8474 7349 7874 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3 + 7349 7874 7649 8174 7349 8474 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 8849 7874 9299 7874 9299 8474 8849 8474 8849 7874 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3 + 8999 8474 9074 8398 9149 8474 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 8549 7874 8849 7874 8849 8474 8549 8474 8549 7874 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3 + 8549 7874 8849 8174 8549 8474 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3 + 5399 8474 5474 8398 5549 8474 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4 + 3 0 1.00 59.98 119.97 + 5699 8174 5924 8174 5924 8024 6149 8024 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4 + 3 0 1.00 59.98 119.97 + 6899 8174 7124 8174 7124 8024 7349 8024 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4 + 3 0 1.00 59.98 119.97 + 8099 8174 8324 8174 8324 8024 8549 8024 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 7649 7874 8099 7874 8099 8474 7649 8474 7649 7874 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3 + 7799 8474 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-1 -1 0.000 0 0 -1 0 0 2 + 7088 9225 7088 9712 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 8288 9225 8288 9712 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 9320 6901 10102 6907 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 9303 8177 10171 8177 +4 2 0 50 -1 0 10 0.0000 0 150 615 4649 3749 IN_VAL \001 +4 2 0 50 -1 0 10 0.0000 0 150 615 4649 4124 IN_ACK \001 +4 0 0 50 -1 0 10 0.0000 0 150 750 9899 3749 OUT_VAL\001 +4 0 0 50 -1 0 10 0.0000 0 150 750 9899 4199 OUT_ACK\001 +4 2 0 50 -1 0 8 0.0000 0 75 60 8774 8024 0\001 +4 2 0 50 -1 0 8 0.0000 0 75 60 8774 8398 1\001 +4 2 0 50 -1 0 8 0.0000 0 75 60 7574 8024 0\001 +4 2 0 50 -1 0 8 0.0000 0 75 60 7574 8398 1\001 +4 2 0 50 -1 0 8 0.0000 0 75 60 6374 8024 0\001 +4 2 0 50 -1 0 8 0.0000 0 75 60 6374 8398 1\001 Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_vhdl_xilinx_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_vhdl_xilinx_body.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_vhdl_xilinx_body.cpp (revision 116) @@ -20,5 +20,47 @@ { log_begin(Comparator,FUNCTION); - vhdl->set_body (""); + vhdl->set_body (0,"ins_c_compare_v9_0 : c_compare_v9_0"); + vhdl->set_body (1,"generic map ("); + vhdl->set_body (2,"c_width => "+toString(_param->_size_data)+","); + vhdl->set_body (2,"c_data_type => "+toString(!_param->_is_signed)+", -- 0 = signed, 1 = unsigned"); + std::string print_res_pin = ""; + switch (_param->_type) + { + case COMPARATOR_EQUAL : + vhdl->set_body (2,"c_has_a_eq_b => 1)"); + print_res_pin = "a_eq_b"; + break; + case COMPARATOR_NOT_EQUAL : + vhdl->set_body (2,"c_has_a_eq_b => 0,"); + vhdl->set_body (2,"c_has_a_ne_b => 1)"); + print_res_pin = "a_ne_b"; + break; + case COMPARATOR_GREATER : + vhdl->set_body (2,"c_has_a_eq_b => 0,"); + vhdl->set_body (2,"c_has_a_gt_b => 1)"); + print_res_pin = "a_gt_b"; + break; + case COMPARATOR_GREATER_OR_EQUAL : + vhdl->set_body (2,"c_has_a_eq_b => 0,"); + vhdl->set_body (2,"c_has_a_ge_b => 1)"); + print_res_pin = "a_ge_b"; + break; + case COMPARATOR_LESS : + vhdl->set_body (2,"c_has_a_eq_b => 0,"); + vhdl->set_body (2,"c_has_a_lt_b => 1)"); + print_res_pin = "a_lt_b"; + break; + case COMPARATOR_LESS_OR_EQUAL : + vhdl->set_body (2,"c_has_a_eq_b => 0,"); + vhdl->set_body (2,"c_has_a_le_b => 1)"); + print_res_pin = "a_le_b"; + break; + } + + vhdl->set_body (1,"port map ("); + vhdl->set_body (2,"a => in_COMPARE_DATA_0,"); + vhdl->set_body (2,"b => in_COMPARE_DATA_1,"); + vhdl->set_body (2,print_res_pin+" => out_COMPARE_TEST);"); + log_end(Comparator,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/configuration.cfg (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/configuration.cfg (revision 116) @@ -1,1 +1,5 @@ Multiplier +16 32 *2 #size_data +0 1 +1 #sign +6 32 *3 #latency +1 1 +1 #delay Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/include/test.h (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/include/test.h (revision 116) @@ -11,5 +11,5 @@ #endif -#define NB_ITERATION 1 +#define NB_ITERATION 128 #define CYCLE_MAX (1024*NB_ITERATION) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/src/main.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/src/main.cpp (revision 116) @@ -7,6 +7,7 @@ #include "Behavioural/Generic/Multiplier/SelfTest/include/test.h" +#include "Behavioural/include/Selftest.h" -#define NB_PARAMS 0 +#define NB_PARAMS 4 void usage (int argc, char * argv[]) @@ -14,5 +15,8 @@ err (_(" %s name_instance list_params.\n"),argv[0]); err (_("list_params is :\n")); - err (_(" * ()\n")); + err (_(" * size_data (uint32_t)\n")); + err (_(" * sign (bool )\n")); + err (_(" * latency (uint32_t)\n")); + err (_(" * delay (uint32_t)\n")); exit (1); @@ -30,5 +34,15 @@ uint32_t x = 1; + uint32_t _size_data; + bool _sign ; + uint32_t _latency ; + uint32_t _delay ; + string name = argv[x++]; + + SELFTEST0(_size_data,uint32_t,argv,x); + SELFTEST0(_sign ,bool ,argv,x); + SELFTEST0(_latency ,uint32_t,argv,x); + SELFTEST0(_delay ,uint32_t,argv,x); int _return = EXIT_SUCCESS; @@ -37,4 +51,8 @@ morpheo::behavioural::generic::multiplier::Parameters * param = new morpheo::behavioural::generic::multiplier::Parameters ( + _size_data, + _sign , + _latency , + _delay , true //is_toplevel ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/src/test.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/src/test.cpp (revision 116) @@ -9,4 +9,5 @@ #include "Behavioural/Generic/Multiplier/SelfTest/include/test.h" #include "Behavioural/include/Allocation.h" +#include "Common/include/BitManipulation.h" void test (string name, @@ -50,5 +51,20 @@ sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); sc_signal * in_NRESET = new sc_signal ("NRESET"); - + + sc_signal * in_MULTIPLIER_DATA_IN_0; + sc_signal * in_MULTIPLIER_DATA_IN_1; + sc_signal * in_MULTIPLIER_NSTALL ; + + sc_signal * out_MULTIPLIER_DATA_LSB_OUT; + sc_signal * out_MULTIPLIER_DATA_MSB_OUT; + + + ALLOC0_SC_SIGNAL( in_MULTIPLIER_DATA_IN_0,"in_MULTIPLIER_DATA_IN_0",Tdata_t ); + ALLOC0_SC_SIGNAL( in_MULTIPLIER_DATA_IN_1,"in_MULTIPLIER_DATA_IN_1",Tdata_t ); + ALLOC0_SC_SIGNAL( in_MULTIPLIER_NSTALL ,"in_MULTIPLIER_NSTALL ",Tcontrol_t); + + ALLOC0_SC_SIGNAL(out_MULTIPLIER_DATA_LSB_OUT,"out_MULTIPLIER_DATA_LSB_OUT",Tdata_t ); + ALLOC0_SC_SIGNAL(out_MULTIPLIER_DATA_MSB_OUT,"out_MULTIPLIER_DATA_MSB_OUT",Tdata_t ); + /******************************************************** * Instanciation @@ -60,4 +76,10 @@ (*(_Multiplier->in_NRESET)) (*(in_NRESET)); + INSTANCE0_SC_SIGNAL(_Multiplier, in_MULTIPLIER_DATA_IN_0); + INSTANCE0_SC_SIGNAL(_Multiplier, in_MULTIPLIER_DATA_IN_1); + INSTANCE0_SC_SIGNAL(_Multiplier, in_MULTIPLIER_NSTALL); + + INSTANCE0_SC_SIGNAL(_Multiplier,out_MULTIPLIER_DATA_LSB_OUT); + INSTANCE0_SC_SIGNAL(_Multiplier,out_MULTIPLIER_DATA_MSB_OUT); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -89,4 +111,107 @@ { LABEL("Iteration %d",iteration); + + uint64_t data0 = range(rand(),_param->_size_data); + uint64_t data1 = range(rand(),_param->_size_data); + + in_MULTIPLIER_DATA_IN_0->write(static_cast(data0)); + in_MULTIPLIER_DATA_IN_1->write(static_cast(data1)); + in_MULTIPLIER_NSTALL->write(static_cast(1)); + + sc_uint<32> res_lsb = 0; + sc_uint<32> res_msb = 0; + + switch (_param->_size_data) + { + case 8 : + { + if (_param->_sign){ // 0 = signed, 1 = unsigned + sc_uint<16> mask = 0xff; + sc_uint<16> tmp = (static_cast >(data0)) * (static_cast >(data1)); + res_lsb = tmp.range(7,0); + res_msb = tmp.range(15,8); + } + else{ + sc_int<8> data_0 = static_cast >(data0); + sc_int<8> data_1 = static_cast >(data1); + sc_int<16> tmp = (static_cast >(data_0) * + static_cast >(data_1)); + res_lsb = static_cast(_param->_mask & tmp); + res_msb = static_cast(_param->_mask & (tmp>>8)); + } + break; + } + case 16 : + { + if (_param->_sign){ // 0 = signed, 1 = unsigned + sc_uint<32> mask = 0xffff; + sc_uint<32> tmp = (static_cast >(data0)) * (static_cast >(data1)); + res_lsb = tmp.range(15,0); + res_msb = tmp.range(31,16); + } + else{ + sc_int<16> data_0 = static_cast >(data0); + sc_int<16> data_1 = static_cast >(data1); + sc_int<32> tmp = (static_cast >(data_0) * + static_cast >(data_1)); + res_lsb = static_cast(_param->_mask & tmp); + res_msb = static_cast(_param->_mask & (tmp>>16)); + + cout << "data_0 : " << std::hex << data_0 << std::dec << " - dec : " << data_0<< endl; + cout << "data_1 : " << std::hex << data_1 << std::dec << " - dec : " << data_1<< endl; + cout << "tmp : " << std::hex << tmp << std::dec << " - dec : " << tmp << endl; + cout << "res_lsb : " << std::hex << res_lsb << std::dec << endl; + cout << "res_msb : " << std::hex << res_msb << std::dec << endl; + } + break; + } + case 32 : + { + if (_param->_sign){ // 0 = signed, 1 = unsigned + sc_uint<32> data_0 = static_cast >(data0); + sc_uint<32> data_1 = static_cast >(data1); + sc_uint<64> tmp = (data0) * (data1); + res_lsb = static_cast(_param->_mask & tmp); + res_msb = static_cast(_param->_mask & (tmp>>32)); + + cout << "tmp : " << std::hex << tmp << std::dec << endl; + } + else{ + sc_int<32> data_0 = static_cast >(data0); + sc_int<32> data_1 = static_cast >(data1); + sc_int<64> tmp = (data0) * (data1); + res_lsb = static_cast(_param->_mask & tmp); + res_msb = static_cast(_param->_mask & (tmp>>32)); + + cout << "data_0 : " << std::hex << data_0 << std::dec << endl; + cout << "data_1 : " << std::hex << data_1 << std::dec << endl; + cout << "tmp : " << std::hex << tmp << std::dec << endl; + cout << "res_lsb : " << std::hex << res_lsb << std::dec << endl; + cout << "res_msb : " << std::hex << res_msb << std::dec << endl; + + + } + break; + } +// case 64 : +// { +// if (_param->_sign){ 0 = signed, 1 = unsigned +// uint64_t tmp = static_cast(data0) * static_cast(data1); +// res_lsb = tmp; +// } +// else{ +// int64_t tmp = static_cast< int64_t>(data0) * static_cast< int64_t>(data1); +// res_lsb = 0xffffffffffffffff&tmp; +// } +// break; +// } + default : + { + TEST_KO("Invalid size for the test."); + } + } + SC_START(_param->_latency); + TEST(Tdata_t,out_MULTIPLIER_DATA_LSB_OUT->read(),res_lsb); + TEST(Tdata_t,out_MULTIPLIER_DATA_MSB_OUT->read(),res_msb); SC_START(1); @@ -104,4 +229,11 @@ delete in_CLOCK; delete in_NRESET; + + DELETE0_SC_SIGNAL( in_MULTIPLIER_DATA_IN_0); + DELETE0_SC_SIGNAL( in_MULTIPLIER_DATA_IN_1); + DELETE0_SC_SIGNAL( in_MULTIPLIER_NSTALL); + DELETE0_SC_SIGNAL(out_MULTIPLIER_DATA_LSB_OUT); + DELETE0_SC_SIGNAL(out_MULTIPLIER_DATA_MSB_OUT); + } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Multiplier.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Multiplier.h (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Multiplier.h (revision 116) @@ -29,4 +29,5 @@ #include +#include namespace morpheo { @@ -57,13 +58,25 @@ #ifdef SYSTEMC // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ public : SC_CLOCK * in_CLOCK ; public : SC_IN (Tcontrol_t) * in_NRESET ; + // ~~~~~[ Interface : "multiplier" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tdata_t) * in_MULTIPLIER_DATA_IN_0; + public : SC_IN (Tdata_t) * in_MULTIPLIER_DATA_IN_1; + public : SC_IN (Tcontrol_t) * in_MULTIPLIER_NSTALL; + + public : SC_OUT(Tdata_t) * out_MULTIPLIER_DATA_LSB_OUT; + public : SC_OUT(Tdata_t) * out_MULTIPLIER_DATA_MSB_OUT; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - + private : std::vector * _pipeline; // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : Tdata_t sig_MULTIPLIER_DATA_IN_0; + private : Tdata_t sig_MULTIPLIER_DATA_IN_1; #endif @@ -99,5 +112,5 @@ #ifdef SYSTEMC public : void transition (void); -//public : void genMoore (void); + public : void genMealy (void); #endif @@ -106,4 +119,7 @@ private : void vhdl_declaration (Vhdl * & vhdl); private : void vhdl_body (Vhdl * & vhdl); + + private : void vhdl_xilinx_declaration (Vhdl * & vhdl); + private : void vhdl_xilinx_body (Vhdl * & vhdl); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Parameters.h (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Parameters.h (revision 116) @@ -11,4 +11,5 @@ #include "Behavioural/include/Parameters.h" #include "Common/include/Debug.h" +#include "Behavioural/Generic/Multiplier/include/Types.h" namespace morpheo { @@ -21,7 +22,18 @@ { //-----[ fields ]------------------------------------------------------------ + public : uint32_t _size_data; + public : bool _sign ; + public : uint32_t _latency ; + public : uint32_t _delay ; + + public : Tdata_t _mask ; +// public : Tdata_t _shift_sign; //-----[ methods ]----------------------------------------------------------- - public : Parameters (bool is_toplevel=false); + public : Parameters (uint32_t size_data, + bool sign , + uint32_t latency , + uint32_t delay , + bool is_toplevel=false); //public : Parameters (Parameters & param) ; public : ~Parameters (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Types.h (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/include/Types.h (revision 116) @@ -16,4 +16,11 @@ namespace multiplier { + typedef Tgeneral_data_t Tdata_t; + + typedef struct + { + Tdata_t MSB; + Tdata_t LSB; + } result_t; }; // end namespace multiplier Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier.cpp (revision 116) @@ -77,13 +77,17 @@ # endif -// log_printf(INFO,Multiplier,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + log_printf(INFO,Multiplier,FUNCTION,_("<%s> : Method - genMealy"),_name.c_str()); -// SC_METHOD (genMoore); -// dont_initialize (); -// sensitive << (*(in_CLOCK)).neg(); // need internal register + SC_METHOD (genMealy); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + + if (_param->_latency == 0) + sensitive << (*(in_MULTIPLIER_DATA_IN_0)) + << (*(in_MULTIPLIER_DATA_IN_1)); -// # ifdef SYSTEMCASS_SPECIFIC -// // List dependency information -// # endif +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_allocation.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_allocation.cpp (revision 116) @@ -53,4 +53,26 @@ in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); } + + // ~~~~~[ Interface "multiplier" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC0_INTERFACE_BEGIN("multiplier", IN, WEST, _("Multiplier's interface.")); + + ALLOC0_SIGNAL_IN ( in_MULTIPLIER_DATA_IN_0,"data_in_0",Tdata_t ,_param->_size_data); + ALLOC0_SIGNAL_IN ( in_MULTIPLIER_DATA_IN_1,"data_in_1",Tdata_t ,_param->_size_data); + ALLOC0_SIGNAL_IN ( in_MULTIPLIER_NSTALL ,"nstall" ,Tcontrol_t,1); + ALLOC0_SIGNAL_OUT(out_MULTIPLIER_DATA_LSB_OUT ,"data_lsb_out" ,Tdata_t ,_param->_size_data); + ALLOC0_SIGNAL_OUT(out_MULTIPLIER_DATA_MSB_OUT ,"data_msb_out" ,Tdata_t ,_param->_size_data); + + ALLOC0_INTERFACE_END(); + } + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC_BODY)) + { + _pipeline = new std::vector(_param->_latency+1); + } +#endif + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_deallocation.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_deallocation.cpp (revision 116) @@ -25,6 +25,20 @@ delete in_CLOCK ; delete in_NRESET; + + DELETE0_SIGNAL(in_MULTIPLIER_DATA_IN_0,_param->_size_data); + DELETE0_SIGNAL(in_MULTIPLIER_DATA_IN_1,_param->_size_data); + DELETE0_SIGNAL(in_MULTIPLIER_NSTALL ,1); + + DELETE0_SIGNAL(out_MULTIPLIER_DATA_LSB_OUT,_param->_size_data); + DELETE0_SIGNAL(out_MULTIPLIER_DATA_MSB_OUT,_param->_size_data); + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC_BODY)) + { + delete _pipeline; + } +#endif delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_genMealy.cpp (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_genMealy.cpp (revision 116) @@ -0,0 +1,34 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + + +#undef FUNCTION +#define FUNCTION "Multiplier::genMealy" + void Multiplier::genMealy (void) + { + log_begin(Multiplier,FUNCTION); + + PORT_WRITE(out_MULTIPLIER_DATA_LSB_OUT, _pipeline->at(0).LSB); + PORT_WRITE(out_MULTIPLIER_DATA_MSB_OUT, _pipeline->at(0).MSB); + + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_transition.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_transition.cpp (revision 116) @@ -20,9 +20,180 @@ { log_begin(Multiplier,FUNCTION); - + + // Test if stall + if (PORT_READ(in_MULTIPLIER_NSTALL)) + { + // Pop a slot of array + for (uint32_t i=1;i<_pipeline->size();i++) + _pipeline->at(i-1)=_pipeline->at(i); + + result_t data; + + switch (_param->_size_data) + { + case 8 : + { + if (_param->_sign) // 0 = signed, 1 = unsigned + { + sc_uint<8> data_0 = static_cast >(PORT_READ(in_MULTIPLIER_DATA_IN_0)); + sc_uint<8> data_1 = static_cast >(PORT_READ(in_MULTIPLIER_DATA_IN_1)); + sc_uint<16> tmp = (static_cast >(data_0) * + static_cast >(data_1)); + + data.LSB = static_cast(_param->_mask & tmp); + data.MSB = static_cast(_param->_mask & (tmp>>8)); + +// std::cout << "uint8 : data_0 : " << std::hex << data_0 << std::dec << std::endl; +// std::cout << "uint8 : data_1 : " << std::hex << data_1 << std::dec << std::endl; +// std::cout << "uint8 : tmp : " << std::hex << tmp << std::dec << std::endl; +// std::cout << "uint8 : lsb : " << std::hex << data.LSB << std::dec << std::endl; +// std::cout << "uint8 : msb : " << std::hex << data.MSB << std::dec << std::endl; + +// log_printf(TRACE,Multiplier,FUNCTION," * signed"); +// log_printf(TRACE,Multiplier,FUNCTION," * data0 = %llx(%lld)",data_0, data_0); +// log_printf(TRACE,Multiplier,FUNCTION," * data1 = %llx(%lld)",data_1, data_1); +// log_printf(TRACE,Multiplier,FUNCTION," * res = %llx(%lld)",tmp, tmp); +// log_printf(TRACE,Multiplier,FUNCTION," * LSB = %x (%d)",data.LSB, data.LSB); +// log_printf(TRACE,Multiplier,FUNCTION," * MSB = %x (%d)",data.MSB, data.MSB); + } + else + { + sc_int<8> data_0 = static_cast >(PORT_READ(in_MULTIPLIER_DATA_IN_0)); + sc_int<8> data_1 = static_cast >(PORT_READ(in_MULTIPLIER_DATA_IN_1)); + sc_int<16> tmp = (static_cast >(data_0) * + static_cast >(data_1)); + + data.LSB = static_cast(_param->_mask & tmp); + data.MSB = static_cast(_param->_mask & (tmp>>8)); + +// std::cout << "int8 : data_0 : " << std::hex << data_0 << std::dec << std::endl; +// std::cout << "int8 : data_1 : " << std::hex << data_1 << std::dec << std::endl; +// std::cout << "int8 : tmp : " << std::hex << tmp << std::dec << std::endl; +// std::cout << "int8 : lsb : " << std::hex << data.LSB << std::dec << std::endl; +// std::cout << "int8 : msb : " << std::hex << data.MSB << std::dec << std::endl; + +// log_printf(TRACE,Multiplier,FUNCTION," * signed"); +// log_printf(TRACE,Multiplier,FUNCTION," * data0 = %llx(%lld)",data_0, data_0); +// log_printf(TRACE,Multiplier,FUNCTION," * data1 = %llx(%lld)",data_1, data_1); +// log_printf(TRACE,Multiplier,FUNCTION," * res = %llx(%lld)",tmp, tmp); +// log_printf(TRACE,Multiplier,FUNCTION," * LSB = %x (%d)",data.LSB, data.LSB); +// log_printf(TRACE,Multiplier,FUNCTION," * MSB = %x (%d)",data.MSB, data.MSB); + } + break; + } + case 16 : + { + if (_param->_sign) // 0 = signed, 1 = unsigned + { + sc_uint<16> data_0 = static_cast >(PORT_READ(in_MULTIPLIER_DATA_IN_0)); + sc_uint<16> data_1 = static_cast >(PORT_READ(in_MULTIPLIER_DATA_IN_1)); + sc_uint<32> tmp = (static_cast >(data_0) * + static_cast >(data_1)); + + data.LSB = static_cast(_param->_mask & tmp); + data.MSB = static_cast(_param->_mask & (tmp>>16)); + +// std::cout << "uint16 : data_0 : " << std::hex << data_0 << std::dec << std::endl; +// std::cout << "uint16 : data_1 : " << std::hex << data_1 << std::dec << std::endl; +// std::cout << "uint16 : tmp : " << std::hex << tmp << std::dec << std::endl; +// std::cout << "uint16 : lsb : " << std::hex << data.LSB << std::dec << std::endl; +// std::cout << "uint16 : msb : " << std::hex << data.MSB << std::dec << std::endl; + +// log_printf(TRACE,Multiplier,FUNCTION," * signed"); +// log_printf(TRACE,Multiplier,FUNCTION," * data0 = %llx(%lld)",data_0, data_0); +// log_printf(TRACE,Multiplier,FUNCTION," * data1 = %llx(%lld)",data_1, data_1); +// log_printf(TRACE,Multiplier,FUNCTION," * res = %llx(%lld)",tmp, tmp); +// log_printf(TRACE,Multiplier,FUNCTION," * LSB = %x (%d)",data.LSB, data.LSB); +// log_printf(TRACE,Multiplier,FUNCTION," * MSB = %x (%d)",data.MSB, data.MSB); + } + else + { + sc_int<16> data_0 = static_cast >(PORT_READ(in_MULTIPLIER_DATA_IN_0)); + sc_int<16> data_1 = static_cast >(PORT_READ(in_MULTIPLIER_DATA_IN_1)); + sc_int<32> tmp = (static_cast >(data_0) * + static_cast >(data_1)); + + data.LSB = static_cast(_param->_mask & tmp); + data.MSB = static_cast(_param->_mask & (tmp>>16)); + + std::cout << "int16 : data_0 : " << std::hex << data_0 << std::dec << " - dec : " << data_0 << std::endl; + std::cout << "int16 : data_1 : " << std::hex << data_1 << std::dec << " - dec : " << data_1 << std::endl; + std::cout << "int16 : tmp : " << std::hex << tmp << std::dec << " - dec : " << tmp << std::endl; + std::cout << "int16 : lsb : " << std::hex << data.LSB << std::dec << std::endl; + std::cout << "int16 : msb : " << std::hex << data.MSB << std::dec << std::endl; + +// log_printf(TRACE,Multiplier,FUNCTION," * signed"); +// log_printf(TRACE,Multiplier,FUNCTION," * data0 = %llx(%lld)",data_0, data_0); +// log_printf(TRACE,Multiplier,FUNCTION," * data1 = %llx(%lld)",data_1, data_1); +// log_printf(TRACE,Multiplier,FUNCTION," * res = %llx(%lld)",tmp, tmp); +// log_printf(TRACE,Multiplier,FUNCTION," * LSB = %x (%d)",data.LSB, data.LSB); +// log_printf(TRACE,Multiplier,FUNCTION," * MSB = %x (%d)",data.MSB, data.MSB); + } + break; + } + case 32 : + { + if (_param->_sign) // 0 = signed, 1 = unsigned + { + sc_uint<32> data_0 = static_cast >(PORT_READ(in_MULTIPLIER_DATA_IN_0)); + sc_uint<32> data_1 = static_cast >(PORT_READ(in_MULTIPLIER_DATA_IN_1)); + sc_uint<64> tmp = (static_cast >(data_0) * + static_cast >(data_1)); + + data.LSB = static_cast(_param->_mask & tmp); + data.MSB = static_cast(_param->_mask & (tmp>>32)); + +// std::cout << "uint32 : data_0 : " << std::hex << data_0 << std::dec << std::endl; +// std::cout << "uint32 : data_1 : " << std::hex << data_1 << std::dec << std::endl; +// std::cout << "uint32 : tmp : " << std::hex << tmp << std::dec << std::endl; +// std::cout << "uint32 : lsb : " << std::hex << data.LSB << std::dec << std::endl; +// std::cout << "uint32 : msb : " << std::hex << data.MSB << std::dec << std::endl; + +// log_printf(TRACE,Multiplier,FUNCTION," * signed"); +// log_printf(TRACE,Multiplier,FUNCTION," * data0 = %llx(%lld)",data_0, data_0); +// log_printf(TRACE,Multiplier,FUNCTION," * data1 = %llx(%lld)",data_1, data_1); +// log_printf(TRACE,Multiplier,FUNCTION," * res = %llx(%lld)",tmp, tmp); +// log_printf(TRACE,Multiplier,FUNCTION," * LSB = %x (%d)",data.LSB, data.LSB); +// log_printf(TRACE,Multiplier,FUNCTION," * MSB = %x (%d)",data.MSB, data.MSB); + } + else + { + sc_int<32> data_0 = static_cast >(PORT_READ(in_MULTIPLIER_DATA_IN_0)); + sc_int<32> data_1 = static_cast >(PORT_READ(in_MULTIPLIER_DATA_IN_1)); + sc_int<64> tmp = (static_cast >(data_0) * + static_cast >(data_1)); + + data.LSB = static_cast(_param->_mask & tmp); + data.MSB = static_cast(_param->_mask & (tmp>>32)); + +// std::cout << "int32 : data_0 : " << std::hex << data_0 << std::dec << std::endl; +// std::cout << "int32 : data_1 : " << std::hex << data_1 << std::dec << std::endl; +// std::cout << "int32 : tmp : " << std::hex << tmp << std::dec << std::endl; +// std::cout << "int32 : lsb : " << std::hex << data.LSB << std::dec << std::endl; +// std::cout << "int32 : msb : " << std::hex << data.MSB << std::dec << std::endl; + +// log_printf(TRACE,Multiplier,FUNCTION," * signed"); +// log_printf(TRACE,Multiplier,FUNCTION," * data0 = %llx(%lld)",data_0, data_0); +// log_printf(TRACE,Multiplier,FUNCTION," * data1 = %llx(%lld)",data_1, data_1); +// log_printf(TRACE,Multiplier,FUNCTION," * res = %llx(%lld)",tmp, tmp); +// log_printf(TRACE,Multiplier,FUNCTION," * LSB = %x (%d)",data.LSB, data.LSB); +// log_printf(TRACE,Multiplier,FUNCTION," * MSB = %x (%d)",data.MSB, data.MSB); + } + break; + } + default : + { + break; + } + } + + _pipeline->at(_param->_latency-1) = data; + + } + #if defined(STATISTICS) or defined(VHDL_TESTBENCH) end_cycle (); #endif - + log_end(Multiplier,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl.cpp (revision 116) @@ -27,6 +27,12 @@ _component->vhdl_instance(vhdl); + // default architecture vhdl_declaration (vhdl); vhdl_body (vhdl); + + // Xilinx architecture + vhdl->set_architecture("xilinx"); + vhdl_xilinx_declaration (vhdl); + vhdl_xilinx_body (vhdl); vhdl->generate_file(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl_xilinx_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl_xilinx_body.cpp (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl_xilinx_body.cpp (revision 116) @@ -0,0 +1,53 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + +#undef FUNCTION +#define FUNCTION "Multiplier::vhdl_xilinx_body" + void Multiplier::vhdl_xilinx_body (Vhdl * & vhdl) + { + + log_begin(Multiplier,FUNCTION); + vhdl->set_body (0,"ins_mult_gen_v9_0 : mult_gen_v9_0"); + vhdl->set_body (1,"generic map ("); + vhdl->set_body (2," c_xdevicefamily => \"virtex4\", -- specifies target Xilinx FPGA name"); + vhdl->set_body (2," c_a_width => "+toString(_param->_size_data)+", -- width of A port"); + vhdl->set_body (2," c_a_type => "+toString(_param->_sign)+", -- datatype of A port"); + vhdl->set_body (2," c_b_width => "+toString(_param->_size_data)+", -- width of B port"); + vhdl->set_body (2," c_b_type => "+toString(_param->_sign)+", -- datatype of B port"); + vhdl->set_body (2," c_out_high => "+toString((_param->_size_data*2)-1)+", -- MSB of P output port (N-1 downto 0 convention)"); + vhdl->set_body (2," c_mult_type => 1, -- Type of multiplier to implement"); + vhdl->set_body (2," c_opt_goal => 1, -- Optimization of multiplier"); + vhdl->set_body (2," c_has_ce => 1, -- Use clock enable on all registers"); + vhdl->set_body (2," c_pipe_stages => "+toString(_param->_latency)+") -- Number of register stages required"); + + vhdl->set_body (1,"port map ("); + vhdl->set_body (2,"clk => in_CLOCK ,"); + vhdl->set_body (2,"a => in_MULTIPLIER_DATA_IN_0,"); + vhdl->set_body (2,"b => in_MULTIPLIER_DATA_IN_1,"); + vhdl->set_body (2,"ce => in_MULTIPLIER_NSTALL ,"); + vhdl->set_body (2,"p => sig_MULTIPLIER_DATA_OUT);"); + + vhdl->set_body (0,"out_MULTIPLIER_DATA_LSB_OUT <= sig_MULTIPLIER_DATA_OUT("+toString(_param->_size_data-1)+" downto 0);"); + vhdl->set_body (0,"out_MULTIPLIER_DATA_MSB_OUT <= sig_MULTIPLIER_DATA_OUT("+toString((_param->_size_data*2)-1)+" downto "+toString(_param->_size_data)+");"); + + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl_xilinx_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl_xilinx_declaration.cpp (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Multiplier_vhdl_xilinx_declaration.cpp (revision 116) @@ -0,0 +1,34 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Multiplier/include/Multiplier.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace multiplier { + +#undef FUNCTION +#define FUNCTION "Multiplier::vhdl_xilinx_declaration" + void Multiplier::vhdl_xilinx_declaration (Vhdl * & vhdl) + { + log_begin(Multiplier,FUNCTION); + + vhdl->set_library("XilinxCoreLib","mult_gen_v9_0_comp","all"); + + vhdl->set_signal ("sig_MULTIPLIER_DATA_OUT", _param->_size_data*2); + + log_end(Multiplier,FUNCTION); + }; + +}; // end namespace multiplier +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters.cpp (revision 116) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/Multiplier/include/Parameters.h" +#include "Common/include/BitManipulation.h" namespace morpheo { @@ -16,7 +17,19 @@ #undef FUNCTION #define FUNCTION "Multiplier::Parameters" - Parameters::Parameters (bool is_toplevel) + Parameters::Parameters (uint32_t size_data, + bool sign , + uint32_t latency , + uint32_t delay , + bool is_toplevel) { + log_begin(Multiplier,FUNCTION); + + _size_data = size_data; + _sign = sign ; + _latency = latency ; + _delay = delay ; + _mask = gen_mask(_size_data); +// _shift_sign = size_data-1; test(); @@ -35,5 +48,5 @@ // { // log_begin(Multiplier,FUNCTION); -// test(); +// test();x // log_end(Multiplier,FUNCTION); // }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters_msg_error.cpp (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/src/Parameters_msg_error.cpp (revision 116) @@ -24,4 +24,13 @@ Parameters_test test ("Multiplier"); + if ((_size_data < 2) or (_size_data > 64)) + test.error(toString(_("size_data (%d) 's valid range is 2 to 64.\n"),_size_data)); + + if (_delay > 1) + test.error(toString(_("delay must be set at 1\n"))); + + if (_latency > 32) + test.error(toString(_("latency's valid range is 0 to 32\n"))); + log_end(Multiplier,FUNCTION); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/mkf.info =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/mkf.info (revision 116) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/mkf.info (revision 116) @@ -0,0 +1,101 @@ + +# Queue_00 +target_dep all Queue_00.ngc +target_dep Queue_00.ngc Queue_00.prj +target_dep Queue_00.prj Queue_00_Pack.vhdl Queue_00.vhdl + +# Queue_01 +target_dep all Queue_01.ngc +target_dep Queue_01.ngc Queue_01.prj +target_dep Queue_01.prj Queue_01_Pack.vhdl Queue_01.vhdl + +# Queue_02 +target_dep all Queue_02.ngc +target_dep Queue_02.ngc Queue_02.prj +target_dep Queue_02.prj Queue_02_Pack.vhdl Queue_02.vhdl + +# Queue_03 +target_dep all Queue_03.ngc +target_dep Queue_03.ngc Queue_03.prj +target_dep Queue_03.prj Queue_03_Pack.vhdl Queue_03.vhdl + +# Queue_04 +target_dep all Queue_04.ngc +target_dep Queue_04.ngc Queue_04.prj +target_dep Queue_04.prj Queue_04_Pack.vhdl Queue_04.vhdl + +# Queue_05 +target_dep all Queue_05.ngc +target_dep Queue_05.ngc Queue_05.prj +target_dep Queue_05.prj Queue_05_Pack.vhdl Queue_05.vhdl + +# Queue_06 +target_dep all Queue_06.ngc +target_dep Queue_06.ngc Queue_06.prj +target_dep Queue_06.prj Queue_06_Pack.vhdl Queue_06.vhdl + +# Queue_07 +target_dep all Queue_07.ngc +target_dep Queue_07.ngc Queue_07.prj +target_dep Queue_07.prj Queue_07_Pack.vhdl Queue_07.vhdl + +# Queue_08 +target_dep all Queue_08.ngc +target_dep Queue_08.ngc Queue_08.prj +target_dep Queue_08.prj Queue_08_Pack.vhdl Queue_08.vhdl + +# Queue_09 +target_dep all Queue_09.ngc +target_dep Queue_09.ngc Queue_09.prj +target_dep Queue_09.prj Queue_09_Pack.vhdl Queue_09.vhdl + +# Queue_10 +target_dep all Queue_10.ngc +target_dep Queue_10.ngc Queue_10.prj +target_dep Queue_10.prj Queue_10_Pack.vhdl Queue_10.vhdl + +# Queue_11 +target_dep all Queue_11.ngc +target_dep Queue_11.ngc Queue_11.prj +target_dep Queue_11.prj Queue_11_Pack.vhdl Queue_11.vhdl + +# Queue_12 +target_dep all Queue_12.ngc +target_dep Queue_12.ngc Queue_12.prj +target_dep Queue_12.prj Queue_12_Pack.vhdl Queue_12.vhdl + +# Queue_13 +target_dep all Queue_13.ngc +target_dep Queue_13.ngc Queue_13.prj +target_dep Queue_13.prj Queue_13_Pack.vhdl Queue_13.vhdl + +# Queue_14 +target_dep all Queue_14.ngc +target_dep Queue_14.ngc Queue_14.prj +target_dep Queue_14.prj Queue_14_Pack.vhdl Queue_14.vhdl + +# Queue_15 +target_dep all Queue_15.ngc +target_dep Queue_15.ngc Queue_15.prj +target_dep Queue_15.prj Queue_15_Pack.vhdl Queue_15.vhdl + +# Queue_16 +target_dep all Queue_16.ngc +target_dep Queue_16.ngc Queue_16.prj +target_dep Queue_16.prj Queue_16_Pack.vhdl Queue_16.vhdl + +# Queue_17 +target_dep all Queue_17.ngc +target_dep Queue_17.ngc Queue_17.prj +target_dep Queue_17.prj Queue_17_Pack.vhdl Queue_17.vhdl + +# Queue_18 +target_dep all Queue_18.ngc +target_dep Queue_18.ngc Queue_18.prj +target_dep Queue_18.prj Queue_18_Pack.vhdl Queue_18.vhdl + +# Queue_19 +target_dep all Queue_19.ngc +target_dep Queue_19.ngc Queue_19.prj +target_dep Queue_19.prj Queue_19_Pack.vhdl Queue_19.vhdl + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis (revision 116) @@ -95,5 +95,5 @@ $(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc &> $@; -$(DIR_WORK) : +$(DIR_WORK) : $(XILINX_CORELIB) @\ $(ECHO) "Create work-space : $@"; \ @@ -104,4 +104,12 @@ $(ECHO) "Run manualy \"$(XILINX_COMPXLIB)\" with $(XILINX_CORELIB) directory"; \ fi; + +$(XILINX_CORELIB) : + @\ + $(ECHO) "Create Corelib : $@"; \ + $(MODELTECH_ENV); $(XILINX_COMPXLIB) + +# $(MODELTECH_ENV); $(XILINX_COMPXLIB) -s mti_se -arch all -lib all -l vhdl -dir $(XILINX_CORELIB) -w -p $(MODELTECH_BIN) -smartmodel_setup + $(DIR_LOG)/%.sim.log : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf (revision 116) @@ -3,8 +3,11 @@ # -all: _Generic/Queue/SelfTest _Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest _Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest +all: _Generic/Queue/SelfTest _Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest _Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest _Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest _Generic/Queue/SelfTest: gmake all -C Generic/Queue/SelfTest + +_Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest: + gmake all -C Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest _Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest: @@ -16,4 +19,5 @@ clean: gmake clean -C Generic/Queue/SelfTest + gmake clean -C Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest gmake clean -C Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest gmake clean -C Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest @@ -23,4 +27,5 @@ install: gmake install -C Generic/Queue/SelfTest + gmake install -C Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest gmake install -C Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest gmake install -C Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h (revision 116) @@ -40,15 +40,15 @@ { TYPE_ALU = 0x0, // 00000 - unit multiple - TYPE_SHIFT = 0x1, // 00000 - unit multiple - TYPE_MOVE = 0x2, // 00000 - unit multiple - TYPE_TEST = 0x3, // 00000 - unit multiple - TYPE_MUL = 0x4, // 00000 - unit multiple - TYPE_DIV = 0x5, // 00000 - unit multiple, type optionnal - TYPE_EXTEND = 0x6, // 00000 - unit multiple, type optionnal - TYPE_FIND = 0x7, // 00000 - unit multiple, type optionnal - TYPE_SPECIAL = 0x8, // 00000 - unit uniq - TYPE_CUSTOM = 0x9, // 00000 - unit uniq , type optionnal - TYPE_BRANCH = 0xa, // 00000 - unit multiple - TYPE_MEMORY = 0xb // 00000 - unit uniq , type exclusive + TYPE_SHIFT = 0x1, // 00001 - unit multiple + TYPE_MOVE = 0x2, // 00010 - unit multiple + TYPE_TEST = 0x3, // 00011 - unit multiple + TYPE_MUL = 0x4, // 00100 - unit multiple + TYPE_DIV = 0x5, // 00101 - unit multiple, type optionnal + TYPE_EXTEND = 0x6, // 00110 - unit multiple, type optionnal + TYPE_FIND = 0x7, // 00111 - unit multiple, type optionnal + TYPE_SPECIAL = 0x8, // 01000 - unit uniq + TYPE_CUSTOM = 0x9, // 01001 - unit uniq , type optionnal + TYPE_BRANCH = 0xa, // 01010 - unit multiple + TYPE_MEMORY = 0xb // 01011 - unit uniq } type_t; @@ -202,43 +202,53 @@ //---------------------------------------------[ Functionnal Unit ]----- -# define OPERATION_ALU_L_ADD 0x1 // 000_0000 l.add , l.addi -# define OPERATION_ALU_L_ADDC 0x2 // 000_0000 l.addc , l.addic -# define OPERATION_ALU_L_SUB 0x4 // 000_0000 l.sub -# define OPERATION_ALU_L_AND 0x8 // 000_0000 l.and , l.andi -# define OPERATION_ALU_L_OR 0x10 // 000_0000 l.or , l.ori -# define OPERATION_ALU_L_XOR 0x20 // 000_0000 l.xor , l.xori - -# define OPERATION_SHIFT_L_SLL 0x1 // 000_0000 l.sll , l.slli -# define OPERATION_SHIFT_L_SRA 0x2 // 000_0000 l.sra , l.srai -# define OPERATION_SHIFT_L_SRL 0x4 // 000_0000 l.srl , l.srli -# define OPERATION_SHIFT_L_ROR 0x8 // 000_0000 l.ror , l.rori - -# define OPERATION_MOVE_L_MOVHI 0x1 // 000_0000 l.movhi -# define OPERATION_MOVE_L_CMOV 0x2 // 000_0000 l.cmov - -# define OPERATION_TEST_L_SFGES 0x41 // 000_0000 l.sfges , l.sfges -# define OPERATION_TEST_L_SFGEU 0x1 // 000_0000 l.sfgeu , l.sfgeu -# define OPERATION_TEST_L_SFGTS 0x42 // 000_0000 L.sfgts , l.sfgts -# define OPERATION_TEST_L_SFGTU 0x2 // 000_0000 l.sfgtu , l.sfgtu -# define OPERATION_TEST_L_SFLES 0x44 // 000_0000 l.sfles , l.sfles -# define OPERATION_TEST_L_SFLEU 0x4 // 000_0000 l.sfleu , l.sfleu -# define OPERATION_TEST_L_SFLTS 0x48 // 000_0000 l.sflts , l.sflts -# define OPERATION_TEST_L_SFLTU 0x8 // 000_0000 l.sfltu , l.sfltu -# define OPERATION_TEST_L_SFEQ 0x10 // 000_0000 l.sfeq , l.sfeqi -# define OPERATION_TEST_L_SFNE 0x20 // 000_0000 l.sfne , l.sfnei - -# define OPERATION_MUL_L_MUL 0x1 // 000_0000 l.mul , l.muli -# define OPERATION_MUL_L_MULU 0x2 // 000_0000 l.mulu - -# define OPERATION_DIV_L_DIV 0x1 // 000_0000 l.div -# define OPERATION_DIV_L_DIVU 0x2 // 000_0000 l.divu - -# define OPERATION_EXTEND_L_EXTEND_Z 0x1 // 000_0000 l.extbz , l.exthz, l.extwz -# define OPERATION_EXTEND_L_EXTEND_S 0x2 // 000_0000 l.extbs , l.exths, l.extws - -# define OPERATION_FIND_L_FF1 0x1 // 000_0000 l.ff1 -# define OPERATION_FIND_L_FL1 0x2 // 000_0000 l.fl1 - -# define OPERATION_SPECIAL_L_NOP 0x7f // 000_0000 l.nop + + // WARNING : Operations are coded in a one-hot implementation that is used in the functional unit's vhdl code. + // Do not change that (you can still change the values as long as it respects the one-hot encoding). + +# define OPERATION_ALU_L_ADD 0x1 // 000_0001 l.add , l.addi +# define OPERATION_ALU_L_ADDC 0x2 // 000_0010 l.addc , l.addic +# define OPERATION_ALU_L_SUB 0x4 // 000_0100 l.sub +# define OPERATION_ALU_L_AND 0x8 // 000_1000 l.and , l.andi +# define OPERATION_ALU_L_OR 0x10 // 001_0000 l.or , l.ori +# define OPERATION_ALU_L_XOR 0x20 // 010_0000 l.xor , l.xori + + // WARNING : Shift and rotate operation codes are hard-coded in the functional unit's vhdl code, + // with bit 0 corresponding to the direction (0 for right, and 1 for left), + // bit 1 to the type (0 for shift, 1 for rotate) and bit 2 is to be set to 0 for a logic + // operation and 1 for an arithmetic operation. + // Do not change that (unless you respect the one-hot encoding described above). + +# define OPERATION_SHIFT_L_SLL 0x1 // 000_0001 l.sll , l.slli +# define OPERATION_SHIFT_L_SRA 0x4 // 000_0100 l.sra , l.srai +# define OPERATION_SHIFT_L_SRL 0x0 // 000_0000 l.srl , l.srli +# define OPERATION_SHIFT_L_ROR 0x2 // 000_0010 l.ror , l.rori + +# define OPERATION_MOVE_L_MOVHI 0x1 // 000_0001 l.movhi +# define OPERATION_MOVE_L_CMOV 0x2 // 000_0010 l.cmov + +# define OPERATION_TEST_L_SFGES 0x45 // 100_0101 l.sfges , l.sfges +# define OPERATION_TEST_L_SFGEU 0x5 // 000_0101 l.sfgeu , l.sfgeu +# define OPERATION_TEST_L_SFGTS 0x46 // 100_0110 L.sfgts , l.sfgts +# define OPERATION_TEST_L_SFGTU 0x6 // 000_0110 l.sfgtu , l.sfgtu +# define OPERATION_TEST_L_SFLES 0x49 // 100_1001 l.sfles , l.sfles +# define OPERATION_TEST_L_SFLEU 0x9 // 000_1001 l.sfleu , l.sfleu +# define OPERATION_TEST_L_SFLTS 0x4A // 100_1010 l.sflts , l.sflts +# define OPERATION_TEST_L_SFLTU 0xA // 000_1010 l.sfltu , l.sfltu +# define OPERATION_TEST_L_SFEQ 0x10 // 001_0000 l.sfeq , l.sfeqi +# define OPERATION_TEST_L_SFNE 0x20 // 010_0000 l.sfne , l.sfnei + +# define OPERATION_MUL_L_MUL 0x1 // 000_0001 l.mul , l.muli +# define OPERATION_MUL_L_MULU 0x2 // 000_0010 l.mulu + +# define OPERATION_DIV_L_DIV 0x1 // 000_0001 l.div +# define OPERATION_DIV_L_DIVU 0x2 // 000_0010 l.divu + +# define OPERATION_EXTEND_L_EXTEND_Z 0x1 // 000_0001 l.extbz , l.exthz, l.extwz +# define OPERATION_EXTEND_L_EXTEND_S 0x2 // 000_0010 l.extbs , l.exths, l.extws + +# define OPERATION_FIND_L_FF1 0x1 // 000_0001 l.ff1 +# define OPERATION_FIND_L_FL1 0x2 // 000_0010 l.fl1 + +# define OPERATION_SPECIAL_L_NOP 0x7f // 111_1111 l.nop # define OPERATION_SPECIAL_L_MFSPR 0x1 // 000_0001 l.mfspr # define OPERATION_SPECIAL_L_MTSPR 0x2 // 000_0010 l.mtspr @@ -253,8 +263,8 @@ # define OPERATION_SPECIAL_L_TRAP 0x42 // 100_0010 l.trap -# define OPERATION_BRANCH_NONE 0x1 // 000_0000 l.j -# define OPERATION_BRANCH_L_TEST_NF 0x2 // 000_0000 l.bnf -# define OPERATION_BRANCH_L_TEST_F 0x4 // 000_0000 l.bf -# define OPERATION_BRANCH_L_JALR 0x8 // 000_0000 l.jal , l.jalr , l.jr +# define OPERATION_BRANCH_NONE 0x1 // 000_0001 l.j +# define OPERATION_BRANCH_L_TEST_NF 0x2 // 000_0010 l.bnf +# define OPERATION_BRANCH_L_TEST_F 0x4 // 000_0100 l.bf +# define OPERATION_BRANCH_L_JALR 0x8 // 000_1000 l.jal , l.jalr , l.jr //-------------------------------------------------------[ Custom ]----- @@ -342,4 +352,5 @@ # define EXCEPTION_DECOD_BUS_ERROR 0x02 // Access at a invalid physical address + // WARNING : Keep EXCEPTION_ALU_NONE value at 0x00 (kind of hard coded in functional unit's vhdl code). # define EXCEPTION_ALU_NONE 0x00 // Functionnal unit generate none exception # define EXCEPTION_ALU_RANGE 0x0b // Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 116) @@ -10,8 +10,8 @@ #define MORPHEO_MAJOR_VERSION "0" #define MORPHEO_MINOR_VERSION "2" -#define MORPHEO_REVISION "115" +#define MORPHEO_REVISION "116" #define MORPHEO_CODENAME "Castor" -#define MORPHEO_DATE_DAY "20" +#define MORPHEO_DATE_DAY "30" #define MORPHEO_DATE_MONTH "04" #define MORPHEO_DATE_YEAR "2009" Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info (revision 115) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info (revision 116) @@ -15,5 +15,5 @@ # build src directory content -target_dep all Generic/Queue/SelfTest + target_dep all Generic/Queue/SelfTest #target_dep all Generic/RegisterFile/RegisterFile_Monolithic/SelfTest #target_dep all Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest @@ -23,7 +23,8 @@ #target_dep all Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest #target_dep all Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest -target_dep all Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest -target_dep all Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest -target_dep all Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest + target_dep all Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest + target_dep all Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest + target_dep all Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest +#target_dep all Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest