Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp	(revision 113)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp	(revision 117)
@@ -70,5 +70,58 @@
   sc_signal<Tcontrol_t>                  * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
-    // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  sc_signal<Tcontrol_t        > **  in_MEMORY_IN_VAL                  ;
+  sc_signal<Tcontrol_t        > ** out_MEMORY_IN_ACK                  ;
+  sc_signal<Tcontext_t        > **  in_MEMORY_IN_CONTEXT_ID           ;
+  sc_signal<Tcontext_t        > **  in_MEMORY_IN_FRONT_END_ID         ;
+  sc_signal<Tcontext_t        > **  in_MEMORY_IN_OOO_ENGINE_ID        ;
+  sc_signal<Tpacket_t         > **  in_MEMORY_IN_PACKET_ID            ;
+  sc_signal<Toperation_t      > **  in_MEMORY_IN_OPERATION            ;
+  sc_signal<Ttype_t           > **  in_MEMORY_IN_TYPE                 ;
+  sc_signal<Tlsq_ptr_t        > **  in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t        > **  in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
+  sc_signal<Tcontrol_t        > **  in_MEMORY_IN_HAS_IMMEDIAT         ;
+  sc_signal<Tgeneral_data_t   > **  in_MEMORY_IN_IMMEDIAT             ;
+  sc_signal<Tgeneral_data_t   > **  in_MEMORY_IN_DATA_RA              ;
+  sc_signal<Tgeneral_data_t   > **  in_MEMORY_IN_DATA_RB              ;
+  sc_signal<Tspecial_data_t   > **  in_MEMORY_IN_DATA_RC              ;
+  sc_signal<Tcontrol_t        > **  in_MEMORY_IN_WRITE_RD             ;
+  sc_signal<Tgeneral_address_t> **  in_MEMORY_IN_NUM_REG_RD           ;
+  sc_signal<Tcontrol_t        > **  in_MEMORY_IN_WRITE_RE             ;
+  sc_signal<Tspecial_address_t> **  in_MEMORY_IN_NUM_REG_RE           ;
+  sc_signal<Tcontrol_t        > ** out_MEMORY_OUT_VAL                 ;
+  sc_signal<Tcontrol_t        > **  in_MEMORY_OUT_ACK                 ;
+  sc_signal<Tcontext_t        > ** out_MEMORY_OUT_CONTEXT_ID          ;
+  sc_signal<Tcontext_t        > ** out_MEMORY_OUT_FRONT_END_ID        ;
+  sc_signal<Tcontext_t        > ** out_MEMORY_OUT_OOO_ENGINE_ID       ;
+  sc_signal<Tpacket_t         > ** out_MEMORY_OUT_PACKET_ID           ;
+//sc_signal<Toperation_t      > ** out_MEMORY_OUT_OPERATION           ;
+//sc_signal<Ttype_t           > ** out_MEMORY_OUT_TYPE                ;
+  sc_signal<Tcontrol_t        > ** out_MEMORY_OUT_WRITE_RD            ;
+  sc_signal<Tgeneral_address_t> ** out_MEMORY_OUT_NUM_REG_RD          ;
+  sc_signal<Tgeneral_data_t   > ** out_MEMORY_OUT_DATA_RD             ;
+  sc_signal<Tcontrol_t        > ** out_MEMORY_OUT_WRITE_RE            ;
+  sc_signal<Tspecial_address_t> ** out_MEMORY_OUT_NUM_REG_RE          ;
+  sc_signal<Tspecial_data_t   > ** out_MEMORY_OUT_DATA_RE             ;
+  sc_signal<Texception_t      > ** out_MEMORY_OUT_EXCEPTION           ;
+  sc_signal<Tcontrol_t        > ** out_MEMORY_OUT_NO_SEQUENCE         ;
+  sc_signal<Taddress_t        > ** out_MEMORY_OUT_ADDRESS             ;
+  sc_signal<Tcontrol_t        > ** out_DCACHE_REQ_VAL                 ;
+  sc_signal<Tcontrol_t        > **  in_DCACHE_REQ_ACK                 ;
+  sc_signal<Tcontext_t        > ** out_DCACHE_REQ_CONTEXT_ID          ;
+  sc_signal<Tpacket_t         > ** out_DCACHE_REQ_PACKET_ID           ;
+  sc_signal<Tdcache_address_t > ** out_DCACHE_REQ_ADDRESS             ;
+  sc_signal<Tdcache_type_t    > ** out_DCACHE_REQ_TYPE                ;
+  sc_signal<Tdcache_data_t    > ** out_DCACHE_REQ_WDATA               ;
+  sc_signal<Tcontrol_t        > **  in_DCACHE_RSP_VAL                 ;
+  sc_signal<Tcontrol_t        > ** out_DCACHE_RSP_ACK                 ;
+  sc_signal<Tcontext_t        > **  in_DCACHE_RSP_CONTEXT_ID          ;
+  sc_signal<Tpacket_t         > **  in_DCACHE_RSP_PACKET_ID           ;
+  sc_signal<Tdcache_data_t    > **  in_DCACHE_RSP_RDATA               ;
+  sc_signal<Tdcache_error_t   > **  in_DCACHE_RSP_ERROR               ;
+  sc_signal<Tcontrol_t        > ** out_BYPASS_MEMORY_VAL              ;
+  sc_signal<Tcontext_t        > ** out_BYPASS_MEMORY_OOO_ENGINE_ID    ;
+  sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG          ;
+  sc_signal<Tgeneral_data_t   > ** out_BYPASS_MEMORY_DATA             ;
+
   ALLOC1_SC_SIGNAL( in_MEMORY_IN_VAL                  ," in_MEMORY_IN_VAL                  ",Tcontrol_t        ,_param->_nb_inst_memory);
   ALLOC1_SC_SIGNAL(out_MEMORY_IN_ACK                  ,"out_MEMORY_IN_ACK                  ",Tcontrol_t        ,_param->_nb_inst_memory);
@@ -379,5 +432,6 @@
 	  tab_request[66].modif(550,0,0,0,65,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,1,0,0x0  ,0x0          ,0x0       ,1,0,0,0x55508570); // just to wait the dcache_rsp
 
-	  const uint32_t nb_request = 64;//_param->_nb_packet;
+	  const uint32_t nb_request = 66;//_param->_nb_packet;
+// 	  const uint32_t nb_request = 64;//_param->_nb_packet;
         
 	  for (uint32_t i=0; i<nb_request; i++)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 113)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 117)
@@ -157,7 +157,7 @@
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-  protected : Tstore_queue_entry_t                                        * _store_queue;
-  protected : Tload_queue_entry_t                                         * _load_queue;
-  protected : Tspeculative_access_queue_entry_t                           * _speculative_access_queue;
+  protected : Tstore_queue_entry_t                                        * _store_queue                     ;//[size_store_queue]
+  protected : Tload_queue_entry_t                                         * _load_queue                      ;//[size_load_queue]
+  protected : Tspeculative_access_queue_entry_t                           * _speculative_access_queue        ;//[size_speculative_access_queue]
   protected : morpheo::behavioural::generic::queue_control::Queue_Control * _speculative_access_queue_control;
 
@@ -174,7 +174,8 @@
 
     // Registers
-  public    : Tlsq_ptr_t                      reg_STORE_QUEUE_PTR_READ;
-//public    : Tlsq_ptr_t                      reg_LOAD_QUEUE_PTR_READ ;
-  public    : Tlsq_ptr_t                      reg_LOAD_QUEUE_CHECK_PRIORITY ;
+  public    : Tlsq_ptr_t                    * reg_STORE_QUEUE_NB_CHECK     ;//[size_store_queue]
+  public    : Tlsq_ptr_t                      reg_STORE_QUEUE_PTR_READ     ;
+//public    : Tlsq_ptr_t                      reg_LOAD_QUEUE_PTR_READ      ;
+  public    : Tlsq_ptr_t                      reg_LOAD_QUEUE_CHECK_PRIORITY;
 
     // signal
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 113)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 117)
@@ -146,15 +146,25 @@
 
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    if (usage_is_set(_usage,USE_SYSTEMC))
+      {
+        _speculative_access_queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control (_param->_size_speculative_access_queue);
 
-//     internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = new Tlsq_ptr_t [_param->_nb_cache_port];
+        ALLOC1(_store_queue             ,Tstore_queue_entry_t             ,_param->_size_store_queue);
+        ALLOC1(_load_queue              ,Tload_queue_entry_t              ,_param->_size_load_queue);
+        ALLOC1(_speculative_access_queue,Tspeculative_access_queue_entry_t,_param->_size_speculative_access_queue);
 
-//     internal_MEMORY_IN_ACK           = new Tcontrol_t      [_param->_nb_inst_memory];
-//     internal_MEMORY_OUT_VAL          = new Tcontrol_t      [_param->_nb_inst_memory];
-//     internal_MEMORY_OUT_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_inst_memory];
-//     internal_MEMORY_OUT_PTR          = new Tlsq_ptr_t      [_param->_nb_inst_memory];
-    
-//     internal_DCACHE_RSP_ACK          = new Tcontrol_t      [_param->_nb_cache_port];
-//     internal_DCACHE_REQ_VAL          = new Tcontrol_t      [_param->_nb_cache_port];
-//     internal_DCACHE_REQ_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_cache_port];
+        ALLOC1(reg_STORE_QUEUE_NB_CHECK                  ,Tlsq_ptr_t     ,_param->_size_store_queue);
+
+//      ALLOC1(internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ,Tlsq_ptr_t     ,_param->_nb_cache_port);
+
+//      ALLOC1(internal_MEMORY_IN_ACK                    ,Tcontrol_t     ,_param->_nb_inst_memory);
+//      ALLOC1(internal_MEMORY_OUT_VAL                   ,Tcontrol_t     ,_param->_nb_inst_memory);
+//      ALLOC1(internal_MEMORY_OUT_SELECT_QUEUE          ,Tselect_queue_t,_param->_nb_inst_memory);
+//      ALLOC1(internal_MEMORY_OUT_PTR                   ,Tlsq_ptr_t     ,_param->_nb_inst_memory);
+                                                         
+//      ALLOC1(internal_DCACHE_RSP_ACK                   ,Tcontrol_t     ,_param->_nb_cache_port );
+//      ALLOC1(internal_DCACHE_REQ_VAL                   ,Tcontrol_t     ,_param->_nb_cache_port );
+//      ALLOC1(internal_DCACHE_REQ_SELECT_QUEUE          ,Tselect_queue_t,_param->_nb_cache_port );
+      }
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
@@ -164,9 +174,4 @@
       _component->generate_file();
 #endif
-
-    _store_queue                      = new Tstore_queue_entry_t              [_param->_size_store_queue];
-    _load_queue	                      = new Tload_queue_entry_t               [_param->_size_load_queue];
-    _speculative_access_queue         = new Tspeculative_access_queue_entry_t [_param->_size_speculative_access_queue];
-    _speculative_access_queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control (_param->_size_speculative_access_queue);
 
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 113)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 117)
@@ -95,15 +95,22 @@
 
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    delete    _speculative_access_queue_control ;
     
-//     delete [] internal_MEMORY_IN_ACK          ;
-//     delete [] internal_MEMORY_OUT_VAL         ;
-//     delete [] internal_MEMORY_OUT_SELECT_QUEUE;
-//     delete [] internal_MEMORY_OUT_PTR         ;
-    
-//     delete [] internal_DCACHE_RSP_ACK         ;
-//     delete [] internal_DCACHE_REQ_VAL         ;
-//     delete [] internal_DCACHE_REQ_SELECT_QUEUE;
+    DELETE1(_store_queue             ,_param->_size_store_queue);
+    DELETE1(_load_queue              ,_param->_size_load_queue);
+    DELETE1(_speculative_access_queue,_param->_size_speculative_access_queue);
 
-//     delete [] internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ;
+    DELETE1(reg_STORE_QUEUE_NB_CHECK                  ,_param->_size_store_queue);
+
+//  DELETE1(internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ,_param->_nb_cache_port);
+
+//  DELETE1(internal_MEMORY_IN_ACK                    ,_param->_nb_inst_memory);
+//  DELETE1(internal_MEMORY_OUT_VAL                   ,_param->_nb_inst_memory);
+//  DELETE1(internal_MEMORY_OUT_SELECT_QUEUE          ,_param->_nb_inst_memory);
+//  DELETE1(internal_MEMORY_OUT_PTR                   ,_param->_nb_inst_memory);
+                                                     
+//  DELETE1(internal_DCACHE_RSP_ACK                   ,_param->_nb_cache_port );
+//  DELETE1(internal_DCACHE_REQ_VAL                   ,_param->_nb_cache_port );
+//  DELETE1(internal_DCACHE_REQ_SELECT_QUEUE          ,_param->_nb_cache_port );
       }
 
@@ -112,8 +119,4 @@
     delete    _component;
 
-    delete [] _store_queue                      ;
-    delete [] _load_queue	                ;
-    delete    _speculative_access_queue_control ;
-    delete [] _speculative_access_queue         ;
 
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 113)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 117)
@@ -98,5 +98,9 @@
       {
 	log_printf(TRACE,Load_store_unit,FUNCTION,"    * Store queue");
-	if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT)
+        // Can retire an store instruction if :
+        //  * state is commit
+        //  * none load must check this store
+	if ((_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) and
+            (reg_STORE_QUEUE_NB_CHECK [reg_STORE_QUEUE_PTR_READ] == 0))
 	  {
 	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",reg_STORE_QUEUE_PTR_READ);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 113)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 117)
@@ -242,5 +242,8 @@
 
 	for (uint32_t i=0; i< _param->_size_store_queue             ; i++)
+          {
+          reg_STORE_QUEUE_NB_CHECK  [i] = 0;
 	  _store_queue              [i]._state = STORE_QUEUE_EMPTY;
+          }
 
 	for (uint32_t i=0; i< _param->_size_load_queue              ; i++)
@@ -252,4 +255,72 @@
     else
       {
+	//================================================================
+	// Interface "MEMORY_OUT"
+	//================================================================
+
+        if ((    internal_MEMORY_OUT_VAL  == 1) and
+            (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1))
+          {
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_OUT[0] transaction");
+
+	    switch (internal_MEMORY_OUT_SELECT_QUEUE)
+	      {
+	      case SELECT_STORE_QUEUE :
+		{
+		  // =======================
+		  // ===== STORE_QUEUE =====
+		  // =======================
+		  
+		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue [%d]",reg_STORE_QUEUE_PTR_READ);
+	    
+		  // Entry flush and increase the read pointer
+		  _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY;
+		  
+		  reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue;
+
+		  break;
+		}
+	      case SELECT_LOAD_QUEUE :
+		{
+		  // ======================
+		  // ===== LOAD_QUEUE =====
+		  // ======================
+		  
+		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * load_queue  [%d]",internal_MEMORY_OUT_PTR);
+		  
+		  // Entry flush and increase the read pointer
+		  
+		  _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY;
+		  
+		  // reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
+
+		  break;
+		}
+	      case SELECT_LOAD_QUEUE_SPECULATIVE :
+		{
+		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * load_queue  [%d] (speculative)",internal_MEMORY_OUT_PTR);
+		  
+                  // !!! WARNING !!!
+                  // !!! Test special case :
+                  // !!! in a cycle an instruction can check the last store AND commit instruction
+                  // !!! also the memory_out is before the port_check
+
+		  _load_queue [internal_MEMORY_OUT_PTR]._state    = LOAD_QUEUE_CHECK;
+		  // NOTE : a speculative load write in the register file.
+		  // if the speculation is a miss, write_rd is re set at 1.
+		  _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0;
+
+#ifdef STATISTICS
+                  if (usage_is_set(_usage,USE_STATISTICS))
+                    (*_stat_nb_inst_load_commit_speculative) ++;
+#endif
+
+		  break;
+		}
+
+		break;
+	      }
+	  }
+
 	//================================================================
 	// Interface "PORT_CHECK"
@@ -278,5 +349,7 @@
 
 		// find a entry that it need a check
-		Tlsq_ptr_t index_store  = _load_queue[index_load]._store_queue_ptr_write;
+		Tlsq_ptr_t index_store     = _load_queue[index_load]._store_queue_ptr_write;
+		Tlsq_ptr_t index_store_old = index_store;
+
                 // Init variable
 		bool       end_check    = false;
@@ -534,4 +607,5 @@
 				  // The check is finish if all bit is set
 				  end_check = (_load_queue[index_load]._check_hit_byte == _param->_mask_check_hit_byte);
+
 				}
 			    }
@@ -553,4 +627,12 @@
 		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * next");
 		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * new store_queue_ptr_write : %d",index_store);
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * update reg_STORE_QUEUE_NB_CHECK");
+#ifdef DEBUG
+                    if (reg_STORE_QUEUE_NB_CHECK [index_store] == 0)
+                      throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
+#endif
+                    reg_STORE_QUEUE_NB_CHECK [index_store] --;
+
 // 		    if (_load_queue[index_load]._store_queue_ptr_write == 0)
 // 		      _load_queue[index_load]._store_queue_ptr_write = _param->_size_store_queue-1;
@@ -615,4 +697,23 @@
 		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * state new : %s",toString(_load_queue[index_load]._state).c_str());
 		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * exception : %d",_load_queue[index_load]._exception);
+
+                    if (end_check)
+                      {
+                        log_printf(TRACE,Load_store_unit,FUNCTION,"                * end check, decrease all nb_check");
+                        
+                        uint32_t i=index_store;
+                        while (i!=reg_STORE_QUEUE_PTR_READ)
+                          {
+                            i=((i==0)?_param->_size_store_queue:i)-1;
+                            
+#ifdef DEBUG
+                            if (reg_STORE_QUEUE_NB_CHECK [i] == 0)
+                              throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
+#endif
+                            
+                            reg_STORE_QUEUE_NB_CHECK [i] --;
+                            //i=(i+1)%_param->_size_store_queue;
+                          }
+                      }
 		  }
 	      }
@@ -803,67 +904,4 @@
 
 	//================================================================
-	// Interface "MEMORY_OUT"
-	//================================================================
-
-        if ((    internal_MEMORY_OUT_VAL  == 1) and
-            (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1))
-          {
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_OUT[0] transaction");
-
-	    switch (internal_MEMORY_OUT_SELECT_QUEUE)
-	      {
-	      case SELECT_STORE_QUEUE :
-		{
-		  // =======================
-		  // ===== STORE_QUEUE =====
-		  // =======================
-		  
-		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue [%d]",reg_STORE_QUEUE_PTR_READ);
-	    
-		  // Entry flush and increase the read pointer
-		  _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY;
-		  
-		  reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue;
-
-		  break;
-		}
-	      case SELECT_LOAD_QUEUE :
-		{
-		  // ======================
-		  // ===== LOAD_QUEUE =====
-		  // ======================
-		  
-		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * load_queue  [%d]",internal_MEMORY_OUT_PTR);
-		  
-		  // Entry flush and increase the read pointer
-		  
-		  _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY;
-		  
-		  // reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
-
-		  break;
-		}
-	      case SELECT_LOAD_QUEUE_SPECULATIVE :
-		{
-		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * load_queue  [%d] (speculative)",internal_MEMORY_OUT_PTR);
-		  
-		  _load_queue [internal_MEMORY_OUT_PTR]._state    = LOAD_QUEUE_CHECK;
-		  // NOTE : a speculative load write in the register file.
-		  // if the speculation is a miss, write_rd is re set at 1.
-		  _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0;
-
-#ifdef STATISTICS
-                  if (usage_is_set(_usage,USE_STATISTICS))
-                    (*_stat_nb_inst_load_commit_speculative) ++;
-#endif
-
-		  break;
-		}
-
-		break;
-	      }
-	  }
-
-	//================================================================
 	// Interface "DCACHE_REQ"
 	//================================================================
@@ -943,4 +981,5 @@
 	    Tdcache_address_t address_lsb    = (address & _param->_mask_address_lsb);
 	    Tdcache_address_t check_hit_byte = gen_mask_not<Tdcache_address_t>(address_lsb+(memory_size(operation)>>3)-1,address_lsb) & _param->_mask_check_hit_byte;
+            Tlsq_ptr_t        store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;
 
 	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * address                 : 0x%.8x", address);
@@ -955,5 +994,5 @@
 	    _load_queue [ptr_write]._packet_id             = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._packet_id;
 	    _load_queue [ptr_write]._operation             = operation;
-	    _load_queue [ptr_write]._store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;
+	    _load_queue [ptr_write]._store_queue_ptr_write = store_queue_ptr_write;
 	    _load_queue [ptr_write]._address               = address;
 	    _load_queue [ptr_write]._check_hit_byte        = check_hit_byte;
@@ -964,5 +1003,4 @@
 	    // NOTE : if have an exception, must write in register, because a depend instruction wait the load data.
 	    _load_queue [ptr_write]._write_rd              = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._write_rd             ;
-	    
 	    _load_queue [ptr_write]._num_reg_rd            = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._num_reg_rd           ;
 	    _load_queue [ptr_write]._exception             = exception;
@@ -980,4 +1018,22 @@
               (*_stat_nb_inst_load) ++;
 #endif
+
+            // Only load need check
+            if (is_operation_memory_load(_load_queue [ptr_write]._operation))
+              {
+                log_printf(TRACE,Load_store_unit,FUNCTION,"    * update nb_check");
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_ptr_write : %d",store_queue_ptr_write);
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      * reg_STORE_QUEUE_PTR_READ  : %d",reg_STORE_QUEUE_PTR_READ);
+                
+                uint32_t i=store_queue_ptr_write;
+                while (i!=reg_STORE_QUEUE_PTR_READ)
+                  {
+                    i=((i==0)?_param->_size_store_queue:i)-1;
+                    
+                    log_printf(TRACE,Load_store_unit,FUNCTION,"      * i                         : %d",i);
+                    
+                    reg_STORE_QUEUE_NB_CHECK [i] ++;
+                  }
+              }
           }
 
@@ -1075,5 +1131,5 @@
 	    uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
 
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d, %s",
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d, %.2d %s",
                        j,
                        _store_queue[j]._context_id          ,
@@ -1088,4 +1144,5 @@
                      //_store_queue[j]._num_reg_rd          ,
                        _store_queue[j]._exception           ,
+                       reg_STORE_QUEUE_NB_CHECK  [j]        ,
                        toString(_store_queue[j]._state).c_str());
 	  }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp	(revision 113)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp	(revision 117)
@@ -58,6 +58,5 @@
 
     _size_dcache_context_id                = log2(nb_context) + log2(nb_front_end) + log2(nb_ooo_engine);
-    _size_dcache_packet_id                 = (log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1;
-
+    _size_dcache_packet_id                 = log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue)+1;
     _have_port_dcache_context_id           = _size_dcache_context_id>0;
 
