Changeset 117 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src
- Timestamp:
- May 16, 2009, 4:42:39 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_genMealy_issue_out.cpp
r115 r117 30 30 Tcontrol_t val [_param->_nb_inst_issue]; 31 31 32 uint32_t index=0; 32 33 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 33 34 val [i] = 0; 34 35 36 //-------------------------------------- 35 37 // From Reexecute_queue 38 //-------------------------------------- 36 39 40 // scan all reexecute_queue slot ... 37 41 // uint32_t num_reexecute_entry = 0; 38 42 for (std::list<entry_t*>::iterator it=_reexecute_queue.begin(); … … 42 46 entry_t* entry = (*it); 43 47 44 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 45 // test if no previous transaction and can accept this type 46 if ((val[i] == 0) and _param->_table_issue_type [i][entry->_type]) 47 { 48 // find a issue port 49 val [i] = 1; 50 51 if (_param->_have_port_context_id) 52 PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [i], entry->_context_id ); 53 if (_param->_have_port_front_end_id) 54 PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [i], entry->_front_end_id ); 55 if (_param->_have_port_rob_ptr ) 56 PORT_WRITE(out_ISSUE_OUT_PACKET_ID [i], entry->_packet_id ); 57 PORT_WRITE(out_ISSUE_OUT_OPERATION [i], entry->_operation ); 58 PORT_WRITE(out_ISSUE_OUT_TYPE [i], entry->_type ); 59 PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [i], entry->_store_queue_ptr_write); 60 if (_param->_have_port_load_queue_ptr) 61 PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [i], entry->_load_queue_ptr_write ); 62 PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [i], entry->_has_immediat ); 63 PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [i], entry->_immediat ); 64 PORT_WRITE(out_ISSUE_OUT_READ_RA [i], entry->_read_ra ); 65 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [i], entry->_num_reg_ra ); 66 PORT_WRITE(out_ISSUE_OUT_READ_RB [i], entry->_read_rb ); 67 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [i], entry->_num_reg_rb ); 68 PORT_WRITE(out_ISSUE_OUT_READ_RC [i], entry->_read_rc ); 69 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [i], entry->_num_reg_rc ); 70 PORT_WRITE(out_ISSUE_OUT_WRITE_RD [i], entry->_write_rd ); 71 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [i], entry->_num_reg_rd ); 72 PORT_WRITE(out_ISSUE_OUT_WRITE_RE [i], entry->_write_re ); 73 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [i], entry->_num_reg_re ); 48 val [index] = 1; 49 50 if (_param->_have_port_context_id) 51 PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [index], entry->_context_id ); 52 if (_param->_have_port_front_end_id) 53 PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [index], entry->_front_end_id ); 54 if (_param->_have_port_rob_ptr ) 55 PORT_WRITE(out_ISSUE_OUT_PACKET_ID [index], entry->_packet_id ); 56 PORT_WRITE(out_ISSUE_OUT_OPERATION [index], entry->_operation ); 57 PORT_WRITE(out_ISSUE_OUT_TYPE [index], entry->_type ); 58 PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [index], entry->_store_queue_ptr_write); 59 if (_param->_have_port_load_queue_ptr) 60 PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [index], entry->_load_queue_ptr_write ); 61 PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [index], entry->_has_immediat ); 62 PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [index], entry->_immediat ); 63 PORT_WRITE(out_ISSUE_OUT_READ_RA [index], entry->_read_ra ); 64 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [index], entry->_num_reg_ra ); 65 PORT_WRITE(out_ISSUE_OUT_READ_RB [index], entry->_read_rb ); 66 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [index], entry->_num_reg_rb ); 67 PORT_WRITE(out_ISSUE_OUT_READ_RC [index], entry->_read_rc ); 68 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [index], entry->_num_reg_rc ); 69 PORT_WRITE(out_ISSUE_OUT_WRITE_RD [index], entry->_write_rd ); 70 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [index], entry->_num_reg_rd ); 71 PORT_WRITE(out_ISSUE_OUT_WRITE_RE [index], entry->_write_re ); 72 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [index], entry->_num_reg_re ); 74 73 75 internal_ISSUE_OUT_FROM_REEXECUTE [i] = true;76 // internal_ISSUE_OUT_NUM_BANK [i] = num_reexecute_entry;77 internal_ISSUE_OUT_ENTRY [i] = entry;74 internal_ISSUE_OUT_FROM_REEXECUTE [index] = true; 75 // internal_ISSUE_OUT_NUM_BANK [index] = num_reexecute_entry; 76 internal_ISSUE_OUT_ENTRY [index] = entry; 78 77 79 break; // stop scan 80 } 81 // num_reexecute_entry ++; 78 index ++; // next slot 82 79 } 80 81 //-------------------------------------- 82 // From Issue_queue 83 //-------------------------------------- 84 index = _param->_nb_inst_reexecute; 83 85 84 // From Issue_queue 86 log_printf(TRACE,Issue_queue,FUNCTION," * From Issue_queue"); 87 88 // for all instruction in issue_queue head ... 85 89 for (uint32_t i=0; i<_param->_nb_bank; ++i) 86 90 { … … 89 93 log_printf(TRACE,Issue_queue,FUNCTION," * Bank [%d]",num_bank); 90 94 91 bool find = false;95 // bool find = false; 92 96 93 // Have instruction ?97 // ... test if have an instruction 94 98 if (not _issue_queue [num_bank].empty()) 95 99 { 96 100 log_printf(TRACE,Issue_queue,FUNCTION," * Not Empty !!!"); 97 101 102 // read instruction 98 103 entry_t* entry = _issue_queue [num_bank].front(); 99 104 100 // have valid instruction, search a valid issue slot. 101 for (uint32_t j=0; j<_param->_nb_inst_issue; j++) 102 { 103 Tcontrol_t issue_ack = PORT_READ(in_ISSUE_OUT_ACK [j]); 105 // Tcontrol_t issue_ack = PORT_READ(in_ISSUE_OUT_ACK [index]); 106 107 log_printf(TRACE,Issue_queue,FUNCTION," * Issue [%d]",index); 108 // log_printf(TRACE,Issue_queue,FUNCTION," * issue_ack : %d",issue_ack); 109 // log_printf(TRACE,Issue_queue,FUNCTION," * previous transaction : %d",val[index]); 110 // log_printf(TRACE,Issue_queue,FUNCTION," * can issue type : %d",_param->_table_issue_type [index][entry->_type]); 104 111 105 log_printf(TRACE,Issue_queue,FUNCTION," * Issue [%d]",j); 106 log_printf(TRACE,Issue_queue,FUNCTION," * issue_ack : %d",issue_ack); 107 log_printf(TRACE,Issue_queue,FUNCTION," * previous transaction : %d",val[j]); 108 log_printf(TRACE,Issue_queue,FUNCTION," * can issue type : %d",_param->_table_issue_type [j][entry->_type]); 112 // in_order : test if find a valid read_unit 113 // if (issue_ack) 114 // { 115 // log_printf(TRACE,Issue_queue,FUNCTION," * find !!!"); 116 117 // find = true; 118 // } 109 119 110 // test if no previous transaction and can accept this type 111 if (not val[j] and 112 _param->_table_issue_type [j][entry->_type] and 113 issue_ack) 114 { 115 log_printf(TRACE,Issue_queue,FUNCTION," * find !!!"); 116 117 // find a issue port 118 val [j] = 1; 119 120 if (_param->_have_port_context_id) 121 PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [j], entry->_context_id ); 122 if (_param->_have_port_front_end_id) 123 PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [j], entry->_front_end_id ); 124 if (_param->_have_port_rob_ptr ) 125 PORT_WRITE(out_ISSUE_OUT_PACKET_ID [j], entry->_packet_id ); 126 PORT_WRITE(out_ISSUE_OUT_OPERATION [j], entry->_operation ); 127 PORT_WRITE(out_ISSUE_OUT_TYPE [j], entry->_type ); 128 PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [j], entry->_store_queue_ptr_write); 129 if (_param->_have_port_load_queue_ptr) 130 PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [j], entry->_load_queue_ptr_write ); 131 PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [j], entry->_has_immediat ); 132 PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [j], entry->_immediat ); 133 PORT_WRITE(out_ISSUE_OUT_READ_RA [j], entry->_read_ra ); 134 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [j], entry->_num_reg_ra ); 135 PORT_WRITE(out_ISSUE_OUT_READ_RB [j], entry->_read_rb ); 136 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [j], entry->_num_reg_rb ); 137 PORT_WRITE(out_ISSUE_OUT_READ_RC [j], entry->_read_rc ); 138 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [j], entry->_num_reg_rc ); 139 PORT_WRITE(out_ISSUE_OUT_WRITE_RD [j], entry->_write_rd ); 140 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [j], entry->_num_reg_rd ); 141 PORT_WRITE(out_ISSUE_OUT_WRITE_RE [j], entry->_write_re ); 142 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [j], entry->_num_reg_re ); 143 144 internal_ISSUE_OUT_FROM_REEXECUTE [j] = false; 145 internal_ISSUE_OUT_NUM_BANK [j] = num_bank; 146 internal_ISSUE_OUT_ENTRY [j] = entry; 147 148 find = true; 149 break; // find : stop scan 150 } 151 } 120 // find a issue port 121 val [index] = true; // instruction is valid 122 123 if (_param->_have_port_context_id) 124 PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [index], entry->_context_id ); 125 if (_param->_have_port_front_end_id) 126 PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [index], entry->_front_end_id ); 127 if (_param->_have_port_rob_ptr ) 128 PORT_WRITE(out_ISSUE_OUT_PACKET_ID [index], entry->_packet_id ); 129 PORT_WRITE(out_ISSUE_OUT_OPERATION [index], entry->_operation ); 130 PORT_WRITE(out_ISSUE_OUT_TYPE [index], entry->_type ); 131 PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [index], entry->_store_queue_ptr_write); 132 if (_param->_have_port_load_queue_ptr) 133 PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [index], entry->_load_queue_ptr_write ); 134 PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [index], entry->_has_immediat ); 135 PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [index], entry->_immediat ); 136 PORT_WRITE(out_ISSUE_OUT_READ_RA [index], entry->_read_ra ); 137 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [index], entry->_num_reg_ra ); 138 PORT_WRITE(out_ISSUE_OUT_READ_RB [index], entry->_read_rb ); 139 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [index], entry->_num_reg_rb ); 140 PORT_WRITE(out_ISSUE_OUT_READ_RC [index], entry->_read_rc ); 141 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [index], entry->_num_reg_rc ); 142 PORT_WRITE(out_ISSUE_OUT_WRITE_RD [index], entry->_write_rd ); 143 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [index], entry->_num_reg_rd ); 144 PORT_WRITE(out_ISSUE_OUT_WRITE_RE [index], entry->_write_re ); 145 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [index], entry->_num_reg_re ); 146 147 internal_ISSUE_OUT_FROM_REEXECUTE [index] = false; 148 internal_ISSUE_OUT_NUM_BANK [index] = num_bank; 149 internal_ISSUE_OUT_ENTRY [index] = entry; 150 151 index ++; // next slot 152 152 } 153 153 154 if (not find) 155 break; // stop scan (in order) 154 // if (not find) 155 // { 156 // log_printf(TRACE,Issue_queue,FUNCTION," * Not find. Stop Scan (in order)"); 157 158 // break; // stop scan (in order) 159 // } 156 160 } 157 161 162 // Output 158 163 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 159 164 { 160 165 internal_ISSUE_OUT_VAL [i] = val [i]; 161 166 PORT_WRITE(out_ISSUE_OUT_VAL [i], internal_ISSUE_OUT_VAL [i]); 167 168 // // Type invalid to the Core_Glue network 169 // if (not val [i]) // == empty 170 // PORT_WRITE(out_ISSUE_OUT_TYPE [i], TYPE_INVALID); 162 171 } 163 172 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_genMoore.cpp
r111 r117 109 109 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 110 110 // test if no previous transaction and can accept this type 111 if ((val[i] == 0) and _param->_table_issue_type [i][entry->_type]) 111 if ((val[i] == 0) 112 // and _param->_table_issue_type [i][entry->_type] 113 ) 112 114 { 113 115 // find a issue port … … 168 170 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 169 171 // test if no previous transaction and can accept this type 170 if ((val[i] == 0) and _param->_table_issue_type [i][entry->_type]) 172 if ((val[i] == 0) 173 // and _param->_table_issue_type [i][entry->_type] 174 ) 171 175 { 172 176 // find a issue port -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_transition.cpp
r111 r117 106 106 log_printf(TRACE,Issue_queue,FUNCTION," * Dump Issue_queue"); 107 107 108 if (_param->_queue_scheme == ISSUE_QUEUE_SCHEME_IN_ORDER) 109 { 110 log_printf(TRACE,Issue_queue,FUNCTION," * reg_NUM_BANK_HEAD : %d",reg_NUM_BANK_HEAD); 111 log_printf(TRACE,Issue_queue,FUNCTION," * reg_NUM_BANK_TAIL : %d",reg_NUM_BANK_TAIL); 112 } 113 108 114 for (uint32_t i=0; i<_param->_nb_bank; i++) 109 115 { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters.cpp
r111 r117 32 32 uint32_t size_store_queue_ptr , 33 33 uint32_t size_load_queue_ptr , 34 uint32_t nb_inst_issue ,34 // uint32_t nb_inst_issue , 35 35 uint32_t * nb_inst_rename , 36 36 uint32_t nb_inst_reexecute , … … 38 38 Tpriority_t priority , 39 39 Tload_balancing_t load_balancing , 40 bool ** table_routing ,41 bool ** table_issue_type ,40 // bool ** table_routing , 41 // bool ** table_issue_type , 42 42 bool is_toplevel ) 43 43 { … … 50 50 _queue_scheme = queue_scheme ; 51 51 _nb_bank = nb_bank ; 52 52 // _nb_inst_issue = nb_inst_issue ; 53 53 _nb_inst_rename = nb_inst_rename ; 54 54 _nb_inst_reexecute = nb_inst_reexecute ; … … 56 56 _priority = priority ; 57 57 _load_balancing = load_balancing ; 58 59 58 // _table_routing = table_routing ; 59 // _table_issue_type = table_issue_type ; 60 60 _size_reexecute_queue = nb_inst_reexecute ; 61 61 62 log_printf(TRACE,Issue_queue,FUNCTION," * table_routing [nb_rename_unit][nb_inst_issue]"); 63 for (uint32_t i=0; i<_nb_rename_unit; ++i) 64 for (uint32_t j=0; j<_nb_inst_issue; ++j) 65 if (_table_routing [i][j]) 66 log_printf(TRACE,Issue_queue,FUNCTION," [%d][%d] -> true",i,j); 62 _nb_inst_issue = _nb_inst_reexecute+_nb_bank; 63 64 // log_printf(TRACE,Issue_queue,FUNCTION," * table_routing [nb_rename_unit][nb_inst_issue]"); 65 // for (uint32_t i=0; i<_nb_rename_unit; ++i) 66 // for (uint32_t j=0; j<_nb_inst_issue; ++j) 67 // if (_table_routing [i][j]) 68 // log_printf(TRACE,Issue_queue,FUNCTION," [%d][%d] -> true",i,j); 67 69 68 log_printf(TRACE,Issue_queue,FUNCTION," * table_issue_type [nb_inst_issue][nb_type]");69 for (uint32_t i=0; i<_nb_inst_issue; ++i)70 for (uint32_t j=0; j<_nb_type; ++j)71 if (_table_issue_type [i][j])72 log_printf(TRACE,Issue_queue,FUNCTION," [%d][%d] -> true",i,j);70 // log_printf(TRACE,Issue_queue,FUNCTION," * table_issue_type [nb_inst_issue][nb_type]"); 71 // for (uint32_t i=0; i<_nb_inst_issue; ++i) 72 // for (uint32_t j=0; j<_nb_type; ++j) 73 // if (_table_issue_type [i][j]) 74 // log_printf(TRACE,Issue_queue,FUNCTION," [%d][%d] -> true",i,j); 73 75 74 76 _max_nb_inst_rename = max<uint32_t>(_nb_inst_rename,_nb_rename_unit); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp
r111 r117 48 48 test.error(toString(_("nb_bank (%d) must be a multiple of size_queue (%d).\n"),_nb_bank,_size_queue)); 49 49 50 if (not is_multiple(_nb_bank, _nb_inst_issue))51 test.error(toString(_("nb_inst_issue (%d) must be a multiple of nb_bank (%d) .\n"),_nb_inst_issue,_nb_bank));50 // if (not is_multiple(_nb_bank, _nb_inst_issue)) 51 // test.error(toString(_("nb_inst_issue (%d) must be a multiple of nb_bank (%d) .\n"),_nb_inst_issue,_nb_bank)); 52 52 53 53 if (_nb_rename_unit_select > _nb_rename_unit) … … 57 57 test.warning(_("For better performance, the bank's size (size_queue/nb_bank) must be > 1.\n")); 58 58 59 for (uint32_t i=0; i<_nb_rename_unit; i++)60 {61 bool type_present [_nb_type];59 // for (uint32_t i=0; i<_nb_rename_unit; i++) 60 // { 61 // bool type_present [_nb_type]; 62 62 63 for (uint32_t j=0; j<_nb_type; j++)64 type_present [j] = not is_type_valid(j);63 // for (uint32_t j=0; j<_nb_type; j++) 64 // type_present [j] = not is_type_valid(j); 65 65 66 bool find = false;67 for (uint32_t j=0; j<_nb_inst_issue; j++)68 if (_table_routing [i][j])69 {70 find = true;66 // bool find = false; 67 // for (uint32_t j=0; j<_nb_inst_issue; j++) 68 // if (_table_routing [i][j]) 69 // { 70 // find = true; 71 71 72 for (uint32_t k=0; k<_nb_type; k++)73 type_present [k] |= _table_issue_type [j][k];74 }72 // for (uint32_t k=0; k<_nb_type; k++) 73 // type_present [k] |= _table_issue_type [j][k]; 74 // } 75 75 76 if (not find)77 test.error(toString(_("Rename_unit [%d] is not connected with a issue slot.\n"),i));78 else79 for (uint32_t j=0; j<_nb_type; j++)80 if (not type_present [j] and not is_type_optionnal(j))81 test.error(toString(_("Rename_unit [%d] can't issue instruction's type \"%s\".\n"),i,toString(j).c_str()));82 }76 // if (not find) 77 // test.error(toString(_("Rename_unit [%d] is not connected with a issue slot.\n"),i)); 78 // else 79 // for (uint32_t j=0; j<_nb_type; j++) 80 // if (not type_present [j] and not is_type_optionnal(j)) 81 // test.error(toString(_("Rename_unit [%d] can't issue instruction's type \"%s\".\n"),i,toString(j).c_str())); 82 // } 83 83 84 84 if ((_priority != PRIORITY_ROUND_ROBIN))
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