Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 122)
@@ -143,4 +143,6 @@
   public    : SC_IN (Tcontrol_t         ) ***  in_RETIRE_EVENT_ACK                 ;//[nb_front_end][nb_context]
   public    : SC_OUT(Tevent_state_t     ) *** out_RETIRE_EVENT_STATE               ;//[nb_front_end][nb_context]
+  public    : SC_OUT(Tcontrol_t         ) *** out_RETIRE_EVENT_FLUSH               ;//[nb_front_end][nb_context]
+  public    : SC_OUT(Tcontrol_t         ) *** out_RETIRE_EVENT_STOP                ;//[nb_front_end][nb_context]
 										   
     // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
@@ -233,4 +235,5 @@
   private   : uint32_t                        reg_NUM_BANK_HEAD                    ;
   private   : uint32_t                        reg_NUM_BANK_TAIL                    ;
+  private   : uint32_t                        reg_NUM_PTR_TAIL                     ;
   private   : uint32_t                      * reg_BANK_PTR                         ;//[nb_bank]
 
@@ -238,7 +241,14 @@
   private   : Tcounter_t                   ** reg_NB_INST_COMMIT_MEM               ;//[nb_front_end][nb_context]
 
-  private   : Tevent_state_t               ** reg_EVENT_STATE                      ;//[nb_front_end][nb_context]
-  private   : bool                         ** reg_EVENT_FLUSH                      ;//[nb_front_end][nb_context]
+  private   : Tcommit_event_state_t        ** reg_EVENT_STATE                      ;//[nb_front_end][nb_context]
+//private   : bool                         ** reg_EVENT_FLUSH                      ;//[nb_front_end][nb_context]
   private   : bool                         ** reg_EVENT_STOP                       ;//[nb_front_end][nb_context]
+  private   : uint32_t                     ** reg_EVENT_NUM_BANK                   ;//[nb_front_end][nb_context]
+  private   : uint32_t                     ** reg_EVENT_NUM_PTR                    ;//[nb_front_end][nb_context]
+  private   : bool                         ** reg_EVENT_CAN_RESTART                ;//[nb_front_end][nb_context]
+  private   : uint32_t                     ** reg_EVENT_PACKET                     ;//[nb_front_end][nb_context]
+  private   : bool                         ** reg_EVENT_LAST                       ;//[nb_front_end][nb_context]
+  private   : uint32_t                     ** reg_EVENT_LAST_NUM_BANK              ;//[nb_front_end][nb_context]
+  private   : uint32_t                     ** reg_EVENT_LAST_NUM_PTR               ;//[nb_front_end][nb_context]
 
 //private   : Taddress_t                   ** reg_PC_PREVIOUS                      ;//[nb_front_end][nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 122)
@@ -28,10 +28,16 @@
     {
       ROB_EMPTY                      , // 
+
       ROB_BRANCH_WAIT_END            , // 
       ROB_BRANCH_COMPLETE            , // 
-      ROB_STORE_WAIT_HEAD_OK         , // 
-//    ROB_STORE_WAIT_HEAD_KO         , // 
-      ROB_STORE_HEAD_OK              , // 
-      ROB_STORE_HEAD_KO              , // 
+
+      ROB_STORE_WAIT_END_OK          , // 
+      ROB_STORE_WAIT_END_KO          , // 
+      ROB_STORE_OK                   , // 
+      ROB_STORE_KO                   , // 
+      ROB_STORE_OK_WAIT_END          , // 
+      ROB_STORE_KO_WAIT_END          , // 
+      ROB_STORE_EVENT                , // 
+
       ROB_OTHER_WAIT_END             , // 
 
@@ -50,11 +56,24 @@
       ROB_END_EXCEPTION_WAIT_HEAD    , // 
       ROB_END_EXCEPTION_UPDATE       , // 
-      ROB_END_EXCEPTION                // 
+      ROB_END_EXCEPTION              , // 
+      ROB_END
+    } rob_state_t;
 
-    } rob_state_t;
+  typedef enum
+    {
+      COMMIT_EVENT_STATE_NO_EVENT  ,
+      COMMIT_EVENT_STATE_EVENT     ,
+      COMMIT_EVENT_STATE_WAIT_DECOD,
+      COMMIT_EVENT_STATE_WAIT_END  ,
+      COMMIT_EVENT_STATE_END     
+    } Tcommit_event_state_t;
+
+#define commit_event_state_to_event_state(x) ((x==COMMIT_EVENT_STATE_EVENT)?EVENT_STATE_EVENT:((x==COMMIT_EVENT_STATE_WAIT_DECOD)?EVENT_STATE_WAITEND:((x==COMMIT_EVENT_STATE_WAIT_END)?EVENT_STATE_WAITEND:((x==COMMIT_EVENT_STATE_END)?EVENT_STATE_END:EVENT_STATE_NO_EVENT))))
+
 
   class entry_t 
   {
   public  : rob_state_t        state                   ;
+  public  : rob_state_t        state_old               ;
   public  : uint32_t           ptr                     ;
   public  : Tcontext_t         front_end_id            ;
@@ -98,4 +117,5 @@
 //public  : Tgeneral_data_t    data_commit             ; // branch's destination
 #ifdef DEBUG
+  public  : Tgeneral_data_t    load_data               ;
   public  : Taddress_t         address                 ;
 #endif
@@ -121,8 +141,10 @@
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_WAIT_END            : return "ROB_BRANCH_WAIT_END"             ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_COMPLETE            : return "ROB_BRANCH_COMPLETE"             ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_OK         : return "ROB_STORE_WAIT_HEAD_OK"          ; break;
-//    case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_KO         : return "ROB_STORE_WAIT_HEAD_KO"          ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_OK              : return "ROB_STORE_HEAD_OK"               ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO              : return "ROB_STORE_HEAD_KO"               ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_END_OK          : return "ROB_STORE_WAIT_END_OK"           ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_END_KO          : return "ROB_STORE_WAIT_END_KO"           ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_OK                   : return "ROB_STORE_OK"                    ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_KO                   : return "ROB_STORE_KO"                    ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_OK_WAIT_END          : return "ROB_STORE_OK_WAIT_END"           ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_KO_WAIT_END          : return "ROB_STORE_KO_WAIT_END"           ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END             : return "ROB_OTHER_WAIT_END"              ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EVENT_WAIT_END             : return "ROB_EVENT_WAIT_END"              ; break;
@@ -140,4 +162,5 @@
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_UPDATE       : return "ROB_END_EXCEPTION_UPDATE"        ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION              : return "ROB_END_EXCEPTION"               ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END                        : return "ROB_END"                         ; break;
 
       default    : return ""      ; break;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 122)
@@ -141,4 +141,6 @@
       _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_ACK               ,ACK,_param->_nb_front_end,_param->_nb_context[it1]);
       _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STATE             ,"state"                ,Tevent_state_t    ,_param->_size_event_state           ,_param->_nb_front_end,_param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_FLUSH             ,"flush"                ,Tcontrol_t        ,1                                   ,_param->_nb_front_end,_param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STOP              ,"stop"                 ,Tcontrol_t        ,1                                   ,_param->_nb_front_end,_param->_nb_context[it1]);
 
       ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]);
@@ -306,21 +308,28 @@
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-    ALLOC2(_nb_cycle_idle           ,double        ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC1(_rob                     ,std::list<entry_t*>,_param->_nb_bank);
+    ALLOC2(_nb_cycle_idle           ,double               ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC1(_rob                     ,std::list<entry_t*>  ,_param->_nb_bank);
     
-    ALLOC1(reg_BANK_PTR             ,uint32_t      ,_param->_nb_bank);
-
-    ALLOC2(reg_NB_INST_COMMIT_ALL   ,Tcounter_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_NB_INST_COMMIT_MEM   ,Tcounter_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC1(reg_BANK_PTR             ,uint32_t             ,_param->_nb_bank);
+                                                          
+    ALLOC2(reg_NB_INST_COMMIT_ALL   ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_NB_INST_COMMIT_MEM   ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
     
-    ALLOC2(reg_EVENT_STATE          ,Tevent_state_t,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_FLUSH          ,bool          ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_STOP           ,bool          ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-//  ALLOC2(reg_PC_PREVIOUS          ,Taddress_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_CURRENT           ,Taddress_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_CURRENT_IS_DS     ,Taddress_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_CURRENT_IS_DS_TAKE,Taddress_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_NEXT              ,Taddress_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_STATE          ,Tcommit_event_state_t,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2(reg_EVENT_FLUSH          ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_STOP           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_NUM_BANK       ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_NUM_PTR        ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_CAN_RESTART    ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_PACKET         ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_LAST           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_LAST_NUM_BANK  ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_LAST_NUM_PTR   ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+                                                          
+//  ALLOC2(reg_PC_PREVIOUS          ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_PC_CURRENT           ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_PC_CURRENT_IS_DS     ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_PC_CURRENT_IS_DS_TAKE,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_PC_NEXT              ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
       }
 
@@ -345,4 +354,5 @@
       if (_param->_have_thread [i])
         {
+          
           std::string filename = morpheo::filename(MORPHEO_LOG,
                                                    "Instruction_flow-thread_"+toString(i),
@@ -351,7 +361,9 @@
                                                    false,
                                                    log_with_pid,
-                                                   false);
+                                                   true);
+
+          log_printf(TRACE,Commit_unit,FUNCTION,"KANE : %s",filename.c_str());
           
-          instruction_log_file [i] .open(filename.c_str() ,std::ios::out | std::ios::trunc);
+          instruction_log_file [i].open(filename.c_str() ,std::ios::out | std::ios::trunc);
         }
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 122)
@@ -94,4 +94,6 @@
         DELETE2_SIGNAL( in_RETIRE_EVENT_ACK               ,_param->_nb_front_end,_param->_nb_context[it1],1);
         DELETE2_SIGNAL(out_RETIRE_EVENT_STATE             ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_event_state);
+        DELETE2_SIGNAL(out_RETIRE_EVENT_FLUSH             ,_param->_nb_front_end,_param->_nb_context[it1],1);
+        DELETE2_SIGNAL(out_RETIRE_EVENT_STOP              ,_param->_nb_front_end,_param->_nb_context[it1],1);
 
         DELETE1_SIGNAL( in_COMMIT_VAL               ,_param->_nb_inst_commit,1                             );
@@ -202,7 +204,16 @@
         DELETE2(reg_NB_INST_COMMIT_ALL   ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_NB_INST_COMMIT_MEM   ,_param->_nb_front_end,_param->_nb_context [it1]);
+
         DELETE2(reg_EVENT_STATE          ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_FLUSH          ,_param->_nb_front_end,_param->_nb_context [it1]);
+//      DELETE2(reg_EVENT_FLUSH          ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_EVENT_STOP           ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_NUM_BANK       ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_NUM_PTR        ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_CAN_RESTART    ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_PACKET         ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_LAST           ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_LAST_NUM_BANK  ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_LAST_NUM_PTR   ,_param->_nb_front_end,_param->_nb_context [it1]);
+
 //      DELETE2(reg_PC_PREVIOUS          ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_PC_CURRENT           ,_param->_nb_front_end,_param->_nb_context [it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 122)
@@ -30,11 +30,13 @@
 #endif
     bool       can_rename_select [_param->_nb_rename_unit];
-    bool       event_stop;
-   
+//     bool       event_stop;
+    
+//     //     Initialisation
+//     event_stop = false; // one signal for all context.
+//     for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+//       for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+//         event_stop |= reg_EVENT_STOP [i][j];   
+
 //     Initialisation
-    event_stop = false; // one signal for all context.
-    for (uint32_t i=0; i<_param->_nb_front_end; ++i)
-      for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
-        event_stop |= reg_EVENT_STOP [i][j];
     for (uint32_t i=0; i<_param->_nb_bank; i++)
       {
@@ -57,5 +59,5 @@
 //     log_printf(TRACE,Commit_unit,FUNCTION,"  * reg_NUM_BANK_TAIL : %d",reg_NUM_BANK_TAIL);
 
-    if (not event_stop)
+//     if (not event_stop)
       {
         std::list<generic::priority::select_t> * select_insert = _priority_insert ->select(); // same select for all insert
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 122)
@@ -56,4 +56,5 @@
 
         }
+
     // Scan Top of each bank
     internal_BANK_RETIRE_HEAD = reg_NUM_BANK_HEAD;
@@ -62,4 +63,5 @@
 	uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank;
 
+        // Test if have instruction
 	if (not _rob[num_bank].empty())
 	  {
@@ -68,5 +70,5 @@
 	    uint32_t   x     = entry->rename_unit_id;
 	    uint32_t   y     = num_inst_retire [x];
-	
+	    bool       bypass= false;
             // test if :
             //  * can retire (all previous instruction is retired)
@@ -77,4 +79,7 @@
 	      {
 		rob_state_t state        = entry->state;
+                Tcontext_t  front_end_id = entry->front_end_id;
+                Tcontext_t  context_id   = entry->context_id;  
+                
                   if ((state == ROB_END_OK         ) or 
                       (state == ROB_END_KO         ) or 
@@ -87,6 +92,4 @@
                       Tcontrol_t         write_re       = entry->write_re;
                       Tspecial_address_t num_reg_re_log = entry->num_reg_re_log;
-                      Tcontext_t         front_end_id   = entry->front_end_id;
-                      Tcontext_t         context_id     = entry->context_id;  
                       
                       // if state is ok, when write flags in the SR regsiters
@@ -173,8 +176,21 @@
                         can_retire [x] = false;
                     }
+
+                  bypass = ((state == ROB_END              ) or 
+                            (state == ROB_STORE_OK         ) or 
+                            (state == ROB_STORE_KO         ) or
+                            (state == ROB_STORE_OK_WAIT_END) or 
+                            (state == ROB_STORE_KO_WAIT_END));
+                  
+                  uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank);
+
+                  // if future event, don't update after this event
+                  if (reg_EVENT_STOP [front_end_id][context_id] and
+                      (reg_EVENT_PACKET [entry->front_end_id][entry->context_id]  == packet))
+                    bypass = false;
 	      }
 
 	    // Retire "in-order"
-	    can_retire [x] &= retire_val [x][y];
+	    can_retire [x]  &= (retire_val [x][y] or bypass);
 	  }
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 122)
@@ -28,48 +28,83 @@
     // ===================================================================
     {
-      log_printf(TRACE,Commit_unit,FUNCTION,"  * REEXECUTE [0]");
-
-      // Store instruction comming Out Of Order in Load Store Unit. 
-      // Must be executed in no speculative mode. Also, send a signal when an Store is in head of ROB
-
-      Tcontrol_t val      = false;
-      uint32_t   num_bank = reg_NUM_BANK_HEAD;
-
-      if (not _rob[num_bank].empty())
+      uint32_t nb_scan_bank = 0; // last scan bank
+      bool     can_continue = true;
+
+      // for each reexecute_port
+      for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i)
 	{
-          log_printf(TRACE,Commit_unit,FUNCTION,"    * ROB is not empty");
-          log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank      : %d",num_bank);
-
-          entry_t    * entry = _rob [num_bank].front();
-	  rob_state_t  state = entry->state;
-
-          // Test state
-	  val   = ((state == ROB_STORE_HEAD_OK) or
-		   (state == ROB_STORE_HEAD_KO));
-
-          log_printf(TRACE,Commit_unit,FUNCTION,"    * val           : %d",val);
-	  if (val)
+	  log_printf(TRACE,Commit_unit,FUNCTION,"  * REEXECUTE [%d]",i);
+	  
+	  // Store instruction comming Out Of Order in Load Store Unit. 
+	  // Must be executed in no speculative mode. Also, send a signal when an Store is in head of ROB
+	  
+	  Tcontrol_t val = false;
+
+	  for (uint32_t j=nb_scan_bank; j<_param->_nb_bank; j++)
 	    {
-              Tpacket_t packet_id = ((entry->ptr << _param->_shift_num_slot) | num_bank);
-
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * packet_id     : %d",packet_id);
-	  
-              // Reexecute store
-	      if (_param->_have_port_context_id)
-  	      PORT_WRITE(out_REEXECUTE_CONTEXT_ID            [0], entry->context_id           );
-	      if (_param->_have_port_front_end_id)
-  	      PORT_WRITE(out_REEXECUTE_FRONT_END_ID          [0], entry->front_end_id         );
-	      if (_param->_have_port_rob_ptr  )
-  	      PORT_WRITE(out_REEXECUTE_PACKET_ID             [0], packet_id                   );
-	      PORT_WRITE(out_REEXECUTE_TYPE                  [0], entry->type                 );
-	      PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_WRITE [0], entry->store_queue_ptr_write);
-	      PORT_WRITE(out_REEXECUTE_OPERATION             [0], (state == ROB_STORE_HEAD_OK)?OPERATION_MEMORY_STORE_HEAD_OK:OPERATION_MEMORY_STORE_HEAD_KO);
-	    }
+	      nb_scan_bank ++;
+	      
+              // translate bank number
+	      uint32_t num_bank = (reg_NUM_BANK_HEAD+j)%_param->_nb_bank;
+	      
+	      log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank      : %d",num_bank);
+
+	      // Test if the head of rob is not empty
+	      if (not _rob[num_bank].empty())
+		{
+		  log_printf(TRACE,Commit_unit,FUNCTION,"    * ROB is not empty");
+		  
+		  // Read state
+		  entry_t    * entry = _rob [num_bank].front();
+		  rob_state_t  state = entry->state;
+		  
+		  // Test state
+		  //  * store is ko, send signal at store_queue
+		  //  * store_is ok, test if in head
+// 		  val   = (((state == ROB_STORE_OK) and (num_bank == (reg_NUM_BANK_HEAD))) or
+// 			    (state == ROB_STORE_KO)  or
+// 			    (state == ROB_STORE_EVENT)
+// 			    );
+		  val   = (((state == ROB_STORE_OK) and can_continue) or
+			    (state == ROB_STORE_KO)  or
+			    (state == ROB_STORE_EVENT)
+			    );
+		  
+                  can_continue &= ((state == ROB_STORE_OK          ) or
+                                   (state == ROB_STORE_OK_WAIT_END ) or
+                                   (state == ROB_END_OK_SPECULATIVE) or
+                                   (state == ROB_END_OK            ) or
+                                   (state == ROB_END               )
+                                   );
+
+		  log_printf(TRACE,Commit_unit,FUNCTION,"    * val           : %d",val);
+
+		  if (val)
+		    {
+		      internal_REEXECUTE_NUM_BANK [i] = num_bank;
+
+		      Tpacket_t packet_id = ((entry->ptr << _param->_shift_num_slot) | num_bank);
+		      
+		      log_printf(TRACE,Commit_unit,FUNCTION,"    * packet_id     : %d",packet_id);
+		      
+		      // Reexecute store
+		      if (_param->_have_port_context_id)
+		      PORT_WRITE(out_REEXECUTE_CONTEXT_ID            [i], entry->context_id           );
+		      if (_param->_have_port_front_end_id)
+		      PORT_WRITE(out_REEXECUTE_FRONT_END_ID          [i], entry->front_end_id         );
+		      if (_param->_have_port_rob_ptr  )
+		      PORT_WRITE(out_REEXECUTE_PACKET_ID             [i], packet_id                   );
+		      PORT_WRITE(out_REEXECUTE_TYPE                  [i], entry->type                 );
+		      PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_WRITE [i], entry->store_queue_ptr_write);
+		      PORT_WRITE(out_REEXECUTE_OPERATION             [i], (state == ROB_STORE_OK)?OPERATION_MEMORY_STORE_HEAD_OK:OPERATION_MEMORY_STORE_HEAD_KO);
+
+		      break; // Stop scan
+		    }
+		}
+	    }  
+
+	  internal_REEXECUTE_VAL      [i] = val;
+	  PORT_WRITE(out_REEXECUTE_VAL[i], internal_REEXECUTE_VAL [i]);
 	}
- 
-      internal_REEXECUTE_VAL      [0] = val;
-      internal_REEXECUTE_NUM_BANK [0] = num_bank;
-      
-      PORT_WRITE(out_REEXECUTE_VAL[0], internal_REEXECUTE_VAL [0]);
     }
 
@@ -79,9 +114,12 @@
     {
       // Branchement must be send at the prediction unit
-      uint32_t nb_scan_bank = 0;
+
+      uint32_t nb_scan_bank = 0; // last scan bank
 
       // for each port, find a valid branchement.
       for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
 	{
+          log_printf(TRACE,Commit_unit,FUNCTION,"  * BRANCH_COMPLETE [%d]",i);
+
 	  Tcontrol_t  val  = false;
 	  
@@ -92,20 +130,65 @@
               // translate bank number
 	      uint32_t num_bank = (reg_NUM_BANK_HEAD+j)%_param->_nb_bank;
+
+              log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank           : %d",num_bank);
 	      
+              // Test if in this bank, they have an instruction
 	      if (not _rob [num_bank].empty())
 		{
+                  log_printf(TRACE,Commit_unit,FUNCTION,"    * not empty");
+
+                  // Read information
 		  entry_t    * entry    = _rob [num_bank].front();
 		  rob_state_t  state    = entry->state;
-		  
-		  if (state == ROB_BRANCH_COMPLETE)
+		  Tcontext_t   front_end_id = entry->front_end_id;
+		  Tcontext_t   context_id   = entry->context_id  ;
+
+                  log_printf(TRACE,Commit_unit,FUNCTION,"    * front_end_id       : %d",front_end_id);
+                  log_printf(TRACE,Commit_unit,FUNCTION,"    * context_id         : %d",context_id  );
+
+                  // don't complete a branch when rob manage an present event
+		  if ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NO_EVENT) and
+                      (state == ROB_BRANCH_COMPLETE))
 		    {
-		      val = true;
-		      
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * find !!!");
+
+                      // test if have a future event (stop is set)
+                      log_printf(TRACE,Commit_unit,FUNCTION,"      * reg_EVENT_STOP   : %d",reg_EVENT_STOP [front_end_id][context_id]);
+
+                      if (reg_EVENT_STOP [front_end_id][context_id])
+                        {
+                          // Have future event, can complete the branch if the event is most speculative than this branchement
+                          // Also, need compare packet_id (is order)
+
+                          uint32_t _top = ((_rob[reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD);
+                          uint32_t _old = reg_EVENT_PACKET [front_end_id][context_id];
+                          uint32_t _new = ((entry->ptr << _param->_shift_num_slot) | num_bank);
+
+//                           log_printf(TRACE,Commit_unit,FUNCTION,"      * _top             : %d",_top);
+//                           log_printf(TRACE,Commit_unit,FUNCTION,"      * _old (before)    : %d",_old);
+//                           log_printf(TRACE,Commit_unit,FUNCTION,"      * _new (before)    : %d",_new);
+
+                          if (_old < _top) _old = _old+_param->_size_queue;
+                          if (_new < _top) _new = _new+_param->_size_queue;
+                          if (_new < _old) val = true;
+
+//                           log_printf(TRACE,Commit_unit,FUNCTION,"      * _old (after )    : %d",_old);
+//                           log_printf(TRACE,Commit_unit,FUNCTION,"      * _new (after )    : %d",_new);
+
+                        }
+                      else
+                        val = true;
+		      
+                      log_printf(TRACE,Commit_unit,FUNCTION,"      * val              : %d",val);
+
+                      if (val)
+                        {
+                          // Have an valid branchement to complete
 		      internal_BRANCH_COMPLETE_NUM_BANK           [i] = num_bank;
 		      
+		      if (_param->_have_port_front_end_id)
+		      PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i],        front_end_id    );
 		      if (_param->_have_port_context_id)
-		      PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID   [i], entry->context_id      );
-		      if (_param->_have_port_front_end_id)
-		      PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i], entry->front_end_id    );
+		      PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID   [i],        context_id      );
 		      if (_param->_have_port_depth)
 		      PORT_WRITE(out_BRANCH_COMPLETE_DEPTH        [i], entry->depth           );
@@ -114,5 +197,6 @@
 		      PORT_WRITE(out_BRANCH_COMPLETE_NO_SEQUENCE  [i], entry->no_sequence     );
 		      
-		      break;
+		      break; // Stop scan
+                        }
 		    }
 		}
@@ -131,4 +215,5 @@
       internal_UPDATE_NUM_BANK = reg_NUM_BANK_HEAD;
 
+      // Test if have an instruction
       if (not _rob[internal_UPDATE_NUM_BANK].empty())
 	{
@@ -138,4 +223,6 @@
 	  entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front();
 
+          // Test state
+          // Update if exception or load miss
           switch (entry->state)
             {
@@ -208,5 +295,14 @@
     for (uint32_t i=0; i<_param->_nb_front_end; i++)
       for (uint32_t j=0; j<_param->_nb_context [i]; j++)
-        PORT_WRITE(out_RETIRE_EVENT_STATE [i][j], reg_EVENT_STATE[i][j]);
+        {
+//        bool flush = reg_EVENT_FLUSH [i][j];
+          bool flush = (((reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_EVENT) or
+                         (reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_WAIT_DECOD)) and
+                        not reg_EVENT_CAN_RESTART[i][j]);
+
+          PORT_WRITE(out_RETIRE_EVENT_STATE [i][j], commit_event_state_to_event_state(reg_EVENT_STATE[i][j]));
+          PORT_WRITE(out_RETIRE_EVENT_FLUSH [i][j], flush);
+          PORT_WRITE(out_RETIRE_EVENT_STOP  [i][j], reg_EVENT_STOP [i][j]);
+        }
 
     log_end(Commit_unit,FUNCTION);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 122)
@@ -16,5 +16,4 @@
 namespace ooo_engine {
 namespace commit_unit {
-
   
 #undef  FUNCTION
@@ -41,4 +40,5 @@
 	reg_NUM_BANK_HEAD = 0;
 	reg_NUM_BANK_TAIL = 0;
+        reg_NUM_PTR_TAIL  = 0;
 
         // Reset counter
@@ -51,7 +51,8 @@
 	      reg_NB_INST_COMMIT_MEM    [i][j] = 0;
                                         
-              reg_EVENT_STATE           [i][j] = EVENT_STATE_NO_EVENT;
-              reg_EVENT_FLUSH           [i][j] = false;
+              reg_EVENT_STATE           [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
+//            reg_EVENT_FLUSH           [i][j] = false;
               reg_EVENT_STOP            [i][j] = false;
+              reg_EVENT_LAST            [i][j] = false;
 
 //            reg_PC_PREVIOUS           [i][j] = (0x100-4)>>2;
@@ -80,169 +81,246 @@
 	for (uint32_t i=0; i<_param->_nb_front_end; i++)
 	  for (uint32_t j=0; j<_param->_nb_context [i]; j++)
-            switch (reg_EVENT_STATE [i][j])
-              {
-              case EVENT_STATE_EVENT    : 
+            {
+              // Test if can_restart : (can_restart is to signal at the state than the decod_queue is empty)
+              //   *     no previous can_restart (trap for one)
+              //   * and decod_queue is empty
+              //   * and have an event or have a futur event
+              if (not reg_EVENT_CAN_RESTART [i][j] and
+                   (PORT_READ(in_NB_INST_DECOD_ALL [i][j]) == 0) and
+                   (reg_EVENT_STOP [i][j] or (reg_EVENT_STATE [i][j] != COMMIT_EVENT_STATE_NO_EVENT)))
+                reg_EVENT_CAN_RESTART [i][j] = true;
+
+              // Test event state
+              switch (reg_EVENT_STATE [i][j])
                 {
-                  if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j])
-                    reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; 
-                  break;
+                case COMMIT_EVENT_STATE_EVENT    : 
+                  {
+                    // Have an event, test if all composant have ack
+                    if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j])
+                      {
+                        // A minor optimisation : test if wait_decod is previously empty.
+                        if (not reg_EVENT_CAN_RESTART [i][j])
+                          reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_DECOD;
+                        else
+                          reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END; 
+                      }
+                    
+                    break;
+                  }
+                case COMMIT_EVENT_STATE_WAIT_DECOD : 
+                  {
+                    // Wait flush of decod_queue.
+                    // Test if can restart now
+                    if (reg_EVENT_CAN_RESTART [i][j])
+                      {
+                        //reg_EVENT_FLUSH [i][j] = false;
+
+                        // A minor optimisation : test if the last element is already retire
+                        if (not reg_EVENT_LAST [i][j])
+                          reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END;
+                        else
+                          reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END; 
+                      }
+                    break;
+                  }
+                case COMMIT_EVENT_STATE_WAIT_END : 
+                  {
+                    // Wait the flush of Re Order Buffer.
+                    // Test if the last element is retire
+                    if (reg_EVENT_LAST [i][j])
+                      reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END ; 
+                    
+                    break;
+                  }
+                case COMMIT_EVENT_STATE_END      :
+                  {
+                    // Just one cycle
+                    
+                    // flush of re order buffer is finish
+                    reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
+                    reg_EVENT_LAST  [i][j] = false;
+                    break;
+                  }
+                  //case COMMIT_EVENT_STATE_NO_EVENT : 
+                default : break;
                 }
-              case EVENT_STATE_WAITEND  : 
+            }
+
+	// ===================================================================
+	// =====[ INSERT ]====================================================
+	// ===================================================================
+        {
+          // variable to count instruction insert
+          uint32_t nb_insert = 0;
+
+          for (uint32_t i=0; i<_param->_nb_bank; i++)
+            {
+              // compute first bank number
+              uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank;
+              
+              if (internal_BANK_INSERT_VAL [num_bank])
                 {
-                  Tcounter_t nb_inst_all = PORT_READ(in_NB_INST_DECOD_ALL [i][j]) + reg_NB_INST_COMMIT_ALL [i][j];
-                  if (nb_inst_all == 0)
+                  // get rename unit source and instruction.
+                  uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank];
+                  uint32_t y = internal_BANK_INSERT_NUM_INST        [num_bank];
+                  
+                  // Test if an instruction is valid
+                  // (all in_order insert combinatory is in rename_unit )
+                  if (PORT_READ(in_INSERT_VAL [x][y]))
                     {
-                      reg_EVENT_STATE [i][j] = EVENT_STATE_END;
-                      reg_EVENT_FLUSH [i][j] = false;
-                      //reg_EVENT_STOP  [i][j] = false;
+                      log_printf(TRACE,Commit_unit,FUNCTION,"  * INSERT            [%d][%d]",x,y);
+                      
+                      // get information
+                      Tcontext_t   front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0;
+                      Tcontext_t   context_id   = (_param->_have_port_context_id  )?PORT_READ(in_INSERT_CONTEXT_ID   [x][y]):0;
+                      Ttype_t      type         = PORT_READ(in_INSERT_TYPE         [x][y]);
+                      Toperation_t operation    = PORT_READ(in_INSERT_OPERATION    [x][y]);
+                      bool         is_store     = is_operation_memory_store(operation);
+                      
+                      Texception_t exception    = PORT_READ(in_INSERT_EXCEPTION    [x][y]);
+                      Tcontrol_t   no_execute   = PORT_READ(in_INSERT_NO_EXECUTE   [x][y]);
+                      
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * front_end_id   : %d",front_end_id);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * context_id     : %d",context_id);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * type           : %s",toString(type).c_str());
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * operation      : %d",operation );
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * exception      : %d",exception );
+                      
+                      // Create new entry and write information
+                      entry_t * entry = new entry_t;
+                      uint32_t  ptr   = reg_BANK_PTR [num_bank];
+
+	              entry->ptr                     = ptr;
+	              entry->front_end_id            = front_end_id;
+	              entry->context_id              = context_id  ;
+	              entry->rename_unit_id          = x;
+	              entry->depth                   = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0;
+	              entry->type                    = type;
+	              entry->operation               = operation;
+	              entry->is_delay_slot           = PORT_READ(in_INSERT_IS_DELAY_SLOT         [x][y]);
+// 	              entry->address                 = PORT_READ(in_INSERT_ADDRESS               [x][y]);
+	              entry->exception               = exception;
+	              entry->exception_use           = PORT_READ(in_INSERT_EXCEPTION_USE         [x][y]);
+	              entry->use_store_queue         = (type == TYPE_MEMORY) and (    is_store) and (not no_execute);
+	              entry->use_load_queue          = (type == TYPE_MEMORY) and (not is_store) and (not no_execute);
+	              entry->store_queue_ptr_write   = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]);
+	              entry->load_queue_ptr_write    = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0;
+#ifdef DEBUG        
+	              entry->read_ra                 = PORT_READ(in_INSERT_READ_RA               [x][y]);
+	              entry->num_reg_ra_log          = PORT_READ(in_INSERT_NUM_REG_RA_LOG        [x][y]);
+	              entry->num_reg_ra_phy          = PORT_READ(in_INSERT_NUM_REG_RA_PHY        [x][y]);
+	              entry->read_rb                 = PORT_READ(in_INSERT_READ_RB               [x][y]);
+	              entry->num_reg_rb_log          = PORT_READ(in_INSERT_NUM_REG_RB_LOG        [x][y]);
+	              entry->num_reg_rb_phy          = PORT_READ(in_INSERT_NUM_REG_RB_PHY        [x][y]);
+	              entry->read_rc                 = PORT_READ(in_INSERT_READ_RC               [x][y]);
+	              entry->num_reg_rc_log          = PORT_READ(in_INSERT_NUM_REG_RC_LOG        [x][y]);
+	              entry->num_reg_rc_phy          = PORT_READ(in_INSERT_NUM_REG_RC_PHY        [x][y]);
+#endif                
+	              entry->write_rd                = PORT_READ(in_INSERT_WRITE_RD              [x][y]);
+	              entry->num_reg_rd_log          = PORT_READ(in_INSERT_NUM_REG_RD_LOG        [x][y]);
+	              entry->num_reg_rd_phy_old      = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD    [x][y]);
+	              entry->num_reg_rd_phy_new      = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW    [x][y]);
+	              entry->write_re                = PORT_READ(in_INSERT_WRITE_RE              [x][y]);
+	              entry->num_reg_re_log          = PORT_READ(in_INSERT_NUM_REG_RE_LOG        [x][y]);
+	              entry->num_reg_re_phy_old      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD    [x][y]);
+	              entry->num_reg_re_phy_new      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW    [x][y]);
+                      entry->no_sequence             = type == TYPE_BRANCH;
+                      entry->speculative             = true;
+#ifdef DEBUG        
+	              entry->address                 = PORT_READ(in_INSERT_ADDRESS               [x][y]);
+#endif                
+	              entry->address_next            = PORT_READ(in_INSERT_ADDRESS_NEXT          [x][y]);
+#ifdef DEBUG        
+                      entry->cycle_rob_in            = simulation_cycle();
+                      entry->cycle_commit            = simulation_cycle();
+#endif      
+            
+                      // Test if exception :
+                      //  * yes : no execute instruction, wait ROB Head
+                      //  * no  : test if no_execute (== instruction is flushed)
+                      //          else test type
+                      //            * BRANCH : l.j   -> branch is ended
+                      //                       other -> wait the execution end of branchment
+                      //            * MEMORY : store -> wait store is at head of ROB
+                      //                       other -> wait end of instruction
+                      //            * OTHER
+            
+                      {
+                        if (exception == EXCEPTION_NONE)
+                          {
+                            // no_execute : l.j, l.nop, l.rfe
+                            
+                            log_printf(TRACE,Commit_unit,FUNCTION,"    * no_execute     : %d",no_execute);
+                            
+                            switch (type)
+                              {
+                              case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END  ; break;}
+                              case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store  ==1)?ROB_STORE_WAIT_END_OK:ROB_OTHER_WAIT_END); break;}
+                              default          : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
+                              }
+                          }
+                        else
+                          {
+                            // Have an exception : wait head of ROB
+                            // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
+                            
+                            entry->state = ROB_END_EXCEPTION_WAIT_HEAD;
+                          }
+                      }
+
+#ifdef STATISTICS
+                      if (usage_is_set(_usage,USE_STATISTICS))
+                        (*_stat_nb_inst_insert [x]) ++;
+#endif
+                    
+                      // Push entry in rob
+                      _rob[num_bank].push_back(entry);
+                      
+                      // Update counter and pointer
+                      reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++;
+                      if (type == TYPE_MEMORY)
+                        reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++;
+                      
+
+                      // flush = present event or future event.
+                      //  * present event = don't can restart
+
+//                       bool flush = reg_EVENT_FLUSH [front_end_id][context_id];
+
+//                       bool flush = (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
+//                                      (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)) or
+//                                     (reg_EVENT_STOP [front_end_id][context_id]));
+                      
+                      // New instruction from decod_queue. Flush if :
+                      //     * future event (instruction don't need execute because they are a previous event (miss load/branch or exception))
+                      //     * or present_event 
+                      //   * and not can_restart (previous empty decod queue), because between the event_stop (branch_complete) and the state event (miss in head), many cycle is occured.
+                      bool flush = ((// present event
+                                     ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
+                                      (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)) or
+                                     // futur event
+                                     reg_EVENT_STOP [front_end_id][context_id])
+                                    // can't restart
+                                    and not reg_EVENT_CAN_RESTART[front_end_id][context_id]
+                                    );
+
+                      if (flush)
+                        {
+                          // A new invalid instruction is push in rob -> new last instruction
+                          reg_EVENT_LAST          [front_end_id][context_id] = false;
+                          reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = num_bank;
+                          reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] = ptr;
+                        }
+                      
+                      // Update pointer
+                      reg_NUM_PTR_TAIL  = ptr;
+                      reg_BANK_PTR [num_bank]  = (reg_BANK_PTR [num_bank]+1)%_param->_size_bank;
+                      nb_insert ++;
                     }
-                  break;
                 }
-              case EVENT_STATE_END      :
-                {
-                  reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT;
-                  break;
-                }
-//            case EVENT_STATE_NO_EVENT : 
-              default : break;
-              }
-
-	// ===================================================================
-	// =====[ INSERT ]====================================================
-	// ===================================================================
-	for (uint32_t i=0; i<_param->_nb_bank; i++)
-	  if (internal_BANK_INSERT_VAL [i])
-	    {
-              // get rename unit source and instruction.
-	      uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i];
-	      uint32_t y = internal_BANK_INSERT_NUM_INST        [i];
-
-	      if (PORT_READ(in_INSERT_VAL [x][y]))
-		{
-		  log_printf(TRACE,Commit_unit,FUNCTION,"  * INSERT            [%d][%d]",x,y);
-
-                  // get information
-		  Tcontext_t   front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0;
-		  Tcontext_t   context_id   = (_param->_have_port_context_id  )?PORT_READ(in_INSERT_CONTEXT_ID   [x][y]):0;
-		  Ttype_t      type         = PORT_READ(in_INSERT_TYPE         [x][y]);
-                  Toperation_t operation    = PORT_READ(in_INSERT_OPERATION    [x][y]);
-                  bool         is_store     = is_operation_memory_store(operation);
-
-		  Texception_t exception    = PORT_READ(in_INSERT_EXCEPTION    [x][y]);
-		  Tcontrol_t   no_execute   = PORT_READ(in_INSERT_NO_EXECUTE   [x][y]);
-
-		  log_printf(TRACE,Commit_unit,FUNCTION,"    * front_end_id   : %d",front_end_id);
-		  log_printf(TRACE,Commit_unit,FUNCTION,"    * context_id     : %d",context_id);
-		  log_printf(TRACE,Commit_unit,FUNCTION,"    * type           : %s",toString(type).c_str());
-		  log_printf(TRACE,Commit_unit,FUNCTION,"    * operation      : %d",operation );
-		  log_printf(TRACE,Commit_unit,FUNCTION,"    * exception      : %d",exception );
-                  
-                  // Create new entry.
-		  entry_t * entry = new entry_t;
-
-		  entry->ptr                     = reg_BANK_PTR [i];
-		  entry->front_end_id            = front_end_id;
-		  entry->context_id              = context_id  ;
-		  entry->rename_unit_id          = x;
-		  entry->depth                   = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0;
-		  entry->type                    = type;
-		  entry->operation               = operation;
-		  entry->is_delay_slot           = PORT_READ(in_INSERT_IS_DELAY_SLOT         [x][y]);
-// 		  entry->address                 = PORT_READ(in_INSERT_ADDRESS               [x][y]);
-		  entry->exception               = exception;
-		  entry->exception_use           = PORT_READ(in_INSERT_EXCEPTION_USE         [x][y]);
-		  entry->use_store_queue         = (type == TYPE_MEMORY) and (    is_store) and (not no_execute);
-		  entry->use_load_queue          = (type == TYPE_MEMORY) and (not is_store) and (not no_execute);
-		  entry->store_queue_ptr_write   = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]);
-		  entry->load_queue_ptr_write    = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0;
-#ifdef DEBUG
-		  entry->read_ra                 = PORT_READ(in_INSERT_READ_RA               [x][y]);
-		  entry->num_reg_ra_log          = PORT_READ(in_INSERT_NUM_REG_RA_LOG        [x][y]);
-		  entry->num_reg_ra_phy          = PORT_READ(in_INSERT_NUM_REG_RA_PHY        [x][y]);
-		  entry->read_rb                 = PORT_READ(in_INSERT_READ_RB               [x][y]);
-		  entry->num_reg_rb_log          = PORT_READ(in_INSERT_NUM_REG_RB_LOG        [x][y]);
-		  entry->num_reg_rb_phy          = PORT_READ(in_INSERT_NUM_REG_RB_PHY        [x][y]);
-		  entry->read_rc                 = PORT_READ(in_INSERT_READ_RC               [x][y]);
-		  entry->num_reg_rc_log          = PORT_READ(in_INSERT_NUM_REG_RC_LOG        [x][y]);
-		  entry->num_reg_rc_phy          = PORT_READ(in_INSERT_NUM_REG_RC_PHY        [x][y]);
-#endif
-		  entry->write_rd                = PORT_READ(in_INSERT_WRITE_RD              [x][y]);
-		  entry->num_reg_rd_log          = PORT_READ(in_INSERT_NUM_REG_RD_LOG        [x][y]);
-		  entry->num_reg_rd_phy_old      = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD    [x][y]);
-		  entry->num_reg_rd_phy_new      = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW    [x][y]);
-		  entry->write_re                = PORT_READ(in_INSERT_WRITE_RE              [x][y]);
-		  entry->num_reg_re_log          = PORT_READ(in_INSERT_NUM_REG_RE_LOG        [x][y]);
-		  entry->num_reg_re_phy_old      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD    [x][y]);
-		  entry->num_reg_re_phy_new      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW    [x][y]);
-                  entry->no_sequence             = type == TYPE_BRANCH;
-                  entry->speculative             = true;
-#ifdef DEBUG
-		  entry->address                 = PORT_READ(in_INSERT_ADDRESS               [x][y]);
-#endif
-		  entry->address_next            = PORT_READ(in_INSERT_ADDRESS_NEXT          [x][y]);
-#ifdef DEBUG
-                  entry->cycle_rob_in            = simulation_cycle();
-                  entry->cycle_commit            = simulation_cycle();
-#endif
-
-                  // Test if exception :
-                  //  * yes : no execute instruction, wait ROB Head
-                  //  * no  : test type
-                  //            * BRANCH : l.j   -> branch is ended
-                  //                       other -> wait the execution end of branchment
-                  //            * MEMORY : store -> wait store is at head of ROB
-                  //                       other -> wait end of instruction
-                  //            * OTHER
-
-//                   bool       flush      = reg_EVENT_FLUSH [front_end_id][context_id];
-
-//                   log_printf(TRACE,Commit_unit,FUNCTION,"    * flush          : %d",flush);
-
-//                   if (flush)
-//                     {
-//                       entry->state    = ROB_END_MISS; // All type (branch, memory and others), because, is not execute
-//                     }
-//                   else
-                    {
-                      if (exception == EXCEPTION_NONE)
-                        {
-                          // no_execute : l.j, l.nop, l.rfe
-                          
-                          log_printf(TRACE,Commit_unit,FUNCTION,"    * no_execute     : %d",no_execute);
-                          
-                          switch (type)
-                            {
-                            case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END  ; break;}
-                            case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store  ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END); break;}
-                            default          : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
-                            }
-                        }
-                      else
-                        {
-                          // Have an exception : wait head of ROB
-                          
-                          // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
-                          
-                          entry->state = ROB_END_EXCEPTION_WAIT_HEAD;
-                        }
-                    }
-
-#ifdef STATISTICS
-                  if (usage_is_set(_usage,USE_STATISTICS))
-                    (*_stat_nb_inst_insert [x]) ++;
-#endif
-
-                  // Push in rob
-		  _rob[i].push_back(entry);
-
-		  // Update counter and pointer
-		  reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++;
-		  if (type == TYPE_MEMORY)
-		    reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++;
-
-		  reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+1)%_param->_nb_bank;
-		  reg_BANK_PTR [i]  = (reg_BANK_PTR [i]+1)%_param->_size_bank;
-		}
-	    }
+            }
+          // Update pointer
+          reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+nb_insert)%_param->_nb_bank;
+        }
 
 	// ===================================================================
@@ -255,12 +333,17 @@
 #endif
 
+        // For each commit instruction ...
 	for (uint32_t i=0; i<_param->_nb_bank; i++)
 	  for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++)
+            // ... test if an instruction have finish this execution
 	    if (internal_BANK_COMMIT_VAL [i][j])
 	      {
-                // An instruction is executed. Change state of this instruction
-
+                // An instruction is executed -> Change state of this instruction
+
+                // Get information
 		uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j];
 
+                // Test if instruction is valid and is enable
+                // (can be disable if this instruction is reexecute)
 		if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x]))
 		  {
@@ -278,5 +361,12 @@
                                                  
 		  //Toperation_t    operation    = PORT_READ(in_COMMIT_OPERATION   [x]);
-		  //Ttype_t         type         = PORT_READ(in_COMMIT_TYPE        [x]);
+ 		    Ttype_t         type         = entry->type;
+		    Tcontrol_t      no_sequence  = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);
+
+#if 0
+		    if ((type == TYPE_MEMORY) and no_sequence)
+		      continue;
+#endif		    
+
 		    Texception_t    exception    = PORT_READ(in_COMMIT_EXCEPTION   [x]);
 
@@ -286,14 +376,17 @@
 
 		    // change state : test exception_use
-		    //  * test if exception : exception and mask
 		    
 		    bool have_exception        = false;
                     bool have_miss_speculation = false;
 
+                    // Test if have an exception ...
 		    if (exception != EXCEPTION_NONE)
                       {
-                        // Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store)
+                        // Test if the instruction is a load and is a miss speculation 
+                        // (load is commit, but they have an dependence with a previous store -> need restart pipeline)
+
                         have_miss_speculation  = (exception == EXCEPTION_MEMORY_MISS_SPECULATION);
 
+                        //  * Test if the exception generated can be trap by this exception
                         switch (entry->exception_use)
                           {
@@ -327,12 +420,56 @@
                       }
                    
+                    // Next state depends of previous state
                     switch (state)
                       {
-                        // Branch ...
-                      case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;}
-                        // Store KO
-                      case ROB_EVENT_WAIT_END  : {state = ROB_END_KO_SPECULATIVE; break;}
-                        // Store OK, Load and other instruction
-                      case ROB_OTHER_WAIT_END  : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_LOAD_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE); break;}
+                        // Branch : if no exception, the branchement can be completed
+                      case ROB_BRANCH_WAIT_END : 
+                        {
+                          if (not have_exception)
+                            state = ROB_BRANCH_COMPLETE;
+                          else
+                            state = ROB_END_EXCEPTION_WAIT_HEAD;
+                          break;
+                        }
+                        // Previous event -> set state as execute
+		      case ROB_STORE_KO_WAIT_END :
+                      case ROB_EVENT_WAIT_END  : 
+                        {
+                          state = ROB_END_KO_SPECULATIVE; 
+                          break;
+                        }
+                        // No previous event - Load and other instruction
+		      case ROB_STORE_OK_WAIT_END :
+                      case ROB_OTHER_WAIT_END  : 
+                        {
+                          if (not have_exception)
+                            {
+                              if (not have_miss_speculation)
+                                state = ROB_END_OK_SPECULATIVE;
+                              else
+                                state = ROB_END_LOAD_MISS_SPECULATIVE; 
+                            }
+                          else
+                            state = ROB_END_EXCEPTION_WAIT_HEAD;
+                          break;
+                        }
+		      case ROB_STORE_WAIT_END_OK :
+			{
+			  if (not have_exception)
+			    state = ROB_STORE_OK;
+			  else
+                            state = ROB_STORE_EVENT;
+			  break;
+			}
+		      case ROB_STORE_WAIT_END_KO :
+			{
+// 			  if (not have_exception)
+			    state = ROB_STORE_KO;
+// 			  else
+//                             state = ROB_END_EXCEPTION_WAIT_HEAD; 
+			  break;
+			}
+
+
                       default :
                         {
@@ -342,15 +479,50 @@
                       }
 
-                    if ((have_exception or have_miss_speculation) and
-                        (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0))
-                      reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true;
-
-		    // update Re Order Buffer
+                    // Commit an instruction ... 
+                    // Test if have an event (miss_speculation or exception) and not manage a previous event
+                    // if yes, this instruction would modify state machine. Also stop Re Order Buffer
+
+//                  bool flush = reg_EVENT_FLUSH [entry->front_end_id][entry->context_id];
+                    bool flush = ((reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_EVENT) or
+                                  (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or
+                                  (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_WAIT_END));
+                    
+                    if ((have_exception or have_miss_speculation) and (not flush))
+                      {
+                        uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | i);
+                        
+                        // test have a previous event detected (event_stop = 1)
+                        // if yes, test if the actual event if "before (in order)" that the previous event
+                        if (reg_EVENT_STOP [entry->front_end_id][entry->context_id])
+                          {
+                            // Compare packet_id (by construction instruction is insert in order by increase packet_id)
+
+                            uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD);
+                            uint32_t _old = reg_EVENT_PACKET [entry->front_end_id][entry->context_id];
+                            uint32_t _new = packet;
+                            if (_old < _top) _old = _old+_param->_size_queue;
+                            if (_new < _top) _new = _new+_param->_size_queue;
+                            if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
+                          }
+                        else
+                          reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
+                        
+                        // have an error, stop issue instruction
+                        reg_EVENT_STOP          [entry->front_end_id][entry->context_id] = true;
+//                         reg_EVENT_NUM_BANK      [entry->front_end_id][entry->context_id] = i;
+//                         reg_EVENT_NUM_PTR       [entry->front_end_id][entry->context_id] = entry->ptr;
+
+//                      reg_EVENT_CAN_RESTART   [entry->front_end_id][entry->context_id] = false;
+                        reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
+                        reg_EVENT_LAST_NUM_PTR  [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL;
+                      }
+                    
+		    // Update Re Order Buffer
 		    entry->state        = state;
 		    entry->exception    = exception;
 		    entry->flags        = PORT_READ(in_COMMIT_FLAGS       [x]);
-		    entry->no_sequence  = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);
+		    entry->no_sequence  = no_sequence;
                     // jalr, jr : address_dest is in register
-                    if ((entry->type      == TYPE_BRANCH) and
+                    if ((       type      == TYPE_BRANCH) and
                         (entry->operation == OPERATION_BRANCH_L_JALR) and
                         (entry->read_rb))
@@ -358,5 +530,6 @@
 
 #ifdef DEBUG
-                  entry->cycle_commit            = simulation_cycle();
+                    entry->load_data               = PORT_READ(in_COMMIT_ADDRESS [x]);
+                    entry->cycle_commit            = simulation_cycle();
 #endif
 		  }
@@ -368,8 +541,11 @@
 	for (uint32_t i=0; i<_param->_nb_bank; i++)
           {
+            // Compute bank number
             uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank;
             
+            // Test if have an request
             if (internal_BANK_RETIRE_VAL [num_bank])
               {
+                // Take num instruction
                 uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank];
                 uint32_t y = internal_BANK_RETIRE_NUM_INST        [num_bank];
@@ -382,128 +558,197 @@
                   throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n"));
 #endif
+
+
+#ifdef STATISTICS
+	    if (usage_is_set(_usage,USE_STATISTICS))
+	      (*_stat_nb_inst_retire [x]) ++;
                 
-                entry_t *  entry        =  _rob [num_bank].front();
-                rob_state_t state = entry->state;
+#endif
                 
-                Tcontext_t front_end_id = entry->front_end_id;
-                Tcontext_t context_id   = entry->context_id  ;
-                uint32_t   num_thread   = _param->_translate_num_context_to_num_thread [front_end_id][context_id];
-                Ttype_t    type         = entry->type        ;
-                bool       retire_ok    = false;
-
-                log_printf(TRACE,Commit_unit,FUNCTION,"    * front_end_id : %d",front_end_id );
-                log_printf(TRACE,Commit_unit,FUNCTION,"    * context_id   : %d",context_id   );
-                log_printf(TRACE,Commit_unit,FUNCTION,"    * rob_ptr      : %d",((entry->ptr << _param->_shift_num_slot) | num_bank));
-                log_printf(TRACE,Commit_unit,FUNCTION,"    * num_thread   : %d",num_thread   );
-                log_printf(TRACE,Commit_unit,FUNCTION,"    * type         : %s",toString(type).c_str());
-                log_printf(TRACE,Commit_unit,FUNCTION,"    * state        : %s",toString(state).c_str());
-
-                if ((state == ROB_END_OK         ) or
-// 		    (state == ROB_END_KO         ) or 
-                    (state == ROB_END_BRANCH_MISS) or 
-                    (state == ROB_END_LOAD_MISS  )//  or 
-// 		    (state == ROB_END_MISS       ) or 
-// 		    (state == ROB_END_EXCEPTION  )
-                    )
-                  {
-                    log_printf(TRACE,Commit_unit,FUNCTION,"    * retire_ok");
-
-                    retire_ok = true;
-
-//                  reg_PC_PREVIOUS           [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id];
-                    reg_PC_CURRENT            [front_end_id][context_id] = reg_PC_NEXT    [front_end_id][context_id];
-                    reg_PC_CURRENT_IS_DS      [front_end_id][context_id] = entry->type == TYPE_BRANCH;
-                    reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence;
-                    reg_PC_NEXT               [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1);
-
-//                   if (entry->address_next != reg_PC_NEXT [front_end_id][context_id])
-//                     throw ERRORMORPHEO(FUNCTION,toString(_("Retire : Instruction's address_next (%.8x) is different of commit_unit's address_next (%.8x)"),entry->address_next,reg_PC_NEXT [front_end_id][context_id]));
-                  }
-
-                if ((state == ROB_END_BRANCH_MISS) or
-                    (state == ROB_END_LOAD_MISS))
-                    {
-                      reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT;
-                      reg_EVENT_FLUSH [front_end_id][context_id] = true;
-                      reg_EVENT_STOP  [front_end_id][context_id] = false;
-                    }
-                
-#if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true)
-                // log file
-                instruction_log_file [num_thread] 
-                  << "[" << simulation_cycle() << "] "
-                  << std::hex
-                  << (entry->address<<2) << " (" << (entry->address) << ") "
-                  << std::dec
-                  << "[" << entry->cycle_rob_in << ", " << entry->cycle_commit << "] "
-                  << "{" << ((retire_ok)?" OK ":"!KO!") << "} "
-                  << std::endl;
-#endif
-
-                // Update nb_inst
-                reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --;
-                if (type == TYPE_MEMORY)
-                  reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
-                
-                reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank;
-                
-                delete entry;
-                _rob [num_bank].pop_front();
-                
-                // Transaction on retire interface : reset watch dog timer.
-                _nb_cycle_idle [front_end_id][context_id] = 0;
-
-                // Increase stop condition
-                if (retire_ok)
-                  _simulation_nb_instruction_commited [num_thread] ++;
-
-#ifdef STATISTICS
-                if (usage_is_set(_usage,USE_STATISTICS))
-                  {
-                    (*_stat_nb_inst_retire [x]) ++;
-                    
-                    if (retire_ok)
-                      {
-                        (*_stat_nb_inst_retire_ok [num_thread]) ++;
-                        (*_stat_nb_inst_type      [type]      ) ++;
-                      }
-                    else
-                      (*_stat_nb_inst_retire_ko [num_thread]) ++;
-                  }
-#endif
+                // Read information
+                entry_t *   entry        =  _rob [num_bank].front();
+
+                entry->state_old = entry->state;
+                entry->state     = ROB_END;
               }
           }
 
+	for (uint32_t i=0; i<_param->_nb_bank; i++)
+	  {
+	    // Compute bank number
+	    bool      can_continue = false;
+	    uint32_t  num_bank = reg_NUM_BANK_HEAD;
+	    
+	    if (not _rob [num_bank].empty ())
+	      {
+	        entry_t * entry = _rob [num_bank].front();
+	        
+	        if (entry->state == ROB_END)
+	          {
+	            log_printf(TRACE,Commit_unit,FUNCTION,"  * RETIRE_ROB [%d]",num_bank);
+	    
+                    can_continue = true;
+
+	            Tcontext_t  front_end_id = entry->front_end_id;
+	            Tcontext_t  context_id   = entry->context_id  ;
+	            uint32_t    num_thread   = _param->_translate_num_context_to_num_thread [front_end_id][context_id];
+	            rob_state_t state        = entry->state_old;
+	            Ttype_t     type         = entry->type        ;
+	            bool        retire_ok    = false;
+	            uint32_t    packet_id    = ((entry->ptr << _param->_shift_num_slot) | num_bank);
+	            
+	            log_printf(TRACE,Commit_unit,FUNCTION,"    * front_end_id : %d",front_end_id );
+	            log_printf(TRACE,Commit_unit,FUNCTION,"    * context_id   : %d",context_id   );
+	            log_printf(TRACE,Commit_unit,FUNCTION,"    * rob_ptr      : %d",packet_id    );
+	            log_printf(TRACE,Commit_unit,FUNCTION,"    * num_thread   : %d",num_thread   );
+	            log_printf(TRACE,Commit_unit,FUNCTION,"    * type         : %s",toString(type).c_str());
+	            log_printf(TRACE,Commit_unit,FUNCTION,"    * state        : %s",toString(state).c_str());
+	            
+                    // Test if the instruction is valid
+                    // (BRANCH_MISS = instruction branch is valid, but have make an invalid prediction)
+                    // (LOAD_MISS   = instruction load   is valid, but have make an invalid result)
+                    if ((state == ROB_END_OK         ) or
+// 	                (state == ROB_END_KO         ) or 
+                        (state == ROB_END_BRANCH_MISS) or 
+                        (state == ROB_END_LOAD_MISS  )//  or 
+// 	                (state == ROB_END_MISS       ) or 
+// 	                (state == ROB_END_EXCEPTION  )
+                        )
+                      {
+                        log_printf(TRACE,Commit_unit,FUNCTION,"    * retire_ok");
+	            
+                        retire_ok = true;
+	            
+                        // Update PC information
+//                      reg_PC_PREVIOUS           [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id];
+                        reg_PC_CURRENT            [front_end_id][context_id] = reg_PC_NEXT    [front_end_id][context_id];
+                        reg_PC_CURRENT_IS_DS      [front_end_id][context_id] = type == TYPE_BRANCH;
+                        reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence;
+                        reg_PC_NEXT               [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1);
+                      }
+	            
+                    // Test if have an event
+                    if ((state == ROB_END_BRANCH_MISS) or
+                        (state == ROB_END_LOAD_MISS))
+	              {
+                          reg_EVENT_STATE         [front_end_id][context_id] = COMMIT_EVENT_STATE_EVENT;
+//                        reg_EVENT_FLUSH         [front_end_id][context_id] = true;
+                          reg_EVENT_STOP          [front_end_id][context_id] = false; // instruction flow can continue
+//                        reg_EVENT_CAN_RESTART   [front_end_id][context_id] = false;
+                          reg_EVENT_LAST          [front_end_id][context_id] = false;
+                          // it the head !
+                          reg_EVENT_PACKET        [front_end_id][context_id] = packet_id;
+	            
+                          // If event is an load_miss, many instruction can be inserted. 
+                          // -> new last instruction
+                          if (state == ROB_END_LOAD_MISS)
+                            {
+                            reg_EVENT_CAN_RESTART   [front_end_id][context_id] = false;
+                            
+                            reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
+                            reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] = reg_NUM_PTR_TAIL;
+                            }
+                        }
+	            
+                    // Test if this instruction is the last instruction of an event
+                    //   * need event
+                    //   * packet id = last packet id
+                    if ((reg_EVENT_STATE         [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT) and
+                        (reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] == num_bank            ) and
+                        (reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] == entry->ptr          ))
+                      reg_EVENT_LAST [front_end_id][context_id] = true;
+	            
+                    // Update nb_inst
+                    reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --;
+                    if (type == TYPE_MEMORY)
+                    reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
+	            
+	            // Update pointer
+	            reg_NUM_BANK_HEAD = (num_bank+1)%_param->_nb_bank;
+                    
+	            // Remove entry
+	            delete entry;
+	            _rob [num_bank].pop_front();
+                    
+                    // Reset watch dog timer because have transaction on retire interface
+                    _nb_cycle_idle [front_end_id][context_id] = 0;
+	            
+                    // Increase stop condition
+                    if (retire_ok)
+                      _simulation_nb_instruction_commited [num_thread] ++;
+
+#ifdef STATISTICS
+	            if (usage_is_set(_usage,USE_STATISTICS))
+	              {
+	            	if (retire_ok)
+	            	  {
+	            	    (*_stat_nb_inst_retire_ok [num_thread]) ++;
+	            	    (*_stat_nb_inst_type      [type]      ) ++;
+	            	  }
+	            	else
+	            	  (*_stat_nb_inst_retire_ko [num_thread]) ++;
+	              }
+#endif
+
+#if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true)
+	            {
+	              // log file
+	              instruction_log_file [num_thread] 
+	            	<< "[" << simulation_cycle() << "] "
+	            	<< std::hex
+	            	<< (entry->address<<2) << " (" << (entry->address) << ") "
+	            	<< std::dec
+	            	<< "[" << entry->cycle_rob_in << ", " << entry->cycle_commit << "] "
+	            	<< "{" << ((retire_ok)?"OK":"KO") << "} ";
+	              
+	              if ((type == TYPE_MEMORY) and  is_operation_memory_load(entry->operation))
+	            	instruction_log_file [num_thread] << std::hex << entry->load_data << std::dec;
+	              
+	              instruction_log_file [num_thread] << std::endl;
+	            }
+#endif	    
+	          }
+	      }
+	    
+	    if (not can_continue)
+	      break; // stop scan
+	  }
+
 	// ===================================================================
 	// =====[ REEXECUTE ]=================================================
 	// ===================================================================
-	if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0]))
-	  {
-            log_printf(TRACE,Commit_unit,FUNCTION,"  * REEXECUTE         [0]");
-
-	    uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0];
-
-	    entry_t    * entry = _rob [num_bank].front();
-	    rob_state_t  state = entry->state;
-
-	    switch (state)
-	      {
-	      case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; }
-	      case ROB_STORE_HEAD_KO : {state = ROB_EVENT_WAIT_END; break; }
-	      default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));}
-	      }
-
-	    entry->state = state;
-	  }
-
+        // Test if have an reexecute instruction (an store in head of rob)
+	for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i)
+	  if (internal_REEXECUTE_VAL [i] and PORT_READ(in_REEXECUTE_ACK [i]))
+	    {
+	      log_printf(TRACE,Commit_unit,FUNCTION,"  * REEXECUTE         [%d]",i);
+	      
+	      uint32_t num_bank = internal_REEXECUTE_NUM_BANK [i];
+	      
+	      entry_t    * entry = _rob [num_bank].front();
+	      rob_state_t  state = entry->state;
+	      
+	      // Change state
+	      switch (state)
+		{
+		case ROB_STORE_OK    : {state = ROB_STORE_OK_WAIT_END; break; }
+		case ROB_STORE_KO    : {state = ROB_STORE_KO_WAIT_END; break; }
+		case ROB_STORE_EVENT : {state = ROB_EVENT_WAIT_END; break; }
+		default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));}
+		}
+	      
+	      entry->state = state;
+	    }
+	
 	// ===================================================================
 	// =====[ BRANCH_COMPLETE ]===========================================
 	// ===================================================================
 	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
+          // Test if the prediction_unit have accept the branch complete transaction
 	  if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i]))
 	    {
               log_printf(TRACE,Commit_unit,FUNCTION,"  * BRANCH_COMPLETE   [%d]",i);
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * miss_prediction : %d",PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]));
-
+
+              // Read information
 	      uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i];
 	      
@@ -516,12 +761,43 @@
 #endif
               Tcontrol_t miss = PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]);
+
+              log_printf(TRACE,Commit_unit,FUNCTION,"    * miss_prediction : %d",miss);
               
               entry->state = (miss)?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE;
-              
-              if (miss and (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0))
-                reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true;
-
-
-//               entry->state = ROB_END_OK_SPECULATIVE;
+
+//            bool flush = reg_EVENT_FLUSH [entry->front_end_id][entry->context_id];
+
+              // Branch_complete can be execute if
+              //   * no present event
+              //   * futur event and most not speculative that the event
+
+              // Also, test if in this cycle, they have not an most recently event !!!
+              if (miss)
+                {
+                  uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank);
+                      
+                  // test if this packet is before previous event
+                  if (reg_EVENT_STOP [entry->front_end_id][entry->context_id])
+                    {
+                      uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD);
+                      uint32_t _old = reg_EVENT_PACKET [entry->front_end_id][entry->context_id];
+                      uint32_t _new = packet;
+                      if (_old < _top) _old = _old+_param->_size_queue;
+                      if (_new < _top) _new = _new+_param->_size_queue;
+                      if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
+                    }
+                  else
+                    reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
+
+                  // In all case, stop instruction flow
+                  reg_EVENT_STOP          [entry->front_end_id][entry->context_id] = true;
+//                   reg_EVENT_NUM_BANK      [entry->front_end_id][entry->context_id] = num_bank;
+//                   reg_EVENT_NUM_PTR       [entry->front_end_id][entry->context_id] = entry->ptr;
+
+                  reg_EVENT_CAN_RESTART   [entry->front_end_id][entry->context_id] = false;
+
+                  reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
+                  reg_EVENT_LAST_NUM_PTR  [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL;
+                }
 	    }
 
@@ -529,8 +805,10 @@
 	// =====[ UPDATE ]====================================================
 	// ===================================================================
+        // Update when exception or load_miss
         if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK))
           {
             log_printf(TRACE,Commit_unit,FUNCTION,"  * UPDATE");
 
+            // Change state
             entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front();
 
@@ -556,5 +834,4 @@
                 }
               }
-
           }
 
@@ -578,129 +855,168 @@
 	// =====[ DEPTH - HEAD ]==============================================
 	// ===================================================================
-	for (uint32_t i=0; i<_param->_nb_bank; i++)
-	  if (not _rob[i].empty())
-	    {
-	      // Scan all instruction in windows and test if instruction is speculative
-	      entry_t    * entry        = _rob [i].front();
-	      
-	      Tcontext_t   front_end_id = entry->front_end_id;
-	      Tcontext_t   context_id   = entry->context_id  ;
-	      rob_state_t  state        = entry->state;
-	      Tdepth_t     depth        = entry->depth;
-
-              Tdepth_t     depth_min    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0;
-              Tdepth_t     depth_max    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;
-              Tcontrol_t   depth_full   = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);
+
+        {
+          bool EVENT_LAST [_param->_nb_front_end][_param->_max_nb_context];
+          for (uint32_t i=0; i<_param->_nb_front_end; i++)
+            for (uint32_t j=0; j<_param->_nb_context [i]; j++)
+              EVENT_LAST [i][j] = reg_EVENT_LAST [i][j];
+
+          // Read all instruction of all top bank
+          for (uint32_t i=0; i<_param->_nb_bank; i++)
+            {
+              uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
               
-              // is a valid instruction ?
-              // If DEPTH_CURRENT :
-              // equal at     DEPTH_MIN            -> not speculative
-              // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
-              //     include ]DEPTH_MIN:DEPTH_MAX] -> speculative
-              
-              // All case
-              // ....... min ...X... max ....... OK
-              // ....... min ....... max ...X... KO
-              // ...X... min ....... max ....... KO
-              // ....... max ....... min ...X... OK
-              // ...X... max ....... min ....... OK
-              // ....... max ...X... min ....... KO
-              
-              bool         flush         = reg_EVENT_FLUSH [front_end_id][context_id];
-              bool         speculative   = entry->speculative and not (depth == depth_min);
-              Tcontrol_t   is_valid      = ((not speculative or 
-                                             (speculative and (depth_full or // all is valid
-                                                               ((depth_min <= depth_max)? // test if depth is overflow
-                                                                ((depth >= depth_min) and (depth <=depth_max)):
-                                                                ((depth >= depth_min) or  (depth <=depth_max))))))
-                                             and not flush);
-
-//            Tcontrol_t   is_valid      = ((depth == depth_min) and not flush);
-
-              log_printf(TRACE,Commit_unit,FUNCTION,"  * HEAD              [%d]",i);
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * is_valid        : %d ((depth == depth_min) and not flush)",is_valid);
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * depth           : %d",depth    );
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_min       : %d",depth_min);
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_max       : %d",depth_max);
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_full      : %d",depth_full);
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * flush           : %d",flush);
-
-	      //------------------------------------------------------
-	      // test if instruction is miss speculative
-	      //------------------------------------------------------
-	      if (not is_valid)
-		{
-		  switch (state)
-		    {
-		    case ROB_BRANCH_WAIT_END             : {state = ROB_EVENT_WAIT_END; break;}
-		    case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS      ; break;}
-                    case ROB_END_BRANCH_MISS             :
-                    case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS      ; break;}
-                    case ROB_END_LOAD_MISS_UPDATE        :
-                    case ROB_END_LOAD_MISS               :
-                    case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_MISS      ; break;}
-		    case ROB_STORE_WAIT_HEAD_OK          : {state = ROB_STORE_HEAD_KO ; break;}
-		  //case ROB_STORE_WAIT_HEAD_KO          : {state = ; break;}
-		    case ROB_OTHER_WAIT_END              : {state = ROB_EVENT_WAIT_END; break;}
-		    case ROB_END_OK                      :
-		    case ROB_END_OK_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
-		    case ROB_END_KO                      :
-		    case ROB_END_KO_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
-		    case ROB_END_EXCEPTION_UPDATE        :
-		    case ROB_END_EXCEPTION               :
-		    case ROB_END_EXCEPTION_WAIT_HEAD     : {state = ROB_END_MISS      ; break;}
-		                                         
-		      // don't change                    
-		    case ROB_STORE_HEAD_KO               : {break;}
-		    case ROB_EVENT_WAIT_END              : {break;}
-		    case ROB_END_MISS                    : {break;}
-		                                         
-		      // can't have miss speculation     
-		    case ROB_STORE_HEAD_OK               :
-		    default                              : 
-		      {
-			throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str()));
-			break;
-		      }
-		    }
-		}
-	      
-	      //------------------------------------------------------
-	      // test if instruction is not speculative
-	      //------------------------------------------------------
-              entry->speculative = speculative;
-// 	      if (entry->depth == depth_min)
-	      if (not speculative)
-		{
-		  switch (state)
-		    {
-		    case ROB_END_OK_SPECULATIVE          : {state = ROB_END_OK                 ; break;}
-		    case ROB_END_KO_SPECULATIVE          : {state = ROB_END_KO                 ; break;}
-		    case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS        ; break;}
-		    case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_LOAD_MISS_UPDATE   ; break;}
-		    default : {break;} // else, no change
-		  }
-		}
-	      
-	      //------------------------------------------------------
-	      // test if instruction is store and head
-	      //------------------------------------------------------
-	      if (i == reg_NUM_BANK_HEAD)
-		{
-		  switch (state)
-		    {
-		    case ROB_STORE_WAIT_HEAD_OK      : {state = ROB_STORE_HEAD_OK;        break;}
-		    case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;}
-                    default : {break;} // else, no change
-		    }
-		}
-	      
-	      entry->state = state;
-	    }
-      }
-
-    // ===================================================================
-    // =====[ OTHER ]=====================================================
-    // ===================================================================
+              // Test if have an instruction
+              if (not _rob[num_bank].empty())
+                {
+                  // Scan all instruction in windows and test if instruction is speculative
+                  entry_t    * entry        = _rob [num_bank].front();
+                  
+                  Tcontext_t   front_end_id = entry->front_end_id;
+                  Tcontext_t   context_id   = entry->context_id  ;
+                  
+                  // scan while last event instruction is not retire
+                  if (EVENT_LAST [front_end_id][context_id] == false)
+                    {
+                      // Read information
+                      rob_state_t  state        = entry->state;
+                      Tdepth_t     depth        = entry->depth;
+                      
+                      Tdepth_t     depth_min    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0;
+                      Tdepth_t     depth_max    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;
+                      Tcontrol_t   depth_full   = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);
+                      
+                      // is a valid instruction ?
+                      // If DEPTH_CURRENT :
+                      // equal at     DEPTH_MIN            -> not speculative
+                      // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
+                      //     include ]DEPTH_MIN:DEPTH_MAX] -> speculative
+                      
+                      // All case
+                      // ....... min ...X... max ....... OK
+                      // ....... min ....... max ...X... KO
+                      // ...X... min ....... max ....... KO
+                      // ....... max ....... min ...X... OK
+                      // ...X... max ....... min ....... OK
+                      // ....... max ...X... min ....... KO
+                      
+                      bool         flush         = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
+                                                    (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or
+                                                    (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END));
+                      bool         speculative   = entry->speculative and not (depth == depth_min);
+                      Tcontrol_t   is_valid      = ((not speculative or 
+                                                     (speculative and (depth_full or // all is valid
+                                                                       ((depth_min <= depth_max)? // test if depth is overflow
+                                                                        ((depth >= depth_min) and (depth <=depth_max)):
+                                                                        ((depth >= depth_min) or  (depth <=depth_max))))))
+                                                    and not flush); // no event
+                      
+                      //Tcontrol_t   is_valid      = ((depth == depth_min) and not flush);
+                      
+                      log_printf(TRACE,Commit_unit,FUNCTION,"  * HEAD              [%d] - %d",num_bank,((entry->ptr << _param->_shift_num_slot) | num_bank));
+                      
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * is_valid        : %d ((depth == depth_min) and not flush)",is_valid);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * depth           : %d",depth    );
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_min       : %d",depth_min);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_max       : %d",depth_max);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_full      : %d",depth_full);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * speculative     : %d",speculative);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * flush           : %d",flush);
+                    
+                      //------------------------------------------------------
+                      // test if instruction is miss speculative
+                      //------------------------------------------------------
+                      if (not is_valid)
+                        {
+                          // Change state
+                          switch (state)
+                            {
+                            case ROB_BRANCH_WAIT_END             : {state = ROB_EVENT_WAIT_END; break;}
+                            case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_BRANCH_MISS             :
+                            case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_LOAD_MISS_UPDATE        :
+                            case ROB_END_LOAD_MISS               :
+                            case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_MISS      ; break;}
+                            case ROB_STORE_OK                    : {state = ROB_STORE_KO      ; break;}
+                            case ROB_STORE_WAIT_END_OK           : {state = ROB_STORE_WAIT_END_KO; break;}
+			    case ROB_STORE_OK_WAIT_END           : {state = ROB_STORE_KO_WAIT_END; break;}
+                            case ROB_OTHER_WAIT_END              : {state = ROB_EVENT_WAIT_END; break;}
+                            case ROB_END_OK                      :
+                            case ROB_END_OK_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_KO                      :
+                            case ROB_END_KO_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_EXCEPTION_UPDATE        :
+                            case ROB_END_EXCEPTION               :
+                            case ROB_END_EXCEPTION_WAIT_HEAD     : {state = ROB_END_MISS      ; break;}
+                              
+                              // don't change state -> wait
+                            case ROB_STORE_WAIT_END_KO           : {break;}
+                            case ROB_STORE_KO                    : {break;}
+                            case ROB_STORE_KO_WAIT_END           : {break;}
+                            case ROB_STORE_EVENT                 : {break;}
+                            case ROB_EVENT_WAIT_END              : {break;}
+                            case ROB_END_MISS                    : {break;}
+                            case ROB_END                         : {break;}
+                              
+                              // can't have miss speculation -> invalid state
+                            default                              : 
+                              {
+                                throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str()));
+                                break;
+                              }
+                            }
+                        }
+                      
+                      //------------------------------------------------------
+                      // test if instruction is not speculative
+                      //------------------------------------------------------
+                      entry->speculative = speculative;
+//                    if (entry->depth == depth_min)
+                      // test if instruction is speculative (depth != depth_min)
+                      if (not speculative)
+                        {
+                          switch (state)
+                            {
+                            case ROB_END_OK_SPECULATIVE          : {state = ROB_END_OK                 ; break;}
+                            case ROB_END_KO_SPECULATIVE          : {state = ROB_END_KO                 ; break;}
+                            case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS        ; break;}
+                            case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_LOAD_MISS_UPDATE   ; break;}
+                            default : {break;} // else, no change
+                            }
+                        }
+                    
+                      //------------------------------------------------------
+                      // test if instruction wait head and is the top of rob
+                      //------------------------------------------------------
+                      // TODO : retire OOO
+                      if (i == 0)
+                        {
+                          switch (state)
+                            {
+//                             case ROB_STORE_WAIT_HEAD_OK      : {state = ROB_STORE_HEAD_OK;        break;}
+                            case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;}
+                            default : {break;} // else, no change
+                            }
+                        }
+                    
+                      // Write new state
+                      entry->state = state;
+                      
+                      // Test if this instruction is the last of event
+                      if ((reg_EVENT_STATE         [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT) and
+                          (reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] == num_bank            ) and
+                          (reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] == entry->ptr          ))
+                        {
+                          log_printf(TRACE,Commit_unit,FUNCTION,"  * Stop Scan !!!");
+                          
+                          EVENT_LAST [front_end_id][context_id] = true;
+                        }
+                    }
+                }
+            }
+        }
+
+
 
 #ifdef STATISTICS
@@ -709,4 +1025,9 @@
         *(_stat_bank_nb_inst [i]) += _rob[i].size();
 #endif
+      }
+
+    // ===================================================================
+    // =====[ OTHER ]=====================================================
+    // ===================================================================
 
 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true)
@@ -715,4 +1036,5 @@
       log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank_head : %d",reg_NUM_BANK_HEAD);
       log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank_tail : %d",reg_NUM_BANK_TAIL);
+      log_printf(TRACE,Commit_unit,FUNCTION,"    * num_ptr_tail  : %d",reg_NUM_PTR_TAIL );
       
       for (uint32_t i=0; i<_param->_nb_front_end; i++)
@@ -720,69 +1042,90 @@
           {
             log_printf(TRACE,Commit_unit,FUNCTION,"    * [%d][%d] - %d",i,j,_param->_translate_num_context_to_num_thread [i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STATE  : %s",toString(reg_EVENT_STATE [i][j]).c_str());
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_FLUSH  : %d",reg_EVENT_FLUSH [i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STOP   : %d",reg_EVENT_STOP  [i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_ALL  : %d",reg_NB_INST_COMMIT_ALL[i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_MEM  : %d",reg_NB_INST_COMMIT_MEM[i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * PC_CURRENT   : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * PC_NEXT      : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STATE       : %s - %s",toString(reg_EVENT_STATE [i][j]).c_str(),toString(commit_event_state_to_event_state(reg_EVENT_STATE [i][j])).c_str());
+//          log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_FLUSH       : %d",reg_EVENT_FLUSH [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STOP        : %d",reg_EVENT_STOP  [i][j]);
+//             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT             : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_PACKET      : %d",reg_EVENT_PACKET[i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_LAST        : %d",reg_EVENT_LAST [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_LAST        : %d (bank %d, ptr %d)",((reg_EVENT_LAST_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [i][j]), reg_EVENT_LAST_NUM_BANK [i][j],reg_EVENT_LAST_NUM_PTR [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_ALL       : %d",reg_NB_INST_COMMIT_ALL[i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_MEM       : %d",reg_NB_INST_COMMIT_MEM[i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * PC_CURRENT        : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * PC_NEXT           : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2);
           }
 
+      std::list<entry_t*>::iterator iter [_param->_nb_bank];
       for (uint32_t i=0; i<_param->_nb_bank; i++)
         {
           uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
-
-          log_printf(TRACE,Commit_unit,FUNCTION,"      * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]);
+//           log_printf(TRACE,Commit_unit,FUNCTION,"      * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]);
+
+          iter [num_bank] = _rob[num_bank].begin();
+        }
+
+      bool all_empty = false;
+      while (not all_empty)
+        {
+          all_empty = true;
           
-          for (std::list<entry_t*>::iterator it=_rob[num_bank].begin();
-               it!=_rob[num_bank].end();
-               it++)
+          for (uint32_t i=0; i<_param->_nb_bank; i++)
             {
-              log_printf(TRACE,Commit_unit,FUNCTION,"        [%.4d][%.4d] (%.4d) %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s",
-                         num_bank                       ,
-                         (*it)->ptr                     ,
-                         (((*it)->ptr << _param->_shift_num_slot) | num_bank),
-                         (*it)->front_end_id            ,
-                         (*it)->context_id              ,
-                         (*it)->rename_unit_id          ,
-                         (*it)->depth                   ,
-                         (*it)->type                    ,
-                         (*it)->operation               ,
-                         (*it)->is_delay_slot           ,
-                         (*it)->use_store_queue         ,
-                         (*it)->store_queue_ptr_write   ,
-                         (*it)->use_load_queue          ,
-                         (*it)->load_queue_ptr_write    ,
-                         toString((*it)->state).c_str() );
-              log_printf(TRACE,Commit_unit,FUNCTION,"                     %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ",
-                         (*it)->read_ra                 ,
-                         (*it)->num_reg_ra_log          ,
-                         (*it)->num_reg_ra_phy          ,
-                         (*it)->read_rb                 ,
-                         (*it)->num_reg_rb_log          ,
-                         (*it)->num_reg_rb_phy          ,
-                         (*it)->read_rc                 ,
-                         (*it)->num_reg_rc_log          ,
-                         (*it)->num_reg_rc_phy          ,
-                         (*it)->write_rd                ,
-                         (*it)->num_reg_rd_log          ,
-                         (*it)->num_reg_rd_phy_old      ,
-                         (*it)->num_reg_rd_phy_new      ,
-                         (*it)->write_re                ,
-                         (*it)->num_reg_re_log          ,
-                         (*it)->num_reg_re_phy_old      ,
-                         (*it)->num_reg_re_phy_new      );
-              
-              log_printf(TRACE,Commit_unit,FUNCTION,"                     %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)",
-                         (*it)->exception_use ,
-                         (*it)->exception     ,
-                         (*it)->flags         ,
-                         (*it)->no_sequence   ,
-                         (*it)->speculative   ,
-                         (*it)->address       ,
-                         (*it)->address<<2    ,
-                         (*it)->address_next  ,
-                         (*it)->address_next<<2
-                         );
+              uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
+      
+              std::list<entry_t*>::iterator it = iter[num_bank];        
+              if (it != _rob[num_bank].end())
+                {
+                  all_empty = false;
+
+                  log_printf(TRACE,Commit_unit,FUNCTION,"        [%.4d][%.4d] (%.4d) %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s",
+                             num_bank                       ,
+                             (*it)->ptr                     ,
+                             (((*it)->ptr << _param->_shift_num_slot) | num_bank),
+                             (*it)->front_end_id            ,
+                             (*it)->context_id              ,
+                             (*it)->rename_unit_id          ,
+                             (*it)->depth                   ,
+                             (*it)->type                    ,
+                             (*it)->operation               ,
+                             (*it)->is_delay_slot           ,
+                             (*it)->use_store_queue         ,
+                             (*it)->store_queue_ptr_write   ,
+                             (*it)->use_load_queue          ,
+                             (*it)->load_queue_ptr_write    ,
+                             toString((*it)->state).c_str() );
+                  log_printf(TRACE,Commit_unit,FUNCTION,"                     %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ",
+                             (*it)->read_ra                 ,
+                             (*it)->num_reg_ra_log          ,
+                             (*it)->num_reg_ra_phy          ,
+                             (*it)->read_rb                 ,
+                             (*it)->num_reg_rb_log          ,
+                             (*it)->num_reg_rb_phy          ,
+                             (*it)->read_rc                 ,
+                             (*it)->num_reg_rc_log          ,
+                             (*it)->num_reg_rc_phy          ,
+                             (*it)->write_rd                ,
+                             (*it)->num_reg_rd_log          ,
+                             (*it)->num_reg_rd_phy_old      ,
+                             (*it)->num_reg_rd_phy_new      ,
+                             (*it)->write_re                ,
+                             (*it)->num_reg_re_log          ,
+                             (*it)->num_reg_re_phy_old      ,
+                             (*it)->num_reg_re_phy_new      );
+                  
+                  log_printf(TRACE,Commit_unit,FUNCTION,"                     %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)",
+                             (*it)->exception_use ,
+                             (*it)->exception     ,
+                             (*it)->flags         ,
+                             (*it)->no_sequence   ,
+                             (*it)->speculative   ,
+                             (*it)->address       ,
+                             (*it)->address<<2    ,
+                             (*it)->address_next  ,
+                             (*it)->address_next<<2
+                             );
+                  
+                  iter [num_bank] ++;
+                }
             }
         }
@@ -822,5 +1165,5 @@
               )
           if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id])
-            throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (%x) is different of reg_PC_CURRENT[%d][%d] (%x).\n"),
+            throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (0x%x) is different of reg_PC_CURRENT[%d][%d] (0x%x).\n"),
                                                  entry->address,
                                                  entry->front_end_id,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp	(revision 122)
@@ -40,6 +40,6 @@
       test.error(_("nb_bank must be a multiple of size_queue.\n"));
 
-    if (_nb_inst_reexecute != 1)
-      test.error(_("nb_inst_reexecute must be set at 1. Anothers value is unsupported.\n"));
+//     if (_nb_inst_reexecute != 1)
+//       test.error(_("nb_inst_reexecute must be set at 1. Anothers value is unsupported.\n"));
 
     for (uint32_t i=0; i<_nb_front_end; ++i)
