Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h	(revision 122)
@@ -121,4 +121,6 @@
   public    : SC_IN (Toperation_t      )  ***  in_ISSUE_OOO_ENGINE_OPERATION                ;//[nb_ooo_engine][nb_inst_issue]
   public    : SC_IN (Tlsq_ptr_t        )  ***  in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE    ;//[nb_ooo_engine][nb_inst_issue]
+  public    : SC_IN (Tlsq_ptr_t        )  ***  in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ     ;//[nb_ooo_engine][nb_inst_issue]
+  public    : SC_IN (Tcontrol_t        )  ***  in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY        ;//[nb_ooo_engine][nb_inst_issue]
   public    : SC_IN (Tlsq_ptr_t        )  ***  in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE     ;//[nb_ooo_engine][nb_inst_issue]
   public    : SC_IN (Tcontrol_t        )  ***  in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT             ;//[nb_ooo_engine][nb_inst_issue]
@@ -144,4 +146,6 @@
   public    : SC_OUT(Ttype_t           )  *** out_ISSUE_EXECUTE_LOOP_TYPE                   ;//[nb_execute_loop][nb_read_unit]
   public    : SC_OUT(Tlsq_ptr_t        )  *** out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE  ;//[nb_execute_loop][nb_read_unit]
+  public    : SC_OUT(Tlsq_ptr_t        )  *** out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_READ   ;//[nb_execute_loop][nb_read_unit]
+  public    : SC_OUT(Tcontrol_t        )  *** out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_EMPTY      ;//[nb_execute_loop][nb_read_unit]
   public    : SC_OUT(Tlsq_ptr_t        )  *** out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE   ;//[nb_execute_loop][nb_read_unit]
   public    : SC_OUT(Tcontrol_t        )  *** out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT           ;//[nb_execute_loop][nb_read_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue.cpp	(revision 122)
@@ -168,4 +168,6 @@
                         << (*(in_ISSUE_OOO_ENGINE_OPERATION             [i][j]))
                         << (*(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE [i][j]))
+                        << (*(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ  [i][j]))
+                        << (*(in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY     [i][j]))
                         << (*(in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT          [i][j]))
                         << (*(in_ISSUE_OOO_ENGINE_IMMEDIAT              [i][j]))
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp	(revision 122)
@@ -143,4 +143,6 @@
       _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_OPERATION                ,"OPERATION"            ,Toperation_t      ,_param->_size_operation       ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
       _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE    ,"STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t        ,_param->_size_store_queue_ptr ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
+      _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ     ,"STORE_QUEUE_PTR_READ" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
+      _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY        ,"STORE_QUEUE_EMPTY"    ,Tcontrol_t        ,1                             ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
       _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE     ,"LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr  ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
       _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT             ,"HAS_IMMEDIAT"         ,Tcontrol_t        ,1                             ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
@@ -172,4 +174,6 @@
       _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_TYPE                   ,"TYPE"                 ,Ttype_t           ,_param->_size_type            ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
       _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE  ,"STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t        ,_param->_size_store_queue_ptr ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
+      _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_READ   ,"STORE_QUEUE_PTR_READ" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
+      _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_EMPTY      ,"STORE_QUEUE_EMPTY"    ,Tcontrol_t        ,1                             ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
       _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE   ,"LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr  ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
       _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT           ,"HAS_IMMEDIAT"         ,Tcontrol_t        ,1                             ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_deallocation.cpp	(revision 122)
@@ -78,4 +78,6 @@
         DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_OPERATION                ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_operation);
         DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE    ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_store_queue_ptr);
+        DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ     ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_store_queue_ptr);
+        DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY        ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],1);
         DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE     ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_load_queue_ptr);
         DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT             ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],1);
@@ -101,4 +103,6 @@
         DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_TYPE                   ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_type);
         DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE  ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_store_queue_ptr);
+        DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_READ   ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_store_queue_ptr);
+        DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_EMPTY      ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],1);
         DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE   ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_load_queue_ptr);
         DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT           ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_issue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_issue.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_issue.cpp	(revision 122)
@@ -194,4 +194,6 @@
 			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_TYPE                  [num_execute_loop][num_read_unit],type);
 			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE [num_ooo_engine][num_inst_issue_queue]));
+			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_READ  [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ  [num_ooo_engine][num_inst_issue_queue]));
+			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_EMPTY     [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY     [num_ooo_engine][num_inst_issue_queue]));
 			        if (_param->_have_port_load_queue_ptr)
 			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE  [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE  [num_ooo_engine][num_inst_issue_queue]));
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h	(revision 122)
@@ -85,4 +85,6 @@
   public    : SC_IN (Ttype_t           )    *  in_EXECUTE_IN_TYPE           ;
   public    : SC_IN (Tlsq_ptr_t        )    *  in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE;
+  public    : SC_IN (Tlsq_ptr_t        )    *  in_EXECUTE_IN_STORE_QUEUE_PTR_READ ;
+  public    : SC_IN (Tcontrol_t        )    *  in_EXECUTE_IN_STORE_QUEUE_EMPTY    ;
   public    : SC_IN (Tlsq_ptr_t        )    *  in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE;
   public    : SC_IN (Tcontrol_t        )    *  in_EXECUTE_IN_HAS_IMMEDIAT   ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp	(revision 122)
@@ -63,4 +63,6 @@
       ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_TYPE                  ,"type"                 ,Ttype_t           , _param->_size_type         );
       ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE ,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
+      ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_STORE_QUEUE_PTR_READ  ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
+      ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_STORE_QUEUE_EMPTY     ,"store_queue_empty"    ,Tcontrol_t        , 1);
       ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE  ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr);
       ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_HAS_IMMEDIAT          ,"has_immediat"         ,Tcontrol_t        , 1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp	(revision 122)
@@ -39,4 +39,6 @@
         DELETE0_SIGNAL( in_EXECUTE_IN_TYPE                  , _param->_size_type         );
         DELETE0_SIGNAL( in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE ,_param->_size_store_queue_ptr);
+        DELETE0_SIGNAL( in_EXECUTE_IN_STORE_QUEUE_PTR_READ  ,_param->_size_store_queue_ptr);
+        DELETE0_SIGNAL( in_EXECUTE_IN_STORE_QUEUE_EMPTY     , 1);
         DELETE0_SIGNAL( in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE  ,_param->_size_load_queue_ptr);
         DELETE0_SIGNAL( in_EXECUTE_IN_HAS_IMMEDIAT          , 1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 122)
@@ -103,4 +103,6 @@
   public    : SC_IN (Ttype_t           )   **  in_MEMORY_IN_TYPE                 ;//[nb_inst_memory]
   public    : SC_IN (Tlsq_ptr_t        )   **  in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;//[nb_inst_memory]
+  public    : SC_IN (Tlsq_ptr_t        )   **  in_MEMORY_IN_STORE_QUEUE_PTR_READ ;//[nb_inst_memory]
+  public    : SC_IN (Tcontrol_t        )   **  in_MEMORY_IN_STORE_QUEUE_EMPTY    ;//[nb_inst_memory]
   public    : SC_IN (Tlsq_ptr_t        )   **  in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_memory]
   public    : SC_IN (Tcontrol_t        )   **  in_MEMORY_IN_HAS_IMMEDIAT         ;//[nb_inst_memory]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h	(revision 122)
@@ -73,4 +73,5 @@
 //public    : Tgeneral_address_t   _num_reg_rd          ;
   public    : Texception_t         _exception           ;
+  public    : bool                 _send_commit         ;
 
     friend std::ostream & operator << (std::ostream& os, const Tstore_queue_entry_t & x) 
@@ -112,4 +113,6 @@
   public    : Tlsq_ptr_t                         _load_queue_ptr_write ;
   public    : Tlsq_ptr_t                         _store_queue_ptr_write;
+  public    : Tlsq_ptr_t                         _store_queue_ptr_read ;
+  public    : Tcontrol_t                         _store_queue_empty    ;
   public    : Tdcache_address_t                  _address              ;
   public    : Tcontrol_t                         _write_rd             ;
@@ -123,5 +126,5 @@
 		<< "   * context, front_end, ooo_engine_id : " << toString(x._context_id) << " - " << toString(x._front_end_id) << " - " << toString(x._ooo_engine_id) << std::endl
 		<< "   * operation                         : " << toString(x._operation) << std::endl
-		<< "   * load, store ptr_write             : " << toString(x._load_queue_ptr_write) << " - " << toString(x._store_queue_ptr_write) << std::endl
+		<< "   * load, store ptr_(write/read) empty: " << toString(x._load_queue_ptr_write) << " - " << toString(x._store_queue_ptr_write) << " - " << toString(x._store_queue_ptr_read) << " - " << toString(x._store_queue_empty) << std::endl
 		<< "   * exception                         : " << toString(x._exception) << std::endl
 		<< std::hex
@@ -166,4 +169,6 @@
   public    : Toperation_t         _operation        ;
   public    : Tlsq_ptr_t           _store_queue_ptr_write;
+  public    : Tlsq_ptr_t           _store_queue_ptr_read ;
+  public    : Tcontrol_t           _store_queue_empty    ;
   public    : Tdcache_address_t    _address          ;
   public    : Tdcache_address_t    _check_hit_byte   ; 
@@ -183,5 +188,5 @@
 		<< "   * context, front_end, ooo_engine_id : " << toString(x._context_id) << " - " << toString(x._front_end_id) << " - " << toString(x._ooo_engine_id) << std::endl
 		<< "   * operation                         : " << toString(x._operation) << std::endl
-		<< "   * store_queue_ptr_write             : " << toString(x._store_queue_ptr_write) << std::endl
+		<< "   * store_queue ptr_(write,read) empty: " << toString(x._store_queue_ptr_write) << " - " << toString(x._store_queue_ptr_read) << " - " << toString(x._store_queue_empty) <<std::endl
 		<< "   * exception                         : " << toString(x._exception) << std::endl
 		<< "   * check_hit, check_hit_byte         : " << toString(x._check_hit) << " - " << toString(x._check_hit_byte) << std::endl
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 122)
@@ -65,4 +65,6 @@
       ALLOC1_SIGNAL_IN ( in_MEMORY_IN_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type                 );
       ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr      );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr      );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1);
       ALLOC1_SIGNAL_IN ( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr       );
       ALLOC1_SIGNAL_IN ( in_MEMORY_IN_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                                  );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 122)
@@ -45,4 +45,6 @@
     DELETE1_SIGNAL( in_MEMORY_IN_TYPE                 ,_param->_nb_inst_memory,_param->_size_type                 );
     DELETE1_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory,_param->_size_store_queue_ptr      );
+    DELETE1_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_READ ,_param->_nb_inst_memory,_param->_size_store_queue_ptr      );
+    DELETE1_SIGNAL( in_MEMORY_IN_STORE_QUEUE_EMPTY    ,_param->_nb_inst_memory,1);
     DELETE1_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory,_param->_size_load_queue_ptr       );
     DELETE1_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT         ,_param->_nb_inst_memory,1                                  );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 122)
@@ -39,4 +39,5 @@
 //  Tspecial_address_t memory_out_num_reg_re    = 0;
 //  Tspecial_data_t    memory_out_data_re       = 0;
+    Tcontrol_t         memory_out_no_sequence   = 0;
     Texception_t       memory_out_exception     = 0;
 
@@ -98,25 +99,44 @@
       {
 	log_printf(TRACE,Load_store_unit,FUNCTION,"    * Store queue");
-        // Can retire an store instruction if :
-        //  * state is commit
-        //  * none load must check this store
-	if ((_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) and
-            (reg_STORE_QUEUE_NB_CHECK [reg_STORE_QUEUE_PTR_READ] == 0))
-	  {
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",reg_STORE_QUEUE_PTR_READ);
-
-	    internal_MEMORY_OUT_VAL          = 1;
-	    internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
-	    
-	    memory_out_context_id    = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id;
-	    memory_out_front_end_id  = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id;
-	    memory_out_ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id;
-	    memory_out_packet_id     = _store_queue [reg_STORE_QUEUE_PTR_READ]._packet_id ;
-//          memory_out_write_rd  	 
-//          memory_out_num_reg_rd	 
-	    memory_out_data_rd       = _store_queue [reg_STORE_QUEUE_PTR_READ]._address; // to the exception
-	    memory_out_exception     = _store_queue [reg_STORE_QUEUE_PTR_READ]._exception;
-	  }
-      }
+
+	for (uint32_t i=0; i<_param->_size_store_queue; ++i)
+	  {
+	    internal_MEMORY_OUT_PTR = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
+	    // Can retire an store instruction if :
+	    //  * state is commit
+	    //  * none load must check this store
+
+
+	    bool val_head = ((i==0) and
+			     (_store_queue [internal_MEMORY_OUT_PTR]._state       == STORE_QUEUE_COMMIT) and
+			     (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == true) and
+			     (reg_STORE_QUEUE_NB_CHECK [internal_MEMORY_OUT_PTR] == 0)
+			     );
+
+	    bool val_commit = ((_store_queue [internal_MEMORY_OUT_PTR]._state       != STORE_QUEUE_EMPTY) and
+			       (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == false));
+
+	    if (val_head or val_commit)
+	      {
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
+		
+		internal_MEMORY_OUT_VAL          = 1;
+		internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
+		
+		memory_out_context_id    = _store_queue [internal_MEMORY_OUT_PTR]._context_id;
+		memory_out_front_end_id  = _store_queue [internal_MEMORY_OUT_PTR]._front_end_id;
+		memory_out_ooo_engine_id = _store_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
+		memory_out_packet_id     = _store_queue [internal_MEMORY_OUT_PTR]._packet_id ;
+//              memory_out_write_rd  	 
+//              memory_out_num_reg_rd	 
+		memory_out_data_rd       = _store_queue [internal_MEMORY_OUT_PTR]._address; // to the exception
+		memory_out_exception     = _store_queue [internal_MEMORY_OUT_PTR]._exception;
+		memory_out_no_sequence   = val_commit;
+		break; // find an entry
+	      }
+
+	  }
+      }
+
     // write output
     PORT_WRITE(out_MEMORY_OUT_VAL          [0], internal_MEMORY_OUT_VAL);
@@ -142,6 +162,10 @@
     PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], 0);
     PORT_WRITE(out_MEMORY_OUT_EXCEPTION    [0], memory_out_exception    );
-    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  [0], memory_out_no_sequence  );// hack
+#ifdef DEBUG
+    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], memory_out_data_rd);
+#else
     PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], 0);
+#endif
 
     // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 122)
@@ -275,10 +275,14 @@
 		  // =======================
 		  
-		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue [%d]",reg_STORE_QUEUE_PTR_READ);
+		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue [%d]",internal_MEMORY_OUT_PTR);
 	    
 		  // Entry flush and increase the read pointer
-		  _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY;
-		  
-		  reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue;
+		  if (_store_queue [internal_MEMORY_OUT_PTR]._send_commit)
+		    {
+		      _store_queue [internal_MEMORY_OUT_PTR]._state = STORE_QUEUE_EMPTY;
+		      reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue;
+		    }
+		  else
+		    _store_queue [internal_MEMORY_OUT_PTR]._send_commit = true;
 
 		  break;
@@ -339,19 +343,21 @@
 	  {
             // Get an index from load queue
-	    uint32_t index_load = (i + reg_LOAD_QUEUE_CHECK_PRIORITY)%_param->_size_load_queue;
+	    uint32_t index_load_queue = (i + reg_LOAD_QUEUE_CHECK_PRIORITY)%_param->_size_load_queue;
 
             // Test if this load must ckecked store queue
-	    if (((_load_queue[index_load]._state == LOAD_QUEUE_WAIT_CHECK) or
-		 (_load_queue[index_load]._state == LOAD_QUEUE_COMMIT_CHECK) or
-		 (_load_queue[index_load]._state == LOAD_QUEUE_CHECK)) and
-		is_operation_memory_load(_load_queue[index_load]._operation))
+	    if (((_load_queue[index_load_queue]._state == LOAD_QUEUE_WAIT_CHECK) or
+		 (_load_queue[index_load_queue]._state == LOAD_QUEUE_COMMIT_CHECK) or
+		 (_load_queue[index_load_queue]._state == LOAD_QUEUE_CHECK)) and
+		is_operation_memory_load(_load_queue[index_load_queue]._operation))
 	      {
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * Find a load : %d",index_load);
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * Find a load : %d",index_load_queue);
 
 		nb_check++; // use one port
 
 		// find a entry that it need a check
-		Tlsq_ptr_t index_store     = _load_queue[index_load]._store_queue_ptr_write;
-// 		Tlsq_ptr_t index_store_old = index_store;
+		Tlsq_ptr_t store_queue_ptr_write = _load_queue[index_load_queue]._store_queue_ptr_write;
+		Tlsq_ptr_t store_queue_ptr_read  = _load_queue[index_load_queue]._store_queue_ptr_read ;
+ 		Tlsq_ptr_t store_queue_empty     = _load_queue[index_load_queue]._store_queue_empty    ;
+// 		Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write;
 
                 // Init variable
@@ -365,10 +371,14 @@
 		//  * when a store is out of store queue, also it was in head of re order buffer. Also, they are none previous load.
 
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * index_store : %d",index_store);
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * ptr_read    : %d",reg_STORE_QUEUE_PTR_READ);
-
-		if (index_store == reg_STORE_QUEUE_PTR_READ)
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_ptr_write    : %d",store_queue_ptr_write);
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_ptr_read     : %d",store_queue_ptr_read );
+// 		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_empty        : %d",store_queue_empty );
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * reg_STORE_QUEUE_PTR_READ : %d",reg_STORE_QUEUE_PTR_READ);
+
+ 		if ((store_queue_ptr_write ==     store_queue_ptr_read) or
+		    (store_queue_ptr_write == reg_STORE_QUEUE_PTR_READ))
+// 		if (store_queue_empty)
 		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * index_store == reg_STORE_QUEUE_PTR_READ");
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write == store_queue_ptr_read");
 		    end_check    = true;
 		    change_state = true;
@@ -376,12 +386,12 @@
 		else
 		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * index_store != reg_STORE_QUEUE_PTR_READ");
-
-		    index_store = (index_store-1)%(_param->_size_store_queue); // store_queue_ptr_write target the next slot to write, also the slot is not significatif when the load is renaming
-
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * index_store : %d",index_store);
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write != store_queue_ptr_read");
+
+		    store_queue_ptr_write = (store_queue_ptr_write-1)%(_param->_size_store_queue); // store_queue_ptr_write target the next slot to write, also the slot is not significatif when the load is renaming
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write : %d",store_queue_ptr_write);
 		    
                     // switch on store_queue state
-		    switch (_store_queue[index_store]._state)
+		    switch (_store_queue[store_queue_ptr_write]._state)
 		      {
 		      case STORE_QUEUE_VALID_NO_SPECULATIVE : 
@@ -397,9 +407,9 @@
 			  // Test thread id
 			  if (_param->_have_port_context_id)
-			    test_thread_id &= (_load_queue[index_load]._context_id    == _store_queue[index_store]._context_id);
+			    test_thread_id &= (_load_queue[index_load_queue]._context_id    == _store_queue[store_queue_ptr_write]._context_id);
 			  if (_param->_have_port_front_end_id)
-			    test_thread_id &= (_load_queue[index_load]._front_end_id  == _store_queue[index_store]._front_end_id);
+			    test_thread_id &= (_load_queue[index_load_queue]._front_end_id  == _store_queue[store_queue_ptr_write]._front_end_id);
 			  if (_param->_have_port_ooo_engine_id)
-			    test_thread_id &= (_load_queue[index_load]._ooo_engine_id == _store_queue[index_store]._ooo_engine_id);
+			    test_thread_id &= (_load_queue[index_load_queue]._ooo_engine_id == _store_queue[store_queue_ptr_write]._ooo_engine_id);
 			  
 			  if (test_thread_id)
@@ -408,6 +418,6 @@
 
 			      log_printf(TRACE,Load_store_unit,FUNCTION,"        * load and store is the same thread.");
-			      Tdcache_address_t load_addr  = _load_queue [index_load ]._address;
-			      Tdcache_address_t store_addr = _store_queue[index_store]._address;
+			      Tdcache_address_t load_addr  = _load_queue [index_load_queue ]._address;
+			      Tdcache_address_t store_addr = _store_queue[store_queue_ptr_write]._address;
 			      
 			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * load_addr                     : %.8x.",load_addr );
@@ -435,10 +445,10 @@
                                   bool is_big_endian = true;
 
-				  Tgeneral_data_t   load_data      = _load_queue [index_load ]._rdata  ;
-				  Tgeneral_data_t   store_data     = _store_queue[index_store]._wdata  ;
-                                  Tdcache_address_t check_hit_byte = _load_queue [index_load ]._check_hit_byte;
-                                  Tcontrol_t        check_hit      = _load_queue [index_load ]._check_hit;
-                                  uint32_t          load_size_access  = memory_size(_load_queue [index_load ]._operation)>>3;
-                                  uint32_t          store_size_access = memory_size(_store_queue[index_store]._operation)>>3;
+				  Tgeneral_data_t   load_data      = _load_queue [index_load_queue ]._rdata  ;
+				  Tgeneral_data_t   store_data     = _store_queue[store_queue_ptr_write]._wdata  ;
+                                  Tdcache_address_t check_hit_byte = _load_queue [index_load_queue ]._check_hit_byte;
+                                  Tcontrol_t        check_hit      = _load_queue [index_load_queue ]._check_hit;
+                                  uint32_t          load_size_access  = memory_size(_load_queue [index_load_queue ]._operation)>>3;
+                                  uint32_t          store_size_access = memory_size(_store_queue[store_queue_ptr_write]._operation)>>3;
 
                                   log_printf(TRACE,Load_store_unit,FUNCTION,"            * is_big_endian           : %d",is_big_endian);
@@ -464,5 +474,5 @@
                                     }
 
-                                  uint32_t store_nb_byte     = (1<<memory_access(_store_queue[index_store]._operation));
+                                  uint32_t store_nb_byte     = (1<<memory_access(_store_queue[store_queue_ptr_write]._operation));
 
                                   // Take interval to the store
@@ -473,5 +483,5 @@
 				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_num_byte_max      : %d",store_num_byte_max);
 
-//                                   uint32_t load_nb_byte      = (1<<memory_access(_load_queue[index_load]._operation));
+//                                   uint32_t load_nb_byte      = (1<<memory_access(_load_queue[index_load_queue]._operation));
 
 // 				  uint32_t load_num_byte_min = (load_addr & _param->_mask_address_lsb);
@@ -517,5 +527,5 @@
 
 //                                           // store duplicate = all store access can be see as full size_data store
-// //                                           uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load ]._operation));
+// //                                           uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load_queue ]._operation));
 
 // //                                           int32_t diff = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1));
@@ -597,7 +607,7 @@
                                     }
 
-				  _load_queue[index_load]._rdata          = load_data;
-                                  _load_queue[index_load]._check_hit_byte = check_hit_byte;
-                                  _load_queue[index_load]._check_hit      = check_hit;
+				  _load_queue[index_load_queue]._rdata          = load_data;
+                                  _load_queue[index_load_queue]._check_hit_byte = check_hit_byte;
+                                  _load_queue[index_load_queue]._check_hit      = check_hit;
 
 				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data  (after) : 0x%.8x",load_data);
@@ -609,5 +619,5 @@
 				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * mask_check_hit_byte: %x",_param->_mask_check_hit_byte);
 				  // The check is finish if all bit is set
-				  end_check = (_load_queue[index_load]._check_hit_byte == _param->_mask_check_hit_byte);
+				  end_check = (_load_queue[index_load_queue]._check_hit_byte == _param->_mask_check_hit_byte);
 
 				}
@@ -629,25 +639,32 @@
 		  {
 		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * next");
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * new store_queue_ptr_write : %d",index_store);
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * new store_queue_ptr_write : %d",store_queue_ptr_write);
 
 		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * update reg_STORE_QUEUE_NB_CHECK");
 #ifdef DEBUG
-                    if (reg_STORE_QUEUE_NB_CHECK [index_store] == 0)
+                    if (reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write] == 0)
                       throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
 #endif
-                    reg_STORE_QUEUE_NB_CHECK [index_store] --;
-
-// 		    if (_load_queue[index_load]._store_queue_ptr_write == 0)
-// 		      _load_queue[index_load]._store_queue_ptr_write = _param->_size_store_queue-1;
+
+                    reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write] --;
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 1 [%d] <- %d", store_queue_ptr_write,reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write]);
+
+		    if ((store_queue_ptr_write ==     store_queue_ptr_read) or
+			(store_queue_ptr_write == reg_STORE_QUEUE_PTR_READ))
+		      {
+// 			store_queue_empty = true;
+			end_check         = true;
+			change_state      = true;
+		      }
+
+// 		    if (_load_queue[index_load_queue]._store_queue_ptr_write == 0)
+// 		      _load_queue[index_load_queue]._store_queue_ptr_write = _param->_size_store_queue-1;
 // 		    else
-// 		      _load_queue[index_load]._store_queue_ptr_write --;
-		    _load_queue[index_load]._store_queue_ptr_write = index_store; // because the index store have be decrease
-
-		    // FIXME : peut n'est pas obliger de faire cette comparaison. Au prochain cycle on le détectera que les pointeur sont égaux. Ceci évitera d'avoir deux comparateurs avec le registre "reg_STORE_QUEUE_PTR_READ"
-		    if (index_store == reg_STORE_QUEUE_PTR_READ)
-		      {
-			end_check    = true;
-			change_state = true;
-		      }
+// 		      _load_queue[index_load_queue]._store_queue_ptr_write --;
+		    _load_queue[index_load_queue]._store_queue_ptr_write = store_queue_ptr_write; // because the index store have be decrease
+ 		    _load_queue[index_load_queue]._store_queue_empty     = store_queue_empty; // because the index store have be decrease
+
+		    // FIXME : peut n'est pas obliger de faire cette comparaison. Au prochain cycle on le détectera que les pointeur sont égaux. Ceci évitera d'avoir deux comparateurs avec le registre "store_queue_ptr_read"
 		  }
 
@@ -657,12 +674,12 @@
                     log_printf(TRACE,Load_store_unit,FUNCTION,"              * end_check : %d",end_check);
 
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * state old : %s",toString(_load_queue[index_load]._state).c_str());
-
-		    switch (_load_queue[index_load]._state)
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * state old : %s",toString(_load_queue[index_load_queue]._state).c_str());
+
+		    switch (_load_queue[index_load_queue]._state)
 		      {
 		      case LOAD_QUEUE_WAIT_CHECK   : 
                         {
 			  if (end_check)
-                            _load_queue[index_load]._state = LOAD_QUEUE_WAIT  ; 
+                            _load_queue[index_load_queue]._state = LOAD_QUEUE_WAIT  ; 
                           break;
                         }
@@ -670,7 +687,7 @@
 			{
 			  if (end_check)
-			    _load_queue[index_load]._state = LOAD_QUEUE_COMMIT; 
+			    _load_queue[index_load_queue]._state = LOAD_QUEUE_COMMIT; 
 			  else
-			    _load_queue[index_load]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end
+			    _load_queue[index_load_queue]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end
 			  break;
 			}
@@ -678,13 +695,13 @@
 			{
 			  if (end_check)
-			    _load_queue[index_load]._state     = LOAD_QUEUE_COMMIT;
+			    _load_queue[index_load_queue]._state     = LOAD_QUEUE_COMMIT;
 
 			  // check find a bypass. A speculative load have been committed : report a speculation miss.
-			  if ((_load_queue[index_load]._check_hit != 0) and 
-                              (_load_queue[index_load]._write_rd  == 0) // is commit
+			  if ((_load_queue[index_load_queue]._check_hit != 0) and 
+                              (_load_queue[index_load_queue]._write_rd  == 0) // is commit
                               )
 			    {
-			      _load_queue[index_load]._exception = EXCEPTION_MEMORY_MISS_SPECULATION;
-			      _load_queue[index_load]._write_rd  = 1; // write the good result
+			      _load_queue[index_load_queue]._exception = EXCEPTION_MEMORY_MISS_SPECULATION;
+			      _load_queue[index_load_queue]._write_rd  = 1; // write the good result
 
 #ifdef STATISTICS
@@ -698,13 +715,14 @@
 		      default : break;
 		      }
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * state new : %s",toString(_load_queue[index_load]._state).c_str());
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * exception : %d",_load_queue[index_load]._exception);
-
-                    if (end_check)
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * state new : %s",toString(_load_queue[index_load_queue]._state).c_str());
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * exception : %d",_load_queue[index_load_queue]._exception);
+
+                    if (end_check//  and not store_queue_empty
+			)
                       {
                         log_printf(TRACE,Load_store_unit,FUNCTION,"                * end check, decrease all nb_check");
                         
-                        uint32_t i=index_store;
-                        while (i!=reg_STORE_QUEUE_PTR_READ)
+                        uint32_t i=store_queue_ptr_write;
+                        while (i!=store_queue_ptr_read)
                           {
                             i=((i==0)?_param->_size_store_queue:i)-1;
@@ -714,8 +732,13 @@
                               throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
 #endif
-                            
+			    
                             reg_STORE_QUEUE_NB_CHECK [i] --;
+
+			    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 2 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
+
                             //i=(i+1)%_param->_size_store_queue;
                           }
+			
+			_load_queue[index_load_queue]._store_queue_empty = true; // end of check
                       }
 		  }
@@ -856,4 +879,5 @@
 		    _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
 		    _store_queue [index]._address              = address;
+		    _store_queue [index]._send_commit          = false;
 
 		    // reordering data
@@ -895,4 +919,6 @@
 		_speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
 		_speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._store_queue_ptr_read = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_READ [internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._store_queue_empty    = PORT_READ(in_MEMORY_IN_STORE_QUEUE_EMPTY    [internal_MEMORY_IN_PORT]);
 		_speculative_access_queue [index]._address              = address;
 		// NOTE : is operation is a load, then they are a result and must write in the register file
@@ -954,4 +980,7 @@
 	    bool         have_exception = (exception != EXCEPTION_MEMORY_NONE);
             bool         need_check= false;
+            Tlsq_ptr_t        store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;
+            Tlsq_ptr_t        store_queue_ptr_read  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_read ;
+            Tcontrol_t        store_queue_empty     = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_empty    ;
 	    
 	    if (have_exception)
@@ -962,8 +991,9 @@
 		  {
 		    // load and synchronisation
-		    if (must_check(operation))
+		    if (must_check(operation) and not store_queue_empty)
 		      {
 			// load
                         need_check = true;
+			
 			_load_queue [ptr_write]._state = LOAD_QUEUE_WAIT_CHECK;
 		      }
@@ -984,5 +1014,4 @@
 	    Tdcache_address_t address_lsb    = (address & _param->_mask_address_lsb);
 	    Tdcache_address_t check_hit_byte = gen_mask_not<Tdcache_address_t>(address_lsb+(memory_size(operation)>>3)-1,address_lsb) & _param->_mask_check_hit_byte;
-            Tlsq_ptr_t        store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;
 
 	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * address                 : 0x%.8x", address);
@@ -998,4 +1027,6 @@
 	    _load_queue [ptr_write]._operation             = operation;
 	    _load_queue [ptr_write]._store_queue_ptr_write = store_queue_ptr_write;
+	    _load_queue [ptr_write]._store_queue_ptr_read  = store_queue_ptr_read ;
+ 	    _load_queue [ptr_write]._store_queue_empty     = store_queue_empty    ;
 	    _load_queue [ptr_write]._address               = address;
 	    _load_queue [ptr_write]._check_hit_byte        = check_hit_byte;
@@ -1023,13 +1054,16 @@
 
             // Only load need check
-            if (need_check)
+            if (need_check//  and not store_queue_empty
+		)
 //             if (is_operation_memory_load(_load_queue [ptr_write]._operation))
               {
                 log_printf(TRACE,Load_store_unit,FUNCTION,"    * update nb_check");
                 log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_ptr_write : %d",store_queue_ptr_write);
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_ptr_read  : %d",store_queue_ptr_read );
+		log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_empty     : %d",store_queue_empty    );
                 log_printf(TRACE,Load_store_unit,FUNCTION,"      * reg_STORE_QUEUE_PTR_READ  : %d",reg_STORE_QUEUE_PTR_READ);
                 
                 uint32_t i=store_queue_ptr_write;
-                while (i!=reg_STORE_QUEUE_PTR_READ)
+                while (i!=store_queue_ptr_read)
                   {
                     i=((i==0)?_param->_size_store_queue:i)-1;
@@ -1038,4 +1072,6 @@
                     
                     reg_STORE_QUEUE_NB_CHECK [i] ++;
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 3 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
                   }
               }
@@ -1097,17 +1133,30 @@
 
                     
-                    uint32_t i=_load_queue[packet_id]._store_queue_ptr_write;
-                    while (i!=reg_STORE_QUEUE_PTR_READ)
-                      {
-                        i=((i==0)?_param->_size_store_queue:i)-1;
-                        
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write : %d", _load_queue[packet_id]._store_queue_ptr_write);
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_read  : %d", _load_queue[packet_id]._store_queue_ptr_read );
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_empty     : %d", _load_queue[packet_id]._store_queue_empty    );
+
+ 		    if (not _load_queue[packet_id]._store_queue_empty)
+		      {
+			uint32_t i=_load_queue[packet_id]._store_queue_ptr_write;
+			
+			while (i!=_load_queue[packet_id]._store_queue_ptr_read)
+			  {
+			    i=((i==0)?_param->_size_store_queue:i)-1;
+			    
 #ifdef DEBUG
-                        if (reg_STORE_QUEUE_NB_CHECK [i] == 0)
-                          throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
+			    if (reg_STORE_QUEUE_NB_CHECK [i] == 0)
+			      throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
 #endif
-                        
-                        reg_STORE_QUEUE_NB_CHECK [i] --;
-                        //i=(i+1)%_param->_size_store_queue;
-                      }
+			    
+			    reg_STORE_QUEUE_NB_CHECK [i] --;
+
+			    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 4 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
+
+			    //i=(i+1)%_param->_size_store_queue;
+			  }
+			_load_queue[packet_id]._store_queue_empty = true; // end of check
+
+		      }
 		  }
 		else
@@ -1150,5 +1199,5 @@
 	    uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
 
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d, %.2d %s",
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d %.1d, %.2d %s",
                        j,
                        _store_queue[j]._context_id          ,
@@ -1163,4 +1212,5 @@
                      //_store_queue[j]._num_reg_rd          ,
                        _store_queue[j]._exception           ,
+                       _store_queue[j]._send_commit         ,
                        reg_STORE_QUEUE_NB_CHECK  [j]        ,
                        toString(_store_queue[j]._state).c_str());
@@ -1174,5 +1224,5 @@
 	    uint32_t j = (*_speculative_access_queue_control)[i];
 
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.4d, %.2d, %s",
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d %.4d %.1d, %.8x, %.1d %.4d, %.2d, %s",
                        j,
                        _speculative_access_queue[j]._context_id          ,
@@ -1183,4 +1233,6 @@
                        _speculative_access_queue[j]._load_queue_ptr_write,
                        _speculative_access_queue[j]._store_queue_ptr_write,
+                       _speculative_access_queue[j]._store_queue_ptr_read ,
+                       _speculative_access_queue[j]._store_queue_empty    ,
                        _speculative_access_queue[j]._address             ,
                        _speculative_access_queue[j]._write_rd            ,
@@ -1198,5 +1250,5 @@
 	    uint32_t j = i;
 
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s",
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d %.1d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s",
                        j,
                        _load_queue[j]._context_id          ,
@@ -1206,4 +1258,6 @@
                        _load_queue[j]._operation           ,
                        _load_queue[j]._store_queue_ptr_write,
+                       _load_queue[j]._store_queue_ptr_read ,
+		       _load_queue[j]._store_queue_empty    ,
                        _load_queue[j]._address             ,
                        _load_queue[j]._check_hit_byte      , 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Read_queue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Read_queue.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Read_queue.h	(revision 122)
@@ -73,4 +73,6 @@
   public    : SC_IN (Ttype_t           )    *  in_READ_QUEUE_IN_TYPE                 ;
   public    : SC_IN (Tlsq_ptr_t        )    *  in_READ_QUEUE_IN_STORE_QUEUE_PTR_WRITE;
+  public    : SC_IN (Tlsq_ptr_t        )    *  in_READ_QUEUE_IN_STORE_QUEUE_PTR_READ ;
+  public    : SC_IN (Tcontrol_t        )    *  in_READ_QUEUE_IN_STORE_QUEUE_EMPTY    ;
   public    : SC_IN (Tlsq_ptr_t        )    *  in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE ;
   public    : SC_IN (Tcontrol_t        )    *  in_READ_QUEUE_IN_HAS_IMMEDIAT         ;
@@ -98,4 +100,6 @@
   public    : SC_OUT(Ttype_t           )    * out_READ_QUEUE_OUT_TYPE                 ;
   public    : SC_OUT(Tlsq_ptr_t        )    * out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE;
+  public    : SC_OUT(Tlsq_ptr_t        )    * out_READ_QUEUE_OUT_STORE_QUEUE_PTR_READ ;
+  public    : SC_OUT(Tcontrol_t        )    * out_READ_QUEUE_OUT_STORE_QUEUE_EMPTY    ;
   public    : SC_OUT(Tlsq_ptr_t        )    * out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE ;
   public    : SC_OUT(Tcontrol_t        )    * out_READ_QUEUE_OUT_HAS_IMMEDIAT         ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Types.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Types.h	(revision 122)
@@ -29,4 +29,6 @@
   public    : Ttype_t            _type         ;
   public    : Tlsq_ptr_t         _store_queue_ptr_write;
+  public    : Tlsq_ptr_t         _store_queue_ptr_read ;
+  public    : Tcontrol_t         _store_queue_empty    ;
   public    : Tlsq_ptr_t         _load_queue_ptr_write;
   public    : Tcontrol_t         _has_immediat ;
@@ -53,4 +55,6 @@
 		    << " * _type                  : " << toString(x._type         ) << std::endl
 		    << " * _store_queue_ptr_write : " << toString(x._store_queue_ptr_write) << std::endl
+		    << " * _store_queue_ptr_read  : " << toString(x._store_queue_ptr_read ) << std::endl
+		    << " * _store_queue_empty     : " << toString(x._store_queue_empty    ) << std::endl
 		    << " * _load_queue_ptr_write  : " << toString(x._load_queue_ptr_write ) << std::endl
 		    << " * _has_immediat          : " << toString(x._has_immediat ) << std::endl
@@ -81,4 +85,6 @@
   public    : Ttype_t            _type         ;
   public    : Tlsq_ptr_t         _store_queue_ptr_write;
+  public    : Tlsq_ptr_t         _store_queue_ptr_read ;
+  public    : Tcontrol_t         _store_queue_empty    ;
   public    : Tlsq_ptr_t         _load_queue_ptr_write;
   public    : Tcontrol_t         _has_immediat ;
@@ -117,4 +123,6 @@
       _type                  = x._type         ;
       _store_queue_ptr_write = x._store_queue_ptr_write;
+      _store_queue_ptr_read  = x._store_queue_ptr_read ;
+      _store_queue_empty     = x._store_queue_empty    ;
       _load_queue_ptr_write  = x._load_queue_ptr_write ;
       _has_immediat          = x._has_immediat ;
@@ -157,4 +165,6 @@
 		    << " * _type                  : " << x._type         << std::endl
 		    << " * _store_queue_ptr_write : " << toString(x._store_queue_ptr_write) << std::endl
+		    << " * _store_queue_ptr_read  : " << toString(x._store_queue_ptr_read ) << std::endl
+		    << " * _store_queue_empty     : " << toString(x._store_queue_empty    ) << std::endl
 		    << " * _load_queue_ptr_write  : " << toString(x._load_queue_ptr_write ) << std::endl
 		    << " * _has_immediat          : " << x._has_immediat << std::endl
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_allocation.cpp	(revision 122)
@@ -62,4 +62,6 @@
       ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type            );
       ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
+      ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
+      ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1);
       ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr);
       ALLOC0_SIGNAL_IN ( in_READ_QUEUE_IN_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                             );
@@ -92,4 +94,6 @@
       ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_TYPE                  ,"type"                 ,Ttype_t           ,_param->_size_type             );
       ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE ,"store_queue_ptr_write",Tlsq_ptr_t        , _param->_size_store_queue_ptr );
+      ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_STORE_QUEUE_PTR_READ  ,"store_queue_ptr_read" ,Tlsq_ptr_t        , _param->_size_store_queue_ptr );
+      ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_STORE_QUEUE_EMPTY     ,"store_queue_empty"    ,Tcontrol_t        ,1                              );
       ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE  ,"load_queue_ptr_write" ,Tlsq_ptr_t        , _param->_size_load_queue_ptr  );
       ALLOC0_SIGNAL_OUT(out_READ_QUEUE_OUT_HAS_IMMEDIAT          ,"has_immediat"         ,Tcontrol_t        ,1                              );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_deallocation.cpp	(revision 122)
@@ -38,4 +38,6 @@
         DELETE0_SIGNAL( in_READ_QUEUE_IN_TYPE                  ,_param->_size_type            );
         DELETE0_SIGNAL( in_READ_QUEUE_IN_STORE_QUEUE_PTR_WRITE ,_param->_size_store_queue_ptr );
+        DELETE0_SIGNAL( in_READ_QUEUE_IN_STORE_QUEUE_PTR_READ  ,_param->_size_store_queue_ptr );
+        DELETE0_SIGNAL( in_READ_QUEUE_IN_STORE_QUEUE_EMPTY     ,1                             );
         DELETE0_SIGNAL( in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE  ,_param->_size_load_queue_ptr  );
         DELETE0_SIGNAL( in_READ_QUEUE_IN_HAS_IMMEDIAT          ,1                             );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMoore.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMoore.cpp	(revision 122)
@@ -45,4 +45,6 @@
     PORT_WRITE (out_READ_QUEUE_OUT_TYPE        , _queue_head->_type        );
     PORT_WRITE (out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE, _queue_head->_store_queue_ptr_write);
+    PORT_WRITE (out_READ_QUEUE_OUT_STORE_QUEUE_PTR_READ , _queue_head->_store_queue_ptr_read );
+    PORT_WRITE (out_READ_QUEUE_OUT_STORE_QUEUE_EMPTY    , _queue_head->_store_queue_empty    );
     if (_param->_have_port_load_queue_ptr)
     PORT_WRITE (out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE , _queue_head->_load_queue_ptr_write );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp	(revision 122)
@@ -75,4 +75,6 @@
 	    entry->_type         = PORT_READ(in_READ_QUEUE_IN_TYPE        );
 	    entry->_store_queue_ptr_write = PORT_READ(in_READ_QUEUE_IN_STORE_QUEUE_PTR_WRITE);
+	    entry->_store_queue_ptr_read  = PORT_READ(in_READ_QUEUE_IN_STORE_QUEUE_PTR_READ );
+	    entry->_store_queue_empty     = PORT_READ(in_READ_QUEUE_IN_STORE_QUEUE_EMPTY    );
 	    if (_param->_have_port_load_queue_ptr)
 	    entry->_load_queue_ptr_write  = PORT_READ(in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE );
@@ -151,5 +153,5 @@
         if (_queue->size()>0)
           {
-            log_printf(TRACE,Read_queue,FUNCTION,"    * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.1d %.1d %.4d %.1d %.8x, %.1d %.1d %.4d %.1d %.8x, %.1d %.1d %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)",
+            log_printf(TRACE,Read_queue,FUNCTION,"    * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.1d %.1d %.4d %.1d %.8x, %.1d %.1d %.4d %.1d %.8x, %.1d %.1d %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)",
                        0,
 
@@ -163,4 +165,6 @@
 
                        _queue_head->_store_queue_ptr_write,
+                       _queue_head->_store_queue_ptr_read ,
+                       _queue_head->_store_queue_empty    ,
                        _queue_head->_load_queue_ptr_write ,
 
@@ -201,5 +205,5 @@
             for (;it!=_queue->end(); ++it)
               {
-                log_printf(TRACE,Read_queue,FUNCTION,"    * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.1d   %.4d           , %.1d   %.4d           , %.1d   %.4d     , %.1d %.4d, %.1d %.4d (%s)",
+                log_printf(TRACE,Read_queue,FUNCTION,"    * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.1d   %.4d           , %.1d   %.4d           , %.1d   %.4d     , %.1d %.4d, %.1d %.4d (%s)",
                            i,
                            
@@ -213,4 +217,6 @@
                            
                            (*it)->_store_queue_ptr_write,
+                           (*it)->_store_queue_ptr_read ,
+                           (*it)->_store_queue_empty    ,
                            (*it)->_load_queue_ptr_write ,
                            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h	(revision 122)
@@ -74,4 +74,6 @@
   public    : SC_IN (Ttype_t           )    *  in_INSERT_TYPE           ;
   public    : SC_IN (Tlsq_ptr_t        )    *  in_INSERT_STORE_QUEUE_PTR_WRITE;
+  public    : SC_IN (Tlsq_ptr_t        )    *  in_INSERT_STORE_QUEUE_PTR_READ ;
+  public    : SC_IN (Tcontrol_t        )    *  in_INSERT_STORE_QUEUE_EMPTY    ;
   public    : SC_IN (Tlsq_ptr_t        )    *  in_INSERT_LOAD_QUEUE_PTR_WRITE ;
   public    : SC_IN (Tcontrol_t        )    *  in_INSERT_HAS_IMMEDIAT   ;
@@ -104,4 +106,6 @@
   public    : SC_OUT(Ttype_t           )   ** out_RETIRE_TYPE           ;
   public    : SC_OUT(Tlsq_ptr_t        )   ** out_RETIRE_STORE_QUEUE_PTR_WRITE;
+  public    : SC_OUT(Tlsq_ptr_t        )   ** out_RETIRE_STORE_QUEUE_PTR_READ ;
+  public    : SC_OUT(Tcontrol_t        )   ** out_RETIRE_STORE_QUEUE_EMPTY    ;
   public    : SC_OUT(Tlsq_ptr_t        )   ** out_RETIRE_LOAD_QUEUE_PTR_WRITE ;
   public    : SC_OUT(Tcontrol_t        )   ** out_RETIRE_HAS_IMMEDIAT   ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Types.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Types.h	(revision 122)
@@ -29,4 +29,6 @@
   public    : Ttype_t            _type        ;
   public    : Tlsq_ptr_t         _store_queue_ptr_write;
+  public    : Tlsq_ptr_t         _store_queue_ptr_read ;
+  public    : Tcontrol_t         _store_queue_empty    ;
   public    : Tlsq_ptr_t         _load_queue_ptr_write ;
   public    : Tcontrol_t         _has_immediat;
@@ -59,4 +61,6 @@
 		    << " * _type                  : " << toString(x._type           ) << std::endl
 		    << " * _store_queue_ptr_write : " << toString(x._store_queue_ptr_write) << std::endl
+		    << " * _store_queue_ptr_read  : " << toString(x._store_queue_ptr_read ) << std::endl
+		    << " * _store_queue_empty     : " << toString(x._store_queue_empty    ) << std::endl
 		    << " * _load_queue_ptr_write  : " << toString(x._load_queue_ptr_write ) << std::endl
 		    << " * _has_immediat          : " << toString(x._has_immediat   ) << std::endl
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp	(revision 122)
@@ -64,4 +64,6 @@
        ALLOC0_SIGNAL_IN ( in_INSERT_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type            );
        ALLOC0_SIGNAL_IN ( in_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr );
+       ALLOC0_SIGNAL_IN ( in_INSERT_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr );
+       ALLOC0_SIGNAL_IN ( in_INSERT_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1                             );
        ALLOC0_SIGNAL_IN ( in_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr  );
        ALLOC0_SIGNAL_IN ( in_INSERT_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                             );
@@ -100,4 +102,6 @@
        ALLOC1_SIGNAL_OUT(out_RETIRE_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type);
        ALLOC1_SIGNAL_OUT(out_RETIRE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
+       ALLOC1_SIGNAL_OUT(out_RETIRE_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
+       ALLOC1_SIGNAL_OUT(out_RETIRE_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1);
        ALLOC1_SIGNAL_OUT(out_RETIRE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr );
        ALLOC1_SIGNAL_OUT(out_RETIRE_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_deallocation.cpp	(revision 122)
@@ -43,4 +43,6 @@
         DELETE0_SIGNAL( in_INSERT_TYPE                 ,_param->_size_type            );
         DELETE0_SIGNAL( in_INSERT_STORE_QUEUE_PTR_WRITE,_param->_size_store_queue_ptr );
+        DELETE0_SIGNAL( in_INSERT_STORE_QUEUE_PTR_READ ,_param->_size_store_queue_ptr );
+        DELETE0_SIGNAL( in_INSERT_STORE_QUEUE_EMPTY    ,1);
         DELETE0_SIGNAL( in_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_size_load_queue_ptr  );
         DELETE0_SIGNAL( in_INSERT_HAS_IMMEDIAT         ,1                             );
@@ -72,4 +74,6 @@
         DELETE1_SIGNAL(out_RETIRE_TYPE                 ,_param->_nb_inst_retire,_param->_size_type);
         DELETE1_SIGNAL(out_RETIRE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire,_param->_size_store_queue_ptr);
+        DELETE1_SIGNAL(out_RETIRE_STORE_QUEUE_PTR_READ ,_param->_nb_inst_retire,_param->_size_store_queue_ptr);
+        DELETE1_SIGNAL(out_RETIRE_STORE_QUEUE_EMPTY    ,_param->_nb_inst_retire,1);
         DELETE1_SIGNAL(out_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire,_param->_size_load_queue_ptr );
         DELETE1_SIGNAL(out_RETIRE_HAS_IMMEDIAT         ,_param->_nb_inst_retire,1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_genMoore.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_genMoore.cpp	(revision 122)
@@ -113,4 +113,6 @@
 	    PORT_WRITE(out_RETIRE_TYPE          [i],_queue[index_find]._type);
 	    PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [i],_queue[index_find]._store_queue_ptr_write);
+	    PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_READ  [i],_queue[index_find]._store_queue_ptr_read );
+	    PORT_WRITE(out_RETIRE_STORE_QUEUE_EMPTY     [i],_queue[index_find]._store_queue_empty    );
 	    if (_param->_have_port_load_queue_ptr)
 	    PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE  [i],_queue[index_find]._load_queue_ptr_write );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp	(revision 122)
@@ -26,5 +26,5 @@
       for (uint32_t it_dump=0;it_dump<_param->_size_queue; it_dump++)   \
         if (_queue_valid [it_dump])                                     \
-          log_printf(TRACE,Reservation_station,FUNCTION,"    * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \
+          log_printf(TRACE,Reservation_station,FUNCTION,"    * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \
                      it_dump,                                           \
                      _queue[it_dump]._context_id           ,            \
@@ -35,4 +35,6 @@
                      _queue[it_dump]._operation            ,            \
                      _queue[it_dump]._store_queue_ptr_write,            \
+                     _queue[it_dump]._store_queue_ptr_read ,            \
+                     _queue[it_dump]._store_queue_empty    ,            \
                      _queue[it_dump]._load_queue_ptr_write ,            \
                      _queue[it_dump]._has_immediat         ,            \
@@ -61,5 +63,5 @@
       for (uint32_t it_dump=0;it_dump<_param->_size_queue; it_dump++)   \
         if (it_dump < _queue_control->nb_elt())                         \
-          log_printf(TRACE,Reservation_station,FUNCTION,"    * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \
+          log_printf(TRACE,Reservation_station,FUNCTION,"    * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \
                      (*_queue_control)[it_dump],                        \
                      _queue[(*_queue_control)[it_dump]]._context_id           , \
@@ -70,4 +72,6 @@
                      _queue[(*_queue_control)[it_dump]]._operation            , \
                      _queue[(*_queue_control)[it_dump]]._store_queue_ptr_write, \
+                     _queue[(*_queue_control)[it_dump]]._store_queue_ptr_read , \
+                     _queue[(*_queue_control)[it_dump]]._store_queue_empty    , \
                      _queue[(*_queue_control)[it_dump]]._load_queue_ptr_write , \
                      _queue[(*_queue_control)[it_dump]]._has_immediat         , \
@@ -292,4 +296,6 @@
   	    _queue[index]._type            = PORT_READ(in_INSERT_TYPE           );
   	    _queue[index]._store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE);
+  	    _queue[index]._store_queue_ptr_read  = PORT_READ(in_INSERT_STORE_QUEUE_PTR_READ );
+  	    _queue[index]._store_queue_empty     = PORT_READ(in_INSERT_STORE_QUEUE_EMPTY    );
 	    if (_param->_have_port_load_queue_ptr)
   	    _queue[index]._load_queue_ptr_write  = PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/include/Read_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/include/Read_unit.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/include/Read_unit.h	(revision 122)
@@ -74,4 +74,6 @@
   public    : SC_IN (Ttype_t           )    *  in_READ_UNIT_IN_TYPE                 ;
   public    : SC_IN (Tlsq_ptr_t        )    *  in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE;
+  public    : SC_IN (Tlsq_ptr_t        )    *  in_READ_UNIT_IN_STORE_QUEUE_PTR_READ ;
+  public    : SC_IN (Tcontrol_t        )    *  in_READ_UNIT_IN_STORE_QUEUE_EMPTY    ;
   public    : SC_IN (Tlsq_ptr_t        )    *  in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ;
   public    : SC_IN (Tcontrol_t        )    *  in_READ_UNIT_IN_HAS_IMMEDIAT         ;
@@ -98,4 +100,6 @@
   public    : SC_OUT(Ttype_t           )   ** out_READ_UNIT_OUT_TYPE                 ;
   public    : SC_OUT(Tlsq_ptr_t        )   ** out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE;
+  public    : SC_OUT(Tlsq_ptr_t        )   ** out_READ_UNIT_OUT_STORE_QUEUE_PTR_READ ;
+  public    : SC_OUT(Tcontrol_t        )   ** out_READ_UNIT_OUT_STORE_QUEUE_EMPTY    ;
   public    : SC_OUT(Tlsq_ptr_t        )   ** out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ;
   public    : SC_OUT(Tcontrol_t        )   ** out_READ_UNIT_OUT_HAS_IMMEDIAT         ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp	(revision 122)
@@ -68,4 +68,6 @@
        ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type         );
        ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
+       ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
+       ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1);
        ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr);
        ALLOC0_SIGNAL_IN ( in_READ_UNIT_IN_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1);
@@ -98,4 +100,6 @@
        ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type            );
        ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
+       ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
+       ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1);
        ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr);
        ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                             );
@@ -268,4 +272,6 @@
 	 _component->port_map(name, "in_READ_QUEUE_IN_TYPE"                 ,dest, "in_READ_UNIT_IN_TYPE"                 );
 	 _component->port_map(name, "in_READ_QUEUE_IN_STORE_QUEUE_PTR_WRITE",dest, "in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE");
+	 _component->port_map(name, "in_READ_QUEUE_IN_STORE_QUEUE_PTR_READ" ,dest, "in_READ_UNIT_IN_STORE_QUEUE_PTR_READ" );
+	 _component->port_map(name, "in_READ_QUEUE_IN_STORE_QUEUE_EMPTY"    ,dest, "in_READ_UNIT_IN_STORE_QUEUE_EMPTY"    );
 	 if (_param->_have_port_load_queue_ptr)
 	 _component->port_map(name, "in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE" ,dest, "in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE" );
@@ -305,4 +311,6 @@
 	 _component->port_map(name,"out_READ_QUEUE_OUT_TYPE"                 ,dest, "in_INSERT_TYPE"                 );
 	 _component->port_map(name,"out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE",dest, "in_INSERT_STORE_QUEUE_PTR_WRITE");
+	 _component->port_map(name,"out_READ_QUEUE_OUT_STORE_QUEUE_PTR_READ" ,dest, "in_INSERT_STORE_QUEUE_PTR_READ" );
+	 _component->port_map(name,"out_READ_QUEUE_OUT_STORE_QUEUE_EMPTY"    ,dest, "in_INSERT_STORE_QUEUE_EMPTY"    );
 	 if (_param->_have_port_load_queue_ptr)
 	 _component->port_map(name,"out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE" ,dest, "in_INSERT_LOAD_QUEUE_PTR_WRITE" );
@@ -429,4 +437,6 @@
 	 _component->port_map(name, "in_INSERT_TYPE"                 ,dest,"out_READ_QUEUE_OUT_TYPE"                 );
 	 _component->port_map(name, "in_INSERT_STORE_QUEUE_PTR_WRITE",dest,"out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE");
+	 _component->port_map(name, "in_INSERT_STORE_QUEUE_PTR_READ" ,dest,"out_READ_QUEUE_OUT_STORE_QUEUE_PTR_READ" );
+	 _component->port_map(name, "in_INSERT_STORE_QUEUE_EMPTY"    ,dest,"out_READ_QUEUE_OUT_STORE_QUEUE_EMPTY"    );
 	 if (_param->_have_port_load_queue_ptr)
 	 _component->port_map(name, "in_INSERT_LOAD_QUEUE_PTR_WRITE" ,dest,"out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE" );
@@ -474,4 +484,6 @@
 	   _component->port_map(name,"out_RETIRE_"+toString(i)+"_TYPE"                 ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_TYPE"                 );
 	   _component->port_map(name,"out_RETIRE_"+toString(i)+"_STORE_QUEUE_PTR_WRITE",dest,"out_READ_UNIT_OUT_"+toString(i)+"_STORE_QUEUE_PTR_WRITE");
+	   _component->port_map(name,"out_RETIRE_"+toString(i)+"_STORE_QUEUE_PTR_READ" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_STORE_QUEUE_PTR_READ" );
+	   _component->port_map(name,"out_RETIRE_"+toString(i)+"_STORE_QUEUE_EMPTY"    ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_STORE_QUEUE_EMPTY"    );
 	   if (_param->_have_port_load_queue_ptr)
 	   _component->port_map(name,"out_RETIRE_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/include/Read_unit_to_Execution_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/include/Read_unit_to_Execution_unit.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/include/Read_unit_to_Execution_unit.h	(revision 122)
@@ -85,4 +85,6 @@
   public    : SC_IN (Ttype_t           )  ***  in_READ_UNIT_OUT_TYPE                   ;//[nb_read_unit][nb_read_unit_port]
   public    : SC_IN (Tlsq_ptr_t        )  ***  in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE  ;//[nb_read_unit][nb_read_unit_port]
+  public    : SC_IN (Tlsq_ptr_t        )  ***  in_READ_UNIT_OUT_STORE_QUEUE_PTR_READ   ;//[nb_read_unit][nb_read_unit_port]
+  public    : SC_IN (Tcontrol_t        )  ***  in_READ_UNIT_OUT_STORE_QUEUE_EMPTY      ;//[nb_read_unit][nb_read_unit_port]
   public    : SC_IN (Tlsq_ptr_t        )  ***  in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE   ;//[nb_read_unit][nb_read_unit_port]
   public    : SC_IN (Tcontrol_t        )  ***  in_READ_UNIT_OUT_HAS_IMMEDIAT           ;//[nb_read_unit][nb_read_unit_port]
@@ -106,4 +108,6 @@
   public    : SC_OUT(Ttype_t           )  *** out_EXECUTE_UNIT_IN_TYPE                 ;//[nb_execute_unit][nb_execute_unit_port]
   public    : SC_OUT(Tlsq_ptr_t        )  *** out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE;//[nb_execute_unit][nb_execute_unit_port]
+  public    : SC_OUT(Tlsq_ptr_t        )  *** out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_READ ;//[nb_execute_unit][nb_execute_unit_port]
+  public    : SC_OUT(Tcontrol_t        )  *** out_EXECUTE_UNIT_IN_STORE_QUEUE_EMPTY    ;//[nb_execute_unit][nb_execute_unit_port]
   public    : SC_OUT(Tlsq_ptr_t        )  *** out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE ;//[nb_execute_unit][nb_execute_unit_port]
   public    : SC_OUT(Tcontrol_t        )  *** out_EXECUTE_UNIT_IN_HAS_IMMEDIAT         ;//[nb_execute_unit][nb_execute_unit_port]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters.cpp	(revision 122)
@@ -59,4 +59,6 @@
     _num_thread_valid        = num_thread_valid    ;
 
+    _nb_thread               = get_nb_thread (nb_context, nb_front_end, nb_ooo_engine);
+
     log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION,"  * table_routing [nb_read_unit][nb_execute_unit][nb_execute_unit_port]");
     for (uint32_t i=0; i<_nb_read_unit; ++i)
@@ -81,5 +83,4 @@
     _max_nb_execute_unit_port= max<uint32_t>(_nb_execute_unit_port, _nb_execute_unit);
 
-    _nb_thread               = get_nb_thread (nb_context, nb_front_end, nb_ooo_engine);
     _nb_load_store_unit      = 0;
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_msg_error.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_msg_error.cpp	(revision 122)
@@ -66,5 +66,5 @@
       if (not is_type_valid(j))
 	for (uint32_t i=0; i<_nb_thread; i++)
-	  if (_num_thread_valid [j] and
+	  if (_num_thread_valid [i] and
               (type_present [i][j]))
 	    test.error(toString(_("The thread '%d' can execute the type's operation '%s' but this type is invalid.\n"),i,toString(j).c_str()));
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_allocation.cpp	(revision 122)
@@ -68,4 +68,6 @@
        _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_TYPE                 ,"TYPE"                 ,Ttype_t           ,_param->_size_type             ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]);
        _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,"STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t        ,_param->_size_store_queue_ptr  ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]);
+       _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_STORE_QUEUE_PTR_READ ,"STORE_QUEUE_PTR_READ" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr  ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]);
+       _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_STORE_QUEUE_EMPTY    ,"STORE_QUEUE_EMPTY"    ,Tcontrol_t        ,1                              ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]);
        _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,"LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr   ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]);
        _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_HAS_IMMEDIAT         ,"HAS_IMMEDIAT"         ,Tcontrol_t        ,1                              ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]);
@@ -99,4 +101,6 @@
        _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_NUM_REG_RE           ,"NUM_REG_RE"           ,Tspecial_address_t,_param->_size_special_register , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]);
        _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE,"STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t        ,_param->_size_store_queue_ptr  , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]);
+       _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_READ ,"STORE_QUEUE_PTR_READ" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr  , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]);
+       _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_STORE_QUEUE_EMPTY    ,"STORE_QUEUE_EMPTY"    ,Tcontrol_t        ,1                              , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]);
        _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,"LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr   , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]);
        _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_IMMEDIAT             ,"IMMEDIAT"             ,Tgeneral_data_t   ,_param->_size_general_data     , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp	(revision 122)
@@ -89,4 +89,6 @@
 		      PORT_WRITE(out_EXECUTE_UNIT_IN_NUM_REG_RE            [dest][port], PORT_READ(in_READ_UNIT_OUT_NUM_REG_RE            [i][j]));
 		      PORT_WRITE(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [dest][port], PORT_READ(in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE [i][j]));
+		      PORT_WRITE(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_READ  [dest][port], PORT_READ(in_READ_UNIT_OUT_STORE_QUEUE_PTR_READ  [i][j]));
+		      PORT_WRITE(out_EXECUTE_UNIT_IN_STORE_QUEUE_EMPTY     [dest][port], PORT_READ(in_READ_UNIT_OUT_STORE_QUEUE_EMPTY     [i][j]));
 		      if (_param->_have_port_load_queue_ptr)
 		      PORT_WRITE(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE  [dest][port], PORT_READ(in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE  [i][j]));
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h	(revision 122)
@@ -81,4 +81,6 @@
   public    : SC_IN (Ttype_t           )   **  in_EXECUTE_LOOP_IN_TYPE                 ;//[nb_read_unit]
   public    : SC_IN (Tlsq_ptr_t        )   **  in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE;//[nb_read_unit]
+  public    : SC_IN (Tlsq_ptr_t        )   **  in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_READ ;//[nb_read_unit]
+  public    : SC_IN (Tcontrol_t        )   **  in_EXECUTE_LOOP_IN_STORE_QUEUE_EMPTY    ;//[nb_read_unit]
   public    : SC_IN (Tlsq_ptr_t        )   **  in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE ;//[nb_read_unit]
   public    : SC_IN (Tcontrol_t        )   **  in_EXECUTE_LOOP_IN_HAS_IMMEDIAT         ;//[nb_read_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp	(revision 122)
@@ -66,4 +66,6 @@
        ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type);         
        ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
+       ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
+       ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1);
        ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr);
        ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1);
@@ -483,4 +485,6 @@
 	     PORT_MAP(_component ,src , "in_READ_UNIT_IN_TYPE"                 ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_TYPE"                 );
 	     PORT_MAP(_component ,src , "in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE",dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_STORE_QUEUE_PTR_WRITE");
+	     PORT_MAP(_component ,src , "in_READ_UNIT_IN_STORE_QUEUE_PTR_READ" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_STORE_QUEUE_PTR_READ" );
+	     PORT_MAP(_component ,src , "in_READ_UNIT_IN_STORE_QUEUE_EMPTY"    ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_STORE_QUEUE_EMPTY"    );
 	     if (_param->_have_port_load_queue_ptr)
 	     PORT_MAP(_component ,src , "in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" );
@@ -531,4 +535,8 @@
 	       COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j               )+"_STORE_QUEUE_PTR_WRITE",
 				         dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_STORE_QUEUE_PTR_WRITE");
+	       COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j               )+"_STORE_QUEUE_PTR_READ" ,
+				         dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_STORE_QUEUE_PTR_READ" );
+	       COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j               )+"_STORE_QUEUE_EMPTY"    ,
+				         dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_STORE_QUEUE_EMPTY"    );
 	       if (_param->_have_port_load_queue_ptr)
 	       COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j               )+"_LOAD_QUEUE_PTR_WRITE" ,
@@ -812,4 +820,8 @@
 	       COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE",
 				         dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_STORE_QUEUE_PTR_WRITE");
+	       COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_STORE_QUEUE_PTR_READ" ,
+				         dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_STORE_QUEUE_PTR_READ" );
+	       COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_STORE_QUEUE_EMPTY"    ,
+				         dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_STORE_QUEUE_EMPTY"    );
 	       if (_param->_have_port_load_queue_ptr)
 	       COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE" ,
@@ -936,4 +948,8 @@
 		 COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_STORE_QUEUE_PTR_WRITE",
 				           dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_STORE_QUEUE_PTR_WRITE");
+		 COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_STORE_QUEUE_PTR_READ",
+				           dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_STORE_QUEUE_PTR_READ" );
+		 COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_STORE_QUEUE_EMPTY"    ,
+				           dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_STORE_QUEUE_EMPTY"    );
 		 if (_param->_have_port_load_queue_ptr)
 		 COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_LOAD_QUEUE_PTR_WRITE" ,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_deallocation.cpp	(revision 122)
@@ -36,4 +36,6 @@
         DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_TYPE                 ,_param->_nb_read_unit,_param->_size_type);         
         DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_read_unit,_param->_size_store_queue_ptr);
+        DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_READ ,_param->_nb_read_unit,_param->_size_store_queue_ptr);
+        DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_STORE_QUEUE_EMPTY    ,_param->_nb_read_unit,1);
         DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_read_unit,_param->_size_load_queue_ptr);
         DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_HAS_IMMEDIAT         ,_param->_nb_read_unit,1);
@@ -99,13 +101,22 @@
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-    delete    _component;
     delete    _component_glue                        ;
+    for (uint32_t i=0; i<_param->_nb_read_unit; i++)
+    delete    _component_read_unit [i]               ;
     delete [] _component_read_unit                   ;
+    for (uint32_t i=0; i<_param->_nb_functionnal_unit; i++)
+    delete    _component_functionnal_unit [i]        ;
     delete [] _component_functionnal_unit            ;
+    for (uint32_t i=0; i<_param->_nb_load_store_unit; i++)
+    delete    _component_load_store_unit [i]         ;
     delete [] _component_load_store_unit             ;
+    for (uint32_t i=0; i<_param->_nb_write_unit; i++)
+    delete    _component_write_unit [i]              ;
     delete [] _component_write_unit                  ;
     delete    _component_read_unit_to_execution_unit ;
     delete    _component_execution_unit_to_write_unit;
     delete    _component_register_unit               ;
+
+    delete    _component;
     
     log_printf(FUNC,Execute_loop,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp	(revision 122)
@@ -590,5 +590,5 @@
     delete    _param_glue;
     for (uint32_t i=0; i<_nb_read_unit; i++)
-      delete _param_read_unit [i];
+    delete    _param_read_unit [i];
     delete [] _param_read_unit;
 
@@ -605,5 +605,5 @@
     delete [] _param_load_store_unit;
     for (uint32_t i=0; i<_nb_write_unit; i++)
-      delete _param_write_unit [i];
+    delete    _param_write_unit [i];
     delete [] _param_write_unit;
     delete    _param_read_unit_to_execution_unit;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 122)
@@ -16,4 +16,5 @@
 namespace context_state {
 
+#define MISS_FAST
 
 #define get_priority(x) \
@@ -53,6 +54,9 @@
 //             uint32_t x = _param->_link_context_to_decod_unit    [i];
 
-            Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
-//          Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
+            Tcounter_t inst_commit_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]);
+//          Tcounter_t inst_commit_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]);
+            Tcounter_t inst_decod_all  = PORT_READ(in_NB_INST_DECOD_ALL [i]);
+            Tcounter_t inst_all        = inst_commit_all + inst_decod_all;
+//          Tcounter_t inst_mem        = inst_commit_mem + inst_decod_all;
 
             context_state_t state = reg_STATE [i];
@@ -69,4 +73,5 @@
                   // Wait end of all instruction
                   if (inst_all == 0)
+//                if (inst_decod_all == 0)
                     state = CONTEXT_STATE_KO_EXCEP_ADDR;
                   break;
@@ -85,7 +90,14 @@
                 {
                   // Wait end of all instruction
-                  if (inst_all == 0)
+//                if (inst_all == 0)
+                  if (
+#ifdef  MISS_FAST
+                      inst_decod_all ==
+#else
+                      inst_all ==
+#endif
+                      0)
                     
-//                  state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
+//                  state = CONTEXT_STATE_OK;
                     state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
                   break;
@@ -94,5 +106,12 @@
                 {
                   // Wait end of all instruction
-                  if (inst_all == 0)
+//                if (inst_all == 0)
+                  if (
+#ifdef  MISS_FAST
+                      inst_decod_all ==
+#else
+                      inst_all ==
+#endif
+                      0)
                     state = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
 
@@ -127,6 +146,12 @@
                 {
                   // Wait end of all instruction
-                  if (inst_all == 0)
-                    
+//                if (inst_all == 0)
+                  if (
+#ifdef  MISS_FAST
+                      inst_decod_all ==
+#else
+                      inst_all ==
+#endif
+                      0)
 //                  state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
                     state = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Parameters.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Parameters.h	(revision 122)
@@ -36,6 +36,8 @@
   public : uint32_t   _nb_thread                          ;
   public : uint32_t * _translate_num_context_to_num_thread;//[nb_context]                    
-  public : const bool _accurate_block_predict    ;
-  public : const bool _accurate_block_decod      ;
+  public : const bool _always_accurate_predict   ;
+  public : const bool _always_accurate_decod     ;
+  public : const bool _can_accurate_predict      ;
+  public : const bool _can_accurate_decod        ;
 
 //public : uint32_t   _size_context_id           ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h	(revision 122)
@@ -25,16 +25,35 @@
     } event_source_t;
 
-  typedef enum
-    {
-      EVENT_STATE_OK                      , // Can predict
-      EVENT_STATE_MISS_FLUSH_UFPT         , // in decod  stage, detect a miss  , continue to execute but flush ufpt
-      EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT , // in commit stage, detect a miss  , stop context and flush ufpt and upt
-      EVENT_STATE_MISS_FLUSH_UPT          , // in commit stage, detect a miss  , context is stop and ufpt is flush, update RAS
-      EVENT_STATE_EVENT_FLUSH_UFPT        , // in commit stage, detect an event, continue to execute but flush ufpt
-      EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT, // in commit stage, detect an event, stop context and flush ufpt and upt
-      EVENT_STATE_EVENT_FLUSH_UPT         , // in commit stage, detect an event, context is stop and ufpt is flush, update RAS
-      EVENT_STATE_UPDATE_CONTEXT          , // prediction unit is update, send signal to context manager
-      EVENT_STATE_WAIT_END_EVENT            // prediction unit is ok, wait the end of event (send by Context State)
-    } event_state_t;
+//   typedef enum
+//     {
+//       EVENT_STATE_OK                      , // Can predict
+//       EVENT_STATE_MISS_FLUSH_UFPT         , // in decod  stage, detect a miss  , continue to execute but flush ufpt
+//       EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT , // in commit stage, detect a miss  , stop context and flush ufpt and upt
+//       EVENT_STATE_MISS_FLUSH_UPT          , // in commit stage, detect a miss  , context is stop and ufpt is flush, update RAS
+//       EVENT_STATE_EVENT_FLUSH_UFPT        , // in commit stage, detect an event, continue to execute but flush ufpt
+//       EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT, // in commit stage, detect an event, stop context and flush ufpt and upt
+//       EVENT_STATE_EVENT_FLUSH_UPT         , // in commit stage, detect an event, context is stop and ufpt is flush, update RAS
+//       EVENT_STATE_UPDATE_CONTEXT          , // prediction unit is update, send signal to context manager
+//       EVENT_STATE_WAIT_END_EVENT            // prediction unit is ok, wait the end of event (send by Context State)
+//     } event_state_t;
+
+  typedef enum
+    {
+      UFPT_EVENT_STATE_OK                     , // Can predict
+      UFPT_EVENT_STATE_KO_FLUSH                 // Can't predict, flush ufpt
+    } ufpt_event_state_t;
+
+  typedef enum
+    {
+      UPT_EVENT_STATE_OK                              , // Can predict
+      UPT_EVENT_STATE_KO_MISS_WAIT_UFPT               , // in decod  stage, detect a miss  , continue to execute but flush ufpt
+      UPT_EVENT_STATE_KO_MISS_FLUSH_UPT               , // in commit stage, detect a miss  , context is stop and ufpt is flush, update RAS
+      UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT              , // in commit stage, detect an event, continue to execute but flush ufpt
+      UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT              , // in commit stage, detect an event, context is stop and ufpt is flush, update RAS
+      UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT        , // prediction unit is update, send signal to context manager
+      UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT        , // prediction unit is ok, wait the end of event (send by Context State)
+      UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT        , // prediction unit is update, send signal to context manager
+      UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT          // prediction unit is ok, wait the end of event (send by Context State)
+    } upt_event_state_t;
 
   typedef enum
@@ -138,22 +157,20 @@
   };
 
-
-  
-  template<> inline std::string toString<morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::event_state_t>(const morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::event_state_t& x)
-  {
-    switch (x)
-      {
-      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_OK                      : return "ok"                      ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_MISS_FLUSH_UFPT         : return "miss_flush_ufpt"         ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : return "miss_flush_ufpt_and_upt" ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_MISS_FLUSH_UPT          : return "miss_flush_upt"          ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_EVENT_FLUSH_UPT         : return "event_flush_upt"         ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_EVENT_FLUSH_UFPT        : return "event_flush_ufpt"        ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: return "event_flush_ufpt_and_upt"; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_UPDATE_CONTEXT          : return "update_context"          ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_WAIT_END_EVENT          : return "wait_end_event"          ; break;
-      default    : return ""; break; 
-      }
-  };
+//   template<> inline std::string toString<morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::event_state_t>(const morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::event_state_t& x)
+//   {
+//     switch (x)
+//       {
+//       case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_OK                      : return "ok"                      ; break;
+//       case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_MISS_FLUSH_UFPT         : return "miss_flush_ufpt"         ; break;
+//       case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : return "miss_flush_ufpt_and_upt" ; break;
+//       case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_MISS_FLUSH_UPT          : return "miss_flush_upt"          ; break;
+//       case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_EVENT_FLUSH_UPT         : return "event_flush_upt"         ; break;
+//       case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_EVENT_FLUSH_UFPT        : return "event_flush_ufpt"        ; break;
+//       case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: return "event_flush_ufpt_and_upt"; break;
+//       case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_UPDATE_CONTEXT          : return "update_context"          ; break;
+//       case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_WAIT_END_EVENT          : return "wait_end_event"          ; break;
+//       default    : return ""; break; 
+//       }
+//   };
 
   template<> inline std::string toString<morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::ufpt_state_t>(const morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::ufpt_state_t& x)
@@ -186,4 +203,31 @@
   };
 
+  template<> inline std::string toString<morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::ufpt_event_state_t>(const morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::ufpt_event_state_t& x)
+  {
+    switch (x)
+      {
+      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UFPT_EVENT_STATE_OK       : return "UFPT_EVENT_STATE_OK"       ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UFPT_EVENT_STATE_KO_FLUSH : return "UFPT_EVENT_STATE_KO_FLUSH" ; break;
+      default    : return ""; break; 
+      }
+  };
+
+  template<> inline std::string toString<morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::upt_event_state_t>(const morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::upt_event_state_t& x)
+  {
+    switch (x)
+      {
+      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPT_EVENT_STATE_OK                        : return "UPT_EVENT_STATE_OK"                        ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPT_EVENT_STATE_KO_MISS_WAIT_UFPT         : return "UPT_EVENT_STATE_KO_MISS_WAIT_UFPT"         ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPT_EVENT_STATE_KO_MISS_FLUSH_UPT         : return "UPT_EVENT_STATE_KO_MISS_FLUSH_UPT"         ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT        : return "UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT"        ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT        : return "UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT"        ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT  : return "UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT"  ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT  : return "UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT"  ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT  : return "UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT"  ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT  : return "UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT"  ; break;
+      default    : return ""; break; 
+      }
+  };
+
 }; // end namespace morpheo              
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h	(revision 122)
@@ -184,10 +184,13 @@
   private   : bool                          * reg_IS_ACCURATE                    ; //[nb_context]
 
-  private   : bool                          * reg_EVENT_VAL                      ; //[nb_context]
+  private   : ufpt_event_state_t            * reg_UFPT_EVENT_STATE               ; //[nb_context]
+  private   : upt_event_state_t             * reg_UPT_EVENT_STATE                ; //[nb_context]
+
+//   private   : bool                          * reg_EVENT_VAL                      ; //[nb_context]
   private   : uint32_t                      * reg_EVENT_UPT_PTR                  ; //[nb_context]
   private   : bool                          * reg_EVENT_UPT_FULL                 ; //[nb_context]
 
-  private   : event_state_t                 * reg_EVENT_STATE                    ; //[nb_context]
-  private   : bool                          * reg_EVENT_IS_BRANCH                ; //[nb_context]
+//   private   : event_state_t                 * reg_EVENT_STATE                    ; //[nb_context]
+//   private   : bool                          * reg_EVENT_IS_BRANCH                ; //[nb_context]
   private   : Tdepth_t                      * reg_EVENT_DEPTH                    ; //[nb_context]
   private   : Taddress_t                    * reg_EVENT_ADDRESS_SRC              ; //[nb_context] // Address branch
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters.cpp	(revision 122)
@@ -34,6 +34,8 @@
                           uint32_t * translate_num_context_to_num_thread ,//[nb_context]
                           bool       is_toplevel):
-    _accurate_block_predict (false),
-    _accurate_block_decod   (false)
+    _always_accurate_predict (false),
+    _always_accurate_decod   (false),
+    _can_accurate_predict    (true ),
+    _can_accurate_decod      (true )
   {
     log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp	(revision 122)
@@ -224,10 +224,13 @@
     ALLOC1(reg_UPT_EMPTY                    ,bool         ,_param->_nb_context);
 
-    ALLOC1(reg_EVENT_VAL                    ,bool         ,_param->_nb_context);
+    ALLOC1(reg_UFPT_EVENT_STATE             ,ufpt_event_state_t,_param->_nb_context);
+    ALLOC1(reg_UPT_EVENT_STATE              ,upt_event_state_t ,_param->_nb_context);
+
+//     ALLOC1(reg_EVENT_VAL                    ,bool         ,_param->_nb_context);
     ALLOC1(reg_EVENT_UPT_PTR                ,uint32_t     ,_param->_nb_context);
     ALLOC1(reg_EVENT_UPT_FULL               ,bool         ,_param->_nb_context);
 
-    ALLOC1(reg_EVENT_STATE                  ,event_state_t ,_param->_nb_context);
-    ALLOC1(reg_EVENT_IS_BRANCH              ,bool          ,_param->_nb_context);
+//     ALLOC1(reg_EVENT_STATE                  ,event_state_t ,_param->_nb_context);
+//     ALLOC1(reg_EVENT_IS_BRANCH              ,bool          ,_param->_nb_context);
     ALLOC1(reg_EVENT_DEPTH                  ,Tdepth_t      ,_param->_nb_context);
     ALLOC1(reg_EVENT_ADDRESS_SRC            ,Taddress_t    ,_param->_nb_context);
@@ -257,5 +260,5 @@
                                                    false,
                                                    log_with_pid,
-                                                   false);
+                                                   true);
           
           branchement_log_file [i] .open(filename.c_str() ,std::ios::out | std::ios::trunc);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp	(revision 122)
@@ -151,10 +151,13 @@
         DELETE1(reg_UPT_EMPTY                    ,_param->_nb_context);
         
-        DELETE1(reg_EVENT_VAL                    ,_param->_nb_context);
+        DELETE1(reg_UFPT_EVENT_STATE             ,_param->_nb_context);
+        DELETE1(reg_UPT_EVENT_STATE              ,_param->_nb_context);
+
+//         DELETE1(reg_EVENT_VAL                    ,_param->_nb_context);
         DELETE1(reg_EVENT_UPT_PTR                ,_param->_nb_context);
         DELETE1(reg_EVENT_UPT_FULL               ,_param->_nb_context);
 
-        DELETE1(reg_EVENT_STATE                  ,_param->_nb_context);
-        DELETE1(reg_EVENT_IS_BRANCH              ,_param->_nb_context);
+//         DELETE1(reg_EVENT_STATE                  ,_param->_nb_context);
+//         DELETE1(reg_EVENT_IS_BRANCH              ,_param->_nb_context);
         DELETE1(reg_EVENT_DEPTH                  ,_param->_nb_context);
         DELETE1(reg_EVENT_ADDRESS_SRC            ,_param->_nb_context);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp	(revision 122)
@@ -33,13 +33,14 @@
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * BRANCH_COMPLETE [%d]",i);
 
-	Tcontext_t          context   = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
-	Tdepth_t            depth     = (_param->_have_port_depth     )?PORT_READ(in_BRANCH_COMPLETE_DEPTH      [i]):0;
-	Tcontrol_t          miss      = false;
-	Tcontrol_t          take      = reg_UPDATE_PREDICTION_TABLE [context][depth]._last_take   ;
-	Taddress_t          addr_dest = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest;
-	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition   ;
+        // Read information
+	Tcontext_t          context     = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
+	Tdepth_t            depth       = (_param->_have_port_depth     )?PORT_READ(in_BRANCH_COMPLETE_DEPTH      [i]):0;
+	Tcontrol_t          miss        = false; // init
+	Tcontrol_t          take        = reg_UPDATE_PREDICTION_TABLE [context][depth]._last_take   ;
+	Taddress_t          addr_dest   = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest;
+	Tbranch_condition_t condition   = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition   ;
 
         Tcontrol_t          no_sequence = PORT_READ(in_BRANCH_COMPLETE_NO_SEQUENCE [i]);
-        Taddress_t          addr_good = PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]);
+        Taddress_t          addr_good   = PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]);
 
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * context        : %d",context);
@@ -54,4 +55,5 @@
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * address_dest : %.8x",addr_dest);
 
+        // Test branch condition
 	switch (condition)
 	  {
@@ -80,6 +82,4 @@
               log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * BRANCH_CONDITION_FLAG");
 
-//               Tcontrol_t take_good = not flag; // flag set = not take
-//               Tcontrol_t take_good = flag; // flag set = take
               Tcontrol_t take_good = no_sequence;
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp	(revision 122)
@@ -28,37 +28,39 @@
     if (PORT_READ(in_NRESET) != 0)
       {
+    // for each decod instruction
     for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
       {
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * DECOD [%d]",i);
 
-        Tcontext_t    context     = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
-        bool          is_accurate = _param->_accurate_block_decod or reg_IS_ACCURATE [context];
-        event_state_t event_state = reg_EVENT_STATE [context];
-        uint32_t      ptr_write   = reg_UPT_TOP     [context];
-        // can continue if next slot is empty
-        Tcontrol_t    can_continue= ((reg_UPDATE_PREDICTION_TABLE [context][(reg_UPT_TOP [context]+1)%_param->_size_upt_queue[context]]._state == UPDATE_PREDICTION_STATE_EMPTY) and 
-                                     (reg_EVENT_STATE [context] == EVENT_STATE_OK));
+        // Read information
+        Tcontext_t         context          = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
+        bool               is_accurate      = (_param->_always_accurate_decod or 
+                                              (_param->_can_accurate_decod and reg_IS_ACCURATE [context]));
+        upt_event_state_t  upt_event_state  = reg_UPT_EVENT_STATE  [context];
+        ufpt_event_state_t ufpt_event_state = reg_UFPT_EVENT_STATE [context];
+        uint32_t           ptr_write        = reg_UPT_TOP     [context]; // One branch per context per cycle
+        uint32_t           ptr_write_next   = (ptr_write+1)%_param->_size_upt_queue[context];
+        // Decod can continue until the next branch if next slot is empty, and no event
+        Tcontrol_t         can_continue     = (reg_UPDATE_PREDICTION_TABLE [context][ptr_write_next]._state == UPDATE_PREDICTION_STATE_EMPTY);
 
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * context     : %d",context    );
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * is_accurate : %d",is_accurate);
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * event_state : %s",toString(event_state).c_str());
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * ptr_write   : %d",ptr_write  );
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * upt_state   : %s",toString(reg_UPDATE_PREDICTION_TABLE [context][ptr_write]._state).c_str());
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * can_continue: %d",can_continue);
+        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * context          : %d",context);
+        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * is_accurate      : %d",is_accurate);
+        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * ufpt_event_state : %s",toString(ufpt_event_state).c_str());
+        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * upt_event_state  : %s",toString(upt_event_state).c_str());
+        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * ptr_write        : %d - %d",ptr_write,ptr_write_next);
+        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * upt_state        : %s",toString(reg_UPDATE_PREDICTION_TABLE [context][ptr_write]._state).c_str());
+        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * can_continue     : %d",can_continue);
 
-        // ack :
+        // can decod (ack) if :
         //   * in all case (miss or hit), need empty slot
+        //   * not previous event (state = ok)
         //   * is_accurate
-        //   * event_state : don't update upt
         internal_DECOD_ACK           [i] = ((reg_UPDATE_PREDICTION_TABLE [context][ptr_write]._state == UPDATE_PREDICTION_STATE_EMPTY) and
-                                            is_accurate and
-//                                             (
-                                             (event_state == EVENT_STATE_OK)//  or
-//                                              (event_state == EVENT_STATE_MISS_FLUSH_UFPT    ) or
-//                                              (event_state == EVENT_STATE_UPDATE_CONTEXT))
-                                            );
+                                            (ufpt_event_state == UFPT_EVENT_STATE_OK) and
+                                            (upt_event_state  == UPT_EVENT_STATE_OK ) and
+                                            is_accurate);
         internal_DECOD_UPT_PTR_WRITE [i] = ptr_write;
 
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * ack         : %d",internal_DECOD_ACK [i]);
+        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * ack              : %d",internal_DECOD_ACK [i]);
 
 	PORT_WRITE(out_DECOD_ACK          [i], internal_DECOD_ACK [i]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_predict.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_predict.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_predict.cpp	(revision 122)
@@ -27,9 +27,10 @@
     if (PORT_READ(in_NRESET) != 0)
       {
-
+    // For each prediction
     for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
       {
+        // Read information
 	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
-	uint32_t   top     = reg_UFPT_TOP[context];
+	uint32_t   top     = reg_UFPT_TOP[context]; // not multi branch prediction
 
 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"PREDICT [%d] (genMealy)",i);
@@ -40,23 +41,23 @@
 // 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * need update : %d",reg_NB_ELT_NEED_UPDATE [context]);
 
+        bool is_accurate = (_param->_always_accurate_predict or 
+                            (_param->_can_accurate_predict and reg_IS_ACCURATE [context]));
+
+        // Ack if :
+        //  * no previous event (ufpt and upt is ok)
+        //  * top slot is empty
+        //  * is_accurate
+	internal_PREDICT_ACK [i] = ((reg_UFPT_EVENT_STATE [context] == UFPT_EVENT_STATE_OK) and
+                                    (reg_UPT_EVENT_STATE  [context] == UPT_EVENT_STATE_OK ) and
+                                    (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state == UPDATE_FETCH_PREDICTION_STATE_EMPTY) and
+                                    is_accurate);
+
         internal_PREDICT_UPDATE_PREDICTION_ID [i] = top;
 
+ 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * ACK         : %d",internal_PREDICT_ACK [i]);
+
+	PORT_WRITE(out_PREDICT_ACK                  [i], internal_PREDICT_ACK                  [i]);
         if (_param->_have_port_depth)
         PORT_WRITE(out_PREDICT_UPDATE_PREDICTION_ID [i], internal_PREDICT_UPDATE_PREDICTION_ID [i]);
-
-        bool is_accurate = _param->_accurate_block_predict or reg_IS_ACCURATE[context];
-
-        // Ack if :
-        //  * slot is empty
-        //  * no previous miss
-        //  * is_accurate
-	internal_PREDICT_ACK [i] = ((reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state == UPDATE_FETCH_PREDICTION_STATE_EMPTY) and
-   				    (reg_EVENT_STATE [context] == EVENT_STATE_OK) and
-//                                  (reg_UFPT_NB_UPDATE [context] == 0) and
-                                    is_accurate);
-
-
- 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * ACK         : %d",internal_PREDICT_ACK [i]);
-	PORT_WRITE(out_PREDICT_ACK [i], internal_PREDICT_ACK [i]);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp	(revision 122)
@@ -40,17 +40,20 @@
         //     include ]DEPTH_MIN:DEPTH_MAX] -> speculative
 
-        PORT_WRITE(out_DEPTH_VAL     [i],((reg_UPDATE_PREDICTION_TABLE [i][reg_UPT_TOP [i]]._state == UPDATE_PREDICTION_STATE_EMPTY) 
-                                          and (reg_EVENT_STATE [i] == EVENT_STATE_OK)
+        uint32_t bottom = reg_UPT_BOTTOM [i];
+        uint32_t top    = reg_UPT_TOP    [i];
+        bool     empty  = reg_UPT_EMPTY [i];
+
+        // Depth_val is set when state is ok and the UPT[top] is empty
+        PORT_WRITE(out_DEPTH_VAL     [i],((reg_UPDATE_PREDICTION_TABLE [i][top]._state == UPDATE_PREDICTION_STATE_EMPTY) 
+                                          and (reg_UFPT_EVENT_STATE [i] == UFPT_EVENT_STATE_OK)
+                                          and (reg_UPT_EVENT_STATE  [i] == UPT_EVENT_STATE_OK)
                                           ));
 	if (_param->_have_port_depth)
           {
-        PORT_WRITE(out_DEPTH_CURRENT [i], reg_UPT_TOP    [i]);
-        PORT_WRITE(out_DEPTH_MIN     [i], reg_UPT_BOTTOM [i]);
-	PORT_WRITE(out_DEPTH_MAX     [i], reg_UPT_TOP    [i]);
-          }
-	PORT_WRITE(out_DEPTH_FULL    [i], not reg_UPT_EMPTY [i] and (reg_UPT_TOP [i] == reg_UPT_BOTTOM [i]));
-
-//         bool empty = reg_UPT_EMPTY [i];
-// 	PORT_WRITE(out_DEPTH_MAX     [i], ((empty)?reg_UPT_BOTTOM [i]:((reg_UPT_TOP [i]==0)?(_param->_size_upt_queue[i]-1):(reg_UPT_TOP [i]-1))));
+        PORT_WRITE(out_DEPTH_CURRENT [i], top);
+        PORT_WRITE(out_DEPTH_MIN     [i], bottom);
+	PORT_WRITE(out_DEPTH_MAX     [i], top);
+          }
+	PORT_WRITE(out_DEPTH_FULL    [i], not empty and (top == bottom));
       }
 
@@ -58,65 +61,62 @@
     // =====[ UPDATE ]====================================================
     // ===================================================================
-
-    bool     retire_ras_from_ufpt [_param->_nb_context]; // event ufpt -> restore RAS, else update upt
-    bool     retire_ras_from_upt  [_param->_nb_context]; // event upt  -> restore RAS, else restore others structure
-//  bool     have_event           [_param->_nb_context];
-    bool     ufpt_update          [_param->_nb_context];
-    bool     upt_update           [_param->_nb_context];
-    Tdepth_t tab_ufpt_depth       [_param->_nb_context];
-    Tdepth_t tab_upt_depth        [_param->_nb_context];
-
-    for (uint32_t i=0; i<_param->_nb_context; i++)
-      {
-        event_state_t event_state = reg_EVENT_STATE [i];
-
-        retire_ras_from_ufpt [i] = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT         ) or
-                                    (event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
-                                    (event_state == EVENT_STATE_EVENT_FLUSH_UFPT        ) or
-                                    (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT));
-        retire_ras_from_upt  [i] = ((event_state == EVENT_STATE_MISS_FLUSH_UPT) or
-                                    (event_state == EVENT_STATE_EVENT_FLUSH_UPT));
-
-//         have_event           [i] = (event_state == EVENT_STATE_EVENT_FLUSH_UPT);
-
-        ufpt_update          [i] = true;
-        upt_update           [i] = true;
-        tab_ufpt_depth       [i] = reg_UFPT_UPDATE [i];
-        tab_upt_depth        [i] = reg_UPT_UPDATE  [i];
-      }
+    {
+      bool     flush_ufpt      [_param->_nb_context]; // event ufpt -> restore RAS, else update upt
+      bool     flush_upt       [_param->_nb_context]; // event upt  -> restore RAS, else restore others structure
+      bool     ufpt_can_update [_param->_nb_context];
+      bool     upt_can_update  [_param->_nb_context];
+      Tdepth_t tab_ufpt_depth  [_param->_nb_context];
+      Tdepth_t tab_upt_depth   [_param->_nb_context];
+      
+      // Init 
+      for (uint32_t i=0; i<_param->_nb_context; i++)
+        {
+          ufpt_event_state_t ufpt_event_state = reg_UFPT_EVENT_STATE [i];
+          upt_event_state_t  upt_event_state  = reg_UPT_EVENT_STATE [i];
+          
+          flush_ufpt      [i] = (ufpt_event_state == UFPT_EVENT_STATE_KO_FLUSH);
+          flush_upt       [i] = ((upt_event_state == UPT_EVENT_STATE_KO_MISS_FLUSH_UPT) or
+                                 (upt_event_state == UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT));
+          ufpt_can_update [i] = true;
+          upt_can_update  [i] = true;
+          tab_ufpt_depth  [i] = reg_UFPT_UPDATE [i];
+          tab_upt_depth   [i] = reg_UPT_UPDATE  [i];
+        }
 
     for (uint32_t i=0; i<_param->_nb_inst_update; i++)
       {
-	Tcontext_t          context     = (reg_UPDATE_PRIORITY+i)%_param->_nb_context;
+	Tcontext_t          context              = (reg_UPDATE_PRIORITY+i)%_param->_nb_context;
 
 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * UPDATE [%d] (genMoore)",i);
 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * context         : %d",context);
-	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * event_state     : %s",toString(reg_EVENT_STATE [context]).c_str());
+	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * flush_ufpt      : %d",flush_ufpt[context]);
+	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * flush_upt       : %d",flush_upt [context]);
 
         Tcontrol_t          val                  = false;
         Tcontrol_t          val_without_ack      = false;
-        Tcontrol_t          miss_prediction      ;
-        Tcontrol_t          direction_good       ;
-        Tcontrol_t          prediction_ifetch    ;
-        Tcontrol_t          btb_val              ;
-        Taddress_t          btb_address_src      ;
-        Taddress_t          btb_address_dest     ;
-        Tbranch_condition_t btb_condition        ;
-        Tcontrol_t          dir_val              ;
-        Thistory_t          dir_history          ;
-        Tcontrol_t          ras_val              ;
-        Tcontrol_t          ras_flush            ;
-        Tcontrol_t          ras_push             ;
-        Taddress_t          ras_address          ;
-        Tptr_t              ras_index            ;
+        Tcontrol_t          miss_prediction      = 0; // not necessary init
+        Tcontrol_t          direction_good       = 0; // not necessary init
+        Tcontrol_t          prediction_ifetch    = 0; // not necessary init
+        Tcontrol_t          btb_val              = 0; // not necessary init
+        Taddress_t          btb_address_src      = 0; // not necessary init
+        Taddress_t          btb_address_dest     = 0; // not necessary init
+        Tbranch_condition_t btb_condition        = 0; // not necessary init
+        Tcontrol_t          dir_val              = 0; // not necessary init
+        Thistory_t          dir_history          = 0; // not necessary init
+        Tcontrol_t          ras_val              = 0; // not necessary init
+        Tcontrol_t          ras_flush            = 0; // not necessary init
+        Tcontrol_t          ras_push             = 0; // not necessary init
+        Taddress_t          ras_address          = 0; // not necessary init
+        Tptr_t              ras_index            = 0; // not necessary init
 
         // Test if update fetch prediction table need update port
-        if (retire_ras_from_ufpt [context])
-          {
-            if (ufpt_update [context])
+        if (flush_ufpt [context])
+          {
+            if (ufpt_can_update [context])
               {
                 // Update Fetch Prediction Table
-                // An update of ufpt is to previous miss. Just restore Return Address Stack
-                
+                // An update of ufpt is to previous miss. Just restore Prediction_unit
+                
+                // Read information
                 Tdepth_t            depth     = tab_ufpt_depth[context];
                 ufpt_state_t        state     = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state; 
@@ -131,5 +131,5 @@
 //              val_without_ack       = not update_ras(condition);
 
-                miss_prediction       = 1;
+                miss_prediction       = 1; // need update, also previous miss
 //              direction_good        = ;
                 prediction_ifetch     = 1;
@@ -138,9 +138,8 @@
 //              btb_address_dest      = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest;
 //              btb_condition         = condition;
-                dir_val               = update_ras(condition);
+                dir_val               = update_dir(condition);
                 dir_history           = reg_UPDATE_PREDICTION_TABLE [context][depth]._history;
-                // repop/ repush data -> don't corrupt ras
-                ras_val               = update_ras(condition); 
-                ras_flush             = 0;
+                ras_val               = update_ras(condition); // repop/ repush data -> don't corrupt ras
+                ras_flush             = 0; // no ras corruption
                 ras_push              = push_ras(condition);
                 ras_address           = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._address_ras;
@@ -153,15 +152,17 @@
                 // Warning : don't update same entry
                 if (depth == reg_UFPT_BOTTOM[context])
-                  ufpt_update [context] = false;
-                
-                tab_ufpt_depth[context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1;
+                  ufpt_can_update [context] = false;
+                else
+                  // update pointer
+                  tab_ufpt_depth[context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1;
               }
           }
         else
           {
-            if (upt_update [context])
+            if (upt_can_update [context])
               {
                 // Update Prediction Table
-                
+
+                // Read information
                 Tdepth_t            depth     = tab_upt_depth[context];
                 upt_state_t         state     = reg_UPDATE_PREDICTION_TABLE [context][depth]._state; 
@@ -174,26 +175,20 @@
                 log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * condition       : %s",toString(condition).c_str());
               
-                Tcontrol_t          state_is_ok_ko           = ((state == UPDATE_PREDICTION_STATE_OK   ) or
-                                                                (state == UPDATE_PREDICTION_STATE_KO   ));
-//                 Tcontrol_t          state_is_event           = ((state == UPDATE_PREDICTION_STATE_KO   ) or
-//                                                                 (state == UPDATE_PREDICTION_STATE_EVENT)//  or
-//                                                                 ((have_event[context])?(state == UPDATE_PREDICTION_STATE_OK):false)
-//                                                                 );
-                
-//                 Tcontrol_t          state_is_event_update    = state_is_event and     need_update(condition);
-//                 Tcontrol_t          state_is_event_no_update = state_is_event and not need_update(condition);
-
-                if (retire_ras_from_upt [context])
+                // is the valid branch (valid branch hit, or valid branch miss)
+                Tcontrol_t          state_is_ok_ko = ((state == UPDATE_PREDICTION_STATE_OK   ) or
+                                                      (state == UPDATE_PREDICTION_STATE_KO   ));
+
+                if (not flush_upt [context])
                   {
-//                 val                   = state_is_event_update;
-//                 val_without_ack       = state_is_event_no_update;
-                val                   = ((state == UPDATE_PREDICTION_STATE_KO   ) or 
-                                         ((state == UPDATE_PREDICTION_STATE_EVENT) and need_update(condition)));
-                val_without_ack       = ((state == UPDATE_PREDICTION_STATE_EVENT) and not need_update(condition));
+                    // no event, just update predictor
+                val                   = (state == UPDATE_PREDICTION_STATE_OK);
+                val_without_ack       = false;
                   }
                 else
                   {
-                val                   = (state == UPDATE_PREDICTION_STATE_OK);
-                val_without_ack       = false;
+                    // event, restore event (if need update)
+                val                   = ( (state == UPDATE_PREDICTION_STATE_KO   ) or 
+                                         ((state == UPDATE_PREDICTION_STATE_EVENT) and     need_update(condition)));
+                val_without_ack       = ( (state == UPDATE_PREDICTION_STATE_EVENT) and not need_update(condition));
                   }                  
 
@@ -205,9 +200,8 @@
                 btb_address_dest      = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest;
                 btb_condition         = condition;
-                dir_val               = // state_is_ok_ko and 
-                                        update_dir(condition); // if not ifetch, then static prediction
+                dir_val               = ifetch and update_dir(condition); // if not ifetch, then static prediction -> history is wrong
                 dir_history           = reg_UPDATE_PREDICTION_TABLE [context][depth]._history     ;
                 ras_val               = update_ras(condition); // repop/ repush data -> don't corrupt ras
-                ras_flush             = (state == UPDATE_PREDICTION_STATE_KO); // miss prediction, RAS is corrupted
+                ras_flush             = (state == UPDATE_PREDICTION_STATE_KO); // miss prediction on RAS -> RAS is corrupted
                 ras_push              = push_ras(condition);
                 // If corrupt, RAS must be flushed.
@@ -218,20 +212,23 @@
                 internal_UPDATE_FROM_UFPT [i] = false;
                 internal_UPDATE_DEPTH     [i] = depth;
-                internal_UPDATE_RAS       [i] = retire_ras_from_upt [context];
+                internal_UPDATE_RAS       [i] = flush_upt [context];
 
                 // Warning : don't update same entry
-                if (retire_ras_from_upt [context])
+                if (flush_upt [context])
                   {
-                    // Restore RAS. 
+                    // Stop condition
                     if ((depth == reg_UPT_BOTTOM[context]) or not (val or val_without_ack))
-                      upt_update [context] = false;
+                      upt_can_update [context] = false;
                     
+                    // flush -> ptr is decrease 
                     tab_upt_depth[context] = (depth==0)?(_param->_size_upt_queue[context]-1):(depth-1);
                   }
                 else
                   {
+                    // Stop condition
                     if ((depth == reg_UPT_TOP [context]) or not (val or val_without_ack))
-                      upt_update [context] = false;
+                      upt_can_update [context] = false;
                     
+                    // flush -> ptr is increase 
                     tab_upt_depth[context] = (depth+1)%_param->_size_upt_queue[context];
                   }
@@ -273,12 +270,16 @@
           }
       }
-    
+    }
+   
     // ===================================================================
     // =====[ BRANCH_EVENT ]==============================================
     // ===================================================================
+
+    // For all context ...
     for (uint32_t i=0; i<_param->_nb_context; i++)
       {
-	Tcontrol_t val = (reg_EVENT_STATE [i] == EVENT_STATE_UPDATE_CONTEXT);
-
+        // ... send an event if upt must be update the context
+	Tcontrol_t val = ((reg_UPT_EVENT_STATE [i] == UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT) or
+                          (reg_UPT_EVENT_STATE [i] == UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT));
         PORT_WRITE(out_BRANCH_EVENT_VAL              [i],val);
         if (_param->_have_port_depth)
@@ -291,7 +292,9 @@
 	internal_BRANCH_EVENT_VAL [i] = val;
       }
+
       }
     else
       {
+        // Reset
         for (uint32_t i=0; i<_param->_nb_inst_update; i++)
           {
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp	(revision 122)
@@ -51,7 +51,10 @@
             reg_IS_ACCURATE          [i] = true;
             
-            reg_EVENT_VAL            [i] = false;
-            reg_EVENT_STATE          [i] = EVENT_STATE_OK;
-            reg_EVENT_IS_BRANCH      [i] = true;
+            reg_UFPT_EVENT_STATE     [i] = UFPT_EVENT_STATE_OK;
+            reg_UPT_EVENT_STATE      [i] = UPT_EVENT_STATE_OK;
+
+//             reg_EVENT_VAL            [i] = false;
+//             reg_EVENT_STATE          [i] = EVENT_STATE_OK;
+//             reg_EVENT_IS_BRANCH      [i] = true;
           }
       }
@@ -74,101 +77,76 @@
 	for (uint32_t i=0; i<_param->_nb_context; i++)
 	  {
+            // -----------------------------
             // UPDATE_FETCH_PREDICTION_TABLE
+            // -----------------------------
             {
               uint32_t bottom = reg_UFPT_BOTTOM [i];
-              
-              // Test if state is end
-              if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END)
+              bool     end    = (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END);
+
+              // Test if bottom slot can be remove
+              if (end)
                 {
                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UFPT [%d][%d]",i,bottom);
                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UFPT [%d][%d].state =  UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom);
-
+                  
                   // Free slot
                   reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
                   // Update pointer
-                  reg_UFPT_BOTTOM [i] = (bottom+1)%_param->_size_ufpt_queue[i];
+                  bottom = (bottom+1)%_param->_size_ufpt_queue[i];
+
+                  reg_UFPT_BOTTOM [i] = bottom;
                 }
             }
 
+            // -----------------------
             // UPDATE_PREDICTION_TABLE
+            // -----------------------
             {
-              uint32_t      bottom      = reg_UPT_BOTTOM [i];
-              bool          end         = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END);
-//               bool          end_ok      = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK);
-//               bool          end_ko      = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO);
-//               event_state_t event_state = reg_EVENT_STATE [i];
-
-              // Test if state is end
-//               if (end_ok or end_ko)
-              
-              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * state is STATE_END      : %d",end);
-              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_BOTTOM (before) : %d",reg_UPT_BOTTOM         [i]);
-
-              if (end)
+              uint32_t bottom = reg_UPT_BOTTOM [i];
+
+//               if (reg_UPT_EVENT_STATE [i] == UPT_EVENT_STATE_OK)
                 {
+                  bool     end    = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END);
+                  
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_BOTTOM (before) : %d",bottom);
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * state is STATE_END      : %d",end);
+                  
+                  if (end)
+                    {
 #if defined(DEBUG) and defined(DEBUG_Update_Prediction_Table) and (DEBUG_Update_Prediction_Table == true)
-                  if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._retire_ok)
-                    {
-                      uint32_t num_thread = _param->_translate_num_context_to_num_thread [i];
-                      branchement_log_file [num_thread] 
-                        << std::hex
-                        << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src       << " "
-                        << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest      << " "
-                        << std::dec
-                        <<         reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take         << " - "
-                        << "["  << simulation_cycle() << "] " << " "
-                        <<         reg_UPDATE_PREDICTION_TABLE [i][bottom]._miss_prediction   << " "
-                        <<         reg_UPDATE_PREDICTION_TABLE [i][bottom]._ifetch_prediction << " "
-                        << "("  << (uint32_t)reg_UPDATE_PREDICTION_TABLE [i][bottom]._condition         << ")"
-                        << std::endl;
+                      if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._retire_ok)
+                        {
+                          uint32_t num_thread = _param->_translate_num_context_to_num_thread [i];
+                          branchement_log_file [num_thread] 
+                            << std::hex
+                            << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src       << " "
+                            << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest      << " "
+                            << std::dec
+                            <<         reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take         << " - "
+                            << "["  << simulation_cycle() << "] " << " "
+                            <<         reg_UPDATE_PREDICTION_TABLE [i][bottom]._miss_prediction   << " "
+                            <<         reg_UPDATE_PREDICTION_TABLE [i][bottom]._ifetch_prediction << " "
+                            << "("  << (uint32_t)reg_UPDATE_PREDICTION_TABLE [i][bottom]._condition         << ")"
+                            << std::endl;
+                        }
+#endif
+                      
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT [%d][%d]",i,bottom);
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT [%d][%d]._state =  UPDATE_PREDICTION_STATE_EMPTY",i,bottom);
+                      // Free slot
+                      reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY;
+                      
+                      // Update pointer
+                      reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i];
+                      
+                      // Free a slot, test if bottom pointer overtake the top pointer
+                      if (reg_UPT_BOTTOM [i] == reg_UPT_TOP [i])
+                        reg_UPT_EMPTY [i] = true; // free a slot
+                      
+                      reg_EVENT_UPT_FULL [i] = false;
                     }
-#endif
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT [%d][%d]",i,bottom);
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT [%d][%d]._state =  UPDATE_PREDICTION_STATE_EMPTY",i,bottom);
-                  // Free slot
-                  reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY;
-
-                  // Update pointer
-                  reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i];
                   
-                  if (reg_UPT_BOTTOM [i] == reg_UPT_TOP [i])
-                    reg_UPT_EMPTY [i] = true; // free a slot
-
-//                   if (bottom = reg_UPT_UPDATE [i])
-//                     reg_UPT_UPDATE [i] = reg_UPT_BOTTOM [i];
-                }// @@@
-              
-              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_BOTTOM (after ) : %d",reg_UPT_BOTTOM         [i]);
-              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_EVENT_VAL           : %d",reg_EVENT_VAL     [i]);
-              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_EVENT_UPT_PTR       : %d",reg_EVENT_UPT_PTR [i]);
-              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_EVENT_UPT_FULL      : %d",reg_EVENT_UPT_FULL[i]);
-
-              if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom))
-                {
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * END EVENT");
-
-                  if ((reg_EVENT_IS_BRANCH [i] == false) and (reg_EVENT_UPT_FULL [i] == false))
-                    reg_EVENT_STATE[i] = EVENT_STATE_OK;
-
-                  if ((reg_EVENT_IS_BRANCH [i] == true) or (reg_EVENT_UPT_FULL [i] == false))
-                    {
-                  reg_EVENT_VAL       [i] = false;
-//                reg_EVENT_IS_BRANCH [i] = true;
-                  reg_UPT_TOP         [i] = reg_UPT_TOP_EVENT [i];
-                  reg_UPT_UPDATE      [i] = reg_UPT_TOP_EVENT [i];
-                  
-                  if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i])
-                    reg_UPT_EMPTY [i] = false;
-                    }
-
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_TOP             : %d",reg_UPT_TOP            [i]);
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_TOP_EVENT       : %d",reg_UPT_TOP_EVENT      [i]);
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_UPDATE          : %d",reg_UPT_UPDATE         [i]);
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_EMPTY           : %d",reg_UPT_EMPTY          [i]);
-                
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_BOTTOM (after ) : %d",reg_UPT_BOTTOM         [i]);
                 }
-              
-              if (end)
-                reg_EVENT_UPT_FULL [i] = false;
             }
 	  }
@@ -186,12 +164,20 @@
 
 	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
+          // Test if have a transaction
 	  if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i])
 	    {
-	      Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
-	      uint32_t   top     = internal_PREDICT_UPDATE_PREDICTION_ID [i];
+              // get transaction information
+	      Tcontext_t          context     = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
+	      uint32_t            top         = internal_PREDICT_UPDATE_PREDICTION_ID [i];
+              Tbranch_condition_t condition   = PORT_READ(in_PREDICT_BTB_CONDITION [i]);
+              bool                is_accurate = (_param->_always_accurate_predict or 
+                                                 (_param->_can_accurate_predict and PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i])));
+
 
 	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * PREDICT[%d] - Accepted",i);
-	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * context : %d",context);
-	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * top     : %d",top);
+	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * context     : %d",context);
+	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * top         : %d",top);
+	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * condition   : %d",condition);
+	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * is_accurate : %d",is_accurate);
 
 #ifdef DEBUG_TEST
@@ -200,9 +186,10 @@
 #endif
 
+              // Ifetch unit have fetch an instruction bundle with a branchement.
+              // Insert in UFPT
               log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top);
  	      reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state        = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD;
 
-              Tbranch_condition_t condition   = PORT_READ(in_PREDICT_BTB_CONDITION [i]);
-              bool                is_accurate = _param->_accurate_block_predict or PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]);
+              // Write information
 	      reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition    = condition;
 	      reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src  = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC  [i]);
@@ -214,11 +201,12 @@
 	      reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras    = PORT_READ(in_PREDICT_RAS_INDEX        [i]);
 
+              // Update pointer
               reg_UFPT_TOP     [context] = (top+1)%_param->_size_ufpt_queue [context];
-//            reg_UFPT_UPDATE  [context] = reg_UFPT_TOP [context];
+
+              // Test if this branchement need update
               if (need_update(condition))
                 {
                   reg_UFPT_NB_NEED_UPDATE [context] ++;
                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
-
                 }
 	    }
@@ -239,10 +227,13 @@
 
 	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+          // Test if have a decod transaction
 	  if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i])
 	    {
+              // Read information
 	      Tcontext_t          context       = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
 	      Tcontrol_t          miss_ifetch   = PORT_READ(in_DECOD_MISS_IFETCH [i]);
 	      Tcontrol_t          miss_decod    = PORT_READ(in_DECOD_MISS_DECOD  [i]);
               uint32_t            upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i];
+              uint32_t            top_next      = (upt_ptr_write+1)%_param->_size_upt_queue [context];
               Tbranch_condition_t condition  ;
               Tcontrol_t          is_accurate;
@@ -257,51 +248,106 @@
 	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * upt_ptr_write : %d",upt_ptr_write);
 
-              if (miss_ifetch or miss_decod)
+              // In decod step, two miss type :
+              // miss_ifetch = branch is previously predict (predict interface), but it's not the good
+              // miss_decod  = branch was not detected
+              if (not (miss_ifetch or miss_decod))
 		{
+		  // Normal case : branch is previous predicted, change state of branch
+
+                  // Read ufpt_ptr (send in predic step)
+                  uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0;
+
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * ufpt_ptr_read : %d",ufpt_ptr_read);
+
+#ifdef DEBUG_TEST
+                  if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
+                    throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state."));
+#endif
+                  // Change state
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read);
+                  reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END;
+
+                  // Push upt (from Pop ufpt)
+                  condition   = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition;
+                  is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate;
+
+                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition         = condition;
+                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src       = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ;
+                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest      = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest;
+                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take         = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take   ;
+//                reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
+                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate       = is_accurate;
+                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history           = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history     ;
+                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras       = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ;
+                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras         = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras   ;
+                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true ; // prediction from ifetch
+
+                  // Update pointer (now, this instruction is not in ufpt)
+                  if (need_update(condition))
+                    {
+                      reg_UFPT_NB_NEED_UPDATE [context] --;
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
+                    }
+		}
+              else
+                {
+                  // Have a miss !!!
                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * miss !!!");
 
-                  // Have a miss !!!
                   condition   = PORT_READ(in_DECOD_BTB_CONDITION [i]);
-                  is_accurate = _param->_accurate_block_decod or PORT_READ(in_DECOD_IS_ACCURATE   [i]);
-
-                  // if can_continue else don't wait the end of all instruction
-                  // can_continue = not miss_commit and the destination is accurate (know)
+                  is_accurate = (_param->_always_accurate_decod or 
+                                 (_param->_can_accurate_decod and PORT_READ(in_DECOD_IS_ACCURATE [i])));
+
+                  // if can_continue, don't wait the end of all instruction 
+                  // (can_continue = not miss_commit and the destination is accurate (know))
                   Tcontrol_t can_continue = is_accurate;
 
 #ifdef DEBUG_TEST
-                  if (reg_EVENT_STATE [context] != EVENT_STATE_OK)
-                    throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state."));
-#endif
-
-                  // miss_ifetch = branch is previously predict, but it's not the good
-                  //   * need flush ufpt
-                  // miss_decod  = branch was not detected
-                  //   * not necessary
+                  if (reg_UPT_EVENT_STATE [context] != UPT_EVENT_STATE_OK)
+                    throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt event state."));
+                  if (reg_UFPT_EVENT_STATE [context] != UFPT_EVENT_STATE_OK)
+                    throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt event state."));
+#endif
+
+                  // miss_ifetch -> need flush ufpt
+                  // miss_decod  -> not necessary
+                  // if can_continue (destination is know) and direction is not take (instruction in ifetch_queue can be valid)
+                  bool flush_ufpt = (not (can_continue and not direction and not miss_ifetch));
 
                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * can_continue: %d",can_continue);
                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * direction   : %d",direction   );
                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * miss_ifetch : %d",miss_ifetch );
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * change    : %d",(not (can_continue and not direction and not miss_ifetch)));
-
-                  // if can_continue (destination is know) and direction is not take, don't need flush fetch_unit.
-                  if (not (can_continue and not direction and not miss_ifetch))
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * flush_ufpt: %d",flush_ufpt  );
+
+                  // Test if can continue without flushing the ufpt (and ifetch_queue)
+                  if (flush_ufpt)
                     {
-                      if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
-                        {
-                          // Change state
-                          log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context);
-                          reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT;
-//                        reg_EVENT_SOURCE[context] = EVENT_SOURCE_UFPT;
-                        }
-                      else
-                        {
-                          log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT (decod - miss - flush ufpt)",context);
-                          reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT;
-                        }
-
-                      // Flush UPFT
+//                       // Optimisation : Test if ufpt have entry that need update prediction struction (as Return Address Stack)
+//                       if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
+//                         {
+//                           // Change state
+//                           log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context);
+//                           reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT;
+
+//                           // @@@
+// //                           // Have an actual event ?
+// //                           if (not reg_EVENT_VAL [context])
+// //                             reg_EVENT_UPT_PTR  [context] = upt_ptr_write;
+//                         }
+//                       else
+//                         {
+//                           log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- UPT_EVENT_STATE_KO_MISS_WAIT_UFPT (decod - miss - flush ufpt)",context);
+//                           // just wait ufpt, don't flush upt
+//                           reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_MISS_WAIT_UFPT;
+//                         }
+
+                      reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT;
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT_EVENT_STATE [%d] <- %s (decod, miss)",context,toString(reg_UPT_EVENT_STATE [context]).c_str());
+
+                      // Need Flush UPFT
                       flush_UFPT [context] = true;
 
-                      reg_EVENT_IS_BRANCH       [context] = true;
+                      // Write information
+//                       reg_EVENT_IS_BRANCH       [context] = true;
                       reg_EVENT_DEPTH           [context] = upt_ptr_write;
                       reg_EVENT_ADDRESS_SRC     [context] = address_src; // delay_slot is compute in Context_State
@@ -310,5 +356,6 @@
                       reg_EVENT_CAN_CONTINUE    [context] = can_continue;
                     }
-                  
+                  // else can continue
+
                   // Push upt (from decod interface)
                   reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition         = condition;
@@ -323,43 +370,6 @@
                   reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction
 		}
-	      else
-		{
-		  // Normal case : branch is previous predicated, change state of branch
-                  uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0;
-
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * ufpt_ptr_read : %d",ufpt_ptr_read);
-
-#ifdef DEBUG_TEST
-                  if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
-                    throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state."));
-#endif
-                  // Change state
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read);
-                  reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END;
-
-                  // Push upt (from Pop ufpt)
-                  condition   = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition;
-                  is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate;
-
-                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition         = condition;
-                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src       = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ;
-                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest      = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest;
-                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take         = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take   ;
-//                reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
-                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate       = is_accurate;
-                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history           = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history     ;
-                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras       = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ;
-                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras         = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras   ;
-                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true ; // prediction from ifetch
-
-                  // Update pointer
-                  if (need_update(condition))
-                    {
-                      reg_UFPT_NB_NEED_UPDATE [context] --;
-                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
-                    }
-		}
-
-              // All case !!!
+
+              // In all case !!!
 #ifdef DEBUG_TEST
               if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY)
@@ -369,5 +379,5 @@
               // Change state
               log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write);
-              reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END;
+              reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state       = UPDATE_PREDICTION_STATE_WAIT_END;
               reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._retire_ok   = false;
               reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._miss_commit = false;
@@ -384,10 +394,6 @@
               
               // Update pointer
-              reg_UPT_TOP     [context] = (upt_ptr_write+1)%_param->_size_upt_queue [context];
-              reg_UPT_EMPTY   [context] = false;
-//            reg_UPT_UPDATE  [context] = reg_UPT_TOP [context];
-
-//               if (miss_ifetch or miss_decod)
-//                 reg_UPT_TOP_EVENT [context] = reg_UPT_TOP [context];
+              reg_UPT_TOP     [context] = top_next;
+              reg_UPT_EMPTY   [context] = false; // new instruction
 	    }
 
@@ -400,8 +406,11 @@
             can_continue [i] = true;
 
+          // For each updated instruction
           for (uint32_t i=0; i<_param->_nb_inst_update; i++)
             {
 	      Tcontext_t context   = internal_UPDATE_CONTEXT_ID [i];
 
+              // Test if transaction
+              // (an val_with_out is an update and don't need update prediction structure
               if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or
                   (internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context]))
@@ -413,26 +422,30 @@
                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * depth   : %d",depth);
                   
+                  upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [context];
+
+                  // One interface to two source : 
+                  //   * from ufpt -> newest prediction
+                  //   * from upt  -> oldest prediction
                   if (internal_UPDATE_FROM_UFPT [i])
                     {
                       // if free a slot, also all queue is updated
                       // Last slot ?
-//                       if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context])
                       if ((--reg_UFPT_NB_UPDATE [context])==0)
                         {
-                          switch (reg_EVENT_STATE [context])
-                            {
-                            case EVENT_STATE_MISS_FLUSH_UFPT         : 
-                              {
-                                reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 
-//                                 reg_EVENT_SOURCE[context] = EVENT_SOURCE_UFPT;
-
-                                break;
-                              }
-                              // impossible to have an update on ufpt and reg_upt_update>reg_upt_top
-                            case EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT ; break;
-                            case EVENT_STATE_EVENT_FLUSH_UFPT        : reg_EVENT_STATE [context] = EVENT_STATE_OK             ; break;
-                            case EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: reg_EVENT_STATE [context] = EVENT_STATE_EVENT_FLUSH_UPT; break;
-                            default : break;
-                            }
+                          log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UFPT_EVENT [%d] <- UFPT_EVENT_STATE_OK (update - end flush ufpt)",context);
+                          reg_UFPT_EVENT_STATE    [context] = UFPT_EVENT_STATE_OK;
+                          reg_UFPT_NB_NEED_UPDATE [context] = 0;
+
+//                           // Test upt event to change state
+//                           // test if upt wait ufpt
+//                           switch (upt_event_state)
+//                             {
+//                               // this case when don't need flush upt (miss decod and can continue)
+//                             case UPT_EVENT_STATE_KO_MISS_WAIT_UFPT  : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
+//                             case UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_OK               ; break;
+//                             default : break;
+//                             }
+
+//                           reg_UPT_EVENT_STATE [context] = upt_event_state;
                         }
                       
@@ -453,10 +466,4 @@
                       reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1;
                       log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]);
-                      // Free a register that need update ?
-                      if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition))
-                        {
-                          reg_UFPT_NB_NEED_UPDATE [context] --;
-                          log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
-                        }
                     }
                   else
@@ -464,5 +471,5 @@
                       log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * Update Prediction Table");
                       log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_UPDATE (before) : %d",reg_UPT_UPDATE [context]);
-                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_EVENT_STATE         : %s",toString(reg_EVENT_STATE [context]).c_str());
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_EVENT_STATE     : %s",toString(upt_event_state).c_str());
  
                       // Change state
@@ -481,12 +488,11 @@
 #endif
 
-//                    bool have_event = ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) or
-//                                       (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_EVENT));
 #ifdef STATISTICS
                       Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
 #endif
-                      bool ok     = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK);
-                      bool ko     = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO);
-
+                      bool ok = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK);
+                      bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO);
+
+                      // Test if branch is valid (prediction can be incorrect)
                       if (ok or ko)
                         {
@@ -508,18 +514,11 @@
                       if (ko)
                         {
-                          // Ko : wait end of all instruction
-//                           log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO_WAIT_END (update)",context,depth);
-                          
-//                           reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO_WAIT_END;
-
+                          // Ko
                           log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",context,depth);
                           
+                          // Wait update of context_state
                           reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
 
-                          reg_EVENT_VAL      [context] = true;
                           reg_EVENT_UPT_PTR  [context] = depth;
-//                        reg_EVENT_UPT_FULL [context] = 0;
-//                        reg_EVENT_UPT_FULL        [i] = (not reg_UPT_EMPTY [i] and (bottom == reg_UPT_TOP [i]));
-
 
 #ifdef STATISTICS
@@ -530,6 +529,5 @@
                       else
                         {
-//                           log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_END_OK (update)",context,depth);
-//                           reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK;
+                          // ok or event
 
                           log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth);
@@ -564,16 +562,24 @@
 //                            reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context];
 
-                              if (reg_EVENT_STATE [context] == EVENT_STATE_EVENT_FLUSH_UPT)
+                              switch (upt_event_state)
                                 {
-                                  reg_EVENT_STATE [context] = EVENT_STATE_OK;
+                                  // this case when don't need flush upt (miss decod and can continue)
+                                case UPT_EVENT_STATE_KO_MISS_FLUSH_UPT  : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
+                                case UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT : 
+                                  {
+                                    upt_event_state = UPT_EVENT_STATE_OK;
+                                    reg_UPT_TOP    [context] = reg_UPT_TOP_EVENT [context];
+                                    reg_UPT_UPDATE [context] = reg_UPT_TOP_EVENT [context];
+
+                                    break;
+                                  }
+                                default : break;
                                 }
-                              else
-                                {
-                                  reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT;
-//                                   reg_EVENT_SOURCE[context] = EVENT_SOURCE_UPT;
-                                }
+                              
+                              reg_UPT_EVENT_STATE [context] = upt_event_state;
                             }
                           else
                             {
+                              // else, decrease update pointer
                               reg_UPT_UPDATE [context] = (((depth==0)?_param->_size_upt_queue[context]:depth)-1);
                             }
@@ -587,10 +593,10 @@
                         }
                       
-                      // Free the branch with no accurate ?
+                      // Test if freeing the branch with no accurate ?
                       if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko)
                         reg_IS_ACCURATE [context] = true;
 
                       log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_UPDATE (after ) : %d",reg_UPT_UPDATE[context]);
-                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_EVENT_STATE         : %s",toString(reg_EVENT_STATE [context]).c_str());
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_EVENT_STATE     : %s",toString(reg_UPT_EVENT_STATE [context]).c_str());
                     }
                 }
@@ -611,153 +617,167 @@
         //     * update status
         //   * Miss prediction :
-	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
-	  if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])
-	    {
-	      Tcontext_t context   = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
-	      Tdepth_t   depth     = (_param->_have_port_depth     )?PORT_READ(in_BRANCH_COMPLETE_DEPTH      [i]):0;
-              Tcontrol_t miss      = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];
-              Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE            [i];
-              Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST    [i];
-
-	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * BRANCH_COMPLETE[%d] - Accepted",i);
-	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * context             : %d",context);
-	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * depth               : %d",depth);
-	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * miss                : %d",miss);
-              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_STATE     : %s",toString(reg_EVENT_STATE [context]).c_str());
-	      
-              if (miss)
-		{
-                  // Flush UPT
-                  uint32_t      top                 = reg_UPT_TOP [context];
-                  uint32_t      new_update          = ((top==0)?_param->_size_upt_queue[context]:top)-1; 
-                                                   
-                  Taddress_t    address_src         = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
-                  event_state_t event_state         = reg_EVENT_STATE [context];
-                  upt_state_t   event_top           = reg_UPDATE_PREDICTION_TABLE [context][top]._state;
-
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * event_top           : %s",toString(event_top).c_str());
-
-                  bool          previous_ufpt_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
-                                                       (event_state == EVENT_STATE_MISS_FLUSH_UFPT         ) or
-                                                       (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
-                                                       (event_state == EVENT_STATE_EVENT_FLUSH_UFPT        ));
-
-                  bool          previous_upt_event  = (false
-                                                       or  (event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT )
-                                                       or  (event_state == EVENT_STATE_MISS_FLUSH_UPT          )
-                                                       or  (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT)
-                                                       or  (event_state == EVENT_STATE_EVENT_FLUSH_UPT         )
-                                                       or  (event_top   == UPDATE_PREDICTION_STATE_END_KO      )
-                                                       or  (event_top   == UPDATE_PREDICTION_STATE_KO          )
-//                                                     or  (event_state == EVENT_STATE_WAIT_END_EVENT          )
-//                                                        or ((event_state == EVENT_STATE_UPDATE_CONTEXT          )
-//                                                            and (reg_EVENT_SOURCE [context] == EVENT_SOURCE_UPT))
-                                                       );
-//                bool          update_ras     = (new_update != depth);
-
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * top                 : %d",top);
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * new_update          : %d",new_update);
-//                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * update_ras          : %d",update_ras);
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * previous_upt_event  : %d",previous_upt_event);
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * previous_ufpt_event : %d",previous_ufpt_event);
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UPT_UPDATE      : %d",reg_UPT_UPDATE [context]);
-                          
-                  // Have a miss !!!
-                  // Flush UPFT
-                  flush_UFPT [context] |= not previous_ufpt_event;
-                  
-                  if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
-                    {
-                      for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];
-                           j!=top; 
-                           j=(j+1)%_param->_size_upt_queue[context])
-                        {
-                          reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;
-                          reg_UPDATE_PREDICTION_TABLE [context][j]._retire_ok = false;
-                        }
-                      
-                  
-//                    reg_UPT_BOTTOM    [context];
-                      reg_UPT_TOP       [context] = depth;
-//                    reg_UPT_TOP_EVENT [context] = top;
-                      
-                      if (not previous_upt_event)
-                        {
-                          reg_UPT_TOP_EVENT [context] = top;
-                          reg_UPT_UPDATE    [context] = new_update;
-                        }
-                      else
-                        {
-                          // Have event. Top index this slot
-                          reg_UPDATE_PREDICTION_TABLE [context][top]._retire_ok = false;
-
-                          switch (event_top)
-                            {
-                            case UPDATE_PREDICTION_STATE_END_KO : 
+        {
+          bool branch_complete_miss [_param->_nb_context];
+          for (uint32_t i=0; i<_param->_nb_context; ++i)
+            branch_complete_miss [i] = false;
+
+          for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
+            if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])
+              {
+                // Read information
+                Tcontext_t context   = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
+                Tdepth_t   depth     = (_param->_have_port_depth     )?PORT_READ(in_BRANCH_COMPLETE_DEPTH      [i]):0;
+                Tcontrol_t miss      = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];
+                Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE            [i];
+                Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST    [i];
+                
+                upt_event_state_t upt_event_state  = reg_UPT_EVENT_STATE [context];
+                
+                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * BRANCH_COMPLETE[%d] - Accepted",i);
+                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * context             : %d",context);
+                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * depth               : %d",depth);
+                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * miss                : %d",miss);
+                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UPT_EVENT_STATE : %s",toString(upt_event_state).c_str());
+                
+                // Test if the completed branch is a speculation miss
+                if (miss)
+                  {
+                    // special case : two branch complete on the same context.
+                    // when the re order keep the order, the branch complete j is most speculative that the branch comple i if i < j
+                    if (not branch_complete_miss [context])
+                      {
+                        branch_complete_miss [context] = true;
+                        // Flush UPT
+                        // get information
+                        uint32_t          top                 = reg_UPT_TOP [context];
+                        uint32_t          new_update          = ((top==0)?_param->_size_upt_queue[context]:top)-1; 
+                        
+                        Taddress_t        address_src         = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
+                        upt_state_t       event_top           = reg_UPDATE_PREDICTION_TABLE [context][top]._state;
+                        
+                        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * upt_event_state     : %s",toString(upt_event_state).c_str());
+                        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * event_top           : %s",toString(event_top).c_str());
+                        
+                        bool              previous_ufpt_event = (reg_UFPT_EVENT_STATE [i] == UFPT_EVENT_STATE_KO_FLUSH);
+                        
+                        
+                        bool              previous_upt_event  = (false
+                                                                 or (upt_event_state == UPT_EVENT_STATE_KO_MISS_WAIT_UFPT )
+                                                                 or (upt_event_state == UPT_EVENT_STATE_KO_MISS_FLUSH_UPT )
+                                                                 or (upt_event_state == UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT)
+                                                                 or (upt_event_state == UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT)
+                                                                 or (event_top       == UPDATE_PREDICTION_STATE_END_KO    )
+                                                                 or (event_top       == UPDATE_PREDICTION_STATE_KO        )
+                                                                 );
+                        
+                        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * top                 : %d",top);
+                        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * new_update          : %d",new_update);
+                        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * previous_upt_event  : %d",previous_upt_event);
+                        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * previous_ufpt_event : %d",previous_ufpt_event);
+                        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UPT_UPDATE      : %d",reg_UPT_UPDATE [context]);
+                        
+                        // Have a miss !!!
+                        // Flush UPFT
+                        flush_UFPT [context] |= not previous_ufpt_event;
+                        
+                        // Test if the entry wait the branchment (else, they have a previous event)
+                        if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
+                          {
+                            // All instruction between the instruction and the top is disable
+                            for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];
+                                 j!=top; 
+                                 j=(j+1)%_param->_size_upt_queue[context])
                               {
-                                // Have already update predictor
-                                reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_END;
-                                reg_UPT_UPDATE              [context] = new_update;
-                                break;
+                                reg_UPDATE_PREDICTION_TABLE [context][j]._state     = UPDATE_PREDICTION_STATE_EVENT;
+                                reg_UPDATE_PREDICTION_TABLE [context][j]._retire_ok = false; // event
                               }
-                            case UPDATE_PREDICTION_STATE_KO :
+                            
+                            // New top
+                            reg_UPT_TOP       [context] = depth;
+                            
+                            if (not previous_upt_event)
                               {
-                                // Doesn't have update predictor
-                                reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
-                                break;
+                                reg_UPT_TOP_EVENT [context] = top;
+                                reg_UPT_UPDATE    [context] = new_update;
                               }
-                            default :
+                            else
                               {
-//                                 reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
+                                // Have event. Top index this slot
+                                reg_UPDATE_PREDICTION_TABLE [context][top]._retire_ok = false;
+                                
+                                switch (event_top)
+                                  {
+                                  case UPDATE_PREDICTION_STATE_END_KO : 
+                                    {
+                                      // Have already update predictor
+                                      reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_END;
+                                      reg_UPT_UPDATE              [context] = new_update;
+                                      break;
+                                    }
+                                  case UPDATE_PREDICTION_STATE_KO :
+                                    {
+                                      // Doesn't have update predictor
+                                      reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
+                                      break;
+                                    }
+                                  default :
+                                    {
+                                      //                                 reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
 //                                 break;
-
+                                      
 #ifdef DEBUG_TEST
-                                throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
-#endif
+                                      throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
+#endif
+                                    }
+                                  }
                               }
-                            }
-                        }
-                      
-                      if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context])
-                        reg_UPT_EMPTY [context] = true;
-                      
-                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);
-                      reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;
-
-                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_NB_NEED_UPDATE [%d] : %d",context,reg_UFPT_NB_NEED_UPDATE [context]);
-                     
-                      if ( (reg_UFPT_NB_NEED_UPDATE [context] > 0) or
-                           (reg_UFPT_NB_UPDATE      [context] > 0))
-                        {
-                          log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);
-                          reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT;
-                        }
-                      else
-                        {
-//                        if (not previous_update_ras)
-                          {
-                            // have ras prediction ?
-                            log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context);
                             
-                            reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT;
+                            if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context])
+                              reg_UPT_EMPTY [context] = true;
+                            
+                            log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);
+                            reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;
+                            
+                            log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_NB_NEED_UPDATE [%d] : %d",context,reg_UFPT_NB_NEED_UPDATE [context]);
+                            
+//                       if ( (reg_UFPT_NB_NEED_UPDATE [context] > 0) or
+//                            (reg_UFPT_NB_UPDATE      [context] > 0))
+//                         {
+//                           log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);
+//                           reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT;
+//                         }
+//                       else
+//                         {
+// //                        if (not previous_update_ras)
+//                           {
+//                             // have ras prediction ?
+//                             log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context);
+                            
+//                             reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT;
+                            
+//                           }
+//                         }
+
+                            reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_MISS_FLUSH_UPT;
+                            log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT_EVENT_STATE [%d] <- %s (branch_complete, ifetch hit)",context,toString(reg_UPT_EVENT_STATE [context]).c_str());
+                            
+                            //                       reg_EVENT_SOURCE          [context] = EVENT_SOURCE_UPT;
+                            
+                            // else no update
+                            
+                            //                       reg_EVENT_IS_BRANCH       [context] = true;
+                            reg_EVENT_DEPTH           [context] = depth;
+                            reg_EVENT_ADDRESS_SRC     [context] = address_src; // delay_slot is compute in Context_State
+                            reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
+                            reg_EVENT_ADDRESS_DEST    [context] = good_addr;
+                            reg_EVENT_CAN_CONTINUE    [context] = false;
                             
                           }
-                        }
-//                       reg_EVENT_SOURCE          [context] = EVENT_SOURCE_UPT;
-                      
-                      // else no update
-                      
-                      reg_EVENT_IS_BRANCH       [context] = true;
-                      reg_EVENT_DEPTH           [context] = depth;
-                      reg_EVENT_ADDRESS_SRC     [context] = address_src; // delay_slot is compute in Context_State
-                      reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
-                      reg_EVENT_ADDRESS_DEST    [context] = good_addr;
-                      reg_EVENT_CAN_CONTINUE    [context] = false;
-
-                    }
-                  reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_commit = true;
-                }
-	      else
-		{
+                        
+                        reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_commit = true;
+                      }
+                  }
+                else
+                  {
                   // Hit case
 
@@ -767,25 +787,26 @@
 // #endif
 
-                  if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
-                    {
-                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);
-                      reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;
-                    }
-		}
-
-              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_STATE     : %s",toString(reg_EVENT_STATE [context]).c_str());
-
-	      // In all case : update good_take
-	      reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take    = good_take;
-
-              // Write address_dest if need read register
-              Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
-              
-              if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or
-                  (condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK   ) or
-                  (condition == BRANCH_CONDITION_READ_STACK                       ) )
-                reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr;
-            }
-
+                  // In same cycle, can have a previous branch_complete
+                    if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
+                      {
+                        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);
+                        reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;
+                      }
+                  }
+                
+                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UPT_EVENT_STATE : %s",toString(reg_UPT_EVENT_STATE [context]).c_str());
+                
+                // In all case : update good_take
+                reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take    = good_take;
+                
+                // Write address_dest if need read register
+                Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
+                
+                if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or
+                    (condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK   ) or
+                    (condition == BRANCH_CONDITION_READ_STACK                       ) )
+                  reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr;
+              }
+        }
 
  	// ===================================================================
@@ -797,11 +818,15 @@
 	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * BRANCH_EVENT [%d] - Accepted",i);
 
-              // if different : an other branch is occured
-              if (reg_EVENT_STATE        [i] == EVENT_STATE_UPDATE_CONTEXT)
+              upt_event_state_t upt_event_state  = reg_UPT_EVENT_STATE [i];
+              
+              switch (upt_event_state)
                 {
-                  // Change state
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_WAIT_END_EVENT (branch_event)",i);
-                  reg_EVENT_STATE [i] = EVENT_STATE_WAIT_END_EVENT;
+                case UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT : upt_event_state = UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT; break;
+                case UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT; break;
+                default : break; // an other branch is occured
                 }
+
+              reg_UPT_EVENT_STATE [i] = upt_event_state;
+              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UPT_EVENT_STATE : %s (branch_event)",toString(upt_event_state).c_str());
             }
 
@@ -826,5 +851,6 @@
               //   * EVENT_TYPE_CSYNC              - nothing
               
-              Tevent_type_t  event_type  = PORT_READ(in_EVENT_TYPE  [i]);
+              Tevent_type_t     event_type      = PORT_READ(in_EVENT_TYPE  [i]);
+              upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [i];
 
               // Test if end of miss -> all previous branch is complete
@@ -837,38 +863,37 @@
                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * type  : EVENT_TYPE_BRANCH_MISS_SPECULATION");
 
-// #ifdef DEBUG_TEST
-//                     if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT)
-//                       throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state."));
-// #endif
-                    // Special case : test if event and branch_complete !
-                    if (reg_EVENT_STATE [i] == EVENT_STATE_WAIT_END_EVENT)
+                    switch (upt_event_state)
                       {
-                    
-                        // Change state
-                        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_OK (event)",i);
-                        
-                        reg_EVENT_STATE [i] = EVENT_STATE_OK;
-                        reg_IS_ACCURATE [i] = true;
-                        
-                        Tdepth_t depth = reg_EVENT_UPT_PTR [i];
-                        
-                        if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_END_KO)
-                          {
-                            log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_END (event)",i,depth);
-                            
-                            reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END;
-                          }
-                        
-#ifdef DEBUG_TEST
-//                     if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO_WAIT_END)
-//                       throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state."));
-//                  if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO)
-//                    throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state."));
-#endif
-
-//                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",i,depth);
-                    
-//                     reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
+                      case UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT :
+                        {
+                          Tdepth_t depth = reg_EVENT_UPT_PTR [i];
+                          
+                          log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * depth : %d",depth);
+                          
+                          if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_END_KO)
+                            {
+                              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_END (event)",i,depth);
+                              
+                              reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END;
+                            }
+
+                            reg_UPT_TOP    [i] = reg_UPT_TOP_EVENT [i];
+                            reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
+
+                          // break; continue
+                        }
+                      case UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT :
+                        {
+                          // Change state
+                          log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_OK (event)",i);
+                          
+                          upt_event_state = UPT_EVENT_STATE_OK;
+                          reg_IS_ACCURATE [i] = true;
+
+                          break;
+                        }
+                      default : break; // an other branch is occured
                       }
+
                     break;
                   }
@@ -893,8 +918,9 @@
 //                                                          (event_state == EVENT_STATE_EVENT_FLUSH_UPT));
 
-                    bool     find   = false; // have slot to update ???
-                    Tdepth_t top    = bottom;
-                    Tdepth_t update = bottom;
-                    bool     empty  = reg_UPT_EMPTY [i];
+                    bool     find     = false; // have slot to update ???
+                    bool     find_top = false;
+                    Tdepth_t top      = bottom;
+                    Tdepth_t update   = bottom;
+                    bool     empty    = reg_UPT_EMPTY [i];
 
                     // flush all slot, because this event is in head of rob
@@ -902,10 +928,14 @@
                       {
                         Tdepth_t x = (bottom+j)%_param->_size_upt_queue[i];
+
+                        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * UPT [%d] : %s",x,toString(reg_UPDATE_PREDICTION_TABLE [i][x]._state).c_str());
                         
                         if ((reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_END) and
                             (reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY))
                           {
+                            log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * find at UPT[%d]",x);
+
                             find = true; // find a not empty slot
-                            reg_UPDATE_PREDICTION_TABLE [i][x]._state = UPDATE_PREDICTION_STATE_EVENT;
+                            reg_UPDATE_PREDICTION_TABLE [i][x]._state     = UPDATE_PREDICTION_STATE_EVENT;
                             reg_UPDATE_PREDICTION_TABLE [i][x]._retire_ok = false;
                             update = x;
@@ -913,23 +943,27 @@
 
                         if (reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY)
-                          top = x+1;
+                          if (not find_top)
+                            {
+                              top = x;
+                              find_top = true;
+                            }
                       }
-
-                    top = top%_param->_size_upt_queue[i];
 
                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * find       : %d",find);
                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * top        : %d",top);
+                    log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * update     : %d",update);
                     
                     // Test if have update slot
+                    reg_UPT_TOP_EVENT [i] = reg_UPT_TOP[i];
                     if (find)
                       {
                         // TODO : special case : event is an exception on branch, also depth is not valid
                         reg_UPT_TOP       [i] = top; // depth is again valid
-                        reg_UPT_TOP_EVENT [i] = top;
                         
                         if (bottom == reg_UPT_TOP [i])
                           reg_UPT_EMPTY [i] = true;
+
+                        reg_UPT_UPDATE [i]  = update;
                       }
-                    reg_UPT_UPDATE [i]  = update;
               
                     // new state :
@@ -939,6 +973,7 @@
                     //            * ok : nothing
                     //            * ko : flush upt
-                    reg_EVENT_VAL             [i] = find;
-                    reg_EVENT_IS_BRANCH       [i] = false;
+//                     reg_EVENT_VAL             [i] = find;
+//                     reg_EVENT_IS_BRANCH       [i] = false;
+//                     reg_EVENT_UPT_PTR         [i] = ((top==0)?_param->_size_upt_queue[i]:top)-1; ///// ZE MODIF
                     reg_EVENT_UPT_PTR         [i] = top;
                     reg_EVENT_UPT_FULL        [i] = (not empty and (bottom == reg_UPT_TOP [i]));
@@ -952,5 +987,5 @@
                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UPT_EMPTY                    : %d",reg_UPT_EMPTY           [i]);
 
-                    log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_VAL                    : %d",reg_EVENT_VAL           [i]);
+//                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_VAL                    : %d",reg_EVENT_VAL           [i]);
                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_UPT_PTR                : %d",reg_EVENT_UPT_PTR       [i]);
                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_UPT_FULL               : %d",reg_EVENT_UPT_FULL      [i]);
@@ -958,172 +993,20 @@
                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_NB_UPDATE               : %d",reg_UFPT_NB_UPDATE      [i]);
 
-                    if ( (reg_UFPT_NB_NEED_UPDATE [i] > 0) or
-                         (reg_UFPT_NB_UPDATE      [i] > 0))
+                    if (find)
                       {
-                        if (find)
-                          {
-                            log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (event - find)",i);
-                            reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT;
-                          }
-                        else
-                          {
-                            log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (event - not find)",i);
-//                          reg_EVENT_VAL   [i] = false;
-
-                            reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT;
-                          }                          
+                        // have ras prediction ?
+                        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT (event - find)",i);
+                        
+                        upt_event_state = UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT;
                       }
                     else
                       {
-                        if (find)
-                          {
-                            // have ras prediction ?
-                            log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (event - find)",i);
-                            
-                            reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT;
-                          }
-                        else
-                          {
-                            // special case : nothing
-                            log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (event - not find)",i);
-
-//                          reg_EVENT_VAL     [i] = false;
-
-                            reg_EVENT_STATE [i] = EVENT_STATE_OK;
-                          }
+                        // special case : nothing
+                        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT (event - not find)",i);
+                        
+//                      reg_EVENT_VAL     [i] = false;
+                        
+                        upt_event_state = UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT;
                       }
-
-                    // else no update
-                    
-//                     Tdepth_t depth      = (_param->_have_port_depth)?PORT_READ(in_EVENT_DEPTH [i]):0;
-//                     uint32_t top        = reg_UPT_TOP    [i];
-//                     uint32_t bottom     = reg_UPT_BOTTOM [i];
-//                     uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; 
-// //                     bool     empty      = reg_UPT_EMPTY [i];
-
-//                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * top        : %d",top);
-//                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * depth      : %d",depth);
-//                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * new_update : %d",new_update);
-
-//                     event_state_t event_state         = reg_EVENT_STATE [i];
-//                     bool          previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
-//                                                          (event_state == EVENT_STATE_MISS_FLUSH_UPT          ) or
-//                                                          (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
-//                                                          (event_state == EVENT_STATE_EVENT_FLUSH_UPT));
-
-//                     bool     find = false; // have slot to update ???
-//                     Tdepth_t depth_new = depth;
-
-//                     // flush all slot, because this event is in head of rob
-//                     for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];
-//                          //uint32_t j=bottom;
-//                          j!=top; 
-//                          j=(j+1)%_param->_size_upt_queue[i])
-//                       if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and
-//                           (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY))
-//                         {
-//                           find = true;
-//                           reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;
-//                           reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok = false;
-//                         }
-//                       else
-//                         if (not find) // while state == end or empty
-//                           depth_new ++;
-                    
-//                     if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and
-//                         (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY))
-//                       {
-//                         find = true;
-//                         reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;
-//                         reg_UPDATE_PREDICTION_TABLE [i][depth]._retire_ok = false;
-
-//                       }
-//                     else
-//                       // while state == end or empty
-//                       depth = (depth_new+1)%_param->_size_upt_queue[i];
-
-//                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * find       : %d",find);
-//                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * depth_new  : %d",depth_new);
-                    
-//                     // Test if have update slot
-//                     if (find)
-//                       {
-// //                         // flush all slot after the event
-// //                         for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];
-// //                              j!=top; 
-// //                              j=(j+1)%_param->_size_upt_queue[i])
-// //                           reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;
-
-// //                         reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;
-                        
-//                         // reg_UPT_BOTTOM    [i];
-//                         // TODO : special case : event is an exception on branch, also depth is not valid
-//                         reg_UPT_TOP       [i] = depth; // depth is again valid
-//                         reg_UPT_TOP_EVENT [i] = top;
-                        
-//                         if (bottom == reg_UPT_TOP [i])
-//                           reg_UPT_EMPTY [i] = true;
-//                       }
-
-//                     bool     full       = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]);
-//                     bool     update_ras = find and ((top != depth) or full);
-                    
-//                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * update_ras : %d",update_ras);
-                    
-//                     if (not previous_update_ras and update_ras)
-//                       reg_UPT_UPDATE [i]  = new_update;
-              
-//                     // new state :
-//                     //   * test if ufpt is empty
-//                     //     * ok : flush upft and upt
-//                     //     * ko : test if have previous flush upt
-//                     //            * ok : nothing
-//                     //            * ko : flush upt
-//                     reg_EVENT_VAL     [i] = update_ras;
-//                     reg_EVENT_UPT_PTR [i] = depth;
-
-//                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_NB_NEED_UPDATE          : %d",reg_UFPT_NB_NEED_UPDATE [i]);
-// //                     if (reg_UFPT_NB_NEED_UPDATE [i] > 0)
-//                     if ( (reg_UFPT_NB_NEED_UPDATE [i] > 0) or
-//                          (reg_UFPT_NB_UPDATE      [i] > 0))
-//                       {
-//                         if (update_ras)
-//                           {
-//                             log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (branch_complete - miss)",i);
-//                             reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT;
-//                           }
-//                         else
-//                           {
-//                             log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (branch_complete - miss)",i);
-// //                          reg_EVENT_VAL   [i] = false;
-
-//                             reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT;
-//                           }                          
-//                       }
-//                     else
-//                       {
-// //                         if (not previous_update_ras)
-//                         if (update_ras)
-//                           {
-//                             // have ras prediction ?
-//                             log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (branch_complete - miss)",i);
-                            
-//                             reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT;
-//                           }
-//                         else
-//                           {
-//                             // special case : nothing
-// //                          reg_EVENT_VAL     [i] = false;
-
-//                             reg_EVENT_STATE [i] = EVENT_STATE_OK;
-//                           }
-//                       }
-
-//                     // else no update
-                    
-//                     reg_EVENT_DEPTH           [i] = depth;
-// //                  reg_EVENT_ADDRESS_SRC     [i] = address_src; // delay_slot is compute in I_State
-// //                  reg_EVENT_ADDRESS_DEST_VAL[i] = good_take;
-// //                  reg_EVENT_ADDRESS_DEST    [i] = good_addr;
 
                     break;
@@ -1135,4 +1018,7 @@
                   }
                 }
+
+              reg_UPT_EVENT_STATE [i] = upt_event_state;
+              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UPT_EVENT_STATE : %s (branch_event)",toString(upt_event_state).c_str());
             }
 
@@ -1149,5 +1035,5 @@
                 log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_NB_NEED_UPDATE          : %d",reg_UFPT_NB_NEED_UPDATE [i]);
 
-              // It's to accelerate miss speculation
+              // It's to accelerate miss speculation -> associative access
               if (reg_UFPT_NB_NEED_UPDATE [i] == 0)
                 {
@@ -1157,5 +1043,4 @@
                   reg_UFPT_BOTTOM [i] = 0;
                   reg_UFPT_TOP    [i] = 0;
-//                reg_UFPT_UPDATE [i];
                 }
               else
@@ -1176,10 +1061,6 @@
                     }
 
-//                   // TOP is next write slot : last slot is TOP-1
-//                   uint32_t top = reg_UFPT_TOP [i];
-//                   reg_UFPT_UPDATE    [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1;
-
-//                reg_UFPT_BOTTOM    [i];
-//                reg_UFPT_TOP       [i];
+                  // Change state
+                  reg_UFPT_EVENT_STATE [i] = UFPT_EVENT_STATE_KO_FLUSH;
                 }
 
@@ -1187,4 +1068,23 @@
 
               }
+
+            // Change state on UPT
+            {
+              upt_event_state_t  upt_event_state  = reg_UPT_EVENT_STATE  [i];
+              ufpt_event_state_t ufpt_event_state = reg_UFPT_EVENT_STATE [i];
+              
+              // Test upt event to change state
+              // test if upt wait ufpt
+              if (ufpt_event_state == UFPT_EVENT_STATE_OK)
+                switch (upt_event_state)
+                  {
+                    // this case when don't need flush upt (miss decod and can continue)
+                  case UPT_EVENT_STATE_KO_MISS_WAIT_UFPT  : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
+                  case UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_OK               ; break;
+                  default : break;
+                  }
+              
+              reg_UPT_EVENT_STATE [i] = upt_event_state;
+            }
           }
 
@@ -1212,9 +1112,10 @@
       {
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_IS_ACCURATE           : %d",reg_IS_ACCURATE        [i]);
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_VAL             : %d"  ,reg_EVENT_VAL             [i]);
+        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_UFPT_STATE      : %s"  ,toString(reg_UFPT_EVENT_STATE [i]).c_str());
+        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_UPT_STATE       : %s"  ,toString(reg_UPT_EVENT_STATE [i]).c_str());
+//         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_VAL             : %d"  ,reg_EVENT_VAL             [i]);
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_UPT_PTR         : %d"  ,reg_EVENT_UPT_PTR         [i]);
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_UPT_FULL        : %d"  ,reg_EVENT_UPT_FULL        [i]);
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_STATE           : %s"  ,toString(reg_EVENT_STATE [i]).c_str());
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_IS_BRANCH       : %d"  ,reg_EVENT_IS_BRANCH       [i]);
+//         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_IS_BRANCH       : %d"  ,reg_EVENT_IS_BRANCH       [i]);
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_DEPTH           : %d"  ,reg_EVENT_DEPTH           [i]);
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_ADDRESS_SRC     : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC     [i],reg_EVENT_ADDRESS_SRC     [i]<<2);
@@ -1223,5 +1124,5 @@
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_CAN_CONTINUE    : %d"  ,reg_EVENT_CAN_CONTINUE    [i]);
 
-	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * Update_Fetch_Prediction_Table   [%d]",i);
+	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * Dump UFPT [%d] (Update_Fetch_Prediction_Table)",i);
 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UFPT_BOTTOM         : %d",reg_UFPT_BOTTOM         [i]);
 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UFPT_TOP            : %d",reg_UFPT_TOP            [i]);
@@ -1246,5 +1147,5 @@
                      );
 
-	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * Update_Prediction_Table   [%d]",i);
+	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * Dump UPT [%d] (Update_Prediction_Table)",i);
 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_BOTTOM          : %d",reg_UPT_BOTTOM         [i]);
 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_TOP             : %d",reg_UPT_TOP            [i]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp	(revision 122)
@@ -120,6 +120,10 @@
     delete    _component_glue           ;
     delete    _component_context_state  ;
+    for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
+    delete    _component_decod_unit  [i];
     delete [] _component_decod_unit     ;
     delete    _component_prediction_unit;
+    for (uint32_t i=0; i<_param->_nb_context; i++)
+    delete    _component_ifetch_unit [i];
     delete [] _component_ifetch_unit    ;
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp	(revision 122)
@@ -292,12 +292,12 @@
     log_begin(Front_end,FUNCTION);
     
-    delete [] _param_glue           ;
-    delete [] _param_context_state  ;
+    delete    _param_glue           ;
+    delete    _param_context_state  ;
     for (uint32_t i=0; i<_nb_decod_unit; i++)
-      delete [] _param_decod_unit [i];
+    delete    _param_decod_unit [i];
     delete [] _param_decod_unit     ;
-    delete [] _param_prediction_unit;
+    delete    _param_prediction_unit;
     for (uint32_t i=0; i<_nb_context; i++)
-      delete [] _param_ifetch_unit [i];
+    delete    _param_ifetch_unit [i];
     delete [] _param_ifetch_unit    ;
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 122)
@@ -143,4 +143,6 @@
   public    : SC_IN (Tcontrol_t         ) ***  in_RETIRE_EVENT_ACK                 ;//[nb_front_end][nb_context]
   public    : SC_OUT(Tevent_state_t     ) *** out_RETIRE_EVENT_STATE               ;//[nb_front_end][nb_context]
+  public    : SC_OUT(Tcontrol_t         ) *** out_RETIRE_EVENT_FLUSH               ;//[nb_front_end][nb_context]
+  public    : SC_OUT(Tcontrol_t         ) *** out_RETIRE_EVENT_STOP                ;//[nb_front_end][nb_context]
 										   
     // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
@@ -233,4 +235,5 @@
   private   : uint32_t                        reg_NUM_BANK_HEAD                    ;
   private   : uint32_t                        reg_NUM_BANK_TAIL                    ;
+  private   : uint32_t                        reg_NUM_PTR_TAIL                     ;
   private   : uint32_t                      * reg_BANK_PTR                         ;//[nb_bank]
 
@@ -238,7 +241,14 @@
   private   : Tcounter_t                   ** reg_NB_INST_COMMIT_MEM               ;//[nb_front_end][nb_context]
 
-  private   : Tevent_state_t               ** reg_EVENT_STATE                      ;//[nb_front_end][nb_context]
-  private   : bool                         ** reg_EVENT_FLUSH                      ;//[nb_front_end][nb_context]
+  private   : Tcommit_event_state_t        ** reg_EVENT_STATE                      ;//[nb_front_end][nb_context]
+//private   : bool                         ** reg_EVENT_FLUSH                      ;//[nb_front_end][nb_context]
   private   : bool                         ** reg_EVENT_STOP                       ;//[nb_front_end][nb_context]
+  private   : uint32_t                     ** reg_EVENT_NUM_BANK                   ;//[nb_front_end][nb_context]
+  private   : uint32_t                     ** reg_EVENT_NUM_PTR                    ;//[nb_front_end][nb_context]
+  private   : bool                         ** reg_EVENT_CAN_RESTART                ;//[nb_front_end][nb_context]
+  private   : uint32_t                     ** reg_EVENT_PACKET                     ;//[nb_front_end][nb_context]
+  private   : bool                         ** reg_EVENT_LAST                       ;//[nb_front_end][nb_context]
+  private   : uint32_t                     ** reg_EVENT_LAST_NUM_BANK              ;//[nb_front_end][nb_context]
+  private   : uint32_t                     ** reg_EVENT_LAST_NUM_PTR               ;//[nb_front_end][nb_context]
 
 //private   : Taddress_t                   ** reg_PC_PREVIOUS                      ;//[nb_front_end][nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 122)
@@ -28,10 +28,16 @@
     {
       ROB_EMPTY                      , // 
+
       ROB_BRANCH_WAIT_END            , // 
       ROB_BRANCH_COMPLETE            , // 
-      ROB_STORE_WAIT_HEAD_OK         , // 
-//    ROB_STORE_WAIT_HEAD_KO         , // 
-      ROB_STORE_HEAD_OK              , // 
-      ROB_STORE_HEAD_KO              , // 
+
+      ROB_STORE_WAIT_END_OK          , // 
+      ROB_STORE_WAIT_END_KO          , // 
+      ROB_STORE_OK                   , // 
+      ROB_STORE_KO                   , // 
+      ROB_STORE_OK_WAIT_END          , // 
+      ROB_STORE_KO_WAIT_END          , // 
+      ROB_STORE_EVENT                , // 
+
       ROB_OTHER_WAIT_END             , // 
 
@@ -50,11 +56,24 @@
       ROB_END_EXCEPTION_WAIT_HEAD    , // 
       ROB_END_EXCEPTION_UPDATE       , // 
-      ROB_END_EXCEPTION                // 
+      ROB_END_EXCEPTION              , // 
+      ROB_END
+    } rob_state_t;
 
-    } rob_state_t;
+  typedef enum
+    {
+      COMMIT_EVENT_STATE_NO_EVENT  ,
+      COMMIT_EVENT_STATE_EVENT     ,
+      COMMIT_EVENT_STATE_WAIT_DECOD,
+      COMMIT_EVENT_STATE_WAIT_END  ,
+      COMMIT_EVENT_STATE_END     
+    } Tcommit_event_state_t;
+
+#define commit_event_state_to_event_state(x) ((x==COMMIT_EVENT_STATE_EVENT)?EVENT_STATE_EVENT:((x==COMMIT_EVENT_STATE_WAIT_DECOD)?EVENT_STATE_WAITEND:((x==COMMIT_EVENT_STATE_WAIT_END)?EVENT_STATE_WAITEND:((x==COMMIT_EVENT_STATE_END)?EVENT_STATE_END:EVENT_STATE_NO_EVENT))))
+
 
   class entry_t 
   {
   public  : rob_state_t        state                   ;
+  public  : rob_state_t        state_old               ;
   public  : uint32_t           ptr                     ;
   public  : Tcontext_t         front_end_id            ;
@@ -98,4 +117,5 @@
 //public  : Tgeneral_data_t    data_commit             ; // branch's destination
 #ifdef DEBUG
+  public  : Tgeneral_data_t    load_data               ;
   public  : Taddress_t         address                 ;
 #endif
@@ -121,8 +141,10 @@
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_WAIT_END            : return "ROB_BRANCH_WAIT_END"             ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_COMPLETE            : return "ROB_BRANCH_COMPLETE"             ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_OK         : return "ROB_STORE_WAIT_HEAD_OK"          ; break;
-//    case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_KO         : return "ROB_STORE_WAIT_HEAD_KO"          ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_OK              : return "ROB_STORE_HEAD_OK"               ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO              : return "ROB_STORE_HEAD_KO"               ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_END_OK          : return "ROB_STORE_WAIT_END_OK"           ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_END_KO          : return "ROB_STORE_WAIT_END_KO"           ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_OK                   : return "ROB_STORE_OK"                    ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_KO                   : return "ROB_STORE_KO"                    ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_OK_WAIT_END          : return "ROB_STORE_OK_WAIT_END"           ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_KO_WAIT_END          : return "ROB_STORE_KO_WAIT_END"           ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END             : return "ROB_OTHER_WAIT_END"              ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EVENT_WAIT_END             : return "ROB_EVENT_WAIT_END"              ; break;
@@ -140,4 +162,5 @@
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_UPDATE       : return "ROB_END_EXCEPTION_UPDATE"        ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION              : return "ROB_END_EXCEPTION"               ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END                        : return "ROB_END"                         ; break;
 
       default    : return ""      ; break;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 122)
@@ -141,4 +141,6 @@
       _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_ACK               ,ACK,_param->_nb_front_end,_param->_nb_context[it1]);
       _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STATE             ,"state"                ,Tevent_state_t    ,_param->_size_event_state           ,_param->_nb_front_end,_param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_FLUSH             ,"flush"                ,Tcontrol_t        ,1                                   ,_param->_nb_front_end,_param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STOP              ,"stop"                 ,Tcontrol_t        ,1                                   ,_param->_nb_front_end,_param->_nb_context[it1]);
 
       ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]);
@@ -306,21 +308,28 @@
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-    ALLOC2(_nb_cycle_idle           ,double        ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC1(_rob                     ,std::list<entry_t*>,_param->_nb_bank);
+    ALLOC2(_nb_cycle_idle           ,double               ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC1(_rob                     ,std::list<entry_t*>  ,_param->_nb_bank);
     
-    ALLOC1(reg_BANK_PTR             ,uint32_t      ,_param->_nb_bank);
-
-    ALLOC2(reg_NB_INST_COMMIT_ALL   ,Tcounter_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_NB_INST_COMMIT_MEM   ,Tcounter_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC1(reg_BANK_PTR             ,uint32_t             ,_param->_nb_bank);
+                                                          
+    ALLOC2(reg_NB_INST_COMMIT_ALL   ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_NB_INST_COMMIT_MEM   ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
     
-    ALLOC2(reg_EVENT_STATE          ,Tevent_state_t,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_FLUSH          ,bool          ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_STOP           ,bool          ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-//  ALLOC2(reg_PC_PREVIOUS          ,Taddress_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_CURRENT           ,Taddress_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_CURRENT_IS_DS     ,Taddress_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_CURRENT_IS_DS_TAKE,Taddress_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_NEXT              ,Taddress_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_STATE          ,Tcommit_event_state_t,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2(reg_EVENT_FLUSH          ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_STOP           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_NUM_BANK       ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_NUM_PTR        ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_CAN_RESTART    ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_PACKET         ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_LAST           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_LAST_NUM_BANK  ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_LAST_NUM_PTR   ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+                                                          
+//  ALLOC2(reg_PC_PREVIOUS          ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_PC_CURRENT           ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_PC_CURRENT_IS_DS     ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_PC_CURRENT_IS_DS_TAKE,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_PC_NEXT              ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
       }
 
@@ -345,4 +354,5 @@
       if (_param->_have_thread [i])
         {
+          
           std::string filename = morpheo::filename(MORPHEO_LOG,
                                                    "Instruction_flow-thread_"+toString(i),
@@ -351,7 +361,9 @@
                                                    false,
                                                    log_with_pid,
-                                                   false);
+                                                   true);
+
+          log_printf(TRACE,Commit_unit,FUNCTION,"KANE : %s",filename.c_str());
           
-          instruction_log_file [i] .open(filename.c_str() ,std::ios::out | std::ios::trunc);
+          instruction_log_file [i].open(filename.c_str() ,std::ios::out | std::ios::trunc);
         }
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 122)
@@ -94,4 +94,6 @@
         DELETE2_SIGNAL( in_RETIRE_EVENT_ACK               ,_param->_nb_front_end,_param->_nb_context[it1],1);
         DELETE2_SIGNAL(out_RETIRE_EVENT_STATE             ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_event_state);
+        DELETE2_SIGNAL(out_RETIRE_EVENT_FLUSH             ,_param->_nb_front_end,_param->_nb_context[it1],1);
+        DELETE2_SIGNAL(out_RETIRE_EVENT_STOP              ,_param->_nb_front_end,_param->_nb_context[it1],1);
 
         DELETE1_SIGNAL( in_COMMIT_VAL               ,_param->_nb_inst_commit,1                             );
@@ -202,7 +204,16 @@
         DELETE2(reg_NB_INST_COMMIT_ALL   ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_NB_INST_COMMIT_MEM   ,_param->_nb_front_end,_param->_nb_context [it1]);
+
         DELETE2(reg_EVENT_STATE          ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_FLUSH          ,_param->_nb_front_end,_param->_nb_context [it1]);
+//      DELETE2(reg_EVENT_FLUSH          ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_EVENT_STOP           ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_NUM_BANK       ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_NUM_PTR        ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_CAN_RESTART    ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_PACKET         ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_LAST           ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_LAST_NUM_BANK  ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_LAST_NUM_PTR   ,_param->_nb_front_end,_param->_nb_context [it1]);
+
 //      DELETE2(reg_PC_PREVIOUS          ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_PC_CURRENT           ,_param->_nb_front_end,_param->_nb_context [it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 122)
@@ -30,11 +30,13 @@
 #endif
     bool       can_rename_select [_param->_nb_rename_unit];
-    bool       event_stop;
-   
+//     bool       event_stop;
+    
+//     //     Initialisation
+//     event_stop = false; // one signal for all context.
+//     for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+//       for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+//         event_stop |= reg_EVENT_STOP [i][j];   
+
 //     Initialisation
-    event_stop = false; // one signal for all context.
-    for (uint32_t i=0; i<_param->_nb_front_end; ++i)
-      for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
-        event_stop |= reg_EVENT_STOP [i][j];
     for (uint32_t i=0; i<_param->_nb_bank; i++)
       {
@@ -57,5 +59,5 @@
 //     log_printf(TRACE,Commit_unit,FUNCTION,"  * reg_NUM_BANK_TAIL : %d",reg_NUM_BANK_TAIL);
 
-    if (not event_stop)
+//     if (not event_stop)
       {
         std::list<generic::priority::select_t> * select_insert = _priority_insert ->select(); // same select for all insert
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 122)
@@ -56,4 +56,5 @@
 
         }
+
     // Scan Top of each bank
     internal_BANK_RETIRE_HEAD = reg_NUM_BANK_HEAD;
@@ -62,4 +63,5 @@
 	uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank;
 
+        // Test if have instruction
 	if (not _rob[num_bank].empty())
 	  {
@@ -68,5 +70,5 @@
 	    uint32_t   x     = entry->rename_unit_id;
 	    uint32_t   y     = num_inst_retire [x];
-	
+	    bool       bypass= false;
             // test if :
             //  * can retire (all previous instruction is retired)
@@ -77,4 +79,7 @@
 	      {
 		rob_state_t state        = entry->state;
+                Tcontext_t  front_end_id = entry->front_end_id;
+                Tcontext_t  context_id   = entry->context_id;  
+                
                   if ((state == ROB_END_OK         ) or 
                       (state == ROB_END_KO         ) or 
@@ -87,6 +92,4 @@
                       Tcontrol_t         write_re       = entry->write_re;
                       Tspecial_address_t num_reg_re_log = entry->num_reg_re_log;
-                      Tcontext_t         front_end_id   = entry->front_end_id;
-                      Tcontext_t         context_id     = entry->context_id;  
                       
                       // if state is ok, when write flags in the SR regsiters
@@ -173,8 +176,21 @@
                         can_retire [x] = false;
                     }
+
+                  bypass = ((state == ROB_END              ) or 
+                            (state == ROB_STORE_OK         ) or 
+                            (state == ROB_STORE_KO         ) or
+                            (state == ROB_STORE_OK_WAIT_END) or 
+                            (state == ROB_STORE_KO_WAIT_END));
+                  
+                  uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank);
+
+                  // if future event, don't update after this event
+                  if (reg_EVENT_STOP [front_end_id][context_id] and
+                      (reg_EVENT_PACKET [entry->front_end_id][entry->context_id]  == packet))
+                    bypass = false;
 	      }
 
 	    // Retire "in-order"
-	    can_retire [x] &= retire_val [x][y];
+	    can_retire [x]  &= (retire_val [x][y] or bypass);
 	  }
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 122)
@@ -28,48 +28,83 @@
     // ===================================================================
     {
-      log_printf(TRACE,Commit_unit,FUNCTION,"  * REEXECUTE [0]");
-
-      // Store instruction comming Out Of Order in Load Store Unit. 
-      // Must be executed in no speculative mode. Also, send a signal when an Store is in head of ROB
-
-      Tcontrol_t val      = false;
-      uint32_t   num_bank = reg_NUM_BANK_HEAD;
-
-      if (not _rob[num_bank].empty())
+      uint32_t nb_scan_bank = 0; // last scan bank
+      bool     can_continue = true;
+
+      // for each reexecute_port
+      for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i)
 	{
-          log_printf(TRACE,Commit_unit,FUNCTION,"    * ROB is not empty");
-          log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank      : %d",num_bank);
-
-          entry_t    * entry = _rob [num_bank].front();
-	  rob_state_t  state = entry->state;
-
-          // Test state
-	  val   = ((state == ROB_STORE_HEAD_OK) or
-		   (state == ROB_STORE_HEAD_KO));
-
-          log_printf(TRACE,Commit_unit,FUNCTION,"    * val           : %d",val);
-	  if (val)
+	  log_printf(TRACE,Commit_unit,FUNCTION,"  * REEXECUTE [%d]",i);
+	  
+	  // Store instruction comming Out Of Order in Load Store Unit. 
+	  // Must be executed in no speculative mode. Also, send a signal when an Store is in head of ROB
+	  
+	  Tcontrol_t val = false;
+
+	  for (uint32_t j=nb_scan_bank; j<_param->_nb_bank; j++)
 	    {
-              Tpacket_t packet_id = ((entry->ptr << _param->_shift_num_slot) | num_bank);
-
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * packet_id     : %d",packet_id);
-	  
-              // Reexecute store
-	      if (_param->_have_port_context_id)
-  	      PORT_WRITE(out_REEXECUTE_CONTEXT_ID            [0], entry->context_id           );
-	      if (_param->_have_port_front_end_id)
-  	      PORT_WRITE(out_REEXECUTE_FRONT_END_ID          [0], entry->front_end_id         );
-	      if (_param->_have_port_rob_ptr  )
-  	      PORT_WRITE(out_REEXECUTE_PACKET_ID             [0], packet_id                   );
-	      PORT_WRITE(out_REEXECUTE_TYPE                  [0], entry->type                 );
-	      PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_WRITE [0], entry->store_queue_ptr_write);
-	      PORT_WRITE(out_REEXECUTE_OPERATION             [0], (state == ROB_STORE_HEAD_OK)?OPERATION_MEMORY_STORE_HEAD_OK:OPERATION_MEMORY_STORE_HEAD_KO);
-	    }
+	      nb_scan_bank ++;
+	      
+              // translate bank number
+	      uint32_t num_bank = (reg_NUM_BANK_HEAD+j)%_param->_nb_bank;
+	      
+	      log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank      : %d",num_bank);
+
+	      // Test if the head of rob is not empty
+	      if (not _rob[num_bank].empty())
+		{
+		  log_printf(TRACE,Commit_unit,FUNCTION,"    * ROB is not empty");
+		  
+		  // Read state
+		  entry_t    * entry = _rob [num_bank].front();
+		  rob_state_t  state = entry->state;
+		  
+		  // Test state
+		  //  * store is ko, send signal at store_queue
+		  //  * store_is ok, test if in head
+// 		  val   = (((state == ROB_STORE_OK) and (num_bank == (reg_NUM_BANK_HEAD))) or
+// 			    (state == ROB_STORE_KO)  or
+// 			    (state == ROB_STORE_EVENT)
+// 			    );
+		  val   = (((state == ROB_STORE_OK) and can_continue) or
+			    (state == ROB_STORE_KO)  or
+			    (state == ROB_STORE_EVENT)
+			    );
+		  
+                  can_continue &= ((state == ROB_STORE_OK          ) or
+                                   (state == ROB_STORE_OK_WAIT_END ) or
+                                   (state == ROB_END_OK_SPECULATIVE) or
+                                   (state == ROB_END_OK            ) or
+                                   (state == ROB_END               )
+                                   );
+
+		  log_printf(TRACE,Commit_unit,FUNCTION,"    * val           : %d",val);
+
+		  if (val)
+		    {
+		      internal_REEXECUTE_NUM_BANK [i] = num_bank;
+
+		      Tpacket_t packet_id = ((entry->ptr << _param->_shift_num_slot) | num_bank);
+		      
+		      log_printf(TRACE,Commit_unit,FUNCTION,"    * packet_id     : %d",packet_id);
+		      
+		      // Reexecute store
+		      if (_param->_have_port_context_id)
+		      PORT_WRITE(out_REEXECUTE_CONTEXT_ID            [i], entry->context_id           );
+		      if (_param->_have_port_front_end_id)
+		      PORT_WRITE(out_REEXECUTE_FRONT_END_ID          [i], entry->front_end_id         );
+		      if (_param->_have_port_rob_ptr  )
+		      PORT_WRITE(out_REEXECUTE_PACKET_ID             [i], packet_id                   );
+		      PORT_WRITE(out_REEXECUTE_TYPE                  [i], entry->type                 );
+		      PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_WRITE [i], entry->store_queue_ptr_write);
+		      PORT_WRITE(out_REEXECUTE_OPERATION             [i], (state == ROB_STORE_OK)?OPERATION_MEMORY_STORE_HEAD_OK:OPERATION_MEMORY_STORE_HEAD_KO);
+
+		      break; // Stop scan
+		    }
+		}
+	    }  
+
+	  internal_REEXECUTE_VAL      [i] = val;
+	  PORT_WRITE(out_REEXECUTE_VAL[i], internal_REEXECUTE_VAL [i]);
 	}
- 
-      internal_REEXECUTE_VAL      [0] = val;
-      internal_REEXECUTE_NUM_BANK [0] = num_bank;
-      
-      PORT_WRITE(out_REEXECUTE_VAL[0], internal_REEXECUTE_VAL [0]);
     }
 
@@ -79,9 +114,12 @@
     {
       // Branchement must be send at the prediction unit
-      uint32_t nb_scan_bank = 0;
+
+      uint32_t nb_scan_bank = 0; // last scan bank
 
       // for each port, find a valid branchement.
       for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
 	{
+          log_printf(TRACE,Commit_unit,FUNCTION,"  * BRANCH_COMPLETE [%d]",i);
+
 	  Tcontrol_t  val  = false;
 	  
@@ -92,20 +130,65 @@
               // translate bank number
 	      uint32_t num_bank = (reg_NUM_BANK_HEAD+j)%_param->_nb_bank;
+
+              log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank           : %d",num_bank);
 	      
+              // Test if in this bank, they have an instruction
 	      if (not _rob [num_bank].empty())
 		{
+                  log_printf(TRACE,Commit_unit,FUNCTION,"    * not empty");
+
+                  // Read information
 		  entry_t    * entry    = _rob [num_bank].front();
 		  rob_state_t  state    = entry->state;
-		  
-		  if (state == ROB_BRANCH_COMPLETE)
+		  Tcontext_t   front_end_id = entry->front_end_id;
+		  Tcontext_t   context_id   = entry->context_id  ;
+
+                  log_printf(TRACE,Commit_unit,FUNCTION,"    * front_end_id       : %d",front_end_id);
+                  log_printf(TRACE,Commit_unit,FUNCTION,"    * context_id         : %d",context_id  );
+
+                  // don't complete a branch when rob manage an present event
+		  if ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NO_EVENT) and
+                      (state == ROB_BRANCH_COMPLETE))
 		    {
-		      val = true;
-		      
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * find !!!");
+
+                      // test if have a future event (stop is set)
+                      log_printf(TRACE,Commit_unit,FUNCTION,"      * reg_EVENT_STOP   : %d",reg_EVENT_STOP [front_end_id][context_id]);
+
+                      if (reg_EVENT_STOP [front_end_id][context_id])
+                        {
+                          // Have future event, can complete the branch if the event is most speculative than this branchement
+                          // Also, need compare packet_id (is order)
+
+                          uint32_t _top = ((_rob[reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD);
+                          uint32_t _old = reg_EVENT_PACKET [front_end_id][context_id];
+                          uint32_t _new = ((entry->ptr << _param->_shift_num_slot) | num_bank);
+
+//                           log_printf(TRACE,Commit_unit,FUNCTION,"      * _top             : %d",_top);
+//                           log_printf(TRACE,Commit_unit,FUNCTION,"      * _old (before)    : %d",_old);
+//                           log_printf(TRACE,Commit_unit,FUNCTION,"      * _new (before)    : %d",_new);
+
+                          if (_old < _top) _old = _old+_param->_size_queue;
+                          if (_new < _top) _new = _new+_param->_size_queue;
+                          if (_new < _old) val = true;
+
+//                           log_printf(TRACE,Commit_unit,FUNCTION,"      * _old (after )    : %d",_old);
+//                           log_printf(TRACE,Commit_unit,FUNCTION,"      * _new (after )    : %d",_new);
+
+                        }
+                      else
+                        val = true;
+		      
+                      log_printf(TRACE,Commit_unit,FUNCTION,"      * val              : %d",val);
+
+                      if (val)
+                        {
+                          // Have an valid branchement to complete
 		      internal_BRANCH_COMPLETE_NUM_BANK           [i] = num_bank;
 		      
+		      if (_param->_have_port_front_end_id)
+		      PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i],        front_end_id    );
 		      if (_param->_have_port_context_id)
-		      PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID   [i], entry->context_id      );
-		      if (_param->_have_port_front_end_id)
-		      PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i], entry->front_end_id    );
+		      PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID   [i],        context_id      );
 		      if (_param->_have_port_depth)
 		      PORT_WRITE(out_BRANCH_COMPLETE_DEPTH        [i], entry->depth           );
@@ -114,5 +197,6 @@
 		      PORT_WRITE(out_BRANCH_COMPLETE_NO_SEQUENCE  [i], entry->no_sequence     );
 		      
-		      break;
+		      break; // Stop scan
+                        }
 		    }
 		}
@@ -131,4 +215,5 @@
       internal_UPDATE_NUM_BANK = reg_NUM_BANK_HEAD;
 
+      // Test if have an instruction
       if (not _rob[internal_UPDATE_NUM_BANK].empty())
 	{
@@ -138,4 +223,6 @@
 	  entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front();
 
+          // Test state
+          // Update if exception or load miss
           switch (entry->state)
             {
@@ -208,5 +295,14 @@
     for (uint32_t i=0; i<_param->_nb_front_end; i++)
       for (uint32_t j=0; j<_param->_nb_context [i]; j++)
-        PORT_WRITE(out_RETIRE_EVENT_STATE [i][j], reg_EVENT_STATE[i][j]);
+        {
+//        bool flush = reg_EVENT_FLUSH [i][j];
+          bool flush = (((reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_EVENT) or
+                         (reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_WAIT_DECOD)) and
+                        not reg_EVENT_CAN_RESTART[i][j]);
+
+          PORT_WRITE(out_RETIRE_EVENT_STATE [i][j], commit_event_state_to_event_state(reg_EVENT_STATE[i][j]));
+          PORT_WRITE(out_RETIRE_EVENT_FLUSH [i][j], flush);
+          PORT_WRITE(out_RETIRE_EVENT_STOP  [i][j], reg_EVENT_STOP [i][j]);
+        }
 
     log_end(Commit_unit,FUNCTION);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 122)
@@ -16,5 +16,4 @@
 namespace ooo_engine {
 namespace commit_unit {
-
   
 #undef  FUNCTION
@@ -41,4 +40,5 @@
 	reg_NUM_BANK_HEAD = 0;
 	reg_NUM_BANK_TAIL = 0;
+        reg_NUM_PTR_TAIL  = 0;
 
         // Reset counter
@@ -51,7 +51,8 @@
 	      reg_NB_INST_COMMIT_MEM    [i][j] = 0;
                                         
-              reg_EVENT_STATE           [i][j] = EVENT_STATE_NO_EVENT;
-              reg_EVENT_FLUSH           [i][j] = false;
+              reg_EVENT_STATE           [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
+//            reg_EVENT_FLUSH           [i][j] = false;
               reg_EVENT_STOP            [i][j] = false;
+              reg_EVENT_LAST            [i][j] = false;
 
 //            reg_PC_PREVIOUS           [i][j] = (0x100-4)>>2;
@@ -80,169 +81,246 @@
 	for (uint32_t i=0; i<_param->_nb_front_end; i++)
 	  for (uint32_t j=0; j<_param->_nb_context [i]; j++)
-            switch (reg_EVENT_STATE [i][j])
-              {
-              case EVENT_STATE_EVENT    : 
+            {
+              // Test if can_restart : (can_restart is to signal at the state than the decod_queue is empty)
+              //   *     no previous can_restart (trap for one)
+              //   * and decod_queue is empty
+              //   * and have an event or have a futur event
+              if (not reg_EVENT_CAN_RESTART [i][j] and
+                   (PORT_READ(in_NB_INST_DECOD_ALL [i][j]) == 0) and
+                   (reg_EVENT_STOP [i][j] or (reg_EVENT_STATE [i][j] != COMMIT_EVENT_STATE_NO_EVENT)))
+                reg_EVENT_CAN_RESTART [i][j] = true;
+
+              // Test event state
+              switch (reg_EVENT_STATE [i][j])
                 {
-                  if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j])
-                    reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; 
-                  break;
+                case COMMIT_EVENT_STATE_EVENT    : 
+                  {
+                    // Have an event, test if all composant have ack
+                    if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j])
+                      {
+                        // A minor optimisation : test if wait_decod is previously empty.
+                        if (not reg_EVENT_CAN_RESTART [i][j])
+                          reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_DECOD;
+                        else
+                          reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END; 
+                      }
+                    
+                    break;
+                  }
+                case COMMIT_EVENT_STATE_WAIT_DECOD : 
+                  {
+                    // Wait flush of decod_queue.
+                    // Test if can restart now
+                    if (reg_EVENT_CAN_RESTART [i][j])
+                      {
+                        //reg_EVENT_FLUSH [i][j] = false;
+
+                        // A minor optimisation : test if the last element is already retire
+                        if (not reg_EVENT_LAST [i][j])
+                          reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END;
+                        else
+                          reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END; 
+                      }
+                    break;
+                  }
+                case COMMIT_EVENT_STATE_WAIT_END : 
+                  {
+                    // Wait the flush of Re Order Buffer.
+                    // Test if the last element is retire
+                    if (reg_EVENT_LAST [i][j])
+                      reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END ; 
+                    
+                    break;
+                  }
+                case COMMIT_EVENT_STATE_END      :
+                  {
+                    // Just one cycle
+                    
+                    // flush of re order buffer is finish
+                    reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
+                    reg_EVENT_LAST  [i][j] = false;
+                    break;
+                  }
+                  //case COMMIT_EVENT_STATE_NO_EVENT : 
+                default : break;
                 }
-              case EVENT_STATE_WAITEND  : 
+            }
+
+	// ===================================================================
+	// =====[ INSERT ]====================================================
+	// ===================================================================
+        {
+          // variable to count instruction insert
+          uint32_t nb_insert = 0;
+
+          for (uint32_t i=0; i<_param->_nb_bank; i++)
+            {
+              // compute first bank number
+              uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank;
+              
+              if (internal_BANK_INSERT_VAL [num_bank])
                 {
-                  Tcounter_t nb_inst_all = PORT_READ(in_NB_INST_DECOD_ALL [i][j]) + reg_NB_INST_COMMIT_ALL [i][j];
-                  if (nb_inst_all == 0)
+                  // get rename unit source and instruction.
+                  uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank];
+                  uint32_t y = internal_BANK_INSERT_NUM_INST        [num_bank];
+                  
+                  // Test if an instruction is valid
+                  // (all in_order insert combinatory is in rename_unit )
+                  if (PORT_READ(in_INSERT_VAL [x][y]))
                     {
-                      reg_EVENT_STATE [i][j] = EVENT_STATE_END;
-                      reg_EVENT_FLUSH [i][j] = false;
-                      //reg_EVENT_STOP  [i][j] = false;
+                      log_printf(TRACE,Commit_unit,FUNCTION,"  * INSERT            [%d][%d]",x,y);
+                      
+                      // get information
+                      Tcontext_t   front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0;
+                      Tcontext_t   context_id   = (_param->_have_port_context_id  )?PORT_READ(in_INSERT_CONTEXT_ID   [x][y]):0;
+                      Ttype_t      type         = PORT_READ(in_INSERT_TYPE         [x][y]);
+                      Toperation_t operation    = PORT_READ(in_INSERT_OPERATION    [x][y]);
+                      bool         is_store     = is_operation_memory_store(operation);
+                      
+                      Texception_t exception    = PORT_READ(in_INSERT_EXCEPTION    [x][y]);
+                      Tcontrol_t   no_execute   = PORT_READ(in_INSERT_NO_EXECUTE   [x][y]);
+                      
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * front_end_id   : %d",front_end_id);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * context_id     : %d",context_id);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * type           : %s",toString(type).c_str());
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * operation      : %d",operation );
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * exception      : %d",exception );
+                      
+                      // Create new entry and write information
+                      entry_t * entry = new entry_t;
+                      uint32_t  ptr   = reg_BANK_PTR [num_bank];
+
+	              entry->ptr                     = ptr;
+	              entry->front_end_id            = front_end_id;
+	              entry->context_id              = context_id  ;
+	              entry->rename_unit_id          = x;
+	              entry->depth                   = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0;
+	              entry->type                    = type;
+	              entry->operation               = operation;
+	              entry->is_delay_slot           = PORT_READ(in_INSERT_IS_DELAY_SLOT         [x][y]);
+// 	              entry->address                 = PORT_READ(in_INSERT_ADDRESS               [x][y]);
+	              entry->exception               = exception;
+	              entry->exception_use           = PORT_READ(in_INSERT_EXCEPTION_USE         [x][y]);
+	              entry->use_store_queue         = (type == TYPE_MEMORY) and (    is_store) and (not no_execute);
+	              entry->use_load_queue          = (type == TYPE_MEMORY) and (not is_store) and (not no_execute);
+	              entry->store_queue_ptr_write   = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]);
+	              entry->load_queue_ptr_write    = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0;
+#ifdef DEBUG        
+	              entry->read_ra                 = PORT_READ(in_INSERT_READ_RA               [x][y]);
+	              entry->num_reg_ra_log          = PORT_READ(in_INSERT_NUM_REG_RA_LOG        [x][y]);
+	              entry->num_reg_ra_phy          = PORT_READ(in_INSERT_NUM_REG_RA_PHY        [x][y]);
+	              entry->read_rb                 = PORT_READ(in_INSERT_READ_RB               [x][y]);
+	              entry->num_reg_rb_log          = PORT_READ(in_INSERT_NUM_REG_RB_LOG        [x][y]);
+	              entry->num_reg_rb_phy          = PORT_READ(in_INSERT_NUM_REG_RB_PHY        [x][y]);
+	              entry->read_rc                 = PORT_READ(in_INSERT_READ_RC               [x][y]);
+	              entry->num_reg_rc_log          = PORT_READ(in_INSERT_NUM_REG_RC_LOG        [x][y]);
+	              entry->num_reg_rc_phy          = PORT_READ(in_INSERT_NUM_REG_RC_PHY        [x][y]);
+#endif                
+	              entry->write_rd                = PORT_READ(in_INSERT_WRITE_RD              [x][y]);
+	              entry->num_reg_rd_log          = PORT_READ(in_INSERT_NUM_REG_RD_LOG        [x][y]);
+	              entry->num_reg_rd_phy_old      = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD    [x][y]);
+	              entry->num_reg_rd_phy_new      = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW    [x][y]);
+	              entry->write_re                = PORT_READ(in_INSERT_WRITE_RE              [x][y]);
+	              entry->num_reg_re_log          = PORT_READ(in_INSERT_NUM_REG_RE_LOG        [x][y]);
+	              entry->num_reg_re_phy_old      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD    [x][y]);
+	              entry->num_reg_re_phy_new      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW    [x][y]);
+                      entry->no_sequence             = type == TYPE_BRANCH;
+                      entry->speculative             = true;
+#ifdef DEBUG        
+	              entry->address                 = PORT_READ(in_INSERT_ADDRESS               [x][y]);
+#endif                
+	              entry->address_next            = PORT_READ(in_INSERT_ADDRESS_NEXT          [x][y]);
+#ifdef DEBUG        
+                      entry->cycle_rob_in            = simulation_cycle();
+                      entry->cycle_commit            = simulation_cycle();
+#endif      
+            
+                      // Test if exception :
+                      //  * yes : no execute instruction, wait ROB Head
+                      //  * no  : test if no_execute (== instruction is flushed)
+                      //          else test type
+                      //            * BRANCH : l.j   -> branch is ended
+                      //                       other -> wait the execution end of branchment
+                      //            * MEMORY : store -> wait store is at head of ROB
+                      //                       other -> wait end of instruction
+                      //            * OTHER
+            
+                      {
+                        if (exception == EXCEPTION_NONE)
+                          {
+                            // no_execute : l.j, l.nop, l.rfe
+                            
+                            log_printf(TRACE,Commit_unit,FUNCTION,"    * no_execute     : %d",no_execute);
+                            
+                            switch (type)
+                              {
+                              case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END  ; break;}
+                              case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store  ==1)?ROB_STORE_WAIT_END_OK:ROB_OTHER_WAIT_END); break;}
+                              default          : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
+                              }
+                          }
+                        else
+                          {
+                            // Have an exception : wait head of ROB
+                            // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
+                            
+                            entry->state = ROB_END_EXCEPTION_WAIT_HEAD;
+                          }
+                      }
+
+#ifdef STATISTICS
+                      if (usage_is_set(_usage,USE_STATISTICS))
+                        (*_stat_nb_inst_insert [x]) ++;
+#endif
+                    
+                      // Push entry in rob
+                      _rob[num_bank].push_back(entry);
+                      
+                      // Update counter and pointer
+                      reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++;
+                      if (type == TYPE_MEMORY)
+                        reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++;
+                      
+
+                      // flush = present event or future event.
+                      //  * present event = don't can restart
+
+//                       bool flush = reg_EVENT_FLUSH [front_end_id][context_id];
+
+//                       bool flush = (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
+//                                      (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)) or
+//                                     (reg_EVENT_STOP [front_end_id][context_id]));
+                      
+                      // New instruction from decod_queue. Flush if :
+                      //     * future event (instruction don't need execute because they are a previous event (miss load/branch or exception))
+                      //     * or present_event 
+                      //   * and not can_restart (previous empty decod queue), because between the event_stop (branch_complete) and the state event (miss in head), many cycle is occured.
+                      bool flush = ((// present event
+                                     ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
+                                      (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)) or
+                                     // futur event
+                                     reg_EVENT_STOP [front_end_id][context_id])
+                                    // can't restart
+                                    and not reg_EVENT_CAN_RESTART[front_end_id][context_id]
+                                    );
+
+                      if (flush)
+                        {
+                          // A new invalid instruction is push in rob -> new last instruction
+                          reg_EVENT_LAST          [front_end_id][context_id] = false;
+                          reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = num_bank;
+                          reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] = ptr;
+                        }
+                      
+                      // Update pointer
+                      reg_NUM_PTR_TAIL  = ptr;
+                      reg_BANK_PTR [num_bank]  = (reg_BANK_PTR [num_bank]+1)%_param->_size_bank;
+                      nb_insert ++;
                     }
-                  break;
                 }
-              case EVENT_STATE_END      :
-                {
-                  reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT;
-                  break;
-                }
-//            case EVENT_STATE_NO_EVENT : 
-              default : break;
-              }
-
-	// ===================================================================
-	// =====[ INSERT ]====================================================
-	// ===================================================================
-	for (uint32_t i=0; i<_param->_nb_bank; i++)
-	  if (internal_BANK_INSERT_VAL [i])
-	    {
-              // get rename unit source and instruction.
-	      uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i];
-	      uint32_t y = internal_BANK_INSERT_NUM_INST        [i];
-
-	      if (PORT_READ(in_INSERT_VAL [x][y]))
-		{
-		  log_printf(TRACE,Commit_unit,FUNCTION,"  * INSERT            [%d][%d]",x,y);
-
-                  // get information
-		  Tcontext_t   front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0;
-		  Tcontext_t   context_id   = (_param->_have_port_context_id  )?PORT_READ(in_INSERT_CONTEXT_ID   [x][y]):0;
-		  Ttype_t      type         = PORT_READ(in_INSERT_TYPE         [x][y]);
-                  Toperation_t operation    = PORT_READ(in_INSERT_OPERATION    [x][y]);
-                  bool         is_store     = is_operation_memory_store(operation);
-
-		  Texception_t exception    = PORT_READ(in_INSERT_EXCEPTION    [x][y]);
-		  Tcontrol_t   no_execute   = PORT_READ(in_INSERT_NO_EXECUTE   [x][y]);
-
-		  log_printf(TRACE,Commit_unit,FUNCTION,"    * front_end_id   : %d",front_end_id);
-		  log_printf(TRACE,Commit_unit,FUNCTION,"    * context_id     : %d",context_id);
-		  log_printf(TRACE,Commit_unit,FUNCTION,"    * type           : %s",toString(type).c_str());
-		  log_printf(TRACE,Commit_unit,FUNCTION,"    * operation      : %d",operation );
-		  log_printf(TRACE,Commit_unit,FUNCTION,"    * exception      : %d",exception );
-                  
-                  // Create new entry.
-		  entry_t * entry = new entry_t;
-
-		  entry->ptr                     = reg_BANK_PTR [i];
-		  entry->front_end_id            = front_end_id;
-		  entry->context_id              = context_id  ;
-		  entry->rename_unit_id          = x;
-		  entry->depth                   = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0;
-		  entry->type                    = type;
-		  entry->operation               = operation;
-		  entry->is_delay_slot           = PORT_READ(in_INSERT_IS_DELAY_SLOT         [x][y]);
-// 		  entry->address                 = PORT_READ(in_INSERT_ADDRESS               [x][y]);
-		  entry->exception               = exception;
-		  entry->exception_use           = PORT_READ(in_INSERT_EXCEPTION_USE         [x][y]);
-		  entry->use_store_queue         = (type == TYPE_MEMORY) and (    is_store) and (not no_execute);
-		  entry->use_load_queue          = (type == TYPE_MEMORY) and (not is_store) and (not no_execute);
-		  entry->store_queue_ptr_write   = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]);
-		  entry->load_queue_ptr_write    = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0;
-#ifdef DEBUG
-		  entry->read_ra                 = PORT_READ(in_INSERT_READ_RA               [x][y]);
-		  entry->num_reg_ra_log          = PORT_READ(in_INSERT_NUM_REG_RA_LOG        [x][y]);
-		  entry->num_reg_ra_phy          = PORT_READ(in_INSERT_NUM_REG_RA_PHY        [x][y]);
-		  entry->read_rb                 = PORT_READ(in_INSERT_READ_RB               [x][y]);
-		  entry->num_reg_rb_log          = PORT_READ(in_INSERT_NUM_REG_RB_LOG        [x][y]);
-		  entry->num_reg_rb_phy          = PORT_READ(in_INSERT_NUM_REG_RB_PHY        [x][y]);
-		  entry->read_rc                 = PORT_READ(in_INSERT_READ_RC               [x][y]);
-		  entry->num_reg_rc_log          = PORT_READ(in_INSERT_NUM_REG_RC_LOG        [x][y]);
-		  entry->num_reg_rc_phy          = PORT_READ(in_INSERT_NUM_REG_RC_PHY        [x][y]);
-#endif
-		  entry->write_rd                = PORT_READ(in_INSERT_WRITE_RD              [x][y]);
-		  entry->num_reg_rd_log          = PORT_READ(in_INSERT_NUM_REG_RD_LOG        [x][y]);
-		  entry->num_reg_rd_phy_old      = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD    [x][y]);
-		  entry->num_reg_rd_phy_new      = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW    [x][y]);
-		  entry->write_re                = PORT_READ(in_INSERT_WRITE_RE              [x][y]);
-		  entry->num_reg_re_log          = PORT_READ(in_INSERT_NUM_REG_RE_LOG        [x][y]);
-		  entry->num_reg_re_phy_old      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD    [x][y]);
-		  entry->num_reg_re_phy_new      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW    [x][y]);
-                  entry->no_sequence             = type == TYPE_BRANCH;
-                  entry->speculative             = true;
-#ifdef DEBUG
-		  entry->address                 = PORT_READ(in_INSERT_ADDRESS               [x][y]);
-#endif
-		  entry->address_next            = PORT_READ(in_INSERT_ADDRESS_NEXT          [x][y]);
-#ifdef DEBUG
-                  entry->cycle_rob_in            = simulation_cycle();
-                  entry->cycle_commit            = simulation_cycle();
-#endif
-
-                  // Test if exception :
-                  //  * yes : no execute instruction, wait ROB Head
-                  //  * no  : test type
-                  //            * BRANCH : l.j   -> branch is ended
-                  //                       other -> wait the execution end of branchment
-                  //            * MEMORY : store -> wait store is at head of ROB
-                  //                       other -> wait end of instruction
-                  //            * OTHER
-
-//                   bool       flush      = reg_EVENT_FLUSH [front_end_id][context_id];
-
-//                   log_printf(TRACE,Commit_unit,FUNCTION,"    * flush          : %d",flush);
-
-//                   if (flush)
-//                     {
-//                       entry->state    = ROB_END_MISS; // All type (branch, memory and others), because, is not execute
-//                     }
-//                   else
-                    {
-                      if (exception == EXCEPTION_NONE)
-                        {
-                          // no_execute : l.j, l.nop, l.rfe
-                          
-                          log_printf(TRACE,Commit_unit,FUNCTION,"    * no_execute     : %d",no_execute);
-                          
-                          switch (type)
-                            {
-                            case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END  ; break;}
-                            case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store  ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END); break;}
-                            default          : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
-                            }
-                        }
-                      else
-                        {
-                          // Have an exception : wait head of ROB
-                          
-                          // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
-                          
-                          entry->state = ROB_END_EXCEPTION_WAIT_HEAD;
-                        }
-                    }
-
-#ifdef STATISTICS
-                  if (usage_is_set(_usage,USE_STATISTICS))
-                    (*_stat_nb_inst_insert [x]) ++;
-#endif
-
-                  // Push in rob
-		  _rob[i].push_back(entry);
-
-		  // Update counter and pointer
-		  reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++;
-		  if (type == TYPE_MEMORY)
-		    reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++;
-
-		  reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+1)%_param->_nb_bank;
-		  reg_BANK_PTR [i]  = (reg_BANK_PTR [i]+1)%_param->_size_bank;
-		}
-	    }
+            }
+          // Update pointer
+          reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+nb_insert)%_param->_nb_bank;
+        }
 
 	// ===================================================================
@@ -255,12 +333,17 @@
 #endif
 
+        // For each commit instruction ...
 	for (uint32_t i=0; i<_param->_nb_bank; i++)
 	  for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++)
+            // ... test if an instruction have finish this execution
 	    if (internal_BANK_COMMIT_VAL [i][j])
 	      {
-                // An instruction is executed. Change state of this instruction
-
+                // An instruction is executed -> Change state of this instruction
+
+                // Get information
 		uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j];
 
+                // Test if instruction is valid and is enable
+                // (can be disable if this instruction is reexecute)
 		if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x]))
 		  {
@@ -278,5 +361,12 @@
                                                  
 		  //Toperation_t    operation    = PORT_READ(in_COMMIT_OPERATION   [x]);
-		  //Ttype_t         type         = PORT_READ(in_COMMIT_TYPE        [x]);
+ 		    Ttype_t         type         = entry->type;
+		    Tcontrol_t      no_sequence  = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);
+
+#if 0
+		    if ((type == TYPE_MEMORY) and no_sequence)
+		      continue;
+#endif		    
+
 		    Texception_t    exception    = PORT_READ(in_COMMIT_EXCEPTION   [x]);
 
@@ -286,14 +376,17 @@
 
 		    // change state : test exception_use
-		    //  * test if exception : exception and mask
 		    
 		    bool have_exception        = false;
                     bool have_miss_speculation = false;
 
+                    // Test if have an exception ...
 		    if (exception != EXCEPTION_NONE)
                       {
-                        // Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store)
+                        // Test if the instruction is a load and is a miss speculation 
+                        // (load is commit, but they have an dependence with a previous store -> need restart pipeline)
+
                         have_miss_speculation  = (exception == EXCEPTION_MEMORY_MISS_SPECULATION);
 
+                        //  * Test if the exception generated can be trap by this exception
                         switch (entry->exception_use)
                           {
@@ -327,12 +420,56 @@
                       }
                    
+                    // Next state depends of previous state
                     switch (state)
                       {
-                        // Branch ...
-                      case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;}
-                        // Store KO
-                      case ROB_EVENT_WAIT_END  : {state = ROB_END_KO_SPECULATIVE; break;}
-                        // Store OK, Load and other instruction
-                      case ROB_OTHER_WAIT_END  : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_LOAD_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE); break;}
+                        // Branch : if no exception, the branchement can be completed
+                      case ROB_BRANCH_WAIT_END : 
+                        {
+                          if (not have_exception)
+                            state = ROB_BRANCH_COMPLETE;
+                          else
+                            state = ROB_END_EXCEPTION_WAIT_HEAD;
+                          break;
+                        }
+                        // Previous event -> set state as execute
+		      case ROB_STORE_KO_WAIT_END :
+                      case ROB_EVENT_WAIT_END  : 
+                        {
+                          state = ROB_END_KO_SPECULATIVE; 
+                          break;
+                        }
+                        // No previous event - Load and other instruction
+		      case ROB_STORE_OK_WAIT_END :
+                      case ROB_OTHER_WAIT_END  : 
+                        {
+                          if (not have_exception)
+                            {
+                              if (not have_miss_speculation)
+                                state = ROB_END_OK_SPECULATIVE;
+                              else
+                                state = ROB_END_LOAD_MISS_SPECULATIVE; 
+                            }
+                          else
+                            state = ROB_END_EXCEPTION_WAIT_HEAD;
+                          break;
+                        }
+		      case ROB_STORE_WAIT_END_OK :
+			{
+			  if (not have_exception)
+			    state = ROB_STORE_OK;
+			  else
+                            state = ROB_STORE_EVENT;
+			  break;
+			}
+		      case ROB_STORE_WAIT_END_KO :
+			{
+// 			  if (not have_exception)
+			    state = ROB_STORE_KO;
+// 			  else
+//                             state = ROB_END_EXCEPTION_WAIT_HEAD; 
+			  break;
+			}
+
+
                       default :
                         {
@@ -342,15 +479,50 @@
                       }
 
-                    if ((have_exception or have_miss_speculation) and
-                        (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0))
-                      reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true;
-
-		    // update Re Order Buffer
+                    // Commit an instruction ... 
+                    // Test if have an event (miss_speculation or exception) and not manage a previous event
+                    // if yes, this instruction would modify state machine. Also stop Re Order Buffer
+
+//                  bool flush = reg_EVENT_FLUSH [entry->front_end_id][entry->context_id];
+                    bool flush = ((reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_EVENT) or
+                                  (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or
+                                  (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_WAIT_END));
+                    
+                    if ((have_exception or have_miss_speculation) and (not flush))
+                      {
+                        uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | i);
+                        
+                        // test have a previous event detected (event_stop = 1)
+                        // if yes, test if the actual event if "before (in order)" that the previous event
+                        if (reg_EVENT_STOP [entry->front_end_id][entry->context_id])
+                          {
+                            // Compare packet_id (by construction instruction is insert in order by increase packet_id)
+
+                            uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD);
+                            uint32_t _old = reg_EVENT_PACKET [entry->front_end_id][entry->context_id];
+                            uint32_t _new = packet;
+                            if (_old < _top) _old = _old+_param->_size_queue;
+                            if (_new < _top) _new = _new+_param->_size_queue;
+                            if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
+                          }
+                        else
+                          reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
+                        
+                        // have an error, stop issue instruction
+                        reg_EVENT_STOP          [entry->front_end_id][entry->context_id] = true;
+//                         reg_EVENT_NUM_BANK      [entry->front_end_id][entry->context_id] = i;
+//                         reg_EVENT_NUM_PTR       [entry->front_end_id][entry->context_id] = entry->ptr;
+
+//                      reg_EVENT_CAN_RESTART   [entry->front_end_id][entry->context_id] = false;
+                        reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
+                        reg_EVENT_LAST_NUM_PTR  [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL;
+                      }
+                    
+		    // Update Re Order Buffer
 		    entry->state        = state;
 		    entry->exception    = exception;
 		    entry->flags        = PORT_READ(in_COMMIT_FLAGS       [x]);
-		    entry->no_sequence  = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);
+		    entry->no_sequence  = no_sequence;
                     // jalr, jr : address_dest is in register
-                    if ((entry->type      == TYPE_BRANCH) and
+                    if ((       type      == TYPE_BRANCH) and
                         (entry->operation == OPERATION_BRANCH_L_JALR) and
                         (entry->read_rb))
@@ -358,5 +530,6 @@
 
 #ifdef DEBUG
-                  entry->cycle_commit            = simulation_cycle();
+                    entry->load_data               = PORT_READ(in_COMMIT_ADDRESS [x]);
+                    entry->cycle_commit            = simulation_cycle();
 #endif
 		  }
@@ -368,8 +541,11 @@
 	for (uint32_t i=0; i<_param->_nb_bank; i++)
           {
+            // Compute bank number
             uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank;
             
+            // Test if have an request
             if (internal_BANK_RETIRE_VAL [num_bank])
               {
+                // Take num instruction
                 uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank];
                 uint32_t y = internal_BANK_RETIRE_NUM_INST        [num_bank];
@@ -382,128 +558,197 @@
                   throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n"));
 #endif
+
+
+#ifdef STATISTICS
+	    if (usage_is_set(_usage,USE_STATISTICS))
+	      (*_stat_nb_inst_retire [x]) ++;
                 
-                entry_t *  entry        =  _rob [num_bank].front();
-                rob_state_t state = entry->state;
+#endif
                 
-                Tcontext_t front_end_id = entry->front_end_id;
-                Tcontext_t context_id   = entry->context_id  ;
-                uint32_t   num_thread   = _param->_translate_num_context_to_num_thread [front_end_id][context_id];
-                Ttype_t    type         = entry->type        ;
-                bool       retire_ok    = false;
-
-                log_printf(TRACE,Commit_unit,FUNCTION,"    * front_end_id : %d",front_end_id );
-                log_printf(TRACE,Commit_unit,FUNCTION,"    * context_id   : %d",context_id   );
-                log_printf(TRACE,Commit_unit,FUNCTION,"    * rob_ptr      : %d",((entry->ptr << _param->_shift_num_slot) | num_bank));
-                log_printf(TRACE,Commit_unit,FUNCTION,"    * num_thread   : %d",num_thread   );
-                log_printf(TRACE,Commit_unit,FUNCTION,"    * type         : %s",toString(type).c_str());
-                log_printf(TRACE,Commit_unit,FUNCTION,"    * state        : %s",toString(state).c_str());
-
-                if ((state == ROB_END_OK         ) or
-// 		    (state == ROB_END_KO         ) or 
-                    (state == ROB_END_BRANCH_MISS) or 
-                    (state == ROB_END_LOAD_MISS  )//  or 
-// 		    (state == ROB_END_MISS       ) or 
-// 		    (state == ROB_END_EXCEPTION  )
-                    )
-                  {
-                    log_printf(TRACE,Commit_unit,FUNCTION,"    * retire_ok");
-
-                    retire_ok = true;
-
-//                  reg_PC_PREVIOUS           [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id];
-                    reg_PC_CURRENT            [front_end_id][context_id] = reg_PC_NEXT    [front_end_id][context_id];
-                    reg_PC_CURRENT_IS_DS      [front_end_id][context_id] = entry->type == TYPE_BRANCH;
-                    reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence;
-                    reg_PC_NEXT               [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1);
-
-//                   if (entry->address_next != reg_PC_NEXT [front_end_id][context_id])
-//                     throw ERRORMORPHEO(FUNCTION,toString(_("Retire : Instruction's address_next (%.8x) is different of commit_unit's address_next (%.8x)"),entry->address_next,reg_PC_NEXT [front_end_id][context_id]));
-                  }
-
-                if ((state == ROB_END_BRANCH_MISS) or
-                    (state == ROB_END_LOAD_MISS))
-                    {
-                      reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT;
-                      reg_EVENT_FLUSH [front_end_id][context_id] = true;
-                      reg_EVENT_STOP  [front_end_id][context_id] = false;
-                    }
-                
-#if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true)
-                // log file
-                instruction_log_file [num_thread] 
-                  << "[" << simulation_cycle() << "] "
-                  << std::hex
-                  << (entry->address<<2) << " (" << (entry->address) << ") "
-                  << std::dec
-                  << "[" << entry->cycle_rob_in << ", " << entry->cycle_commit << "] "
-                  << "{" << ((retire_ok)?" OK ":"!KO!") << "} "
-                  << std::endl;
-#endif
-
-                // Update nb_inst
-                reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --;
-                if (type == TYPE_MEMORY)
-                  reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
-                
-                reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank;
-                
-                delete entry;
-                _rob [num_bank].pop_front();
-                
-                // Transaction on retire interface : reset watch dog timer.
-                _nb_cycle_idle [front_end_id][context_id] = 0;
-
-                // Increase stop condition
-                if (retire_ok)
-                  _simulation_nb_instruction_commited [num_thread] ++;
-
-#ifdef STATISTICS
-                if (usage_is_set(_usage,USE_STATISTICS))
-                  {
-                    (*_stat_nb_inst_retire [x]) ++;
-                    
-                    if (retire_ok)
-                      {
-                        (*_stat_nb_inst_retire_ok [num_thread]) ++;
-                        (*_stat_nb_inst_type      [type]      ) ++;
-                      }
-                    else
-                      (*_stat_nb_inst_retire_ko [num_thread]) ++;
-                  }
-#endif
+                // Read information
+                entry_t *   entry        =  _rob [num_bank].front();
+
+                entry->state_old = entry->state;
+                entry->state     = ROB_END;
               }
           }
 
+	for (uint32_t i=0; i<_param->_nb_bank; i++)
+	  {
+	    // Compute bank number
+	    bool      can_continue = false;
+	    uint32_t  num_bank = reg_NUM_BANK_HEAD;
+	    
+	    if (not _rob [num_bank].empty ())
+	      {
+	        entry_t * entry = _rob [num_bank].front();
+	        
+	        if (entry->state == ROB_END)
+	          {
+	            log_printf(TRACE,Commit_unit,FUNCTION,"  * RETIRE_ROB [%d]",num_bank);
+	    
+                    can_continue = true;
+
+	            Tcontext_t  front_end_id = entry->front_end_id;
+	            Tcontext_t  context_id   = entry->context_id  ;
+	            uint32_t    num_thread   = _param->_translate_num_context_to_num_thread [front_end_id][context_id];
+	            rob_state_t state        = entry->state_old;
+	            Ttype_t     type         = entry->type        ;
+	            bool        retire_ok    = false;
+	            uint32_t    packet_id    = ((entry->ptr << _param->_shift_num_slot) | num_bank);
+	            
+	            log_printf(TRACE,Commit_unit,FUNCTION,"    * front_end_id : %d",front_end_id );
+	            log_printf(TRACE,Commit_unit,FUNCTION,"    * context_id   : %d",context_id   );
+	            log_printf(TRACE,Commit_unit,FUNCTION,"    * rob_ptr      : %d",packet_id    );
+	            log_printf(TRACE,Commit_unit,FUNCTION,"    * num_thread   : %d",num_thread   );
+	            log_printf(TRACE,Commit_unit,FUNCTION,"    * type         : %s",toString(type).c_str());
+	            log_printf(TRACE,Commit_unit,FUNCTION,"    * state        : %s",toString(state).c_str());
+	            
+                    // Test if the instruction is valid
+                    // (BRANCH_MISS = instruction branch is valid, but have make an invalid prediction)
+                    // (LOAD_MISS   = instruction load   is valid, but have make an invalid result)
+                    if ((state == ROB_END_OK         ) or
+// 	                (state == ROB_END_KO         ) or 
+                        (state == ROB_END_BRANCH_MISS) or 
+                        (state == ROB_END_LOAD_MISS  )//  or 
+// 	                (state == ROB_END_MISS       ) or 
+// 	                (state == ROB_END_EXCEPTION  )
+                        )
+                      {
+                        log_printf(TRACE,Commit_unit,FUNCTION,"    * retire_ok");
+	            
+                        retire_ok = true;
+	            
+                        // Update PC information
+//                      reg_PC_PREVIOUS           [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id];
+                        reg_PC_CURRENT            [front_end_id][context_id] = reg_PC_NEXT    [front_end_id][context_id];
+                        reg_PC_CURRENT_IS_DS      [front_end_id][context_id] = type == TYPE_BRANCH;
+                        reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence;
+                        reg_PC_NEXT               [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1);
+                      }
+	            
+                    // Test if have an event
+                    if ((state == ROB_END_BRANCH_MISS) or
+                        (state == ROB_END_LOAD_MISS))
+	              {
+                          reg_EVENT_STATE         [front_end_id][context_id] = COMMIT_EVENT_STATE_EVENT;
+//                        reg_EVENT_FLUSH         [front_end_id][context_id] = true;
+                          reg_EVENT_STOP          [front_end_id][context_id] = false; // instruction flow can continue
+//                        reg_EVENT_CAN_RESTART   [front_end_id][context_id] = false;
+                          reg_EVENT_LAST          [front_end_id][context_id] = false;
+                          // it the head !
+                          reg_EVENT_PACKET        [front_end_id][context_id] = packet_id;
+	            
+                          // If event is an load_miss, many instruction can be inserted. 
+                          // -> new last instruction
+                          if (state == ROB_END_LOAD_MISS)
+                            {
+                            reg_EVENT_CAN_RESTART   [front_end_id][context_id] = false;
+                            
+                            reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
+                            reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] = reg_NUM_PTR_TAIL;
+                            }
+                        }
+	            
+                    // Test if this instruction is the last instruction of an event
+                    //   * need event
+                    //   * packet id = last packet id
+                    if ((reg_EVENT_STATE         [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT) and
+                        (reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] == num_bank            ) and
+                        (reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] == entry->ptr          ))
+                      reg_EVENT_LAST [front_end_id][context_id] = true;
+	            
+                    // Update nb_inst
+                    reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --;
+                    if (type == TYPE_MEMORY)
+                    reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
+	            
+	            // Update pointer
+	            reg_NUM_BANK_HEAD = (num_bank+1)%_param->_nb_bank;
+                    
+	            // Remove entry
+	            delete entry;
+	            _rob [num_bank].pop_front();
+                    
+                    // Reset watch dog timer because have transaction on retire interface
+                    _nb_cycle_idle [front_end_id][context_id] = 0;
+	            
+                    // Increase stop condition
+                    if (retire_ok)
+                      _simulation_nb_instruction_commited [num_thread] ++;
+
+#ifdef STATISTICS
+	            if (usage_is_set(_usage,USE_STATISTICS))
+	              {
+	            	if (retire_ok)
+	            	  {
+	            	    (*_stat_nb_inst_retire_ok [num_thread]) ++;
+	            	    (*_stat_nb_inst_type      [type]      ) ++;
+	            	  }
+	            	else
+	            	  (*_stat_nb_inst_retire_ko [num_thread]) ++;
+	              }
+#endif
+
+#if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true)
+	            {
+	              // log file
+	              instruction_log_file [num_thread] 
+	            	<< "[" << simulation_cycle() << "] "
+	            	<< std::hex
+	            	<< (entry->address<<2) << " (" << (entry->address) << ") "
+	            	<< std::dec
+	            	<< "[" << entry->cycle_rob_in << ", " << entry->cycle_commit << "] "
+	            	<< "{" << ((retire_ok)?"OK":"KO") << "} ";
+	              
+	              if ((type == TYPE_MEMORY) and  is_operation_memory_load(entry->operation))
+	            	instruction_log_file [num_thread] << std::hex << entry->load_data << std::dec;
+	              
+	              instruction_log_file [num_thread] << std::endl;
+	            }
+#endif	    
+	          }
+	      }
+	    
+	    if (not can_continue)
+	      break; // stop scan
+	  }
+
 	// ===================================================================
 	// =====[ REEXECUTE ]=================================================
 	// ===================================================================
-	if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0]))
-	  {
-            log_printf(TRACE,Commit_unit,FUNCTION,"  * REEXECUTE         [0]");
-
-	    uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0];
-
-	    entry_t    * entry = _rob [num_bank].front();
-	    rob_state_t  state = entry->state;
-
-	    switch (state)
-	      {
-	      case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; }
-	      case ROB_STORE_HEAD_KO : {state = ROB_EVENT_WAIT_END; break; }
-	      default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));}
-	      }
-
-	    entry->state = state;
-	  }
-
+        // Test if have an reexecute instruction (an store in head of rob)
+	for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i)
+	  if (internal_REEXECUTE_VAL [i] and PORT_READ(in_REEXECUTE_ACK [i]))
+	    {
+	      log_printf(TRACE,Commit_unit,FUNCTION,"  * REEXECUTE         [%d]",i);
+	      
+	      uint32_t num_bank = internal_REEXECUTE_NUM_BANK [i];
+	      
+	      entry_t    * entry = _rob [num_bank].front();
+	      rob_state_t  state = entry->state;
+	      
+	      // Change state
+	      switch (state)
+		{
+		case ROB_STORE_OK    : {state = ROB_STORE_OK_WAIT_END; break; }
+		case ROB_STORE_KO    : {state = ROB_STORE_KO_WAIT_END; break; }
+		case ROB_STORE_EVENT : {state = ROB_EVENT_WAIT_END; break; }
+		default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));}
+		}
+	      
+	      entry->state = state;
+	    }
+	
 	// ===================================================================
 	// =====[ BRANCH_COMPLETE ]===========================================
 	// ===================================================================
 	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
+          // Test if the prediction_unit have accept the branch complete transaction
 	  if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i]))
 	    {
               log_printf(TRACE,Commit_unit,FUNCTION,"  * BRANCH_COMPLETE   [%d]",i);
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * miss_prediction : %d",PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]));
-
+
+              // Read information
 	      uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i];
 	      
@@ -516,12 +761,43 @@
 #endif
               Tcontrol_t miss = PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]);
+
+              log_printf(TRACE,Commit_unit,FUNCTION,"    * miss_prediction : %d",miss);
               
               entry->state = (miss)?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE;
-              
-              if (miss and (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0))
-                reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true;
-
-
-//               entry->state = ROB_END_OK_SPECULATIVE;
+
+//            bool flush = reg_EVENT_FLUSH [entry->front_end_id][entry->context_id];
+
+              // Branch_complete can be execute if
+              //   * no present event
+              //   * futur event and most not speculative that the event
+
+              // Also, test if in this cycle, they have not an most recently event !!!
+              if (miss)
+                {
+                  uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank);
+                      
+                  // test if this packet is before previous event
+                  if (reg_EVENT_STOP [entry->front_end_id][entry->context_id])
+                    {
+                      uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD);
+                      uint32_t _old = reg_EVENT_PACKET [entry->front_end_id][entry->context_id];
+                      uint32_t _new = packet;
+                      if (_old < _top) _old = _old+_param->_size_queue;
+                      if (_new < _top) _new = _new+_param->_size_queue;
+                      if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
+                    }
+                  else
+                    reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
+
+                  // In all case, stop instruction flow
+                  reg_EVENT_STOP          [entry->front_end_id][entry->context_id] = true;
+//                   reg_EVENT_NUM_BANK      [entry->front_end_id][entry->context_id] = num_bank;
+//                   reg_EVENT_NUM_PTR       [entry->front_end_id][entry->context_id] = entry->ptr;
+
+                  reg_EVENT_CAN_RESTART   [entry->front_end_id][entry->context_id] = false;
+
+                  reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
+                  reg_EVENT_LAST_NUM_PTR  [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL;
+                }
 	    }
 
@@ -529,8 +805,10 @@
 	// =====[ UPDATE ]====================================================
 	// ===================================================================
+        // Update when exception or load_miss
         if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK))
           {
             log_printf(TRACE,Commit_unit,FUNCTION,"  * UPDATE");
 
+            // Change state
             entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front();
 
@@ -556,5 +834,4 @@
                 }
               }
-
           }
 
@@ -578,129 +855,168 @@
 	// =====[ DEPTH - HEAD ]==============================================
 	// ===================================================================
-	for (uint32_t i=0; i<_param->_nb_bank; i++)
-	  if (not _rob[i].empty())
-	    {
-	      // Scan all instruction in windows and test if instruction is speculative
-	      entry_t    * entry        = _rob [i].front();
-	      
-	      Tcontext_t   front_end_id = entry->front_end_id;
-	      Tcontext_t   context_id   = entry->context_id  ;
-	      rob_state_t  state        = entry->state;
-	      Tdepth_t     depth        = entry->depth;
-
-              Tdepth_t     depth_min    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0;
-              Tdepth_t     depth_max    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;
-              Tcontrol_t   depth_full   = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);
+
+        {
+          bool EVENT_LAST [_param->_nb_front_end][_param->_max_nb_context];
+          for (uint32_t i=0; i<_param->_nb_front_end; i++)
+            for (uint32_t j=0; j<_param->_nb_context [i]; j++)
+              EVENT_LAST [i][j] = reg_EVENT_LAST [i][j];
+
+          // Read all instruction of all top bank
+          for (uint32_t i=0; i<_param->_nb_bank; i++)
+            {
+              uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
               
-              // is a valid instruction ?
-              // If DEPTH_CURRENT :
-              // equal at     DEPTH_MIN            -> not speculative
-              // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
-              //     include ]DEPTH_MIN:DEPTH_MAX] -> speculative
-              
-              // All case
-              // ....... min ...X... max ....... OK
-              // ....... min ....... max ...X... KO
-              // ...X... min ....... max ....... KO
-              // ....... max ....... min ...X... OK
-              // ...X... max ....... min ....... OK
-              // ....... max ...X... min ....... KO
-              
-              bool         flush         = reg_EVENT_FLUSH [front_end_id][context_id];
-              bool         speculative   = entry->speculative and not (depth == depth_min);
-              Tcontrol_t   is_valid      = ((not speculative or 
-                                             (speculative and (depth_full or // all is valid
-                                                               ((depth_min <= depth_max)? // test if depth is overflow
-                                                                ((depth >= depth_min) and (depth <=depth_max)):
-                                                                ((depth >= depth_min) or  (depth <=depth_max))))))
-                                             and not flush);
-
-//            Tcontrol_t   is_valid      = ((depth == depth_min) and not flush);
-
-              log_printf(TRACE,Commit_unit,FUNCTION,"  * HEAD              [%d]",i);
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * is_valid        : %d ((depth == depth_min) and not flush)",is_valid);
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * depth           : %d",depth    );
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_min       : %d",depth_min);
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_max       : %d",depth_max);
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_full      : %d",depth_full);
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * flush           : %d",flush);
-
-	      //------------------------------------------------------
-	      // test if instruction is miss speculative
-	      //------------------------------------------------------
-	      if (not is_valid)
-		{
-		  switch (state)
-		    {
-		    case ROB_BRANCH_WAIT_END             : {state = ROB_EVENT_WAIT_END; break;}
-		    case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS      ; break;}
-                    case ROB_END_BRANCH_MISS             :
-                    case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS      ; break;}
-                    case ROB_END_LOAD_MISS_UPDATE        :
-                    case ROB_END_LOAD_MISS               :
-                    case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_MISS      ; break;}
-		    case ROB_STORE_WAIT_HEAD_OK          : {state = ROB_STORE_HEAD_KO ; break;}
-		  //case ROB_STORE_WAIT_HEAD_KO          : {state = ; break;}
-		    case ROB_OTHER_WAIT_END              : {state = ROB_EVENT_WAIT_END; break;}
-		    case ROB_END_OK                      :
-		    case ROB_END_OK_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
-		    case ROB_END_KO                      :
-		    case ROB_END_KO_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
-		    case ROB_END_EXCEPTION_UPDATE        :
-		    case ROB_END_EXCEPTION               :
-		    case ROB_END_EXCEPTION_WAIT_HEAD     : {state = ROB_END_MISS      ; break;}
-		                                         
-		      // don't change                    
-		    case ROB_STORE_HEAD_KO               : {break;}
-		    case ROB_EVENT_WAIT_END              : {break;}
-		    case ROB_END_MISS                    : {break;}
-		                                         
-		      // can't have miss speculation     
-		    case ROB_STORE_HEAD_OK               :
-		    default                              : 
-		      {
-			throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str()));
-			break;
-		      }
-		    }
-		}
-	      
-	      //------------------------------------------------------
-	      // test if instruction is not speculative
-	      //------------------------------------------------------
-              entry->speculative = speculative;
-// 	      if (entry->depth == depth_min)
-	      if (not speculative)
-		{
-		  switch (state)
-		    {
-		    case ROB_END_OK_SPECULATIVE          : {state = ROB_END_OK                 ; break;}
-		    case ROB_END_KO_SPECULATIVE          : {state = ROB_END_KO                 ; break;}
-		    case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS        ; break;}
-		    case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_LOAD_MISS_UPDATE   ; break;}
-		    default : {break;} // else, no change
-		  }
-		}
-	      
-	      //------------------------------------------------------
-	      // test if instruction is store and head
-	      //------------------------------------------------------
-	      if (i == reg_NUM_BANK_HEAD)
-		{
-		  switch (state)
-		    {
-		    case ROB_STORE_WAIT_HEAD_OK      : {state = ROB_STORE_HEAD_OK;        break;}
-		    case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;}
-                    default : {break;} // else, no change
-		    }
-		}
-	      
-	      entry->state = state;
-	    }
-      }
-
-    // ===================================================================
-    // =====[ OTHER ]=====================================================
-    // ===================================================================
+              // Test if have an instruction
+              if (not _rob[num_bank].empty())
+                {
+                  // Scan all instruction in windows and test if instruction is speculative
+                  entry_t    * entry        = _rob [num_bank].front();
+                  
+                  Tcontext_t   front_end_id = entry->front_end_id;
+                  Tcontext_t   context_id   = entry->context_id  ;
+                  
+                  // scan while last event instruction is not retire
+                  if (EVENT_LAST [front_end_id][context_id] == false)
+                    {
+                      // Read information
+                      rob_state_t  state        = entry->state;
+                      Tdepth_t     depth        = entry->depth;
+                      
+                      Tdepth_t     depth_min    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0;
+                      Tdepth_t     depth_max    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;
+                      Tcontrol_t   depth_full   = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);
+                      
+                      // is a valid instruction ?
+                      // If DEPTH_CURRENT :
+                      // equal at     DEPTH_MIN            -> not speculative
+                      // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
+                      //     include ]DEPTH_MIN:DEPTH_MAX] -> speculative
+                      
+                      // All case
+                      // ....... min ...X... max ....... OK
+                      // ....... min ....... max ...X... KO
+                      // ...X... min ....... max ....... KO
+                      // ....... max ....... min ...X... OK
+                      // ...X... max ....... min ....... OK
+                      // ....... max ...X... min ....... KO
+                      
+                      bool         flush         = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
+                                                    (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or
+                                                    (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END));
+                      bool         speculative   = entry->speculative and not (depth == depth_min);
+                      Tcontrol_t   is_valid      = ((not speculative or 
+                                                     (speculative and (depth_full or // all is valid
+                                                                       ((depth_min <= depth_max)? // test if depth is overflow
+                                                                        ((depth >= depth_min) and (depth <=depth_max)):
+                                                                        ((depth >= depth_min) or  (depth <=depth_max))))))
+                                                    and not flush); // no event
+                      
+                      //Tcontrol_t   is_valid      = ((depth == depth_min) and not flush);
+                      
+                      log_printf(TRACE,Commit_unit,FUNCTION,"  * HEAD              [%d] - %d",num_bank,((entry->ptr << _param->_shift_num_slot) | num_bank));
+                      
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * is_valid        : %d ((depth == depth_min) and not flush)",is_valid);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * depth           : %d",depth    );
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_min       : %d",depth_min);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_max       : %d",depth_max);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_full      : %d",depth_full);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * speculative     : %d",speculative);
+                      log_printf(TRACE,Commit_unit,FUNCTION,"    * flush           : %d",flush);
+                    
+                      //------------------------------------------------------
+                      // test if instruction is miss speculative
+                      //------------------------------------------------------
+                      if (not is_valid)
+                        {
+                          // Change state
+                          switch (state)
+                            {
+                            case ROB_BRANCH_WAIT_END             : {state = ROB_EVENT_WAIT_END; break;}
+                            case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_BRANCH_MISS             :
+                            case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_LOAD_MISS_UPDATE        :
+                            case ROB_END_LOAD_MISS               :
+                            case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_MISS      ; break;}
+                            case ROB_STORE_OK                    : {state = ROB_STORE_KO      ; break;}
+                            case ROB_STORE_WAIT_END_OK           : {state = ROB_STORE_WAIT_END_KO; break;}
+			    case ROB_STORE_OK_WAIT_END           : {state = ROB_STORE_KO_WAIT_END; break;}
+                            case ROB_OTHER_WAIT_END              : {state = ROB_EVENT_WAIT_END; break;}
+                            case ROB_END_OK                      :
+                            case ROB_END_OK_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_KO                      :
+                            case ROB_END_KO_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_EXCEPTION_UPDATE        :
+                            case ROB_END_EXCEPTION               :
+                            case ROB_END_EXCEPTION_WAIT_HEAD     : {state = ROB_END_MISS      ; break;}
+                              
+                              // don't change state -> wait
+                            case ROB_STORE_WAIT_END_KO           : {break;}
+                            case ROB_STORE_KO                    : {break;}
+                            case ROB_STORE_KO_WAIT_END           : {break;}
+                            case ROB_STORE_EVENT                 : {break;}
+                            case ROB_EVENT_WAIT_END              : {break;}
+                            case ROB_END_MISS                    : {break;}
+                            case ROB_END                         : {break;}
+                              
+                              // can't have miss speculation -> invalid state
+                            default                              : 
+                              {
+                                throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str()));
+                                break;
+                              }
+                            }
+                        }
+                      
+                      //------------------------------------------------------
+                      // test if instruction is not speculative
+                      //------------------------------------------------------
+                      entry->speculative = speculative;
+//                    if (entry->depth == depth_min)
+                      // test if instruction is speculative (depth != depth_min)
+                      if (not speculative)
+                        {
+                          switch (state)
+                            {
+                            case ROB_END_OK_SPECULATIVE          : {state = ROB_END_OK                 ; break;}
+                            case ROB_END_KO_SPECULATIVE          : {state = ROB_END_KO                 ; break;}
+                            case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS        ; break;}
+                            case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_LOAD_MISS_UPDATE   ; break;}
+                            default : {break;} // else, no change
+                            }
+                        }
+                    
+                      //------------------------------------------------------
+                      // test if instruction wait head and is the top of rob
+                      //------------------------------------------------------
+                      // TODO : retire OOO
+                      if (i == 0)
+                        {
+                          switch (state)
+                            {
+//                             case ROB_STORE_WAIT_HEAD_OK      : {state = ROB_STORE_HEAD_OK;        break;}
+                            case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;}
+                            default : {break;} // else, no change
+                            }
+                        }
+                    
+                      // Write new state
+                      entry->state = state;
+                      
+                      // Test if this instruction is the last of event
+                      if ((reg_EVENT_STATE         [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT) and
+                          (reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] == num_bank            ) and
+                          (reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] == entry->ptr          ))
+                        {
+                          log_printf(TRACE,Commit_unit,FUNCTION,"  * Stop Scan !!!");
+                          
+                          EVENT_LAST [front_end_id][context_id] = true;
+                        }
+                    }
+                }
+            }
+        }
+
+
 
 #ifdef STATISTICS
@@ -709,4 +1025,9 @@
         *(_stat_bank_nb_inst [i]) += _rob[i].size();
 #endif
+      }
+
+    // ===================================================================
+    // =====[ OTHER ]=====================================================
+    // ===================================================================
 
 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true)
@@ -715,4 +1036,5 @@
       log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank_head : %d",reg_NUM_BANK_HEAD);
       log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank_tail : %d",reg_NUM_BANK_TAIL);
+      log_printf(TRACE,Commit_unit,FUNCTION,"    * num_ptr_tail  : %d",reg_NUM_PTR_TAIL );
       
       for (uint32_t i=0; i<_param->_nb_front_end; i++)
@@ -720,69 +1042,90 @@
           {
             log_printf(TRACE,Commit_unit,FUNCTION,"    * [%d][%d] - %d",i,j,_param->_translate_num_context_to_num_thread [i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STATE  : %s",toString(reg_EVENT_STATE [i][j]).c_str());
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_FLUSH  : %d",reg_EVENT_FLUSH [i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STOP   : %d",reg_EVENT_STOP  [i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_ALL  : %d",reg_NB_INST_COMMIT_ALL[i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_MEM  : %d",reg_NB_INST_COMMIT_MEM[i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * PC_CURRENT   : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * PC_NEXT      : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STATE       : %s - %s",toString(reg_EVENT_STATE [i][j]).c_str(),toString(commit_event_state_to_event_state(reg_EVENT_STATE [i][j])).c_str());
+//          log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_FLUSH       : %d",reg_EVENT_FLUSH [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STOP        : %d",reg_EVENT_STOP  [i][j]);
+//             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT             : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_PACKET      : %d",reg_EVENT_PACKET[i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_LAST        : %d",reg_EVENT_LAST [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_LAST        : %d (bank %d, ptr %d)",((reg_EVENT_LAST_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [i][j]), reg_EVENT_LAST_NUM_BANK [i][j],reg_EVENT_LAST_NUM_PTR [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_ALL       : %d",reg_NB_INST_COMMIT_ALL[i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_MEM       : %d",reg_NB_INST_COMMIT_MEM[i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * PC_CURRENT        : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * PC_NEXT           : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2);
           }
 
+      std::list<entry_t*>::iterator iter [_param->_nb_bank];
       for (uint32_t i=0; i<_param->_nb_bank; i++)
         {
           uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
-
-          log_printf(TRACE,Commit_unit,FUNCTION,"      * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]);
+//           log_printf(TRACE,Commit_unit,FUNCTION,"      * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]);
+
+          iter [num_bank] = _rob[num_bank].begin();
+        }
+
+      bool all_empty = false;
+      while (not all_empty)
+        {
+          all_empty = true;
           
-          for (std::list<entry_t*>::iterator it=_rob[num_bank].begin();
-               it!=_rob[num_bank].end();
-               it++)
+          for (uint32_t i=0; i<_param->_nb_bank; i++)
             {
-              log_printf(TRACE,Commit_unit,FUNCTION,"        [%.4d][%.4d] (%.4d) %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s",
-                         num_bank                       ,
-                         (*it)->ptr                     ,
-                         (((*it)->ptr << _param->_shift_num_slot) | num_bank),
-                         (*it)->front_end_id            ,
-                         (*it)->context_id              ,
-                         (*it)->rename_unit_id          ,
-                         (*it)->depth                   ,
-                         (*it)->type                    ,
-                         (*it)->operation               ,
-                         (*it)->is_delay_slot           ,
-                         (*it)->use_store_queue         ,
-                         (*it)->store_queue_ptr_write   ,
-                         (*it)->use_load_queue          ,
-                         (*it)->load_queue_ptr_write    ,
-                         toString((*it)->state).c_str() );
-              log_printf(TRACE,Commit_unit,FUNCTION,"                     %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ",
-                         (*it)->read_ra                 ,
-                         (*it)->num_reg_ra_log          ,
-                         (*it)->num_reg_ra_phy          ,
-                         (*it)->read_rb                 ,
-                         (*it)->num_reg_rb_log          ,
-                         (*it)->num_reg_rb_phy          ,
-                         (*it)->read_rc                 ,
-                         (*it)->num_reg_rc_log          ,
-                         (*it)->num_reg_rc_phy          ,
-                         (*it)->write_rd                ,
-                         (*it)->num_reg_rd_log          ,
-                         (*it)->num_reg_rd_phy_old      ,
-                         (*it)->num_reg_rd_phy_new      ,
-                         (*it)->write_re                ,
-                         (*it)->num_reg_re_log          ,
-                         (*it)->num_reg_re_phy_old      ,
-                         (*it)->num_reg_re_phy_new      );
-              
-              log_printf(TRACE,Commit_unit,FUNCTION,"                     %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)",
-                         (*it)->exception_use ,
-                         (*it)->exception     ,
-                         (*it)->flags         ,
-                         (*it)->no_sequence   ,
-                         (*it)->speculative   ,
-                         (*it)->address       ,
-                         (*it)->address<<2    ,
-                         (*it)->address_next  ,
-                         (*it)->address_next<<2
-                         );
+              uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
+      
+              std::list<entry_t*>::iterator it = iter[num_bank];        
+              if (it != _rob[num_bank].end())
+                {
+                  all_empty = false;
+
+                  log_printf(TRACE,Commit_unit,FUNCTION,"        [%.4d][%.4d] (%.4d) %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s",
+                             num_bank                       ,
+                             (*it)->ptr                     ,
+                             (((*it)->ptr << _param->_shift_num_slot) | num_bank),
+                             (*it)->front_end_id            ,
+                             (*it)->context_id              ,
+                             (*it)->rename_unit_id          ,
+                             (*it)->depth                   ,
+                             (*it)->type                    ,
+                             (*it)->operation               ,
+                             (*it)->is_delay_slot           ,
+                             (*it)->use_store_queue         ,
+                             (*it)->store_queue_ptr_write   ,
+                             (*it)->use_load_queue          ,
+                             (*it)->load_queue_ptr_write    ,
+                             toString((*it)->state).c_str() );
+                  log_printf(TRACE,Commit_unit,FUNCTION,"                     %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ",
+                             (*it)->read_ra                 ,
+                             (*it)->num_reg_ra_log          ,
+                             (*it)->num_reg_ra_phy          ,
+                             (*it)->read_rb                 ,
+                             (*it)->num_reg_rb_log          ,
+                             (*it)->num_reg_rb_phy          ,
+                             (*it)->read_rc                 ,
+                             (*it)->num_reg_rc_log          ,
+                             (*it)->num_reg_rc_phy          ,
+                             (*it)->write_rd                ,
+                             (*it)->num_reg_rd_log          ,
+                             (*it)->num_reg_rd_phy_old      ,
+                             (*it)->num_reg_rd_phy_new      ,
+                             (*it)->write_re                ,
+                             (*it)->num_reg_re_log          ,
+                             (*it)->num_reg_re_phy_old      ,
+                             (*it)->num_reg_re_phy_new      );
+                  
+                  log_printf(TRACE,Commit_unit,FUNCTION,"                     %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)",
+                             (*it)->exception_use ,
+                             (*it)->exception     ,
+                             (*it)->flags         ,
+                             (*it)->no_sequence   ,
+                             (*it)->speculative   ,
+                             (*it)->address       ,
+                             (*it)->address<<2    ,
+                             (*it)->address_next  ,
+                             (*it)->address_next<<2
+                             );
+                  
+                  iter [num_bank] ++;
+                }
             }
         }
@@ -822,5 +1165,5 @@
               )
           if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id])
-            throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (%x) is different of reg_PC_CURRENT[%d][%d] (%x).\n"),
+            throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (0x%x) is different of reg_PC_CURRENT[%d][%d] (0x%x).\n"),
                                                  entry->address,
                                                  entry->front_end_id,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp	(revision 122)
@@ -40,6 +40,6 @@
       test.error(_("nb_bank must be a multiple of size_queue.\n"));
 
-    if (_nb_inst_reexecute != 1)
-      test.error(_("nb_inst_reexecute must be set at 1. Anothers value is unsupported.\n"));
+//     if (_nb_inst_reexecute != 1)
+//       test.error(_("nb_inst_reexecute must be set at 1. Anothers value is unsupported.\n"));
 
     for (uint32_t i=0; i<_nb_front_end; ++i)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h	(revision 122)
@@ -77,4 +77,6 @@
   public    : SC_IN (Ttype_t           )  ***  in_ISSUE_IN_TYPE                  ;//[nb_rename_unit][nb_inst_rename]
   public    : SC_IN (Tlsq_ptr_t        )  ***  in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_rename]
+  public    : SC_IN (Tlsq_ptr_t        )  ***  in_ISSUE_IN_STORE_QUEUE_PTR_READ  ;//[nb_rename_unit][nb_inst_rename]
+  public    : SC_IN (Tcontrol_t        )  ***  in_ISSUE_IN_STORE_QUEUE_EMPTY     ;//[nb_rename_unit][nb_inst_rename]
   public    : SC_IN (Tlsq_ptr_t        )  ***  in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE  ;//[nb_rename_unit][nb_inst_rename]
   public    : SC_IN (Tcontrol_t        )  ***  in_ISSUE_IN_HAS_IMMEDIAT          ;//[nb_rename_unit][nb_inst_rename]
@@ -100,4 +102,6 @@
   public    : SC_IN (Ttype_t           )   **  in_REEXECUTE_TYPE                 ;//[nb_inst_reexecute]
   public    : SC_IN (Tlsq_ptr_t        )   **  in_REEXECUTE_STORE_QUEUE_PTR_WRITE;//[nb_inst_reexecute]
+  public    : SC_IN (Tlsq_ptr_t        )   **  in_REEXECUTE_STORE_QUEUE_PTR_READ ;//[nb_inst_reexecute]
+  public    : SC_IN (Tcontrol_t        )   **  in_REEXECUTE_STORE_QUEUE_EMPTY    ;//[nb_inst_reexecute]
   public    : SC_IN (Tlsq_ptr_t        )   **  in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_reexecute]
   public    : SC_IN (Tcontrol_t        )   **  in_REEXECUTE_HAS_IMMEDIAT         ;//[nb_inst_reexecute]
@@ -123,4 +127,6 @@
   public    : SC_OUT(Ttype_t           )   ** out_ISSUE_OUT_TYPE                 ;//[nb_inst_issue]
   public    : SC_OUT(Tlsq_ptr_t        )   ** out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE;//[nb_inst_issue]
+  public    : SC_OUT(Tlsq_ptr_t        )   ** out_ISSUE_OUT_STORE_QUEUE_PTR_READ ;//[nb_inst_issue]
+  public    : SC_OUT(Tcontrol_t        )   ** out_ISSUE_OUT_STORE_QUEUE_EMPTY    ;//[nb_inst_issue]
   public    : SC_OUT(Tlsq_ptr_t        )   ** out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_issue]
   public    : SC_OUT(Tcontrol_t        )   ** out_ISSUE_OUT_HAS_IMMEDIAT         ;//[nb_inst_issue]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Types.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Types.h	(revision 122)
@@ -33,4 +33,6 @@
   public : Ttype_t            _type                  ;
   public : Tlsq_ptr_t         _store_queue_ptr_write ;
+  public : Tlsq_ptr_t         _store_queue_ptr_read  ;
+  public : Tcontrol_t         _store_queue_empty     ;
   public : Tlsq_ptr_t         _load_queue_ptr_write  ;
   public : Tcontrol_t         _has_immediat          ;
@@ -53,4 +55,6 @@
 		    Ttype_t            type                  ,
 		    Tlsq_ptr_t         store_queue_ptr_write ,
+		    Tlsq_ptr_t         store_queue_ptr_read  ,
+		    Tcontrol_t         store_queue_empty     ,
 		    Tlsq_ptr_t         load_queue_ptr_write  ,
 		    Tcontrol_t         has_immediat          ,
@@ -73,4 +77,6 @@
       _type                  = type                 ;
       _store_queue_ptr_write = store_queue_ptr_write;
+      _store_queue_ptr_read  = store_queue_ptr_read ;
+      _store_queue_empty     = store_queue_empty    ;
       _load_queue_ptr_write  = load_queue_ptr_write ;
       _has_immediat          = has_immediat         ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp	(revision 122)
@@ -69,4 +69,6 @@
       _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type            ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
       _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
+      _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
+      _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1                             ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
       _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr  ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
       _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                             ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
@@ -98,4 +100,6 @@
       ALLOC1_SIGNAL_IN ( in_REEXECUTE_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type            );
       ALLOC1_SIGNAL_IN ( in_REEXECUTE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr );
+      ALLOC1_SIGNAL_IN ( in_REEXECUTE_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr );
+      ALLOC1_SIGNAL_IN ( in_REEXECUTE_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1);
       ALLOC1_SIGNAL_IN ( in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr  );
       ALLOC1_SIGNAL_IN ( in_REEXECUTE_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                             );
@@ -127,4 +131,6 @@
       ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type            );
       ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr );
+      ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr );
+      ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1);
       ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr  );
       ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                             );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp	(revision 122)
@@ -36,4 +36,6 @@
 	DELETE2_SIGNAL( in_ISSUE_IN_TYPE                 ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_type            );
 	DELETE2_SIGNAL( in_ISSUE_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_store_queue_ptr );
+	DELETE2_SIGNAL( in_ISSUE_IN_STORE_QUEUE_PTR_READ ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_store_queue_ptr );
+	DELETE2_SIGNAL( in_ISSUE_IN_STORE_QUEUE_EMPTY    ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],1);
 	DELETE2_SIGNAL( in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_load_queue_ptr  );
 	DELETE2_SIGNAL( in_ISSUE_IN_HAS_IMMEDIAT         ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],1                             );
@@ -58,4 +60,6 @@
         DELETE1_SIGNAL( in_REEXECUTE_TYPE                 ,_param->_nb_inst_reexecute,_param->_size_type            );
         DELETE1_SIGNAL( in_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute,_param->_size_store_queue_ptr );
+        DELETE1_SIGNAL( in_REEXECUTE_STORE_QUEUE_PTR_READ ,_param->_nb_inst_reexecute,_param->_size_store_queue_ptr );
+        DELETE1_SIGNAL( in_REEXECUTE_STORE_QUEUE_EMPTY    ,_param->_nb_inst_reexecute,1);
         DELETE1_SIGNAL( in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute,_param->_size_load_queue_ptr  );
         DELETE1_SIGNAL( in_REEXECUTE_HAS_IMMEDIAT         ,_param->_nb_inst_reexecute,1                             );
@@ -80,4 +84,6 @@
         DELETE1_SIGNAL(out_ISSUE_OUT_TYPE                 ,_param->_nb_inst_issue,_param->_size_type            );
         DELETE1_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_issue,_param->_size_store_queue_ptr );
+        DELETE1_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_PTR_READ ,_param->_nb_inst_issue,_param->_size_store_queue_ptr );
+        DELETE1_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_EMPTY    ,_param->_nb_inst_issue,1);
         DELETE1_SIGNAL(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_issue,_param->_size_load_queue_ptr  );
         DELETE1_SIGNAL(out_ISSUE_OUT_HAS_IMMEDIAT         ,_param->_nb_inst_issue,1                             );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_genMealy_issue_out.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_genMealy_issue_out.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_genMealy_issue_out.cpp	(revision 122)
@@ -57,4 +57,6 @@
 	  PORT_WRITE(out_ISSUE_OUT_TYPE                  [index], entry->_type                 );
 	  PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [index], entry->_store_queue_ptr_write);
+	  PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_READ  [index], entry->_store_queue_ptr_read );
+	  PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_EMPTY     [index], entry->_store_queue_empty    );
 	  if (_param->_have_port_load_queue_ptr)
 	  PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE  [index], entry->_load_queue_ptr_write );
@@ -130,4 +132,6 @@
               PORT_WRITE(out_ISSUE_OUT_TYPE                  [index], entry->_type                 );
               PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [index], entry->_store_queue_ptr_write);
+              PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_READ  [index], entry->_store_queue_ptr_read );
+              PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_EMPTY     [index], entry->_store_queue_empty    );
               if (_param->_have_port_load_queue_ptr)
               PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE  [index], entry->_load_queue_ptr_write );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_transition.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_transition.cpp	(revision 122)
@@ -66,4 +66,6 @@
 		                                         PORT_READ(in_ISSUE_IN_TYPE                  [i][j]),
 		                                         PORT_READ(in_ISSUE_IN_STORE_QUEUE_PTR_WRITE [i][j]),
+		                                         PORT_READ(in_ISSUE_IN_STORE_QUEUE_PTR_READ  [i][j]),
+		                                         PORT_READ(in_ISSUE_IN_STORE_QUEUE_EMPTY     [i][j]),
                      (_param->_have_port_load_queue_ptr)?PORT_READ(in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE  [i][j]):0,
 		                                         PORT_READ(in_ISSUE_IN_HAS_IMMEDIAT          [i][j]),
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_genMoore.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_genMoore.cpp	(revision 122)
@@ -125,4 +125,6 @@
 	        PORT_WRITE(out_ISSUE_OUT_TYPE                  [i], entry->_type                 );
 	        PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [i], entry->_store_queue_ptr_write);
+	        PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_READ  [i], entry->_store_queue_ptr_read );
+	        PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_EMPTY     [i], entry->_store_queue_empty    );
 	        if (_param->_have_port_load_queue_ptr)
 	        PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE  [i], entry->_load_queue_ptr_write );
@@ -186,4 +188,6 @@
 	            PORT_WRITE(out_ISSUE_OUT_TYPE                  [i], entry->_type                 );
 	            PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [i], entry->_store_queue_ptr_write);
+	            PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_READ  [i], entry->_store_queue_ptr_read );
+	            PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_EMPTY     [i], entry->_store_queue_empty    );
 	            if (_param->_have_port_load_queue_ptr)
 	            PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE  [i], entry->_load_queue_ptr_write );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_transition.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_transition.cpp	(revision 122)
@@ -65,4 +65,6 @@
 			                                 PORT_READ(in_ISSUE_IN_TYPE                  [x][y]),
 			                                 PORT_READ(in_ISSUE_IN_STORE_QUEUE_PTR_WRITE [x][y]),
+			                                 PORT_READ(in_ISSUE_IN_STORE_QUEUE_PTR_READ  [x][y]),
+			                                 PORT_READ(in_ISSUE_IN_STORE_QUEUE_EMPTY     [x][y]),
                      (_param->_have_port_load_queue_ptr)?PORT_READ(in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE  [x][y]):0,
 			                                 PORT_READ(in_ISSUE_IN_HAS_IMMEDIAT          [x][y]),
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_transition.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_transition.cpp	(revision 122)
@@ -53,4 +53,6 @@
 			                             PORT_READ(in_REEXECUTE_TYPE                  [i]),
 			                             PORT_READ(in_REEXECUTE_STORE_QUEUE_PTR_WRITE [i]),
+			                             PORT_READ(in_REEXECUTE_STORE_QUEUE_PTR_READ  [i]),
+			                             PORT_READ(in_REEXECUTE_STORE_QUEUE_EMPTY     [i]),
                  (_param->_have_port_load_queue_ptr)?PORT_READ(in_REEXECUTE_LOAD_QUEUE_PTR_WRITE  [i]):0,
 			                             PORT_READ(in_REEXECUTE_HAS_IMMEDIAT          [i]),
@@ -119,5 +121,5 @@
         for (std::list<entry_t*>::iterator it=_issue_queue[i].begin();it!=_issue_queue[i].end(); ++it)
           {
-            log_printf(TRACE,Issue_queue,FUNCTION,"      [%.4d] %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d",
+            log_printf(TRACE,Issue_queue,FUNCTION,"      [%.4d] %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d",
                        j,
                        
@@ -130,4 +132,6 @@
                        
                        (*it)->_store_queue_ptr_write,
+                       (*it)->_store_queue_ptr_read ,
+                       (*it)->_store_queue_empty    ,
                        (*it)->_load_queue_ptr_write ,
                        
@@ -161,5 +165,5 @@
       for (std::list<entry_t*>::iterator it=_reexecute_queue.begin();it!=_reexecute_queue.end(); ++it)
         {
-          log_printf(TRACE,Issue_queue,FUNCTION,"      [%.4d] %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d",
+          log_printf(TRACE,Issue_queue,FUNCTION,"      [%.4d] %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d",
                      i,
                      
@@ -172,4 +176,6 @@
                      
                      (*it)->_store_queue_ptr_write,
+                     (*it)->_store_queue_ptr_read ,
+                     (*it)->_store_queue_empty    ,
                      (*it)->_load_queue_ptr_write ,
                      
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h	(revision 122)
@@ -90,4 +90,6 @@
   public    : SC_IN (Tgeneral_data_t    ) ***  in_INSERT_RENAME_UNIT_IMMEDIAT                  ;//[nb_rename_unit][nb_inst_insert]
   public    : SC_IN (Tlsq_ptr_t         ) ***  in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE     ;//[nb_rename_unit][nb_inst_insert]
+  public    : SC_IN (Tlsq_ptr_t         ) ***  in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ      ;//[nb_rename_unit][nb_inst_insert]
+  public    : SC_IN (Tcontrol_t         ) ***  in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY         ;//[nb_rename_unit][nb_inst_insert]
   public    : SC_IN (Tlsq_ptr_t         ) ***  in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE      ;//[nb_rename_unit][nb_inst_insert]
   public    : SC_IN (Tcontrol_t         ) ***  in_INSERT_RENAME_UNIT_READ_RA                   ;//[nb_rename_unit][nb_inst_insert]
@@ -136,4 +138,6 @@
   public    : SC_OUT(Ttype_t            ) *** out_INSERT_ISSUE_QUEUE_TYPE                      ;//[nb_rename_unit][nb_inst_insert]
   public    : SC_OUT(Tlsq_ptr_t         ) *** out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE     ;//[nb_rename_unit][nb_inst_insert]
+  public    : SC_OUT(Tlsq_ptr_t         ) *** out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ      ;//[nb_rename_unit][nb_inst_insert]
+  public    : SC_OUT(Tcontrol_t         ) *** out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY         ;//[nb_rename_unit][nb_inst_insert]
   public    : SC_OUT(Tlsq_ptr_t         ) *** out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE      ;//[nb_rename_unit][nb_inst_insert]
   public    : SC_OUT(Tcontrol_t         ) *** out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT              ;//[nb_rename_unit][nb_inst_insert]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue.cpp	(revision 122)
@@ -152,4 +152,6 @@
                         << (*(in_INSERT_RENAME_UNIT_IMMEDIAT              [i][j]))
                         << (*(in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE [i][j]))
+                        << (*(in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ  [i][j]))
+                        << (*(in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY     [i][j]))
                         << (*(in_INSERT_RENAME_UNIT_READ_RA               [i][j]))
                         << (*(in_INSERT_RENAME_UNIT_NUM_REG_RA_PHY        [i][j]))
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp	(revision 122)
@@ -93,4 +93,6 @@
       _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_IMMEDIAT                  ,"RENAME_UNIT_IMMEDIAT"                  ,Tgeneral_data_t    ,_param->_size_general_data    ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
       _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE     ,"RENAME_UNIT_STORE_QUEUE_PTR_WRITE"     ,Tlsq_ptr_t         ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ      ,"RENAME_UNIT_STORE_QUEUE_PTR_READ"      ,Tlsq_ptr_t         ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY         ,"RENAME_UNIT_STORE_QUEUE_EMPTY"         ,Tcontrol_t         ,1                             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
       _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE      ,"RENAME_UNIT_LOAD_QUEUE_PTR_WRITE"      ,Tlsq_ptr_t         ,_param->_size_load_queue_ptr  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
       _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_READ_RA                   ,"RENAME_UNIT_READ_RA"                   ,Tcontrol_t         ,1                             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -139,4 +141,6 @@
       _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_TYPE                      ,"ISSUE_QUEUE_TYPE"                      ,Ttype_t            ,_param->_size_type            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
       _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE     ,"ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE"     ,Tlsq_ptr_t         ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ      ,"ISSUE_QUEUE_STORE_QUEUE_PTR_READ"      ,Tlsq_ptr_t         ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY         ,"ISSUE_QUEUE_STORE_QUEUE_EMPTY"         ,Tcontrol_t         ,1                             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
       _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE      ,"ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE"      ,Tlsq_ptr_t         ,_param->_size_load_queue_ptr  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
       _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT              ,"ISSUE_QUEUE_HAS_IMMEDIAT"              ,Tcontrol_t         ,1                             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_deallocation.cpp	(revision 122)
@@ -48,4 +48,6 @@
         DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_IMMEDIAT                  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_data    );
         DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr );
+        DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr );
+        DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                             );
         DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr  );
         DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_READ_RA                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                             );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert.cpp	(revision 122)
@@ -36,4 +36,6 @@
           Tgeneral_data_t    IMMEDIAT              = PORT_READ(in_INSERT_RENAME_UNIT_IMMEDIAT              [i][j]);
           Tlsq_ptr_t         STORE_QUEUE_PTR_WRITE = PORT_READ(in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE [i][j]);
+          Tlsq_ptr_t         STORE_QUEUE_PTR_READ  = PORT_READ(in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ  [i][j]);
+          Tcontrol_t         STORE_QUEUE_EMPTY     = PORT_READ(in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY     [i][j]);
           Tlsq_ptr_t         LOAD_QUEUE_PTR_WRITE  = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE [i][j]):0;
           Tcontrol_t         READ_RA               = PORT_READ(in_INSERT_RENAME_UNIT_READ_RA               [i][j]);
@@ -91,4 +93,6 @@
           PORT_WRITE(out_INSERT_ISSUE_QUEUE_OPERATION             [i][j],OPERATION            );
           PORT_WRITE(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE [i][j],STORE_QUEUE_PTR_WRITE);
+          PORT_WRITE(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ  [i][j],STORE_QUEUE_PTR_READ );
+          PORT_WRITE(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY     [i][j],STORE_QUEUE_EMPTY    );
           if (_param->_have_port_load_queue_ptr)
           PORT_WRITE(out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE  [i][j],LOAD_QUEUE_PTR_WRITE );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h	(revision 122)
@@ -129,4 +129,6 @@
   public    : SC_OUT(Ttype_t            )  ** out_REEXECUTE_TYPE                       ;//[nb_inst_reexecute]
   public    : SC_OUT(Tlsq_ptr_t         )  ** out_REEXECUTE_STORE_QUEUE_PTR_WRITE      ;//[nb_inst_reexecute]
+  public    : SC_OUT(Tlsq_ptr_t         )  ** out_REEXECUTE_STORE_QUEUE_PTR_READ       ;//[nb_inst_reexecute] //*
+  public    : SC_OUT(Tcontrol_t         )  ** out_REEXECUTE_STORE_QUEUE_EMPTY          ;//[nb_inst_reexecute] //*
   public    : SC_OUT(Tlsq_ptr_t         )  ** out_REEXECUTE_LOAD_QUEUE_PTR_WRITE       ;//[nb_inst_reexecute] //*
   public    : SC_OUT(Tcontrol_t         )  ** out_REEXECUTE_HAS_IMMEDIAT               ;//[nb_inst_reexecute]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp	(revision 122)
@@ -143,4 +143,6 @@
       ALLOC1_SIGNAL_OUT(out_REEXECUTE_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type            );
       ALLOC1_SIGNAL_OUT(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr );
+      ALLOC1_SIGNAL_OUT(out_REEXECUTE_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr );
+      ALLOC1_SIGNAL_OUT(out_REEXECUTE_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1);
       ALLOC1_SIGNAL_OUT(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr  );
       ALLOC1_SIGNAL_OUT(out_REEXECUTE_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                             );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_deallocation.cpp	(revision 122)
@@ -83,4 +83,6 @@
         DELETE1_SIGNAL(out_REEXECUTE_TYPE                       , _param->_nb_inst_reexecute,_param->_size_type               );
         DELETE1_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE      , _param->_nb_inst_reexecute,_param->_size_store_queue_ptr    );
+        DELETE1_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_READ       , _param->_nb_inst_reexecute,_param->_size_store_queue_ptr    );
+        DELETE1_SIGNAL(out_REEXECUTE_STORE_QUEUE_EMPTY          , _param->_nb_inst_reexecute,1);
         DELETE1_SIGNAL(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE       , _param->_nb_inst_reexecute,_param->_size_load_queue_ptr     );
         DELETE1_SIGNAL(out_REEXECUTE_HAS_IMMEDIAT               , _param->_nb_inst_reexecute,1                                );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp	(revision 122)
@@ -56,4 +56,6 @@
 	    PORT_WRITE(out_REEXECUTE_TYPE                  [i],entry->type          );
 	    PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_WRITE [i],0);
+// 	    PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_READ  [i], 0);
+// 	    PORT_WRITE(out_REEXECUTE_STORE_QUEUE_EMPTY     [i], 0);
 	    PORT_WRITE(out_REEXECUTE_HAS_IMMEDIAT          [i],1);
 	    PORT_WRITE(out_REEXECUTE_IMMEDIAT              [i],entry->data          );
@@ -82,4 +84,6 @@
 	    PORT_WRITE(out_REEXECUTE_TYPE                  [i], PORT_READ(in_REEXECUTE_ROB_TYPE                    [i]));
 	    PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_WRITE [i], PORT_READ(in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE   [i]));
+// 	    PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_READ  [i], 0);
+// 	    PORT_WRITE(out_REEXECUTE_STORE_QUEUE_EMPTY     [i], 0);
 	    PORT_WRITE(out_REEXECUTE_HAS_IMMEDIAT          [i], 0);
 	    PORT_WRITE(out_REEXECUTE_IMMEDIAT              [i], 0);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h	(revision 122)
@@ -70,4 +70,6 @@
   public    : SC_IN (Toperation_t   )      **  in_INSERT_OPERATION            ; // [nb_inst_insert]
   public    : SC_OUT(Tlsq_ptr_t     )      ** out_INSERT_STORE_QUEUE_PTR_WRITE; // [nb_inst_insert]
+  public    : SC_OUT(Tlsq_ptr_t     )      ** out_INSERT_STORE_QUEUE_PTR_READ ; // [nb_inst_insert]
+  public    : SC_OUT(Tcontrol_t     )      ** out_INSERT_STORE_QUEUE_EMPTY    ; // [nb_inst_insert]
   public    : SC_OUT(Tlsq_ptr_t     )      ** out_INSERT_LOAD_QUEUE_PTR_WRITE ; // [nb_inst_insert]
 
@@ -84,23 +86,31 @@
   public    : SC_IN (Tlsq_ptr_t     )      **  in_RETIRE_LOAD_QUEUE_PTR_WRITE ; // [nb_inst_retire]
 
+    // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_VAL            ;//[nb_front_end][nb_context]
+  public    : SC_OUT(Tcontrol_t        )  *** out_RETIRE_EVENT_ACK            ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tevent_state_t    )  ***  in_RETIRE_EVENT_STATE          ;//[nb_front_end][nb_context]
+
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-  public    : Tlsq_ptr_t                     * reg_STORE_QUEUE_PTR_WRITE; // [nb_load_store_queue]
-  public    : bool                          ** reg_STORE_QUEUE_USE      ; // [nb_load_store_queue][size_store_queue]
-  public    : Tlsq_ptr_t                     * reg_STORE_QUEUE_NB_USE   ; // [nb_load_store_queue]
-  public    : Tlsq_ptr_t                     * reg_LOAD_QUEUE_PTR_WRITE ; // [nb_load_store_queue]
-  public    : bool                          ** reg_LOAD_QUEUE_USE       ; // [nb_load_store_queue][size_load_queue]
+  private   : Tlsq_ptr_t                     * reg_STORE_QUEUE_PTR_WRITE; // [nb_load_store_queue]
+  private   : Tlsq_ptr_t                    ** reg_STORE_QUEUE_PTR_READ ; // [nb_front_end][nb_context]
+  private   : bool                          ** reg_STORE_QUEUE_EMPTY    ; // [nb_front_end][nb_context]
+  private   : bool                          ** reg_STORE_QUEUE_USE      ; // [nb_load_store_queue][size_store_queue]
+  private   : Tlsq_ptr_t                     * reg_STORE_QUEUE_NB_USE   ; // [nb_load_store_queue]
+  private   : Tlsq_ptr_t                     * reg_LOAD_QUEUE_PTR_WRITE ; // [nb_load_store_queue]
+  private   : bool                          ** reg_LOAD_QUEUE_USE       ; // [nb_load_store_queue][size_load_queue]
 
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-  public    : Tcontrol_t                     * internal_INSERT_ACK          ; // [nb_inst_insert]
-  public    : operation_use_t                * internal_INSERT_OPERATION_USE; // [nb_inst_insert]
-  public    : uint32_t                       * internal_INSERT_LSQ          ; // [nb_inst_insert]
-  public    : Tlsq_ptr_t                     * internal_INSERT_PTR          ; // [nb_inst_insert]
+  private   : Tcontrol_t                     * internal_INSERT_ACK          ; // [nb_inst_insert]
+  private   : operation_use_t                * internal_INSERT_OPERATION_USE; // [nb_inst_insert]
+  private   : uint32_t                       * internal_INSERT_LSQ          ; // [nb_inst_insert]
+  private   : Tlsq_ptr_t                     * internal_INSERT_PTR          ; // [nb_inst_insert]
 
-  public    : Tcontrol_t                     * internal_RETIRE_ACK          ; // [nb_inst_retire]
-  public    : operation_use_t                * internal_RETIRE_OPERATION_USE; // [nb_inst_retire]
-  public    : uint32_t                       * internal_RETIRE_LSQ          ; // [nb_inst_retire]
-  public    : Tlsq_ptr_t                     * internal_RETIRE_PTR          ; // [nb_inst_retire]
+  private   : Tcontrol_t                     * internal_RETIRE_ACK          ; // [nb_inst_retire]
+  private   : operation_use_t                * internal_RETIRE_OPERATION_USE; // [nb_inst_retire]
+  private   : uint32_t                       * internal_RETIRE_LSQ          ; // [nb_inst_retire]
+  private   : Tlsq_ptr_t                     * internal_RETIRE_PTR          ; // [nb_inst_retire]
+  private   : Tcontrol_t                    ** internal_RETIRE_EVENT_ACK    ;//[nb_front_end][nb_context]
 
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit.cpp	(revision 122)
@@ -74,4 +74,14 @@
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
+
+	// Constant : accepted already transaction
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            {
+              internal_RETIRE_EVENT_ACK [i][j] = 1;
+              
+              PORT_WRITE(out_RETIRE_EVENT_ACK[i][j],internal_RETIRE_EVENT_ACK [i][j]);
+            }
+
 	log_printf(INFO,Load_Store_pointer_unit,FUNCTION,"Method - transition");
 
@@ -101,34 +111,34 @@
 
 # ifdef SYSTEMCASS_SPECIFIC
-	// List dependency information
-	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
-	  {
-	    (*(out_INSERT_ACK                   [i])) (*( in_INSERT_VAL                   [i]));
-	    if (_param->_have_port_front_end_id)
-	    (*(out_INSERT_ACK                   [i])) (*( in_INSERT_FRONT_END_ID          [i]));
-	    if (_param->_have_port_context_id)
-	    (*(out_INSERT_ACK                   [i])) (*( in_INSERT_CONTEXT_ID            [i]));
-	    (*(out_INSERT_ACK                   [i])) (*( in_INSERT_TYPE                  [i]));
-	    (*(out_INSERT_ACK                   [i])) (*( in_INSERT_OPERATION             [i]));
+// 	// List dependency information
+// 	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+// 	  {
+// 	    (*(out_INSERT_ACK                   [i])) (*( in_INSERT_VAL                   [i]));
+// 	    if (_param->_have_port_front_end_id)
+// 	    (*(out_INSERT_ACK                   [i])) (*( in_INSERT_FRONT_END_ID          [i]));
+// 	    if (_param->_have_port_context_id)
+// 	    (*(out_INSERT_ACK                   [i])) (*( in_INSERT_CONTEXT_ID            [i]));
+// 	    (*(out_INSERT_ACK                   [i])) (*( in_INSERT_TYPE                  [i]));
+// 	    (*(out_INSERT_ACK                   [i])) (*( in_INSERT_OPERATION             [i]));
   
-	    (*(out_INSERT_STORE_QUEUE_PTR_WRITE [i])) (*( in_INSERT_VAL                   [i]));
-	    if (_param->_have_port_front_end_id)
-	    (*(out_INSERT_STORE_QUEUE_PTR_WRITE [i])) (*( in_INSERT_FRONT_END_ID          [i]));
-	    if (_param->_have_port_context_id)
-	    (*(out_INSERT_STORE_QUEUE_PTR_WRITE [i])) (*( in_INSERT_CONTEXT_ID            [i]));
-	    (*(out_INSERT_STORE_QUEUE_PTR_WRITE [i])) (*( in_INSERT_TYPE                  [i]));
-	    (*(out_INSERT_STORE_QUEUE_PTR_WRITE [i])) (*( in_INSERT_OPERATION             [i]));
+// 	    (*(out_INSERT_STORE_QUEUE_PTR_WRITE [i])) (*( in_INSERT_VAL                   [i]));
+// 	    if (_param->_have_port_front_end_id)
+// 	    (*(out_INSERT_STORE_QUEUE_PTR_WRITE [i])) (*( in_INSERT_FRONT_END_ID          [i]));
+// 	    if (_param->_have_port_context_id)
+// 	    (*(out_INSERT_STORE_QUEUE_PTR_WRITE [i])) (*( in_INSERT_CONTEXT_ID            [i]));
+// 	    (*(out_INSERT_STORE_QUEUE_PTR_WRITE [i])) (*( in_INSERT_TYPE                  [i]));
+// 	    (*(out_INSERT_STORE_QUEUE_PTR_WRITE [i])) (*( in_INSERT_OPERATION             [i]));
   
-	    if (_param->_have_port_load_queue_ptr)
-	      {
-	    (*(out_INSERT_LOAD_QUEUE_PTR_WRITE  [i])) (*( in_INSERT_VAL                   [i]));
-	    if (_param->_have_port_front_end_id)
-	    (*(out_INSERT_LOAD_QUEUE_PTR_WRITE  [i])) (*( in_INSERT_FRONT_END_ID          [i]));
-	    if (_param->_have_port_context_id)
-	    (*(out_INSERT_LOAD_QUEUE_PTR_WRITE  [i])) (*( in_INSERT_CONTEXT_ID            [i]));
-	    (*(out_INSERT_LOAD_QUEUE_PTR_WRITE  [i])) (*( in_INSERT_TYPE                  [i]));
-	    (*(out_INSERT_LOAD_QUEUE_PTR_WRITE  [i])) (*( in_INSERT_OPERATION             [i]));
-	      }
-	  }
+// 	    if (_param->_have_port_load_queue_ptr)
+// 	      {
+// 	    (*(out_INSERT_LOAD_QUEUE_PTR_WRITE  [i])) (*( in_INSERT_VAL                   [i]));
+// 	    if (_param->_have_port_front_end_id)
+// 	    (*(out_INSERT_LOAD_QUEUE_PTR_WRITE  [i])) (*( in_INSERT_FRONT_END_ID          [i]));
+// 	    if (_param->_have_port_context_id)
+// 	    (*(out_INSERT_LOAD_QUEUE_PTR_WRITE  [i])) (*( in_INSERT_CONTEXT_ID            [i]));
+// 	    (*(out_INSERT_LOAD_QUEUE_PTR_WRITE  [i])) (*( in_INSERT_TYPE                  [i]));
+// 	    (*(out_INSERT_LOAD_QUEUE_PTR_WRITE  [i])) (*( in_INSERT_OPERATION             [i]));
+// 	      }
+// 	  }
 # endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp	(revision 122)
@@ -67,4 +67,6 @@
       ALLOC1_SIGNAL_IN ( in_INSERT_OPERATION            ,"operation"            ,Toperation_t,_param->_size_operation      );
       ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t  ,_param->_size_store_queue_ptr);
+      ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t  ,_param->_size_store_queue_ptr);
+      ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t  ,1                            );
       ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t  ,_param->_size_load_queue_ptr );
 
@@ -80,6 +82,6 @@
       ALLOC1_SIGNAL_IN ( in_RETIRE_FRONT_END_ID         ,"front_end_id"         ,Tcontext_t  ,_param->_size_front_end_id   );
       ALLOC1_SIGNAL_IN ( in_RETIRE_CONTEXT_ID           ,"context_id"           ,Tcontext_t  ,_param->_size_context_id     );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_TYPE                 ,"type"                 ,Ttype_t     ,_param->_size_type           );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_OPERATION            ,"operation"            ,Toperation_t,_param->_size_operation      );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_TYPE                 ,"type"                 ,Ttype_t     ,_param->_size_type           );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_OPERATION            ,"operation"            ,Toperation_t,_param->_size_operation      );
       ALLOC1_SIGNAL_IN ( in_RETIRE_USE_STORE_QUEUE      ,"use_store_queue"      ,Tcontrol_t  ,1);
       ALLOC1_SIGNAL_IN ( in_RETIRE_USE_LOAD_QUEUE       ,"use_load_queue"       ,Tcontrol_t  ,1);
@@ -90,7 +92,20 @@
     }
 
+    // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      ALLOC2_INTERFACE_BEGIN("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]);
+
+      _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_VAL           ,VAL,_param->_nb_front_end, _param->_nb_context[it1]);
+      _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_ACK           ,ACK,_param->_nb_front_end, _param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE         ,"state"                ,Tevent_state_t    ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
+    }
+
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
     ALLOC1(reg_STORE_QUEUE_PTR_WRITE     ,Tlsq_ptr_t     ,_param->_nb_load_store_queue);
+    ALLOC2(reg_STORE_QUEUE_PTR_READ      ,Tlsq_ptr_t     ,_param->_nb_front_end, _param->_nb_context[it1]);
+    ALLOC2(reg_STORE_QUEUE_EMPTY         ,bool           ,_param->_nb_front_end, _param->_nb_context[it1]);
     ALLOC2(reg_STORE_QUEUE_USE           ,bool           ,_param->_nb_load_store_queue,_param->_size_store_queue [it1]);
     ALLOC1(reg_STORE_QUEUE_NB_USE        ,Tlsq_ptr_t     ,_param->_nb_load_store_queue);
@@ -107,5 +122,8 @@
     ALLOC1(internal_RETIRE_LSQ           ,uint32_t       ,_param->_nb_inst_retire);
     ALLOC1(internal_RETIRE_PTR           ,Tlsq_ptr_t     ,_param->_nb_inst_retire);
+
+    ALLOC2(internal_RETIRE_EVENT_ACK     ,Tcontrol_t     ,_param->_nb_front_end,_param->_nb_context[it1]);
       }
+
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_deallocation.cpp	(revision 122)
@@ -36,4 +36,6 @@
         DELETE1_SIGNAL( in_INSERT_OPERATION            ,_param->_nb_inst_insert,_param->_size_operation      );
         DELETE1_SIGNAL(out_INSERT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_insert,_param->_size_store_queue_ptr);
+        DELETE1_SIGNAL(out_INSERT_STORE_QUEUE_PTR_READ ,_param->_nb_inst_insert,_param->_size_store_queue_ptr);
+        DELETE1_SIGNAL(out_INSERT_STORE_QUEUE_EMPTY    ,_param->_nb_inst_insert,1);
         DELETE1_SIGNAL(out_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_insert,_param->_size_load_queue_ptr );
 
@@ -49,5 +51,11 @@
         DELETE1_SIGNAL( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire,_param->_size_load_queue_ptr );
 
+        DELETE2_SIGNAL( in_RETIRE_EVENT_VAL            ,_param->_nb_front_end, _param->_nb_context[it1],1);
+        DELETE2_SIGNAL(out_RETIRE_EVENT_ACK            ,_param->_nb_front_end, _param->_nb_context[it1],1);
+        DELETE2_SIGNAL( in_RETIRE_EVENT_STATE          ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state);
+
         DELETE1(reg_STORE_QUEUE_PTR_WRITE     ,_param->_nb_load_store_queue);
+        DELETE2(reg_STORE_QUEUE_PTR_READ      ,_param->_nb_front_end, _param->_nb_context[it1]);
+        DELETE2(reg_STORE_QUEUE_EMPTY         ,_param->_nb_front_end, _param->_nb_context[it1]);
         DELETE2(reg_STORE_QUEUE_USE           ,_param->_nb_load_store_queue,_param->_size_store_queue [it1]);
         DELETE1(reg_STORE_QUEUE_NB_USE        ,_param->_nb_load_store_queue);
@@ -64,4 +72,6 @@
         DELETE1(internal_RETIRE_LSQ           ,_param->_nb_inst_retire);
         DELETE1(internal_RETIRE_PTR           ,_param->_nb_inst_retire);
+
+        DELETE2(internal_RETIRE_EVENT_ACK     ,_param->_nb_front_end,_param->_nb_context[it1]);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp	(revision 122)
@@ -54,6 +54,6 @@
 	Tcontrol_t ack                   = false;
 
-	if ( (PORT_READ(in_INSERT_VAL  [i]) == true       ) and
-	     (PORT_READ(in_INSERT_TYPE [i]) == TYPE_MEMORY))
+	if ((PORT_READ(in_INSERT_VAL  [i]) == true       ) and
+	    (PORT_READ(in_INSERT_TYPE [i]) == TYPE_MEMORY))
 	  {
             log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * type is memory");
@@ -75,5 +75,8 @@
 		uint32_t   ptr;
 
-                PORT_WRITE(out_INSERT_STORE_QUEUE_PTR_WRITE [i], STORE_QUEUE_PTR_WRITE [lsq]);
+                PORT_WRITE(out_INSERT_STORE_QUEUE_PTR_WRITE [i],     STORE_QUEUE_PTR_WRITE [lsq]);
+//                 PORT_WRITE(out_INSERT_STORE_QUEUE_PTR_READ  [i], ((reg_STORE_QUEUE_PTR_READ  [front_end_id][context_id]+1)%_param->_size_load_queue[lsq]));
+                PORT_WRITE(out_INSERT_STORE_QUEUE_PTR_READ  [i], reg_STORE_QUEUE_PTR_READ  [front_end_id][context_id]);
+                PORT_WRITE(out_INSERT_STORE_QUEUE_EMPTY     [i], reg_STORE_QUEUE_EMPTY     [front_end_id][context_id]);
                 if (_param->_have_port_load_queue_ptr)
                 PORT_WRITE(out_INSERT_LOAD_QUEUE_PTR_WRITE  [i], LOAD_QUEUE_PTR_WRITE  [lsq]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_transition.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_transition.cpp	(revision 122)
@@ -38,4 +38,10 @@
 	      reg_LOAD_QUEUE_USE  [i][j] = false;
 	  }
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            {
+              reg_STORE_QUEUE_PTR_READ  [i][j] = 0;
+              reg_STORE_QUEUE_EMPTY     [i][j] = true;
+            }
       }
     else
@@ -56,4 +62,6 @@
  		    log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * use STORE_QUEUE");
 
+		    Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [i]):0;
+		    Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_INSERT_CONTEXT_ID   [i]):0;
 		    uint32_t   lsq = internal_INSERT_LSQ [i];
 		    Tlsq_ptr_t ptr = internal_INSERT_PTR [i];
@@ -62,4 +70,5 @@
  		    log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * ptr : %d",ptr);
 
+		    reg_STORE_QUEUE_EMPTY     [front_end_id][context_id] = false; // new element
 		    reg_STORE_QUEUE_PTR_WRITE [lsq]      = (ptr+1)%_param->_size_store_queue[lsq];
 		    reg_STORE_QUEUE_NB_USE    [lsq]      ++;
@@ -109,5 +118,7 @@
  		    log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * lsq : %d",lsq);
  		    log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * ptr : %d",ptr);
-		    
+	
+                    // TODO : if ROB retire ooo context, can retire store ooo.
+
 // 		    reg_STORE_QUEUE_PTR_WRITE [lsq]      = ((ptr==0)?_param->_size_store_queue[lsq]:ptr)-1;
 		    reg_STORE_QUEUE_NB_USE    [lsq]      --;
@@ -137,6 +148,36 @@
 		}	
 	    }
+        
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            {
+              uint32_t lsq = _param->_link_load_store_unit_with_thread[i][j];
+                    
+              if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_NO_EVENT)
+                {
+                  uint32_t ptr_old =  reg_STORE_QUEUE_PTR_READ[i][j];
+                  uint32_t ptr_new = (reg_STORE_QUEUE_PTR_READ[i][j]+1)%_param->_size_store_queue[lsq];
+
+                  if ((reg_STORE_QUEUE_USE [lsq][ptr_old] == false) and
+		      (reg_STORE_QUEUE_EMPTY    [i][j] == false))
+                    {
+                      reg_STORE_QUEUE_PTR_READ [i][j] = ptr_new;
+                      if (ptr_new == reg_STORE_QUEUE_PTR_WRITE [lsq])
+                      reg_STORE_QUEUE_EMPTY    [i][j] = true;
+                    }
+                }
+              
+              if (PORT_READ(in_RETIRE_EVENT_VAL[i][j]) and internal_RETIRE_EVENT_ACK [i][j])
+                if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)
+                  {
+		    log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"  * EVENT [%d][%d]",i,j);
+
+                    // reset ptr_read
+                    reg_STORE_QUEUE_PTR_READ [i][j] = reg_STORE_QUEUE_PTR_WRITE [lsq];
+                    reg_STORE_QUEUE_EMPTY    [i][j] = true;
+                  }
+            }
       }
-
+    
     // ===================================================================
     // =====[ OTHER ]=====================================================
@@ -150,4 +191,8 @@
         {
           log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * Load_Store_unit [%d]",i);
+          log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"      * reg_LOAD_QUEUE_PTR_WRITE  : %d", reg_LOAD_QUEUE_PTR_WRITE [i]);
+          log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"      * reg_LOAD_QUEUE_USE        :");
+          for (uint32_t j=0; j<_param->_size_load_queue [i]; ++j)
+          log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"        [%d] %d",j,reg_LOAD_QUEUE_USE [i][j]);
           log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"      * reg_STORE_QUEUE_NB_USE    : %d", reg_STORE_QUEUE_NB_USE   [i]);
           log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"      * reg_STORE_QUEUE_PTR_WRITE : %d", reg_STORE_QUEUE_PTR_WRITE[i]);
@@ -155,9 +200,11 @@
           for (uint32_t j=0; j<_param->_size_store_queue [i]; ++j)
           log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"        [%d] %d",j,reg_STORE_QUEUE_USE [i][j]);
-          log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"      * reg_LOAD_QUEUE_PTR_WRITE  : %d", reg_LOAD_QUEUE_PTR_WRITE [i]);
-          log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"      * reg_LOAD_QUEUE_USE        :");
-          for (uint32_t j=0; j<_param->_size_load_queue [i]; ++j)
-          log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"        [%d] %d",j,reg_LOAD_QUEUE_USE [i][j]);
         }
+      for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+        for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+          {
+          log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"      * reg_STORE_QUEUE_PTR_READ [%d][%d] : %d",i,j,reg_STORE_QUEUE_PTR_READ [i][j]);
+          log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"      * reg_STORE_QUEUE_EMPTY    [%d][%d] : %d",i,j,reg_STORE_QUEUE_EMPTY    [i][j]);
+          }
     }
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h	(revision 122)
@@ -100,6 +100,6 @@
   public    : SC_IN (Tgeneral_address_t)   **  in_RETIRE_NUM_REG_RD_LOG    ;//[nb_inst_retire]
   public    : SC_IN (Tspecial_address_t)   **  in_RETIRE_NUM_REG_RE_LOG    ;//[nb_inst_retire]
-  public    : SC_IN (Tgeneral_address_t)   **  in_RETIRE_NUM_REG_RD_PHY_OLD;//[nb_inst_retire]
-  public    : SC_IN (Tspecial_address_t)   **  in_RETIRE_NUM_REG_RE_PHY_OLD;//[nb_inst_retire]
+  public    : SC_IN (Tgeneral_address_t)   **  in_RETIRE_NUM_REG_RD_PHY_NEW;//[nb_inst_retire]
+  public    : SC_IN (Tspecial_address_t)   **  in_RETIRE_NUM_REG_RE_PHY_NEW;//[nb_inst_retire]
   public    : SC_OUT(Tcontrol_t        )   ** out_RETIRE_RESTORE_RD_PHY_OLD;//[nb_inst_retire]
   public    : SC_OUT(Tcontrol_t        )   ** out_RETIRE_RESTORE_RE_PHY_OLD;//[nb_inst_retire]
@@ -114,7 +114,12 @@
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-  private   : Tgeneral_address_t          *** rat_gpr;                      //[nb_front_end][nb_context][nb_general_register_logic]
+  private   : Tgeneral_address_t          *** rat_gpr_not_speculative;      //[nb_front_end][nb_context][nb_general_register_logic]
+  private   : Tgeneral_address_t          *** rat_gpr_speculative;          //[nb_front_end][nb_context][nb_general_register_logic]
+  private   : bool                        *** rat_gpr_speculative_valid;    //[nb_front_end][nb_context][nb_general_register_logic]
   private   : bool                        *** rat_gpr_update_table;         //[nb_front_end][nb_context][nb_general_register_logic]
-  private   : Tspecial_address_t          *** rat_spr;                      //[nb_front_end][nb_context][nb_special_register_logic]
+
+  private   : Tspecial_address_t          *** rat_spr_not_speculative;      //[nb_front_end][nb_context][nb_special_register_logic]
+  private   : Tspecial_address_t          *** rat_spr_speculative;          //[nb_front_end][nb_context][nb_special_register_logic]
+  private   : bool                        *** rat_spr_speculative_valid;    //[nb_front_end][nb_context][nb_special_register_logic]
   private   : bool                        *** rat_spr_update_table;         //[nb_front_end][nb_context][nb_special_register_logic]
 
@@ -123,10 +128,12 @@
   private   : Tcontrol_t                    * internal_INSERT_ACK;          //[nb_inst_insert]
   private   : Tcontrol_t                    * internal_RETIRE_ACK;          //[nb_inst_retire]
-  public    : Tcontrol_t                   ** internal_RETIRE_EVENT_ACK    ;//[nb_front_end][nb_context]
-
-  private   : bool                        *** internal_rat_gpr_update_table;         //[nb_front_end][nb_context][nb_general_register_logic]
-  private   : bool                        *** internal_rat_spr_update_table;         //[nb_front_end][nb_context][nb_special_register_logic]
-  public    : Tcontrol_t                    * internal_RETIRE_RESTORE_RD_PHY_OLD;//[nb_inst_retire]
-  public    : Tcontrol_t                    * internal_RETIRE_RESTORE_RE_PHY_OLD;//[nb_inst_retire]
+  private   : Tcontrol_t                   ** internal_RETIRE_EVENT_ACK    ;//[nb_front_end][nb_context]
+
+  private   : bool                        *** internal_rat_gpr_update_table;//[nb_front_end][nb_context][nb_general_register_logic]
+  private   : bool                        *** internal_rat_spr_update_table;//[nb_front_end][nb_context][nb_special_register_logic]
+
+  private   : Tcontrol_t                    * internal_RETIRE_RESTORE           ;//[nb_inst_retire]
+  private   : Tcontrol_t                    * internal_RETIRE_RESTORE_RD_PHY_OLD;//[nb_inst_retire]
+  private   : Tcontrol_t                    * internal_RETIRE_RESTORE_RE_PHY_OLD;//[nb_inst_retire]
 
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp	(revision 122)
@@ -129,4 +129,8 @@
                       << (*(in_RENAME_NUM_REG_RE_LOG [i]));
           }
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            sensitive << (*(in_RETIRE_EVENT_VAL   [i][j]))
+                      << (*(in_RETIRE_EVENT_STATE [i][j]));
 
 # ifdef SYSTEMCASS_SPECIFIC
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp	(revision 122)
@@ -109,6 +109,6 @@
       ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RD_LOG    ,"num_reg_rd_log"    ,Tgeneral_address_t,_param->_size_general_register_logic);
       ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_LOG    ,"num_reg_re_log"    ,Tspecial_address_t,_param->_size_special_register_logic);
-      ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RD_PHY_OLD,"num_reg_rd_phy_old",Tgeneral_address_t,_param->_size_general_register);
-      ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register);
+      ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RD_PHY_NEW,"num_reg_rd_phy_new",Tgeneral_address_t,_param->_size_general_register);
+      ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register);
       ALLOC1_SIGNAL_OUT(out_RETIRE_RESTORE_RD_PHY_OLD,"restore_rd_phy_old",Tcontrol_t        ,1);
       ALLOC1_SIGNAL_OUT(out_RETIRE_RESTORE_RE_PHY_OLD,"restore_re_phy_old",Tcontrol_t        ,1);
@@ -136,11 +136,18 @@
     ALLOC2(internal_RETIRE_EVENT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]);
 
-    ALLOC3(rat_gpr                      ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-    ALLOC3(rat_spr                      ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
-    ALLOC3(rat_gpr_update_table         ,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-    ALLOC3(rat_spr_update_table         ,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
-    ALLOC3(internal_rat_gpr_update_table,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-    ALLOC3(internal_rat_spr_update_table,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+    ALLOC3(rat_gpr_not_speculative  ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
+    ALLOC3(rat_gpr_speculative      ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
+    ALLOC3(rat_gpr_speculative_valid,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
+    ALLOC3(rat_gpr_update_table     ,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
+    
+    ALLOC3(rat_spr_not_speculative  ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+    ALLOC3(rat_spr_speculative      ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+    ALLOC3(rat_spr_speculative_valid,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+    ALLOC3(rat_spr_update_table     ,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
 
+    ALLOC3(internal_rat_gpr_update_table,bool, _param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
+    ALLOC3(internal_rat_spr_update_table,bool, _param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+
+    ALLOC1(internal_RETIRE_RESTORE           ,Tcontrol_t,_param->_nb_inst_retire);
     ALLOC1(internal_RETIRE_RESTORE_RD_PHY_OLD,Tcontrol_t,_param->_nb_inst_retire);
     ALLOC1(internal_RETIRE_RESTORE_RE_PHY_OLD,Tcontrol_t,_param->_nb_inst_retire);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp	(revision 122)
@@ -64,6 +64,6 @@
         DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_LOG    ,_param->_nb_inst_retire,_param->_size_general_register_logic);
         DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_LOG    ,_param->_nb_inst_retire,_param->_size_special_register_logic);
-        DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire,_param->_size_general_register);
-        DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire,_param->_size_special_register);
+        DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW,_param->_nb_inst_retire,_param->_size_general_register);
+        DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire,_param->_size_special_register);
         DELETE1_SIGNAL(out_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire,1);
         DELETE1_SIGNAL(out_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire,1);
@@ -79,16 +79,23 @@
         DELETE2(internal_RETIRE_EVENT_ACK              ,_param->_nb_front_end,_param->_nb_context[it1]);
 
-        DELETE3(rat_gpr                      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-        DELETE3(rat_spr                      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+        DELETE3(rat_gpr_not_speculative      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
+        DELETE3(rat_gpr_speculative          ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
+        DELETE3(rat_gpr_speculative_valid    ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
         DELETE3(rat_gpr_update_table         ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
+
+        DELETE3(rat_spr_not_speculative      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+        DELETE3(rat_spr_speculative          ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+        DELETE3(rat_spr_speculative_valid    ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
         DELETE3(rat_spr_update_table         ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+
         DELETE3(internal_rat_gpr_update_table,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
         DELETE3(internal_rat_spr_update_table,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
         
+        DELETE1(internal_RETIRE_RESTORE           ,_param->_nb_inst_retire);
         DELETE1(internal_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire);
         DELETE1(internal_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire);
       }
 
-    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
     delete    _component;
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp	(revision 122)
@@ -26,4 +26,5 @@
     log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
 
+    if (PORT_READ(in_NRESET) != 0)
     for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
       if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access
@@ -33,7 +34,11 @@
 	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
 	Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
+        bool       have_event   = (PORT_READ(in_RETIRE_EVENT_VAL [front_end_id][context_id]) and // always ack
+                                   (PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) == EVENT_STATE_EVENT));
+
 
         log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id       : %d",front_end_id);
         log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id         : %d",context_id);
+        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * have_event         : %d",have_event);
 
         Tgeneral_address_t num_reg_ra_log    = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register;
@@ -43,9 +48,13 @@
         Tspecial_address_t num_reg_re_log    = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register;
                                             
-        Tgeneral_address_t num_reg_ra_phy    = rat_gpr[front_end_id][context_id][num_reg_ra_log];
-        Tgeneral_address_t num_reg_rb_phy    = rat_gpr[front_end_id][context_id][num_reg_rb_log];
-        Tspecial_address_t num_reg_rc_phy    = rat_spr[front_end_id][context_id][num_reg_rc_log];
-        Tgeneral_address_t num_reg_rd_phy_old= rat_gpr[front_end_id][context_id][num_reg_rd_log];
-        Tspecial_address_t num_reg_re_phy_old= rat_spr[front_end_id][context_id][num_reg_re_log];
+        // if rat_speculative is valid, 
+        // then read rat_speculative have the most valid alias register
+        // else, they have an previous event, the rat_not_speculative have the valid register
+
+        Tgeneral_address_t num_reg_ra_phy    = (rat_gpr_speculative_valid[front_end_id][context_id][num_reg_ra_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_ra_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_ra_log];
+        Tgeneral_address_t num_reg_rb_phy    = (rat_gpr_speculative_valid[front_end_id][context_id][num_reg_rb_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_rb_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_rb_log];
+        Tspecial_address_t num_reg_rc_phy    = (rat_spr_speculative_valid[front_end_id][context_id][num_reg_rc_log] and not have_event)?rat_spr_speculative[front_end_id][context_id][num_reg_rc_log]:rat_spr_not_speculative[front_end_id][context_id][num_reg_rc_log];
+        Tgeneral_address_t num_reg_rd_phy_old= (rat_gpr_speculative_valid[front_end_id][context_id][num_reg_rd_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_rd_log];
+        Tspecial_address_t num_reg_re_phy_old= (rat_spr_speculative_valid[front_end_id][context_id][num_reg_re_log] and not have_event)?rat_spr_speculative[front_end_id][context_id][num_reg_re_log]:rat_spr_not_speculative[front_end_id][context_id][num_reg_re_log];
 
         log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_ra         : %d -> %d",num_reg_ra_log,num_reg_ra_phy    );
@@ -54,5 +63,4 @@
         log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd         : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old);
         log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re         : %d -> %d",num_reg_re_log,num_reg_re_phy_old);
-        
 
 	PORT_WRITE(out_RENAME_NUM_REG_RA_PHY     [i], num_reg_ra_phy    );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp	(revision 122)
@@ -26,8 +26,12 @@
     log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
 
+    if (PORT_READ(in_NRESET) != 0)
+      {
     // Init internal update table
     for (uint32_t i=0; i<_param->_nb_front_end; i++)
       for (uint32_t j=0; j<_param->_nb_context[i]; j++)
         {
+          log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * init [%d][%d]",i,j);
+
           // An event occure
           // bool event = (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) != EVENT_STATE_NO_EVENT);
@@ -35,14 +39,15 @@
                                      (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT));
 
+          log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * reset_update_table : %d",reset_update_table);
+
           // not event -> update_table == 1 -> always update
           // event     -> update_table and not reset
           for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k)
             internal_rat_gpr_update_table [i][j][k] = // not event or 
-                                                      (rat_gpr_update_table [i][j][k] and not reset_update_table);
+                                                      (not reset_update_table and rat_gpr_update_table [i][j][k]);
           for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k)
             internal_rat_spr_update_table [i][j][k] = // not event or 
-                                                      (rat_spr_update_table [i][j][k] and not reset_update_table);
+                                                      (not reset_update_table and rat_spr_update_table [i][j][k]);
         }
-
 
     // RETIRE is in order -> also don't need test if an instruction is valid
@@ -55,14 +60,16 @@
         Tcontrol_t retire_restore_re_phy_old = false;
 
-        Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
-        Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RETIRE_CONTEXT_ID   [i]):0;
-        Tcontrol_t restore      = (PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) != EVENT_STATE_NO_EVENT);
+        Tcontext_t front_end_id   = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
+        Tcontext_t context_id     = (_param->_have_port_context_id  )?PORT_READ(in_RETIRE_CONTEXT_ID   [i]):0;
+        Tcontrol_t retire_restore = (PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) != EVENT_STATE_NO_EVENT);
+
+        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id         : %d",front_end_id);
+        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id           : %d",context_id  );
+        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * restore              : %d",retire_restore);
 
         // Test if event -> need restore ?
-        if (restore)
+        if (retire_restore)
           {
-            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * Have event");
-            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id         : %d",front_end_id);
-            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id           : %d",context_id  );
+            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * Have event");
                         
             // Test and update update table
@@ -87,14 +94,16 @@
               }
 
-            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * restore_rd_phy_old   : %d",retire_restore_rd_phy_old);
-            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * restore_re_phy_old   : %d",retire_restore_re_phy_old);
+            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * restore_rd_phy_old   : %d",retire_restore_rd_phy_old);
+            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * restore_re_phy_old   : %d",retire_restore_re_phy_old);
           }
 
-        internal_RETIRE_RESTORE_RD_PHY_OLD[i] = retire_restore_rd_phy_old;
-        internal_RETIRE_RESTORE_RE_PHY_OLD[i] = retire_restore_re_phy_old;
+        internal_RETIRE_RESTORE            [i] = retire_restore;
+        internal_RETIRE_RESTORE_RD_PHY_OLD [i] = retire_restore_rd_phy_old;
+        internal_RETIRE_RESTORE_RE_PHY_OLD [i] = retire_restore_re_phy_old;
               
-        PORT_WRITE(out_RETIRE_RESTORE_RD_PHY_OLD[i], internal_RETIRE_RESTORE_RD_PHY_OLD[i]);
-        PORT_WRITE(out_RETIRE_RESTORE_RE_PHY_OLD[i], internal_RETIRE_RESTORE_RE_PHY_OLD[i]);
-        PORT_WRITE(out_RETIRE_RESTORE           [i], restore);
+        PORT_WRITE(out_RETIRE_RESTORE           [i], internal_RETIRE_RESTORE            [i]);
+        PORT_WRITE(out_RETIRE_RESTORE_RD_PHY_OLD[i], internal_RETIRE_RESTORE_RD_PHY_OLD [i]);
+        PORT_WRITE(out_RETIRE_RESTORE_RE_PHY_OLD[i], internal_RETIRE_RESTORE_RE_PHY_OLD [i]);
+      }
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp	(revision 122)
@@ -34,15 +34,20 @@
 	  for (uint32_t j=0; j<_param->_nb_context[i]; j++)
 	    {
-	      rat_gpr [i][j][0] = 0;
+	      rat_gpr_not_speculative   [i][j][0] = 0;
+              rat_gpr_speculative_valid [i][j][0] = false;
 
 	      for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
                 {
-                  rat_gpr             [i][j][k] = gpr++;
-//                rat_gpr_update_table[i][j][k] = 0;
+                  rat_gpr_not_speculative    [i][j][k] = gpr++;
+//                rat_gpr_speculative        [i][j][k] = gpr++;
+                  rat_gpr_speculative_valid  [i][j][k] = false;
+//                rat_gpr_update_table       [i][j][k] = false;
                 }
 	      for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
                 {
-                  rat_spr             [i][j][k] = spr++;
-//                rat_spr_update_table[i][j][k] = 0;
+                  rat_spr_not_speculative    [i][j][k] = spr++;
+//                rat_spr_speculative        [i][j][k] = spr++;
+                  rat_spr_speculative_valid  [i][j][k] = false;
+//                rat_spr_update_table       [i][j][k] = false;
                 }
 	    }
@@ -53,7 +58,32 @@
 
 	// =====================================================
+	// ====[ RETIRE_EVENT ]=================================
+	// =====================================================
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j])
+              // Test if event have just occure
+              if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)
+                {
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * Reset Update Table");
+                  
+                  // Reset update_table and validity table
+                  for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
+                    {
+                      rat_gpr_update_table      [i][j][k] = false;
+                      rat_gpr_speculative_valid [i][j][k] = false;
+                    }
+                  for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
+                    {
+                      rat_spr_update_table      [i][j][k] = false;
+                      rat_spr_speculative_valid [i][j][k] = false;
+                    }
+                }
+
+	// =====================================================
 	// ====[ INSERT ]=======================================
 	// =====================================================
 	// First : interface insert
+        // this instruction is speculative !!!
 	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
 	  // Test transaction
@@ -64,41 +94,37 @@
 	      Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
 	      Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
-
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end      : %d",front_end_id);
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context        : %d",context_id);
+              Tcontrol_t write_rd     = PORT_READ(in_INSERT_WRITE_RD [i]);
+              Tcontrol_t write_re     = PORT_READ(in_INSERT_WRITE_RE [i]);
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end          : %d",front_end_id);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context            : %d",context_id);
 	      
-	      // Test if write
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_rd       : %d",PORT_READ(in_INSERT_WRITE_RD [i]));
-	      if (PORT_READ(in_INSERT_WRITE_RD [i]) == 1)
-                {
-                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy : %d",PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]));
-                  rat_gpr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RD_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]);
-                }
-
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_re       : %d",PORT_READ(in_INSERT_WRITE_RE [i]));
-	      if (PORT_READ(in_INSERT_WRITE_RE [i]) == 1)
-                {
-                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy : %d",PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]));
-                  rat_spr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RE_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]);
+	      // Test if write and modifie RAT
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_rd           : %d",write_rd);
+	      if (write_rd == 1)
+                {
+                  Tgeneral_address_t num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [i]);
+                  Tgeneral_address_t num_reg_rd_phy = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_log     : %d",num_reg_rd_log);
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy     : %d",num_reg_rd_phy);
+
+                  rat_gpr_speculative       [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy;
+                  rat_gpr_speculative_valid [front_end_id][context_id][num_reg_rd_log] = true;
+                }
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_re           : %d",write_re);
+	      if (write_re == 1)
+                {
+                  Tspecial_address_t num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [i]);
+                  Tspecial_address_t num_reg_re_phy = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_log     : %d",num_reg_re_log);
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy     : %d",num_reg_re_phy);
+
+                  rat_spr_speculative       [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy;
+                  rat_spr_speculative_valid [front_end_id][context_id][num_reg_re_log] = true;
                 }
 	    }
-
-	// =====================================================
-	// ====[ RETIRE_EVENT ]=================================
-	// =====================================================
-        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
-          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
-            if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j])
-              // Test if event have just occure
-              if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)
-                {
-                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * Reset Update Table");
-                  
-                  // Reset update_table
-                  for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
-                    rat_gpr_update_table [i][j][k] = 0;
-                  for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
-                    rat_spr_update_table [i][j][k] = 0;
-                }
 
 	// =====================================================
@@ -117,59 +143,61 @@
 	      // the retire interface became of the Re Order Buffer, also is in program sequence !
 
-              Tcontext_t         front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
-              Tcontext_t         context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RETIRE_CONTEXT_ID   [i]):0;
-              Tevent_state_t     event_state  = PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]);
-
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id : %d",front_end_id);
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id   : %d",context_id);
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * event_state  : %d",event_state);
-
-// 	      if (event_state != EVENT_STATE_NO_EVENT)
-// 		{
- 		  // Test if write and have not a previous update
-		  if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1)
-		    {
-		      Tgeneral_address_t rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]);
+              Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
+              Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RETIRE_CONTEXT_ID   [i]):0;
+              Tcontrol_t write_rd     = PORT_READ(in_RETIRE_WRITE_RD [i]);
+              Tcontrol_t write_re     = PORT_READ(in_RETIRE_WRITE_RE [i]);
+              Tcontrol_t restore      = internal_RETIRE_RESTORE [i];
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id       : %d",front_end_id);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id         : %d",context_id  );
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * restore            : %d",restore     );
+
+              // Test if write and have not a previous update
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_rd           : %d",write_rd);
+              if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1)
+                {
+                  Tgeneral_address_t num_reg_rd_log     = PORT_READ(in_RETIRE_NUM_REG_RD_LOG     [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_log     : %d",num_reg_rd_log    );
+
+                  if (not restore)
+                    {
+                  Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy_new : %d",num_reg_rd_phy_new);
+
+                  rat_gpr_not_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
+                    }
+
+                  Tcontrol_t         restore_rd         = internal_RETIRE_RESTORE_RD_PHY_OLD [i];
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * restore_rd         : %d",restore_rd        );
                       
-		      log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * retire RD");
-		      log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * rd_log       : %d",rd_log);
-		      
-// #ifdef DEBUG_TEST
-//                       if (not (internal_RETIRE_RESTORE_RD_PHY_OLD [i] and ( (rat_gpr_update_table [front_end_id][context_id][rd_log] == 0)) and (event_state != EVENT_STATE_NO_EVENT)))
-//                         throw ERRORMORPHEO(FUNCTION,toString(_("restore_rd_phy_old [%d] = %d, but rat_gpr_update_table[%d][%d][%d] = %d\n"),
-//                                                              i,internal_RETIRE_RESTORE_RD_PHY_OLD [i],
-//                                                              front_end_id,context_id,rd_log,rat_gpr_update_table [front_end_id][context_id][rd_log]));
-// #endif
-
- 		      if (internal_RETIRE_RESTORE_RD_PHY_OLD [i])
-// 		      if (rat_gpr_update_table [front_end_id][context_id][rd_log] == 0)
-			{                      
-			  rat_gpr              [front_end_id][context_id][rd_log] = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]);
-			  rat_gpr_update_table [front_end_id][context_id][rd_log] = 1;
-			}
-		    }
-
-		  if (PORT_READ(in_RETIRE_WRITE_RE [i]) == 1)
-		    {
-		      Tspecial_address_t re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]);
-
-		      log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * retire RE");
-		      log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * re_log       : %d",re_log);
-
-// #ifdef DEBUG_TEST
-//                       if (not (internal_RETIRE_RESTORE_RE_PHY_OLD [i] and ((rat_spr_update_table [front_end_id][context_id][re_log] == 0) and (event_state != EVENT_STATE_NO_EVENT))))
-//                         throw ERRORMORPHEO(FUNCTION,toString(_("restore_re_phy_old [%d] = %d, but rat_spr_update_table[%d][%d][%d] = %d\n"),
-//                                                              i,internal_RETIRE_RESTORE_RE_PHY_OLD [i],
-//                                                              front_end_id,context_id,re_log,rat_spr_update_table [front_end_id][context_id][re_log]));
-// #endif
-
- 		      if (internal_RETIRE_RESTORE_RE_PHY_OLD [i])
-// 		      if (rat_spr_update_table [front_end_id][context_id][re_log] == 0)
-			{                      
-			  rat_spr              [front_end_id][context_id][re_log] = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]);
-			  rat_spr_update_table [front_end_id][context_id][re_log] = 1;
-			}
-		    }
-// 		}
+                  if (restore_rd)
+                  rat_gpr_update_table    [front_end_id][context_id][num_reg_rd_log] = true;
+                }
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_re           : %d",write_re);
+              if (PORT_READ(in_RETIRE_WRITE_RE [i]) == 1)
+                {
+                  Tspecial_address_t num_reg_re_log     = PORT_READ(in_RETIRE_NUM_REG_RE_LOG     [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_log     : %d",num_reg_re_log    );
+
+                  if (not restore)
+                    {
+                  Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy_new : %d",num_reg_re_phy_new);
+
+                  rat_spr_not_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
+                    }
+
+                  Tcontrol_t         restore_re         = internal_RETIRE_RESTORE_RE_PHY_OLD [i];
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * restore_re         : %d",restore_re        );
+                      
+                  if (restore_re)
+                  rat_spr_update_table    [front_end_id][context_id][num_reg_re_log] = true;
+                }
+
 	    }
       }
@@ -194,5 +222,5 @@
                       break;
                     else
-                      str+=toString("GPR[%.4d] - %.5d %.1d | ",index,rat_gpr[i][j][index],rat_gpr_update_table[i][j][index]);
+                      str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) %.1d | ",index,rat_gpr_speculative_valid [i][j][index],rat_gpr_speculative [i][j][index],rat_gpr_not_speculative [i][j][index],rat_gpr_update_table[i][j][index]);
                   }
                 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
@@ -209,5 +237,5 @@
                       break;
                     else
-                      str+=toString("SPR[%.4d] - %.5d %.1d | ",index,rat_spr[i][j][index],rat_spr_update_table[i][j][index]);
+                      str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) %.1d | ",index,rat_spr_speculative_valid [i][j][index],rat_spr_speculative [i][j][index],rat_spr_not_speculative [i][j][index],rat_spr_update_table[i][j][index]);
                   }
                 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
@@ -218,20 +246,35 @@
 
 #ifdef DEBUG_TEST
-        if (1)
+# if 1
+    {
+      for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+        for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
           {
-            for (uint32_t i=0; i<_param->_nb_front_end; ++i)
-              for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
-                {
-                  for (uint32_t x=0; x<_param->_nb_general_register_logic; ++x)
-                    for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y)
-                      if (rat_gpr[i][j][x] == rat_gpr[i][j][y])
-                        throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr[%d][%d][%d] == rat_gpr[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr[i][j][x]));
-                  for (uint32_t x=0; x<_param->_nb_special_register_logic; ++x)
-                    for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y)
-                      if (rat_spr[i][j][x] == rat_spr[i][j][y])
-                        throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr[%d][%d][%d] == rat_spr[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr[i][j][x]));
-                }
-
+            for (uint32_t x=0; x<_param->_nb_general_register_logic; ++x)
+              for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y)
+                {
+                  if (rat_gpr_speculative_valid [i][j][x] and
+                      rat_gpr_speculative_valid [i][j][y] and
+                      (rat_gpr_speculative[i][j][x] == rat_gpr_speculative[i][j][y]))
+                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_speculative[%d][%d][%d] == rat_gpr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_speculative[i][j][x]));
+                  if (rat_gpr_not_speculative[i][j][x] == rat_gpr_not_speculative[i][j][y])
+                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_not_speculative[%d][%d][%d] == rat_gpr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_not_speculative[i][j][x]));
+                  
+                }
+            for (uint32_t x=0; x<_param->_nb_special_register_logic; ++x)
+              for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y)
+                {
+                  if(rat_spr_speculative_valid [i][j][x] and
+                     rat_spr_speculative_valid [i][j][y] and
+                     (rat_spr_speculative[i][j][x] == rat_spr_speculative[i][j][y]))
+                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_speculative[%d][%d][%d] == rat_spr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_speculative[i][j][x]));
+                  if (rat_spr_not_speculative[i][j][x] == rat_spr_not_speculative[i][j][y])
+                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_not_speculative[%d][%d][%d] == rat_spr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_not_speculative[i][j][x]));
+                  
+                }
           }
+      
+    }
+# endif
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp	(revision 122)
@@ -361,8 +361,8 @@
 	  PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RE_LOG"    ,
 		              dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RE_LOG"    );
-	  PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RD_PHY_OLD",
-		              dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RD_PHY_OLD");
-	  PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RE_PHY_OLD",
-		              dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RE_PHY_OLD");
+	  PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RD_PHY_NEW",
+		              dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RD_PHY_NEW");
+	  PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RE_PHY_NEW",
+		              dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RE_PHY_NEW");
 
 	  dest = _name+"_register_translation_unit_glue";
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h	(revision 122)
@@ -125,5 +125,6 @@
 
     // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-  public    : SC_IN (Tevent_state_t    )  ***  in_RETIRE_EVENT_STATE      ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_FLUSH      ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_STOP       ;//[nb_front_end][nb_context]
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select.cpp	(revision 122)
@@ -125,5 +125,6 @@
 	for (uint32_t i=0; i<_param->_nb_front_end; i++)
 	  for (uint32_t j=0; j<_param->_nb_context [i]; j++)
-            sensitive << (*(in_RETIRE_EVENT_STATE [i][j]));
+            sensitive << (*(in_RETIRE_EVENT_FLUSH [i][j]))
+                      << (*(in_RETIRE_EVENT_STOP  [i][j]));
 
 	for (uint32_t i=0; i<_param->_nb_inst_rename; i++)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp	(revision 122)
@@ -130,5 +130,6 @@
       ALLOC2_INTERFACE_BEGIN("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]);
 
-      _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE         ,"state"                ,Tevent_state_t    ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_FLUSH         ,"flush"                ,Tcontrol_t        ,1                        , _param->_nb_front_end, _param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STOP          ,"stop"                 ,Tcontrol_t        ,1                        , _param->_nb_front_end, _param->_nb_context[it1]);
 
       ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp	(revision 122)
@@ -85,5 +85,6 @@
         DELETE1_SIGNAL(out_RENAME_OUT_EXCEPTION     ,_param->_nb_inst_rename,_param->_size_exception             );
 
-        DELETE2_SIGNAL( in_RETIRE_EVENT_STATE       ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state);
+        DELETE2_SIGNAL( in_RETIRE_EVENT_FLUSH       ,_param->_nb_front_end, _param->_nb_context[it1],1);
+        DELETE2_SIGNAL( in_RETIRE_EVENT_STOP        ,_param->_nb_front_end, _param->_nb_context[it1],1);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp	(revision 122)
@@ -17,4 +17,5 @@
 namespace rename_select {
 
+// #define CONTINUE_ON_EVENT_STOP
 
 #undef  FUNCTION
@@ -59,63 +60,74 @@
                 PORT_READ(in_RENAME_IN_VAL[x][y]))
 	      {
-		// Find !!!
-		val [i]    = true;
-		ack [x][y] = PORT_READ(in_RENAME_OUT_ACK [i]);
 
                 log_printf(TRACE,Rename_select,FUNCTION,"      * in_RENAME_OUT_ACK    : %d",PORT_READ(in_RENAME_OUT_ACK[i]));
                 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_IN_FRONT_END_ID [x][y]):0;
                 Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_IN_CONTEXT_ID   [x][y]):0;
+		Tcontrol_t stop         = PORT_READ(in_RETIRE_EVENT_STOP  [x][context_id]);
 
 		log_printf(TRACE,Rename_select,FUNCTION,"      * front_end_id         : %d",front_end_id);
 		log_printf(TRACE,Rename_select,FUNCTION,"      * context_id           : %d",context_id);
+                log_printf(TRACE,Rename_select,FUNCTION,"      * stop                 : %d",stop);
                 
                 // Test if ROB is Flushed
-                Tevent_state_t event_state         = PORT_READ(in_RETIRE_EVENT_STATE [x][context_id]);
-		Tcontrol_t     have_event          = (event_state != EVENT_STATE_NO_EVENT);
-		Tcontrol_t     can_register_access = not have_event;
-		Tcontrol_t     no_execute          = (PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y]) or have_event);
-		Tcontrol_t     read_ra             = (PORT_READ(in_RENAME_IN_READ_RA    [x][y]) and can_register_access);
-		Tcontrol_t     read_rb             = (PORT_READ(in_RENAME_IN_READ_RB    [x][y]) and can_register_access);
-		Tcontrol_t     read_rc             = (PORT_READ(in_RENAME_IN_READ_RC    [x][y]) and can_register_access);
-		Tcontrol_t     write_rd            = (PORT_READ(in_RENAME_IN_WRITE_RD   [x][y]) and can_register_access);
-		Tcontrol_t     write_re            = (PORT_READ(in_RENAME_IN_WRITE_RE   [x][y]) and can_register_access);
-// 		Tcontrol_t     read_ra             = (PORT_READ(in_RENAME_IN_READ_RA    [x][y]));
-// 		Tcontrol_t     read_rb             = (PORT_READ(in_RENAME_IN_READ_RB    [x][y]));
-// 		Tcontrol_t     read_rc             = (PORT_READ(in_RENAME_IN_READ_RC    [x][y]));
-// 		Tcontrol_t     write_rd            = (PORT_READ(in_RENAME_IN_WRITE_RD   [x][y]));
-// 		Tcontrol_t     write_re            = (PORT_READ(in_RENAME_IN_WRITE_RE   [x][y]));
-
-                log_printf(TRACE,Rename_select,FUNCTION,"      * event_state          : %d",event_state);
-                log_printf(TRACE,Rename_select,FUNCTION,"      * no_execute (before)  : %d",PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y]));
-                log_printf(TRACE,Rename_select,FUNCTION,"      * no_execute (after)   : %d",no_execute);
-
-		if (_param->_have_port_front_end_id)
-		PORT_WRITE(out_RENAME_OUT_FRONT_END_ID [i],front_end_id);
-		if (_param->_have_port_context_id)
-                PORT_WRITE(out_RENAME_OUT_CONTEXT_ID   [i],context_id);
-		if (_param->_have_port_depth)
-		PORT_WRITE(out_RENAME_OUT_DEPTH        [i],PORT_READ(in_RENAME_IN_DEPTH         [x][y]));
-		PORT_WRITE(out_RENAME_OUT_TYPE         [i],PORT_READ(in_RENAME_IN_TYPE          [x][y]));
-		PORT_WRITE(out_RENAME_OUT_OPERATION    [i],PORT_READ(in_RENAME_IN_OPERATION     [x][y]));
-		PORT_WRITE(out_RENAME_OUT_NO_EXECUTE   [i],no_execute);
-		PORT_WRITE(out_RENAME_OUT_IS_DELAY_SLOT[i],PORT_READ(in_RENAME_IN_IS_DELAY_SLOT [x][y]));
-#ifdef DEBUG
-		PORT_WRITE(out_RENAME_OUT_ADDRESS      [i],PORT_READ(in_RENAME_IN_ADDRESS       [x][y]));
+#ifndef CONTINUE_ON_EVENT_STOP
+                if (not stop)
 #endif
-		PORT_WRITE(out_RENAME_OUT_ADDRESS_NEXT [i],PORT_READ(in_RENAME_IN_ADDRESS_NEXT  [x][y]));
-		PORT_WRITE(out_RENAME_OUT_HAS_IMMEDIAT [i],PORT_READ(in_RENAME_IN_HAS_IMMEDIAT  [x][y]));
-		PORT_WRITE(out_RENAME_OUT_IMMEDIAT     [i],PORT_READ(in_RENAME_IN_IMMEDIAT      [x][y]));
-		PORT_WRITE(out_RENAME_OUT_READ_RA      [i],read_ra);
-		PORT_WRITE(out_RENAME_OUT_NUM_REG_RA   [i],PORT_READ(in_RENAME_IN_NUM_REG_RA    [x][y]));
-		PORT_WRITE(out_RENAME_OUT_READ_RB      [i],read_rb);
-		PORT_WRITE(out_RENAME_OUT_NUM_REG_RB   [i],PORT_READ(in_RENAME_IN_NUM_REG_RB    [x][y]));
-		PORT_WRITE(out_RENAME_OUT_READ_RC      [i],read_rc);
-		PORT_WRITE(out_RENAME_OUT_NUM_REG_RC   [i],PORT_READ(in_RENAME_IN_NUM_REG_RC    [x][y]));
-		PORT_WRITE(out_RENAME_OUT_WRITE_RD     [i],write_rd);
-		PORT_WRITE(out_RENAME_OUT_NUM_REG_RD   [i],PORT_READ(in_RENAME_IN_NUM_REG_RD    [x][y]));
-		PORT_WRITE(out_RENAME_OUT_WRITE_RE     [i],write_re);
-		PORT_WRITE(out_RENAME_OUT_NUM_REG_RE   [i],PORT_READ(in_RENAME_IN_NUM_REG_RE    [x][y]));
-		PORT_WRITE(out_RENAME_OUT_EXCEPTION_USE[i],PORT_READ(in_RENAME_IN_EXCEPTION_USE [x][y]));
-		PORT_WRITE(out_RENAME_OUT_EXCEPTION    [i],PORT_READ(in_RENAME_IN_EXCEPTION     [x][y]));
+                  {
+                    // Find !!!
+                    val [i]    = true;
+                    ack [x][y] = PORT_READ(in_RENAME_OUT_ACK [i]);
+                    
+		    Tcontrol_t     have_event          = (PORT_READ(in_RETIRE_EVENT_FLUSH [x][context_id]) 
+#ifdef CONTINUE_ON_EVENT_STOP
+                                                          or stop
+#endif
+                                                          );
+		    Tcontrol_t     can_register_access = not have_event;
+		    Tcontrol_t     no_execute          = (PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y]) or have_event);
+		    Tcontrol_t     read_ra             = (PORT_READ(in_RENAME_IN_READ_RA    [x][y]) and can_register_access);
+		    Tcontrol_t     read_rb             = (PORT_READ(in_RENAME_IN_READ_RB    [x][y]) and can_register_access);
+		    Tcontrol_t     read_rc             = (PORT_READ(in_RENAME_IN_READ_RC    [x][y]) and can_register_access);
+		    Tcontrol_t     write_rd            = (PORT_READ(in_RENAME_IN_WRITE_RD   [x][y]) and can_register_access);
+		    Tcontrol_t     write_re            = (PORT_READ(in_RENAME_IN_WRITE_RE   [x][y]) and can_register_access);
+// 		    Tcontrol_t     read_ra             = (PORT_READ(in_RENAME_IN_READ_RA    [x][y]));
+// 		    Tcontrol_t     read_rb             = (PORT_READ(in_RENAME_IN_READ_RB    [x][y]));
+// 		    Tcontrol_t     read_rc             = (PORT_READ(in_RENAME_IN_READ_RC    [x][y]));
+// 		    Tcontrol_t     write_rd            = (PORT_READ(in_RENAME_IN_WRITE_RD   [x][y]));
+// 		    Tcontrol_t     write_re            = (PORT_READ(in_RENAME_IN_WRITE_RE   [x][y]));
+                    
+                    log_printf(TRACE,Rename_select,FUNCTION,"      * have_event           : %d",have_event);
+                    log_printf(TRACE,Rename_select,FUNCTION,"      * no_execute (before)  : %d",PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y]));
+                    log_printf(TRACE,Rename_select,FUNCTION,"      * no_execute (after)   : %d",no_execute);
+                    
+		    if (_param->_have_port_front_end_id)
+		    PORT_WRITE(out_RENAME_OUT_FRONT_END_ID [i],front_end_id);
+		    if (_param->_have_port_context_id)
+                    PORT_WRITE(out_RENAME_OUT_CONTEXT_ID   [i],context_id);
+		    if (_param->_have_port_depth)
+		    PORT_WRITE(out_RENAME_OUT_DEPTH        [i],PORT_READ(in_RENAME_IN_DEPTH         [x][y]));
+		    PORT_WRITE(out_RENAME_OUT_TYPE         [i],PORT_READ(in_RENAME_IN_TYPE          [x][y]));
+		    PORT_WRITE(out_RENAME_OUT_OPERATION    [i],PORT_READ(in_RENAME_IN_OPERATION     [x][y]));
+		    PORT_WRITE(out_RENAME_OUT_NO_EXECUTE   [i],no_execute);
+		    PORT_WRITE(out_RENAME_OUT_IS_DELAY_SLOT[i],PORT_READ(in_RENAME_IN_IS_DELAY_SLOT [x][y]));
+#ifdef DEBUG        
+		    PORT_WRITE(out_RENAME_OUT_ADDRESS      [i],PORT_READ(in_RENAME_IN_ADDRESS       [x][y]));
+#endif              
+		    PORT_WRITE(out_RENAME_OUT_ADDRESS_NEXT [i],PORT_READ(in_RENAME_IN_ADDRESS_NEXT  [x][y]));
+		    PORT_WRITE(out_RENAME_OUT_HAS_IMMEDIAT [i],PORT_READ(in_RENAME_IN_HAS_IMMEDIAT  [x][y]));
+		    PORT_WRITE(out_RENAME_OUT_IMMEDIAT     [i],PORT_READ(in_RENAME_IN_IMMEDIAT      [x][y]));
+		    PORT_WRITE(out_RENAME_OUT_READ_RA      [i],read_ra);
+		    PORT_WRITE(out_RENAME_OUT_NUM_REG_RA   [i],PORT_READ(in_RENAME_IN_NUM_REG_RA    [x][y]));
+		    PORT_WRITE(out_RENAME_OUT_READ_RB      [i],read_rb);
+		    PORT_WRITE(out_RENAME_OUT_NUM_REG_RB   [i],PORT_READ(in_RENAME_IN_NUM_REG_RB    [x][y]));
+		    PORT_WRITE(out_RENAME_OUT_READ_RC      [i],read_rc);
+		    PORT_WRITE(out_RENAME_OUT_NUM_REG_RC   [i],PORT_READ(in_RENAME_IN_NUM_REG_RC    [x][y]));
+		    PORT_WRITE(out_RENAME_OUT_WRITE_RD     [i],write_rd);
+		    PORT_WRITE(out_RENAME_OUT_NUM_REG_RD   [i],PORT_READ(in_RENAME_IN_NUM_REG_RD    [x][y]));
+		    PORT_WRITE(out_RENAME_OUT_WRITE_RE     [i],write_re);
+		    PORT_WRITE(out_RENAME_OUT_NUM_REG_RE   [i],PORT_READ(in_RENAME_IN_NUM_REG_RE    [x][y]));
+		    PORT_WRITE(out_RENAME_OUT_EXCEPTION_USE[i],PORT_READ(in_RENAME_IN_EXCEPTION_USE [x][y]));
+		    PORT_WRITE(out_RENAME_OUT_EXCEPTION    [i],PORT_READ(in_RENAME_IN_EXCEPTION     [x][y]));
+                  }
 	      }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h	(revision 122)
@@ -107,10 +107,18 @@
   public    : SC_OUT(Tcontrol_t        )   ** out_RETIRE_LOAD_STORE_QUEUE_POINTER_VAL           ;//[nb_inst_retire]
   public    : SC_IN (Tcontrol_t        )   **  in_RETIRE_LOAD_STORE_QUEUE_POINTER_ACK           ;//[nb_inst_retire]
-//public    : SC_OUT(Ttype_t           )   ** out_RETIRE_LOAD_STORE_QUEUE_POINTER_TYPE          ;//[nb_inst_retire]
-//public    : SC_OUT(Toperation_t      )   ** out_RETIRE_LOAD_STORE_QUEUE_POINTER_OPERATION     ;//[nb_inst_retire]
 											        
   public    : SC_OUT(Tcontrol_t        )   ** out_RETIRE_REGISTER_TRANSLATION_VAL               ;//[nb_inst_retire]
   public    : SC_IN (Tcontrol_t        )   **  in_RETIRE_REGISTER_TRANSLATION_ACK               ;//[nb_inst_retire]
+
+    // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_VAL                              ;//[nb_front_end][nb_context]
+  public    : SC_OUT(Tcontrol_t        )  *** out_RETIRE_EVENT_ACK                              ;//[nb_front_end][nb_context]
 											        
+  public    : SC_OUT(Tcontrol_t        )  *** out_RETIRE_EVENT_LOAD_STORE_QUEUE_POINTER_VAL     ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_LOAD_STORE_QUEUE_POINTER_ACK     ;//[nb_front_end][nb_context]
+											        
+  public    : SC_OUT(Tcontrol_t        )  *** out_RETIRE_EVENT_REGISTER_TRANSLATION_VAL         ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_REGISTER_TRANSLATION_ACK         ;//[nb_front_end][nb_context]
+
     // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~		        
   public    : SC_IN (Tspr_t            )  ***  in_SPR_READ_SR                                   ;//[nb_front_end][nb_context]
@@ -153,9 +161,10 @@
 					       
 #ifdef SYSTEMC				       
-  public  : void        transition                (void);
-//public  : void        genMoore                  (void);
-  public  : void        genMealy_insert_valack    (void);
-  public  : void        genMealy_retire_valack    (void);
-  public  : void        genMealy_insert           (void);
+  public  : void        transition                   (void);
+//public  : void        genMoore                     (void);
+  public  : void        genMealy_insert_valack       (void);
+  public  : void        genMealy_retire_valack       (void);
+  public  : void        genMealy_retire_event_valack (void);
+  public  : void        genMealy_insert              (void);
 #endif					       
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp	(revision 122)
@@ -126,4 +126,21 @@
 	    << (*(in_RETIRE_REGISTER_TRANSLATION_ACK     [i]))
 	    ;
+
+# ifdef SYSTEMCASS_SPECIFIC
+	// List dependency information
+# endif    
+
+	log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> : Method - genMealy_retire_event_valack"),_name.c_str());
+
+	SC_METHOD (genMealy_retire_event_valack);
+	dont_initialize ();
+// 	sensitive << (*(in_CLOCK)).neg(); // don't need internal register
+	for (uint32_t i=0; i<_param->_nb_front_end; i++)
+	  for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+            sensitive 
+              << (*(in_RETIRE_EVENT_VAL                          [i][j]))
+              << (*(in_RETIRE_EVENT_LOAD_STORE_QUEUE_POINTER_ACK [i][j]))
+              << (*(in_RETIRE_EVENT_REGISTER_TRANSLATION_ACK     [i][j]))
+              ;
 
 # ifdef SYSTEMCASS_SPECIFIC
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp	(revision 122)
@@ -115,4 +115,18 @@
     }
 
+    // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      ALLOC2_INTERFACE_BEGIN("retire_event",OUT,NORTH,_("Retire_Event interface"),_param->_nb_front_end,_param->_nb_context[it1]);
+
+      _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_VAL                             ,"VAL"                                  ,Tcontrol_t        ,1,_param->_nb_front_end,_param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_ACK                             ,"ACK"                                  ,Tcontrol_t        ,1,_param->_nb_front_end,_param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_LOAD_STORE_QUEUE_POINTER_VAL    ,"LOAD_STORE_QUEUE_POINTER_VAL"         ,Tcontrol_t        ,1,_param->_nb_front_end,_param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_LOAD_STORE_QUEUE_POINTER_ACK    ,"LOAD_STORE_QUEUE_POINTER_ACK"         ,Tcontrol_t        ,1,_param->_nb_front_end,_param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_REGISTER_TRANSLATION_VAL        ,"REGISTER_TRANSLATION_VAL"             ,Tcontrol_t        ,1,_param->_nb_front_end,_param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_REGISTER_TRANSLATION_ACK        ,"REGISTER_TRANSLATION_ACK"             ,Tcontrol_t        ,1,_param->_nb_front_end,_param->_nb_context[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]);
+    }
+
     // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_deallocation.cpp	(revision 122)
@@ -72,4 +72,11 @@
         DELETE1_SIGNAL(out_RETIRE_REGISTER_TRANSLATION_VAL               ,_param->_nb_inst_retire,1);
         DELETE1_SIGNAL( in_RETIRE_REGISTER_TRANSLATION_ACK               ,_param->_nb_inst_retire,1);
+
+        DELETE2_SIGNAL( in_RETIRE_EVENT_VAL                              ,_param->_nb_front_end,_param->_nb_context[it1],1);
+        DELETE2_SIGNAL(out_RETIRE_EVENT_ACK                              ,_param->_nb_front_end,_param->_nb_context[it1],1);
+        DELETE2_SIGNAL(out_RETIRE_EVENT_LOAD_STORE_QUEUE_POINTER_VAL     ,_param->_nb_front_end,_param->_nb_context[it1],1);
+        DELETE2_SIGNAL( in_RETIRE_EVENT_LOAD_STORE_QUEUE_POINTER_ACK     ,_param->_nb_front_end,_param->_nb_context[it1],1);
+        DELETE2_SIGNAL(out_RETIRE_EVENT_REGISTER_TRANSLATION_VAL         ,_param->_nb_front_end,_param->_nb_context[it1],1);
+        DELETE2_SIGNAL( in_RETIRE_EVENT_REGISTER_TRANSLATION_ACK         ,_param->_nb_front_end,_param->_nb_context[it1],1);
 									 
         DELETE2_SIGNAL( in_SPR_READ_SR                                   ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_spr);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_retire_event_valack.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_retire_event_valack.cpp	(revision 122)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_retire_event_valack.cpp	(revision 122)
@@ -0,0 +1,73 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_ooo_engine {
+namespace ooo_engine {
+namespace rename_unit {
+namespace rename_unit_glue {
+
+
+#undef  FUNCTION
+#define FUNCTION "Rename_unit_Glue::genMealy_retire_event_valack"
+  void Rename_unit_Glue::genMealy_retire_event_valack (void)
+  {
+    log_begin(Rename_unit_Glue,FUNCTION);
+    log_function(Rename_unit_Glue,FUNCTION,_name.c_str());
+
+    for (uint32_t i=0; i<_param->_nb_front_end; i++)
+      for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+        {
+          Tcontrol_t VAL                          = PORT_READ(in_RETIRE_EVENT_VAL                          [i][j]);
+          Tcontrol_t LOAD_STORE_QUEUE_POINTER_ACK = PORT_READ(in_RETIRE_EVENT_LOAD_STORE_QUEUE_POINTER_ACK [i][j]);
+          Tcontrol_t REGISTER_TRANSLATION_ACK     = PORT_READ(in_RETIRE_EVENT_REGISTER_TRANSLATION_ACK     [i][j]);
+          
+          Tcontrol_t ACK                          = (//VAL                            and
+                                                       LOAD_STORE_QUEUE_POINTER_ACK   and
+                                                       REGISTER_TRANSLATION_ACK     
+                                                     );
+          Tcontrol_t LOAD_STORE_QUEUE_POINTER_VAL = (
+                                                       VAL                            and
+                                                     //LOAD_STORE_QUEUE_POINTER_ACK   and
+                                                       REGISTER_TRANSLATION_ACK     
+                                                     );
+          Tcontrol_t REGISTER_TRANSLATION_VAL     = (
+                                                       VAL                            and
+                                                       LOAD_STORE_QUEUE_POINTER_ACK //and
+                                                     //REGISTER_TRANSLATION_ACK     
+                                                     );
+          
+          PORT_WRITE(out_RETIRE_EVENT_ACK                          [i][j], ACK                         );
+          PORT_WRITE(out_RETIRE_EVENT_LOAD_STORE_QUEUE_POINTER_VAL [i][j], LOAD_STORE_QUEUE_POINTER_VAL);
+          PORT_WRITE(out_RETIRE_EVENT_REGISTER_TRANSLATION_VAL     [i][j], REGISTER_TRANSLATION_VAL    );
+          
+          log_printf(TRACE,Rename_unit_Glue,FUNCTION,"  * retire_event [%d][%d]",i,j);
+          log_printf(TRACE,Rename_unit_Glue,FUNCTION,"    * val (commit_unit)            (r) : %d",VAL                         );
+          log_printf(TRACE,Rename_unit_Glue,FUNCTION,"    * ack (commit_unit)            (w) : %d",ACK                         );
+          log_printf(TRACE,Rename_unit_Glue,FUNCTION,"    * register_translation_val     (w) : %d",REGISTER_TRANSLATION_VAL    );
+          log_printf(TRACE,Rename_unit_Glue,FUNCTION,"    * register_translation_ack     (r) : %d",REGISTER_TRANSLATION_ACK    );
+          log_printf(TRACE,Rename_unit_Glue,FUNCTION,"    * load_store_queue_pointer_val (w) : %d",LOAD_STORE_QUEUE_POINTER_VAL);
+          log_printf(TRACE,Rename_unit_Glue,FUNCTION,"    * load_store_queue_pointer_ack (r) : %d",LOAD_STORE_QUEUE_POINTER_ACK);
+        }
+    
+    log_end(Rename_unit_Glue,FUNCTION);
+  };
+  
+}; // end namespace rename_unit_glue
+}; // end namespace rename_unit
+}; // end namespace ooo_engine
+}; // end namespace multi_ooo_engine
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h	(revision 122)
@@ -114,4 +114,6 @@
   public    : SC_OUT(Tgeneral_data_t   )   ** out_INSERT_IMMEDIAT             ;//[nb_inst_insert]
   public    : SC_OUT(Tlsq_ptr_t        )   ** out_INSERT_STORE_QUEUE_PTR_WRITE;//[nb_inst_insert]
+  public    : SC_OUT(Tlsq_ptr_t        )   ** out_INSERT_STORE_QUEUE_PTR_READ ;//[nb_inst_insert]
+  public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_STORE_QUEUE_EMPTY    ;//[nb_inst_insert]
   public    : SC_OUT(Tlsq_ptr_t        )   ** out_INSERT_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_insert]
   public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_READ_RA              ;//[nb_inst_insert]
@@ -171,4 +173,6 @@
   public    : SC_OUT(Tcontrol_t        )  *** out_RETIRE_EVENT_ACK            ;//[nb_front_end][nb_context]
   public    : SC_IN (Tevent_state_t    )  ***  in_RETIRE_EVENT_STATE          ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_FLUSH          ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_STOP           ;//[nb_front_end][nb_context]
 
     // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp	(revision 122)
@@ -111,4 +111,6 @@
       ALLOC1_SIGNAL_OUT(out_INSERT_IMMEDIAT             ,"immediat"             ,Tgeneral_data_t   ,_param->_size_general_data          );
       ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr       );
+      ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr       );
+      ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1                                   );
       ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr        );
       ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION_USE        ,"exception_use"        ,Texception_t      ,_param->_size_exception_use         );
@@ -180,4 +182,6 @@
       _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_ACK           ,ACK,_param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE         ,"state"                ,Tevent_state_t    ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_FLUSH         ,"flush"                ,Tcontrol_t        ,1                        , _param->_nb_front_end, _param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STOP          ,"stop"                 ,Tcontrol_t        ,1                        , _param->_nb_front_end, _param->_nb_context[it1]);
 
       ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
@@ -452,6 +456,8 @@
                                        dest,"retire_event_"+toString(i)+"_"+toString(j));
 #endif     
-	    PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE",
-                                dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE");
+	    PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_FLUSH",
+                                dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_FLUSH");
+	    PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STOP",
+                                dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STOP");
           }
     }
@@ -637,5 +643,5 @@
         for (uint32_t j=0; j<_param->_nb_context[i]; j++)
           {
-            dest = _name;
+            dest = _name+"_glue";
             
 #ifdef POSITION
@@ -643,8 +649,15 @@
                                        dest,"retire_event_"+toString(i)+"_"+toString(j));
 #endif     
-            PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_VAL"  ,
-                                dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_VAL"  );
-	    PORT_MAP(_component,src ,"out_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_ACK"  ,
-                                dest,"out_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_ACK"  );
+            COMPONENT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+                     "_VAL"  ,
+                                     dest,"out_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_REGISTER_TRANSLATION_VAL"  );
+	    COMPONENT_MAP(_component,src ,"out_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+                     "_ACK"  ,
+                                     dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_REGISTER_TRANSLATION_ACK"  );
+
+            dest = _name;
+
+#ifdef POSITION
+            _component->interface_map (src ,"retire_event_"+toString(i)+"_"+toString(j),
+                                       dest,"retire_event_"+toString(i)+"_"+toString(j));
+#endif     
 	    PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE",
                                 dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE");
@@ -680,4 +693,8 @@
 	  PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_STORE_QUEUE_PTR_WRITE",
 		              dest,"out_INSERT_"+toString(i)+"_STORE_QUEUE_PTR_WRITE");
+	  PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_STORE_QUEUE_PTR_READ" ,
+		              dest,"out_INSERT_"+toString(i)+"_STORE_QUEUE_PTR_READ" );
+	  PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_STORE_QUEUE_EMPTY"    ,
+		              dest,"out_INSERT_"+toString(i)+"_STORE_QUEUE_EMPTY"    );
 	  if (_param->_have_port_load_queue_ptr)
 	  PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" ,
@@ -746,4 +763,28 @@
 	  //// in_RETIRE_OPERATION    - glue
 	}
+
+      for (uint32_t i=0; i<_param->_nb_front_end; i++)
+        for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+          {
+            dest = _name+"_glue";
+           
+#ifdef POSITION
+            _component->interface_map (src ,"retire_event_"+toString(i)+"_"+toString(j),
+                                       dest,"retire_event_"+toString(i)+"_"+toString(j));
+#endif     
+            COMPONENT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+                         "_VAL"  ,
+                                     dest,"out_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_LOAD_STORE_QUEUE_POINTER_VAL"  );
+	    COMPONENT_MAP(_component,src ,"out_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+                         "_ACK"  ,
+                                     dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_LOAD_STORE_QUEUE_POINTER_ACK"  );
+
+            dest = _name;
+            
+#ifdef POSITION
+            _component->interface_map (src ,"retire_event_"+toString(i)+"_"+toString(j),
+                                       dest,"retire_event_"+toString(i)+"_"+toString(j));
+#endif     
+	    PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE",
+                                dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE");
+          }
     }
 
@@ -844,4 +885,26 @@
 
       for (uint32_t i=0; i<_param->_nb_front_end; i++)
+        for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+          {
+            dest = _name;
+            
+#ifdef POSITION
+            _component->interface_map (src ,"retire_event_"+toString(i)+"_"+toString(j),
+                                       dest,"retire_event_"+toString(i)+"_"+toString(j));
+#endif      
+            
+            PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_VAL",
+		                dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_VAL");
+            PORT_MAP(_component,src ,"out_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_ACK",
+		                dest,"out_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_ACK");
+
+            //   out_RETIRE_EVENT_LOAD_STORE_QUEUE_POINTER_VAL          - load_store_pointer_unit
+            //    in_RETIRE_EVENT_LOAD_STORE_QUEUE_POINTER_ACK          - load_store_pointer_unit
+            //   out_RETIRE_EVENT_REGISTER_TRANSLATION_VAL              - register_translation_unit
+            //    in_RETIRE_EVENT_REGISTER_TRANSLATION_ACK              - register_translation_unit
+          }
+
+
+      for (uint32_t i=0; i<_param->_nb_front_end; i++)
 	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
 	  {
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp	(revision 122)
@@ -72,4 +72,6 @@
         DELETE1_SIGNAL(out_INSERT_IMMEDIAT             ,_param->_nb_inst_insert,_param->_size_general_data          );
         DELETE1_SIGNAL(out_INSERT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_insert,_param->_size_store_queue_ptr       );
+        DELETE1_SIGNAL(out_INSERT_STORE_QUEUE_PTR_READ ,_param->_nb_inst_insert,_param->_size_store_queue_ptr       );
+        DELETE1_SIGNAL(out_INSERT_STORE_QUEUE_EMPTY    ,_param->_nb_inst_insert,1                                   );
         DELETE1_SIGNAL(out_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_insert,_param->_size_load_queue_ptr        );
         DELETE1_SIGNAL(out_INSERT_EXCEPTION_USE        ,_param->_nb_inst_insert,_param->_size_exception_use         );
@@ -127,4 +129,6 @@
         DELETE2_SIGNAL(out_RETIRE_EVENT_ACK            ,_param->_nb_front_end, _param->_nb_context[it1],1);
         DELETE2_SIGNAL( in_RETIRE_EVENT_STATE          ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state);
+        DELETE2_SIGNAL( in_RETIRE_EVENT_FLUSH          ,_param->_nb_front_end, _param->_nb_context[it1],1);
+        DELETE2_SIGNAL( in_RETIRE_EVENT_STOP           ,_param->_nb_front_end, _param->_nb_context[it1],1);
         
         DELETE2_SIGNAL(in_SPR_READ_SR                  ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h	(revision 122)
@@ -105,4 +105,6 @@
   public    : SC_OUT(Toperation_t      )   ** out_ISSUE_OPERATION                  ;//[nb_inst_issue]
   public    : SC_OUT(Tlsq_ptr_t        )   ** out_ISSUE_STORE_QUEUE_PTR_WRITE      ;//[nb_inst_issue]
+  public    : SC_OUT(Tlsq_ptr_t        )   ** out_ISSUE_STORE_QUEUE_PTR_READ       ;//[nb_inst_issue]
+  public    : SC_OUT(Tcontrol_t        )   ** out_ISSUE_STORE_QUEUE_EMPTY          ;//[nb_inst_issue]
   public    : SC_OUT(Tlsq_ptr_t        )   ** out_ISSUE_LOAD_QUEUE_PTR_WRITE       ;//[nb_inst_issue]
   public    : SC_OUT(Tcontrol_t        )   ** out_ISSUE_HAS_IMMEDIAT               ;//[nb_inst_issue]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp	(revision 122)
@@ -100,4 +100,6 @@
       ALLOC1_SIGNAL_OUT (out_ISSUE_OPERATION                  ,"OPERATION"                 ,Toperation_t      ,_param->_size_operation              );
       ALLOC1_SIGNAL_OUT (out_ISSUE_STORE_QUEUE_PTR_WRITE      ,"STORE_QUEUE_PTR_WRITE"     ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr        );
+      ALLOC1_SIGNAL_OUT (out_ISSUE_STORE_QUEUE_PTR_READ       ,"STORE_QUEUE_PTR_READ"      ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr        );
+      ALLOC1_SIGNAL_OUT (out_ISSUE_STORE_QUEUE_EMPTY          ,"STORE_QUEUE_EMPTY"         ,Tcontrol_t        ,1                                    );
       ALLOC1_SIGNAL_OUT (out_ISSUE_LOAD_QUEUE_PTR_WRITE       ,"LOAD_QUEUE_PTR_WRITE"      ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr         );
       ALLOC1_SIGNAL_OUT (out_ISSUE_HAS_IMMEDIAT               ,"HAS_IMMEDIAT"              ,Tcontrol_t        ,1                                    );
@@ -561,4 +563,8 @@
             COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+                            "_STORE_QUEUE_PTR_WRITE",
                                      dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_STORE_QUEUE_PTR_WRITE");
+            COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+                            "_STORE_QUEUE_PTR_READ" ,
+                                     dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_STORE_QUEUE_PTR_READ" );
+            COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+                            "_STORE_QUEUE_EMPTY"    ,
+                                     dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_STORE_QUEUE_EMPTY"    );
             if (_param->_have_port_load_queue_ptr)
             COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+                            "_LOAD_QUEUE_PTR_WRITE" ,
@@ -655,5 +661,5 @@
           }
 
-        // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+        // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
         {
           std::vector<uint32_t>::iterator it = _param->_link_front_end_with_rename_unit[i].begin();
@@ -676,4 +682,8 @@
                     COMPONENT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(x)+"_"+toString(k)+"_STATE",
                                              dest,"out_RETIRE_EVENT_"+toString(j)+"_"+toString(k)+"_STATE");
+                    COMPONENT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(x)+"_"+toString(k)+"_FLUSH",
+                                             dest,"out_RETIRE_EVENT_"+toString(j)+"_"+toString(k)+"_FLUSH");
+                    COMPONENT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(x)+"_"+toString(k)+"_STOP",
+                                             dest,"out_RETIRE_EVENT_"+toString(j)+"_"+toString(k)+"_STOP");
                   }
                 x++;
@@ -850,5 +860,4 @@
             //  out_RETIRE_NUM_REG_RE_PHY_OLD        - component_rename_unit
             //  out_RETIRE_NUM_REG_RE_PHY_NEW        - component_rename_unit
-            //  out_RETIRE_EVENT_STATE               - component_rename_unit
     
             //  out_RETIRE_CONTEXT_ID                - component_rename_unit
@@ -872,4 +881,6 @@
         //  in_RETIRE_ACK         - rename_unit. in_RETIRE_ACK        
         // out_RETIRE_EVENT_STATE - rename_unit.out_RETIRE_EVENT_STATE
+        // out_RETIRE_EVENT_FLUSH - rename_unit.out_RETIRE_EVENT_FLUSH
+        // out_RETIRE_EVENT_STOP  - rename_unit.out_RETIRE_EVENT_STOP
   
 
@@ -1150,4 +1161,8 @@
             COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+            "_STORE_QUEUE_PTR_WRITE",
                                      dest,"out_INSERT_"  +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE");
+            COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+            "_STORE_QUEUE_PTR_READ" ,
+                                     dest,"out_INSERT_"  +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_STORE_QUEUE_PTR_READ" );
+            COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+            "_STORE_QUEUE_EMPTY"    ,
+                                     dest,"out_INSERT_"  +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_STORE_QUEUE_EMPTY"    );
             if (_param->_have_port_load_queue_ptr)
             COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+            "_LOAD_QUEUE_PTR_WRITE" ,
@@ -1212,4 +1227,8 @@
           COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_STORE_QUEUE_PTR_WRITE",
                                    dest,"out_REEXECUTE_"+toString(i)+"_STORE_QUEUE_PTR_WRITE");
+          COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_STORE_QUEUE_PTR_READ" ,
+                                   dest,"out_REEXECUTE_"+toString(i)+"_STORE_QUEUE_PTR_READ" );
+          COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_STORE_QUEUE_EMPTY"    ,
+                                   dest,"out_REEXECUTE_"+toString(i)+"_STORE_QUEUE_EMPTY"    );
           if (_param->_have_port_load_queue_ptr)
           COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" ,
@@ -1270,4 +1289,8 @@
           PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_STORE_QUEUE_PTR_WRITE",
                               dest,"out_ISSUE_"    +toString(i)+"_STORE_QUEUE_PTR_WRITE");
+          PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_STORE_QUEUE_PTR_READ" ,
+                              dest,"out_ISSUE_"    +toString(i)+"_STORE_QUEUE_PTR_READ" );
+          PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_STORE_QUEUE_EMPTY"    ,
+                              dest,"out_ISSUE_"    +toString(i)+"_STORE_QUEUE_EMPTY"    );
           if (_param->_have_port_load_queue_ptr)
           PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" ,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp	(revision 122)
@@ -63,4 +63,6 @@
         DELETE1_SIGNAL(out_ISSUE_OPERATION                  ,_param->_nb_inst_issue,_param->_size_operation              );
         DELETE1_SIGNAL(out_ISSUE_STORE_QUEUE_PTR_WRITE      ,_param->_nb_inst_issue,_param->_size_store_queue_ptr        );
+        DELETE1_SIGNAL(out_ISSUE_STORE_QUEUE_PTR_READ       ,_param->_nb_inst_issue,_param->_size_store_queue_ptr        );
+        DELETE1_SIGNAL(out_ISSUE_STORE_QUEUE_EMPTY          ,_param->_nb_inst_issue,1                                    );
         DELETE1_SIGNAL(out_ISSUE_LOAD_QUEUE_PTR_WRITE       ,_param->_nb_inst_issue,_param->_size_load_queue_ptr         );
         DELETE1_SIGNAL(out_ISSUE_HAS_IMMEDIAT               ,_param->_nb_inst_issue,1                                    );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp	(revision 122)
@@ -728,4 +728,8 @@
             COMPONENT_MAP(_component,src ,"out_ISSUE_"                           +toString(j)+"_STORE_QUEUE_PTR_WRITE",
                                      dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_STORE_QUEUE_PTR_WRITE");
+            COMPONENT_MAP(_component,src ,"out_ISSUE_"                           +toString(j)+"_STORE_QUEUE_PTR_READ" ,
+                                     dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_STORE_QUEUE_PTR_READ" );
+            COMPONENT_MAP(_component,src ,"out_ISSUE_"                           +toString(j)+"_STORE_QUEUE_EMPTY"    ,
+                                     dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_STORE_QUEUE_EMPTY"    );
             if (_param->_have_port_load_queue_ptr)
             COMPONENT_MAP(_component,src ,"out_ISSUE_"                           +toString(j)+"_LOAD_QUEUE_PTR_WRITE" ,
@@ -872,4 +876,8 @@
             COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_"                   +toString(j)+"_STORE_QUEUE_PTR_WRITE",
                                      dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_STORE_QUEUE_PTR_WRITE");
+            COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_"                   +toString(j)+"_STORE_QUEUE_PTR_READ" ,
+                                     dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_STORE_QUEUE_PTR_READ" );
+            COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_"                   +toString(j)+"_STORE_QUEUE_EMPTY"    ,
+                                     dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_STORE_QUEUE_EMPTY"    );
             if (_param->_have_port_load_queue_ptr)
             COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_"                   +toString(j)+"_LOAD_QUEUE_PTR_WRITE" ,
@@ -1324,4 +1332,6 @@
       //  in_ISSUE_OOO_ENGINE_OPERATION             - ooo_engine.out_ISSUE_OPERATION            
       //  in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE - ooo_engine.out_ISSUE_STORE_QUEUE_PTR_WRITE
+      //  in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ  - ooo_engine.out_ISSUE_STORE_QUEUE_PTR_READ 
+      //  in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY     - ooo_engine.out_ISSUE_STORE_QUEUE_EMPTY    
       //  in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE  - ooo_engine.out_ISSUE_LOAD_QUEUE_PTR_WRITE 
       //  in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT          - ooo_engine.out_ISSUE_HAS_IMMEDIAT         
@@ -1347,4 +1357,6 @@
       // out_ISSUE_EXECUTE_LOOP_TYPE                  - execute_loop. in_EXECUTE_LOOP_IN_TYPE                 
       // out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE - execute_loop. in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE
+      // out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_READ  - execute_loop. in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_READ 
+      // out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_EMPTY     - execute_loop. in_EXECUTE_LOOP_IN_STORE_QUEUE_EMPTY    
       // out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE  - execute_loop. in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE 
       // out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT          - execute_loop. in_EXECUTE_LOOP_IN_HAS_IMMEDIAT         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp	(revision 122)
@@ -59,10 +59,16 @@
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
-    DELETE0(_component_glue);
-    DELETE0(_component_dcache_access);
-    DELETE0(_component_icache_access);
-    DELETE1(_component_execute_loop, _param->_nb_execute_loop);
-    DELETE1(_component_ooo_engine  , _param->_nb_ooo_engine);
-    DELETE1(_component_front_end   , _param->_nb_front_end);
+    delete    _component_glue;
+    delete    _component_dcache_access;
+    delete    _component_icache_access;
+    for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
+    delete    _component_execute_loop [i];
+    delete [] _component_execute_loop;
+    for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
+    delete    _component_ooo_engine [i];
+    delete [] _component_ooo_engine;
+    for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+    delete    _component_front_end [i];
+    delete [] _component_front_end;
 
     delete _component;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp	(revision 121)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp	(revision 122)
@@ -2181,6 +2181,12 @@
     log_begin(Core,FUNCTION);
 
+    for (uint32_t i=0; i<_nb_front_end; ++i)
+    delete    _param_front_end [i];
     delete [] _param_front_end;
+    for (uint32_t i=0; i<_nb_ooo_engine; ++i)
+    delete    _param_ooo_engine [i];
     delete [] _param_ooo_engine;
+    for (uint32_t i=0; i<_nb_execute_loop; ++i)
+    delete    _param_execute_loop [i];
     delete [] _param_execute_loop;
     delete    _param_icache_access;
