Changeset 123 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src

Timestamp:

Jun 8, 2009, 10:43:30 PM (15 years ago)

Author:

rosiere

Message:

1) Fix performance
2) add auto generation to SPECINT2000
3) add reset in genMoore and genMealy

Location:

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src

Files:

• Dcache_Access.cpp (modified) (1 diff)
• Dcache_Access_genMealy_req.cpp (modified) (2 diffs)
• Dcache_Access_genMealy_rsp.cpp (modified) (2 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access.cpp

@@ -37 +37 @@
     usage_environment(_usage);
 
-#if DEBUG_Dcache_Access == true
-    log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Dcache_Access == true
+//     log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> Parameters"),_name.c_str());
 
-    std::cout << *param << std::endl;
-#endif    
+//     std::cout << *param << std::endl;
+// #endif    
 
     log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> : Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_req.cpp

@@ -21 +21 @@
     log_begin(Dcache_Access,FUNCTION);
 
+    if (PORT_READ(in_NRESET))
+      {
     Tcontrol_t dcache_req_val [_param->_nb_dcache_port];
     for (uint32_t i=0; i<_param->_nb_dcache_port; ++i)
@@ -105 +107 @@
         for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k)
           PORT_WRITE(out_LSQ_REQ_ACK [i][j][k], lsq_req_ack [i][j][k]);
+      }
+
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_dcache_port; ++i)
+          PORT_WRITE(out_DCACHE_REQ_VAL [i], 0);
+        
+        for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
+          for (uint32_t j=0; j<_param->_nb_load_store_unit[i]; ++j)
+            for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k)
+              PORT_WRITE(out_LSQ_REQ_ACK [i][j][k], 0);
+      }
 
     log_end(Dcache_Access,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_rsp.cpp

@@ -21 +21 @@
     log_begin(Dcache_Access,FUNCTION);
 
+    if (PORT_READ(in_NRESET))
+      {
     Tcontrol_t lsq_rsp_val [_param->_nb_execute_loop][_param->_max_nb_load_store_unit][_param->_max_nb_cache_access];
     for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
@@ -87 +89 @@
         for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k)
           PORT_WRITE(out_LSQ_RSP_VAL [i][j][k], lsq_rsp_val [i][j][k]);
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_dcache_port; ++i)
+          PORT_WRITE(out_DCACHE_RSP_ACK [i],0);
+
+        for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
+          for (uint32_t j=0; j<_param->_nb_load_store_unit[i]; ++j)
+            for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k)
+              PORT_WRITE(out_LSQ_RSP_VAL [i][j][k], 0);
+      }
 
     log_end(Dcache_Access,FUNCTION);