Changeset 124 for trunk/IPs/systemC/Environment/src
- Timestamp:
- Jun 17, 2009, 2:11:25 PM (16 years ago)
- Location:
- trunk/IPs/systemC/Environment/src
- Files:
-
- 2 edited
-
Environment_genMoore.cpp (modified) (2 diffs)
-
Environment_transition.cpp (modified) (8 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/Environment/src/Environment_genMoore.cpp
r88 r124 30 30 //----------------------------------------------------------------------------- 31 31 { 32 // init 32 33 for (uint32_t j = 0; j < param->icache_dedicated_nb_port [i]; j ++) 34 icache_rsp_val [i][j] = 0; 35 36 for (uint32_t j = 0; j+1 < component_buffer_irsp [i]->nb_slot_use(); j ++) 33 37 { 34 38 // Test the number of element in the respons's buffer 35 if (j >= component_buffer_irsp [i]->nb_slot_use()) 36 { 37 icache_rsp_val [i][j] = 0; // No respons 38 } 39 else 40 { 41 queue::slot_t<irsp_t*> slot = component_buffer_irsp [i]->read(j); 39 40 queue::slot_t<irsp_t*> slot = component_buffer_irsp [i]->read(j); 41 42 uint32_t port = slot._data->port; 43 44 bool val = ((slot._delay == 0) and (icache_rsp_val [i][port] == 0)); 45 46 _cout(ENVIRONMENT, "buffer_irsp [%d][%d] - delay %d - port %d\n",i,j,slot._delay,port); 47 48 49 if (val) 50 { 51 _cout(ENVIRONMENT, "ICACHE_RSP [%d][%d] - respons valid\n",i,port); 52 53 icache_rsp_val [i][port] = 1; 54 55 ICACHE_RSP_CONTEXT_ID [i][port]->write(slot._data->trdid); // TODO : test if exist 56 ICACHE_RSP_PACKET_ID [i][port]->write(slot._data->pktid); // TODO : test if exist 57 ICACHE_RSP_ERROR [i][port]->write(slot._data->error); 42 58 43 bool val = (slot._delay == 0); 44 45 icache_rsp_val [i][j] = (val); // respons if have a result 46 47 if (val) 48 { 49 ICACHE_RSP_CONTEXT_ID [i][j]->write(slot._data->trdid); // TODO : test if exist 50 ICACHE_RSP_PACKET_ID [i][j]->write(slot._data->pktid); // TODO : test if exist 51 ICACHE_RSP_ERROR [i][j]->write(slot._data->error); 52 53 for (uint32_t k = 0; k < param->iaccess_nb_instruction[i]; k ++) 54 { 55 Ticache_instruction_t data = 0; 56 57 atoi (slot._data->data[k], data, param->iaccess_size_instruction[i]/8); 58 59 ICACHE_RSP_INSTRUCTION [i][j][k]->write(data); 60 } 61 } 62 } 63 64 ICACHE_RSP_VAL [i][j]->write (icache_rsp_val [i][j]); 65 } 59 for (uint32_t k = 0; k < param->iaccess_nb_instruction[i]; k ++) 60 { 61 Ticache_instruction_t data = 0; 62 63 atoi (slot._data->data[k], data, param->iaccess_size_instruction[i]/8); 64 65 ICACHE_RSP_INSTRUCTION [i][port][k]->write(data); 66 } 67 } 68 } 69 70 for (uint32_t j = 0; j < param->icache_dedicated_nb_port [i]; j ++) 71 ICACHE_RSP_VAL [i][j]->write (icache_rsp_val [i][j]); 66 72 } 67 73 … … 103 109 if (val) 104 110 { 111 _cout(ENVIRONMENT, "DCACHE_RSP [%d][%d] - respons valid\n",i,j); 112 105 113 DCACHE_RSP_CONTEXT_ID [i][j]->write(slot._data->trdid); // TODO : test if exist 106 114 DCACHE_RSP_PACKET_ID [i][j]->write(slot._data->pktid); // TODO : test if exist -
trunk/IPs/systemC/Environment/src/Environment_transition.cpp
r123 r124 44 44 if (ICACHE_REQ_VAL [i][j]->read() and icache_req_ack [i][j]) 45 45 { 46 _cout(ENVIRONMENT, "ICACHE_REQ [%d] : Transaction accepted\n",i);46 _cout(ENVIRONMENT, "ICACHE_REQ [%d][%d] : Transaction accepted\n",i,j); 47 47 48 48 Ticache_context_t context = ICACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence … … 83 83 { 84 84 uint32_t addr = address+k*(size); 85 _cout(ENVIRONMENT," * addr : %.8x \n",addr);85 _cout(ENVIRONMENT," * addr : %.8x - ",addr); 86 86 87 87 bus_error |= !component_data->read(addr,size,read_iram[k]); … … 93 93 } 94 94 95 _cout(ENVIRONMENT," * inst :");95 //_cout(ENVIRONMENT," * inst : "); 96 96 for (int32_t cpt=(param->iaccess_size_instruction[i]/8)-1; cpt>=0; --cpt) 97 97 __cout(ENVIRONMENT, "%.2x",0xff&static_cast<uint32_t>(read_iram[k][cpt])); … … 144 144 _cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i); 145 145 146 irsp_t * rsp = new irsp_t(context, 146 irsp_t * rsp = new irsp_t(j, 147 context, 147 148 packet, 148 149 param->iaccess_nb_instruction[i], … … 163 164 if (DCACHE_REQ_VAL [i][j]->read() and dcache_req_ack [i][j]) 164 165 { 165 _cout(ENVIRONMENT, "DCACHE_REQ [%d] : Transaction accepted\n",i);166 _cout(ENVIRONMENT, "DCACHE_REQ [%d][%d] : Transaction accepted\n",i,j); 166 167 167 168 Tdcache_context_t context = DCACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence … … 339 340 340 341 uint32_t num_ramlock = (address - entity.segment->getBase()); // Char access 342 uint32_t num_lock = num_ramlock % (param->daccess_size_data [i]/8); 341 343 uint32_t num_component_ramlock = entity.segment->getIndex(); 342 344 343 _cout(ENVIRONMENT," * num_ramlock : %d\n",num_ramlock ); 344 _cout(ENVIRONMENT," * num_component_ramlock : %d\n",num_component_ramlock); 345 // _cout(ENVIRONMENT," * num_ramlock : %d\n",num_ramlock ); 346 // _cout(ENVIRONMENT," * num_lock : %d\n",num_lock ); 347 // _cout(ENVIRONMENT," * num_component_ramlock : %d\n",num_component_ramlock); 348 _cout(true," * num_ramlock : %d\n",num_ramlock ); 349 _cout(true," * num_lock : %d\n",num_lock ); 350 _cout(true," * num_component_ramlock : %d\n",num_component_ramlock); 345 351 346 352 // No test : because out of range … … 352 358 353 359 memset (read_dram[0],0,size); 354 360 355 361 if (must_read == true) 356 read_dram [0][ 0] = static_cast<char>(component_ramlock [num_component_ramlock]->read (num_ramlock));362 read_dram [0][num_lock] = static_cast<char>(component_ramlock [num_component_ramlock]->read (num_ramlock)); 357 363 if (must_write == true) 358 read_dram [0][0] = static_cast<char>(component_ramlock [num_component_ramlock]->write(num_ramlock)); 364 read_dram [0][num_lock] = static_cast<char>(component_ramlock [num_component_ramlock]->write(num_ramlock)); 365 366 _cout(true," * lock : %d\n",(int)read_dram [0][num_lock]); 367 // _cout(ENVIRONMENT," * lock : %d\n",(int)read_dram [0][num_lock]); 359 368 360 369 break; … … 506 515 507 516 // Simplification : the size of a line is a multiple of size_iword (no test) 508 drsp_t * rsp = new drsp_t(context, 517 drsp_t * rsp = new drsp_t(j, 518 context, 509 519 packet, 510 520 1,
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