Changeset 124 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src

Timestamp:

Jun 17, 2009, 2:11:25 PM (15 years ago)

Author:

rosiere

Message:

1) Add test and configuration
2) Fix Bug
3) Add log file in load store unit
4) Fix Bug in environment

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (modified) (11 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp

@@ -20 +20 @@
 #define MANAGE_EVENT MANAGE_EVENT_NO_WAIT
 
+#define PRIORITY_MISS_LOAD   3
+#define PRIORITY_MISS_BRANCH 2
+#define PRIORITY_EXCEPTION   1
+#define PRIORITY_NONE        0
+
 #define get_priority(x) \
   (((state == CONTEXT_STATE_KO_MISS_LOAD_ADDR                  ) or  \
@@ -25 +30 @@
     (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR       ) or  \
     (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND    ) or  \
-    (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE))?3: \
+    (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE))?PRIORITY_MISS_LOAD: \
   (((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR                ) or  \
     (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND             ) or  \
-    (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE         ))?2: \
-   ((state == EVENT_TYPE_EXCEPTION)?1:                           \
+    (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE         ))?PRIORITY_MISS_BRANCH: \
+   ((state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION:                           \
     0)))
 
@@ -299 +304 @@
               // priority : miss_load > miss_branch > excep > spr/sync
               uint8_t    priority0  = get_priority(state);
-              uint8_t    priority1  = 2; // miss
+              uint8_t    priority1  = PRIORITY_MISS_BRANCH; // miss
 
               // is_valid = can modify local information
@@ -306 +311 @@
               bool       is_valid   = ((state == CONTEXT_STATE_OK) or
                                        (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or
+//                                     (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or
                                        (depth1< depth0) or
                                        ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth
+
+              bool       is_invalid = priority0 == PRIORITY_MISS_LOAD;
 
 #ifdef DEBUG_TEST
@@ -327 +334 @@
               log_printf(TRACE,Context_State,FUNCTION,"  * is_valid    : %d",is_valid  );
 
-              if (is_valid)
+              if (is_valid and not is_invalid)
                 {
 //                reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
@@ -333 +340 @@
                   if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE)
                     {
+// #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)
+//                       reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR;
+// #else
                       reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND;
+// #endif
                     }
                   else
@@ -346 +357 @@
                         reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
                       else
-                        reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_WAITEND;
+                        {
+// #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)
+//                           reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
+// #else
+                          reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_WAITEND;
+// #endif
+                        }
 
                       reg_EVENT_ADDRESS          [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC  [i])+1; // address delay slot
@@ -386 +403 @@
               // priority : miss_load > miss_branch > excep > spr/sync
               uint8_t    priority0  = get_priority(state);
-              uint8_t    priority1  = 2; // miss
+              uint8_t    priority1  = PRIORITY_MISS_BRANCH; // miss
 
               // is_valid = can modify local information
@@ -440 +457 @@
               // miss_load > miss_branch > excep > spr/sync
               uint8_t    priority0  = get_priority(state);
-              uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?1:0;
+              uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION:PRIORITY_NONE;
 
               // is_valid = can modify local information
@@ -623 +640 @@
                         case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND :
                           {
+// #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)
+//                             state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR;
+// #else
                             state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND;
+// #endif
                             break;
                           }
                         default :
                           {
+// #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)
+//                             state_next = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
+// #else
                             state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND;
+// #endif
                             break;
                           }
@@ -688 +713 @@
               throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i));
           }
+
+
+#if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)
+        for (uint32_t i=0; i<_param->_nb_context; i++)
+          switch (reg_STATE [i])
+            {
+            case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND          : reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR         ; break;
+            case CONTEXT_STATE_KO_MISS_LOAD_WAITEND            : reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR           ; break;
+            case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; break;
+            default : break;
+            }
+#endif
       }