Index: trunk/IPs/systemC/Environment/src/Environment.cpp =================================================================== --- trunk/IPs/systemC/Environment/src/Environment.cpp (revision 127) +++ trunk/IPs/systemC/Environment/src/Environment.cpp (revision 128) @@ -1,3 +1,4 @@ #include "../include/Environment.h" +#include "../../processor/Morpheo/Common/include/ToString.h" using namespace morpheo; @@ -13,8 +14,8 @@ component_tty = new tty::TTY * [param->nb_component_tty]; for (uint32_t i=0; inb_component_tty; i++) - component_tty [i] = new tty::TTY ("tty_"+i ,param->param_tty [i]); + component_tty [i] = new tty::TTY ("tty_"+morpheo::toString(i),param->param_tty [i]); component_ramlock = new ramlock::RamLock * [param->nb_component_ramlock]; for (uint32_t i=0; inb_component_ramlock; i++) - component_ramlock [i] = new ramlock::RamLock ("ramlock_"+i,param->param_ramlock [i]); + component_ramlock [i] = new ramlock::RamLock ("ramlock_"+morpheo::toString(i),param->param_ramlock [i]); component_sim2os = new sim2os::Sim2OS ("sim2os" ,param->param_sim2os ); component_data = new data::Data ("data" ,param->param_data ); @@ -186,6 +187,8 @@ icache_req_ack = new Tcontrol_t * [param->nb_entity]; icache_rsp_val = new Tcontrol_t * [param->nb_entity]; + icache_rsp_num = new uint32_t * [param->nb_entity]; dcache_req_ack = new Tcontrol_t * [param->nb_entity]; dcache_rsp_val = new Tcontrol_t * [param->nb_entity]; + dcache_rsp_num = new uint32_t * [param->nb_entity]; for (uint32_t i=0; inb_entity; i++) @@ -193,6 +196,8 @@ icache_req_ack [i] = new Tcontrol_t [param->icache_dedicated_nb_port[i]]; icache_rsp_val [i] = new Tcontrol_t [param->icache_dedicated_nb_port[i]]; + icache_rsp_num [i] = new uint32_t [param->icache_dedicated_nb_port[i]]; dcache_req_ack [i] = new Tcontrol_t [param->dcache_dedicated_nb_port[i]]; dcache_rsp_val [i] = new Tcontrol_t [param->dcache_dedicated_nb_port[i]]; + dcache_rsp_num [i] = new uint32_t [param->dcache_dedicated_nb_port[i]]; } @@ -214,12 +219,16 @@ delete [] icache_req_ack [i]; delete [] icache_rsp_val [i]; + delete [] icache_rsp_num [i]; delete [] dcache_req_ack [i]; delete [] dcache_rsp_val [i]; + delete [] dcache_rsp_num [i]; } delete [] icache_req_ack; delete [] icache_rsp_val; + delete [] icache_rsp_num; delete [] dcache_req_ack; delete [] dcache_rsp_val; + delete [] dcache_rsp_num; delete CLOCK ; @@ -243,8 +252,8 @@ for (uint32_t k=0; kiaccess_nb_instruction[i]; k++) - delete ICACHE_RSP_INSTRUCTION [i][j][k]; - + delete ICACHE_RSP_INSTRUCTION [i][j][k]; delete [] ICACHE_RSP_INSTRUCTION [i][j]; } + delete [] ICACHE_REQ_VAL [i]; delete [] ICACHE_REQ_ACK [i]; @@ -276,5 +285,5 @@ for (uint32_t i=0; inb_entity; i++) { - for (uint32_t j=0; jicache_dedicated_nb_port[i]; j++) + for (uint32_t j=0; jdcache_dedicated_nb_port[i]; j++) { delete DCACHE_REQ_VAL [i][j]; Index: trunk/IPs/systemC/Environment/src/Environment_genMoore.cpp =================================================================== --- trunk/IPs/systemC/Environment/src/Environment_genMoore.cpp (revision 127) +++ trunk/IPs/systemC/Environment/src/Environment_genMoore.cpp (revision 128) @@ -1,3 +1,4 @@ #include "../include/Environment.h" +#include "../../processor/Morpheo/Common/include/Systemc.h" using namespace morpheo; @@ -7,4 +8,6 @@ void Environment::genMoore (void) { + _cout(ENVIRONMENT, " [%d] \n",static_cast(simulation_cycle())); + //Scan all entity and for each entity scan all port for (uint32_t i = 0; i < param->nb_entity; i++) @@ -32,7 +35,10 @@ // init for (uint32_t j = 0; j < param->icache_dedicated_nb_port [i]; j ++) - icache_rsp_val [i][j] = 0; + { + icache_rsp_val [i][j] = 0; + icache_rsp_num [i][j] = 0; + } - _cout(ENVIRONMENT, "buffer_irsp [%d] : nb_slot_use %d\n",i,component_buffer_irsp [i]->nb_slot_use()); + _cout(ENVIRONMENT, " * buffer_irsp [%d] : nb_slot_use %d\n",i,component_buffer_irsp [i]->nb_slot_use()); for (uint32_t j = 0; j+1 <= component_buffer_irsp [i]->nb_slot_use(); j ++) { @@ -45,12 +51,13 @@ bool val = ((slot._delay == 0) and (icache_rsp_val [i][port] == 0)); - _cout(ENVIRONMENT, "buffer_irsp [%d][%d] - delay %d - port %d\n",i,j,slot._delay,port); + _cout(ENVIRONMENT, " * buffer_irsp [%d][%d] - delay %d - port %d\n",i,j,slot._delay,port); if (val) { - _cout(ENVIRONMENT, "ICACHE_RSP [%d][%d] - respons valid\n",i,port); + _cout(ENVIRONMENT, " * ICACHE_RSP [%d][%d] - respons valid\n",i,port); icache_rsp_val [i][port] = 1; + icache_rsp_num [i][port] = j; ICACHE_RSP_CONTEXT_ID [i][port]->write(slot._data->trdid); // TODO : test if exist @@ -93,35 +100,38 @@ //----------------------------------------------------------------------------- { + // init for (uint32_t j = 0; j < param->dcache_dedicated_nb_port [i]; j ++) + { + dcache_rsp_val [i][j] = 0; + dcache_rsp_num [i][j] = 0; + } + + for (uint32_t j = 0; j+1 <= component_buffer_drsp [i]->nb_slot_use(); j ++) { - // Test the number of element in the respons's buffer - if (j >= component_buffer_drsp [i]->nb_slot_use()) - { - dcache_rsp_val [i][j] = 0; // No respons - } - else - { - queue::slot_t slot = component_buffer_drsp [i]->read(j); + queue::slot_t slot = component_buffer_drsp [i]->read(j); + + uint32_t port = slot._data->port; + bool val = ((slot._delay == 0) and (dcache_rsp_val [i][port] == 0)); + + if (val) + { + _cout(ENVIRONMENT, " * DCACHE_RSP [%d][%d] - respons valid\n",i,port); + + dcache_rsp_val [i][port] = 1; + dcache_rsp_num [i][port] = j; + + DCACHE_RSP_CONTEXT_ID [i][port]->write(slot._data->trdid); // TODO : test if exist + DCACHE_RSP_PACKET_ID [i][port]->write(slot._data->pktid); // TODO : test if exist + DCACHE_RSP_ERROR [i][port]->write(slot._data->error); + + Tdcache_data_t data = 0; + atoi (slot._data->data[0], data, param->daccess_size_data[i]/8); + + DCACHE_RSP_RDATA [i][port]->write(data); + } + } - bool val = (slot._delay == 0); // respons if have a result - - dcache_rsp_val [i][j] = (val); // respons if have a result - - if (val) - { - _cout(ENVIRONMENT, "DCACHE_RSP [%d][%d] - respons valid\n",i,j); - - DCACHE_RSP_CONTEXT_ID [i][j]->write(slot._data->trdid); // TODO : test if exist - DCACHE_RSP_PACKET_ID [i][j]->write(slot._data->pktid); // TODO : test if exist - DCACHE_RSP_ERROR [i][j]->write(slot._data->error); - - Tdcache_data_t data = 0; - atoi (slot._data->data[0], data, param->daccess_size_data[i]/8); - - DCACHE_RSP_RDATA [i][j]->write(data); - } - } - DCACHE_RSP_VAL [i][j]->write (dcache_rsp_val [i][j]); - } + for (uint32_t j = 0; j < param->dcache_dedicated_nb_port [i]; j ++) + DCACHE_RSP_VAL [i][j]->write (dcache_rsp_val [i][j]); } } Index: trunk/IPs/systemC/Environment/src/Environment_transition.cpp =================================================================== --- trunk/IPs/systemC/Environment/src/Environment_transition.cpp (revision 127) +++ trunk/IPs/systemC/Environment/src/Environment_transition.cpp (revision 128) @@ -3,4 +3,5 @@ #define CYCLE_MAX 0 #include "../../processor/Morpheo/Common/include/Test.h" +#include "../../processor/Morpheo/Common/include/Systemc.h" using namespace morpheo; @@ -10,4 +11,6 @@ void Environment::transition (void) { + _cout(ENVIRONMENT, " [%d] \n",static_cast(simulation_cycle())); + if (NRESET->read() == 0) { @@ -21,9 +24,17 @@ for (uint32_t i = 0; i < param->nb_entity; i++) for (int32_t j=param->icache_dedicated_nb_port [i]-1; j>=0; j--) - if (icache_rsp_val [i][j] and ICACHE_RSP_ACK [i][j]->read()) - { - delete component_buffer_irsp [i]->read(j)._data; - component_buffer_irsp [i]->pop(j); - } + { + _cout(ENVIRONMENT, " * ICACHE_RSP [%d][%d]\n",i,j); + + if (icache_rsp_val [i][j] and ICACHE_RSP_ACK [i][j]->read()) + { + _cout(ENVIRONMENT, " * ICACHE_RSP [%d][%d] : Transaction accepted\n",i,j); + + uint32_t num = icache_rsp_num [i][j]; + + delete component_buffer_irsp [i]->read(num)._data; + component_buffer_irsp [i]->pop(num); + } + } //============================================================================= //===== [ DCACHE - RESPONS ]=================================================== @@ -31,9 +42,16 @@ for (uint32_t i = 0; i < param->nb_entity; i++) for (int32_t j=param->dcache_dedicated_nb_port [i]-1; j>=0; j--) - if (dcache_rsp_val [i][j] and DCACHE_RSP_ACK [i][j]->read()) - { - delete component_buffer_drsp [i]->read(j)._data; - component_buffer_drsp [i]->pop(j); - } + { + _cout(ENVIRONMENT, " * DCACHE_RSP [%d][%d]\n",i,j); + if (dcache_rsp_val [i][j] and DCACHE_RSP_ACK [i][j]->read()) + { + _cout(ENVIRONMENT, " * DCACHE_RSP [%d][%d] : Transaction accepted\n",i,j); + + uint32_t num = dcache_rsp_num [i][j]; + + delete component_buffer_drsp [i]->read(num)._data; + component_buffer_drsp [i]->pop(num); + } + } //============================================================================= @@ -44,5 +62,5 @@ if (ICACHE_REQ_VAL [i][j]->read() and icache_req_ack [i][j]) { - _cout(ENVIRONMENT, "ICACHE_REQ [%d][%d] : Transaction accepted\n",i,j); + _cout(ENVIRONMENT, " * ICACHE_REQ [%d][%d] : Transaction accepted\n",i,j); Ticache_context_t context = ICACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence @@ -52,10 +70,10 @@ uint32_t size = (param->iaccess_size_address [i]+2)/8; - _cout(ENVIRONMENT," * information\n"); - _cout(ENVIRONMENT," * context : %d\n" ,static_cast(context)); - _cout(ENVIRONMENT," * packet : %d\n" ,static_cast(packet )); - _cout(ENVIRONMENT," * address : %.x\n",static_cast(address)); - _cout(ENVIRONMENT," * type : %d\n" ,static_cast(type )); - _cout(ENVIRONMENT," * size : %d\n" ,static_cast(size )); + _cout(ENVIRONMENT," * information\n"); + _cout(ENVIRONMENT," * context : %d\n" ,static_cast(context)); + _cout(ENVIRONMENT," * packet : %d\n" ,static_cast(packet )); + _cout(ENVIRONMENT," * address : %.x\n",static_cast(address)); + _cout(ENVIRONMENT," * type : %d\n" ,static_cast(type )); + _cout(ENVIRONMENT," * size : %d\n" ,static_cast(size )); // search the entity @@ -72,5 +90,5 @@ (entity.segment->getType() == data::TYPE_TARGET_MEMORY)) { - _cout(ENVIRONMENT," * OK !\n"); + _cout(ENVIRONMENT," * OK !\n"); bus_error = false; uncached = entity.segment->getUncached(); @@ -78,10 +96,10 @@ if (must_read == true) // Test if must read the ram { - _cout(ENVIRONMENT," * must read\n"); + _cout(ENVIRONMENT," * must read\n"); // Read all instruction for (unsigned int k=0; kiaccess_nb_instruction[i]; k++) { uint32_t addr = address+k*(size); - _cout(ENVIRONMENT," * addr : %.8x - ",addr); + _cout(ENVIRONMENT," * addr : %.8x - ",addr); bus_error |= !component_data->read(addr,size,read_iram[k]); @@ -102,8 +120,8 @@ else { - _cout(ENVIRONMENT, " * KO !\n"); - _cout(ENVIRONMENT, " * present : %d\n",entity.present); + _cout(ENVIRONMENT, " * KO !\n"); + _cout(ENVIRONMENT, " * present : %d\n",entity.present); if (entity.present) - _cout(ENVIRONMENT, " * type : %d must be data::TYPE_TARGET_MEMORY (%d)\n",entity.segment->getType(), data::TYPE_TARGET_MEMORY); + _cout(ENVIRONMENT, " * type : %d must be data::TYPE_TARGET_MEMORY (%d)\n",entity.segment->getType(), data::TYPE_TARGET_MEMORY); // entity is not present, or is present but is not a memory : have a bus error @@ -121,19 +139,19 @@ cache_type.direction); - _cout(ENVIRONMENT, " * latence : %d\n",latence); + _cout(ENVIRONMENT, " * latence : %d\n",latence); // If is a respons -> compute the latence and push in the write_buffer if (must_ack or (must_ack_on_error and bus_error)) { - _cout(ENVIRONMENT, " * must ack\n"); + _cout(ENVIRONMENT, " * must ack\n"); if (bus_error == true) { - _cout(ENVIRONMENT," * Icache : have a bus error\n"); - _cout(ENVIRONMENT," * entity : %d\n",i); - _cout(ENVIRONMENT," * port : %d\n",j); - _cout(ENVIRONMENT," * req_addr : %x\n",address); - _cout(ENVIRONMENT," * req_trdid : %d\n",context); - _cout(ENVIRONMENT," * req_pktid : %d\n",packet ); + _cout(ENVIRONMENT," * Icache : have a bus error\n"); + _cout(ENVIRONMENT," * entity : %d\n",i); + _cout(ENVIRONMENT," * port : %d\n",j); + _cout(ENVIRONMENT," * req_addr : %x\n",address); + _cout(ENVIRONMENT," * req_trdid : %d\n",context); + _cout(ENVIRONMENT," * req_pktid : %d\n",packet ); // Write in instruction [0] the bad address (only 32bit ....) @@ -142,5 +160,5 @@ // Simplification : the size of a line is a multiple of size_iword (no test) - _cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i); + _cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i); irsp_t * rsp = new irsp_t(j, @@ -154,5 +172,5 @@ } - _cout(ENVIRONMENT, " * End request\n"); + _cout(ENVIRONMENT, " * End request\n"); } @@ -164,5 +182,5 @@ if (DCACHE_REQ_VAL [i][j]->read() and dcache_req_ack [i][j]) { - _cout(ENVIRONMENT, "DCACHE_REQ [%d][%d] : Transaction accepted\n",i,j); + _cout(ENVIRONMENT, " * DCACHE_REQ [%d][%d] : Transaction accepted\n",i,j); Tdcache_context_t context = DCACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence @@ -173,10 +191,10 @@ uint32_t size = param->daccess_size_data [i]/8; - _cout(ENVIRONMENT," * information\n"); - _cout(ENVIRONMENT," * context : %d\n" ,static_cast(context)); - _cout(ENVIRONMENT," * packet : %d\n" ,static_cast(packet )); - _cout(ENVIRONMENT," * address : %.x\n",static_cast(address)); - _cout(ENVIRONMENT," * type : %d\n" ,static_cast(type )); - _cout(ENVIRONMENT," * size : %d\n" ,static_cast(size )); + _cout(ENVIRONMENT," * information\n"); + _cout(ENVIRONMENT," * context : %d\n" ,static_cast(context)); + _cout(ENVIRONMENT," * packet : %d\n" ,static_cast(packet )); + _cout(ENVIRONMENT," * address : %.x\n",static_cast(address)); + _cout(ENVIRONMENT," * type : %d\n" ,static_cast(type )); + _cout(ENVIRONMENT," * size : %d\n" ,static_cast(size )); bool uncached = false; @@ -231,5 +249,5 @@ uint32_t num_tty = (address - entity.segment->getBase())>>4; uint32_t num_print = ((address>>2) & 0x3); - _cout(true," * TYPE_TARGET_TTY : num_tty : %d, num_print : %d\n",num_tty, num_print); + _cout(true," * TYPE_TARGET_TTY : num_tty : %d, num_print : %d\n",num_tty, num_print); switch (num_print) @@ -294,11 +312,11 @@ case data::TYPE_TARGET_MEMORY : { - _cout(ENVIRONMENT," * TYPE_TARGET_MEMORY\n"); - _cout(ENVIRONMENT," * access : %x\n",address); + _cout(ENVIRONMENT," * TYPE_TARGET_MEMORY\n"); + _cout(ENVIRONMENT," * access : %x\n",address); if (must_read == true) { // Read - _cout(ENVIRONMENT," * Read (%d bytes)\n",size); + _cout(ENVIRONMENT," * Read (%d bytes)\n",size); bus_error |= !component_data->read(address,nb_bytes,read_dram[0]); // always read a complete word @@ -315,6 +333,6 @@ { // Write - _cout(ENVIRONMENT," * Write (%d bytes)\n",size); - _cout(ENVIRONMENT," * Wdata : %x\n",wdata); + _cout(ENVIRONMENT," * Write (%d bytes)\n",size); + _cout(ENVIRONMENT," * Wdata : %x\n",wdata); itoa(wdata,write_dram,nb_bytes); @@ -330,5 +348,5 @@ case data::TYPE_TARGET_RAMLOCK : { - _cout(ENVIRONMENT," * TYPE_TARGET_RAMLOCK\n"); + _cout(ENVIRONMENT," * TYPE_TARGET_RAMLOCK\n"); // Access is on a byte, else error @@ -343,10 +361,10 @@ uint32_t num_component_ramlock = entity.segment->getIndex(); -// _cout(ENVIRONMENT," * num_ramlock : %d\n",num_ramlock ); -// _cout(ENVIRONMENT," * num_lock : %d\n",num_lock ); -// _cout(ENVIRONMENT," * num_component_ramlock : %d\n",num_component_ramlock); - _cout(true," * num_ramlock : %d\n",num_ramlock ); - _cout(true," * num_lock : %d\n",num_lock ); - _cout(true," * num_component_ramlock : %d\n",num_component_ramlock); + _cout(ENVIRONMENT," * num_ramlock : %d\n",num_ramlock ); + _cout(ENVIRONMENT," * num_lock : %d\n",num_lock ); + _cout(ENVIRONMENT," * num_component_ramlock : %d\n",num_component_ramlock); +// _cout(true," * num_ramlock : %d\n",num_ramlock ); +// _cout(true," * num_lock : %d\n",num_lock ); +// _cout(true," * num_component_ramlock : %d\n",num_component_ramlock); // No test : because out of range @@ -364,6 +382,6 @@ read_dram [0][num_lock] = static_cast(component_ramlock [num_component_ramlock]->write(num_ramlock)); - _cout(true," * lock : %d\n",(int)read_dram [0][num_lock]); -// _cout(ENVIRONMENT," * lock : %d\n",(int)read_dram [0][num_lock]); +// _cout(true," * lock : %d\n",(int)read_dram [0][num_lock]); + _cout(ENVIRONMENT," * lock : %d\n",(int)read_dram [0][num_lock]); break; @@ -375,5 +393,5 @@ case data::TYPE_TARGET_SIM2OS : { - _cout(ENVIRONMENT," * TYPE_TARGET_SIM2OS\n"); + _cout(ENVIRONMENT," * TYPE_TARGET_SIM2OS\n"); // Mapping : @@ -385,5 +403,5 @@ uint32_t num_reg = (address - entity.segment->getBase())>>2; - _cout(ENVIRONMENT," * num_reg : %d\n",num_reg); + _cout(ENVIRONMENT," * num_reg : %d\n",num_reg); switch (num_reg) @@ -398,5 +416,5 @@ else { - _cout(ENVIRONMENT," * service : %x\n",wdata); + _cout(ENVIRONMENT," * service : %x\n",wdata); component_sim2os->execute(sim2os::int2service(static_cast(wdata))); } @@ -414,5 +432,5 @@ // Decomposition en groupe octect Tdcache_data_t result = static_cast(reinterpret_cast(component_sim2os->result)); - _cout(ENVIRONMENT," * result : %x\n",result); + _cout(ENVIRONMENT," * result : %x\n",result); itoa(result,read_dram[0],size); @@ -431,5 +449,5 @@ // Decomposition en groupe octect Tdcache_data_t error = (Tdcache_data_t)component_sim2os->error; - _cout(ENVIRONMENT," * error : %x\n",error); + _cout(ENVIRONMENT," * error : %x\n",error); itoa(error,read_dram[0],size); @@ -447,5 +465,5 @@ else { - _cout(ENVIRONMENT," * argument[%d] : %x\n",num_reg-1,wdata); + _cout(ENVIRONMENT," * argument[%d] : %x\n",num_reg-1,wdata); component_sim2os->parameter(num_reg-2,(void *)wdata); } @@ -498,10 +516,10 @@ if (bus_error == true) { - _cout(ENVIRONMENT," * Dcache : have a bus error\n"); - _cout(ENVIRONMENT," * entity : %d\n",i); - _cout(ENVIRONMENT," * port : %d\n",j); - _cout(ENVIRONMENT," * req_addr : 0x%x\n",address); - _cout(ENVIRONMENT," * req_trdid : %d\n",context); - _cout(ENVIRONMENT," * req_pktid : %d\n",packet ); + _cout(ENVIRONMENT," * Dcache : have a bus error\n"); + _cout(ENVIRONMENT," * entity : %d\n",i); + _cout(ENVIRONMENT," * port : %d\n",j); + _cout(ENVIRONMENT," * req_addr : 0x%x\n",address); + _cout(ENVIRONMENT," * req_trdid : %d\n",context); + _cout(ENVIRONMENT," * req_pktid : %d\n",packet ); // Write in data [0] the bad address (32bit or 64bits ) @@ -509,5 +527,5 @@ } - _cout(ENVIRONMENT," * Rdata : "); + _cout(ENVIRONMENT," * Rdata : "); for (uint32_t x=0; x(read_dram[0][x]));