Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp	(revision 123)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp	(revision 128)
@@ -35,5 +35,5 @@
         DELETE0_SIGNAL(out_ADDRESS_BRANCH_STATE               ,_param->_size_branch_state            );
         DELETE0_SIGNAL(out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth);
-        DELETE1_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE          ,1,_param->_nb_instruction);
+        DELETE1_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE         ,_param->_nb_instruction,1);
         
         DELETE0_SIGNAL(out_PREDICT_VAL                        ,1);
@@ -48,5 +48,5 @@
         DELETE0_SIGNAL( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth);
         DELETE0_SIGNAL( in_PREDICT_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr);
-        DELETE1_SIGNAL(in_PREDICT_INSTRUCTION_ENABLE           ,1,_param->_nb_instruction);
+        DELETE1_SIGNAL(in_PREDICT_INSTRUCTION_ENABLE          ,_param->_nb_instruction,1);
         
         DELETE0_SIGNAL( in_EVENT_VAL             ,1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp	(revision 123)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp	(revision 128)
@@ -28,21 +28,36 @@
       {
 	// nothing is valid
-	reg_PC_ACCESS_VAL    = 0;
-
-	reg_PC_CURRENT_VAL   = 0;
-
-        reg_PC_NEXT_VAL      = 1;
-        reg_PC_NEXT          = 0x100>>2;
-        reg_PC_NEXT_IS_DS_TAKE                  = 0;
+	reg_PC_ACCESS_VAL                               = 0;
+        reg_PC_ACCESS                                   = 0;// not necessary
+        reg_PC_ACCESS_IS_DS_TAKE                        = 0;// not necessary
+        for (uint32_t i=0; i<_param->_nb_instruction; i++)
+        reg_PC_ACCESS_INSTRUCTION_ENABLE [i]            = 0;// not necessary
+        reg_PC_ACCESS_INST_IFETCH_PTR                   = 0;// not necessary
+        reg_PC_ACCESS_BRANCH_STATE                      = 0;// not necessary
+        reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID       = 0;// not necessary
+
+	reg_PC_CURRENT_VAL                              = 0;
+        reg_PC_CURRENT                                  = 0;// not necessary
+        reg_PC_CURRENT_IS_DS_TAKE                       = 0;// not necessary
+        for (uint32_t i=0; i<_param->_nb_instruction; i++)
+        reg_PC_CURRENT_INSTRUCTION_ENABLE [i]           = 0;// not necessary
+        reg_PC_CURRENT_INST_IFETCH_PTR                  = 0;// not necessary
+        reg_PC_CURRENT_BRANCH_STATE                     = 0;// not necessary
+        reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID      = 0;// not necessary
+
+        reg_PC_NEXT_VAL                                 = 1;
+        reg_PC_NEXT                                     = 0x100>>2;
+        reg_PC_NEXT_IS_DS_TAKE                          = 0;
         uint32_t index = reg_PC_NEXT % _param->_nb_instruction;
         for (uint32_t i=0; i<_param->_nb_instruction; i++)
-        reg_PC_NEXT_INSTRUCTION_ENABLE [i]      = 0;
-        reg_PC_NEXT_INSTRUCTION_ENABLE [index]  = 1;
-        reg_PC_NEXT_INST_IFETCH_PTR             = 0;
-        reg_PC_NEXT_BRANCH_STATE                = 0;
-        reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0;
-
-
-	reg_PC_NEXT_NEXT_VAL = 0;
+        reg_PC_NEXT_INSTRUCTION_ENABLE [i]              = 0;
+        reg_PC_NEXT_INSTRUCTION_ENABLE [index]          = 1;
+        reg_PC_NEXT_INST_IFETCH_PTR                     = 0;
+        reg_PC_NEXT_BRANCH_STATE                        = 0;
+        reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID         = 0;
+
+	reg_PC_NEXT_NEXT_VAL                            = 0;
+        reg_PC_NEXT_NEXT                                = 0;// not necessary
+        reg_PC_NEXT_NEXT_IS_DS_TAKE                     = 0;// not necessary
       }
     else
