Changeset 128 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit
- Timestamp:
- Jun 26, 2009, 10:43:23 AM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit
- Files:
-
- 5 edited
-
SelfTest/src/main.cpp (modified) (1 diff)
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SelfTest/src/test.cpp (modified) (16 diffs)
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src/Commit_unit_deallocation.cpp (modified) (1 diff)
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src/Commit_unit_genMealy_retire.cpp (modified) (4 diffs)
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src/Commit_unit_transition.cpp (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp
r110 r128 142 142 143 143 test (name,param); 144 145 delete param; 144 146 } 145 147 catch (morpheo::ErrorMorpheo & error) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp
r121 r128 29 29 #endif 30 30 31 simulation_init(0,0 );31 simulation_init(0,0,0,false,false); 32 32 33 33 debug_idle_cycle = CYCLE_MAX; … … 62 62 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 63 63 64 sc_signal<Tcontrol_t > *** in_INSERT_VAL ; 65 sc_signal<Tcontrol_t > *** out_INSERT_ACK ; 66 sc_signal<Tcontext_t > *** in_INSERT_FRONT_END_ID ; 67 sc_signal<Tcontext_t > *** in_INSERT_CONTEXT_ID ; 68 sc_signal<Tpacket_t > *** out_INSERT_PACKET_ID ; 69 //sc_signal<Tcontext_t > *** in_INSERT_RENAME_UNIT_ID ; 70 sc_signal<Tdepth_t > *** in_INSERT_DEPTH ; 71 sc_signal<Ttype_t > *** in_INSERT_TYPE ; 72 sc_signal<Toperation_t > *** in_INSERT_OPERATION ; 73 sc_signal<Tcontrol_t > *** in_INSERT_NO_EXECUTE ; 74 sc_signal<Tcontrol_t > *** in_INSERT_LAST_EVENT ; 75 sc_signal<Tcontrol_t > *** in_INSERT_IS_DELAY_SLOT ; 76 sc_signal<Taddress_t > *** in_INSERT_ADDRESS ; 77 sc_signal<Taddress_t > *** in_INSERT_ADDRESS_NEXT ; 78 sc_signal<Texception_t > *** in_INSERT_EXCEPTION ; 79 sc_signal<Texception_t > *** in_INSERT_EXCEPTION_USE ; 80 sc_signal<Tlsq_ptr_t > *** in_INSERT_STORE_QUEUE_PTR_WRITE ; 81 sc_signal<Tlsq_ptr_t > *** in_INSERT_LOAD_QUEUE_PTR_WRITE ; 82 sc_signal<Tcontrol_t > *** in_INSERT_READ_RA ; 83 sc_signal<Tgeneral_address_t> *** in_INSERT_NUM_REG_RA_LOG ; 84 sc_signal<Tgeneral_address_t> *** in_INSERT_NUM_REG_RA_PHY ; 85 sc_signal<Tcontrol_t > *** in_INSERT_READ_RB ; 86 sc_signal<Tgeneral_address_t> *** in_INSERT_NUM_REG_RB_LOG ; 87 sc_signal<Tgeneral_address_t> *** in_INSERT_NUM_REG_RB_PHY ; 88 sc_signal<Tcontrol_t > *** in_INSERT_READ_RC ; 89 sc_signal<Tspecial_address_t> *** in_INSERT_NUM_REG_RC_LOG ; 90 sc_signal<Tspecial_address_t> *** in_INSERT_NUM_REG_RC_PHY ; 91 sc_signal<Tcontrol_t > *** in_INSERT_WRITE_RD ; 92 sc_signal<Tgeneral_address_t> *** in_INSERT_NUM_REG_RD_LOG ; 93 sc_signal<Tgeneral_address_t> *** in_INSERT_NUM_REG_RD_PHY_OLD ; 94 sc_signal<Tgeneral_address_t> *** in_INSERT_NUM_REG_RD_PHY_NEW ; 95 sc_signal<Tcontrol_t > *** in_INSERT_WRITE_RE ; 96 sc_signal<Tspecial_address_t> *** in_INSERT_NUM_REG_RE_LOG ; 97 sc_signal<Tspecial_address_t> *** in_INSERT_NUM_REG_RE_PHY_OLD ; 98 sc_signal<Tspecial_address_t> *** in_INSERT_NUM_REG_RE_PHY_NEW ; 99 100 sc_signal<Tcontrol_t > *** out_RETIRE_VAL ; 101 sc_signal<Tcontrol_t > *** in_RETIRE_ACK ; 102 sc_signal<Tcontext_t > *** out_RETIRE_FRONT_END_ID ; 103 sc_signal<Tcontext_t > *** out_RETIRE_CONTEXT_ID ; 104 //sc_signal<Tcontext_t > *** out_RETIRE_RENAME_UNIT_ID ; 105 sc_signal<Tcontrol_t > *** out_RETIRE_USE_STORE_QUEUE ; 106 sc_signal<Tcontrol_t > *** out_RETIRE_USE_LOAD_QUEUE ; 107 sc_signal<Tlsq_ptr_t > *** out_RETIRE_STORE_QUEUE_PTR_WRITE ; 108 sc_signal<Tlsq_ptr_t > *** out_RETIRE_LOAD_QUEUE_PTR_WRITE ; 109 sc_signal<Tcontrol_t > *** out_RETIRE_READ_RA ; 110 sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RA_PHY ; 111 sc_signal<Tcontrol_t > *** out_RETIRE_READ_RB ; 112 sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RB_PHY ; 113 sc_signal<Tcontrol_t > *** out_RETIRE_READ_RC ; 114 sc_signal<Tspecial_address_t> *** out_RETIRE_NUM_REG_RC_PHY ; 115 sc_signal<Tcontrol_t > *** out_RETIRE_WRITE_RD ; 116 sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RD_LOG ; 117 sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RD_PHY_OLD ; 118 sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RD_PHY_NEW ; 119 sc_signal<Tcontrol_t > *** out_RETIRE_WRITE_RE ; 120 sc_signal<Tspecial_address_t> *** out_RETIRE_NUM_REG_RE_LOG ; 121 sc_signal<Tspecial_address_t> *** out_RETIRE_NUM_REG_RE_PHY_OLD ; 122 sc_signal<Tspecial_address_t> *** out_RETIRE_NUM_REG_RE_PHY_NEW ; 123 124 sc_signal<Tcontrol_t > *** out_RETIRE_EVENT_VAL ; 125 sc_signal<Tcontrol_t > *** in_RETIRE_EVENT_ACK ; 126 sc_signal<Tevent_state_t > *** out_RETIRE_EVENT_STATE ; 127 sc_signal<Tcontrol_t > *** out_RETIRE_EVENT_STOP ; 128 129 sc_signal<Tcontrol_t > ** in_COMMIT_VAL ; 130 sc_signal<Tcontrol_t > ** out_COMMIT_ACK ; 131 sc_signal<Tcontrol_t > ** in_COMMIT_WEN ; 132 sc_signal<Tpacket_t > ** in_COMMIT_PACKET_ID ; 133 //sc_signal<Toperation_t > ** in_COMMIT_OPERATION ; 134 //sc_signal<Ttype_t > ** in_COMMIT_TYPE ; 135 sc_signal<Tspecial_data_t > ** in_COMMIT_FLAGS ; 136 sc_signal<Texception_t > ** in_COMMIT_EXCEPTION ; 137 sc_signal<Tcontrol_t > ** in_COMMIT_NO_SEQUENCE ; 138 sc_signal<Taddress_t > ** in_COMMIT_ADDRESS ; 139 sc_signal<Tgeneral_address_t> ** out_COMMIT_NUM_REG_RD ; 140 141 sc_signal<Tcontrol_t > ** out_REEXECUTE_VAL ; 142 sc_signal<Tcontrol_t > ** in_REEXECUTE_ACK ; 143 sc_signal<Tcontext_t > ** out_REEXECUTE_CONTEXT_ID ; 144 sc_signal<Tcontext_t > ** out_REEXECUTE_FRONT_END_ID ; 145 sc_signal<Tpacket_t > ** out_REEXECUTE_PACKET_ID ; 146 sc_signal<Toperation_t > ** out_REEXECUTE_OPERATION ; 147 sc_signal<Ttype_t > ** out_REEXECUTE_TYPE ; 148 sc_signal<Tlsq_ptr_t > ** out_REEXECUTE_STORE_QUEUE_PTR_WRITE; 149 150 sc_signal<Tcontrol_t > ** out_BRANCH_COMPLETE_VAL ; 151 sc_signal<Tcontrol_t > ** in_BRANCH_COMPLETE_ACK ; 152 sc_signal<Tcontext_t > ** out_BRANCH_COMPLETE_CONTEXT_ID ; 153 sc_signal<Tcontext_t > ** out_BRANCH_COMPLETE_FRONT_END_ID ; 154 sc_signal<Tdepth_t > ** out_BRANCH_COMPLETE_DEPTH ; 155 sc_signal<Taddress_t > ** out_BRANCH_COMPLETE_ADDRESS ; 156 sc_signal<Tcontrol_t > ** out_BRANCH_COMPLETE_NO_SEQUENCE ; 157 sc_signal<Tcontrol_t > ** in_BRANCH_COMPLETE_MISS_PREDICTION; 158 159 sc_signal<Tcontrol_t > * out_UPDATE_VAL ; 160 sc_signal<Tcontrol_t > * in_UPDATE_ACK ; 161 sc_signal<Tcontext_t > * out_UPDATE_CONTEXT_ID ; 162 sc_signal<Tcontext_t > * out_UPDATE_FRONT_END_ID ; 163 sc_signal<Tdepth_t > * out_UPDATE_DEPTH ; 164 sc_signal<Tevent_type_t > * out_UPDATE_TYPE ; 165 sc_signal<Tcontrol_t > * out_UPDATE_IS_DELAY_SLOT ; 166 sc_signal<Taddress_t > * out_UPDATE_ADDRESS ; 167 sc_signal<Tcontrol_t > * out_UPDATE_ADDRESS_EPCR_VAL ; 168 sc_signal<Taddress_t > * out_UPDATE_ADDRESS_EPCR ; 169 sc_signal<Tcontrol_t > * out_UPDATE_ADDRESS_EEAR_VAL ; 170 sc_signal<Tgeneral_data_t > * out_UPDATE_ADDRESS_EEAR ; 171 172 sc_signal<Tcontrol_t > *** in_EVENT_VAL ; 173 sc_signal<Tcontrol_t > *** out_EVENT_ACK ; 174 sc_signal<Taddress_t > *** in_EVENT_ADDRESS ; 175 sc_signal<Taddress_t > *** in_EVENT_ADDRESS_NEXT ; 176 sc_signal<Tcontrol_t > *** in_EVENT_ADDRESS_NEXT_VAL ; 177 sc_signal<Tcontrol_t > *** in_EVENT_IS_DS_TAKE ; 178 179 sc_signal<Tcounter_t > *** out_NB_INST_COMMIT_ALL ; 180 sc_signal<Tcounter_t > *** out_NB_INST_COMMIT_MEM ; 181 sc_signal<Tcounter_t > *** in_NB_INST_DECOD_ALL ; 182 sc_signal<Tdepth_t > *** in_DEPTH_MIN ; 183 sc_signal<Tdepth_t > *** in_DEPTH_MAX ; 184 sc_signal<Tcontrol_t > *** in_DEPTH_FULL ; 185 186 sc_signal<Tcontrol_t > *** in_SPR_READ_SR_OVE ; 187 188 sc_signal<Tcontrol_t > *** out_SPR_WRITE_VAL ; 189 sc_signal<Tcontrol_t > *** in_SPR_WRITE_ACK ; 190 sc_signal<Tcontrol_t > *** out_SPR_WRITE_SR_F_VAL ; 191 sc_signal<Tcontrol_t > *** out_SPR_WRITE_SR_F ; 192 sc_signal<Tcontrol_t > *** out_SPR_WRITE_SR_CY_VAL ; 193 sc_signal<Tcontrol_t > *** out_SPR_WRITE_SR_CY ; 194 sc_signal<Tcontrol_t > *** out_SPR_WRITE_SR_OV_VAL ; 195 sc_signal<Tcontrol_t > *** out_SPR_WRITE_SR_OV ; 196 197 sc_signal<bool > * out_INFO_ROB_EMPTY ; 198 64 199 ALLOC2_SC_SIGNAL( in_INSERT_VAL ," in_INSERT_VAL ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 65 200 ALLOC2_SC_SIGNAL(out_INSERT_ACK ,"out_INSERT_ACK ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 72 207 ALLOC2_SC_SIGNAL( in_INSERT_OPERATION ," in_INSERT_OPERATION ",Toperation_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 73 208 ALLOC2_SC_SIGNAL( in_INSERT_NO_EXECUTE ," in_INSERT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 209 ALLOC2_SC_SIGNAL( in_INSERT_LAST_EVENT ," in_INSERT_LAST_EVENT ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 74 210 ALLOC2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ," in_INSERT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 75 #ifdef DEBUG76 211 ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS ," in_INSERT_ADDRESS ",Taddress_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 77 #endif78 212 ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT ," in_INSERT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 79 213 ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION ," in_INSERT_EXCEPTION ",Texception_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 125 259 ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_ACK ," in_RETIRE_EVENT_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); 126 260 ALLOC2_SC_SIGNAL(out_RETIRE_EVENT_STATE ,"out_RETIRE_EVENT_STATE ",Tevent_state_t ,_param->_nb_front_end,_param->_nb_context[it1]); 261 ALLOC2_SC_SIGNAL(out_RETIRE_EVENT_STOP ,"out_RETIRE_EVENT_STOP ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); 127 262 128 263 ALLOC1_SC_SIGNAL( in_COMMIT_VAL ," in_COMMIT_VAL ",Tcontrol_t ,_param->_nb_inst_commit); … … 137 272 ALLOC1_SC_SIGNAL( in_COMMIT_ADDRESS ," in_COMMIT_ADDRESS ",Taddress_t ,_param->_nb_inst_commit); 138 273 ALLOC1_SC_SIGNAL(out_COMMIT_NUM_REG_RD ,"out_COMMIT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_commit); 274 139 275 ALLOC1_SC_SIGNAL(out_REEXECUTE_VAL ,"out_REEXECUTE_VAL ",Tcontrol_t ,_param->_nb_inst_reexecute); 140 276 ALLOC1_SC_SIGNAL( in_REEXECUTE_ACK ," in_REEXECUTE_ACK ",Tcontrol_t ,_param->_nb_inst_reexecute); … … 191 327 ALLOC2_SC_SIGNAL(out_SPR_WRITE_SR_OV ,"out_SPR_WRITE_SR_OV ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); 192 328 329 ALLOC0_SC_SIGNAL(out_INFO_ROB_EMPTY ,"out_INFO_ROB_EMPTY ",bool ); 330 193 331 /******************************************************** 194 332 * Instanciation … … 215 353 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 216 354 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 355 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_LAST_EVENT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 217 356 #ifdef DEBUG 218 357 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 272 411 INSTANCE2_SC_SIGNAL(_Commit_unit, in_RETIRE_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); 273 412 INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context[it1]); 413 INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_EVENT_STOP ,_param->_nb_front_end,_param->_nb_context[it1]); 274 414 INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_VAL ,_param->_nb_inst_commit); 275 415 INSTANCE1_SC_SIGNAL(_Commit_unit,out_COMMIT_ACK ,_param->_nb_inst_commit); … … 351 491 INSTANCE2_SC_SIGNAL(_Commit_unit,out_SPR_WRITE_SR_OV ,_param->_nb_front_end,_param->_nb_context[it1]); 352 492 493 #ifdef DEBUG_TEST 494 INSTANCE0_SC_SIGNAL(_Commit_unit,out_INFO_ROB_EMPTY ); 495 #endif 496 353 497 msg(_("<%s> : Start Simulation ............\n"),name.c_str()); 354 498 … … 378 522 in_NRESET->write(1); 379 523 524 #ifdef SELFTEST 380 525 LABEL("Loop of Test"); 381 526 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) … … 435 580 in_INSERT_IS_DELAY_SLOT [i][j]->write(0); 436 581 in_INSERT_NO_EXECUTE [i][j]->write(0); 582 in_INSERT_LAST_EVENT [i][j]->write(0); 437 583 in_INSERT_ADDRESS_NEXT [i][j]->write(addr); 438 584 in_INSERT_EXCEPTION [i][j]->write(0); … … 608 754 609 755 } 756 #else 757 SC_START(10); 758 #endif 610 759 611 760 /******************************************************** … … 631 780 DELETE2_SC_SIGNAL( in_INSERT_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 632 781 DELETE2_SC_SIGNAL( in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 782 DELETE2_SC_SIGNAL( in_INSERT_LAST_EVENT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 633 783 DELETE2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 634 #ifdef DEBUG635 784 DELETE2_SC_SIGNAL( in_INSERT_ADDRESS ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 636 #endif637 785 DELETE2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 638 786 DELETE2_SC_SIGNAL( in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 666 814 DELETE2_SC_SIGNAL(out_RETIRE_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 667 815 DELETE2_SC_SIGNAL(out_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 668 // 669 // 670 // 671 // 672 // 673 // 816 //DELETE2_SC_SIGNAL(out_RETIRE_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 817 //DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 818 //DELETE2_SC_SIGNAL(out_RETIRE_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 819 //DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 820 //DELETE2_SC_SIGNAL(out_RETIRE_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 821 //DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 674 822 DELETE2_SC_SIGNAL(out_RETIRE_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 675 823 DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RD_LOG ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); … … 683 831 DELETE2_SC_SIGNAL( in_RETIRE_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); 684 832 DELETE2_SC_SIGNAL(out_RETIRE_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context[it1]); 833 DELETE2_SC_SIGNAL(out_RETIRE_EVENT_STOP ,_param->_nb_front_end,_param->_nb_context[it1]); 685 834 DELETE1_SC_SIGNAL( in_COMMIT_VAL ,_param->_nb_inst_commit); 686 835 DELETE1_SC_SIGNAL(out_COMMIT_ACK ,_param->_nb_inst_commit); … … 747 896 DELETE2_SC_SIGNAL(out_SPR_WRITE_SR_OV_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); 748 897 DELETE2_SC_SIGNAL(out_SPR_WRITE_SR_OV ,_param->_nb_front_end,_param->_nb_context[it1]); 898 899 DELETE0_SC_SIGNAL(out_INFO_ROB_EMPTY ); 749 900 } 750 901 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
r125 r128 239 239 240 240 #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true) 241 for (uint32_t i=0; i<_param->_nb_thread; ++i) 242 if (_param->_have_thread [i]) 243 { 244 instruction_log_file [i].close(); 245 } 241 { 242 for (uint32_t i=0; i<_param->_nb_thread; ++i) 243 if (_param->_have_thread [i]) 244 { 245 instruction_log_file [i].close(); 246 } 247 delete [] instruction_log_file; 248 } 246 249 #endif 247 250 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
r123 r128 52 52 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 53 53 { 54 spr_write_val [i][j] = 0;54 spr_write_val [i][j] = 0; 55 55 spr_write_sr_f_val [i][j] = 0; 56 56 spr_write_sr_cy_val [i][j] = 0; … … 63 63 for (uint32_t i=0; i<_param->_nb_bank; i++) 64 64 { 65 uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank; 65 uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank; 66 67 log_printf(TRACE,Commit_unit,FUNCTION," * BANK [%d]",num_bank); 66 68 67 69 // Test if have instruction … … 72 74 uint32_t x = entry->rename_unit_id; 73 75 uint32_t y = num_inst_retire [x]; 74 bool bypass= false; 75 // test if : 76 // * can retire (all previous instruction is retired) 77 // * all structure is ok (not busy) 78 if (can_retire [x] and // in-order 79 (y < _param->_nb_inst_retire [x]) and 80 PORT_READ(in_RETIRE_ACK [x][y])) // not busy 81 { 82 rob_state_t state = entry->state; 83 Tcontext_t front_end_id = entry->front_end_id; 84 Tcontext_t context_id = entry->context_id; 76 77 log_printf(TRACE,Commit_unit,FUNCTION," * num_rename_unit : %d",x); 78 log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_retire : %d",y); 79 80 if (y < _param->_nb_inst_retire [x]) 81 { 82 #ifdef DEBUG_TEST 83 if (x >= _param->_nb_rename_unit) 84 throw ERRORMORPHEO(FUNCTION,toString(_("Invalid rename_unit number (%d, max is %d).\n"),x,_param->_nb_rename_unit)); 85 #endif 86 bool bypass= false; 87 88 log_printf(TRACE,Commit_unit,FUNCTION," * can_retire : %d",can_retire [x]); 89 log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE_ACK : %d",PORT_READ(in_RETIRE_ACK [x][y])); 90 91 // test if : 92 // * can retire (all previous instruction is retired) 93 // * all structure is ok (not busy) 94 if (can_retire [x] and // in-order 95 PORT_READ(in_RETIRE_ACK [x][y])) // not busy 96 { 97 log_printf(TRACE,Commit_unit,FUNCTION," * valid !!!"); 98 99 rob_state_t state = entry->state; 100 Tcontext_t front_end_id = entry->front_end_id; 101 Tcontext_t context_id = entry->context_id; 102 103 log_printf(TRACE,Commit_unit,FUNCTION," * state : %s",toString(state).c_str()); 104 log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); 105 log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); 106 107 if ((state == ROB_END_OK ) or 108 (state == ROB_END_KO ) or 109 (state == ROB_END_BRANCH_MISS) or 110 (state == ROB_END_LOAD_MISS ) or 111 (state == ROB_END_MISS )// or 112 // (state == ROB_END_EXCEPTION) 113 ) 114 { 115 Tcontrol_t write_re = entry->write_re; 116 Tspecial_address_t num_reg_re_log = entry->num_reg_re_log; 117 118 // if state is ok, when write flags in the SR regsiters 119 bool spr_write_ack = true; 120 121 // Write in SR the good flag 122 if ((state == ROB_END_OK ) and write_re) 123 // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE 124 { 125 log_printf(TRACE,Commit_unit,FUNCTION," * need write SR flags"); 126 log_printf(TRACE,Commit_unit,FUNCTION," * SPR_WRITE_ACK : %d",PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id])); 127 128 spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]); 129 130 // retire_ack is set !!! 131 spr_write_val [front_end_id][context_id] = 1; 132 133 Tspecial_data_t flags = entry->flags; 134 135 switch (num_reg_re_log) 136 { 137 case SPR_LOGIC_SR_F : 138 { 139 spr_write_sr_f_val [front_end_id][context_id] = 1; 140 spr_write_sr_f [front_end_id][context_id] = (flags & FLAG_F )!=0; 141 142 break; 143 } 144 case SPR_LOGIC_SR_CY_OV : 145 { 146 spr_write_sr_cy_val [front_end_id][context_id] = 1; 147 spr_write_sr_ov_val [front_end_id][context_id] = 1; 148 spr_write_sr_cy [front_end_id][context_id] = (flags & FLAG_CY)!=0; 149 spr_write_sr_ov [front_end_id][context_id] = (flags & FLAG_OV)!=0; 150 151 break; 152 } 153 default : 154 { 155 #ifdef DEBUG_TEST 156 throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n")); 157 #endif 158 } 159 } 160 } 161 162 // find an instruction can be retire, and in order 163 164 if (spr_write_ack) 165 { 166 retire_val [x][y] = 1; 167 num_inst_retire [x] ++; 168 internal_BANK_RETIRE_VAL [num_bank] = true; 169 } 170 171 internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x; 172 internal_BANK_RETIRE_NUM_INST [num_bank] = y; 173 174 if (_param->_have_port_front_end_id) 175 PORT_WRITE(out_RETIRE_FRONT_END_ID [x][y], front_end_id ); 176 if (_param->_have_port_context_id) 177 PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id ); 178 // PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id ); 179 PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue ); 180 PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue ); 181 PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write); 182 if (_param->_have_port_load_queue_ptr) 183 PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE [x][y], entry->load_queue_ptr_write ); 184 // PORT_WRITE(out_RETIRE_READ_RA [x][y], entry->read_ra ); 185 // PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY [x][y], entry->num_reg_ra_phy ); 186 // PORT_WRITE(out_RETIRE_READ_RB [x][y], entry->read_rb ); 187 // PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY [x][y], entry->num_reg_rb_phy ); 188 // PORT_WRITE(out_RETIRE_READ_RC [x][y], entry->read_rc ); 189 // PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY [x][y], entry->num_reg_rc_phy ); 190 PORT_WRITE(out_RETIRE_WRITE_RD [x][y], entry->write_rd ); 191 PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG [x][y], entry->num_reg_rd_log ); 192 PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD [x][y], entry->num_reg_rd_phy_old ); 193 PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW [x][y], entry->num_reg_rd_phy_new ); 194 PORT_WRITE(out_RETIRE_WRITE_RE [x][y], write_re ); 195 PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG [x][y], num_reg_re_log ); 196 PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD [x][y], entry->num_reg_re_phy_old ); 197 PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW [x][y], entry->num_reg_re_phy_new ); 198 199 // Event -> rob must be manage this event 200 if ((state == ROB_END_BRANCH_MISS) or 201 (state == ROB_END_LOAD_MISS)) 202 can_retire [x] = false; 203 } 204 205 log_printf(TRACE,Commit_unit,FUNCTION," * bypass (before) : %d",bypass); 206 207 bypass = ((state == ROB_END ) or 208 (state == ROB_STORE_OK ) or 209 (state == ROB_STORE_KO ) or 210 (state == ROB_STORE_OK_WAIT_END) or 211 (state == ROB_STORE_KO_WAIT_END)); 212 213 log_printf(TRACE,Commit_unit,FUNCTION," * bypass (after) : %d",bypass); 214 215 uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank); 216 217 log_printf(TRACE,Commit_unit,FUNCTION," * packet : %d",packet); 218 219 // if future event, don't update after this event 220 if ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and 221 (reg_EVENT_PACKET [front_end_id][context_id] == packet)) 222 { 223 log_printf(TRACE,Commit_unit,FUNCTION," * is the event instruction, stop bypass !!!"); 224 bypass = false; 225 } 226 } 85 227 86 if ((state == ROB_END_OK ) or 87 (state == ROB_END_KO ) or 88 (state == ROB_END_BRANCH_MISS) or 89 (state == ROB_END_LOAD_MISS ) or 90 (state == ROB_END_MISS )// or 91 // (state == ROB_END_EXCEPTION) 92 ) 93 { 94 Tcontrol_t write_re = entry->write_re; 95 Tspecial_address_t num_reg_re_log = entry->num_reg_re_log; 96 97 // if state is ok, when write flags in the SR regsiters 98 bool spr_write_ack = true; 99 100 // Write in SR the good flag 101 if ((state == ROB_END_OK ) and write_re) 102 // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE 103 { 104 spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]); 105 106 // retire_ack is set !!! 107 spr_write_val [front_end_id][context_id] = 1; 108 109 Tspecial_data_t flags = entry->flags; 110 111 switch (num_reg_re_log) 112 { 113 case SPR_LOGIC_SR_F : 114 { 115 spr_write_sr_f_val [front_end_id][context_id] = 1; 116 spr_write_sr_f [front_end_id][context_id] = (flags & FLAG_F )!=0; 117 118 break; 119 } 120 case SPR_LOGIC_SR_CY_OV : 121 { 122 spr_write_sr_cy_val [front_end_id][context_id] = 1; 123 spr_write_sr_ov_val [front_end_id][context_id] = 1; 124 spr_write_sr_cy [front_end_id][context_id] = (flags & FLAG_CY)!=0; 125 spr_write_sr_ov [front_end_id][context_id] = (flags & FLAG_OV)!=0; 126 127 break; 128 } 129 default : 130 { 131 #ifdef DEBUG_TEST 132 throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n")); 133 #endif 134 } 135 } 136 } 137 138 // find an instruction can be retire, and in order 139 140 if (spr_write_ack) 141 { 142 retire_val [x][y] = 1; 143 num_inst_retire [x] ++; 144 internal_BANK_RETIRE_VAL [num_bank] = true; 145 } 146 147 internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x; 148 internal_BANK_RETIRE_NUM_INST [num_bank] = y; 149 150 if (_param->_have_port_front_end_id) 151 PORT_WRITE(out_RETIRE_FRONT_END_ID [x][y], front_end_id ); 152 if (_param->_have_port_context_id) 153 PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id ); 154 // PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id ); 155 PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue ); 156 PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue ); 157 PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write); 158 if (_param->_have_port_load_queue_ptr) 159 PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE [x][y], entry->load_queue_ptr_write ); 160 // PORT_WRITE(out_RETIRE_READ_RA [x][y], entry->read_ra ); 161 // PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY [x][y], entry->num_reg_ra_phy ); 162 // PORT_WRITE(out_RETIRE_READ_RB [x][y], entry->read_rb ); 163 // PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY [x][y], entry->num_reg_rb_phy ); 164 // PORT_WRITE(out_RETIRE_READ_RC [x][y], entry->read_rc ); 165 // PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY [x][y], entry->num_reg_rc_phy ); 166 PORT_WRITE(out_RETIRE_WRITE_RD [x][y], entry->write_rd ); 167 PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG [x][y], entry->num_reg_rd_log ); 168 PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD [x][y], entry->num_reg_rd_phy_old ); 169 PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW [x][y], entry->num_reg_rd_phy_new ); 170 PORT_WRITE(out_RETIRE_WRITE_RE [x][y], write_re ); 171 PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG [x][y], num_reg_re_log ); 172 PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD [x][y], entry->num_reg_re_phy_old ); 173 PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW [x][y], entry->num_reg_re_phy_new ); 174 175 // Event -> rob must be manage this event 176 if ((state == ROB_END_BRANCH_MISS) or 177 (state == ROB_END_LOAD_MISS)) 178 can_retire [x] = false; 179 } 180 181 bypass = ((state == ROB_END ) or 182 (state == ROB_STORE_OK ) or 183 (state == ROB_STORE_KO ) or 184 (state == ROB_STORE_OK_WAIT_END) or 185 (state == ROB_STORE_KO_WAIT_END)); 186 187 uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank); 188 189 // if future event, don't update after this event 190 if ((reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and 191 (reg_EVENT_PACKET [entry->front_end_id][entry->context_id] == packet)) 192 bypass = false; 193 } 194 195 // Retire "in-order" 196 can_retire [x] &= (retire_val [x][y] or bypass); 228 // Retire "in-order" 229 can_retire [x] &= (retire_val [x][y] or bypass); 230 } 197 231 } 198 232 } … … 219 253 for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) 220 254 PORT_WRITE(out_RETIRE_VAL [i][j],0); 255 256 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 257 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 258 PORT_WRITE(out_SPR_WRITE_VAL [i][j], 0); 221 259 } 222 260 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r124 r128 54 54 // reg_EVENT_FLUSH [i][j] = false; 55 55 // reg_EVENT_STOP [i][j] = false; 56 reg_EVENT_NUM_BANK [i][j] = 0; // not necessary 57 reg_EVENT_NUM_PTR [i][j] = 0; // not necessary 58 //reg_EVENT_CAN_RESTART [i][j] = 0; // not necessary 59 reg_EVENT_PACKET [i][j] = 0; // not necessary 56 60 reg_EVENT_NB_INST [i][j] = 0; 57 61 reg_EVENT_LAST [i][j] = false; 62 reg_EVENT_LAST_NUM_BANK [i][j] = 0; // not necessary 63 reg_EVENT_LAST_NUM_PTR [i][j] = 0; // not necessary 58 64 59 65 reg_EVENT_NEXT_STOP [i][j] = false; 66 reg_EVENT_NEXT_PACKET [i][j] = 0; // not necessary 60 67 61 68 // reg_PC_PREVIOUS [i][j] = (0x100-4)>>2; … … 274 281 entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]); 275 282 entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); 283 284 entry->flags = 0; // not necessary 276 285 entry->no_sequence = type == TYPE_BRANCH; 277 286 // entry->speculative = true; 278 287 #ifdef DEBUG 279 288 entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); 289 #else 290 entry->address = 0; // not necessary 280 291 #endif 281 292 entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]); … … 1339 1350 (*it)->flags , 1340 1351 (*it)->no_sequence , 1341 // 1352 // (*it)->speculative , 1342 1353 (*it)->address , 1343 1354 (*it)->address<<2 ,
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