Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp	(revision 128)
@@ -142,4 +142,6 @@
       
       test (name,param);
+
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp	(revision 128)
@@ -29,5 +29,5 @@
 #endif
 
-  simulation_init(0,0);
+  simulation_init(0,0,0,false,false);
 
   debug_idle_cycle = CYCLE_MAX;
@@ -62,4 +62,139 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
+  sc_signal<Tcontrol_t        > ***  in_INSERT_VAL                     ;
+  sc_signal<Tcontrol_t        > *** out_INSERT_ACK                     ;
+  sc_signal<Tcontext_t        > ***  in_INSERT_FRONT_END_ID            ;
+  sc_signal<Tcontext_t        > ***  in_INSERT_CONTEXT_ID              ;
+  sc_signal<Tpacket_t         > *** out_INSERT_PACKET_ID               ;
+//sc_signal<Tcontext_t        > ***  in_INSERT_RENAME_UNIT_ID          ;
+  sc_signal<Tdepth_t          > ***  in_INSERT_DEPTH                   ;
+  sc_signal<Ttype_t           > ***  in_INSERT_TYPE                    ;
+  sc_signal<Toperation_t      > ***  in_INSERT_OPERATION               ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_NO_EXECUTE              ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_LAST_EVENT              ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_IS_DELAY_SLOT           ;
+  sc_signal<Taddress_t        > ***  in_INSERT_ADDRESS                 ;
+  sc_signal<Taddress_t        > ***  in_INSERT_ADDRESS_NEXT            ;
+  sc_signal<Texception_t      > ***  in_INSERT_EXCEPTION               ;
+  sc_signal<Texception_t      > ***  in_INSERT_EXCEPTION_USE           ;
+  sc_signal<Tlsq_ptr_t        > ***  in_INSERT_STORE_QUEUE_PTR_WRITE   ;
+  sc_signal<Tlsq_ptr_t        > ***  in_INSERT_LOAD_QUEUE_PTR_WRITE    ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_READ_RA                 ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RA_LOG          ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RA_PHY          ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_READ_RB                 ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RB_LOG          ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RB_PHY          ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_READ_RC                 ;
+  sc_signal<Tspecial_address_t> ***  in_INSERT_NUM_REG_RC_LOG          ;
+  sc_signal<Tspecial_address_t> ***  in_INSERT_NUM_REG_RC_PHY          ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_WRITE_RD                ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RD_LOG          ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RD_PHY_OLD      ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RD_PHY_NEW      ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_WRITE_RE                ;
+  sc_signal<Tspecial_address_t> ***  in_INSERT_NUM_REG_RE_LOG          ;
+  sc_signal<Tspecial_address_t> ***  in_INSERT_NUM_REG_RE_PHY_OLD      ;
+  sc_signal<Tspecial_address_t> ***  in_INSERT_NUM_REG_RE_PHY_NEW      ;
+
+  sc_signal<Tcontrol_t        > *** out_RETIRE_VAL                     ;
+  sc_signal<Tcontrol_t        > ***  in_RETIRE_ACK                     ;
+  sc_signal<Tcontext_t        > *** out_RETIRE_FRONT_END_ID            ;
+  sc_signal<Tcontext_t        > *** out_RETIRE_CONTEXT_ID              ;
+//sc_signal<Tcontext_t        > *** out_RETIRE_RENAME_UNIT_ID          ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_USE_STORE_QUEUE         ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_USE_LOAD_QUEUE          ;
+  sc_signal<Tlsq_ptr_t        > *** out_RETIRE_STORE_QUEUE_PTR_WRITE   ;
+  sc_signal<Tlsq_ptr_t        > *** out_RETIRE_LOAD_QUEUE_PTR_WRITE    ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_READ_RA                 ;
+  sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RA_PHY          ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_READ_RB                 ;
+  sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RB_PHY          ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_READ_RC                 ;
+  sc_signal<Tspecial_address_t> *** out_RETIRE_NUM_REG_RC_PHY          ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_WRITE_RD                ;
+  sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RD_LOG          ;
+  sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RD_PHY_OLD      ;
+  sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RD_PHY_NEW      ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_WRITE_RE                ;
+  sc_signal<Tspecial_address_t> *** out_RETIRE_NUM_REG_RE_LOG          ;
+  sc_signal<Tspecial_address_t> *** out_RETIRE_NUM_REG_RE_PHY_OLD      ;
+  sc_signal<Tspecial_address_t> *** out_RETIRE_NUM_REG_RE_PHY_NEW      ;
+
+  sc_signal<Tcontrol_t        > *** out_RETIRE_EVENT_VAL               ;
+  sc_signal<Tcontrol_t        > ***  in_RETIRE_EVENT_ACK               ;
+  sc_signal<Tevent_state_t    > *** out_RETIRE_EVENT_STATE             ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_EVENT_STOP              ;
+
+  sc_signal<Tcontrol_t        >  **  in_COMMIT_VAL                     ;
+  sc_signal<Tcontrol_t        >  ** out_COMMIT_ACK                     ;
+  sc_signal<Tcontrol_t        >  **  in_COMMIT_WEN                     ;
+  sc_signal<Tpacket_t         >  **  in_COMMIT_PACKET_ID               ;
+//sc_signal<Toperation_t      >  **  in_COMMIT_OPERATION               ;
+//sc_signal<Ttype_t           >  **  in_COMMIT_TYPE                    ;
+  sc_signal<Tspecial_data_t   >  **  in_COMMIT_FLAGS                   ;
+  sc_signal<Texception_t      >  **  in_COMMIT_EXCEPTION               ;
+  sc_signal<Tcontrol_t        >  **  in_COMMIT_NO_SEQUENCE             ;
+  sc_signal<Taddress_t        >  **  in_COMMIT_ADDRESS                 ;
+  sc_signal<Tgeneral_address_t>  ** out_COMMIT_NUM_REG_RD              ;
+
+  sc_signal<Tcontrol_t        >  ** out_REEXECUTE_VAL                  ;
+  sc_signal<Tcontrol_t        >  **  in_REEXECUTE_ACK                  ;
+  sc_signal<Tcontext_t        >  ** out_REEXECUTE_CONTEXT_ID           ;
+  sc_signal<Tcontext_t        >  ** out_REEXECUTE_FRONT_END_ID         ;
+  sc_signal<Tpacket_t         >  ** out_REEXECUTE_PACKET_ID            ;
+  sc_signal<Toperation_t      >  ** out_REEXECUTE_OPERATION            ;
+  sc_signal<Ttype_t           >  ** out_REEXECUTE_TYPE                 ;
+  sc_signal<Tlsq_ptr_t        >  ** out_REEXECUTE_STORE_QUEUE_PTR_WRITE;
+
+  sc_signal<Tcontrol_t        >  ** out_BRANCH_COMPLETE_VAL            ;
+  sc_signal<Tcontrol_t        >  **  in_BRANCH_COMPLETE_ACK            ;
+  sc_signal<Tcontext_t        >  ** out_BRANCH_COMPLETE_CONTEXT_ID     ;
+  sc_signal<Tcontext_t        >  ** out_BRANCH_COMPLETE_FRONT_END_ID   ;
+  sc_signal<Tdepth_t          >  ** out_BRANCH_COMPLETE_DEPTH          ;
+  sc_signal<Taddress_t        >  ** out_BRANCH_COMPLETE_ADDRESS        ;
+  sc_signal<Tcontrol_t        >  ** out_BRANCH_COMPLETE_NO_SEQUENCE    ;
+  sc_signal<Tcontrol_t        >  **  in_BRANCH_COMPLETE_MISS_PREDICTION;
+
+  sc_signal<Tcontrol_t        >   * out_UPDATE_VAL                     ;
+  sc_signal<Tcontrol_t        >   *  in_UPDATE_ACK                     ;
+  sc_signal<Tcontext_t        >   * out_UPDATE_CONTEXT_ID              ;
+  sc_signal<Tcontext_t        >   * out_UPDATE_FRONT_END_ID            ;
+  sc_signal<Tdepth_t          >   * out_UPDATE_DEPTH                   ;
+  sc_signal<Tevent_type_t     >   * out_UPDATE_TYPE                    ;
+  sc_signal<Tcontrol_t        >   * out_UPDATE_IS_DELAY_SLOT           ;
+  sc_signal<Taddress_t        >   * out_UPDATE_ADDRESS                 ;
+  sc_signal<Tcontrol_t        >   * out_UPDATE_ADDRESS_EPCR_VAL        ;
+  sc_signal<Taddress_t        >   * out_UPDATE_ADDRESS_EPCR            ;
+  sc_signal<Tcontrol_t        >   * out_UPDATE_ADDRESS_EEAR_VAL        ;
+  sc_signal<Tgeneral_data_t   >   * out_UPDATE_ADDRESS_EEAR            ;
+
+  sc_signal<Tcontrol_t        > ***  in_EVENT_VAL                      ;
+  sc_signal<Tcontrol_t        > *** out_EVENT_ACK                      ;
+  sc_signal<Taddress_t        > ***  in_EVENT_ADDRESS                  ;
+  sc_signal<Taddress_t        > ***  in_EVENT_ADDRESS_NEXT             ;
+  sc_signal<Tcontrol_t        > ***  in_EVENT_ADDRESS_NEXT_VAL         ;
+  sc_signal<Tcontrol_t        > ***  in_EVENT_IS_DS_TAKE               ;
+
+  sc_signal<Tcounter_t        > *** out_NB_INST_COMMIT_ALL             ;
+  sc_signal<Tcounter_t        > *** out_NB_INST_COMMIT_MEM             ;
+  sc_signal<Tcounter_t        > ***  in_NB_INST_DECOD_ALL              ;
+  sc_signal<Tdepth_t          > ***  in_DEPTH_MIN                      ;
+  sc_signal<Tdepth_t          > ***  in_DEPTH_MAX                      ;
+  sc_signal<Tcontrol_t        > ***  in_DEPTH_FULL                     ;
+
+  sc_signal<Tcontrol_t        > ***  in_SPR_READ_SR_OVE                ;
+
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_VAL                  ;
+  sc_signal<Tcontrol_t        > ***  in_SPR_WRITE_ACK                  ;
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_SR_F_VAL             ;
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_SR_F                 ;
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_SR_CY_VAL            ;
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_SR_CY                ;
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_SR_OV_VAL            ;
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_SR_OV                ;
+
+  sc_signal<bool              >   * out_INFO_ROB_EMPTY                 ;
+
   ALLOC2_SC_SIGNAL( in_INSERT_VAL                     ," in_INSERT_VAL                     ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   ALLOC2_SC_SIGNAL(out_INSERT_ACK                     ,"out_INSERT_ACK                     ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -72,8 +207,7 @@
   ALLOC2_SC_SIGNAL( in_INSERT_OPERATION               ," in_INSERT_OPERATION               ",Toperation_t      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   ALLOC2_SC_SIGNAL( in_INSERT_NO_EXECUTE              ," in_INSERT_NO_EXECUTE              ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  ALLOC2_SC_SIGNAL( in_INSERT_LAST_EVENT              ," in_INSERT_LAST_EVENT              ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   ALLOC2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT           ," in_INSERT_IS_DELAY_SLOT           ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#ifdef DEBUG
   ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS                 ," in_INSERT_ADDRESS                 ",Taddress_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#endif
   ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT            ," in_INSERT_ADDRESS_NEXT            ",Taddress_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION               ," in_INSERT_EXCEPTION               ",Texception_t      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -125,4 +259,5 @@
   ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_ACK               ," in_RETIRE_EVENT_ACK               ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_context[it1]);
   ALLOC2_SC_SIGNAL(out_RETIRE_EVENT_STATE             ,"out_RETIRE_EVENT_STATE             ",Tevent_state_t    ,_param->_nb_front_end,_param->_nb_context[it1]);
+  ALLOC2_SC_SIGNAL(out_RETIRE_EVENT_STOP              ,"out_RETIRE_EVENT_STOP              ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_context[it1]);
 
   ALLOC1_SC_SIGNAL( in_COMMIT_VAL                     ," in_COMMIT_VAL               ",Tcontrol_t        ,_param->_nb_inst_commit);
@@ -137,4 +272,5 @@
   ALLOC1_SC_SIGNAL( in_COMMIT_ADDRESS                 ," in_COMMIT_ADDRESS           ",Taddress_t        ,_param->_nb_inst_commit);
   ALLOC1_SC_SIGNAL(out_COMMIT_NUM_REG_RD              ,"out_COMMIT_NUM_REG_RD        ",Tgeneral_address_t,_param->_nb_inst_commit);
+
   ALLOC1_SC_SIGNAL(out_REEXECUTE_VAL                  ,"out_REEXECUTE_VAL                  ",Tcontrol_t        ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL( in_REEXECUTE_ACK                  ," in_REEXECUTE_ACK                  ",Tcontrol_t        ,_param->_nb_inst_reexecute);
@@ -191,4 +327,6 @@
   ALLOC2_SC_SIGNAL(out_SPR_WRITE_SR_OV                ,"out_SPR_WRITE_SR_OV                ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_context[it1]);
 
+  ALLOC0_SC_SIGNAL(out_INFO_ROB_EMPTY                 ,"out_INFO_ROB_EMPTY                 ",bool              );
+
   /********************************************************
    * Instanciation
@@ -215,4 +353,5 @@
   INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_IS_DELAY_SLOT           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NO_EXECUTE              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_LAST_EVENT              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
 #ifdef DEBUG
   INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -272,4 +411,5 @@
   INSTANCE2_SC_SIGNAL(_Commit_unit, in_RETIRE_EVENT_ACK               ,_param->_nb_front_end,_param->_nb_context[it1]);
   INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_EVENT_STATE             ,_param->_nb_front_end,_param->_nb_context[it1]);
+  INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_EVENT_STOP              ,_param->_nb_front_end,_param->_nb_context[it1]);
   INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_VAL                     ,_param->_nb_inst_commit);
   INSTANCE1_SC_SIGNAL(_Commit_unit,out_COMMIT_ACK                     ,_param->_nb_inst_commit);
@@ -351,4 +491,8 @@
   INSTANCE2_SC_SIGNAL(_Commit_unit,out_SPR_WRITE_SR_OV                ,_param->_nb_front_end,_param->_nb_context[it1]);
 
+#ifdef DEBUG_TEST
+  INSTANCE0_SC_SIGNAL(_Commit_unit,out_INFO_ROB_EMPTY                 );
+#endif
+
   msg(_("<%s> : Start Simulation ............\n"),name.c_str());
     
@@ -378,4 +522,5 @@
   in_NRESET->write(1);  
 
+#ifdef SELFTEST
   LABEL("Loop of Test");
   for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
@@ -435,4 +580,5 @@
 		  in_INSERT_IS_DELAY_SLOT           [i][j]->write(0);
 		  in_INSERT_NO_EXECUTE              [i][j]->write(0);
+		  in_INSERT_LAST_EVENT              [i][j]->write(0);
 		  in_INSERT_ADDRESS_NEXT            [i][j]->write(addr);
 		  in_INSERT_EXCEPTION               [i][j]->write(0);
@@ -608,4 +754,7 @@
 
     }
+#else
+  SC_START(10);
+#endif
 
   /********************************************************
@@ -631,8 +780,7 @@
   DELETE2_SC_SIGNAL( in_INSERT_OPERATION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_NO_EXECUTE              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  DELETE2_SC_SIGNAL( in_INSERT_LAST_EVENT              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#ifdef DEBUG
   DELETE2_SC_SIGNAL( in_INSERT_ADDRESS                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#endif
   DELETE2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_EXCEPTION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -666,10 +814,10 @@
   DELETE2_SC_SIGNAL(out_RETIRE_STORE_QUEUE_PTR_WRITE   ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
   DELETE2_SC_SIGNAL(out_RETIRE_LOAD_QUEUE_PTR_WRITE    ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
-//   DELETE2_SC_SIGNAL(out_RETIRE_READ_RA                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
-//   DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RA_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
-//   DELETE2_SC_SIGNAL(out_RETIRE_READ_RB                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
-//   DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RB_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
-//   DELETE2_SC_SIGNAL(out_RETIRE_READ_RC                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
-//   DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RC_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//DELETE2_SC_SIGNAL(out_RETIRE_READ_RA                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RA_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//DELETE2_SC_SIGNAL(out_RETIRE_READ_RB                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RB_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//DELETE2_SC_SIGNAL(out_RETIRE_READ_RC                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RC_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
   DELETE2_SC_SIGNAL(out_RETIRE_WRITE_RD                ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
   DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RD_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
@@ -683,4 +831,5 @@
   DELETE2_SC_SIGNAL( in_RETIRE_EVENT_ACK               ,_param->_nb_front_end,_param->_nb_context[it1]);
   DELETE2_SC_SIGNAL(out_RETIRE_EVENT_STATE             ,_param->_nb_front_end,_param->_nb_context[it1]);
+  DELETE2_SC_SIGNAL(out_RETIRE_EVENT_STOP              ,_param->_nb_front_end,_param->_nb_context[it1]);
   DELETE1_SC_SIGNAL( in_COMMIT_VAL               ,_param->_nb_inst_commit);
   DELETE1_SC_SIGNAL(out_COMMIT_ACK               ,_param->_nb_inst_commit);
@@ -747,4 +896,6 @@
   DELETE2_SC_SIGNAL(out_SPR_WRITE_SR_OV_VAL            ,_param->_nb_front_end,_param->_nb_context[it1]);
   DELETE2_SC_SIGNAL(out_SPR_WRITE_SR_OV                ,_param->_nb_front_end,_param->_nb_context[it1]);
+
+  DELETE0_SC_SIGNAL(out_INFO_ROB_EMPTY                 );
     }
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 128)
@@ -239,9 +239,12 @@
 
 #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true)
-    for (uint32_t i=0; i<_param->_nb_thread; ++i)
-      if (_param->_have_thread [i])
-        {
-          instruction_log_file [i].close();
-        }
+    {   
+      for (uint32_t i=0; i<_param->_nb_thread; ++i)
+        if (_param->_have_thread [i])
+          {
+            instruction_log_file [i].close();
+          }
+      delete [] instruction_log_file;
+    }
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 128)
@@ -52,5 +52,5 @@
       for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
         {
-          spr_write_val [i][j] = 0;
+          spr_write_val       [i][j] = 0;
           spr_write_sr_f_val  [i][j] = 0;
           spr_write_sr_cy_val [i][j] = 0;
@@ -63,5 +63,7 @@
     for (uint32_t i=0; i<_param->_nb_bank; i++)
       {
-	uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank;
+        uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank;
+
+        log_printf(TRACE,Commit_unit,FUNCTION,"  * BANK [%d]",num_bank);
 
         // Test if have instruction
@@ -72,127 +74,159 @@
 	    uint32_t   x     = entry->rename_unit_id;
 	    uint32_t   y     = num_inst_retire [x];
-	    bool       bypass= false;
-            // test if :
-            //  * can retire (all previous instruction is retired)
-            //  * all structure is ok (not busy)
-	    if (can_retire [x] and // in-order
-		(y < _param->_nb_inst_retire [x]) and
-		PORT_READ(in_RETIRE_ACK [x][y])) // not busy
-	      {
-		rob_state_t state        = entry->state;
-                Tcontext_t  front_end_id = entry->front_end_id;
-                Tcontext_t  context_id   = entry->context_id;  
+
+            log_printf(TRACE,Commit_unit,FUNCTION,"    * num_rename_unit        : %d",x);
+            log_printf(TRACE,Commit_unit,FUNCTION,"    * num_inst_retire        : %d",y);
+
+            if (y < _param->_nb_inst_retire [x])
+              {
+#ifdef DEBUG_TEST
+                if (x >= _param->_nb_rename_unit)
+                  throw ERRORMORPHEO(FUNCTION,toString(_("Invalid rename_unit number (%d, max is %d).\n"),x,_param->_nb_rename_unit));
+#endif
+                bool       bypass= false;
+
+                log_printf(TRACE,Commit_unit,FUNCTION,"    * can_retire             : %d",can_retire [x]);
+                log_printf(TRACE,Commit_unit,FUNCTION,"    * RETIRE_ACK             : %d",PORT_READ(in_RETIRE_ACK [x][y]));
+
+                // test if :
+                //  * can retire (all previous instruction is retired)
+                //  * all structure is ok (not busy)
+                if (can_retire [x] and // in-order
+                    PORT_READ(in_RETIRE_ACK [x][y])) // not busy
+                  {
+                    log_printf(TRACE,Commit_unit,FUNCTION,"    * valid !!!");
+
+                    rob_state_t state        = entry->state;
+                    Tcontext_t  front_end_id = entry->front_end_id;
+                    Tcontext_t  context_id   = entry->context_id;  
+
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * state                : %s",toString(state).c_str());
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * front_end_id         : %d",front_end_id);
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * context_id           : %d",context_id  );
+                    
+                    if ((state == ROB_END_OK         ) or 
+                        (state == ROB_END_KO         ) or 
+                        (state == ROB_END_BRANCH_MISS) or 
+                        (state == ROB_END_LOAD_MISS  ) or 
+                        (state == ROB_END_MISS       )//  or 
+// 		        (state == ROB_END_EXCEPTION)
+                        )
+                      {
+                        Tcontrol_t         write_re       = entry->write_re;
+                        Tspecial_address_t num_reg_re_log = entry->num_reg_re_log;
+                        
+                        // if state is ok, when write flags in the SR regsiters
+                        bool spr_write_ack = true;
+                        
+                        // Write in SR the good flag
+                        if ((state == ROB_END_OK  ) and write_re)
+                          // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE
+                          {
+                            log_printf(TRACE,Commit_unit,FUNCTION,"      * need write SR flags");
+                            log_printf(TRACE,Commit_unit,FUNCTION,"      * SPR_WRITE_ACK        : %d",PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]));
+
+                            spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]);
+                            
+                            // retire_ack is set !!!
+                            spr_write_val       [front_end_id][context_id] = 1;
+                            
+                            Tspecial_data_t flags = entry->flags;
+                            
+                            switch (num_reg_re_log)
+                              {
+                              case SPR_LOGIC_SR_F     : 
+                                {
+                                  spr_write_sr_f_val  [front_end_id][context_id] = 1;
+                                  spr_write_sr_f      [front_end_id][context_id] = (flags & FLAG_F )!=0;
+                                  
+                                  break;
+                                }
+                              case SPR_LOGIC_SR_CY_OV :
+                                {
+                                  spr_write_sr_cy_val [front_end_id][context_id] = 1;
+                                  spr_write_sr_ov_val [front_end_id][context_id] = 1;	
+                                  spr_write_sr_cy     [front_end_id][context_id] = (flags & FLAG_CY)!=0;
+                                  spr_write_sr_ov     [front_end_id][context_id] = (flags & FLAG_OV)!=0;
+                                  
+                                  break;
+                                }
+                              default : 
+                                {
+#ifdef DEBUG_TEST
+                                  throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n"));
+#endif
+                                }
+                              }
+                          }
+                        
+                        // find an instruction can be retire, and in order
+                        
+                        if (spr_write_ack)
+                          {
+                            retire_val [x][y] = 1;
+                            num_inst_retire [x] ++;
+                            internal_BANK_RETIRE_VAL [num_bank] = true;
+                          }
+                        
+                        internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x;
+                        internal_BANK_RETIRE_NUM_INST        [num_bank] = y;
+                        
+                        if (_param->_have_port_front_end_id)
+                        PORT_WRITE(out_RETIRE_FRONT_END_ID          [x][y], front_end_id                );
+                        if (_param->_have_port_context_id)
+                        PORT_WRITE(out_RETIRE_CONTEXT_ID            [x][y], context_id                  );
+// 		        PORT_WRITE(out_RETIRE_RENAME_UNIT_ID        [x][y], entry->rename_unit_id       );
+                        PORT_WRITE(out_RETIRE_USE_STORE_QUEUE       [x][y], entry->use_store_queue      );
+                        PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE        [x][y], entry->use_load_queue       );
+                        PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write);
+                        if (_param->_have_port_load_queue_ptr)
+		        PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE  [x][y], entry->load_queue_ptr_write );
+//                      PORT_WRITE(out_RETIRE_READ_RA               [x][y], entry->read_ra              );
+//                      PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY        [x][y], entry->num_reg_ra_phy       );
+//                      PORT_WRITE(out_RETIRE_READ_RB               [x][y], entry->read_rb              );
+//                      PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY        [x][y], entry->num_reg_rb_phy       );
+//                      PORT_WRITE(out_RETIRE_READ_RC               [x][y], entry->read_rc              );
+//                      PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY        [x][y], entry->num_reg_rc_phy       );
+                        PORT_WRITE(out_RETIRE_WRITE_RD              [x][y], entry->write_rd             );
+                        PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG        [x][y], entry->num_reg_rd_log       );
+                        PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD    [x][y], entry->num_reg_rd_phy_old   );
+                        PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW    [x][y], entry->num_reg_rd_phy_new   );
+                        PORT_WRITE(out_RETIRE_WRITE_RE              [x][y], write_re                    );
+                        PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG        [x][y], num_reg_re_log              );
+                        PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD    [x][y], entry->num_reg_re_phy_old   );
+                        PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW    [x][y], entry->num_reg_re_phy_new   );
+                        
+                        // Event -> rob must be manage this event
+                        if ((state == ROB_END_BRANCH_MISS) or
+                            (state == ROB_END_LOAD_MISS))
+                          can_retire [x] = false;
+                      }
+
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * bypass (before)      : %d",bypass);
+
+                    bypass = ((state == ROB_END              ) or 
+                              (state == ROB_STORE_OK         ) or 
+                              (state == ROB_STORE_KO         ) or
+                              (state == ROB_STORE_OK_WAIT_END) or 
+                              (state == ROB_STORE_KO_WAIT_END));
+
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * bypass (after)       : %d",bypass);
+                    
+                    uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank);
+
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * packet               : %d",packet);
+                    
+                    // if future event, don't update after this event
+                    if ((reg_EVENT_STATE  [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and
+                        (reg_EVENT_PACKET [front_end_id][context_id] == packet))
+                      {
+                        log_printf(TRACE,Commit_unit,FUNCTION,"      * is the event instruction, stop bypass !!!");
+                        bypass = false;
+                      }
+                  }
                 
-                  if ((state == ROB_END_OK         ) or 
-                      (state == ROB_END_KO         ) or 
-                      (state == ROB_END_BRANCH_MISS) or 
-                      (state == ROB_END_LOAD_MISS  ) or 
-                      (state == ROB_END_MISS       )//  or 
-// 		      (state == ROB_END_EXCEPTION)
-                      )
-                    {
-                      Tcontrol_t         write_re       = entry->write_re;
-                      Tspecial_address_t num_reg_re_log = entry->num_reg_re_log;
-                      
-                      // if state is ok, when write flags in the SR regsiters
-                      bool spr_write_ack = true;
-                      
-                      // Write in SR the good flag
-                      if ((state == ROB_END_OK  ) and write_re)
-                        // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE
-                        {
-                          spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]);
-                          
-                          // retire_ack is set !!!
-                          spr_write_val       [front_end_id][context_id] = 1;
-                          
-                          Tspecial_data_t flags = entry->flags;
-                          
-                          switch (num_reg_re_log)
-                            {
-                            case SPR_LOGIC_SR_F     : 
-                              {
-                                spr_write_sr_f_val  [front_end_id][context_id] = 1;
-                                spr_write_sr_f      [front_end_id][context_id] = (flags & FLAG_F )!=0;
-                                
-                                break;
-                              }
-                            case SPR_LOGIC_SR_CY_OV :
-                              {
-                                spr_write_sr_cy_val [front_end_id][context_id] = 1;
-                                spr_write_sr_ov_val [front_end_id][context_id] = 1;	
-                                spr_write_sr_cy     [front_end_id][context_id] = (flags & FLAG_CY)!=0;
-                                spr_write_sr_ov     [front_end_id][context_id] = (flags & FLAG_OV)!=0;
-                                
-                                break;
-                              }
-                            default : 
-                              {
-#ifdef DEBUG_TEST
-                                throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n"));
-#endif
-                              }
-                            }
-                        }
-                      
-                      // find an instruction can be retire, and in order
-                      
-                      if (spr_write_ack)
-                        {
-                          retire_val [x][y] = 1;
-                          num_inst_retire [x] ++;
-                          internal_BANK_RETIRE_VAL [num_bank] = true;
-                        }
-                      
-                      internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x;
-                      internal_BANK_RETIRE_NUM_INST        [num_bank] = y;
-                      
-                      if (_param->_have_port_front_end_id)
-                      PORT_WRITE(out_RETIRE_FRONT_END_ID          [x][y], front_end_id                );
-                      if (_param->_have_port_context_id)
-                      PORT_WRITE(out_RETIRE_CONTEXT_ID            [x][y], context_id                  );
-// 		      PORT_WRITE(out_RETIRE_RENAME_UNIT_ID        [x][y], entry->rename_unit_id       );
-                      PORT_WRITE(out_RETIRE_USE_STORE_QUEUE       [x][y], entry->use_store_queue      );
-                      PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE        [x][y], entry->use_load_queue       );
-                      PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write);
-                      if (_param->_have_port_load_queue_ptr)
-		      PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE  [x][y], entry->load_queue_ptr_write );
-//                       PORT_WRITE(out_RETIRE_READ_RA               [x][y], entry->read_ra              );
-//                       PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY        [x][y], entry->num_reg_ra_phy       );
-//                       PORT_WRITE(out_RETIRE_READ_RB               [x][y], entry->read_rb              );
-//                       PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY        [x][y], entry->num_reg_rb_phy       );
-//                       PORT_WRITE(out_RETIRE_READ_RC               [x][y], entry->read_rc              );
-//                       PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY        [x][y], entry->num_reg_rc_phy       );
-                      PORT_WRITE(out_RETIRE_WRITE_RD              [x][y], entry->write_rd             );
-                      PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG        [x][y], entry->num_reg_rd_log       );
-                      PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD    [x][y], entry->num_reg_rd_phy_old   );
-                      PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW    [x][y], entry->num_reg_rd_phy_new   );
-                      PORT_WRITE(out_RETIRE_WRITE_RE              [x][y], write_re                    );
-                      PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG        [x][y], num_reg_re_log              );
-                      PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD    [x][y], entry->num_reg_re_phy_old   );
-                      PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW    [x][y], entry->num_reg_re_phy_new   );
-
-                      // Event -> rob must be manage this event
-                      if ((state == ROB_END_BRANCH_MISS) or
-                          (state == ROB_END_LOAD_MISS))
-                        can_retire [x] = false;
-                    }
-
-                  bypass = ((state == ROB_END              ) or 
-                            (state == ROB_STORE_OK         ) or 
-                            (state == ROB_STORE_KO         ) or
-                            (state == ROB_STORE_OK_WAIT_END) or 
-                            (state == ROB_STORE_KO_WAIT_END));
-                  
-                  uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank);
-
-                  // if future event, don't update after this event
-                  if ((reg_EVENT_STATE  [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and
-                      (reg_EVENT_PACKET [entry->front_end_id][entry->context_id] == packet))
-                    bypass = false;
-	      }
-
-	    // Retire "in-order"
-	    can_retire [x]  &= (retire_val [x][y] or bypass);
+                // Retire "in-order"
+                can_retire [x]  &= (retire_val [x][y] or bypass);
+              }
 	  }
       }
@@ -219,4 +253,8 @@
           for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++)
             PORT_WRITE(out_RETIRE_VAL [i][j],0);
+
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            PORT_WRITE(out_SPR_WRITE_VAL [i][j], 0);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 128)
@@ -54,8 +54,15 @@
 //            reg_EVENT_FLUSH           [i][j] = false;
 //            reg_EVENT_STOP            [i][j] = false;
+              reg_EVENT_NUM_BANK        [i][j] = 0; // not necessary
+              reg_EVENT_NUM_PTR         [i][j] = 0; // not necessary
+            //reg_EVENT_CAN_RESTART     [i][j] = 0; // not necessary
+              reg_EVENT_PACKET          [i][j] = 0; // not necessary
               reg_EVENT_NB_INST         [i][j] = 0;
               reg_EVENT_LAST            [i][j] = false;
+              reg_EVENT_LAST_NUM_BANK   [i][j] = 0; // not necessary
+              reg_EVENT_LAST_NUM_PTR    [i][j] = 0; // not necessary
 
               reg_EVENT_NEXT_STOP       [i][j] = false;
+              reg_EVENT_NEXT_PACKET     [i][j] = 0; // not necessary
 
 //            reg_PC_PREVIOUS           [i][j] = (0x100-4)>>2;
@@ -274,8 +281,12 @@
 	              entry->num_reg_re_phy_old      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD    [x][y]);
 	              entry->num_reg_re_phy_new      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW    [x][y]);
+
+                      entry->flags                   = 0; // not necessary
                       entry->no_sequence             = type == TYPE_BRANCH;
 //                    entry->speculative             = true;
 #ifdef DEBUG        
 	              entry->address                 = PORT_READ(in_INSERT_ADDRESS               [x][y]);
+#else
+                      entry->address                 = 0; // not necessary
 #endif                
 	              entry->address_next            = PORT_READ(in_INSERT_ADDRESS_NEXT          [x][y]);
@@ -1339,5 +1350,5 @@
                              (*it)->flags         ,
                              (*it)->no_sequence   ,
-//                              (*it)->speculative   ,
+//                           (*it)->speculative   ,
                              (*it)->address       ,
                              (*it)->address<<2    ,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/test.cpp	(revision 128)
@@ -57,4 +57,6 @@
   sc_signal<Ttype_t           > ***  in_ISSUE_IN_TYPE                  ;
   sc_signal<Tlsq_ptr_t        > ***  in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ;
+  sc_signal<Tlsq_ptr_t        > ***  in_ISSUE_IN_STORE_QUEUE_PTR_READ  ;
+  sc_signal<Tcontrol_t        > ***  in_ISSUE_IN_STORE_QUEUE_EMPTY     ;
   sc_signal<Tlsq_ptr_t        > ***  in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE  ;
   sc_signal<Tcontrol_t        > ***  in_ISSUE_IN_HAS_IMMEDIAT          ;
@@ -78,4 +80,6 @@
   sc_signal<Ttype_t           >  **  in_REEXECUTE_TYPE                 ;
   sc_signal<Tlsq_ptr_t        >  **  in_REEXECUTE_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t        >  **  in_REEXECUTE_STORE_QUEUE_PTR_READ ;
+  sc_signal<Tcontrol_t        >  **  in_REEXECUTE_STORE_QUEUE_EMPTY    ;
   sc_signal<Tlsq_ptr_t        >  **  in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ;
   sc_signal<Tcontrol_t        >  **  in_REEXECUTE_HAS_IMMEDIAT         ;
@@ -99,4 +103,6 @@
   sc_signal<Ttype_t           >  ** out_ISSUE_OUT_TYPE                 ;
   sc_signal<Tlsq_ptr_t        >  ** out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t        >  ** out_ISSUE_OUT_STORE_QUEUE_PTR_READ ;
+  sc_signal<Tcontrol_t        >  ** out_ISSUE_OUT_STORE_QUEUE_EMPTY    ;
   sc_signal<Tlsq_ptr_t        >  ** out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ;
   sc_signal<Tcontrol_t        >  ** out_ISSUE_OUT_HAS_IMMEDIAT         ;
@@ -121,4 +127,6 @@
   ALLOC2_SC_SIGNAL( in_ISSUE_IN_TYPE                  ," in_ISSUE_IN_TYPE                  ",Ttype_t           ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]);
   ALLOC2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ," in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t        ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]);
+  ALLOC2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_PTR_READ  ," in_ISSUE_IN_STORE_QUEUE_PTR_READ  ",Tlsq_ptr_t        ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]);
+  ALLOC2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_EMPTY     ," in_ISSUE_IN_STORE_QUEUE_EMPTY     ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]);
   ALLOC2_SC_SIGNAL( in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE  ," in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE  ",Tlsq_ptr_t        ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]);
   ALLOC2_SC_SIGNAL( in_ISSUE_IN_HAS_IMMEDIAT          ," in_ISSUE_IN_HAS_IMMEDIAT          ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]);
@@ -142,4 +150,6 @@
   ALLOC1_SC_SIGNAL( in_REEXECUTE_TYPE                 ," in_REEXECUTE_TYPE                 ",Ttype_t           ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_PTR_WRITE," in_REEXECUTE_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t        ,_param->_nb_inst_reexecute);
+  ALLOC1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_PTR_READ ," in_REEXECUTE_STORE_QUEUE_PTR_READ ",Tlsq_ptr_t        ,_param->_nb_inst_reexecute);
+  ALLOC1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_EMPTY    ," in_REEXECUTE_STORE_QUEUE_EMPTY    ",Tcontrol_t        ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL( in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ," in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t        ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL( in_REEXECUTE_HAS_IMMEDIAT         ," in_REEXECUTE_HAS_IMMEDIAT         ",Tcontrol_t        ,_param->_nb_inst_reexecute);
@@ -163,4 +173,6 @@
   ALLOC1_SC_SIGNAL(out_ISSUE_OUT_TYPE                 ,"out_ISSUE_OUT_TYPE                 ",Ttype_t           ,_param->_nb_inst_issue);
   ALLOC1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE,"out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t        ,_param->_nb_inst_issue);
+  ALLOC1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_PTR_READ ,"out_ISSUE_OUT_STORE_QUEUE_PTR_READ ",Tlsq_ptr_t        ,_param->_nb_inst_issue);
+  ALLOC1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_EMPTY    ,"out_ISSUE_OUT_STORE_QUEUE_EMPTY    ",Tcontrol_t        ,_param->_nb_inst_issue);
   ALLOC1_SC_SIGNAL(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ,"out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t        ,_param->_nb_inst_issue);
   ALLOC1_SC_SIGNAL(out_ISSUE_OUT_HAS_IMMEDIAT         ,"out_ISSUE_OUT_HAS_IMMEDIAT         ",Tcontrol_t        ,_param->_nb_inst_issue);
@@ -197,4 +209,6 @@
   INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_TYPE                  ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
   INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
+  INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_STORE_QUEUE_PTR_READ  ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
+  INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_STORE_QUEUE_EMPTY     ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE  ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
@@ -223,4 +237,6 @@
   INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_TYPE                 ,_param->_nb_inst_reexecute);
   INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute);
+  INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_STORE_QUEUE_PTR_READ ,_param->_nb_inst_reexecute);
+  INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_STORE_QUEUE_EMPTY    ,_param->_nb_inst_reexecute);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute);
@@ -249,4 +265,6 @@
   INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_TYPE                 ,_param->_nb_inst_issue);
   INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_issue);
+  INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_STORE_QUEUE_PTR_READ ,_param->_nb_inst_issue);
+  INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_STORE_QUEUE_EMPTY    ,_param->_nb_inst_issue);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_issue);
@@ -423,4 +441,6 @@
   DELETE2_SC_SIGNAL( in_ISSUE_IN_TYPE                  ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
   DELETE2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
+  DELETE2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_PTR_READ  ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
+  DELETE2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_EMPTY     ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
   DELETE2_SC_SIGNAL( in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE  ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
   DELETE2_SC_SIGNAL( in_ISSUE_IN_HAS_IMMEDIAT          ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
@@ -445,4 +465,6 @@
   DELETE1_SC_SIGNAL( in_REEXECUTE_TYPE                 ,_param->_nb_inst_reexecute);
   DELETE1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute);
+  DELETE1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_PTR_READ ,_param->_nb_inst_reexecute);
+  DELETE1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_EMPTY    ,_param->_nb_inst_reexecute);
   DELETE1_SC_SIGNAL( in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute);
   DELETE1_SC_SIGNAL( in_REEXECUTE_HAS_IMMEDIAT         ,_param->_nb_inst_reexecute);
@@ -467,4 +489,6 @@
   DELETE1_SC_SIGNAL(out_ISSUE_OUT_TYPE                 ,_param->_nb_inst_issue);
   DELETE1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_issue);
+  DELETE1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_PTR_READ ,_param->_nb_inst_issue);
+  DELETE1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_EMPTY    ,_param->_nb_inst_issue);
   DELETE1_SC_SIGNAL(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_issue);
   DELETE1_SC_SIGNAL(out_ISSUE_OUT_HAS_IMMEDIAT         ,_param->_nb_inst_issue);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp	(revision 128)
@@ -156,8 +156,4 @@
 
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-    ALLOC1(internal_BANK_IN_ACK             ,Tcontrol_t,_param->_nb_bank);
-    ALLOC1(internal_BANK_IN_NUM_RENAME_UNIT ,uint32_t  ,_param->_nb_bank);
-    ALLOC1(internal_BANK_IN_NUM_INST        ,uint32_t  ,_param->_nb_bank);
-
     ALLOC1(internal_ISSUE_OUT_VAL           ,Tcontrol_t,_param->_nb_inst_issue);
     ALLOC1(internal_ISSUE_OUT_FROM_REEXECUTE,Tcontrol_t,_param->_nb_inst_issue);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp	(revision 128)
@@ -101,4 +101,10 @@
 
         // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+	while (not _reexecute_queue.empty())
+	  {
+	    delete _reexecute_queue.front();
+	    _reexecute_queue.pop_front();
+	  }
+
         DELETE1(_issue_queue                     ,_param->_nb_bank);
         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_transition.cpp	(revision 128)
@@ -105,9 +105,9 @@
                 log_printf(TRACE,Issue_queue,FUNCTION,"  * ISSUE_OUT [%d] - From issue_queue [%d]",i,num_bank);
                 
+                delete entry;
+                
                 _issue_queue [num_bank].remove(entry);
-                
+
                 reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank;
-                
-                delete entry;
               } 
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_transition.cpp	(revision 128)
@@ -101,6 +101,7 @@
                 log_printf(TRACE,Issue_queue,FUNCTION,"  * ISSUE_OUT [%d] - From issue_queue [%d]",i,num_bank);
                 
+                delete entry;
+
                 _issue_queue [num_bank].remove(entry);
-                delete entry;
               } 
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/main.cpp	(revision 128)
@@ -108,4 +108,6 @@
       
       test (name,param);
+
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/test.cpp	(revision 128)
@@ -48,4 +48,127 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
+  sc_signal<Tcontext_t         > ***  in_RENAME_FRONT_END_ID                     ;
+  sc_signal<Tcontext_t         > *** out_RENAME_RENAME_UNIT_FRONT_END_ID         ;
+
+  sc_signal<Tcontrol_t         >  ** out_INSERT_VAL                              ;
+  sc_signal<Tcontrol_t         >  **  in_INSERT_ACK                              ;
+  sc_signal<Tcontrol_t         >  ** out_INSERT_RD_USE                           ;
+  sc_signal<Tgeneral_address_t >  ** out_INSERT_RD_NUM_REG                       ;
+  sc_signal<Tcontrol_t         >  ** out_INSERT_RE_USE                           ;
+  sc_signal<Tspecial_address_t >  ** out_INSERT_RE_NUM_REG                       ;
+
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_VAL                  ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_RENAME_UNIT_ACK                  ;
+  sc_signal<Tcontext_t         > ***  in_INSERT_RENAME_UNIT_FRONT_END_ID         ;
+  sc_signal<Tcontext_t         > ***  in_INSERT_RENAME_UNIT_CONTEXT_ID           ;
+  sc_signal<Ttype_t            > ***  in_INSERT_RENAME_UNIT_TYPE                 ;
+  sc_signal<Toperation_t       > ***  in_INSERT_RENAME_UNIT_OPERATION            ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_NO_EXECUTE           ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_HAS_IMMEDIAT         ;
+  sc_signal<Tgeneral_data_t    > ***  in_INSERT_RENAME_UNIT_IMMEDIAT             ;
+  sc_signal<Tlsq_ptr_t         > ***  in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t         > ***  in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY    ;
+  sc_signal<Tlsq_ptr_t         > ***  in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_READ_RA              ;
+  sc_signal<Tgeneral_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RA_PHY       ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_READ_RB              ;
+  sc_signal<Tgeneral_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RB_PHY       ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_READ_RC              ;
+  sc_signal<Tspecial_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RC_PHY       ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_WRITE_RD             ;
+  sc_signal<Tgeneral_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_OLD   ;
+  sc_signal<Tgeneral_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_NEW   ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_WRITE_RE             ;
+  sc_signal<Tspecial_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_OLD   ;
+  sc_signal<Tspecial_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW   ;
+
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_VAL                  ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_COMMIT_UNIT_ACK                  ;
+  sc_signal<Tcontext_t         > *** out_INSERT_COMMIT_UNIT_FRONT_END_ID         ;
+  sc_signal<Tcontext_t         > *** out_INSERT_COMMIT_UNIT_CONTEXT_ID           ;
+//sc_signal<Tcontext_t         > *** out_INSERT_COMMIT_UNIT_RENAME_UNIT_ID       ;
+  sc_signal<Ttype_t            > *** out_INSERT_COMMIT_UNIT_TYPE                 ;
+  sc_signal<Toperation_t       > *** out_INSERT_COMMIT_UNIT_OPERATION            ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_NO_EXECUTE           ;
+  sc_signal<Tlsq_ptr_t         > *** out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE;
+//   sc_signal<Tlsq_ptr_t         > *** out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_READ ;
+//   sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_STORE_QUEUE_EMPTY    ;
+  sc_signal<Tlsq_ptr_t         > *** out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_READ_RA              ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RA_PHY       ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_READ_RB              ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RB_PHY       ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_READ_RC              ;
+  sc_signal<Tspecial_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RC_PHY       ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_WRITE_RD             ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_OLD   ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_NEW   ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_WRITE_RE             ;
+  sc_signal<Tspecial_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_OLD   ;
+  sc_signal<Tspecial_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_NEW   ;
+
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_VAL                  ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_ISSUE_QUEUE_ACK                  ;
+  sc_signal<Tcontext_t         > *** out_INSERT_ISSUE_QUEUE_CONTEXT_ID           ;
+  sc_signal<Tcontext_t         > *** out_INSERT_ISSUE_QUEUE_FRONT_END_ID         ;
+  sc_signal<Toperation_t       > *** out_INSERT_ISSUE_QUEUE_OPERATION            ;
+  sc_signal<Ttype_t            > *** out_INSERT_ISSUE_QUEUE_TYPE                 ;
+  sc_signal<Tlsq_ptr_t         > *** out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t         > *** out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY    ;
+  sc_signal<Tlsq_ptr_t         > *** out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT         ;
+  sc_signal<Tgeneral_data_t    > *** out_INSERT_ISSUE_QUEUE_IMMEDIAT             ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_READ_RA              ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_ISSUE_QUEUE_NUM_REG_RA           ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_READ_RB              ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_ISSUE_QUEUE_NUM_REG_RB           ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_READ_RC              ;
+  sc_signal<Tspecial_address_t > *** out_INSERT_ISSUE_QUEUE_NUM_REG_RC           ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_WRITE_RD             ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_ISSUE_QUEUE_NUM_REG_RD           ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_WRITE_RE             ;
+  sc_signal<Tspecial_address_t > *** out_INSERT_ISSUE_QUEUE_NUM_REG_RE           ;
+
+//sc_signal<Tcontrol_t         >  ** out_RETIRE_VAL                              ;
+//sc_signal<Tcontrol_t         >  **  in_RETIRE_ACK                              ;
+//sc_signal<Tcontrol_t         >  ** out_RETIRE_RD_OLD_USE                       ;
+//sc_signal<Tgeneral_address_t >  ** out_RETIRE_RD_OLD_NUM_REG                   ;
+//sc_signal<Tcontrol_t         >  ** out_RETIRE_RD_NEW_USE                       ;
+//sc_signal<Tgeneral_address_t >  ** out_RETIRE_RD_NEW_NUM_REG                   ;
+//sc_signal<Tcontrol_t         >  ** out_RETIRE_RE_OLD_USE                       ;
+//sc_signal<Tspecial_address_t >  ** out_RETIRE_RE_OLD_NUM_REG                   ;
+//sc_signal<Tcontrol_t         >  ** out_RETIRE_RE_NEW_USE                       ;
+//sc_signal<Tspecial_address_t >  ** out_RETIRE_RE_NEW_NUM_REG                   ;
+
+//sc_signal<Tcontrol_t         > *** out_RETIRE_RENAME_UNIT_VAL                  ;
+//sc_signal<Tcontrol_t         > ***  in_RETIRE_RENAME_UNIT_ACK                  ;
+//sc_signal<Tcontext_t         > *** out_RETIRE_RENAME_UNIT_FRONT_END_ID         ;
+//sc_signal<Tcontrol_t         > *** out_RETIRE_RENAME_UNIT_WRITE_RD             ;
+//sc_signal<Tgeneral_address_t > *** out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_OLD   ;
+//sc_signal<Tgeneral_address_t > *** out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_NEW   ;
+//sc_signal<Tcontrol_t         > *** out_RETIRE_RENAME_UNIT_WRITE_RE             ;
+//sc_signal<Tspecial_address_t > *** out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_OLD   ;
+//sc_signal<Tspecial_address_t > *** out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_NEW   ;
+//sc_signal<Tevent_state_t     > *** out_RETIRE_RENAME_UNIT_EVENT_STATE          ;
+
+//sc_signal<Tcontrol_t         > ***  in_RETIRE_COMMIT_UNIT_VAL                  ;
+//sc_signal<Tcontrol_t         > *** out_RETIRE_COMMIT_UNIT_ACK                  ;
+//sc_signal<Tcontext_t         > ***  in_RETIRE_COMMIT_UNIT_FRONT_END_ID         ;
+//sc_signal<Tcontrol_t         > ***  in_RETIRE_COMMIT_UNIT_WRITE_RD             ;
+//sc_signal<Tgeneral_address_t > ***  in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_OLD   ;
+//sc_signal<Tgeneral_address_t > ***  in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_NEW   ;
+//sc_signal<Tcontrol_t         > ***  in_RETIRE_COMMIT_UNIT_WRITE_RE             ;
+//sc_signal<Tspecial_address_t > ***  in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_OLD   ;
+//sc_signal<Tspecial_address_t > ***  in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW   ;
+//sc_signal<Tevent_state_t     > ***  in_RETIRE_COMMIT_UNIT_EVENT_STATE          ;
+
+  sc_signal<Tcontrol_t         > *** out_SPR_SR_IEE                              ;
+  sc_signal<Tcontrol_t         > *** out_SPR_SR_EPH                              ;
+  sc_signal<Tspr_t             > *** out_SPR_RENAME_UNIT_SR                      ;
+  sc_signal<Tcontrol_t         > *** out_SPR_COMMIT_UNIT_SR_OVE                  ;
+  sc_signal<Tspr_t             > ***  in_SPR_SPECIAL_REGISTER_UNIT_SR            ;
+
   ALLOC2_SC_SIGNAL( in_RENAME_FRONT_END_ID                     ," in_RENAME_FRONT_END_ID                     ",Tcontext_t         ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);                               
   ALLOC2_SC_SIGNAL(out_RENAME_RENAME_UNIT_FRONT_END_ID         ,"out_RENAME_RENAME_UNIT_FRONT_END_ID         ",Tcontext_t         ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);                               
@@ -68,4 +191,6 @@
   ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_IMMEDIAT             ," in_INSERT_RENAME_UNIT_IMMEDIAT             ",Tgeneral_data_t    ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE," in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
+  ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ ," in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ ",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
+  ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY    ," in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY    ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE ," in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_READ_RA              ," in_INSERT_RENAME_UNIT_READ_RA              ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
@@ -91,4 +216,6 @@
   ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NO_EXECUTE           ,"out_INSERT_COMMIT_UNIT_NO_EXECUTE           ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE,"out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
+//   ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_READ ,"out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_READ ",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
+//   ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_EMPTY    ,"out_INSERT_COMMIT_UNIT_STORE_QUEUE_EMPTY    ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE ,"out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_READ_RA              ,"out_INSERT_COMMIT_UNIT_READ_RA              ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
@@ -112,4 +239,6 @@
   ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_TYPE                 ,"out_INSERT_ISSUE_QUEUE_TYPE                 ",Ttype_t            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE,"out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
+  ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ ,"out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ ",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
+  ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY    ,"out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY    ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ,"out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT         ,"out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT         ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
@@ -199,4 +328,6 @@
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_IMMEDIAT                  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -225,4 +356,6 @@
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_NO_EXECUTE                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+//   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+//   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -251,4 +384,6 @@
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_TYPE                      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -399,4 +534,6 @@
   DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_IMMEDIAT                  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_READ_RA                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -422,4 +559,6 @@
   DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NO_EXECUTE                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+//   DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+//   DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_READ_RA                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -443,4 +582,6 @@
   DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_TYPE                      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_deallocation.cpp	(revision 128)
@@ -71,4 +71,5 @@
         DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_TYPE                      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type            );
         DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_OPERATION                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_operation       );
+        DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_NO_EXECUTE                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1);
         DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr );
         DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr  );
@@ -95,4 +96,6 @@
         DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_TYPE                      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type            );
         DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr );
+        DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr );
+        DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1);
         DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr  );
         DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                             );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert.cpp	(revision 128)
@@ -54,6 +54,6 @@
           Tspecial_address_t NUM_REG_RE_PHY_NEW    = PORT_READ(in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW    [i][j]);
 
-          Tgeneral_address_t general_address_msb   = FRONT_END_ID << _param->_size_general_register;
-          Tspecial_address_t special_address_msb   = FRONT_END_ID << _param->_size_special_register;
+          Tgeneral_address_t general_address_msb   = i << _param->_size_general_register;
+          Tspecial_address_t special_address_msb   = i << _param->_size_special_register;
           
           PORT_WRITE(out_INSERT_RD_USE                            [x]   ,WRITE_RD);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters.cpp	(revision 128)
@@ -7,4 +7,5 @@
 
 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Parameters.h"
+#include "Behavioural/include/Allocation.h"
 #include "Common/include/Max.h"
 #include "Common/include/BitManipulation.h"
@@ -61,5 +62,5 @@
       }
 
-    _translate_front_end_id_to_rename_unit  = new uint32_t [_nb_front_end];
+    ALLOC1(_translate_front_end_id_to_rename_unit,uint32_t,_nb_front_end);
     
     for (uint32_t i=0; i<_nb_front_end; i++)
@@ -119,5 +120,7 @@
   {
     log_begin(OOO_Engine_Glue,FUNCTION);
-    delete _translate_front_end_id_to_rename_unit;
+
+    DELETE1(_translate_front_end_id_to_rename_unit,_nb_front_end);
+ 
     log_end(OOO_Engine_Glue,FUNCTION);
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/main.cpp	(revision 128)
@@ -101,4 +101,6 @@
       
       test (name,param);
+
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/test.cpp	(revision 128)
@@ -137,4 +137,75 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
+  sc_signal<Tcontrol_t         > ***  in_EXECUTE_LOOP_VAL                     ;
+  sc_signal<Tcontrol_t         > *** out_EXECUTE_LOOP_ACK                     ;
+  sc_signal<Tcontext_t         > ***  in_EXECUTE_LOOP_CONTEXT_ID              ;
+  sc_signal<Tcontext_t         > ***  in_EXECUTE_LOOP_FRONT_END_ID            ;
+  sc_signal<Tpacket_t          > ***  in_EXECUTE_LOOP_PACKET_ID               ;
+//sc_signal<Toperation_t       > ***  in_EXECUTE_LOOP_OPERATION               ;
+//sc_signal<Ttype_t            > ***  in_EXECUTE_LOOP_TYPE                    ;
+  sc_signal<Tspecial_data_t    > ***  in_EXECUTE_LOOP_FLAGS                   ;
+  sc_signal<Texception_t       > ***  in_EXECUTE_LOOP_EXCEPTION               ;
+  sc_signal<Tcontrol_t         > ***  in_EXECUTE_LOOP_NO_SEQUENCE             ;
+  sc_signal<Tgeneral_data_t    > ***  in_EXECUTE_LOOP_ADDRESS                 ;
+  sc_signal<Tgeneral_data_t    > ***  in_EXECUTE_LOOP_DATA                    ;
+
+  sc_signal<Tcontrol_t         >  ** out_COMMIT_VAL                           ;
+  sc_signal<Tcontrol_t         >  **  in_COMMIT_ACK                           ;
+  sc_signal<Tcontrol_t         >  ** out_COMMIT_WEN                           ;
+  sc_signal<Tcontext_t         >  ** out_COMMIT_CONTEXT_ID                    ;
+  sc_signal<Tcontext_t         >  ** out_COMMIT_FRONT_END_ID                  ;
+  sc_signal<Tpacket_t          >  ** out_COMMIT_PACKET_ID                     ;
+//sc_signal<Toperation_t       >  ** out_COMMIT_OPERATION                     ;
+//sc_signal<Ttype_t            >  ** out_COMMIT_TYPE                          ;
+  sc_signal<Tspecial_data_t    >  ** out_COMMIT_FLAGS                         ;
+  sc_signal<Texception_t       >  ** out_COMMIT_EXCEPTION                     ;
+  sc_signal<Tcontrol_t         >  ** out_COMMIT_NO_SEQUENCE                   ;
+  sc_signal<Tgeneral_data_t    >  ** out_COMMIT_ADDRESS                       ;
+  sc_signal<Tgeneral_address_t >  **  in_COMMIT_NUM_REG_RD                    ;
+
+  sc_signal<Tcontrol_t         >  ** out_SPR_VAL                              ;
+  sc_signal<Tcontrol_t         >  **  in_SPR_ACK                              ;
+  sc_signal<Tcontrol_t         >  ** out_SPR_WEN                              ;
+  sc_signal<Tcontext_t         >  ** out_SPR_CONTEXT_ID                       ;
+  sc_signal<Tcontext_t         >  ** out_SPR_FRONT_END_ID                     ;
+  sc_signal<Tspr_address_t     >  ** out_SPR_NUM_GROUP                        ;
+  sc_signal<Tspr_address_t     >  ** out_SPR_NUM_REG                          ;
+  sc_signal<Tspr_t             >  ** out_SPR_WDATA                            ;
+  sc_signal<Tspr_t             >  **  in_SPR_RDATA                            ;
+  sc_signal<Tcontrol_t         >  **  in_SPR_INVALID                          ;
+
+  sc_signal<Tcontrol_t         >  **  in_REEXECUTE_ROB_VAL                    ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_ROB_ACK                    ;
+  sc_signal<Tcontext_t         >  **  in_REEXECUTE_ROB_CONTEXT_ID             ;
+  sc_signal<Tcontext_t         >  **  in_REEXECUTE_ROB_FRONT_END_ID           ;
+  sc_signal<Tpacket_t          >  **  in_REEXECUTE_ROB_PACKET_ID              ;
+  sc_signal<Toperation_t       >  **  in_REEXECUTE_ROB_OPERATION              ;
+  sc_signal<Ttype_t            >  **  in_REEXECUTE_ROB_TYPE                   ;
+  sc_signal<Tlsq_ptr_t         >  **  in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE  ;
+
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_VAL                        ;
+  sc_signal<Tcontrol_t         >  **  in_REEXECUTE_ACK                        ;
+  sc_signal<Tcontext_t         >  ** out_REEXECUTE_CONTEXT_ID                 ;
+  sc_signal<Tcontext_t         >  ** out_REEXECUTE_FRONT_END_ID               ;
+  sc_signal<Tpacket_t          >  ** out_REEXECUTE_PACKET_ID                  ;
+  sc_signal<Toperation_t       >  ** out_REEXECUTE_OPERATION                  ;
+  sc_signal<Ttype_t            >  ** out_REEXECUTE_TYPE                       ;
+  sc_signal<Tlsq_ptr_t         >  ** out_REEXECUTE_STORE_QUEUE_PTR_WRITE      ;
+  sc_signal<Tlsq_ptr_t         >  ** out_REEXECUTE_STORE_QUEUE_PTR_READ       ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_STORE_QUEUE_EMPTY          ;
+  sc_signal<Tlsq_ptr_t         >  ** out_REEXECUTE_LOAD_QUEUE_PTR_WRITE       ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_HAS_IMMEDIAT               ;
+  sc_signal<Tgeneral_data_t    >  ** out_REEXECUTE_IMMEDIAT                   ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_READ_RA                    ;
+  sc_signal<Tgeneral_address_t >  ** out_REEXECUTE_NUM_REG_RA                 ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_READ_RB                    ;
+  sc_signal<Tgeneral_address_t >  ** out_REEXECUTE_NUM_REG_RB                 ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_READ_RC                    ;
+  sc_signal<Tspecial_address_t >  ** out_REEXECUTE_NUM_REG_RC                 ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_WRITE_RD                   ;
+  sc_signal<Tgeneral_address_t >  ** out_REEXECUTE_NUM_REG_RD                 ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_WRITE_RE                   ;
+  sc_signal<Tspecial_address_t >  ** out_REEXECUTE_NUM_REG_RE                 ;
+
   ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_VAL                     ," in_EXECUTE_LOOP_VAL                   ",Tcontrol_t         ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]);
   ALLOC2_SC_SIGNAL(out_EXECUTE_LOOP_ACK                     ,"out_EXECUTE_LOOP_ACK                   ",Tcontrol_t         ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]);
@@ -192,4 +263,6 @@
   ALLOC1_SC_SIGNAL(out_REEXECUTE_TYPE                       ,"out_REEXECUTE_TYPE                     ",Ttype_t            ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE      ,"out_REEXECUTE_STORE_QUEUE_PTR_WRITE    ",Tlsq_ptr_t         ,_param->_nb_inst_reexecute);
+  ALLOC1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_READ       ,"out_REEXECUTE_STORE_QUEUE_PTR_READ     ",Tlsq_ptr_t         ,_param->_nb_inst_reexecute);
+  ALLOC1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_EMPTY          ,"out_REEXECUTE_STORE_QUEUE_EMPTY        ",Tcontrol_t         ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE       ,"out_REEXECUTE_LOAD_QUEUE_PTR_WRITE     ",Tlsq_ptr_t         ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL(out_REEXECUTE_HAS_IMMEDIAT               ,"out_REEXECUTE_HAS_IMMEDIAT             ",Tcontrol_t         ,_param->_nb_inst_reexecute);
@@ -284,4 +357,6 @@
   INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_TYPE                       ,_param->_nb_inst_reexecute);
   INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_STORE_QUEUE_PTR_WRITE      ,_param->_nb_inst_reexecute);
+  INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_STORE_QUEUE_PTR_READ       ,_param->_nb_inst_reexecute);
+  INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_STORE_QUEUE_EMPTY          ,_param->_nb_inst_reexecute);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_LOAD_QUEUE_PTR_WRITE       ,_param->_nb_inst_reexecute);
@@ -475,4 +550,6 @@
 		TEST(Tcontrol_t        ,out_REEXECUTE_HAS_IMMEDIAT          [i]->read(), 1);
 		TEST(Tlsq_ptr_t        ,out_REEXECUTE_STORE_QUEUE_PTR_WRITE [i]->read(), 0);
+		TEST(Tlsq_ptr_t        ,out_REEXECUTE_STORE_QUEUE_PTR_READ  [i]->read(), 0);
+		TEST(Tlsq_ptr_t        ,out_REEXECUTE_STORE_QUEUE_EMPTY     [i]->read(), 0);
 		TEST(Tlsq_ptr_t        ,out_REEXECUTE_LOAD_QUEUE_PTR_WRITE  [i]->read(), 0);
 		TEST(Tcontrol_t        ,out_REEXECUTE_READ_RA               [i]->read(), 0);
@@ -568,4 +645,6 @@
   DELETE1_SC_SIGNAL(out_REEXECUTE_TYPE                       ,_param->_nb_inst_reexecute);
   DELETE1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE      ,_param->_nb_inst_reexecute);
+  DELETE1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_READ       ,_param->_nb_inst_reexecute);
+  DELETE1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_EMPTY          ,_param->_nb_inst_reexecute);
   DELETE1_SC_SIGNAL(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE       ,_param->_nb_inst_reexecute);
   DELETE1_SC_SIGNAL(out_REEXECUTE_HAS_IMMEDIAT               ,_param->_nb_inst_reexecute);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_statistics_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_statistics_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_statistics_deallocation.cpp	(revision 128)
@@ -29,4 +29,5 @@
     delete _stat;
    
+    delete [] _stat_bank_spr_nb_elt;
     delete [] _stat_bank_gpr_nb_elt;
  
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/main.cpp	(revision 128)
@@ -67,4 +67,6 @@
       
       test (name,param);
+
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp	(revision 128)
@@ -50,4 +50,48 @@
   sc_clock              *  in_CLOCK  = new sc_clock ("clock", 1.0, 0.5);	 
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
+
+  sc_signal<Tcontrol_t        >  **  in_RENAME_VAL               ;
+  sc_signal<Tcontrol_t        >  ** out_RENAME_ACK               ;
+  sc_signal<Tcontext_t        >  **  in_RENAME_FRONT_END_ID      ;
+  sc_signal<Tcontext_t        >  **  in_RENAME_CONTEXT_ID        ;
+  sc_signal<Tgeneral_address_t>  **  in_RENAME_NUM_REG_RA_LOG    ;
+  sc_signal<Tgeneral_address_t>  **  in_RENAME_NUM_REG_RB_LOG    ;
+  sc_signal<Tspecial_address_t>  **  in_RENAME_NUM_REG_RC_LOG    ;
+  sc_signal<Tgeneral_address_t>  **  in_RENAME_NUM_REG_RD_LOG    ;
+  sc_signal<Tspecial_address_t>  **  in_RENAME_NUM_REG_RE_LOG    ;
+  sc_signal<Tgeneral_address_t>  ** out_RENAME_NUM_REG_RA_PHY    ;
+  sc_signal<Tgeneral_address_t>  ** out_RENAME_NUM_REG_RB_PHY    ;
+  sc_signal<Tspecial_address_t>  ** out_RENAME_NUM_REG_RC_PHY    ;
+  sc_signal<Tgeneral_address_t>  ** out_RENAME_NUM_REG_RD_PHY_OLD;
+  sc_signal<Tspecial_address_t>  ** out_RENAME_NUM_REG_RE_PHY_OLD;
+
+  sc_signal<Tcontrol_t        >  **  in_INSERT_VAL               ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_ACK               ;
+//sc_signal<Tcontext_t        >  **  in_INSERT_FRONT_END_ID      ;
+//sc_signal<Tcontext_t        >  **  in_INSERT_CONTEXT_ID        ;
+  sc_signal<Tcontrol_t        >  **  in_INSERT_WRITE_RD          ;
+  sc_signal<Tcontrol_t        >  **  in_INSERT_WRITE_RE          ;
+  sc_signal<Tgeneral_address_t>  **  in_INSERT_NUM_REG_RD_LOG    ;
+  sc_signal<Tspecial_address_t>  **  in_INSERT_NUM_REG_RE_LOG    ;
+  sc_signal<Tgeneral_address_t>  **  in_INSERT_NUM_REG_RD_PHY    ;
+  sc_signal<Tspecial_address_t>  **  in_INSERT_NUM_REG_RE_PHY    ;
+
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_VAL               ;
+  sc_signal<Tcontrol_t        >  ** out_RETIRE_ACK               ;
+  sc_signal<Tcontext_t        >  **  in_RETIRE_FRONT_END_ID      ;
+  sc_signal<Tcontext_t        >  **  in_RETIRE_CONTEXT_ID        ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_WRITE_RD          ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_WRITE_RE          ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RD_LOG    ;
+  sc_signal<Tspecial_address_t>  **  in_RETIRE_NUM_REG_RE_LOG    ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RD_PHY_NEW;
+  sc_signal<Tspecial_address_t>  **  in_RETIRE_NUM_REG_RE_PHY_NEW;
+  sc_signal<Tcontrol_t        >  ** out_RETIRE_RESTORE_RD_PHY_OLD;
+  sc_signal<Tcontrol_t        >  ** out_RETIRE_RESTORE_RE_PHY_OLD;
+  sc_signal<Tcontrol_t        >  ** out_RETIRE_RESTORE           ;
+
+  sc_signal<Tcontrol_t        > ***  in_RETIRE_EVENT_VAL         ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_EVENT_ACK         ;
+  sc_signal<Tevent_state_t    > ***  in_RETIRE_EVENT_STATE       ;
 
   ALLOC1_SC_SIGNAL( in_RENAME_VAL               ," in_RENAME_VAL               ",Tcontrol_t        ,_param->_nb_inst_insert);
@@ -85,6 +129,6 @@
   ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_LOG    ," in_RETIRE_NUM_REG_RD_LOG    ",Tgeneral_address_t,_param->_nb_inst_retire);
   ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_LOG    ," in_RETIRE_NUM_REG_RE_LOG    ",Tspecial_address_t,_param->_nb_inst_retire);
-  ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD," in_RETIRE_NUM_REG_RD_PHY_OLD",Tgeneral_address_t,_param->_nb_inst_retire);
-  ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD," in_RETIRE_NUM_REG_RE_PHY_OLD",Tspecial_address_t,_param->_nb_inst_retire);
+  ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW," in_RETIRE_NUM_REG_RD_PHY_NEW",Tgeneral_address_t,_param->_nb_inst_retire);
+  ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW," in_RETIRE_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_nb_inst_retire);
   ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE_RD_PHY_OLD,"out_RETIRE_RESTORE_RD_PHY_OLD",Tcontrol_t        ,_param->_nb_inst_retire);
   ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE_RE_PHY_OLD,"out_RETIRE_RESTORE_RE_PHY_OLD",Tcontrol_t        ,_param->_nb_inst_retire);
@@ -144,6 +188,6 @@
   INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RD_LOG    ,_param->_nb_inst_retire);
   INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RE_LOG    ,_param->_nb_inst_retire);
-  INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire);
-  INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire);
+  INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RD_PHY_NEW,_param->_nb_inst_retire);
+  INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire);
   INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire);
   INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire);
@@ -272,6 +316,6 @@
 	      in_RETIRE_NUM_REG_RD_LOG     [i]->write(rand() % _param->_nb_general_register_logic);
 	      in_RETIRE_NUM_REG_RE_LOG     [i]->write(rand() % _param->_nb_special_register_logic);
-	      in_RETIRE_NUM_REG_RD_PHY_OLD [i]->write(rand() % _param->_nb_general_register);
-	      in_RETIRE_NUM_REG_RE_PHY_OLD [i]->write(rand() % _param->_nb_special_register);
+	      in_RETIRE_NUM_REG_RD_PHY_NEW [i]->write(rand() % _param->_nb_general_register);
+	      in_RETIRE_NUM_REG_RE_PHY_NEW [i]->write(rand() % _param->_nb_special_register);
 
 	      in_RETIRE_EVENT_STATE        [front_end_id][context_id]->write(EVENT_STATE_NO_EVENT);
@@ -409,6 +453,6 @@
 	      in_RETIRE_NUM_REG_RD_LOG     [i]->write(rand() % _param->_nb_general_register_logic);
 	      in_RETIRE_NUM_REG_RE_LOG     [i]->write(rand() % _param->_nb_special_register_logic);
-	      in_RETIRE_NUM_REG_RD_PHY_OLD [i]->write(rand() % _param->_nb_general_register);
-	      in_RETIRE_NUM_REG_RE_PHY_OLD [i]->write(rand() % _param->_nb_special_register);
+	      in_RETIRE_NUM_REG_RD_PHY_NEW [i]->write(rand() % _param->_nb_general_register);
+	      in_RETIRE_NUM_REG_RE_PHY_NEW [i]->write(rand() % _param->_nb_special_register);
 
               in_RETIRE_EVENT_STATE [retire_front_end_id [i]][retire_context_id [i]]->write(EVENT_STATE_WAITEND);
@@ -451,5 +495,5 @@
 
 		      if (rat_gpr_updt [front_end_id][context_id][in_RETIRE_NUM_REG_RD_LOG[i]->read()] == false)
-			rat_gpr[front_end_id][context_id][in_RETIRE_NUM_REG_RD_LOG[i]->read()] = in_RETIRE_NUM_REG_RD_PHY_OLD[i]->read();
+			rat_gpr[front_end_id][context_id][in_RETIRE_NUM_REG_RD_LOG[i]->read()] = in_RETIRE_NUM_REG_RD_PHY_NEW[i]->read();
 		      rat_gpr_updt [front_end_id][context_id][in_RETIRE_NUM_REG_RD_LOG[i]->read()] = true;
 		    }
@@ -459,5 +503,5 @@
 
 		      if (rat_spr_updt [front_end_id][context_id][in_RETIRE_NUM_REG_RE_LOG[i]->read()] == false)
-			rat_spr[front_end_id][context_id][in_RETIRE_NUM_REG_RE_LOG[i]->read()] = in_RETIRE_NUM_REG_RE_PHY_OLD[i]->read();
+			rat_spr[front_end_id][context_id][in_RETIRE_NUM_REG_RE_LOG[i]->read()] = in_RETIRE_NUM_REG_RE_PHY_NEW[i]->read();
 		      rat_spr_updt [front_end_id][context_id][in_RETIRE_NUM_REG_RE_LOG[i]->read()] = true;
 		    }
@@ -498,53 +542,48 @@
   delete in_NRESET;
 
-  delete []  in_RENAME_VAL               ;
-  delete [] out_RENAME_ACK               ;
-  if (_param->_have_port_front_end_id)
-  delete []  in_RENAME_FRONT_END_ID      ;
-  if (_param->_have_port_context_id)
-  delete []  in_RENAME_CONTEXT_ID        ;
-  delete []  in_RENAME_NUM_REG_RA_LOG    ;
-  delete []  in_RENAME_NUM_REG_RB_LOG    ;
-  delete []  in_RENAME_NUM_REG_RC_LOG    ;
-  delete []  in_RENAME_NUM_REG_RD_LOG    ;
-  delete []  in_RENAME_NUM_REG_RE_LOG    ;
-  delete [] out_RENAME_NUM_REG_RA_PHY    ;
-  delete [] out_RENAME_NUM_REG_RB_PHY    ;
-  delete [] out_RENAME_NUM_REG_RC_PHY    ;
-  delete [] out_RENAME_NUM_REG_RD_PHY_OLD;
-  delete [] out_RENAME_NUM_REG_RE_PHY_OLD;
-
-  delete []  in_INSERT_VAL               ;
-  delete [] out_INSERT_ACK               ;
-//if (_param->_have_port_front_end_id)
-//delete []  in_INSERT_FRONT_END_ID      ;
-//if (_param->_have_port_context_id)
-//delete []  in_INSERT_CONTEXT_ID        ;
-  delete []  in_INSERT_WRITE_RD          ;
-  delete []  in_INSERT_WRITE_RE          ;
-  delete []  in_INSERT_NUM_REG_RD_LOG    ;
-  delete []  in_INSERT_NUM_REG_RE_LOG    ;
-  delete []  in_INSERT_NUM_REG_RD_PHY    ;
-  delete []  in_INSERT_NUM_REG_RE_PHY    ;
-
-  delete []  in_RETIRE_VAL               ;
-  delete [] out_RETIRE_ACK               ;
-  if (_param->_have_port_front_end_id)
-  delete []  in_RETIRE_FRONT_END_ID      ;
-  if (_param->_have_port_context_id)
-  delete []  in_RETIRE_CONTEXT_ID        ;
-  delete []  in_RETIRE_WRITE_RD          ;
-  delete []  in_RETIRE_WRITE_RE          ;
-  delete []  in_RETIRE_NUM_REG_RD_LOG    ;
-  delete []  in_RETIRE_NUM_REG_RE_LOG    ;
-  delete []  in_RETIRE_NUM_REG_RD_PHY_OLD;
-  delete []  in_RETIRE_NUM_REG_RE_PHY_OLD;
-  delete [] out_RETIRE_RESTORE_RD_PHY_OLD;
-  delete [] out_RETIRE_RESTORE_RE_PHY_OLD;
-  delete [] out_RETIRE_RESTORE           ;
-
-  DELETE2_SC_SIGNAL( in_RETIRE_EVENT_VAL            ,_param->_nb_front_end, _param->_nb_context[it1]);
-  DELETE2_SC_SIGNAL(out_RETIRE_EVENT_ACK            ,_param->_nb_front_end, _param->_nb_context[it1]);
-  DELETE2_SC_SIGNAL( in_RETIRE_EVENT_STATE          ,_param->_nb_front_end, _param->_nb_context[it1]);
+
+  DELETE1_SC_SIGNAL( in_RENAME_VAL               ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_RENAME_ACK               ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_FRONT_END_ID      ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_CONTEXT_ID        ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_NUM_REG_RA_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_NUM_REG_RB_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_NUM_REG_RC_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_NUM_REG_RD_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_NUM_REG_RE_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_RENAME_NUM_REG_RA_PHY    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_RENAME_NUM_REG_RB_PHY    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_RENAME_NUM_REG_RC_PHY    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_RENAME_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_RENAME_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert);
+
+  DELETE1_SC_SIGNAL( in_INSERT_VAL               ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_ACK               ,_param->_nb_inst_insert);
+//DELETE1_SC_SIGNAL( in_INSERT_FRONT_END_ID      ,_param->_nb_inst_insert);
+//DELETE1_SC_SIGNAL( in_INSERT_CONTEXT_ID        ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_WRITE_RD          ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_WRITE_RE          ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_NUM_REG_RD_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_NUM_REG_RE_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_NUM_REG_RD_PHY    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_NUM_REG_RE_PHY    ,_param->_nb_inst_insert);
+
+  DELETE1_SC_SIGNAL( in_RETIRE_VAL               ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL(out_RETIRE_ACK               ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_FRONT_END_ID      ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_CONTEXT_ID        ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_WRITE_RD          ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_WRITE_RE          ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_LOG    ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_LOG    ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL(out_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL(out_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL(out_RETIRE_RESTORE           ,_param->_nb_inst_retire);
+
+  DELETE2_SC_SIGNAL( in_RETIRE_EVENT_VAL         ,_param->_nb_front_end,_param->_nb_context[it1]);
+  DELETE2_SC_SIGNAL(out_RETIRE_EVENT_ACK         ,_param->_nb_front_end,_param->_nb_context[it1]);
+  DELETE2_SC_SIGNAL( in_RETIRE_EVENT_STATE       ,_param->_nb_front_end,_param->_nb_context[it1]);
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp	(revision 128)
@@ -36,4 +36,6 @@
 	      rat_gpr_not_speculative   [i][j][0] = 0;
               rat_gpr_speculative_valid [i][j][0] = false;
+              rat_gpr_speculative       [i][j][0] = 0    ; // not necessary
+              rat_gpr_update_table      [i][j][0] = false; // not necessary
 
 	      for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters.cpp	(revision 128)
@@ -127,9 +127,9 @@
     log_printf(FUNC,Register_translation_unit,FUNCTION,"Begin");
 
-    delete [] _param_dependency_checking_unit;
-    delete [] _param_free_list_unit;
-    delete [] _param_register_address_translation_unit;
-    delete [] _param_stat_list_unit;    
-    delete [] _param_register_translation_unit_glue;
+    delete _param_dependency_checking_unit;
+    delete _param_free_list_unit;
+    delete _param_register_address_translation_unit;
+    delete _param_stat_list_unit;    
+    delete _param_register_translation_unit_glue;
 
     log_printf(FUNC,Register_translation_unit,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp	(revision 128)
@@ -135,4 +135,6 @@
       
       test (name,param);
+      
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp	(revision 128)
@@ -48,4 +48,97 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_VAL               ;
+  sc_signal<Tcontrol_t        > *** out_RENAME_IN_ACK               ;
+  sc_signal<Tcontext_t        > ***  in_RENAME_IN_FRONT_END_ID      ;
+  sc_signal<Tcontext_t        > ***  in_RENAME_IN_CONTEXT_ID        ;
+  sc_signal<Tdepth_t          > ***  in_RENAME_IN_DEPTH             ;
+  sc_signal<Ttype_t           > ***  in_RENAME_IN_TYPE              ;
+  sc_signal<Toperation_t      > ***  in_RENAME_IN_OPERATION         ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_NO_EXECUTE        ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_LAST_EVENT        ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_IS_DELAY_SLOT     ;
+  sc_signal<Tgeneral_data_t   > ***  in_RENAME_IN_ADDRESS           ;
+  sc_signal<Tgeneral_data_t   > ***  in_RENAME_IN_ADDRESS_NEXT      ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_HAS_IMMEDIAT      ;
+  sc_signal<Tgeneral_data_t   > ***  in_RENAME_IN_IMMEDIAT          ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_READ_RA           ;
+  sc_signal<Tgeneral_address_t> ***  in_RENAME_IN_NUM_REG_RA        ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_READ_RB           ;
+  sc_signal<Tgeneral_address_t> ***  in_RENAME_IN_NUM_REG_RB        ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_READ_RC           ;
+  sc_signal<Tspecial_address_t> ***  in_RENAME_IN_NUM_REG_RC        ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_WRITE_RD          ;
+  sc_signal<Tgeneral_address_t> ***  in_RENAME_IN_NUM_REG_RD        ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_WRITE_RE          ;
+  sc_signal<Tspecial_address_t> ***  in_RENAME_IN_NUM_REG_RE        ;
+  sc_signal<Texception_t      > ***  in_RENAME_IN_EXCEPTION_USE     ;
+  sc_signal<Texception_t      > ***  in_RENAME_IN_EXCEPTION         ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_VAL                  ;
+  sc_signal<Tcontrol_t        >  **  in_INSERT_ACK                  ;
+  sc_signal<Tcontext_t        >  ** out_INSERT_FRONT_END_ID         ;
+  sc_signal<Tcontext_t        >  ** out_INSERT_CONTEXT_ID           ;
+  sc_signal<Tdepth_t          >  ** out_INSERT_DEPTH                ;
+  sc_signal<Ttype_t           >  ** out_INSERT_TYPE                 ;
+  sc_signal<Toperation_t      >  ** out_INSERT_OPERATION            ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_NO_EXECUTE           ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_LAST_EVENT           ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_IS_DELAY_SLOT        ;
+  sc_signal<Tgeneral_data_t   >  ** out_INSERT_ADDRESS              ;
+  sc_signal<Tgeneral_data_t   >  ** out_INSERT_ADDRESS_NEXT         ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_HAS_IMMEDIAT         ;
+  sc_signal<Tgeneral_data_t   >  ** out_INSERT_IMMEDIAT             ;
+  sc_signal<Tlsq_ptr_t        >  ** out_INSERT_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t        >  ** out_INSERT_STORE_QUEUE_PTR_READ ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_STORE_QUEUE_EMPTY    ;
+  sc_signal<Tlsq_ptr_t        >  ** out_INSERT_LOAD_QUEUE_PTR_WRITE ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_READ_RA              ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RA_LOG       ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RA_PHY       ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_READ_RB              ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RB_LOG       ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RB_PHY       ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_READ_RC              ;
+  sc_signal<Tspecial_address_t>  ** out_INSERT_NUM_REG_RC_LOG       ;
+  sc_signal<Tspecial_address_t>  ** out_INSERT_NUM_REG_RC_PHY       ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_WRITE_RD             ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RD_LOG       ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RD_PHY_OLD   ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RD_PHY_NEW   ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_WRITE_RE             ;
+  sc_signal<Tspecial_address_t>  ** out_INSERT_NUM_REG_RE_LOG       ;
+  sc_signal<Tspecial_address_t>  ** out_INSERT_NUM_REG_RE_PHY_OLD   ;
+  sc_signal<Tspecial_address_t>  ** out_INSERT_NUM_REG_RE_PHY_NEW   ;
+  sc_signal<Texception_t      >  ** out_INSERT_EXCEPTION_USE        ;
+  sc_signal<Texception_t      >  ** out_INSERT_EXCEPTION            ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_VAL                  ;
+  sc_signal<Tcontrol_t        >  ** out_RETIRE_ACK                  ;
+  sc_signal<Tcontext_t        >  **  in_RETIRE_FRONT_END_ID         ;
+  sc_signal<Tcontext_t        >  **  in_RETIRE_CONTEXT_ID           ;
+//sc_signal<Ttype_t           >  **  in_RETIRE_TYPE                 ;
+//sc_signal<Toperation_t      >  **  in_RETIRE_OPERATION            ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_USE_STORE_QUEUE      ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_USE_LOAD_QUEUE       ;
+  sc_signal<Tlsq_ptr_t        >  **  in_RETIRE_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t        >  **  in_RETIRE_LOAD_QUEUE_PTR_WRITE ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_READ_RA              ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RA_PHY       ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_READ_RB              ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RB_PHY       ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_READ_RC              ;
+  sc_signal<Tspecial_address_t>  **  in_RETIRE_NUM_REG_RC_PHY       ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_WRITE_RD             ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RD_LOG       ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RD_PHY_OLD   ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RD_PHY_NEW   ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_WRITE_RE             ;
+  sc_signal<Tspecial_address_t>  **  in_RETIRE_NUM_REG_RE_LOG       ;
+  sc_signal<Tspecial_address_t>  **  in_RETIRE_NUM_REG_RE_PHY_OLD   ;
+  sc_signal<Tspecial_address_t>  **  in_RETIRE_NUM_REG_RE_PHY_NEW   ;
+  sc_signal<Tcontrol_t        > ***  in_RETIRE_EVENT_VAL            ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_EVENT_ACK            ;
+  sc_signal<Tevent_state_t    > ***  in_RETIRE_EVENT_STATE          ;
+  sc_signal<Tspr_t            > ***  in_SPR_READ_SR                 ;
+  sc_signal<bool              >   *  in_INFO_ROB_EMPTY              ;
+
   ALLOC2_SC_SIGNAL( in_RENAME_IN_VAL               ," in_RENAME_IN_VAL               ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
   ALLOC2_SC_SIGNAL(out_RENAME_IN_ACK               ,"out_RENAME_IN_ACK               ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
@@ -56,8 +149,7 @@
   ALLOC2_SC_SIGNAL( in_RENAME_IN_OPERATION         ," in_RENAME_IN_OPERATION         ",Toperation_t      ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
   ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE        ," in_RENAME_IN_NO_EXECUTE        ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
+  ALLOC2_SC_SIGNAL( in_RENAME_IN_LAST_EVENT        ," in_RENAME_IN_LAST_EVENT        ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
   ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT     ," in_RENAME_IN_IS_DELAY_SLOT     ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
-#ifdef DEBUG
   ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS           ," in_RENAME_IN_ADDRESS           ",Tgeneral_data_t   ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
-#endif
   ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT      ," in_RENAME_IN_ADDRESS_NEXT      ",Tgeneral_data_t   ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
   ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT      ," in_RENAME_IN_HAS_IMMEDIAT      ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
@@ -83,12 +175,13 @@
   ALLOC1_SC_SIGNAL(out_INSERT_OPERATION            ,"out_INSERT_OPERATION            ",Toperation_t      ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_NO_EXECUTE           ,"out_INSERT_NO_EXECUTE           ",Tcontrol_t        ,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL(out_INSERT_LAST_EVENT           ,"out_INSERT_LAST_EVENT           ",Tcontrol_t        ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT        ,"out_INSERT_IS_DELAY_SLOT        ",Tcontrol_t        ,_param->_nb_inst_insert);
-#ifdef DEBUG
   ALLOC1_SC_SIGNAL(out_INSERT_ADDRESS              ,"out_INSERT_ADDRESS              ",Tgeneral_data_t   ,_param->_nb_inst_insert);
-#endif
   ALLOC1_SC_SIGNAL(out_INSERT_ADDRESS_NEXT         ,"out_INSERT_ADDRESS_NEXT         ",Tgeneral_data_t   ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT         ,"out_INSERT_HAS_IMMEDIAT         ",Tcontrol_t        ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_IMMEDIAT             ,"out_INSERT_IMMEDIAT             ",Tgeneral_data_t   ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_STORE_QUEUE_PTR_WRITE,"out_INSERT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t        ,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL(out_INSERT_STORE_QUEUE_PTR_READ ,"out_INSERT_STORE_QUEUE_PTR_READ ",Tlsq_ptr_t        ,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL(out_INSERT_STORE_QUEUE_EMPTY    ,"out_INSERT_STORE_QUEUE_EMPTY    ",Tcontrol_t        ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_LOAD_QUEUE_PTR_WRITE ,"out_INSERT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t        ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_READ_RA              ,"out_INSERT_READ_RA              ",Tcontrol_t        ,_param->_nb_inst_insert);
@@ -139,4 +232,5 @@
   ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_STATE          ," in_RETIRE_EVENT_STATE          ",Tevent_state_t    ,_param->_nb_front_end,_param->_nb_context[it1]);
   ALLOC2_SC_SIGNAL( in_SPR_READ_SR                 ," in_SPR_READ_SR                 ",Tspr_t            ,_param->_nb_front_end,_param->_nb_context[it1]);
+  ALLOC0_SC_SIGNAL( in_INFO_ROB_EMPTY              ," in_INFO_ROB_EMPTY              ",bool              );
   
   /********************************************************
@@ -160,4 +254,5 @@
   INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_OPERATION         ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
   INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_NO_EXECUTE        ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
+  INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_LAST_EVENT        ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
   INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_IS_DELAY_SLOT     ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
 #ifdef DEBUG
@@ -191,4 +286,5 @@
   INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_OPERATION            ,_param->_nb_inst_insert);
   INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NO_EXECUTE           ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_LAST_EVENT           ,_param->_nb_inst_insert);
   INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_IS_DELAY_SLOT        ,_param->_nb_inst_insert);
 #ifdef DEBUG
@@ -199,4 +295,6 @@
   INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_IMMEDIAT             ,_param->_nb_inst_insert);
   INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_STORE_QUEUE_PTR_READ ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_STORE_QUEUE_EMPTY    ,_param->_nb_inst_insert);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_insert);
@@ -261,4 +359,7 @@
   INSTANCE2_SC_SIGNAL(_Rename_unit,in_SPR_READ_SR                  ,_param->_nb_front_end, _param->_nb_context[it1]);
 
+#ifdef DEBUG_TEST
+  INSTANCE0_SC_SIGNAL(_Rename_unit,in_INFO_ROB_EMPTY               );
+#endif
 
   msg(_("<%s> : Start Simulation ............\n"),name.c_str());
@@ -314,8 +415,7 @@
   DELETE2_SC_SIGNAL( in_RENAME_IN_OPERATION         ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
   DELETE2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE        ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
+  DELETE2_SC_SIGNAL( in_RENAME_IN_LAST_EVENT        ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
   DELETE2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT     ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
-#ifdef DEBUG
   DELETE2_SC_SIGNAL( in_RENAME_IN_ADDRESS           ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
-#endif
   DELETE2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT      ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
   DELETE2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT      ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
@@ -342,12 +442,13 @@
   DELETE1_SC_SIGNAL(out_INSERT_OPERATION            ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_NO_EXECUTE           ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_LAST_EVENT           ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT        ,_param->_nb_inst_insert);
-#ifdef DEBUG
   DELETE1_SC_SIGNAL(out_INSERT_ADDRESS              ,_param->_nb_inst_insert);
-#endif
   DELETE1_SC_SIGNAL(out_INSERT_ADDRESS_NEXT         ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT         ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_IMMEDIAT             ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_STORE_QUEUE_PTR_READ ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_STORE_QUEUE_EMPTY    ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_EXCEPTION_USE        ,_param->_nb_inst_insert);
@@ -401,4 +502,6 @@
 
   DELETE2_SC_SIGNAL(in_SPR_READ_SR                  ,_param->_nb_front_end, _param->_nb_context[it1]);
+
+  DELETE0_SC_SIGNAL(in_INFO_ROB_EMPTY               );
     }
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp	(revision 128)
@@ -20,5 +20,5 @@
 #endif
 
-  simulation_init(0,0);
+  simulation_init(0,0,0,false,false);
 
   debug_idle_cycle = CYCLE_MAX;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/test.cpp	(revision 128)
@@ -47,4 +47,34 @@
   sc_clock              *  in_CLOCK  = new sc_clock ("clock", 1.0, 0.5);	 
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
+
+  sc_signal<Tcontrol_t    >   **  in_SPR_ACCESS_VAL         ;
+  sc_signal<Tcontrol_t    >   ** out_SPR_ACCESS_ACK         ;
+  sc_signal<Tcontext_t    >   **  in_SPR_ACCESS_FRONT_END_ID;
+  sc_signal<Tcontext_t    >   **  in_SPR_ACCESS_CONTEXT_ID  ;
+  sc_signal<Tcontrol_t    >   **  in_SPR_ACCESS_WEN         ;
+  sc_signal<Tspr_address_t>   **  in_SPR_ACCESS_NUM_GROUP   ;
+  sc_signal<Tspr_address_t>   **  in_SPR_ACCESS_NUM_REG     ;
+  sc_signal<Tspr_t        >   **  in_SPR_ACCESS_WDATA       ;
+  sc_signal<Tspr_t        >   ** out_SPR_ACCESS_RDATA       ;
+  sc_signal<Tcontrol_t    >   ** out_SPR_ACCESS_INVALID     ;
+
+  sc_signal<Tspr_t        >  *** out_SPR_READ_SR            ;
+
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_VAL         ;
+  sc_signal<Tcontrol_t    >  *** out_SPR_COMMIT_ACK         ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_SR_F_VAL    ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_SR_F        ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_SR_CY_VAL   ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_SR_CY       ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_SR_OV_VAL   ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_SR_OV       ;
+
+  sc_signal<Tcontrol_t    >  ***  in_SPR_EVENT_VAL          ;
+  sc_signal<Tcontrol_t    >  *** out_SPR_EVENT_ACK          ;
+  sc_signal<Tspr_t        >  ***  in_SPR_EVENT_EPCR         ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_EVENT_EEAR_WEN     ;
+  sc_signal<Tspr_t        >  ***  in_SPR_EVENT_EEAR         ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_EVENT_SR_DSX       ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_EVENT_SR_TO_ESR    ;
 
   ALLOC1_SC_SIGNAL( in_SPR_ACCESS_VAL         ," in_SPR_ACCESS_VAL         ",Tcontrol_t    ,_param->_nb_inst_reexecute);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h	(revision 128)
@@ -578,4 +578,5 @@
   public : void   reset (void  ) 
     {
+      thread_id = 0; // not necessary
     };
   public : Tspr_t read  (void  )
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp	(revision 128)
@@ -158,4 +158,6 @@
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+    for (uint32_t i=0; i<_param->_nb_rename_unit; ++i)
+    delete    _component_rename_unit [i]       ;
     delete [] _component_rename_unit           ;
     delete    _component_commit_unit           ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp	(revision 128)
@@ -411,4 +411,6 @@
     delete [] _link_front_end_with_rename_unit             ;
 
+    for (uint32_t i=0; i<_nb_rename_unit; i++)
+    delete    _param_rename_unit [i]      ;
     delete [] _param_rename_unit          ;
     delete    _param_commit_unit          ;
