Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-1_front_end-1_ooo_engine-1_execute_loop.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-1_front_end-1_ooo_engine-1_execute_loop.cfg	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-1_front_end-1_ooo_engine-1_execute_loop.cfg	(revision 128)
@@ -11,4 +11,5 @@
 4	4	+1	# ooo_engine_nb_inst_branch_complete    [0]          [nb_ooo_engine]
 4	4	+1	# nb_inst_insert                        [0]          [nb_ooo_engine]  
+4	4	+1	# nb_inst_reexecute                     [0]          [nb_ooo_engine]  
 4	4	+1	# nb_inst_issue                         [0]          [nb_ooo_engine]  
 4	4	+1	# nb_inst_execute                       [0]          [nb_ooo_engine]  
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-1_ooo_engine-1_execute_loop.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-1_ooo_engine-1_execute_loop.cfg	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-1_ooo_engine-1_execute_loop.cfg	(revision 128)
@@ -20,4 +20,5 @@
 4	4	+1	# ooo_engine_nb_inst_branch_complete    [0]          [nb_ooo_engine]
 3	3	+1	# nb_inst_insert                        [0]          [nb_ooo_engine]  
+3	3	+1	# nb_inst_reexecute                     [0]          [nb_ooo_engine]  
 3	3	+1	# nb_inst_issue                         [0]          [nb_ooo_engine]  
 4	4	+1	# nb_inst_execute                       [0]          [nb_ooo_engine]  
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-1_execute_loop.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-1_execute_loop.cfg	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-1_execute_loop.cfg	(revision 128)
@@ -28,4 +28,7 @@
 1	1	+1	# nb_inst_insert                        [1]          [nb_ooo_engine]  
 2	2	+1	# nb_inst_insert                        [2]          [nb_ooo_engine]  
+3	3	+1	# nb_inst_reexecute                     [0]          [nb_ooo_engine]  
+1	1	+1	# nb_inst_reexecute                     [1]          [nb_ooo_engine]  
+2	2	+1	# nb_inst_reexecute                     [2]          [nb_ooo_engine]  
 3	3	+1	# nb_inst_issue                         [0]          [nb_ooo_engine]  
 1	1	+1	# nb_inst_issue                         [1]          [nb_ooo_engine]  
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-2_execute_loop.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-2_execute_loop.cfg	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-2_execute_loop.cfg	(revision 128)
@@ -29,4 +29,7 @@
 1	1	+1	# nb_inst_insert                        [1]          [nb_ooo_engine]  
 2	2	+1	# nb_inst_insert                        [2]          [nb_ooo_engine]  
+3	3	+1	# nb_inst_reexecute                     [0]          [nb_ooo_engine]  
+1	1	+1	# nb_inst_reexecute                     [1]          [nb_ooo_engine]  
+2	2	+1	# nb_inst_reexecute                     [2]          [nb_ooo_engine]  
 3	3	+1	# nb_inst_issue                         [0]          [nb_ooo_engine]  
 1	1	+1	# nb_inst_issue                         [1]          [nb_ooo_engine]  
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-min.cfg	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-min.cfg	(revision 128)
@@ -11,4 +11,5 @@
 1	1	+1	# ooo_engine_nb_inst_branch_complete    [0]                  [nb_ooo_engine]
 1	1	+1	# nb_inst_insert                        [0]                  [nb_ooo_engine]  
+1	1	+1	# nb_inst_reexecute                     [0]                  [nb_ooo_engine]  
 1	1	+1	# nb_inst_issue                         [0]                  [nb_ooo_engine]  
 1	1	+1	# nb_inst_execute                       [0][0]               [nb_ooo_engine][ooo_engine_nb_execute_loop]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/main.cpp	(revision 128)
@@ -25,7 +25,9 @@
   err (_(" * ooo_engine_nb_inst_branch_complete    [nb_ooo_engine]                                            (uint32_t         )\n"));
   err (_(" * nb_inst_insert                        [nb_ooo_engine]                                            (uint32_t         )\n"));
+  err (_(" * nb_inst_reexecute                     [nb_ooo_engine]                                            (uint32_t         )\n"));
 //err (_(" * nb_inst_issue_queue                   [nb_ooo_engine]                                            (uint32_t         )\n"));
   err (_(" * nb_inst_issue_slot                    [nb_ooo_engine]                                            (uint32_t         )\n"));
   err (_(" * nb_inst_execute                       [nb_ooo_engine][ooo_engine_nb_execute_loop]                (uint32_t         )\n"));
+//err (_(" * issue_queue_in_order                  [nb_ooo_engine]                                            (bool             )\n"));
   err (_(" * nb_read_unit                          [nb_execute_loop]                                          (uint32_t         )\n"));
   err (_(" * nb_write_unit                         [nb_execute_loop]                                          (uint32_t         )\n"));
@@ -86,6 +88,8 @@
   uint32_t              * ooo_engine_nb_inst_branch_complete   ;//[nb_ooo_engine]
   uint32_t              * nb_inst_insert                       ;//[nb_ooo_engine]
+  uint32_t              * nb_inst_reexecute                    ;//[nb_ooo_engine]
   uint32_t              * nb_inst_issue_slot                   ;//[nb_ooo_engine]
   uint32_t             ** nb_inst_execute                      ;//[nb_ooo_engine][ooo_engine_nb_execute_loop]
+  bool                  * issue_queue_in_order                 ;//[nb_ooo_engine]
   uint32_t              * nb_read_unit                         ;//[nb_execute_loop]
   uint32_t              * nb_write_unit                        ;//[nb_execute_loop]
@@ -121,5 +125,5 @@
   nb_params = static_cast<int> (2+NB_PARAMS+
                                 3*nb_front_end+
-                                5*nb_ooo_engine+
+                                6*nb_ooo_engine+
                                 3*nb_execute_loop
                                 );
@@ -134,4 +138,5 @@
   SELFTEST1(ooo_engine_nb_inst_branch_complete   ,uint32_t         ,argv,x,nb_ooo_engine);
   SELFTEST1(nb_inst_insert                       ,uint32_t         ,argv,x,nb_ooo_engine);
+  SELFTEST1(nb_inst_reexecute                    ,uint32_t         ,argv,x,nb_ooo_engine);
   SELFTEST1(nb_inst_issue_slot                   ,uint32_t         ,argv,x,nb_ooo_engine);
 
@@ -149,5 +154,5 @@
   nb_params = static_cast<int> (2+NB_PARAMS+
                                 3*nb_front_end+
-                                5*nb_ooo_engine+
+                                6*nb_ooo_engine+
                                 3*nb_execute_loop+
                                 1*sum_ooo_engine_nb_execute_loop
@@ -157,4 +162,9 @@
 
   SELFTEST2(nb_inst_execute                      ,uint32_t         ,argv,x,nb_ooo_engine,ooo_engine_nb_execute_loop[it1]);
+
+  ALLOC1   (issue_queue_in_order                 ,bool                    ,nb_ooo_engine);
+  for (uint32_t i=0; i<nb_ooo_engine; ++i)
+    issue_queue_in_order [i] = true;
+
   SELFTEST1(nb_read_unit                         ,uint32_t         ,argv,x,nb_execute_loop);
   SELFTEST1(nb_write_unit                        ,uint32_t         ,argv,x,nb_execute_loop);
@@ -179,5 +189,5 @@
   nb_params = static_cast<int> (2+NB_PARAMS+
                                 3*nb_front_end+
-                                5*nb_ooo_engine+
+                                6*nb_ooo_engine+
                                 3*nb_execute_loop+
                                 sum_nb_inst_issue*sum_nb_read_unit+
@@ -239,7 +249,9 @@
          ooo_engine_nb_inst_branch_complete   ,//[nb_ooo_engine]
          nb_inst_insert                       ,//[nb_ooo_engine]
+         nb_inst_reexecute                    ,//[nb_ooo_engine]
          nb_inst_issue_slot                   ,//[nb_ooo_engine]
          nb_inst_issue_slot                   ,//[nb_ooo_engine]
          nb_inst_execute                      ,//[nb_ooo_engine][ooo_engine_nb_execute_loop]
+         issue_queue_in_order                 ,//[nb_ooo_engine]
          nb_read_unit                         ,//[nb_execute_loop]
          nb_write_unit                        ,//[nb_execute_loop]
@@ -265,4 +277,6 @@
       
       test (name,param);
+
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
@@ -285,13 +299,19 @@
     }
 
-  DELETE2(translate_execute_loop_num_ooo_engine,nb_execute_loop,execute_loop_nb_ooo_engine[it1]);
-  DELETE2(translate_ooo_engine_num_execute_loop,nb_ooo_engine,ooo_engine_nb_execute_loop[it1]);
-  DELETE2(translate_ooo_engine_num_front_end   ,nb_ooo_engine,ooo_engine_nb_front_end[it1]);
-  DELETE3(table_issue_type                                                           ,nb_execute_loop,nb_read_unit[it1],MAX_TYPE);
-  DELETE4(table_dispatch                       ,nb_ooo_engine,nb_inst_issue_slot[it1],nb_execute_loop,nb_read_unit[it2]);
+//DELETE0(size_special_register                );
+//DELETE0(size_general_register                );
+//DELETE0(size_special_data                    );
+//DELETE0(size_general_data                    );
+//DELETE0(size_store_queue_ptr                 );
+//DELETE0(size_load_queue_ptr                  );
+//DELETE0(size_rob_ptr                         );
+//DELETE0(size_depth                           );
   DELETE1(nb_write_unit                        ,nb_execute_loop);
   DELETE1(nb_read_unit                         ,nb_execute_loop);
+  DELETE1(issue_queue_in_order                 ,nb_ooo_engine);
   DELETE2(nb_inst_execute                      ,nb_ooo_engine,ooo_engine_nb_execute_loop[it1]);
   DELETE1(nb_inst_issue_slot                   ,nb_ooo_engine);
+  DELETE1(nb_inst_reexecute                    ,nb_ooo_engine);
+  DELETE1(nb_inst_insert                       ,nb_ooo_engine);
   DELETE1(ooo_engine_nb_inst_branch_complete   ,nb_ooo_engine);
   DELETE1(front_end_nb_inst_branch_complete    ,nb_front_end);
@@ -300,5 +320,8 @@
   DELETE1(ooo_engine_nb_execute_loop           ,nb_ooo_engine);
   DELETE1(ooo_engine_nb_front_end              ,nb_ooo_engine);
+//DELETE0(nb_execute_loop                      );
+//DELETE0(nb_ooo_engine                        );
   DELETE1(nb_context                           ,nb_front_end);
+//DELETE0(nb_front_end                         );
 
   return (_return);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp	(revision 128)
@@ -19,4 +19,6 @@
   morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
 #endif
+
+  _model.set_model(NAME_Core_Glue,MODEL_SYSTEMC,true);
 
   Tusage_t _usage = USE_ALL;
@@ -50,4 +52,5 @@
 
   sc_signal<Tcontext_t        >  *** out_RENAME_FRONT_END_ID                       ;
+
   sc_signal<Tcontrol_t        >  *** out_BRANCH_COMPLETE_FRONT_END_VAL             ;
   sc_signal<Tcontrol_t        >  ***  in_BRANCH_COMPLETE_FRONT_END_ACK             ;
@@ -57,4 +60,5 @@
   sc_signal<Tcontrol_t        >  *** out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE     ;
   sc_signal<Tcontrol_t        >  ***  in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ;
+
   sc_signal<Tcontrol_t        >  ***  in_BRANCH_COMPLETE_OOO_ENGINE_VAL            ;
   sc_signal<Tcontrol_t        >  *** out_BRANCH_COMPLETE_OOO_ENGINE_ACK            ;
@@ -65,4 +69,5 @@
   sc_signal<Tcontrol_t        >  ***  in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE    ;
   sc_signal<Tcontrol_t        >  *** out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION;
+
   sc_signal<Tcontrol_t        >   ** out_COMMIT_EVENT_FRONT_END_VAL                ;
   sc_signal<Tcontrol_t        >   **  in_COMMIT_EVENT_FRONT_END_ACK                ;
@@ -76,4 +81,5 @@
   sc_signal<Tcontrol_t        >   ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL   ;
   sc_signal<Tgeneral_data_t   >   ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR       ;
+
   sc_signal<Tcontrol_t        >   **  in_COMMIT_EVENT_OOO_ENGINE_VAL               ;
   sc_signal<Tcontrol_t        >   ** out_COMMIT_EVENT_OOO_ENGINE_ACK               ;
@@ -88,4 +94,5 @@
   sc_signal<Tcontrol_t        >   **  in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL  ;
   sc_signal<Tgeneral_data_t   >   **  in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR      ;
+
   sc_signal<Tcontrol_t        >  ***  in_ISSUE_OOO_ENGINE_VAL                      ;
   sc_signal<Tcontrol_t        >  *** out_ISSUE_OOO_ENGINE_ACK                      ;
@@ -96,4 +103,6 @@
   sc_signal<Toperation_t      >  ***  in_ISSUE_OOO_ENGINE_OPERATION                ;
   sc_signal<Tlsq_ptr_t        >  ***  in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE    ;
+  sc_signal<Tlsq_ptr_t        >  ***  in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ     ;
+  sc_signal<Tcontrol_t        >  ***  in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY        ;
   sc_signal<Tlsq_ptr_t        >  ***  in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE     ;
   sc_signal<Tcontrol_t        >  ***  in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT             ;
@@ -109,4 +118,5 @@
   sc_signal<Tcontrol_t        >  ***  in_ISSUE_OOO_ENGINE_WRITE_RE                 ;
   sc_signal<Tspecial_address_t>  ***  in_ISSUE_OOO_ENGINE_NUM_REG_RE               ;
+
   sc_signal<Tcontrol_t        >  *** out_ISSUE_EXECUTE_LOOP_VAL                    ;
   sc_signal<Tcontrol_t        >  ***  in_ISSUE_EXECUTE_LOOP_ACK                    ;
@@ -118,4 +128,6 @@
   sc_signal<Ttype_t           >  *** out_ISSUE_EXECUTE_LOOP_TYPE                   ;
   sc_signal<Tlsq_ptr_t        >  *** out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE  ;
+  sc_signal<Tlsq_ptr_t        >  *** out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_READ   ;
+  sc_signal<Tcontrol_t        >  *** out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_EMPTY      ;
   sc_signal<Tlsq_ptr_t        >  *** out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE   ;
   sc_signal<Tcontrol_t        >  *** out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT           ;
@@ -131,4 +143,5 @@
   sc_signal<Tcontrol_t        >  *** out_ISSUE_EXECUTE_LOOP_WRITE_RE               ;
   sc_signal<Tspecial_address_t>  *** out_ISSUE_EXECUTE_LOOP_NUM_REG_RE             ;
+
   sc_signal<Tcontrol_t        > **** out_EXECUTE_OOO_ENGINE_VAL                    ;
   sc_signal<Tcontrol_t        > ****  in_EXECUTE_OOO_ENGINE_ACK                    ;
@@ -143,4 +156,5 @@
   sc_signal<Taddress_t        > **** out_EXECUTE_OOO_ENGINE_ADDRESS                ;
   sc_signal<Tgeneral_data_t   > **** out_EXECUTE_OOO_ENGINE_DATA                   ;
+
   sc_signal<Tcontrol_t        >  ***  in_EXECUTE_EXECUTE_LOOP_VAL                  ;
   sc_signal<Tcontrol_t        >  *** out_EXECUTE_EXECUTE_LOOP_ACK                  ;
@@ -156,4 +170,5 @@
   sc_signal<Taddress_t        >  ***  in_EXECUTE_EXECUTE_LOOP_ADDRESS              ;
   sc_signal<Tgeneral_data_t   >  ***  in_EXECUTE_EXECUTE_LOOP_DATA                 ;
+
   sc_signal<Tcontrol_t        >  ***  in_INSERT_OOO_ENGINE_VAL                     ;
   sc_signal<Tcontrol_t        >  *** out_INSERT_OOO_ENGINE_ACK                     ;
@@ -216,4 +231,6 @@
   ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_OPERATION                ," in_ISSUE_OOO_ENGINE_OPERATION                ",Toperation_t      ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
   ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE    ," in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE    ",Tlsq_ptr_t        ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
+  ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ     ," in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ     ",Tlsq_ptr_t        ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
+  ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY        ," in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY        ",Tcontrol_t        ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
   ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE     ," in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE     ",Tlsq_ptr_t        ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
   ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT             ," in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT             ",Tcontrol_t        ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
@@ -238,4 +255,6 @@
   ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_TYPE                   ,"out_ISSUE_EXECUTE_LOOP_TYPE                   ",Ttype_t           ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
   ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE  ,"out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE  ",Tlsq_ptr_t        ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
+  ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_READ   ,"out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_READ   ",Tlsq_ptr_t        ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
+  ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_EMPTY      ,"out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_EMPTY      ",Tcontrol_t        ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
   ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE   ,"out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE   ",Tlsq_ptr_t        ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
   ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT           ,"out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT           ",Tcontrol_t        ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
@@ -358,5 +377,7 @@
   INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_TYPE                     ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
   INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_OPERATION                ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
-  INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE    ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 
+  INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE    ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
+  INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ     ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
+  INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY        ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE     ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
@@ -386,4 +407,6 @@
   INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_TYPE                   ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
   INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE  ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
+  INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_READ   ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
+  INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_EMPTY      ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE   ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
@@ -469,4 +492,5 @@
   in_NRESET->write(1);  
 
+#ifdef SELFTEST
   LABEL("Test RENAME_FRONT_END_ID");
   if (_param->_have_port_front_end_id)
@@ -612,4 +636,6 @@
             in_ISSUE_OOO_ENGINE_OPERATION             [i][j]->write(range<Ttype_t        >(rand(),_param->_size_type               ));
             in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE [i][j]->write(range<Tlsq_ptr_t     >(rand(),_param->_size_store_queue_ptr    ));
+            in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ  [i][j]->write(range<Tlsq_ptr_t     >(rand(),_param->_size_store_queue_ptr    ));
+            in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY     [i][j]->write(rand()%2);
             in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE  [i][j]->write(range<Tlsq_ptr_t     >(rand(),_param->_size_load_queue_ptr     ));
             in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT          [i][j]->write(rand()%2);
@@ -751,4 +777,8 @@
               TEST(Tlsq_ptr_t        ,out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE  [i][j]->read(), 
                                        in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE    [x][y]->read());
+              TEST(Tlsq_ptr_t        ,out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_READ   [i][j]->read(), 
+                                       in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ     [x][y]->read());
+              TEST(Tlsq_ptr_t        ,out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_EMPTY      [i][j]->read(), 
+                                       in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY        [x][y]->read());
               TEST(Tlsq_ptr_t        ,out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE   [i][j]->read(), 
                                        in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE     [x][y]->read());
@@ -781,4 +811,7 @@
       SC_START(1);
     }
+#else
+  SC_START(5);
+#endif
 
   /********************************************************
@@ -841,4 +874,6 @@
   DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_OPERATION                ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
   DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE    ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
+  DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ     ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
+  DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY        ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
   DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE     ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
   DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT             ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]);
@@ -863,4 +898,6 @@
   DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_TYPE                   ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
   DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE  ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
+  DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_READ   ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
+  DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_EMPTY      ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
   DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE   ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
   DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT           ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp	(revision 128)
@@ -10,10 +10,8 @@
 #include "Common/include/Max.h"
 
-namespace morpheo                    {
+namespace morpheo {
 namespace behavioural {
 namespace core {
 namespace core_glue {
-
-
 
 #undef  FUNCTION
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/src/main.cpp	(revision 128)
@@ -15,4 +15,5 @@
   err (_("<Usage> %s name_instance list_params.\n"),argv[0]);
   err (_("list_params is :\n"));
+//err (_(" * nb_thread                                                                 (uint32_t         )\n"));
   err (_(" * nb_execute_loop                                                           (uint32_t         )\n"));
   err (_(" * nb_load_store_unit [nb_execute_loop]                                      (uint32_t         )\n"));
@@ -158,4 +159,6 @@
       
       test (name,param);
+
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/src/test.cpp	(revision 128)
@@ -54,4 +54,34 @@
   sc_clock              *  in_CLOCK  = new sc_clock ("clock", 1.0, 0.5);	 
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
+
+  sc_signal<Tcontrol_t        >   ** out_DCACHE_REQ_VAL         ;
+  sc_signal<Tcontrol_t        >   **  in_DCACHE_REQ_ACK         ;
+  sc_signal<Tcontext_t        >   ** out_DCACHE_REQ_THREAD_ID   ;
+  sc_signal<Tpacket_t         >   ** out_DCACHE_REQ_PACKET_ID   ;
+  sc_signal<Tdcache_address_t >   ** out_DCACHE_REQ_ADDRESS     ;
+  sc_signal<Tdcache_data_t    >   ** out_DCACHE_REQ_WDATA       ;
+  sc_signal<Tdcache_type_t    >   ** out_DCACHE_REQ_TYPE        ;
+
+  sc_signal<Tcontrol_t        >   **  in_DCACHE_RSP_VAL         ;
+  sc_signal<Tcontrol_t        >   ** out_DCACHE_RSP_ACK         ;
+  sc_signal<Tcontext_t        >   **  in_DCACHE_RSP_THREAD_ID   ;
+  sc_signal<Tpacket_t         >   **  in_DCACHE_RSP_PACKET_ID   ;
+  sc_signal<Tdcache_data_t    >   **  in_DCACHE_RSP_RDATA       ;
+  sc_signal<Tdcache_error_t   >   **  in_DCACHE_RSP_ERROR       ;
+
+  sc_signal<Tcontrol_t        > ****  in_LSQ_REQ_VAL            ;
+  sc_signal<Tcontrol_t        > **** out_LSQ_REQ_ACK            ;
+  sc_signal<Tcontext_t        > ****  in_LSQ_REQ_THREAD_ID      ;
+  sc_signal<Tpacket_t         > ****  in_LSQ_REQ_PACKET_ID      ;
+  sc_signal<Tdcache_address_t > ****  in_LSQ_REQ_ADDRESS        ;
+  sc_signal<Tdcache_data_t    > ****  in_LSQ_REQ_WDATA          ;
+  sc_signal<Tdcache_type_t    > ****  in_LSQ_REQ_TYPE           ;
+
+  sc_signal<Tcontrol_t        > **** out_LSQ_RSP_VAL            ;
+  sc_signal<Tcontrol_t        > ****  in_LSQ_RSP_ACK            ;
+  sc_signal<Tcontext_t        > **** out_LSQ_RSP_THREAD_ID      ;
+  sc_signal<Tpacket_t         > **** out_LSQ_RSP_PACKET_ID      ;
+  sc_signal<Tdcache_data_t    > **** out_LSQ_RSP_RDATA          ;
+  sc_signal<Tdcache_error_t   > **** out_LSQ_RSP_ERROR          ;
 
   ALLOC1_SC_SIGNAL(out_DCACHE_REQ_VAL         ,"out_DCACHE_REQ_VAL      ",Tcontrol_t        ,_param->_nb_dcache_port);
@@ -183,4 +213,5 @@
   in_NRESET->write(1);  
 
+#ifdef SELFTEST
   LABEL("Loop of Test");
 
@@ -280,4 +311,7 @@
       SC_START(1);
     }
+#else
+  SC_START(5);
+#endif
 
   /********************************************************
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_req.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_req.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_req.cpp	(revision 128)
@@ -20,4 +20,5 @@
   {
     log_begin(Dcache_Access,FUNCTION);
+    log_function(Dcache_Access,FUNCTION,_name.c_str());
 
     if (PORT_READ(in_NRESET))
@@ -53,8 +54,9 @@
 	      {
 		uint32_t   num_port       = _param->_table_routing[num_execute_loop][num_load_store_unit][num_cache_access];
+
+                log_printf(TRACE,Dcache_Access,FUNCTION,"  * LSQ_REQ [%d][%d][%d] <-> DCACHE_REQ [%d]",num_execute_loop,num_load_store_unit,num_cache_access,num_port);
+
 		Tcontrol_t dcache_req_ack = PORT_READ(in_DCACHE_REQ_ACK [num_port]);
 
-                log_printf(TRACE,Dcache_Access,FUNCTION,"  * num_port      : %d",num_port);
-		
 #ifdef STATISTICS
 		if (dcache_req_ack)
@@ -67,9 +69,9 @@
 		if (not dcache_req_val [num_port])
 		  {
+                    log_printf(TRACE,Dcache_Access,FUNCTION,"  * is valid !!!");
+
 		    dcache_req_val  [num_port] = 1;
 		    lsq_req_ack [num_execute_loop][num_load_store_unit][num_cache_access] = dcache_req_ack;
 		    
-                    log_printf(TRACE,Dcache_Access,FUNCTION,"    * kane - dcache");
-
 		    if (_param->_have_port_dcache_thread_id)
                       {
@@ -79,4 +81,8 @@
                     log_printf(TRACE,Dcache_Access,FUNCTION,"    * num_thread  : %d",num_thread );
 
+#ifdef DEBUG_TEST
+                    if (num_thread >= _param->_nb_thread)
+                      throw ERRORMORPHEO(FUNCTION,toString(_("Invalid thread number : %d\n"),num_thread));
+#endif
 
                     PORT_WRITE(out_DCACHE_REQ_THREAD_ID [num_port], num_thread);
@@ -88,7 +94,10 @@
  		    if (_param->_have_port_dcache_packet_id)
                       {
-                    Tpacket_t packet_id = (_param->_have_port_lsq_packet_id [num_execute_loop][num_load_store_unit])?PORT_READ(in_LSQ_REQ_PACKET_ID [num_execute_loop][num_load_store_unit][num_cache_access]):0;
-                    PORT_WRITE(out_DCACHE_REQ_PACKET_ID [num_port], ((num_cache_access    << _param->_shift_num_cache_access   )+
-                                                                     packet_id));
+                    Tpacket_t packet_id = ((num_cache_access << _param->_shift_num_cache_access)+
+                                           ((_param->_have_port_lsq_packet_id [num_execute_loop][num_load_store_unit])?PORT_READ(in_LSQ_REQ_PACKET_ID [num_execute_loop][num_load_store_unit][num_cache_access]):0));
+
+                    log_printf(TRACE,Dcache_Access,FUNCTION,"    * packet_id   : %d",packet_id);
+
+                    PORT_WRITE(out_DCACHE_REQ_PACKET_ID [num_port], packet_id);
                       }
 		    PORT_WRITE(out_DCACHE_REQ_ADDRESS   [num_port], PORT_READ(in_LSQ_REQ_ADDRESS   [num_execute_loop][num_load_store_unit][num_cache_access]));
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_rsp.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_rsp.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_rsp.cpp	(revision 128)
@@ -20,4 +20,5 @@
   {
     log_begin(Dcache_Access,FUNCTION);
+    log_function(Dcache_Access,FUNCTION,_name.c_str());
 
     if (PORT_READ(in_NRESET))
@@ -46,8 +47,13 @@
 	    Tpacket_t  lsq_packet_id       =  packet_id                                        & _param->_mask_num_lsq_packet;
 
-// 	    log_printf(TRACE,Dcache_Access,FUNCTION,"thread_id          : %d",thread_id);
-// 	    log_printf(TRACE,Dcache_Access,FUNCTION,"execute_loop_id    : %d",execute_loop_id);
-// 	    log_printf(TRACE,Dcache_Access,FUNCTION,"load_store_unit_id : %d",load_store_unit_id);
-// 	    log_printf(TRACE,Dcache_Access,FUNCTION,"cache_access_id    : %d",cache_access_id);
+            log_printf(TRACE,Dcache_Access,FUNCTION,"  * DCACHE_RSP [%d] <-> LSQ_RSP [%d][%d][%d]",i,execute_loop_id,load_store_unit_id,cache_access_id);
+
+	    log_printf(TRACE,Dcache_Access,FUNCTION,"    * thread_id            : %d",thread_id);
+	    log_printf(TRACE,Dcache_Access,FUNCTION,"      * execute_loop_id    : %d",execute_loop_id);
+	    log_printf(TRACE,Dcache_Access,FUNCTION,"      * load_store_unit_id : %d",load_store_unit_id);
+	    log_printf(TRACE,Dcache_Access,FUNCTION,"      * context_id         : %d",context_id);
+	    log_printf(TRACE,Dcache_Access,FUNCTION,"    * packet_id            : %d",thread_id);
+	    log_printf(TRACE,Dcache_Access,FUNCTION,"      * cache_access_id    : %d",cache_access_id);
+	    log_printf(TRACE,Dcache_Access,FUNCTION,"      * lsq_packet_id      : %d",lsq_packet_id);
 	    
 #ifdef DEBUG_TEST
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters.cpp	(revision 128)
@@ -55,4 +55,16 @@
     _translate_load_store_unit_to_thread = translate_load_store_unit_to_thread;
 
+//     log_printf(TRACE,Dcache_Access,FUNCTION,"  * table_routing");
+//     for (uint32_t i=0; i<_nb_execute_loop; i++)
+//       for (uint32_t j=0; j<_nb_load_store_unit [i]; ++j)
+// 	for (uint32_t k=0; k<_nb_cache_access [i][j]; ++k)
+//           log_printf(TRACE,Dcache_Access,FUNCTION,"    [%d][%d][%d] %d",i,j,k,_table_routing [i][j][k]);
+
+//     log_printf(TRACE,Dcache_Access,FUNCTION,"  * translate_load_store_unit_to_thread");
+//     for (uint32_t i=0; i<_nb_execute_loop; i++)
+//       for (uint32_t j=0; j<_nb_load_store_unit [i]; j++)
+//         for (uint32_t k=0; k<_nb_context[i]; k++)
+//           log_printf(TRACE,Dcache_Access,FUNCTION,"    [%d][%d][%d] %d",i,j,k,_translate_load_store_unit_to_thread [i][j][k]);
+
     test();
 
@@ -93,4 +105,6 @@
     _translate_thread_to_context         = new uint32_t [nb_thread];
 
+    log_printf(TRACE,Dcache_Access,FUNCTION,"  * translate_load_store_unit_to_thread");
+
     for (uint32_t i=0; i<_nb_execute_loop; ++i)
       for (uint32_t j=0; j<_nb_load_store_unit [i]; ++j)
@@ -99,7 +113,18 @@
             uint32_t num_thread = _translate_load_store_unit_to_thread [i][j][k];
             
+            log_printf(TRACE,Dcache_Access,FUNCTION,"    [%d][%d][%d] %d",i,j,k,_translate_load_store_unit_to_thread [i][j][k]);
+
+            if (num_thread < _nb_thread)
+              {
             _translate_thread_to_execute_loop    [num_thread] = i;
             _translate_thread_to_load_store_unit [num_thread] = j;
             _translate_thread_to_context         [num_thread] = k;
+              }
+            else
+              {
+            _translate_thread_to_execute_loop    [num_thread] = _nb_execute_loop;
+            _translate_thread_to_load_store_unit [num_thread] = _nb_load_store_unit [i];
+            _translate_thread_to_context         [num_thread] = _nb_context [i];
+              }
           }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters_msg_error.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters_msg_error.cpp	(revision 128)
@@ -49,11 +49,15 @@
           {
             uint32_t num_thread = _translate_load_store_unit_to_thread [i][j][k];
-            if (num_thread >= _nb_thread)
-              test.error(toString(_("Context [%d][%d][%d] is linked with an invalid thread id.\n"),i,j,k));
-            else
-              if (thread_link [num_thread] == true)
-                test.error(toString(_("Context [%d][%d][%d] is linked with an already used thread id.\n"),i,j,k));
-              else
-                thread_link [num_thread] = true;
+
+            if (num_thread != _nb_thread)
+              thread_link [num_thread] = true;
+
+//             if (num_thread >= _nb_thread)
+//               test.error(toString(_("Context [%d][%d][%d] is linked with an invalid thread id.\n"),i,j,k));
+//             else
+//               if (thread_link [num_thread] == true)
+//                 test.error(toString(_("Context [%d][%d][%d] is linked with an already used thread id.\n"),i,j,k));
+//               else
+//                 thread_link [num_thread] = true;
           }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/main.cpp	(revision 128)
@@ -121,4 +121,6 @@
       
       test (name,param);
+
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/test.cpp	(revision 128)
@@ -53,4 +53,29 @@
   sc_clock              *  in_CLOCK  = new sc_clock ("clock", 1.0, 0.5);	 
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
+
+  sc_signal<Tcontrol_t           >   ** out_ICACHE_REQ_VAL         ;
+  sc_signal<Tcontrol_t           >   **  in_ICACHE_REQ_ACK         ;
+  sc_signal<Tcontext_t           >   ** out_ICACHE_REQ_THREAD_ID   ;
+  sc_signal<Tpacket_t            >   ** out_ICACHE_REQ_PACKET_ID   ;
+  sc_signal<Ticache_address_t    >   ** out_ICACHE_REQ_ADDRESS     ;
+  sc_signal<Ticache_type_t       >   ** out_ICACHE_REQ_TYPE        ;
+  sc_signal<Tcontrol_t           >   **  in_ICACHE_RSP_VAL         ;
+  sc_signal<Tcontrol_t           >   ** out_ICACHE_RSP_ACK         ;
+  sc_signal<Tcontext_t           >   **  in_ICACHE_RSP_THREAD_ID   ;
+  sc_signal<Tpacket_t            >   **  in_ICACHE_RSP_PACKET_ID   ;
+  sc_signal<Ticache_instruction_t>  ***  in_ICACHE_RSP_INSTRUCTION ;
+  sc_signal<Ticache_error_t      >   **  in_ICACHE_RSP_ERROR       ;
+  sc_signal<Tcontrol_t           >  ***  in_CONTEXT_REQ_VAL        ;
+  sc_signal<Tcontrol_t           >  *** out_CONTEXT_REQ_ACK        ;
+//sc_signal<Tcontext_t           >  ***  in_CONTEXT_REQ_THREAD_ID  ;
+  sc_signal<Tpacket_t            >  ***  in_CONTEXT_REQ_PACKET_ID  ;
+  sc_signal<Ticache_address_t    >  ***  in_CONTEXT_REQ_ADDRESS    ;
+  sc_signal<Ticache_type_t       >  ***  in_CONTEXT_REQ_TYPE       ;
+  sc_signal<Tcontrol_t           >  *** out_CONTEXT_RSP_VAL        ;
+  sc_signal<Tcontrol_t           >  ***  in_CONTEXT_RSP_ACK        ;
+//sc_signal<Tcontext_t           >  *** out_CONTEXT_RSP_THREAD_ID  ;
+  sc_signal<Tpacket_t            >  *** out_CONTEXT_RSP_PACKET_ID  ;
+  sc_signal<Ticache_instruction_t> **** out_CONTEXT_RSP_INSTRUCTION;
+  sc_signal<Ticache_error_t      >  *** out_CONTEXT_RSP_ERROR      ;
 
   ALLOC1_SC_SIGNAL(out_ICACHE_REQ_VAL         ,"out_ICACHE_REQ_VAL         ",Tcontrol_t           ,_param->_nb_icache_port);
@@ -165,4 +190,5 @@
   in_NRESET->write(1);  
 
+#ifdef SELFTEST
   LABEL("Loop of Test");
 
@@ -259,4 +285,7 @@
       SC_START(1);
     }
+#else
+  SC_START(5);
+#endif
 
   /********************************************************
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h	(revision 128)
@@ -109,5 +109,5 @@
       for (uint32_t i=0; i<NB_GROUP; i++)
 	{
-	  _spr               [i] = NULL;
+	  _spr [i] = NULL;
 	}
     }
@@ -117,7 +117,7 @@
       for (uint32_t x=0; x<NB_GROUP; x++)
 	if (_spr[x] != NULL)
-	  delete _spr[x];
-      delete _spr;
-      delete _spr_access_mode;
+	  delete [] _spr[x];
+      delete [] _spr;
+      delete    _spr_access_mode;
     }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp	(revision 128)
@@ -32,23 +32,23 @@
         DELETE0_SIGNAL( in_EXECUTE_IN_VAL                   ,1);
         DELETE0_SIGNAL(out_EXECUTE_IN_ACK                   ,1);
-        DELETE0_SIGNAL( in_EXECUTE_IN_CONTEXT_ID            , _param->_size_context_id   );
-        DELETE0_SIGNAL( in_EXECUTE_IN_FRONT_END_ID          , _param->_size_front_end_id );
-        DELETE0_SIGNAL( in_EXECUTE_IN_OOO_ENGINE_ID         , _param->_size_ooo_engine_id);
-        DELETE0_SIGNAL( in_EXECUTE_IN_PACKET_ID             , _param->_size_rob_ptr    );
-        DELETE0_SIGNAL( in_EXECUTE_IN_OPERATION             , _param->_size_operation    );
-        DELETE0_SIGNAL( in_EXECUTE_IN_TYPE                  , _param->_size_type         );
+        DELETE0_SIGNAL( in_EXECUTE_IN_CONTEXT_ID            ,_param->_size_context_id   );
+        DELETE0_SIGNAL( in_EXECUTE_IN_FRONT_END_ID          ,_param->_size_front_end_id );
+        DELETE0_SIGNAL( in_EXECUTE_IN_OOO_ENGINE_ID         ,_param->_size_ooo_engine_id);
+        DELETE0_SIGNAL( in_EXECUTE_IN_PACKET_ID             ,_param->_size_rob_ptr      );
+        DELETE0_SIGNAL( in_EXECUTE_IN_OPERATION             ,_param->_size_operation    );
+        DELETE0_SIGNAL( in_EXECUTE_IN_TYPE                  ,_param->_size_type         );
         DELETE0_SIGNAL( in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE ,_param->_size_store_queue_ptr);
         DELETE0_SIGNAL( in_EXECUTE_IN_STORE_QUEUE_PTR_READ  ,_param->_size_store_queue_ptr);
-        DELETE0_SIGNAL( in_EXECUTE_IN_STORE_QUEUE_EMPTY     , 1);
+        DELETE0_SIGNAL( in_EXECUTE_IN_STORE_QUEUE_EMPTY     ,1);
         DELETE0_SIGNAL( in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE  ,_param->_size_load_queue_ptr);
-        DELETE0_SIGNAL( in_EXECUTE_IN_HAS_IMMEDIAT          , 1);
-        DELETE0_SIGNAL( in_EXECUTE_IN_IMMEDIAT              , _param->_size_general_data);
-        DELETE0_SIGNAL( in_EXECUTE_IN_DATA_RA               , _param->_size_general_data);
-        DELETE0_SIGNAL( in_EXECUTE_IN_DATA_RB               , _param->_size_general_data);
-        DELETE0_SIGNAL( in_EXECUTE_IN_DATA_RC               , _param->_size_special_data);
-        DELETE0_SIGNAL( in_EXECUTE_IN_WRITE_RD              , 1);
-        DELETE0_SIGNAL( in_EXECUTE_IN_NUM_REG_RD            , _param->_size_general_register);
-        DELETE0_SIGNAL( in_EXECUTE_IN_WRITE_RE              , 1);
-        DELETE0_SIGNAL( in_EXECUTE_IN_NUM_REG_RE            , _param->_size_special_register);
+        DELETE0_SIGNAL( in_EXECUTE_IN_HAS_IMMEDIAT          ,1);
+        DELETE0_SIGNAL( in_EXECUTE_IN_IMMEDIAT              ,_param->_size_general_data);
+        DELETE0_SIGNAL( in_EXECUTE_IN_DATA_RA               ,_param->_size_general_data);
+        DELETE0_SIGNAL( in_EXECUTE_IN_DATA_RB               ,_param->_size_general_data);
+        DELETE0_SIGNAL( in_EXECUTE_IN_DATA_RC               ,_param->_size_special_data);
+        DELETE0_SIGNAL( in_EXECUTE_IN_WRITE_RD              ,1);
+        DELETE0_SIGNAL( in_EXECUTE_IN_NUM_REG_RD            ,_param->_size_general_register);
+        DELETE0_SIGNAL( in_EXECUTE_IN_WRITE_RE              ,1);
+        DELETE0_SIGNAL( in_EXECUTE_IN_NUM_REG_RE            ,_param->_size_special_register);
 
         DELETE0_SIGNAL(out_EXECUTE_OUT_VAL            ,1);
@@ -72,15 +72,24 @@
         // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
         
+        for (uint32_t i=0; i<_param->_nb_type; i++)
+        delete [] _function_execute [i];
+        delete [] _function_execute;
+
 	for (uint32_t i=0; i<_param->_nb_context; i++)
-	  for (uint32_t j=0; j<_param->_nb_front_end; j++)
-	    for (uint32_t k=0; k<_param->_nb_ooo_engine; k++)
-	      delete _execute_register [i][j][k];
+          {
+            for (uint32_t j=0; j<_param->_nb_front_end; j++)
+              {
+                for (uint32_t k=0; k<_param->_nb_ooo_engine; k++)
+                delete    _execute_register [i][j][k];
+                delete [] _execute_register [i][j];
+              }
+            delete [] _execute_register [i];
+          }
+        delete [] _execute_register;
 
-        DELETE3(_execute_register,_param->_nb_context,_param->_nb_front_end,_param->_nb_ooo_engine);
-        DELETE0(_execute_param);
+        delete    _execute_param;
+        delete    _execute_operation_out;
         if (_param->_have_pipeline_in)
-        DELETE0(_execute_operation_in);
-        DELETE0(_execute_operation_out);
-        DELETE2(_function_execute,_param->_nb_type,_param->_nb_operation);
+        delete    _execute_operation_in;
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp	(revision 128)
@@ -132,4 +132,7 @@
 	    execute_operation->_num_reg_re    = PORT_READ(in_EXECUTE_IN_NUM_REG_RE  );
 	    execute_operation->_data_re       = 0; // no necessaray
+	    execute_operation->_exception     = 0; // no necessaray
+	    execute_operation->_no_sequence   = 0; // no necessaray
+	    execute_operation->_address       = 0; // no necessaray
 
             log_printf(TRACE,Functionnal_unit,FUNCTION,"    * context_id    : %d",execute_operation->_context_id   );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 128)
@@ -122,9 +122,12 @@
 
 #if defined(DEBUG) and defined(DEBUG_Load_store_unit) and (DEBUG_Load_store_unit == true)
-    for (uint32_t i=0; i<_param->_nb_thread; ++i)
-      if (_param->_num_thread_valid [i])
-        {
-          memory_log_file [i].close();
-        }
+    {
+      for (uint32_t i=0; i<_param->_nb_thread; ++i)
+        if (_param->_num_thread_valid [i])
+          {
+            memory_log_file [i].close();
+          }
+      delete [] memory_log_file;
+    }
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 128)
@@ -239,18 +239,65 @@
 	_speculative_access_queue_control->clear();
 
-	reg_STORE_QUEUE_PTR_READ = 0;
+	reg_STORE_QUEUE_PTR_READ       = 0;
 	reg_LOAD_QUEUE_CHECK_PRIORITY  = 0;
 
 	for (uint32_t i=0; i< _param->_size_store_queue             ; i++)
           {
-          reg_STORE_QUEUE_NB_CHECK  [i] = 0;
-	  _store_queue              [i]._state = STORE_QUEUE_EMPTY;
+            reg_STORE_QUEUE_NB_CHECK  [i] = 0;
+  	    _store_queue              [i]._state                 = STORE_QUEUE_EMPTY;
+  	    _store_queue              [i]._context_id            = 0; // not necessary
+  	    _store_queue              [i]._front_end_id          = 0; // not necessary
+  	    _store_queue              [i]._ooo_engine_id         = 0; // not necessary
+  	    _store_queue              [i]._packet_id             = 0; // not necessary
+  	    _store_queue              [i]._operation             = 0; // not necessary
+  	    _store_queue              [i]._load_queue_ptr_write  = 0; // not necessary
+  	    _store_queue              [i]._address               = 0; // not necessary
+  	    _store_queue              [i]._wdata                 = 0; // not necessary
+//	    _store_queue              [i]._write_rd              = 0; // not necessary
+//	    _store_queue              [i]._num_reg_rd            = 0; // not necessary
+  	    _store_queue              [i]._exception             = 0; // not necessary
+  	    _store_queue              [i]._send_commit           = 0; // not necessary
           }
 
 	for (uint32_t i=0; i< _param->_size_load_queue              ; i++)
-	  _load_queue               [i]._state = LOAD_QUEUE_EMPTY;
+          {
+            _load_queue               [i]._state                 = LOAD_QUEUE_EMPTY;
+            _load_queue               [i]._context_id            = 0; // not necessary
+            _load_queue               [i]._front_end_id          = 0; // not necessary
+            _load_queue               [i]._ooo_engine_id         = 0; // not necessary
+            _load_queue               [i]._packet_id             = 0; // not necessary
+            _load_queue               [i]._operation             = 0; // not necessary
+            _load_queue               [i]._store_queue_ptr_write = 0; // not necessary
+            _load_queue               [i]._store_queue_ptr_read  = 0; // not necessary
+            _load_queue               [i]._store_queue_empty     = 0; // not necessary
+            _load_queue               [i]._address               = 0; // not necessary
+            _load_queue               [i]._check_hit_byte        = 0; // not necessary 
+            _load_queue               [i]._check_hit             = 0; // not necessary
+            _load_queue               [i]._shift                 = 0; // not necessary
+            _load_queue               [i]._is_load_signed        = 0; // not necessary
+            _load_queue               [i]._access_size           = 0; // not necessary
+            _load_queue               [i]._rdata                 = 0; // not necessary
+            _load_queue               [i]._write_rd              = 0; // not necessary
+            _load_queue               [i]._num_reg_rd            = 0; // not necessary
+            _load_queue               [i]._exception             = 0; // not necessary
+          }
 
 	for (uint32_t i=0; i< _param->_size_speculative_access_queue; i++)
-	  _speculative_access_queue [i]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY;
+          {
+            _speculative_access_queue [i]._state                 = SPECULATIVE_ACCESS_QUEUE_EMPTY;
+            _speculative_access_queue [i]._context_id            = 0; // not necessary
+            _speculative_access_queue [i]._front_end_id          = 0; // not necessary
+            _speculative_access_queue [i]._ooo_engine_id         = 0; // not necessary
+            _speculative_access_queue [i]._packet_id             = 0; // not necessary
+            _speculative_access_queue [i]._operation             = 0; // not necessary
+            _speculative_access_queue [i]._load_queue_ptr_write  = 0; // not necessary
+            _speculative_access_queue [i]._store_queue_ptr_write = 0; // not necessary
+            _speculative_access_queue [i]._store_queue_ptr_read  = 0; // not necessary
+            _speculative_access_queue [i]._store_queue_empty     = 0; // not necessary
+            _speculative_access_queue [i]._address               = 0; // not necessary
+            _speculative_access_queue [i]._write_rd              = 0; // not necessary
+            _speculative_access_queue [i]._num_reg_rd            = 0; // not necessary
+            _speculative_access_queue [i]._exception             = 0; // not necessary
+          }
       }
     else
@@ -1000,7 +1047,7 @@
 	    bool         have_exception = (exception != EXCEPTION_MEMORY_NONE);
             bool         need_check= false;
-            Tlsq_ptr_t        store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;
-            Tlsq_ptr_t        store_queue_ptr_read  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_read ;
-            Tcontrol_t        store_queue_empty     = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_empty    ;
+            Tlsq_ptr_t   store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;
+            Tlsq_ptr_t   store_queue_ptr_read  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_read ;
+            Tcontrol_t   store_queue_empty     = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_empty    ;
 	    
 	    if (have_exception)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_deallocation.cpp	(revision 128)
@@ -62,5 +62,7 @@
         DELETE0_SIGNAL(out_READ_QUEUE_OUT_OPERATION            ,_param->_size_operation        );
         DELETE0_SIGNAL(out_READ_QUEUE_OUT_TYPE                 ,_param->_size_type             );
-        DELETE0_SIGNAL(out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE, _param->_size_store_queue_ptr );
+        DELETE0_SIGNAL(out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE,_param->_size_store_queue_ptr  );
+        DELETE0_SIGNAL(out_READ_QUEUE_OUT_STORE_QUEUE_PTR_READ ,_param->_size_store_queue_ptr  );
+        DELETE0_SIGNAL(out_READ_QUEUE_OUT_STORE_QUEUE_EMPTY    ,1                              );
         DELETE0_SIGNAL(out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE , _param->_size_load_queue_ptr  );
         DELETE0_SIGNAL(out_READ_QUEUE_OUT_HAS_IMMEDIAT         ,1                              );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp	(revision 128)
@@ -42,17 +42,37 @@
 
 	// Init, else error in registerfile
-	_queue_head->_ooo_engine_id = 0;
-        // not necessary
-        _queue_head->_read_ra_val = false;
-        _queue_head->_read_rb_val = false;
-        _queue_head->_read_rc_val = false;
-
-        _queue_head->_data_ra_val = false;
-        _queue_head->_data_rb_val = false;
-        _queue_head->_data_rc_val = false;
-
-        _queue_head->_num_reg_ra  = 0;
-        _queue_head->_num_reg_rb  = 0;
-        _queue_head->_num_reg_rc  = 0;
+	_queue_head->_context_id           = 0;// not necessary
+	_queue_head->_front_end_id         = 0;// not necessary
+	_queue_head->_ooo_engine_id        = 0;// not necessary
+
+        _queue_head->_rob_id                = 0;// not necessary
+        _queue_head->_operation             = 0;// not necessary
+        _queue_head->_type                  = 0;// not necessary
+        _queue_head->_store_queue_ptr_write = 0;// not necessary
+        _queue_head->_store_queue_ptr_read  = 0;// not necessary
+        _queue_head->_store_queue_empty     = 0;// not necessary
+        _queue_head->_load_queue_ptr_write  = 0;// not necessary
+        _queue_head->_has_immediat          = 0;// not necessary
+        _queue_head->_immediat              = 0;// not necessary
+
+        _queue_head->_read_ra               = 0;// not necessary
+        _queue_head->_read_rb               = 0;// not necessary
+        _queue_head->_read_rc               = 0;// not necessary
+        _queue_head->_write_rd              = 0;// not necessary
+        _queue_head->_write_re              = 0;// not necessary
+
+        _queue_head->_read_ra_val          = false;
+        _queue_head->_read_rb_val          = false;
+        _queue_head->_read_rc_val          = false;
+
+        _queue_head->_data_ra_val          = false;
+        _queue_head->_data_rb_val          = false;
+        _queue_head->_data_rc_val          = false;
+
+        _queue_head->_num_reg_ra           = 0;// not necessary
+        _queue_head->_num_reg_rb           = 0;// not necessary
+        _queue_head->_num_reg_rc           = 0;// not necessary
+        _queue_head->_num_reg_rd           = 0;// not necessary
+        _queue_head->_num_reg_re           = 0;// not necessary
       }
     else
@@ -76,31 +96,26 @@
 	    Tread_queue_entry_t * entry = new Tread_queue_entry_t;
 
-	    if(_param->_have_port_context_id   )
-	    entry->_context_id   = PORT_READ(in_READ_QUEUE_IN_CONTEXT_ID  );
-	    if(_param->_have_port_front_end_id )
-	    entry->_front_end_id = PORT_READ(in_READ_QUEUE_IN_FRONT_END_ID);
-	    if(_param->_have_port_ooo_engine_id)
-	    entry->_ooo_engine_id= PORT_READ(in_READ_QUEUE_IN_OOO_ENGINE_ID);
-	    if(_param->_have_port_rob_ptr      )
-	    entry->_rob_id       = PORT_READ(in_READ_QUEUE_IN_ROB_ID      );
-	    entry->_operation    = PORT_READ(in_READ_QUEUE_IN_OPERATION   );
-	    entry->_type         = PORT_READ(in_READ_QUEUE_IN_TYPE        );
+            entry->_context_id            = (_param->_have_port_context_id    )?PORT_READ(in_READ_QUEUE_IN_CONTEXT_ID   ):0;
+	    entry->_front_end_id          = (_param->_have_port_front_end_id  )?PORT_READ(in_READ_QUEUE_IN_FRONT_END_ID ):0;
+	    entry->_ooo_engine_id         = (_param->_have_port_ooo_engine_id )?PORT_READ(in_READ_QUEUE_IN_OOO_ENGINE_ID):0;
+            entry->_rob_id                = (_param->_have_port_rob_ptr       )?PORT_READ(in_READ_QUEUE_IN_ROB_ID       ):0;
+	    entry->_operation             = PORT_READ(in_READ_QUEUE_IN_OPERATION   );
+	    entry->_type                  = PORT_READ(in_READ_QUEUE_IN_TYPE        );
 	    entry->_store_queue_ptr_write = PORT_READ(in_READ_QUEUE_IN_STORE_QUEUE_PTR_WRITE);
 	    entry->_store_queue_ptr_read  = PORT_READ(in_READ_QUEUE_IN_STORE_QUEUE_PTR_READ );
 	    entry->_store_queue_empty     = PORT_READ(in_READ_QUEUE_IN_STORE_QUEUE_EMPTY    );
-	    if (_param->_have_port_load_queue_ptr)
-	    entry->_load_queue_ptr_write  = PORT_READ(in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE );
-	    entry->_has_immediat = PORT_READ(in_READ_QUEUE_IN_HAS_IMMEDIAT);
-	    entry->_immediat     = PORT_READ(in_READ_QUEUE_IN_IMMEDIAT    );
-	    entry->_read_ra      = PORT_READ(in_READ_QUEUE_IN_READ_RA     );
-	    entry->_num_reg_ra   = PORT_READ(in_READ_QUEUE_IN_NUM_REG_RA  );
-	    entry->_read_rb      = PORT_READ(in_READ_QUEUE_IN_READ_RB     );
-	    entry->_num_reg_rb   = PORT_READ(in_READ_QUEUE_IN_NUM_REG_RB  );
-	    entry->_read_rc      = PORT_READ(in_READ_QUEUE_IN_READ_RC     );
-	    entry->_num_reg_rc   = PORT_READ(in_READ_QUEUE_IN_NUM_REG_RC  );
-	    entry->_write_rd     = PORT_READ(in_READ_QUEUE_IN_WRITE_RD    );
-	    entry->_num_reg_rd   = PORT_READ(in_READ_QUEUE_IN_NUM_REG_RD  );
-	    entry->_write_re     = PORT_READ(in_READ_QUEUE_IN_WRITE_RE    );
-	    entry->_num_reg_re   = PORT_READ(in_READ_QUEUE_IN_NUM_REG_RE  );
+            entry->_load_queue_ptr_write  = (_param->_have_port_load_queue_ptr)?PORT_READ(in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE ):0;
+	    entry->_has_immediat          = PORT_READ(in_READ_QUEUE_IN_HAS_IMMEDIAT);
+	    entry->_immediat              = PORT_READ(in_READ_QUEUE_IN_IMMEDIAT    );
+	    entry->_read_ra               = PORT_READ(in_READ_QUEUE_IN_READ_RA     );
+	    entry->_num_reg_ra            = PORT_READ(in_READ_QUEUE_IN_NUM_REG_RA  );
+	    entry->_read_rb               = PORT_READ(in_READ_QUEUE_IN_READ_RB     );
+	    entry->_num_reg_rb            = PORT_READ(in_READ_QUEUE_IN_NUM_REG_RB  );
+	    entry->_read_rc               = PORT_READ(in_READ_QUEUE_IN_READ_RC     );
+	    entry->_num_reg_rc            = PORT_READ(in_READ_QUEUE_IN_NUM_REG_RC  );
+	    entry->_write_rd              = PORT_READ(in_READ_QUEUE_IN_WRITE_RD    );
+	    entry->_num_reg_rd            = PORT_READ(in_READ_QUEUE_IN_NUM_REG_RD  );
+	    entry->_write_re              = PORT_READ(in_READ_QUEUE_IN_WRITE_RE    );
+	    entry->_num_reg_re            = PORT_READ(in_READ_QUEUE_IN_NUM_REG_RE  );
 
 	    log_printf(TRACE,Read_queue,FUNCTION,"    * push (id : %d-%d)",entry->_context_id, entry->_rob_id);
@@ -122,4 +137,5 @@
 	    // Pop the entry
 	    log_printf(TRACE,Read_queue,FUNCTION,"    * pop  (id : %d-%d)",_queue->front()->_context_id, _queue->front()->_rob_id);
+            delete _queue->front();
 	    _queue->pop_front();
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp	(revision 128)
@@ -112,4 +112,36 @@
 	_queue_control->clear();
 #endif
+
+	for (uint32_t i=0; i<_param->_size_queue; i++)
+          {
+	    _queue[i]._context_id            = 0; // not necessary
+	    _queue[i]._front_end_id          = 0; // not necessary
+	    _queue[i]._ooo_engine_id         = 0; // not necessary
+	    _queue[i]._rob_id                = 0; // not necessary
+  	    _queue[i]._operation             = 0; // not necessary
+  	    _queue[i]._type                  = 0; // not necessary
+  	    _queue[i]._store_queue_ptr_write = 0; // not necessary
+  	    _queue[i]._store_queue_ptr_read  = 0; // not necessary
+  	    _queue[i]._store_queue_empty     = 0; // not necessary
+  	    _queue[i]._load_queue_ptr_write  = 0; // not necessary
+  	    _queue[i]._has_immediat          = 0; // not necessary
+  	    _queue[i]._immediat              = 0; // not necessary
+//	    _queue[i]._read_ra               = 0; // not necessary
+  	    _queue[i]._num_reg_ra            = 0; // not necessary
+  	    _queue[i]._data_ra_val           = 0; // not necessary
+  	    _queue[i]._data_ra               = 0; // not necessary
+//	    _queue[i]._read_rb               = 0; // not necessary
+  	    _queue[i]._num_reg_rb            = 0; // not necessary
+  	    _queue[i]._data_rb_val           = 0; // not necessary
+  	    _queue[i]._data_rb               = 0; // not necessary
+//	    _queue[i]._read_rc               = 0; // not necessary
+  	    _queue[i]._num_reg_rc            = 0; // not necessary
+  	    _queue[i]._data_rc_val           = 0; // not necessary
+  	    _queue[i]._data_rc               = 0; // not necessary
+  	    _queue[i]._write_rd              = 0; // not necessary
+  	    _queue[i]._num_reg_rd            = 0; // not necessary
+  	    _queue[i]._write_re              = 0; // not necessary
+  	    _queue[i]._num_reg_re            = 0; // not necessary
+          }
       }
     else
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_deallocation.cpp	(revision 128)
@@ -38,4 +38,6 @@
         DELETE0_SIGNAL( in_READ_UNIT_IN_TYPE                 ,_param->_size_type         );
         DELETE0_SIGNAL( in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE,_param->_size_store_queue_ptr);
+        DELETE0_SIGNAL( in_READ_UNIT_IN_STORE_QUEUE_PTR_READ ,_param->_size_store_queue_ptr);
+        DELETE0_SIGNAL( in_READ_UNIT_IN_STORE_QUEUE_EMPTY    ,1);
         DELETE0_SIGNAL( in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,_param->_size_load_queue_ptr);
         DELETE0_SIGNAL( in_READ_UNIT_IN_HAS_IMMEDIAT         ,1);
@@ -61,4 +63,6 @@
         DELETE1_SIGNAL(out_READ_UNIT_OUT_TYPE                 ,_param->_nb_inst_retire,_param->_size_type            );
         DELETE1_SIGNAL(out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire,_param->_size_store_queue_ptr);
+        DELETE1_SIGNAL(out_READ_UNIT_OUT_STORE_QUEUE_PTR_READ ,_param->_nb_inst_retire,_param->_size_store_queue_ptr);
+        DELETE1_SIGNAL(out_READ_UNIT_OUT_STORE_QUEUE_EMPTY    ,_param->_nb_inst_retire,1);
         DELETE1_SIGNAL(out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire,_param->_size_load_queue_ptr);
         DELETE1_SIGNAL(out_READ_UNIT_OUT_HAS_IMMEDIAT         ,_param->_nb_inst_retire,1                             );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp	(revision 128)
@@ -91,7 +91,13 @@
     delete _queue;
 
+#ifdef VHDL
+     if (usage_is_set(_usage,USE_VHDL))
+       {
+         delete _component_queue;
+         delete _param_queue;
+       }
+#endif
+
     delete _component;
-    delete _component_queue;
-    delete _param_queue;
 
     log_printf(FUNC,Write_queue,FUNCTION,"End");
@@ -104,5 +110,4 @@
 }; // end namespace multi_execute_loop
 }; // end namespace core
-
 }; // end namespace behavioural
 }; // end namespace morpheo              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp	(revision 128)
@@ -18,5 +18,4 @@
 namespace write_unit {
 namespace write_queue {
-
 
 #undef  FUNCTION
@@ -114,4 +113,19 @@
                      (*it)->_no_sequence  ,
                      (*it)->_address      );
+
+//           log_printf(TRACE,Write_queue,FUNCTION,"    * context_id   : %d",  (*it)->_context_id   );
+//           log_printf(TRACE,Write_queue,FUNCTION,"    * front_end_id : %d",  (*it)->_front_end_id );
+//           log_printf(TRACE,Write_queue,FUNCTION,"    * ooo_engine_id: %d",  (*it)->_ooo_engine_id);
+//           log_printf(TRACE,Write_queue,FUNCTION,"    * packet_id    : %d",  (*it)->_packet_id    );
+//           log_printf(TRACE,Write_queue,FUNCTION,"    * write_rd     : %d",  (*it)->_write_rd     );
+//           log_printf(TRACE,Write_queue,FUNCTION,"    * num_reg_rd   : %d",  (*it)->_num_reg_rd   );
+//           log_printf(TRACE,Write_queue,FUNCTION,"    * data_rd      : %d",  (*it)->_data_rd      );
+//           log_printf(TRACE,Write_queue,FUNCTION,"    * write_re     : %d",  (*it)->_write_re     );
+//           log_printf(TRACE,Write_queue,FUNCTION,"    * num_reg_re   : %d",  (*it)->_num_reg_re   );
+//           log_printf(TRACE,Write_queue,FUNCTION,"    * data_re      : %d",  (*it)->_data_re      );
+//           log_printf(TRACE,Write_queue,FUNCTION,"    * exception    : %d",  (*it)->_exception    );
+//           log_printf(TRACE,Write_queue,FUNCTION,"    * no_sequence  : %d",  (*it)->_no_sequence  );
+//           log_printf(TRACE,Write_queue,FUNCTION,"    * address      : %d",  (*it)->_address      );
+
           i++;
         }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_deallocation.cpp	(revision 128)
@@ -38,4 +38,6 @@
          DELETE2_SIGNAL( in_READ_UNIT_OUT_TYPE                   , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_type             );
          DELETE2_SIGNAL( in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE  , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_store_queue_ptr  );
+         DELETE2_SIGNAL( in_READ_UNIT_OUT_STORE_QUEUE_PTR_READ   , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_store_queue_ptr  );
+         DELETE2_SIGNAL( in_READ_UNIT_OUT_STORE_QUEUE_EMPTY      , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],1                              );
          DELETE2_SIGNAL( in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE   , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_load_queue_ptr   );
          DELETE2_SIGNAL( in_READ_UNIT_OUT_HAS_IMMEDIAT           , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],1                              );
@@ -63,4 +65,6 @@
          DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_NUM_REG_RE           , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_special_register );
          DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE, _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_store_queue_ptr  );
+         DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_READ , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_store_queue_ptr  );
+         DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_STORE_QUEUE_EMPTY    , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],1                              );
          DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_load_queue_ptr   );
          DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_IMMEDIAT             , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_general_data     );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/include/Register_unit_Glue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/include/Register_unit_Glue.h	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/include/Register_unit_Glue.h	(revision 128)
@@ -61,6 +61,6 @@
   public    : SC_CLOCK                      *  in_CLOCK  ;
   public    : SC_IN (Tcontrol_t)            *  in_NRESET ;
-  public    : SC_OUT(Tcontrol_t        )    * out_CONST_0;
-  public    : SC_OUT(Tcontrol_t        )    * out_CONST_1;
+//public    : SC_OUT(Tcontrol_t        )    * out_CONST_0;
+//public    : SC_OUT(Tcontrol_t        )    * out_CONST_1;
 
     // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -77,5 +77,5 @@
   public    : SC_OUT(Tcontrol_t        )  *** out_GPR_READ_STATUS_VAL       ;
   public    : SC_IN (Tcontrol_t        )  ***  in_GPR_READ_STATUS_ACK       ;
-  public    : SC_IN (Tcontrol_t        )  ***  in_GPR_READ_STATUS_DATA_VAL  ;
+  public    : SC_IN (Tgeneral_data_t   )  ***  in_GPR_READ_STATUS_DATA_VAL  ; // type for compatibility with the registerFile
 
     // ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -92,5 +92,5 @@
   public    : SC_OUT(Tcontrol_t        )  *** out_SPR_READ_STATUS_VAL       ;
   public    : SC_IN (Tcontrol_t        )  ***  in_SPR_READ_STATUS_ACK       ;
-  public    : SC_IN (Tcontrol_t        )  ***  in_SPR_READ_STATUS_DATA_VAL  ;
+  public    : SC_IN (Tspecial_data_t   )  ***  in_SPR_READ_STATUS_DATA_VAL  ; // type for compatibility with the registerFile
 
     // ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -104,4 +104,5 @@
   public    : SC_OUT(Tcontrol_t        )  *** out_GPR_WRITE_STATUS_VAL      ;
   public    : SC_IN (Tcontrol_t        )  ***  in_GPR_WRITE_STATUS_ACK      ;
+  public    : SC_OUT(Tgeneral_data_t   )  *** out_GPR_WRITE_STATUS_DATA     ; // type for compatibility with the registerFile
     
     // ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -115,4 +116,5 @@
   public    : SC_OUT(Tcontrol_t        )  *** out_SPR_WRITE_STATUS_VAL      ;
   public    : SC_IN (Tcontrol_t        )  ***  in_SPR_WRITE_STATUS_ACK      ;
+  public    : SC_OUT(Tspecial_data_t   )  *** out_SPR_WRITE_STATUS_DATA     ; // type for compatibility with the registerFile
 
     // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -124,7 +126,9 @@
   public    : SC_OUT(Tcontrol_t        )  *** out_INSERT_ROB_GPR_STATUS_VAL            ;
   public    : SC_IN (Tcontrol_t        )  ***  in_INSERT_ROB_GPR_STATUS_ACK            ;
+  public    : SC_OUT(Tgeneral_data_t   )  *** out_INSERT_ROB_GPR_STATUS_DATA           ; // type for compatibility with the registerFile
 
   public    : SC_OUT(Tcontrol_t        )  *** out_INSERT_ROB_SPR_STATUS_VAL            ;
   public    : SC_IN (Tcontrol_t        )  ***  in_INSERT_ROB_SPR_STATUS_ACK            ;
+  public    : SC_OUT(Tspecial_data_t   )  *** out_INSERT_ROB_SPR_STATUS_DATA           ; // type for compatibility with the registerFile
 
 //     // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue.cpp	(revision 128)
@@ -71,7 +71,19 @@
       {
     // Constant
-
-    PORT_WRITE(out_CONST_0 ,0);
-    PORT_WRITE(out_CONST_1 ,1);
+//     PORT_WRITE(out_CONST_0 ,0);
+//     PORT_WRITE(out_CONST_1 ,1);
+        for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
+          {
+            for (uint32_t j=0; j<_param->_nb_gpr_write; ++j)
+              PORT_WRITE(out_GPR_WRITE_STATUS_DATA [i][j],1);
+            for (uint32_t j=0; j<_param->_nb_spr_write; ++j)
+              PORT_WRITE(out_SPR_WRITE_STATUS_DATA [i][j],1);
+
+            for (uint32_t j=0; j<_param->_nb_inst_insert_rob[i]; ++j)
+              {
+                PORT_WRITE(out_INSERT_ROB_GPR_STATUS_DATA [i][j],0);
+                PORT_WRITE(out_INSERT_ROB_SPR_STATUS_DATA [i][j],0);
+              }
+          }
 
     log_printf(INFO,Register_unit_Glue,FUNCTION,"Method - transition");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_allocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_allocation.cpp	(revision 128)
@@ -48,6 +48,6 @@
      in_CLOCK        = interface->set_signal_clk              ("clock" ,1, CLOCK_VHDL_NO);
      in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_NO);
-    out_CONST_0      = interface->set_signal_out <Tcontrol_t> ("const_0",1);
-    out_CONST_1      = interface->set_signal_out <Tcontrol_t> ("const_1",1);
+//     out_CONST_0      = interface->set_signal_out <Tcontrol_t> ("const_0",1);
+//     out_CONST_1      = interface->set_signal_out <Tcontrol_t> ("const_1",1);
 
     // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -79,5 +79,5 @@
       ALLOC2_VALACK_OUT(out_GPR_READ_STATUS_VAL      ,VAL);
       ALLOC2_VALACK_IN ( in_GPR_READ_STATUS_ACK      ,ACK);
-      ALLOC2_SIGNAL_IN ( in_GPR_READ_STATUS_DATA_VAL,"data_val",Tcontrol_t,1);
+      ALLOC2_SIGNAL_IN ( in_GPR_READ_STATUS_DATA_VAL,"data_val",Tgeneral_data_t,1);
 
       ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_gpr_read);
@@ -112,5 +112,5 @@
       ALLOC2_VALACK_OUT(out_SPR_READ_STATUS_VAL      ,VAL);
       ALLOC2_VALACK_IN ( in_SPR_READ_STATUS_ACK      ,ACK);
-      ALLOC2_SIGNAL_IN ( in_SPR_READ_STATUS_DATA_VAL,"data_val",Tcontrol_t,1);
+      ALLOC2_SIGNAL_IN ( in_SPR_READ_STATUS_DATA_VAL,"data_val",Tspecial_data_t,1);
       
       ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_spr_read);
@@ -140,6 +140,7 @@
       ALLOC2_INTERFACE_BEGIN("gpr_write_status",IN,NORTH,_("Interface to write generalist register - from/to status"),_param->_nb_ooo_engine,_param->_nb_gpr_write);
       
-      ALLOC2_VALACK_OUT(out_GPR_WRITE_STATUS_VAL,VAL);
-      ALLOC2_VALACK_IN ( in_GPR_WRITE_STATUS_ACK,ACK);
+      ALLOC2_VALACK_OUT(out_GPR_WRITE_STATUS_VAL ,VAL);
+      ALLOC2_VALACK_IN ( in_GPR_WRITE_STATUS_ACK ,ACK);
+      ALLOC2_SIGNAL_OUT(out_GPR_WRITE_STATUS_DATA,"data",Tgeneral_data_t,1);
 
       ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_gpr_write);
@@ -171,4 +172,5 @@
       ALLOC2_VALACK_OUT(out_SPR_WRITE_STATUS_VAL,VAL);
       ALLOC2_VALACK_IN ( in_SPR_WRITE_STATUS_ACK,ACK);
+      ALLOC2_SIGNAL_OUT(out_SPR_WRITE_STATUS_DATA,"data",Tspecial_data_t,1);
 
       ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_spr_write);
@@ -190,6 +192,7 @@
       ALLOC2_INTERFACE_BEGIN("insert_rob_gpr_status",IN,WEST,_("Interface to update status (insert)"),_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
       
-      _ALLOC2_VALACK_OUT(out_INSERT_ROB_GPR_STATUS_VAL,VAL,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
-      _ALLOC2_VALACK_IN ( in_INSERT_ROB_GPR_STATUS_ACK,ACK,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
+      _ALLOC2_VALACK_OUT(out_INSERT_ROB_GPR_STATUS_VAL ,VAL                   ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
+      _ALLOC2_VALACK_IN ( in_INSERT_ROB_GPR_STATUS_ACK ,ACK                   ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
+      _ALLOC2_SIGNAL_OUT(out_INSERT_ROB_GPR_STATUS_DATA,"data",Tgeneral_data_t,1,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
 
       ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
@@ -199,6 +202,7 @@
       ALLOC2_INTERFACE_BEGIN("insert_rob_spr_status",IN,WEST,_("Interface to update status (insert)"),_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
       
-      _ALLOC2_VALACK_OUT(out_INSERT_ROB_SPR_STATUS_VAL,VAL,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
-      _ALLOC2_VALACK_IN ( in_INSERT_ROB_SPR_STATUS_ACK,ACK,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
+      _ALLOC2_VALACK_OUT(out_INSERT_ROB_SPR_STATUS_VAL ,VAL                   ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
+      _ALLOC2_VALACK_IN ( in_INSERT_ROB_SPR_STATUS_ACK ,ACK                   ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
+      _ALLOC2_SIGNAL_OUT(out_INSERT_ROB_SPR_STATUS_DATA,"data",Tspecial_data_t,1,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
 
       ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_deallocation.cpp	(revision 128)
@@ -24,5 +24,5 @@
     log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin");
 
-    if (usage_is_set(_usage,USE_VHDL))
+//     if (usage_is_set(_usage,USE_VHDL))
       {
 //#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
@@ -30,6 +30,6 @@
 //#endif
     delete  in_NRESET;
-    delete out_CONST_0;
-    delete out_CONST_1;
+//     delete out_CONST_0;
+//     delete out_CONST_1;
 
     DELETE1_SIGNAL( in_GPR_READ_VAL           ,_param->_nb_gpr_read,1  );
@@ -69,27 +69,31 @@
     DELETE2_SIGNAL( in_GPR_WRITE_REGISTERFILE_ACK,_param->_nb_ooo_engine,_param->_nb_gpr_write,1  );
 
-    DELETE2_SIGNAL(out_GPR_WRITE_STATUS_VAL,_param->_nb_ooo_engine,_param->_nb_gpr_write,1  );
-    DELETE2_SIGNAL( in_GPR_WRITE_STATUS_ACK,_param->_nb_ooo_engine,_param->_nb_gpr_write,1  );
+    DELETE2_SIGNAL(out_GPR_WRITE_STATUS_VAL      ,_param->_nb_ooo_engine,_param->_nb_gpr_write,1  );
+    DELETE2_SIGNAL( in_GPR_WRITE_STATUS_ACK      ,_param->_nb_ooo_engine,_param->_nb_gpr_write,1  );
+    DELETE2_SIGNAL(out_GPR_WRITE_STATUS_DATA     ,_param->_nb_ooo_engine,_param->_nb_gpr_write,1  );
 
-    DELETE1_SIGNAL( in_SPR_WRITE_VAL          ,_param->_nb_spr_write,1  );
-    DELETE1_SIGNAL(out_SPR_WRITE_ACK          ,_param->_nb_spr_write,1  );
-    DELETE1_SIGNAL( in_SPR_WRITE_OOO_ENGINE_ID,_param->_nb_spr_write,_param->_size_ooo_engine_id);
+    DELETE1_SIGNAL( in_SPR_WRITE_VAL             ,_param->_nb_spr_write,1  );
+    DELETE1_SIGNAL(out_SPR_WRITE_ACK             ,_param->_nb_spr_write,1  );
+    DELETE1_SIGNAL( in_SPR_WRITE_OOO_ENGINE_ID   ,_param->_nb_spr_write,_param->_size_ooo_engine_id);
 
     DELETE2_SIGNAL(out_SPR_WRITE_REGISTERFILE_VAL,_param->_nb_ooo_engine,_param->_nb_spr_write,1  );
     DELETE2_SIGNAL( in_SPR_WRITE_REGISTERFILE_ACK,_param->_nb_ooo_engine,_param->_nb_spr_write,1  );
 
-    DELETE2_SIGNAL(out_SPR_WRITE_STATUS_VAL,_param->_nb_ooo_engine,_param->_nb_spr_write,1  );
-    DELETE2_SIGNAL( in_SPR_WRITE_STATUS_ACK,_param->_nb_ooo_engine,_param->_nb_spr_write,1  );
+    DELETE2_SIGNAL(out_SPR_WRITE_STATUS_VAL      ,_param->_nb_ooo_engine,_param->_nb_spr_write,1  );
+    DELETE2_SIGNAL( in_SPR_WRITE_STATUS_ACK      ,_param->_nb_ooo_engine,_param->_nb_spr_write,1  );
+    DELETE2_SIGNAL(out_SPR_WRITE_STATUS_DATA     ,_param->_nb_ooo_engine,_param->_nb_spr_write,1  );
 
-    DELETE2_SIGNAL( in_INSERT_ROB_VAL   ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
-    DELETE2_SIGNAL(out_INSERT_ROB_ACK   ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
-    DELETE2_SIGNAL( in_INSERT_ROB_RD_USE,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
-    DELETE2_SIGNAL( in_INSERT_ROB_RE_USE,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
+    DELETE2_SIGNAL( in_INSERT_ROB_VAL            ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
+    DELETE2_SIGNAL(out_INSERT_ROB_ACK            ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
+    DELETE2_SIGNAL( in_INSERT_ROB_RD_USE         ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
+    DELETE2_SIGNAL( in_INSERT_ROB_RE_USE         ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
 
-    DELETE2_SIGNAL(out_INSERT_ROB_GPR_STATUS_VAL,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
-    DELETE2_SIGNAL( in_INSERT_ROB_GPR_STATUS_ACK,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
+    DELETE2_SIGNAL(out_INSERT_ROB_GPR_STATUS_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
+    DELETE2_SIGNAL( in_INSERT_ROB_GPR_STATUS_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
+    DELETE2_SIGNAL(out_INSERT_ROB_GPR_STATUS_DATA,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
 
-    DELETE2_SIGNAL(out_INSERT_ROB_SPR_STATUS_VAL,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
-    DELETE2_SIGNAL( in_INSERT_ROB_SPR_STATUS_ACK,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
+    DELETE2_SIGNAL(out_INSERT_ROB_SPR_STATUS_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
+    DELETE2_SIGNAL( in_INSERT_ROB_SPR_STATUS_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
+    DELETE2_SIGNAL(out_INSERT_ROB_SPR_STATUS_DATA,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob [it1],1);
       }
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_write_status.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_write_status.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_write_status.cpp	(revision 128)
@@ -38,4 +38,7 @@
 	      {
 		Tcontrol_t id = (i == ooo_engine_id)?1:0;
+
+                log_printf(TRACE,Register_unit_Glue,FUNCTION,"  * GPR_WRITE_STATUS_VAL [%d (%d)][%d] : %d (%d and %d)",i, ooo_engine_id,j,id and status_val, id, status_val);
+
 		PORT_WRITE(out_GPR_WRITE_STATUS_VAL       [i][j], (id and status_val));
 	      }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_insert.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_insert.cpp	(revision 128)
@@ -46,18 +46,17 @@
                                        gpr_status_ack);
 
-          log_printf(TRACE,OOO_Engine_Glue,FUNCTION,"  * insert_rob [%d][%d]",i,j);
-          log_printf(TRACE,OOO_Engine_Glue,FUNCTION,"    * val            (r) : %d",val           );
-          log_printf(TRACE,OOO_Engine_Glue,FUNCTION,"    * ack            (w) : %d",ack           );
-          log_printf(TRACE,OOO_Engine_Glue,FUNCTION,"    * gpr_use (rd)   (r) : %d",gpr_use       );
-          log_printf(TRACE,OOO_Engine_Glue,FUNCTION,"    * gpr_status_val (w) : %d",gpr_status_val);
-          log_printf(TRACE,OOO_Engine_Glue,FUNCTION,"    * gpr_status_ack (r) : %d",gpr_status_ack);
-          log_printf(TRACE,OOO_Engine_Glue,FUNCTION,"    * spr_use (re)   (r) : %d",spr_use       );
-          log_printf(TRACE,OOO_Engine_Glue,FUNCTION,"    * spr_status_val (w) : %d",spr_status_val);
-          log_printf(TRACE,OOO_Engine_Glue,FUNCTION,"    * spr_status_ack (r) : %d",spr_status_ack);
+          log_printf(TRACE,Register_unit_Glue,FUNCTION,"  * insert_rob [%d][%d]",i,j);
+          log_printf(TRACE,Register_unit_Glue,FUNCTION,"    * val            (r) : %d",val           );
+          log_printf(TRACE,Register_unit_Glue,FUNCTION,"    * ack            (w) : %d",ack           );
+          log_printf(TRACE,Register_unit_Glue,FUNCTION,"    * gpr_use (rd)   (r) : %d",gpr_use       );
+          log_printf(TRACE,Register_unit_Glue,FUNCTION,"    * gpr_status_val (w) : %d",gpr_status_val);
+          log_printf(TRACE,Register_unit_Glue,FUNCTION,"    * gpr_status_ack (r) : %d",gpr_status_ack);
+          log_printf(TRACE,Register_unit_Glue,FUNCTION,"    * spr_use (re)   (r) : %d",spr_use       );
+          log_printf(TRACE,Register_unit_Glue,FUNCTION,"    * spr_status_val (w) : %d",spr_status_val);
+          log_printf(TRACE,Register_unit_Glue,FUNCTION,"    * spr_status_ack (r) : %d",spr_status_ack);
 
           PORT_WRITE(out_INSERT_ROB_ACK            [i][j], ack           );
           PORT_WRITE(out_INSERT_ROB_GPR_STATUS_VAL [i][j], gpr_status_val);
           PORT_WRITE(out_INSERT_ROB_SPR_STATUS_VAL [i][j], spr_status_val);
-
         }
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read.cpp	(revision 128)
@@ -1,2 +1,3 @@
+
 #ifdef SYSTEMC
 //#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp	(revision 128)
@@ -21,4 +21,10 @@
   morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
 #endif
+
+  _model.set_model(NAME_Register_unit            ,MODEL_SYSTEMC, true);
+  _model.set_model(NAME_RegisterFile             ,MODEL_SYSTEMC, true);
+  _model.set_model(NAME_RegisterFile_Monolithic  ,MODEL_SYSTEMC, true);
+  _model.set_model(NAME_RegisterFile_Multi_Banked,MODEL_SYSTEMC, true);
+  _model.set_model(NAME_Register_unit_Glue       ,MODEL_SYSTEMC, true);
 
   Tusage_t _usage = USE_ALL;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_allocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_allocation.cpp	(revision 128)
@@ -292,58 +292,64 @@
      
     // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-    std::string name_component;
+    std::string src,dest;
     
     for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
       {
-	name_component = _name+"_gpr_"+toString(i);
+	src = _name+"_gpr_"+toString(i);
 	
-        log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),name_component.c_str());
+        log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),src.c_str());
 	
-#ifdef POSITION
-	_component->interface_map (name_component,"",
-				   _name         ,"");
-#endif
-	
-	_component->port_map(name_component,"in_CLOCK"   , _name, "in_CLOCK");
-	_component->port_map(name_component,"in_NRESET"  , _name, "in_NRESET");
+        {
+          dest = _name;
+#ifdef POSITION
+          _component->interface_map (src ,"",
+                                     dest,"");
+#endif
+          PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
+          PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
+        }
 
 	for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
 	  {
-	    _component->port_map(name_component,
-				 "in_READ_"+toString(j)+"_VAL",
-				 _name+"_glue",
-				 "out_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL");
-	    _component->port_map(name_component,
-				 "out_READ_"+toString(j)+"_ACK",
-				 _name+"_glue",
-				 "in_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK");
-	    _component->port_map(name_component,
-				 "out_READ_"+toString(j)+"_DATA",
-				 _name+"_glue",
-				 "in_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_DATA");
-	    _component->port_map(name_component,
-				 "in_READ_"+toString(j)+"_ADDRESS",
-				 _name,
-				 "in_GPR_READ_"+toString(j)+"_NUM_REG");
+            dest = _name+"_glue";
+            
+#ifdef POSITION
+            _component->interface_map (src ,    "read_"+toString(j),
+                                       dest,"gpr_read_registerfile_"+toString(i)+"_"+toString(j));
+#endif
+
+	    COMPONENT_MAP(_component,src , "in_READ_"                                 +toString(j)+"_VAL",
+                                     dest,"out_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL");
+	    COMPONENT_MAP(_component,src ,"out_READ_"                                 +toString(j)+"_ACK",
+                                     dest, "in_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK");
+	    COMPONENT_MAP(_component,src ,"out_READ_"                                 +toString(j)+"_DATA",
+                                     dest, "in_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_DATA");
+
+            dest = _name;
+
+	    PORT_MAP     (_component,src , "in_READ_"    +toString(j)+"_ADDRESS",
+                                     dest, "in_GPR_READ_"+toString(j)+"_NUM_REG");
 	  }
+
 	for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
 	  {
-	    _component->port_map(name_component,
-				 "in_WRITE_"+toString(j)+"_VAL",
-				 _name+"_glue",
-				 "out_GPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL");
-	    _component->port_map(name_component,
-				 "out_WRITE_"+toString(j)+"_ACK",
-				 _name+"_glue",
-				 "in_GPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK");
-	    _component->port_map(name_component,
-				 "in_WRITE_"+toString(j)+"_ADDRESS",
-				 _name,
-				 "in_GPR_WRITE_"+toString(j)+"_NUM_REG"
-				 );
-	    _component->port_map(name_component,
-				 "in_WRITE_"+toString(j)+"_DATA",
-				 _name,
-				 "in_GPR_WRITE_"+toString(j)+"_DATA");
+            dest = _name+"_glue";
+            
+#ifdef POSITION
+            _component->interface_map (src ,    "write_"+toString(j),
+                                       dest,"gpr_write_registerfile_"+toString(i)+"_"+toString(j));
+#endif
+
+	    COMPONENT_MAP(_component,src , "in_WRITE_"                                 +toString(j)+"_VAL",
+                                     dest,"out_GPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL");
+	    COMPONENT_MAP(_component,src ,"out_WRITE_"                                 +toString(j)+"_ACK",
+                                     dest, "in_GPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK");
+
+            dest = _name;
+
+	    PORT_MAP     (_component,src , "in_WRITE_"    +toString(j)+"_ADDRESS",
+                                     dest, "in_GPR_WRITE_"+toString(j)+"_NUM_REG");
+	    PORT_MAP     (_component,src , "in_WRITE_"    +toString(j)+"_DATA",
+                                     dest, "in_GPR_WRITE_"+toString(j)+"_DATA");
 	  }
 
@@ -353,34 +359,38 @@
       for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
 	{
-	  name_component = _name+"_gpr_status_"+toString(i);
+	  src = _name+"_gpr_status_"+toString(i);
 	  
-	  log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),name_component.c_str());
-	  
-#ifdef POSITION
-	  _component->interface_map (name_component,"",
-				     _name         ,"");
-#endif
-	  
-	  _component->port_map(name_component,"in_CLOCK" , _name, "in_CLOCK");
-	  _component->port_map(name_component,"in_NRESET", _name, "in_NRESET");
-	  
+	  log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),src.c_str());
+
+          {
+            dest = _name;
+#ifdef POSITION
+            _component->interface_map (src ,"",
+                                       dest,"");
+#endif
+            PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
+            PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
+          }
+          
 	  for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
 	    {
-	      _component->port_map(name_component,
-				   "in_READ_"+toString(j)+"_VAL" ,
-				   _name+"_glue",
-				   "out_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_VAL"        );
-	      _component->port_map(name_component,
-				   "out_READ_"+toString(j)+"_ACK",
-				   _name+"_glue",
-				   "in_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK" );
-	      _component->port_map(name_component,
-				   "out_READ_"+toString(j)+"_DATA",
-				   _name+"_glue",
-				   "in_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_DATA_VAL"   );
-	      _component->port_map(name_component,
-				   "in_READ_"+toString(j)+"_ADDRESS",
-				   _name,
-				   "in_GPR_READ_"+toString(j)+"_NUM_REG");
+              dest = _name+"_glue";
+              
+#ifdef POSITION
+              _component->interface_map (src ,    "read_"+toString(j),
+                                         dest,"gpr_read_status_"+toString(i)+"_"+toString(j));
+#endif
+
+	      COMPONENT_MAP(_component,src , "in_READ_"                           +toString(j)+"_VAL",
+                                       dest,"out_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_VAL");
+	      COMPONENT_MAP(_component,src ,"out_READ_"                           +toString(j)+"_ACK",
+                                       dest, "in_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK");
+	      COMPONENT_MAP(_component,src ,"out_READ_"                           +toString(j)+"_DATA",
+                                       dest, "in_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_DATA_VAL");
+
+              dest = _name;
+              
+              PORT_MAP     (_component,src , "in_READ_"    +toString(j)+"_ADDRESS",
+                                       dest, "in_GPR_READ_"+toString(j)+"_NUM_REG");
 	    }
 
@@ -388,107 +398,51 @@
 	  for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
 	    {
-	      _component->port_map(name_component,
-				   "in_WRITE_"+toString(x)+"_VAL" ,
-				   _name+"_glue",
-				   "out_GPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_VAL");
-	      _component->port_map(name_component,
-				   "out_WRITE_"+toString(x)+"_ACK",
-				   _name+"_glue",
-				   "in_GPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK" );
-	      _component->port_map(name_component,
-				   "in_WRITE_"+toString(x)+"_DATA" ,
-				   _name+"_glue",
-				   "out_CONST_1");
-
-	      _component->port_map(_name+"_glue",
-				   "out_CONST_1",
-				   name_component,
-				   "in_WRITE_"+toString(x)+"_DATA" );
-
-
-	      _component->port_map(name_component,
-				   "in_WRITE_"+toString(x++)+"_ADDRESS",
-				   _name,
-				   "in_GPR_WRITE_"+toString(j)+"_NUM_REG");
+              dest = _name+"_glue";
+              
+#ifdef POSITION
+              _component->interface_map (src ,    "write_"+toString(j),
+                                         dest,"gpr_write_status_"+toString(i)+"_"+toString(j));
+#endif
+
+              COMPONENT_MAP(_component,src , "in_WRITE_"                           +toString(x)+"_VAL",
+                                       dest,"out_GPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_VAL");
+              COMPONENT_MAP(_component,src ,"out_WRITE_"                           +toString(x)+"_ACK",
+                                       dest, "in_GPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK");
+              COMPONENT_MAP(_component,src , "in_WRITE_"                           +toString(x)+"_DATA",
+                                       dest,"out_GPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_DATA");
+//                                     dest,"out_CONST_1");
+              
+              dest = _name;
+              
+              PORT_MAP     (_component,src , "in_WRITE_"    +toString(x)+"_ADDRESS",
+                                       dest, "in_GPR_WRITE_"+toString(j)+"_NUM_REG");
+
+              x++;
 	    }
 	  
 	  for (uint32_t j=0; j<_param->_nb_inst_insert_rob [i]; j++)
 	    {
-	      _component->port_map(name_component,
-				   "in_WRITE_"+toString(x)+"_VAL" ,
-				   _name+"_glue",
-				   "out_INSERT_ROB_GPR_STATUS_"+toString(i)+"_"+toString(j)+"_VAL");
-	      _component->port_map(name_component,
-				   "out_WRITE_"+toString(x)+"_ACK",
-				   _name+"_glue",
-				   "in_INSERT_ROB_GPR_STATUS_"+toString(i)+"_"+toString(j)+"_ACK" );
-
-	      _component->port_map(name_component,
-				   "in_WRITE_"+toString(x)+"_DATA",
-				    _name+"_glue",
-				   "out_CONST_0"
-				   );
-	      _component->port_map( _name+"_glue",
-				    "out_CONST_0",
-				    name_component,
-				   "in_WRITE_"+toString(x)+"_DATA");
-
-	      _component->port_map(name_component,
-				   "in_WRITE_"+toString(x++)+"_ADDRESS",
-				   _name,
-				   "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RD_NUM_REG");
-
+              dest = _name+"_glue";
+              
+#ifdef POSITION
+              _component->interface_map (src ,    "write_"+toString(j),
+                                         dest,"insert_rob_gpr_status_"+toString(i)+"_"+toString(j));
+#endif
+
+              COMPONENT_MAP(_component,src , "in_WRITE_"                                +toString(x)+"_VAL",
+                                       dest,"out_INSERT_ROB_GPR_STATUS_"+toString(i)+"_"+toString(j)+"_VAL");
+              COMPONENT_MAP(_component,src ,"out_WRITE_"                                +toString(x)+"_ACK",
+                                       dest, "in_INSERT_ROB_GPR_STATUS_"+toString(i)+"_"+toString(j)+"_ACK");
+              COMPONENT_MAP(_component,src , "in_WRITE_"                                +toString(x)+"_DATA",
+                                       dest,"out_INSERT_ROB_GPR_STATUS_"+toString(i)+"_"+toString(j)+"_DATA");
+//                                     dest,"out_CONST_0");
+              
+              dest = _name;
+              
+              PORT_MAP     (_component,src , "in_WRITE_"                     +toString(x)+"_ADDRESS",
+                                       dest, "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RD_NUM_REG");
+
+              x++;
 	    }
-
-// 	  for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++)
-// 	    {
-// 	      _component->port_map(name_component,
-// 				   "in_WRITE_"+toString(x)+"_VAL" ,
-// 				   _name+"_glue",
-// 				   "out_RETIRE_ROB_GPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_VAL");
-// 	      _component->port_map(name_component,
-// 				   "out_WRITE_"+toString(x)+"_ACK",
-// 				   _name+"_glue",
-// 				   "in_RETIRE_ROB_GPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_ACK" );
-
-// 	      _component->port_map(name_component,
-// 				   "in_WRITE_"+toString(x)+"_DATA" ,
-// 				   _name+"_glue",
-// 				   "out_CONST_0");
-// 	      _component->port_map(_name+"_glue",
-// 				   "out_CONST_0",
-// 				   name_component,
-// 				   "in_WRITE_"+toString(x)+"_DATA" );
-
-// 	      _component->port_map(name_component,
-// 				   "in_WRITE_"+toString(x++)+"_ADDRESS",
-// 				   _name,
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_NUM_REG");
-	      
-// 	      _component->port_map(name_component,
-// 				   "in_WRITE_"+toString(x)+"_VAL" ,
-// 				   _name+"_glue",
-// 				   "out_RETIRE_ROB_GPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_VAL");
-// 	      _component->port_map(name_component,
-// 				   "out_WRITE_"+toString(x)+"_ACK",
-// 				   _name+"_glue",
-// 				   "in_RETIRE_ROB_GPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_ACK" );
-
-// 	      _component->port_map(name_component,
-// 				   "in_WRITE_"+toString(x)+"_DATA" ,
-// 				   _name+"_glue",
-// 				   "out_CONST_1"
-// 				   );
-// 	      _component->port_map(_name+"_glue",
-// 				   "out_CONST_1",
-// 				   name_component,
-// 				   "in_WRITE_"+toString(x)+"_DATA"
-// 				   );
-
-// 	      _component->port_map(name_component,
-// 				   "in_WRITE_"+toString(x++)+"_ADDRESS",
-// 				   _name,
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_NUM_REG");
-// 	    }
 
 	}
@@ -497,54 +451,60 @@
     for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
       {
-	name_component = _name+"_spr_"+toString(i);
+	src = _name+"_spr_"+toString(i);
 	
-	log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),name_component.c_str());
+	log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),src.c_str());
 	
-#ifdef POSITION
-	_component->interface_map (name_component,"",
-				   _name         ,"");
-#endif
-	
-	_component->port_map(name_component,"in_CLOCK" , _name, "in_CLOCK");
-	_component->port_map(name_component,"in_NRESET", _name, "in_NRESET");
+        {
+          dest = _name;
+#ifdef POSITION
+          _component->interface_map (src ,"",
+                                     dest,"");
+#endif
+          PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
+          PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
+        }
 
 	for (uint32_t j=0; j<_param->_nb_spr_read; j++)
 	  {
-	    _component->port_map(name_component,
-				 "in_READ_"+toString(j)+"_VAL",
-				 _name+"_glue",
-				 "out_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL");
-	    _component->port_map(name_component,
-				 "out_READ_"+toString(j)+"_ACK",
-				 _name+"_glue",
-				 "in_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK");
-	    _component->port_map(name_component,
-				 "out_READ_"+toString(j)+"_DATA",
-				 _name+"_glue",
-				 "in_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_DATA");
-	    _component->port_map(name_component,
-				 "in_READ_"+toString(j)+"_ADDRESS",
-				 _name,
-				 "in_SPR_READ_"+toString(j)+"_NUM_REG");
+            dest = _name+"_glue";
+            
+#ifdef POSITION
+            _component->interface_map (src ,    "read_"+toString(j),
+                                       dest,"spr_read_registerfile_"+toString(i)+"_"+toString(j));
+#endif
+
+	    COMPONENT_MAP(_component,src , "in_READ_"                                 +toString(j)+"_VAL",
+                                     dest,"out_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL");
+	    COMPONENT_MAP(_component,src ,"out_READ_"                                 +toString(j)+"_ACK",
+                                     dest, "in_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK");
+	    COMPONENT_MAP(_component,src ,"out_READ_"                                 +toString(j)+"_DATA",
+                                     dest, "in_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_DATA");
+
+            dest = _name;
+
+	    PORT_MAP     (_component,src , "in_READ_"    +toString(j)+"_ADDRESS",
+                                     dest, "in_SPR_READ_"+toString(j)+"_NUM_REG");
 	  }
+
 	for (uint32_t j=0; j<_param->_nb_spr_write; j++)
 	  {
-	    _component->port_map(name_component,
-				 "in_WRITE_"+toString(j)+"_VAL",
-				 _name+"_glue",
-				 "out_SPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL");
-	    _component->port_map(name_component,
-				 "out_WRITE_"+toString(j)+"_ACK",
-				 _name+"_glue",
-				 "in_SPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK");
-	    _component->port_map(name_component,
-				 "in_WRITE_"+toString(j)+"_ADDRESS",
-				 _name,
-				 "in_SPR_WRITE_"+toString(j)+"_NUM_REG"
-				 );
-	    _component->port_map(name_component,
-				 "in_WRITE_"+toString(j)+"_DATA",
-				 _name,
-				 "in_SPR_WRITE_"+toString(j)+"_DATA");
+            dest = _name+"_glue";
+            
+#ifdef POSITION
+            _component->interface_map (src ,    "write_"+toString(j),
+                                       dest,"spr_write_registerfile_"+toString(i)+"_"+toString(j));
+#endif
+
+	    COMPONENT_MAP(_component,src , "in_WRITE_"                                 +toString(j)+"_VAL",
+                                     dest,"out_SPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL");
+	    COMPONENT_MAP(_component,src ,"out_WRITE_"                                 +toString(j)+"_ACK",
+                                     dest, "in_SPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK");
+
+            dest = _name;
+
+	    PORT_MAP     (_component,src , "in_WRITE_"    +toString(j)+"_ADDRESS",
+                                     dest, "in_SPR_WRITE_"+toString(j)+"_NUM_REG");
+	    PORT_MAP     (_component,src , "in_WRITE_"    +toString(j)+"_DATA",
+                                     dest, "in_SPR_WRITE_"+toString(j)+"_DATA");
 	  }
 
@@ -554,34 +514,38 @@
       for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
 	{
-	  name_component = _name+"_spr_status_"+toString(i);
+	  src = _name+"_spr_status_"+toString(i);
 	  
-	  log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),name_component.c_str());	
+	  log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),src.c_str());	
   
-#ifdef POSITION
-	  _component->interface_map (name_component,"",
-				     _name         ,"");
-#endif
-	  
-	  _component->port_map(name_component,"in_CLOCK" , _name, "in_CLOCK");
-	  _component->port_map(name_component,"in_NRESET", _name, "in_NRESET");
-	  
+          {
+            dest = _name;
+#ifdef POSITION
+            _component->interface_map (src ,"",
+                                       dest,"");
+#endif
+            PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
+            PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
+          }
+
 	  for (uint32_t j=0; j<_param->_nb_spr_read; j++)
 	    {
-	      _component->port_map(name_component,
-				   "in_READ_"+toString(j)+"_VAL" ,
-				   _name+"_glue",
-				   "out_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_VAL"        );
-	      _component->port_map(name_component,
-				   "out_READ_"+toString(j)+"_ACK",
-				   _name+"_glue",
-				   "in_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK" );
-	      _component->port_map(name_component,
-				   "out_READ_"+toString(j)+"_DATA",
-				   _name+"_glue",
-				   "in_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_DATA_VAL"   );
-	      _component->port_map(name_component,
-				   "in_READ_"+toString(j)+"_ADDRESS",
-				   _name,
-				   "in_SPR_READ_"+toString(j)+"_NUM_REG");
+              dest = _name+"_glue";
+              
+#ifdef POSITION
+              _component->interface_map (src ,    "read_"+toString(j),
+                                         dest,"spr_read_status_"+toString(i)+"_"+toString(j));
+#endif
+
+	      COMPONENT_MAP(_component,src , "in_READ_"                           +toString(j)+"_VAL",
+                                       dest,"out_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_VAL");
+	      COMPONENT_MAP(_component,src ,"out_READ_"                           +toString(j)+"_ACK",
+                                       dest, "in_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK");
+	      COMPONENT_MAP(_component,src ,"out_READ_"                           +toString(j)+"_DATA",
+                                       dest, "in_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_DATA_VAL");
+
+              dest = _name;
+              
+              PORT_MAP     (_component,src , "in_READ_"    +toString(j)+"_ADDRESS",
+                                       dest, "in_SPR_READ_"+toString(j)+"_NUM_REG");
 	    }
 
@@ -589,108 +553,52 @@
 	  for (uint32_t j=0; j<_param->_nb_spr_write; j++)
 	    {
-	      _component->port_map(name_component,
-				   "in_WRITE_"+toString(x)+"_VAL" ,
-				   _name+"_glue",
-				   "out_SPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_VAL");
-	      _component->port_map(name_component,
-				   "out_WRITE_"+toString(x)+"_ACK",
-				   _name+"_glue",
-				   "in_SPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK" );
-	      _component->port_map(name_component,
-				   "in_WRITE_"+toString(x)+"_DATA" ,
-				   _name+"_glue",
-				   "out_CONST_1");
-	      _component->port_map(_name+"_glue",
-				   "out_CONST_1",
-				   name_component,
-				   "in_WRITE_"+toString(x)+"_DATA"
-				   );
-
-	      _component->port_map(name_component,
-				   "in_WRITE_"+toString(x++)+"_ADDRESS",
-				   _name,
-				   "in_SPR_WRITE_"+toString(j)+"_NUM_REG");
+              dest = _name+"_glue";
+              
+#ifdef POSITION
+              _component->interface_map (src ,    "write_"+toString(j),
+                                         dest,"spr_write_status_"+toString(i)+"_"+toString(j));
+#endif
+
+              COMPONENT_MAP(_component,src , "in_WRITE_"                           +toString(x)+"_VAL",
+                                       dest,"out_SPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_VAL");
+              COMPONENT_MAP(_component,src ,"out_WRITE_"                           +toString(x)+"_ACK",
+                                       dest, "in_SPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK");
+              COMPONENT_MAP(_component,src , "in_WRITE_"                           +toString(x)+"_DATA",
+                                       dest,"out_SPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_DATA");
+//                                     dest,"out_CONST_1");
+              
+              dest = _name;
+              
+              PORT_MAP     (_component,src , "in_WRITE_"    +toString(x)+"_ADDRESS",
+                                       dest, "in_SPR_WRITE_"+toString(j)+"_NUM_REG");
+
+              x++;
 	    }
 	  
 	  for (uint32_t j=0; j<_param->_nb_inst_insert_rob [i]; j++)
 	    {
-	      _component->port_map(name_component,
-				   "in_WRITE_"+toString(x)+"_VAL" ,
-				   _name+"_glue",
-				   "out_INSERT_ROB_SPR_STATUS_"+toString(i)+"_"+toString(j)+"_VAL");
-	      _component->port_map(name_component,
-				   "out_WRITE_"+toString(x)+"_ACK",
-				   _name+"_glue",
-				   "in_INSERT_ROB_SPR_STATUS_"+toString(i)+"_"+toString(j)+"_ACK" );
-
-	      _component->port_map(name_component,
-				   "in_WRITE_"+toString(x)+"_DATA",
-				    _name+"_glue",
-				   "out_CONST_0"
-				   );
-	      _component->port_map( _name+"_glue",
-				    "out_CONST_0",
-				   name_component,
-				   "in_WRITE_"+toString(x)+"_DATA"
-				   );
-
-	      _component->port_map(name_component,
-				   "in_WRITE_"+toString(x++)+"_ADDRESS",
-				   _name,
-				   "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RE_NUM_REG");
-
+              dest = _name+"_glue";
+              
+#ifdef POSITION
+              _component->interface_map (src ,    "write_"+toString(j),
+                                         dest,"insert_rob_spr_status_"+toString(i)+"_"+toString(j));
+#endif
+
+              COMPONENT_MAP(_component,src , "in_WRITE_"                                +toString(x)+"_VAL",
+                                       dest,"out_INSERT_ROB_SPR_STATUS_"+toString(i)+"_"+toString(j)+"_VAL");
+              COMPONENT_MAP(_component,src ,"out_WRITE_"                                +toString(x)+"_ACK",
+                                       dest, "in_INSERT_ROB_SPR_STATUS_"+toString(i)+"_"+toString(j)+"_ACK");
+              COMPONENT_MAP(_component,src , "in_WRITE_"                                +toString(x)+"_DATA",
+                                       dest,"out_INSERT_ROB_SPR_STATUS_"+toString(i)+"_"+toString(j)+"_DATA");
+//                                     dest,"out_CONST_0");
+              
+              dest = _name;
+              
+              PORT_MAP     (_component,src , "in_WRITE_"                     +toString(x)+"_ADDRESS",
+                                       dest, "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RE_NUM_REG");
+
+              x++;
 	    }
 
-// 	  for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++)
-// 	    {
-// 	      _component->port_map(name_component,
-// 				   "in_WRITE_"+toString(x)+"_VAL" ,
-// 				   _name+"_glue",
-// 				   "out_RETIRE_ROB_SPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_VAL");
-// 	      _component->port_map(name_component,
-// 				   "out_WRITE_"+toString(x)+"_ACK",
-// 				   _name+"_glue",
-// 				   "in_RETIRE_ROB_SPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_ACK" );
-
-// 	      _component->port_map(name_component,
-// 				   "in_WRITE_"+toString(x)+"_DATA" ,
-// 				   _name+"_glue",
-// 				   "out_CONST_0");
-// 	      _component->port_map(_name+"_glue",
-// 				   "out_CONST_0",
-// 				   name_component,
-// 				   "in_WRITE_"+toString(x)+"_DATA"
-// 				   );
-
-// 	      _component->port_map(name_component,
-// 				   "in_WRITE_"+toString(x++)+"_ADDRESS",
-// 				   _name,
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_NUM_REG");
-	      
-// 	      _component->port_map(name_component,
-// 				   "in_WRITE_"+toString(x)+"_VAL" ,
-// 				   _name+"_glue",
-// 				   "out_RETIRE_ROB_SPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_VAL");
-// 	      _component->port_map(name_component,
-// 				   "out_WRITE_"+toString(x)+"_ACK",
-// 				   _name+"_glue",
-// 				   "in_RETIRE_ROB_SPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_ACK" );
-
-// 	      _component->port_map(name_component,
-// 				   "in_WRITE_"+toString(x)+"_DATA" ,
-// 				   _name+"_glue",
-// 				   "out_CONST_1"
-// 				   );
-// 	      _component->port_map(_name+"_glue",
-// 				   "out_CONST_1",
-// 				   name_component,
-// 				   "in_WRITE_"+toString(x)+"_DATA"
-// 				   );
-
-// 	      _component->port_map(name_component,
-// 				   "in_WRITE_"+toString(x++)+"_ADDRESS",
-// 				   _name,
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_NUM_REG");
-// 	    }
 
 	}
@@ -698,308 +606,157 @@
 
     {
-      name_component = _name+"_glue";
+      src = _name+"_glue";
      
-      log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),name_component.c_str());  
+      log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),src.c_str());  
    
-#ifdef POSITION
-      _component->interface_map (name_component,"",
-				 _name         ,"");
-#endif
-    
-      _component->port_map(name_component,"in_CLOCK" , _name, "in_CLOCK" );
-      _component->port_map(name_component,"in_NRESET", _name, "in_NRESET");
-//       _component->port_map(name_component,"out_CONST_0",_name,"out_CONST_0");
-//       _component->port_map(name_component,"out_CONST_1",_name,"out_CONST_1");
+        {
+          dest = _name;
+#ifdef POSITION
+          _component->interface_map (src ,"",
+                                     dest,"");
+#endif
+          PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
+          PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
+        }
 
       for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
 	{
-	  _component->port_map(name_component,
-			       "in_GPR_READ_"+toString(j)+"_VAL",
-			       _name, 
-			       "in_GPR_READ_"+toString(j)+"_VAL");
-	  _component->port_map(name_component,
-			       "out_GPR_READ_"+toString(j)+"_ACK",
-			       _name,
-			       "out_GPR_READ_"+toString(j)+"_ACK"           );
+          dest = _name;
+              
+#ifdef POSITION
+          _component->interface_map (src ,"gpr_read_"+toString(j),
+                                     dest,"gpr_read_"+toString(j));
+#endif
+
+          PORT_MAP(_component,src , "in_GPR_READ_"+toString(j)+"_VAL",
+                              dest, "in_GPR_READ_"+toString(j)+"_VAL");
+          PORT_MAP(_component,src ,"out_GPR_READ_"+toString(j)+"_ACK",
+                              dest,"out_GPR_READ_"+toString(j)+"_ACK");
 	  if (_param->_have_port_ooo_engine_id == true)
-	    _component->port_map(name_component,
-				 "in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID" , 
-				 _name,
-				 "in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID");
-	  _component->port_map(name_component,
-			       "out_GPR_READ_"+toString(j)+"_DATA"          , 
-			       _name,
-			       "out_GPR_READ_"+toString(j)+"_DATA");
-	  _component->port_map(name_component,
-			       "out_GPR_READ_"+toString(j)+"_DATA_VAL"      , 
-			       _name,
-			       "out_GPR_READ_"+toString(j)+"_DATA_VAL");
-
-	  for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
-	    {
-	      _component->port_map(name_component ,
-				   "out_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL",
-				   _name+"_gpr_"+toString(i),
-				   "in_READ_"+toString(j)+"_VAL"  );
-	      _component->port_map(name_component,
-				   "in_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK"  ,
-				   _name+"_gpr_"+toString(i),
-				   "out_READ_"+toString(j)+"_ACK" );
-	      _component->port_map(name_component,
-				   "in_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_DATA" ,
-				   _name+"_gpr_"+toString(i),
-				   "out_READ_"+toString(j)+"_DATA");
-	      _component->port_map(name_component,
-				   "out_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_VAL"        ,
-				   _name+"_gpr_status_"+toString(i),
-				   "in_READ_"+toString(j)+"_VAL" );
-	      _component->port_map(name_component,
-				   "in_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK" ,
-				   _name+"_gpr_status_"+toString(i),
-				   "out_READ_"+toString(j)+"_ACK");
-	      _component->port_map(name_component,
-				   "in_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_DATA_VAL"   ,
-				   _name+"_gpr_status_"+toString(i),
-				   "out_READ_"+toString(j)+"_DATA");
-	    }
+          PORT_MAP(_component,src , "in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID",
+                              dest, "in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID");
+          PORT_MAP(_component,src ,"out_GPR_READ_"+toString(j)+"_DATA",
+                              dest,"out_GPR_READ_"+toString(j)+"_DATA");
+          PORT_MAP(_component,src ,"out_GPR_READ_"+toString(j)+"_DATA_VAL",
+                              dest,"out_GPR_READ_"+toString(j)+"_DATA_VAL");
+
+          // out_GPR_READ_REGISTERFILE_VAL   - gpr. in_READ_VAL
+          //  in_GPR_READ_REGISTERFILE_ACK   - gpr.out_READ_ACK
+          //  in_GPR_READ_REGISTERFILE_DATA  - gpr.out_READ_DATA
+          
+          // out_GPR_READ_STATUS_VAL         - gpr. in_READ_VAL
+          //  in_GPR_READ_STATUS_ACK         - gpr.out_READ_ACK
+          //  in_GPR_READ_STATUS_DATA_VAL    - gpr.out_READ_DATA
 	}
 
       for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
 	{
-	  _component->port_map(name_component,
-			       "in_GPR_WRITE_"+toString(j)+"_VAL",
-			       _name, 
-			       "in_GPR_WRITE_"+toString(j)+"_VAL"           );
-	  _component->port_map(name_component,
-			       "out_GPR_WRITE_"+toString(j)+"_ACK", 
-			       _name,
-			       "out_GPR_WRITE_"+toString(j)+"_ACK"           );
+          dest = _name;
+
+#ifdef POSITION
+          _component->interface_map (src ,"gpr_write_"+toString(j),
+                                     dest,"gpr_write_"+toString(j));
+#endif
+
+          PORT_MAP(_component,src , "in_GPR_WRITE_"+toString(j)+"_VAL",
+                              dest, "in_GPR_WRITE_"+toString(j)+"_VAL");
+          PORT_MAP(_component,src ,"out_GPR_WRITE_"+toString(j)+"_ACK",
+                              dest,"out_GPR_WRITE_"+toString(j)+"_ACK");
 	  if (_param->_have_port_ooo_engine_id == true)
-	    _component->port_map(name_component,
-				 "in_GPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID", 
-				 _name,
-				 "in_GPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID" );
-	  
-	  for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+          PORT_MAP(_component,src , "in_GPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID",
+                              dest, "in_GPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID");
+
+          // out_GPR_WRITE_REGISTERFILE_VAL - gpr. in_WRITE_VAL
+          //  in_GPR_WRITE_REGISTERFILE_ACK - gpr.out_WRITE_ACK
+          // out_GPR_WRITE_STATUS_VAL       - gpr. in_WRITE_VAL
+          //  in_GPR_WRITE_STATUS_ACK       - gpr.out_WRITE_ACK
+          // out_GPR_WRITE_STATUS_DATA      - gpr. in_WRITE_DATA
+	}
+
+      for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+	{
+          dest = _name;
+              
+#ifdef POSITION
+          _component->interface_map (src ,"spr_read_"+toString(j),
+                                     dest,"spr_read_"+toString(j));
+#endif
+
+          PORT_MAP(_component,src , "in_SPR_READ_"+toString(j)+"_VAL",
+                              dest, "in_SPR_READ_"+toString(j)+"_VAL");
+          PORT_MAP(_component,src ,"out_SPR_READ_"+toString(j)+"_ACK",
+                              dest,"out_SPR_READ_"+toString(j)+"_ACK");
+	  if (_param->_have_port_ooo_engine_id == true)
+          PORT_MAP(_component,src , "in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID",
+                              dest, "in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID");
+          PORT_MAP(_component,src ,"out_SPR_READ_"+toString(j)+"_DATA",
+                              dest,"out_SPR_READ_"+toString(j)+"_DATA");
+          PORT_MAP(_component,src ,"out_SPR_READ_"+toString(j)+"_DATA_VAL",
+                              dest,"out_SPR_READ_"+toString(j)+"_DATA_VAL");
+
+          // out_SPR_READ_REGISTERFILE_VAL   - spr. in_READ_VAL
+          //  in_SPR_READ_REGISTERFILE_ACK   - spr.out_READ_ACK
+          //  in_SPR_READ_REGISTERFILE_DATA  - spr.out_READ_DATA
+          
+          // out_SPR_READ_STATUS_VAL         - spr. in_READ_VAL
+          //  in_SPR_READ_STATUS_ACK         - spr.out_READ_ACK
+          //  in_SPR_READ_STATUS_DATA_VAL    - spr.out_READ_DATA
+	}
+
+      for (uint32_t j=0; j<_param->_nb_spr_write; j++)
+	{
+          dest = _name;
+
+#ifdef POSITION
+          _component->interface_map (src ,"spr_write_"+toString(j),
+                                     dest,"spr_write_"+toString(j));
+#endif
+
+          PORT_MAP(_component,src , "in_SPR_WRITE_"+toString(j)+"_VAL",
+                              dest, "in_SPR_WRITE_"+toString(j)+"_VAL");
+          PORT_MAP(_component,src ,"out_SPR_WRITE_"+toString(j)+"_ACK",
+                              dest,"out_SPR_WRITE_"+toString(j)+"_ACK");
+	  if (_param->_have_port_ooo_engine_id == true)
+          PORT_MAP(_component,src , "in_SPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID",
+                              dest, "in_SPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID");
+
+          // out_SPR_WRITE_REGISTERFILE_VAL - spr. in_WRITE_VAL
+          //  in_SPR_WRITE_REGISTERFILE_ACK - spr.out_WRITE_ACK
+          // out_SPR_WRITE_STATUS_VAL       - spr. in_WRITE_VAL
+          //  in_SPR_WRITE_STATUS_ACK       - spr.out_WRITE_ACK
+          // out_SPR_WRITE_STATUS_DATA      - spr. in_WRITE_DATA
+	}
+
+      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	{
+	  uint32_t x     =_param->_nb_inst_insert_rob [i];
+
+	  for (uint32_t j=0; j<x; j++)
 	    {
-	      _component->port_map(name_component,
-				   "out_GPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL"  ,
-				   _name+"_gpr_"+toString(i),
-				   "in_WRITE_"+toString(j)+"_VAL" );
-	      _component->port_map(name_component,
-				   "in_GPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK"  ,
-				   _name+"_gpr_"+toString(i),
-				   "out_WRITE_"+toString(j)+"_ACK" );
-	      _component->port_map(name_component,
-				   "out_GPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_VAL"        ,
-				   _name+"_gpr_status_"+toString(i),
-				   "in_WRITE_"+toString(j)+"_VAL" );
-	      _component->port_map(name_component,
-				   "in_GPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK"        ,
-				   _name+"_gpr_status_"+toString(i),
-				   "out_WRITE_"+toString(j)+"_ACK" );
+              dest = _name;
+
+#ifdef POSITION
+              _component->interface_map (src ,"insert_rob_"+toString(i)+"_"+toString(j),
+                                         dest,"insert_rob_"+toString(i)+"_"+toString(j));
+#endif
+
+	      PORT_MAP(_component,src , "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_VAL",
+                                  dest, "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_VAL");
+	      PORT_MAP(_component,src ,"out_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_ACK",
+                                  dest,"out_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_ACK");
+	      PORT_MAP(_component,src , "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RD_USE",
+                                  dest, "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RD_USE");
+	      PORT_MAP(_component,src , "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RE_USE",
+                                  dest, "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RE_USE");
+              
+              // out_INSERT_ROB_GPR_STATUS_VAL - gpr_status.  in_WRITE_VAL
+              //  in_INSERT_ROB_GPR_STATUS_ACK - gpr_status. out_WRITE_ACK
+              // out_INSERT_ROB_GPR_STATUS_DATA- gpr_status.  in_WRITE_DATA
+              // out_INSERT_ROB_SPR_STATUS_VAL - spr_status.  in_WRITE_VAL
+              //  in_INSERT_ROB_SPR_STATUS_ACK - spr_status. out_WRITE_ACK
+              //  in_INSERT_ROB_SPR_STATUS_DATA- spr_status. out_WRITE_DATA
 	    }
 	}
       
-      for (uint32_t j=0; j<_param->_nb_spr_read; j++)
-	{
-	  _component->port_map(name_component,
-			       "in_SPR_READ_"+toString(j)+"_VAL",
-			       _name, 
-			       "in_SPR_READ_"+toString(j)+"_VAL");
-	  _component->port_map(name_component,
-			       "out_SPR_READ_"+toString(j)+"_ACK",
-			       _name,
-			       "out_SPR_READ_"+toString(j)+"_ACK"           );
-	  if (_param->_have_port_ooo_engine_id == true)
-	    _component->port_map(name_component,
-				 "in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID" , 
-				 _name,
-				 "in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID");
-	  _component->port_map(name_component,
-			       "out_SPR_READ_"+toString(j)+"_DATA"          , 
-			       _name,
-			       "out_SPR_READ_"+toString(j)+"_DATA");
-	  _component->port_map(name_component,
-			       "out_SPR_READ_"+toString(j)+"_DATA_VAL"      , 
-			       _name,
-			       "out_SPR_READ_"+toString(j)+"_DATA_VAL");
-
-	  for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
-	    {
-	      _component->port_map(name_component ,
-				   "out_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL",
-				   _name+"_spr_"+toString(i),
-				   "in_READ_"+toString(j)+"_VAL"  );
-	      _component->port_map(name_component,
-				   "in_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK"  ,
-				   _name+"_spr_"+toString(i),
-				   "out_READ_"+toString(j)+"_ACK" );
-	      _component->port_map(name_component,
-				   "in_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_DATA" ,
-				   _name+"_spr_"+toString(i),
-				   "out_READ_"+toString(j)+"_DATA");
-	      _component->port_map(name_component,
-				   "out_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_VAL"        ,
-				   _name+"_spr_status_"+toString(i),
-				   "in_READ_"+toString(j)+"_VAL" );
-	      _component->port_map(name_component,
-				   "in_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK" ,
-				   _name+"_spr_status_"+toString(i),
-				   "out_READ_"+toString(j)+"_ACK");
-	      _component->port_map(name_component,
-				   "in_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_DATA_VAL"   ,
-				   _name+"_spr_status_"+toString(i),
-				   "out_READ_"+toString(j)+"_DATA");
-	    }
-	}
-
-      for (uint32_t j=0; j<_param->_nb_spr_write; j++)
-	{
-	  _component->port_map(name_component,
-			       "in_SPR_WRITE_"+toString(j)+"_VAL",
-			       _name, 
-			       "in_SPR_WRITE_"+toString(j)+"_VAL"           );
-	  _component->port_map(name_component,
-			       "out_SPR_WRITE_"+toString(j)+"_ACK", 
-			       _name,
-			       "out_SPR_WRITE_"+toString(j)+"_ACK"           );
-	  if (_param->_have_port_ooo_engine_id == true)
-	    _component->port_map(name_component,
-				 "in_SPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID", 
-				 _name,
-				 "in_SPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID" );
-	  
-	  for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
-	    {
-	      _component->port_map(name_component,
-				   "out_SPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL"  ,
-				   _name+"_spr_"+toString(i),
-				   "in_WRITE_"+toString(j)+"_VAL" );
-	      _component->port_map(name_component,
-				   "in_SPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK"  ,
-				   _name+"_spr_"+toString(i),
-				   "out_WRITE_"+toString(j)+"_ACK" );
-	      _component->port_map(name_component,
-				   "out_SPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_VAL"        ,
-				   _name+"_spr_status_"+toString(i),
-				   "in_WRITE_"+toString(j)+"_VAL" );
-	      _component->port_map(name_component,
-				   "in_SPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK"        ,
-				   _name+"_spr_status_"+toString(i),
-				   "out_WRITE_"+toString(j)+"_ACK" );
-	    }
-	}
-
-      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
-	{
-	  uint32_t x     =_param->_nb_inst_insert_rob [i];
-	  uint32_t gpr_j = _param->_nb_gpr_write;
-	  uint32_t spr_j = _param->_nb_spr_write;
-
-	  for (uint32_t j=0; j<x; j++)
-	    {
-	      _component->port_map(name_component,
-				   "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_VAL",
-				   _name,
-				   "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_VAL");
-	      _component->port_map(name_component,
-				   "out_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_ACK",
-				   _name,
-				   "out_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_ACK");
-	      _component->port_map(name_component,
-				   "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RD_USE",
-				   _name,
-				   "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RD_USE");
-	      _component->port_map(name_component,
-				   "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RE_USE",
-				   _name,
-				   "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RE_USE");
-	      _component->port_map(name_component,
-				   "out_INSERT_ROB_GPR_STATUS_"+toString(i)+"_"+toString(j)+"_VAL",
-				   _name+"_gpr_status_"+toString(i),
-				   "in_WRITE_"+toString(gpr_j)+"_VAL");
-	      _component->port_map(name_component,
-				   "in_INSERT_ROB_GPR_STATUS_"+toString(i)+"_"+toString(j)+"_ACK",
-				   _name+"_gpr_status_"+toString(i),
-				   "out_WRITE_"+toString(gpr_j++)+"_ACK");
-	      _component->port_map(name_component,
-				   "out_INSERT_ROB_SPR_STATUS_"+toString(i)+"_"+toString(j)+"_VAL",
-				   _name+"_spr_status_"+toString(i),
-				   "in_WRITE_"+toString(spr_j)+"_VAL");
-	      _component->port_map(name_component,
-				   "in_INSERT_ROB_SPR_STATUS_"+toString(i)+"_"+toString(j)+"_ACK",
-				   _name+"_spr_status_"+toString(i),
-				   "out_WRITE_"+toString(spr_j++)+"_ACK");
-	    }
-	}
-
-//       for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
-// 	{
-// 	  uint32_t x     =_param->_nb_inst_retire_rob [i];
-// 	  uint32_t gpr_j = _param->_nb_gpr_write + _param->_nb_inst_insert_rob [i];
-// 	  uint32_t spr_j = _param->_nb_spr_write + _param->_nb_inst_insert_rob [i];
-
-// 	  for (uint32_t j=0; j<x; j++)
-// 	    {
-// 	      _component->port_map(name_component,
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_VAL",
-// 				   _name,
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_VAL");
-// 	      _component->port_map(name_component,
-// 				   "out_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_ACK",
-// 				   _name,
-// 				   "out_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_ACK");
-// 	      _component->port_map(name_component,
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_USE",
-// 				   _name,
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_USE");
-// 	      _component->port_map(name_component,
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_USE",
-// 				   _name,
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_USE");
-// 	      _component->port_map(name_component,
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_USE",
-// 				   _name, 
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_USE");
-// 	      _component->port_map(name_component,
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_USE",
-// 				   _name,
-// 				   "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_USE");
-	    
-// 	      _component->port_map(name_component,
-// 				   "out_RETIRE_ROB_GPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_VAL",
-// 				   _name+"_gpr_status_"+toString(i),
-// 				   "in_WRITE_"+toString(gpr_j)+"_VAL");
-// 	      _component->port_map(name_component,
-// 				   "in_RETIRE_ROB_GPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_ACK",
-// 				   _name+"_gpr_status_"+toString(i),
-// 				   "out_WRITE_"+toString(gpr_j++)+"_ACK");
-// 	      _component->port_map(name_component,
-// 				   "out_RETIRE_ROB_GPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_VAL",
-// 				   _name+"_gpr_status_"+toString(i),
-// 				   "in_WRITE_"+toString(gpr_j)+"_VAL");
-// 	      _component->port_map(name_component,
-// 				   "in_RETIRE_ROB_GPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_ACK",
-// 				   _name+"_gpr_status_"+toString(i),
-// 				   "out_WRITE_"+toString(gpr_j++)+"_ACK");
-// 	      _component->port_map(name_component,
-// 				   "out_RETIRE_ROB_SPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_VAL",
-// 				   _name+"_spr_status_"+toString(i),
-// 				   "in_WRITE_"+toString(spr_j)+"_VAL");
-// 	      _component->port_map(name_component,
-// 				   "in_RETIRE_ROB_SPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_ACK",
-// 				   _name+"_spr_status_"+toString(i),
-// 				   "out_WRITE_"+toString(spr_j++)+"_ACK");
-// 	      _component->port_map(name_component,
-// 				   "out_RETIRE_ROB_SPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_VAL",
-// 				   _name+"_spr_status_"+toString(i),
-// 				   "in_WRITE_"+toString(spr_j)+"_VAL");
-// 	      _component->port_map(name_component,
-// 				   "in_RETIRE_ROB_SPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_ACK",
-// 				   _name+"_spr_status_"+toString(i),
-// 				   "out_WRITE_"+toString(spr_j++)+"_ACK");
-// 	    }
-// 	}
     }// glue
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_deallocation.cpp	(revision 128)
@@ -74,5 +74,11 @@
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-
+    for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+      {
+    delete    component_gpr        [i];
+    delete    component_gpr_status [i];
+    delete    component_spr        [i];
+    delete    component_spr_status [i];
+      }
     delete [] component_gpr       ;
     delete [] component_gpr_status;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/main.cpp	(revision 128)
@@ -7,4 +7,5 @@
 
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/include/test.h"
+#include "Behavioural/include/Allocation.h"
 
 #define NB_PARAMS 18
@@ -309,4 +310,9 @@
   morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void) = &(morpheo::behavioural::custom::default_get_custom_information);
 
+  bool * num_thread_valid;
+  ALLOC1(num_thread_valid              ,bool, nb_thread);
+  for (uint32_t i=0; i<nb_thread; ++i)
+    num_thread_valid [i] = true;
+
   try 
     {
@@ -367,8 +373,11 @@
          is_load_store_unit                            , //[nb_execute_unit]
          translate_num_execute_unit                    , //[nb_execute_unit]
+         num_thread_valid                              , //[nb_thread]
          true // is_toplevel
          );
       
       test (name,param);
+
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
@@ -383,4 +392,62 @@
     }
 
+  for (uint32_t i=0; i< nb_functionnal_unit; i++)
+    {
+  for (uint32_t j=0; j< MAX_TYPE; j++)
+  delete [] timing [i][j];
+  delete [] timing [i];
+    }
+  delete [] timing;
+
+  DELETE1(translate_num_execute_unit    ,_nb_execute_unit);
+  DELETE1(is_load_store_unit            ,_nb_execute_unit);
+
+  for (uint32_t i=0; i<nb_execute_unit; i++)
+  delete    read_unit_to_execution_unit_table_thread [i];
+  delete [] read_unit_to_execution_unit_table_thread;
+
+  for (uint32_t i=0; i<nb_read_unit; i++)
+    {
+  for (uint32_t j=0; j<nb_execute_unit; j++)
+  delete [] read_unit_to_execution_unit_table_routing [i][j];
+  delete [] read_unit_to_execution_unit_table_routing [i];
+   }
+  delete [] read_unit_to_execution_unit_table_routing;
+
+  for (uint32_t i=0; i<nb_write_unit; i++)
+  delete    execution_unit_to_write_unit_table_thread [i];
+  delete [] execution_unit_to_write_unit_table_thread;
+
+  for (uint32_t i=0; i<nb_execute_unit; i++)
+    {
+      uint32_t nb_execute_unit_port = (i<nb_load_store_unit)?nb_inst_memory[i]:nb_inst_functionnal_unit[i-nb_load_store_unit];
+  for (uint32_t j=0; j<nb_execute_unit_port; j++)
+  delete [] execution_unit_to_write_unit_table_routing [i][j];
+  delete [] execution_unit_to_write_unit_table_routing [i];
+   }
+  delete [] execution_unit_to_write_unit_table_routing;
+
+  DELETE1(nb_inst_retire_rob            ,_nb_ooo_engine);
+  DELETE1(nb_inst_insert_rob            ,_nb_ooo_engine);
+  DELETE1(nb_special_register           ,_nb_ooo_engine);
+  DELETE1(nb_general_register           ,_nb_ooo_engine);
+  DELETE1(write_queue_scheme            ,_nb_write_unit);
+  DELETE1(nb_bypass_write               ,_nb_write_unit);
+  DELETE1(size_execute_queue            ,_nb_write_unit);
+  DELETE1(size_write_queue              ,_nb_write_unit);
+  DELETE1(nb_inst_memory                ,_nb_load_store_unit);
+  DELETE1(nb_cache_port                 ,_nb_load_store_unit);
+  DELETE1(nb_bypass_memory              ,_nb_load_store_unit);
+  DELETE1(speculative_load              ,_nb_load_store_unit);
+  DELETE1(nb_port_check                 ,_nb_load_store_unit);
+  DELETE1(size_speculative_access_queue ,_nb_load_store_unit);
+  DELETE1(size_load_queue               ,_nb_load_store_unit);
+  DELETE1(size_store_queue              ,_nb_load_store_unit);
+  DELETE1(nb_inst_functionnal_unit      ,_nb_functionnal_unit);
+  DELETE1(nb_inst_retire                ,_nb_read_unit);
+  DELETE1(size_reservation_station      ,_nb_read_unit);
+  DELETE1(size_read_queue               ,_nb_read_unit);
+  DELETE1(num_thread_valid              , nb_thread);
+
   return (EXIT_SUCCESS);
 }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/test.cpp	(revision 128)
@@ -50,4 +50,69 @@
   sc_clock              *  in_CLOCK  = new sc_clock ("clock", 1.0, 0.5);	 
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
+
+  sc_signal<Tcontrol_t        >  **  in_EXECUTE_LOOP_IN_VAL                  ;
+  sc_signal<Tcontrol_t        >  ** out_EXECUTE_LOOP_IN_ACK                  ;
+  sc_signal<Tcontext_t        >  **  in_EXECUTE_LOOP_IN_CONTEXT_ID           ;
+  sc_signal<Tcontext_t        >  **  in_EXECUTE_LOOP_IN_FRONT_END_ID         ;
+  sc_signal<Tcontext_t        >  **  in_EXECUTE_LOOP_IN_OOO_ENGINE_ID        ;
+  sc_signal<Tpacket_t         >  **  in_EXECUTE_LOOP_IN_PACKET_ID            ;
+  sc_signal<Toperation_t      >  **  in_EXECUTE_LOOP_IN_OPERATION            ;
+  sc_signal<Ttype_t           >  **  in_EXECUTE_LOOP_IN_TYPE                 ;
+  sc_signal<Tlsq_ptr_t        >  **  in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t        >  **  in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE ;
+  sc_signal<Tcontrol_t        >  **  in_EXECUTE_LOOP_IN_HAS_IMMEDIAT         ;
+  sc_signal<Tgeneral_data_t   >  **  in_EXECUTE_LOOP_IN_IMMEDIAT             ;
+  sc_signal<Tcontrol_t        >  **  in_EXECUTE_LOOP_IN_READ_RA              ;
+  sc_signal<Tgeneral_address_t>  **  in_EXECUTE_LOOP_IN_NUM_REG_RA           ;
+  sc_signal<Tcontrol_t        >  **  in_EXECUTE_LOOP_IN_READ_RB              ;
+  sc_signal<Tgeneral_address_t>  **  in_EXECUTE_LOOP_IN_NUM_REG_RB           ;
+  sc_signal<Tcontrol_t        >  **  in_EXECUTE_LOOP_IN_READ_RC              ;
+  sc_signal<Tspecial_address_t>  **  in_EXECUTE_LOOP_IN_NUM_REG_RC           ;
+  sc_signal<Tcontrol_t        >  **  in_EXECUTE_LOOP_IN_WRITE_RD             ;
+  sc_signal<Tgeneral_address_t>  **  in_EXECUTE_LOOP_IN_NUM_REG_RD           ;
+  sc_signal<Tcontrol_t        >  **  in_EXECUTE_LOOP_IN_WRITE_RE             ;
+  sc_signal<Tspecial_address_t>  **  in_EXECUTE_LOOP_IN_NUM_REG_RE           ;
+  sc_signal<Tcontrol_t        >  ** out_EXECUTE_LOOP_OUT_VAL                 ;
+  sc_signal<Tcontrol_t        >  **  in_EXECUTE_LOOP_OUT_ACK                 ;
+  sc_signal<Tcontext_t        >  ** out_EXECUTE_LOOP_OUT_CONTEXT_ID          ;
+  sc_signal<Tcontext_t        >  ** out_EXECUTE_LOOP_OUT_FRONT_END_ID        ;
+  sc_signal<Tcontext_t        >  ** out_EXECUTE_LOOP_OUT_OOO_ENGINE_ID       ;
+  sc_signal<Tpacket_t         >  ** out_EXECUTE_LOOP_OUT_PACKET_ID           ;
+//sc_signal<Toperation_t      >  ** out_EXECUTE_LOOP_OUT_OPERATION           ;
+//sc_signal<Ttype_t           >  ** out_EXECUTE_LOOP_OUT_TYPE                ;
+  sc_signal<Tspecial_data_t   >  ** out_EXECUTE_LOOP_OUT_FLAGS               ;
+  sc_signal<Texception_t      >  ** out_EXECUTE_LOOP_OUT_EXCEPTION           ;
+  sc_signal<Tcontrol_t        >  ** out_EXECUTE_LOOP_OUT_NO_SEQUENCE         ;
+  sc_signal<Taddress_t        >  ** out_EXECUTE_LOOP_OUT_ADDRESS             ;
+  sc_signal<Tgeneral_data_t   >  ** out_EXECUTE_LOOP_OUT_DATA                ;
+  sc_signal<Tcontrol_t        > *** out_DCACHE_REQ_VAL                       ;
+  sc_signal<Tcontrol_t        > ***  in_DCACHE_REQ_ACK                       ;
+  sc_signal<Tcontext_t        > *** out_DCACHE_REQ_CONTEXT_ID                ;
+  sc_signal<Tpacket_t         > *** out_DCACHE_REQ_PACKET_ID                 ;
+  sc_signal<Tdcache_address_t > *** out_DCACHE_REQ_ADDRESS                   ;
+  sc_signal<Tdcache_type_t    > *** out_DCACHE_REQ_TYPE                      ;
+  sc_signal<Tdcache_data_t    > *** out_DCACHE_REQ_WDATA                     ;
+  sc_signal<Tcontrol_t        > ***  in_DCACHE_RSP_VAL                       ;
+  sc_signal<Tcontrol_t        > *** out_DCACHE_RSP_ACK                       ;
+  sc_signal<Tcontext_t        > ***  in_DCACHE_RSP_CONTEXT_ID                ;
+  sc_signal<Tpacket_t         > ***  in_DCACHE_RSP_PACKET_ID                 ;
+  sc_signal<Tdcache_data_t    > ***  in_DCACHE_RSP_RDATA                     ;
+  sc_signal<Tdcache_error_t   > ***  in_DCACHE_RSP_ERROR                     ; 
+  sc_signal<Tcontrol_t        > ***  in_INSERT_ROB_VAL                       ;
+  sc_signal<Tcontrol_t        > *** out_INSERT_ROB_ACK                       ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_ROB_RD_USE                    ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_ROB_RD_NUM_REG                ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_ROB_RE_USE                    ;
+  sc_signal<Tspecial_address_t> ***  in_INSERT_ROB_RE_NUM_REG                ;
+//sc_signal<Tcontrol_t        > ***  in_RETIRE_ROB_VAL                       ;
+//sc_signal<Tcontrol_t        > *** out_RETIRE_ROB_ACK                       ;
+//sc_signal<Tcontrol_t        > ***  in_RETIRE_ROB_RD_OLD_USE                ; 
+//sc_signal<Tgeneral_address_t> ***  in_RETIRE_ROB_RD_OLD_NUM_REG            ;
+//sc_signal<Tcontrol_t        > ***  in_RETIRE_ROB_RD_NEW_USE                ;
+//sc_signal<Tgeneral_address_t> ***  in_RETIRE_ROB_RD_NEW_NUM_REG            ;
+//sc_signal<Tcontrol_t        > ***  in_RETIRE_ROB_RE_OLD_USE                ; 
+//sc_signal<Tspecial_address_t> ***  in_RETIRE_ROB_RE_OLD_NUM_REG            ;
+//sc_signal<Tcontrol_t        > ***  in_RETIRE_ROB_RE_NEW_USE                ;
+//sc_signal<Tspecial_address_t> ***  in_RETIRE_ROB_RE_NEW_NUM_REG            ;
   
   ALLOC1_SC_SIGNAL( in_EXECUTE_LOOP_IN_VAL                  ," in_EXECUTE_LOOP_IN_VAL                  ",Tcontrol_t        ,_param->_nb_read_unit);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp	(revision 128)
@@ -7,4 +7,5 @@
 
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Parameters.h"
+#include "Behavioural/include/Allocation.h"
 #include "Common/include/Max.h"
 
@@ -139,13 +140,10 @@
     _nb_execute_unit                            = _nb_functionnal_unit + _nb_load_store_unit;
 
-    _nb_execute_unit_port                       = new uint32_t [_nb_execute_unit];
-    
-    _read_unit_to_execution_unit_table_execute_type = new bool * [_nb_execute_unit];
+    ALLOC1(_nb_execute_unit_port                          ,uint32_t,_nb_execute_unit);
+    ALLOC2(_read_unit_to_execution_unit_table_execute_type,bool    ,_nb_execute_unit,_nb_type);
+
     for (uint32_t i=0; i<_nb_execute_unit; i++)
-      {
-	_read_unit_to_execution_unit_table_execute_type [i] = new bool [_nb_type];
-	for (uint32_t j=0; j<_nb_type; j++)
-	  _read_unit_to_execution_unit_table_execute_type [i][j] = false;
-      }
+      for (uint32_t j=0; j<_nb_type; j++)
+        _read_unit_to_execution_unit_table_execute_type [i][j] = false;
 
     // Fill execute_type
@@ -203,15 +201,15 @@
     uint32_t _max_nb_inst_memory = max<uint32_t>(_nb_inst_memory,_nb_load_store_unit);
 
-    _set_read_unit_source_register_write = new std::set<uint32_t> [_nb_read_unit];
-    _set_read_unit_source_bypass_write   = new std::set<uint32_t> [_nb_read_unit];
-    _set_read_unit_source_bypass_memory  = new std::set<uint32_t> [_nb_read_unit];
-    
-    _read_unit_nb_register_write          = new uint32_t [_nb_read_unit];
-    _read_unit_nb_bypass_write            = new uint32_t [_nb_read_unit];
-    _read_unit_nb_bypass_memory           = new uint32_t [_nb_read_unit];
-
-    _link_read_unit_with_load_store_unit  = new bool ** [nb_read_unit];
-    _link_read_unit_with_write_unit       = new bool *  [nb_read_unit];
-    _link_read_unit_with_thread           = new bool *  [nb_read_unit];
+    ALLOC1(_set_read_unit_source_register_write  ,std::set<uint32_t>,_nb_read_unit);
+    ALLOC1(_set_read_unit_source_bypass_write    ,std::set<uint32_t>,_nb_read_unit);
+    ALLOC1(_set_read_unit_source_bypass_memory   ,std::set<uint32_t>,_nb_read_unit);
+
+    ALLOC1(_read_unit_nb_register_write          ,uint32_t          ,_nb_read_unit);
+    ALLOC1(_read_unit_nb_bypass_write            ,uint32_t          ,_nb_read_unit);
+    ALLOC1(_read_unit_nb_bypass_memory           ,uint32_t          ,_nb_read_unit);
+
+    ALLOC3(_link_read_unit_with_load_store_unit  ,bool              ,_nb_read_unit,_nb_execute_unit,_max_nb_inst_memory);
+    ALLOC2(_link_read_unit_with_write_unit       ,bool              ,_nb_read_unit,_nb_write_unit  );
+    ALLOC2(_link_read_unit_with_thread           ,bool              ,_nb_read_unit,_nb_thread      );
 
     for (uint32_t i=0; i<_nb_read_unit; i++)
@@ -221,15 +219,8 @@
 	_read_unit_nb_bypass_memory  [i] = 0;
 
-	_link_read_unit_with_load_store_unit [i] = new bool * [_nb_execute_unit];
-	_link_read_unit_with_write_unit      [i] = new bool   [_nb_write_unit];
-	_link_read_unit_with_thread          [i] = new bool   [_nb_thread];
-
 	for (uint32_t j=0; j<_nb_execute_unit; j++)
-	  {
-	    _link_read_unit_with_load_store_unit [i][j] = new bool [_max_nb_inst_memory];
-
-	    for (uint32_t k=0; k<_max_nb_inst_memory; k++)
-	      _link_read_unit_with_load_store_unit [i][j][k] = false;
-	  }
+          for (uint32_t k=0; k<_max_nb_inst_memory; k++)
+            _link_read_unit_with_load_store_unit [i][j][k] = false;
+
 	for (uint32_t j=0; j<_nb_write_unit; j++)
 	  _link_read_unit_with_write_unit [i][j] = false;
@@ -594,13 +585,13 @@
     delete    _param_read_unit [i];
     delete [] _param_read_unit;
-
+    
     for (uint32_t i=0; i<_nb_execute_unit; i++)
       {
         uint32_t x = _translate_num_execute_unit [i];
-
+        
         if (_is_load_store_unit [i] == false)
           delete _param_functionnal_unit [x];
         else
-          delete _param_load_store_unit [x];
+          delete _param_load_store_unit  [x];
       }
     delete [] _param_functionnal_unit;
@@ -613,17 +604,24 @@
     delete    _param_register_unit;
 
-    delete [] _read_unit_to_execution_unit_table_execute_type;
-    delete [] _read_unit_nb_register_write;
-    delete [] _read_unit_nb_bypass_write;
-    delete [] _read_unit_nb_bypass_memory;
-    delete [] _set_read_unit_source_register_write ;
-    delete [] _set_read_unit_source_bypass_write   ;
-    delete [] _set_read_unit_source_bypass_memory  ;
-    delete [] _link_read_unit_with_load_store_unit;
-    delete [] _link_read_unit_with_write_unit;
-    delete [] _link_read_unit_with_thread;
-    delete [] _is_load_store_unit;
-    delete [] _translate_num_execute_unit;
-    delete [] _nb_execute_unit_port;
+    uint32_t _nb_thread = get_nb_thread(_nb_context,
+					_nb_front_end,
+					_nb_ooo_engine);
+    uint32_t _max_nb_inst_memory = max<uint32_t>(_nb_inst_memory,_nb_load_store_unit);
+
+    DELETE2(_link_read_unit_with_thread           ,_nb_read_unit,_nb_thread      );
+    DELETE2(_link_read_unit_with_write_unit       ,_nb_read_unit,_nb_write_unit  );
+    DELETE3(_link_read_unit_with_load_store_unit  ,_nb_read_unit,_nb_execute_unit,_max_nb_inst_memory);
+
+    DELETE1(_read_unit_nb_bypass_memory           ,_nb_read_unit);
+    DELETE1(_read_unit_nb_bypass_write            ,_nb_read_unit);
+    DELETE1(_read_unit_nb_register_write          ,_nb_read_unit);
+
+    DELETE1(_set_read_unit_source_bypass_memory   ,_nb_read_unit);
+    DELETE1(_set_read_unit_source_bypass_write    ,_nb_read_unit);
+    DELETE1(_set_read_unit_source_register_write  ,_nb_read_unit);
+
+    DELETE2(_read_unit_to_execution_unit_table_execute_type,_nb_execute_unit,_nb_type);
+    DELETE1(_nb_execute_unit_port                          ,_nb_execute_unit);
+
     log_printf(FUNC,Execute_loop,FUNCTION,"End");
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 128)
@@ -50,5 +50,14 @@
             reg_STATE            [i] = CONTEXT_STATE_OK;
             reg_INTERRUPT_ENABLE [i] = 0;
-            reg_EVENT_DEPTH      [i] = 0; // unacessary
+
+            reg_EVENT_ADDRESS          [i] = 0; // not necessary
+            reg_EVENT_ADDRESS_EPCR     [i] = 0; // not necessary 
+            reg_EVENT_ADDRESS_EPCR_VAL [i] = 0; // not necessary
+            reg_EVENT_ADDRESS_EEAR     [i] = 0; // not necessary 
+            reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; // not necessary
+            reg_EVENT_IS_DELAY_SLOT    [i] = 0; // not necessary
+            reg_EVENT_IS_DS_TAKE       [i] = 0; // not necessary
+            reg_EVENT_DEPTH            [i] = 0; // not necessary
+            reg_EVENT_FLUSH_ONLY       [i] = 0; // not necessary
           }
       }
@@ -236,4 +245,233 @@
             reg_STATE [i] = state;
           }
+
+        // -------------------------------------------------------------------
+        // -----[ BRANCH_EVENT ]----------------------------------------------
+        // -------------------------------------------------------------------
+        for (uint32_t i=0; i<_param->_nb_context; ++i)
+          if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i])
+            {
+              log_printf(TRACE,Context_State,FUNCTION,"  * BRANCH_EVENT [%d]",i);
+
+              context_state_t state = reg_STATE [i];
+
+              Tdepth_t   depth      = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0;
+              Tdepth_t   depth_cur  = reg_EVENT_DEPTH [i];
+              Tdepth_t   depth_min  = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0;
+              Tdepth_t   depth_max  = _param->_nb_inst_branch_speculated [i];
+              
+              Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
+              Tdepth_t   depth1     = (depth    >=depth_min)?(depth    -depth_min):((depth    +depth_max-depth_min));
+//               Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
+//               Tdepth_t   depth1     = (depth    >=depth_min)?(depth    ):((depth    +depth_max));
+
+              // priority : miss_load > miss_branch > excep > spr/sync
+              uint8_t    priority0  = get_priority(state);
+              uint8_t    priority1  = PRIORITY_MISS_BRANCH; // miss
+
+              // is_valid = can modify local information
+              //   if context_state_ok : yes
+              //   if context_state_ko : test the depth, and the priority of event
+              bool       is_valid   = ((state == CONTEXT_STATE_OK) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or
+//                                     (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or
+                                       (depth1< depth0) or
+                                       ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth
+
+              bool       is_invalid = priority0 == PRIORITY_MISS_LOAD;
+
+#ifdef DEBUG_TEST
+              if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and
+                  (depth0 != depth1))
+                throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str()));
+#endif
+
+              log_printf(TRACE,Context_State,FUNCTION,"    * state     : %s",toString(state).c_str());
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth     : %d",depth     );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth_cur : %d",depth_cur );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth_min : %d",depth_min );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth_max : %d",depth_max );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth0    : %d",depth0    );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth1    : %d",depth1    );
+              log_printf(TRACE,Context_State,FUNCTION,"    * priority0 : %d",priority0 );
+              log_printf(TRACE,Context_State,FUNCTION,"    * priority1 : %d",priority1 );
+              log_printf(TRACE,Context_State,FUNCTION,"  * is_valid    : %d",is_valid  );
+              log_printf(TRACE,Context_State,FUNCTION,"  * is_invalid  : %d",is_invalid);
+
+              if (is_valid and not is_invalid)
+                {
+//                reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
+
+                  if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE)
+                    {
+// #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)
+//                       reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR;
+// #else
+                      reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND;
+// #endif
+                    }
+                  else
+                    {
+                      Tcontrol_t can_continue = PORT_READ(in_BRANCH_EVENT_CAN_CONTINUE    [i]);
+                      Tcontrol_t dest_val     = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
+
+                      log_printf(TRACE,Context_State,FUNCTION,"  * dest_val    : %d",dest_val    );
+                      log_printf(TRACE,Context_State,FUNCTION,"  * can_continue: %d",can_continue);
+
+                      if (can_continue)
+                        reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
+                      else
+                        {
+// #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)
+//                           reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
+// #else
+                          reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_WAITEND;
+// #endif
+                        }
+
+                      reg_EVENT_ADDRESS          [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC  [i])+1; // address delay slot
+                      reg_EVENT_ADDRESS_EPCR     [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]);   // address_next
+                      reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val;
+                    //reg_EVENT_ADDRESS_EEAR     [i] = 0; 
+                      reg_EVENT_ADDRESS_EEAR_VAL [i] = 0;
+                      reg_EVENT_IS_DELAY_SLOT    [i] = 1;
+                      reg_EVENT_IS_DS_TAKE       [i] = dest_val;
+                      reg_EVENT_DEPTH            [i] = depth;
+                      reg_EVENT_FLUSH_ONLY       [i] = can_continue;
+                    }
+                }
+            }
+        
+        // -------------------------------------------------------------------
+        // -----[ DECOD_EVENT ]-----------------------------------------------
+        // -------------------------------------------------------------------
+
+        for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
+          if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i])
+            {
+              log_printf(TRACE,Context_State,FUNCTION,"  * DECOD_EVENT [%d]",i);
+
+              Tcontext_t context    = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0;
+              Tdepth_t   depth      = (_param->_have_port_depth      )?PORT_READ(in_DECOD_EVENT_DEPTH      [i]):0;
+              Tdepth_t   depth_cur  = reg_EVENT_DEPTH [context];
+              Tdepth_t   depth_min = (_param->_have_port_depth      )?PORT_READ(in_DEPTH_MIN [context]):0;
+              Tdepth_t   depth_max  = _param->_nb_inst_branch_speculated [context];
+              
+              Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
+              Tdepth_t   depth1     = (depth    >=depth_min)?(depth    -depth_min):((depth    +depth_max-depth_min));
+//               Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
+//               Tdepth_t   depth1     = (depth    >=depth_min)?(depth    ):((depth    +depth_max));
+
+              context_state_t state = reg_STATE [context];
+              Tevent_type_t   type  = PORT_READ(in_DECOD_EVENT_TYPE [i]);
+              
+              // miss_load > miss_branch > excep > spr/sync
+              uint8_t    priority0  = get_priority(state);
+              uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION:PRIORITY_NONE;
+
+              // is_valid = can modify local information
+              //  if context_state_ok : yes
+              //  if context_state_ko : test the depth, and the priority of envent
+
+              bool       is_valid   = ((state == CONTEXT_STATE_OK) or
+                                       (depth1< depth0) or
+                                       ((depth1==depth0) and (priority1>=priority0)));
+
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth     : %d",depth     );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth_cur : %d",depth_cur );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth_min : %d",depth_min );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth_max : %d",depth_max );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth0    : %d",depth0    );
+              log_printf(TRACE,Context_State,FUNCTION,"    * depth1    : %d",depth1    );
+              log_printf(TRACE,Context_State,FUNCTION,"    * priority0 : %d",priority0 );
+              log_printf(TRACE,Context_State,FUNCTION,"    * priority1 : %d",priority1 );
+              log_printf(TRACE,Context_State,FUNCTION,"  * is_valid    : %d",is_valid  );
+
+              if (is_valid)
+                {
+                  log_printf(TRACE,Context_State,FUNCTION,"    * is_valid");
+
+                  // decod : 
+                  // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys)
+                  context_state_t state_next    = state;
+                  Taddress_t      address       = PORT_READ(in_DECOD_EVENT_ADDRESS       [i]);
+                  Tcontrol_t      is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]);
+
+                  switch (type)
+                    {
+                    case EVENT_TYPE_EXCEPTION          : 
+                      {
+                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_EXCEPTION");
+
+                        state_next = CONTEXT_STATE_KO_EXCEP; 
+
+                        break;
+                      }
+                    case EVENT_TYPE_SPR_ACCESS         : 
+                      {
+                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_SPR_ACCESS");
+
+//                      state_next = CONTEXT_STATE_KO_SPR  ; 
+                        state_next = CONTEXT_STATE_KO_SPR_EXEC; 
+                        address++; // take next address
+//                         if (is_delay_slot)
+//                           throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
+                        break;
+                      }
+                    case EVENT_TYPE_MSYNC              : 
+                      {
+                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_MSYNC");
+
+//                      state_next = CONTEXT_STATE_KO_MSYNC;
+                        state_next = CONTEXT_STATE_KO_MSYNC_EXEC;
+                        address++;  // take next address
+//                         if (is_delay_slot)
+//                           throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n");
+                        break;
+                      }
+                    case EVENT_TYPE_PSYNC              :
+                      {
+                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_PSYNC");
+
+//                      state_next = CONTEXT_STATE_KO_PSYNC;
+                        state_next = CONTEXT_STATE_KO_PSYNC_FLUSH;
+                        address++;  // take next address
+                        if (is_delay_slot)
+                          throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n");
+                        break;
+                      }
+                    case EVENT_TYPE_CSYNC              :
+                      {
+                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_CSYNC");
+
+//                      state_next = CONTEXT_STATE_KO_CSYNC;
+                        state_next = CONTEXT_STATE_KO_CSYNC_FLUSH;
+                        address++;  // take next address
+                        if (is_delay_slot)
+                          throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n");
+                        break;
+                      }               
+                    case EVENT_TYPE_NONE               :
+                    case EVENT_TYPE_BRANCH_MISS_SPECULATION   :
+                    case EVENT_TYPE_LOAD_MISS_SPECULATION   :
+//                     case EVENT_TYPE_BRANCH_NO_ACCURATE :
+                    default :
+                      {
+                        throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str()));
+                      }
+                    }
+
+                  reg_STATE                  [context] = state_next;
+                  reg_EVENT_ADDRESS          [context] = address;
+                  reg_EVENT_ADDRESS_EPCR     [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR  [i]); 
+                  reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
+                //reg_EVENT_ADDRESS_EEAR     [context]
+                  reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;
+                  reg_EVENT_IS_DELAY_SLOT    [context] = is_delay_slot;
+                //reg_EVENT_IS_DS_TAKE       [context] = 0;
+                  reg_EVENT_DEPTH            [context] = depth;
+                  reg_EVENT_FLUSH_ONLY       [context] = false;
+                }
+            }
 
         // -------------------------------------------------------------------
@@ -283,100 +521,4 @@
 
         // -------------------------------------------------------------------
-        // -----[ BRANCH_EVENT ]----------------------------------------------
-        // -------------------------------------------------------------------
-        for (uint32_t i=0; i<_param->_nb_context; ++i)
-          if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i])
-            {
-              log_printf(TRACE,Context_State,FUNCTION,"  * BRANCH_EVENT [%d]",i);
-
-              context_state_t state = reg_STATE [i];
-
-              Tdepth_t   depth      = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0;
-              Tdepth_t   depth_cur  = reg_EVENT_DEPTH [i];
-              Tdepth_t   depth_min  = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0;
-              Tdepth_t   depth_max  = _param->_nb_inst_branch_speculated [i];
-              
-              Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
-              Tdepth_t   depth1     = (depth    >=depth_min)?(depth    -depth_min):((depth    +depth_max-depth_min));
-//               Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
-//               Tdepth_t   depth1     = (depth    >=depth_min)?(depth    ):((depth    +depth_max));
-
-              // priority : miss_load > miss_branch > excep > spr/sync
-              uint8_t    priority0  = get_priority(state);
-              uint8_t    priority1  = PRIORITY_MISS_BRANCH; // miss
-
-              // is_valid = can modify local information
-              //   if context_state_ok : yes
-              //   if context_state_ko : test the depth, and the priority of event
-              bool       is_valid   = ((state == CONTEXT_STATE_OK) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or
-//                                     (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or
-                                       (depth1< depth0) or
-                                       ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth
-
-              bool       is_invalid = priority0 == PRIORITY_MISS_LOAD;
-
-#ifdef DEBUG_TEST
-              if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and
-                  (depth0 != depth1))
-                throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str()));
-#endif
-
-              log_printf(TRACE,Context_State,FUNCTION,"    * state     : %s",toString(state).c_str());
-              log_printf(TRACE,Context_State,FUNCTION,"    * depth     : %d",depth     );
-              log_printf(TRACE,Context_State,FUNCTION,"    * depth_cur : %d",depth_cur );
-              log_printf(TRACE,Context_State,FUNCTION,"    * depth_min : %d",depth_min );
-              log_printf(TRACE,Context_State,FUNCTION,"    * depth_max : %d",depth_max );
-              log_printf(TRACE,Context_State,FUNCTION,"    * depth0    : %d",depth0    );
-              log_printf(TRACE,Context_State,FUNCTION,"    * depth1    : %d",depth1    );
-              log_printf(TRACE,Context_State,FUNCTION,"    * priority0 : %d",priority0 );
-              log_printf(TRACE,Context_State,FUNCTION,"    * priority1 : %d",priority1 );
-              log_printf(TRACE,Context_State,FUNCTION,"  * is_valid    : %d",is_valid  );
-
-              if (is_valid and not is_invalid)
-                {
-//                reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
-
-                  if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE)
-                    {
-// #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)
-//                       reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR;
-// #else
-                      reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND;
-// #endif
-                    }
-                  else
-                    {
-                      Tcontrol_t can_continue = PORT_READ(in_BRANCH_EVENT_CAN_CONTINUE    [i]);
-                      Tcontrol_t dest_val     = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
-
-                      log_printf(TRACE,Context_State,FUNCTION,"  * dest_val    : %d",dest_val    );
-                      log_printf(TRACE,Context_State,FUNCTION,"  * can_continue: %d",can_continue);
-
-                      if (can_continue)
-                        reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
-                      else
-                        {
-// #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)
-//                           reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
-// #else
-                          reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_WAITEND;
-// #endif
-                        }
-
-                      reg_EVENT_ADDRESS          [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC  [i])+1; // address delay slot
-                      reg_EVENT_ADDRESS_EPCR     [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]);   // address_next
-                      reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val;
-                    //reg_EVENT_ADDRESS_EEAR     [i] = 0; 
-                      reg_EVENT_ADDRESS_EEAR_VAL [i] = 0;
-                      reg_EVENT_IS_DELAY_SLOT    [i] = 1;
-                      reg_EVENT_IS_DS_TAKE       [i] = dest_val;
-                      reg_EVENT_DEPTH            [i] = depth;
-                      reg_EVENT_FLUSH_ONLY       [i] = can_continue;
-                    }
-                }
-            }
-
-        // -------------------------------------------------------------------
         // -----[ BRANCH_COMPLETE ]----------------------------------------------
         // -------------------------------------------------------------------
@@ -429,136 +571,4 @@
                   reg_EVENT_DEPTH            [context_id] = depth;
                   reg_EVENT_FLUSH_ONLY       [context_id] = false;
-                }
-            }
-        
-        // -------------------------------------------------------------------
-        // -----[ DECOD_EVENT ]-----------------------------------------------
-        // -------------------------------------------------------------------
-
-        for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
-          if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i])
-            {
-              log_printf(TRACE,Context_State,FUNCTION,"  * DECOD_EVENT [%d]",i);
-
-              Tcontext_t context    = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0;
-              Tdepth_t   depth      = (_param->_have_port_depth      )?PORT_READ(in_DECOD_EVENT_DEPTH      [i]):0;
-              Tdepth_t   depth_cur  = reg_EVENT_DEPTH [context];
-              Tdepth_t   depth_min = (_param->_have_port_depth      )?PORT_READ(in_DEPTH_MIN [context]):0;
-              Tdepth_t   depth_max  = _param->_nb_inst_branch_speculated [context];
-              
-              Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
-              Tdepth_t   depth1     = (depth    >=depth_min)?(depth    -depth_min):((depth    +depth_max-depth_min));
-//               Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
-//               Tdepth_t   depth1     = (depth    >=depth_min)?(depth    ):((depth    +depth_max));
-
-              context_state_t state = reg_STATE [context];
-              Tevent_type_t   type  = PORT_READ(in_DECOD_EVENT_TYPE [i]);
-              
-              // miss_load > miss_branch > excep > spr/sync
-              uint8_t    priority0  = get_priority(state);
-              uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION:PRIORITY_NONE;
-
-              // is_valid = can modify local information
-              //  if context_state_ok : yes
-              //  if context_state_ko : test the depth, and the priority of envent
-
-              bool       is_valid   = ((state == CONTEXT_STATE_OK) or
-                                       (depth1< depth0) or
-                                       ((depth1==depth0) and (priority1>=priority0)));
-
-              log_printf(TRACE,Context_State,FUNCTION,"    * depth     : %d",depth     );
-              log_printf(TRACE,Context_State,FUNCTION,"    * depth_cur : %d",depth_cur );
-              log_printf(TRACE,Context_State,FUNCTION,"    * depth_min : %d",depth_min );
-              log_printf(TRACE,Context_State,FUNCTION,"    * depth_max : %d",depth_max );
-              log_printf(TRACE,Context_State,FUNCTION,"    * depth0    : %d",depth0    );
-              log_printf(TRACE,Context_State,FUNCTION,"    * depth1    : %d",depth1    );
-              log_printf(TRACE,Context_State,FUNCTION,"    * priority0 : %d",priority0 );
-              log_printf(TRACE,Context_State,FUNCTION,"    * priority1 : %d",priority1 );
-              log_printf(TRACE,Context_State,FUNCTION,"  * is_valid    : %d",is_valid  );
-
-              if (is_valid)
-                {
-                  log_printf(TRACE,Context_State,FUNCTION,"    * is_valid");
-
-                  // decod : 
-                  // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys)
-                  context_state_t state_next    = state;
-                  Taddress_t      address       = PORT_READ(in_DECOD_EVENT_ADDRESS       [i]);
-                  Tcontrol_t      is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]);
-
-                  switch (type)
-                    {
-                    case EVENT_TYPE_EXCEPTION          : 
-                      {
-                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_EXCEPTION");
-
-                        state_next = CONTEXT_STATE_KO_EXCEP; 
-
-                        break;
-                      }
-                    case EVENT_TYPE_SPR_ACCESS         : 
-                      {
-                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_SPR_ACCESS");
-
-//                      state_next = CONTEXT_STATE_KO_SPR  ; 
-                        state_next = CONTEXT_STATE_KO_SPR_EXEC; 
-                        address++; // take next address
-//                         if (is_delay_slot)
-//                           throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
-                        break;
-                      }
-                    case EVENT_TYPE_MSYNC              : 
-                      {
-                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_MSYNC");
-
-//                      state_next = CONTEXT_STATE_KO_MSYNC;
-                        state_next = CONTEXT_STATE_KO_MSYNC_EXEC;
-                        address++;  // take next address
-//                         if (is_delay_slot)
-//                           throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n");
-                        break;
-                      }
-                    case EVENT_TYPE_PSYNC              :
-                      {
-                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_PSYNC");
-
-//                      state_next = CONTEXT_STATE_KO_PSYNC;
-                        state_next = CONTEXT_STATE_KO_PSYNC_FLUSH;
-                        address++;  // take next address
-                        if (is_delay_slot)
-                          throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n");
-                        break;
-                      }
-                    case EVENT_TYPE_CSYNC              :
-                      {
-                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_CSYNC");
-
-//                      state_next = CONTEXT_STATE_KO_CSYNC;
-                        state_next = CONTEXT_STATE_KO_CSYNC_FLUSH;
-                        address++;  // take next address
-                        if (is_delay_slot)
-                          throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n");
-                        break;
-                      }               
-                    case EVENT_TYPE_NONE               :
-                    case EVENT_TYPE_BRANCH_MISS_SPECULATION   :
-                    case EVENT_TYPE_LOAD_MISS_SPECULATION   :
-//                     case EVENT_TYPE_BRANCH_NO_ACCURATE :
-                    default :
-                      {
-                        throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str()));
-                      }
-                    }
-
-                  reg_STATE                  [context] = state_next;
-                  reg_EVENT_ADDRESS          [context] = address;
-                  reg_EVENT_ADDRESS_EPCR     [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR  [i]); 
-                  reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
-                //reg_EVENT_ADDRESS_EEAR     [context]
-                  reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;
-                  reg_EVENT_IS_DELAY_SLOT    [context] = is_delay_slot;
-                //reg_EVENT_IS_DS_TAKE       [context] = 0;
-                  reg_EVENT_DEPTH            [context] = depth;
-                  reg_EVENT_FLUSH_ONLY       [context] = false;
                 }
             }
@@ -706,4 +716,7 @@
             }
 
+        // -------------------------------------------------------------------
+        // -----[ INTERRUPT ]-------------------------------------------------
+        // -------------------------------------------------------------------
         for (uint32_t i=0; i<_param->_nb_context; ++i)
           {
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp	(revision 128)
@@ -90,4 +90,5 @@
         DELETE1_SIGNAL(in_CONTEXT_DECOD_ENABLE                ,_param->_nb_context,1);
         DELETE1_SIGNAL(in_CONTEXT_EVENT                       ,_param->_nb_context,1);
+        DELETE1_SIGNAL(in_CONTEXT_DEPTH_VAL                   ,_param->_nb_context,1);
         DELETE1_SIGNAL(in_CONTEXT_DEPTH                       ,_param->_nb_context,_param->_size_depth);
         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp	(revision 128)
@@ -35,5 +35,5 @@
         DELETE0_SIGNAL(out_ADDRESS_BRANCH_STATE               ,_param->_size_branch_state            );
         DELETE0_SIGNAL(out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth);
-        DELETE1_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE          ,1,_param->_nb_instruction);
+        DELETE1_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE         ,_param->_nb_instruction,1);
         
         DELETE0_SIGNAL(out_PREDICT_VAL                        ,1);
@@ -48,5 +48,5 @@
         DELETE0_SIGNAL( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth);
         DELETE0_SIGNAL( in_PREDICT_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr);
-        DELETE1_SIGNAL(in_PREDICT_INSTRUCTION_ENABLE           ,1,_param->_nb_instruction);
+        DELETE1_SIGNAL(in_PREDICT_INSTRUCTION_ENABLE          ,_param->_nb_instruction,1);
         
         DELETE0_SIGNAL( in_EVENT_VAL             ,1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp	(revision 128)
@@ -28,21 +28,36 @@
       {
 	// nothing is valid
-	reg_PC_ACCESS_VAL    = 0;
-
-	reg_PC_CURRENT_VAL   = 0;
-
-        reg_PC_NEXT_VAL      = 1;
-        reg_PC_NEXT          = 0x100>>2;
-        reg_PC_NEXT_IS_DS_TAKE                  = 0;
+	reg_PC_ACCESS_VAL                               = 0;
+        reg_PC_ACCESS                                   = 0;// not necessary
+        reg_PC_ACCESS_IS_DS_TAKE                        = 0;// not necessary
+        for (uint32_t i=0; i<_param->_nb_instruction; i++)
+        reg_PC_ACCESS_INSTRUCTION_ENABLE [i]            = 0;// not necessary
+        reg_PC_ACCESS_INST_IFETCH_PTR                   = 0;// not necessary
+        reg_PC_ACCESS_BRANCH_STATE                      = 0;// not necessary
+        reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID       = 0;// not necessary
+
+	reg_PC_CURRENT_VAL                              = 0;
+        reg_PC_CURRENT                                  = 0;// not necessary
+        reg_PC_CURRENT_IS_DS_TAKE                       = 0;// not necessary
+        for (uint32_t i=0; i<_param->_nb_instruction; i++)
+        reg_PC_CURRENT_INSTRUCTION_ENABLE [i]           = 0;// not necessary
+        reg_PC_CURRENT_INST_IFETCH_PTR                  = 0;// not necessary
+        reg_PC_CURRENT_BRANCH_STATE                     = 0;// not necessary
+        reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID      = 0;// not necessary
+
+        reg_PC_NEXT_VAL                                 = 1;
+        reg_PC_NEXT                                     = 0x100>>2;
+        reg_PC_NEXT_IS_DS_TAKE                          = 0;
         uint32_t index = reg_PC_NEXT % _param->_nb_instruction;
         for (uint32_t i=0; i<_param->_nb_instruction; i++)
-        reg_PC_NEXT_INSTRUCTION_ENABLE [i]      = 0;
-        reg_PC_NEXT_INSTRUCTION_ENABLE [index]  = 1;
-        reg_PC_NEXT_INST_IFETCH_PTR             = 0;
-        reg_PC_NEXT_BRANCH_STATE                = 0;
-        reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0;
-
-
-	reg_PC_NEXT_NEXT_VAL = 0;
+        reg_PC_NEXT_INSTRUCTION_ENABLE [i]              = 0;
+        reg_PC_NEXT_INSTRUCTION_ENABLE [index]          = 1;
+        reg_PC_NEXT_INST_IFETCH_PTR                     = 0;
+        reg_PC_NEXT_BRANCH_STATE                        = 0;
+        reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID         = 0;
+
+	reg_PC_NEXT_NEXT_VAL                            = 0;
+        reg_PC_NEXT_NEXT                                = 0;// not necessary
+        reg_PC_NEXT_NEXT_IS_DS_TAKE                     = 0;// not necessary
       }
     else
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h	(revision 128)
@@ -47,15 +47,7 @@
   public : ~ifetch_queue_entry_t (void)
     {
-      delete _instruction       ;
-      delete _instruction_enable;
+      delete [] _instruction       ;
+      delete [] _instruction_enable;
     }
-
-//   public : friend std::ostream& operator<< (std::ostream& output,
-// 					    ifetch_queue_entry_t & x)
-//     {
-//       output << ;
-//       return output;
-//     }
-
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp	(revision 128)
@@ -31,5 +31,18 @@
 
 	for (uint32_t i=0; i<_param->_size_queue; i++)
-	  _queue [i]->_state = IFETCH_QUEUE_STATE_EMPTY;
+          {
+            _queue [i]->_state = IFETCH_QUEUE_STATE_EMPTY;
+            _queue [i]->_address                     = 0; // not necessary
+            _queue [i]->_inst_ifetch_ptr             = 0; // not necessary
+            _queue [i]->_branch_state                = 0; // not necessary
+            _queue [i]->_branch_update_prediction_id = 0; // not necessary
+            _queue [i]->_exception                   = 0; // not necessary
+
+	    for (uint32_t j=0; j<_param->_nb_instruction; j++)
+              {
+            _queue [i]->_instruction             [j] = 0; // not necessary
+            _queue [i]->_instruction_enable      [j] = 0; // not necessary
+              }
+          }
       }
     else
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp	(revision 128)
@@ -60,6 +60,6 @@
         DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth);
         DELETE0_SIGNAL(out_DECOD_EXCEPTION                  ,_param->_size_exception_ifetch);
-        DELETE1_SIGNAL(out_DECOD_VAL                        ,1,_param->_nb_instruction);
-        DELETE1_SIGNAL( in_DECOD_ACK                        ,1,_param->_nb_instruction);
+        DELETE1_SIGNAL(out_DECOD_VAL                        ,_param->_nb_instruction,1);
+        DELETE1_SIGNAL( in_DECOD_ACK                        ,_param->_nb_instruction,1);
         DELETE1_SIGNAL(out_DECOD_INSTRUCTION                ,_param->_nb_instruction,_param->_size_instruction);
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/include/Branch_Target_Buffer_Glue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/include/Branch_Target_Buffer_Glue.h	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/include/Branch_Target_Buffer_Glue.h	(revision 128)
@@ -82,5 +82,5 @@
   public    : SC_IN (Tcontrol_t         ) ***  in_PREDICT_REGISTER_IS_ACCURATE   ; //[nb_inst_predict][associativity]
 
-  public    : SC_IN (Tptr_t             )  **  in_PREDICT_SORT_VAL               ; //[nb_inst_predict]
+  public    : SC_IN (Tcontrol_t         )  **  in_PREDICT_SORT_VAL               ; //[nb_inst_predict]
   public    : SC_IN (Tptr_t             )  **  in_PREDICT_SORT_INDEX             ; //[nb_inst_predict]
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_allocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_allocation.cpp	(revision 128)
@@ -74,6 +74,6 @@
 	if (_param->_have_port_victim)
 	  {
-	ALLOC1_SIGNAL_IN ( in_PREDICT_SORT_VAL  ,"sort_val"  ,Tptr_t,1);
-	ALLOC1_SIGNAL_IN ( in_PREDICT_SORT_INDEX,"sort_index",Tptr_t,_param->_size_victim);
+	ALLOC1_SIGNAL_IN ( in_PREDICT_SORT_VAL      , "sort_val"      ,Tcontrol_t         ,1);
+	ALLOC1_SIGNAL_IN ( in_PREDICT_SORT_INDEX    , "sort_index"    ,Tptr_t             ,_param->_size_victim);
 
 	ALLOC1_SIGNAL_OUT(out_PREDICT_VICTIM_VAL    , "victim_val"    ,Tcontrol_t         , 1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp	(revision 128)
@@ -38,4 +38,5 @@
         log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * val          : %d",val         );
         log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * register_ack : %d",register_ack);
+        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * port_victim  : %d",_param->_have_port_victim);
         log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * sort_val     : %d",sort_val    );
         log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * victim_ack   : %d",victim_ack  );
@@ -51,4 +52,5 @@
 
 	// Multiplexor
+
 	PORT_WRITE(out_PREDICT_HIT          [i],hit);
 	PORT_WRITE(out_PREDICT_ADDRESS_SRC  [i],address_src);
@@ -64,4 +66,5 @@
                                                     victim_ack
                                                     ));
+
 	PORT_WRITE(out_PREDICT_REGISTER_VAL   [i], (
                                                     val          and 
@@ -84,4 +87,5 @@
 	PORT_WRITE(out_PREDICT_VICTIM_INDEX   [i], index);
 	  }
+
       }
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp	(revision 128)
@@ -29,5 +29,14 @@
 	for (uint32_t i=0; i<_param->_size_bank; i++)
 	  for (uint32_t j=0; j<_param->_associativity; j++)
-	    reg_BTB [i][j]._val = false;
+            {
+              reg_BTB [i][j]._val              = false;
+              reg_BTB [i][j]._context          = 0; // not necessary
+              reg_BTB [i][j]._address_dest_val = 0; // not necessary
+              reg_BTB [i][j]._address_src      = 0; // not necessary
+              reg_BTB [i][j]._address_dest     = 0; // not necessary
+              reg_BTB [i][j]._condition        = 0; // not necessary
+              reg_BTB [i][j]._last_take        = 0; // not necessary
+              reg_BTB [i][j]._accurate         = 0; // not necessary
+            }
       }
     else
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_deallocation.cpp	(revision 128)
@@ -64,7 +64,7 @@
       {
 	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
-	  delete _component_sort [i];
+        delete    _component_sort [i];
 	delete [] _component_sort;
-	delete _component_victim;
+	delete    _component_victim;
       }
     delete _component_branch_target_buffer_glue;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_statistics_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_statistics_allocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_statistics_allocation.cpp	(revision 128)
@@ -35,5 +35,5 @@
       }
 
-//     _stat->add_stat(_component_branch_target_buffer_glue    ->_stat);
+    _stat->add_stat(_component_branch_target_buffer_glue    ->_stat);
     _stat->add_stat(_component_branch_target_buffer_register->_stat);
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Parameters.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Parameters.cpp	(revision 128)
@@ -80,4 +80,9 @@
   {
     log_begin(Meta_Predictor_Glue,FUNCTION);
+
+    DELETE1(_predictor_history_mask     ,_nb_predictor);
+    DELETE1(_predictor_history_shift_msb,_nb_predictor);
+    DELETE1(_predictor_history_shift    ,_nb_predictor);
+
     log_end(Meta_Predictor_Glue,FUNCTION);
   };
@@ -88,8 +93,4 @@
   {
     log_begin(Meta_Predictor_Glue,FUNCTION);
-
-    DELETE1(_predictor_history_mask ,_nb_predictor);
-    DELETE1(_predictor_history_shift,_nb_predictor);
-
     log_end(Meta_Predictor_Glue,FUNCTION);
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_deallocation.cpp	(revision 128)
@@ -45,6 +45,8 @@
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
-    DELETE0(_component_glue);
-    DELETE1(_component_two_level_branch_predictor,_param->_nb_predictor);
+    delete    _component_glue;
+    for (uint32_t i=0; i<_param->_nb_predictor; ++i)
+    delete    _component_two_level_branch_predictor [i];
+    delete [] _component_two_level_branch_predictor;
 
     delete _component;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_statistics_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_statistics_allocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_statistics_allocation.cpp	(revision 128)
@@ -28,4 +28,8 @@
 		      "Meta_Predictor",
 		      param_statistics);
+
+    for (uint32_t i=0; i<_param->_nb_predictor; ++i)
+    _stat->add_stat(_component_two_level_branch_predictor [i]->_stat);
+    _stat->add_stat(_component_glue                          ->_stat);
     
     log_end(Meta_Predictor,FUNCTION);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Parameters.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Parameters.cpp	(revision 128)
@@ -122,5 +122,8 @@
     log_begin(Meta_Predictor,FUNCTION);
 
-    DELETE1(_param_two_level_branch_predictor, _nb_predictor);
+    delete    _param_glue;
+    for (uint32_t i=0; i<_nb_predictor; ++i)
+    delete    _param_two_level_branch_predictor [i];
+    delete [] _param_two_level_branch_predictor;
 
     DELETE1(_predictor_size_history          , _nb_predictor);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_statistics_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_statistics_allocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_statistics_allocation.cpp	(revision 128)
@@ -28,5 +28,7 @@
 		      param_statistics);
 
-    _stat->add_stat(_component_glue->_stat);
+    if (_param->_have_component_meta_predictor)
+    _stat->add_stat(_component_meta_predictor->_stat);
+    _stat->add_stat(_component_glue          ->_stat);
     
     log_printf(FUNC,Direction,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp	(revision 128)
@@ -37,4 +37,7 @@
 // 	    reg_PREDICT_BOTTOM [i] = 0;
 	    reg_PREDICT_NB_ELT [i] = 0;
+
+            for (uint32_t j=0; j<_param->_size_queue [i]; ++j)
+            reg_stack [i][j]._address = 0; // not necessary
 	  }
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters.cpp	(revision 128)
@@ -63,5 +63,5 @@
     for (uint32_t i=0; i<_nb_thread; i++)
       _have_thread[i] = false;
-    for (uint32_t i=0; i<_nb_context; i++)
+    for (uint32_t i=0; i<_nb_thread; i++)
       _have_thread[_translate_num_context_to_num_thread [i]] = true;
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp	(revision 128)
@@ -172,9 +172,12 @@
 
 #if defined(DEBUG) and defined(DEBUG_Update_Prediction_Table) and (DEBUG_Update_Prediction_Table == true)
-    for (uint32_t i=0; i<_param->_nb_thread; ++i)
-      if (_param->_have_thread [i])
-        {
-          branchement_log_file [i].close();
-        }
+    {
+      for (uint32_t i=0; i<_param->_nb_thread; ++i)
+        if (_param->_have_thread [i])
+          {
+            branchement_log_file [i].close();
+          }
+      delete [] branchement_log_file;
+    }
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp	(revision 128)
@@ -29,9 +29,13 @@
     delete    _stat;
 
-    DELETE2(_stat_nb_branch_hit            ,_param->_nb_context,MAX_BRANCH_CONDITION);
-    DELETE2(_stat_nb_branch_miss           ,_param->_nb_context,MAX_BRANCH_CONDITION);
-    DELETE1(_stat_nb_branch_unused         ,_param->_nb_context);
-    DELETE1(_stat_ufpt_queue_nb_elt        ,_param->_nb_context);
-    DELETE1(_stat_upt_queue_nb_elt         ,_param->_nb_context);
+    DELETE2(_stat_nb_branch_hit              ,_param->_nb_context,MAX_BRANCH_CONDITION);
+    DELETE2(_stat_nb_branch_miss             ,_param->_nb_context,MAX_BRANCH_CONDITION);
+    DELETE1(_stat_nb_branch_unused           ,_param->_nb_context);
+
+    DELETE1(_stat_nb_branch_ifetch_prediction,_param->_nb_context);
+    DELETE1(_stat_nb_branch_accurate         ,_param->_nb_context);
+
+    DELETE1(_stat_ufpt_queue_nb_elt          ,_param->_nb_context);
+    DELETE1(_stat_upt_queue_nb_elt           ,_param->_nb_context);
     
     log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp	(revision 128)
@@ -34,5 +34,15 @@
 	  {
             for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
-              reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
+              {
+            reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state            = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
+            reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition        = 0; // not necessary
+            reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src      = 0; // not necessary
+            reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest     = 0; // not necessary
+            reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take        = 0; // not necessary
+            reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate      = 0; // not necessary
+            reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history          = 0; // not necessary
+            reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras      = 0; // not necessary
+            reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras        = 0; // not necessary
+              }
             reg_UFPT_BOTTOM          [i] = 0;
             reg_UFPT_TOP             [i] = 0;
@@ -42,5 +52,20 @@
                                                                 
             for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
-              reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY;
+              {
+            reg_UPDATE_PREDICTION_TABLE [i][j]._state            = UPDATE_PREDICTION_STATE_EMPTY;
+            reg_UPDATE_PREDICTION_TABLE [i][j]._condition        = 0; // not necessary
+            reg_UPDATE_PREDICTION_TABLE [i][j]._address_src      = 0; // not necessary
+            reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest     = 0; // not necessary
+            reg_UPDATE_PREDICTION_TABLE [i][j]._last_take        = 0; // not necessary
+            reg_UPDATE_PREDICTION_TABLE [i][j]._good_take        = 0; // not necessary
+            reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate      = 0; // not necessary
+            reg_UPDATE_PREDICTION_TABLE [i][j]._history          = 0; // not necessary
+            reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras      = 0; // not necessary
+            reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras        = 0; // not necessary
+            reg_UPDATE_PREDICTION_TABLE [i][j]._ifetch_prediction= 0; // not necessary
+            reg_UPDATE_PREDICTION_TABLE [i][j]._miss_commit      = 0; // not necessary
+            reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok        = 0; // not necessary
+            reg_UPDATE_PREDICTION_TABLE [i][j]._miss_prediction  = 0; // not necessary
+              }
             reg_UPT_BOTTOM           [i] = 0;
             reg_UPT_TOP              [i] = 0;
@@ -54,7 +79,16 @@
             reg_UPT_EVENT_STATE      [i] = UPT_EVENT_STATE_OK;
 
-//             reg_EVENT_VAL            [i] = false;
-//             reg_EVENT_STATE          [i] = EVENT_STATE_OK;
-//             reg_EVENT_IS_BRANCH      [i] = true;
+            reg_EVENT_UPT_PTR          [i] = 0; // not necessary
+            reg_EVENT_UPT_FULL         [i] = 0; // not necessary
+
+//          reg_EVENT_STATE            [i] = EVENT_STATE_OK; // not necessary
+//          reg_EVENT_IS_BRANCH        [i] = true          ; // not necessary
+
+            reg_EVENT_DEPTH            [i] = 0; // not necessary
+            reg_EVENT_ADDRESS_SRC      [i] = 0; // not necessary
+            reg_EVENT_ADDRESS_DEST_VAL [i] = 0; // not necessary
+            reg_EVENT_ADDRESS_DEST     [i] = 0; // not necessary
+            reg_EVENT_CAN_CONTINUE     [i] = 0; // not necessary
+
           }
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp	(revision 128)
@@ -66,5 +66,5 @@
         DELETE1_SIGNAL( in_BRANCH_EVENT_ACK              ,_param->_nb_context,1);
 //      DELETE1_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID       ,_param->_nb_context,_param->_size_context_id);
-//      DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH            ,_param->_nb_context,_param->_size_depth);
+        DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH            ,_param->_nb_context,_param->_size_depth);
 //      DELETE1_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION  ,_param->_nb_context,1);
         DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC      ,_param->_nb_context,_param->_size_instruction_address);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/main.cpp	(revision 128)
@@ -223,4 +223,6 @@
       
       test (name,param);
+
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp	(revision 128)
@@ -47,4 +47,81 @@
   sc_clock              *  in_CLOCK  = new sc_clock ("clock", 1.0, 0.5);	 
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
+
+  sc_signal<Tcontrol_t           >  ** out_ICACHE_REQ_VAL                 ;
+  sc_signal<Tcontrol_t           >  **  in_ICACHE_REQ_ACK                 ;
+//sc_signal<Tcontext_t           >  ** out_ICACHE_REQ_THREAD_ID           ;
+  sc_signal<Tpacket_t            >  ** out_ICACHE_REQ_PACKET_ID           ;
+  sc_signal<Ticache_instruction_t>  ** out_ICACHE_REQ_ADDRESS             ;
+  sc_signal<Ticache_type_t       >  ** out_ICACHE_REQ_TYPE                ;
+  sc_signal<Tcontrol_t           >  **  in_ICACHE_RSP_VAL                 ;
+  sc_signal<Tcontrol_t           >  ** out_ICACHE_RSP_ACK                 ;
+//sc_signal<Tcontext_t           >  **  in_ICACHE_RSP_THREAD_ID           ;
+  sc_signal<Tpacket_t            >  **  in_ICACHE_RSP_PACKET_ID           ;
+  sc_signal<Ticache_instruction_t> ***  in_ICACHE_RSP_INSTRUCTION         ;
+  sc_signal<Ticache_error_t      >  **  in_ICACHE_RSP_ERROR               ;
+  sc_signal<Tcontrol_t           >  ** out_DECOD_VAL                      ;
+  sc_signal<Tcontrol_t           >  **  in_DECOD_ACK                      ;
+  sc_signal<Tcontext_t           >  ** out_DECOD_CONTEXT_ID               ;
+  sc_signal<Tdepth_t             >  ** out_DECOD_DEPTH                    ;
+  sc_signal<Ttype_t              >  ** out_DECOD_TYPE                     ;
+  sc_signal<Toperation_t         >  ** out_DECOD_OPERATION                ;
+  sc_signal<Tcontrol_t           >  ** out_DECOD_NO_EXECUTE               ;
+  sc_signal<Tcontrol_t           >  ** out_DECOD_IS_DELAY_SLOT            ;
+  sc_signal<Tgeneral_data_t      >  ** out_DECOD_ADDRESS                  ;
+  sc_signal<Tgeneral_data_t      >  ** out_DECOD_ADDRESS_NEXT             ;
+  sc_signal<Tcontrol_t           >  ** out_DECOD_HAS_IMMEDIAT             ;
+  sc_signal<Tgeneral_data_t      >  ** out_DECOD_IMMEDIAT                 ;
+  sc_signal<Tcontrol_t           >  ** out_DECOD_READ_RA                  ;
+  sc_signal<Tgeneral_address_t   >  ** out_DECOD_NUM_REG_RA               ;
+  sc_signal<Tcontrol_t           >  ** out_DECOD_READ_RB                  ;
+  sc_signal<Tgeneral_address_t   >  ** out_DECOD_NUM_REG_RB               ;
+  sc_signal<Tcontrol_t           >  ** out_DECOD_READ_RC                  ;
+  sc_signal<Tspecial_address_t   >  ** out_DECOD_NUM_REG_RC               ;
+  sc_signal<Tcontrol_t           >  ** out_DECOD_WRITE_RD                 ;
+  sc_signal<Tgeneral_address_t   >  ** out_DECOD_NUM_REG_RD               ;
+  sc_signal<Tcontrol_t           >  ** out_DECOD_WRITE_RE                 ;
+  sc_signal<Tspecial_address_t   >  ** out_DECOD_NUM_REG_RE               ;
+  sc_signal<Texception_t         >  ** out_DECOD_EXCEPTION_USE            ;
+  sc_signal<Texception_t         >  ** out_DECOD_EXCEPTION                ;
+  sc_signal<Tcontrol_t           >  **  in_BRANCH_COMPLETE_VAL            ;
+  sc_signal<Tcontrol_t           >  ** out_BRANCH_COMPLETE_ACK            ;
+  sc_signal<Tcontext_t           >  **  in_BRANCH_COMPLETE_CONTEXT_ID     ;
+  sc_signal<Tdepth_t             >  **  in_BRANCH_COMPLETE_DEPTH          ;
+  sc_signal<Taddress_t           >  **  in_BRANCH_COMPLETE_ADDRESS        ;
+  sc_signal<Tcontrol_t           >  **  in_BRANCH_COMPLETE_NO_SEQUENCE    ;
+  sc_signal<Tcontrol_t           >  ** out_BRANCH_COMPLETE_MISS_PREDICTION;
+  sc_signal<Tcontrol_t           >   *  in_COMMIT_EVENT_VAL               ;
+  sc_signal<Tcontrol_t           >   * out_COMMIT_EVENT_ACK               ;
+  sc_signal<Tcontext_t           >   *  in_COMMIT_EVENT_CONTEXT_ID        ;
+  sc_signal<Tdepth_t             >   *  in_COMMIT_EVENT_DEPTH             ;
+  sc_signal<Tevent_type_t        >   *  in_COMMIT_EVENT_TYPE              ;
+  sc_signal<Tcontrol_t           >   *  in_COMMIT_EVENT_IS_DELAY_SLOT     ;
+  sc_signal<Taddress_t           >   *  in_COMMIT_EVENT_ADDRESS           ;
+  sc_signal<Tcontrol_t           >   *  in_COMMIT_EVENT_ADDRESS_EPCR_VAL  ;
+  sc_signal<Taddress_t           >   *  in_COMMIT_EVENT_ADDRESS_EPCR      ;
+  sc_signal<Tcontrol_t           >   *  in_COMMIT_EVENT_ADDRESS_EEAR_VAL  ;
+  sc_signal<Tgeneral_data_t      >   *  in_COMMIT_EVENT_ADDRESS_EEAR      ;
+  sc_signal<Tcontrol_t           >  ** out_EVENT_VAL                      ;
+  sc_signal<Tcontrol_t           >  **  in_EVENT_ACK                      ;
+  sc_signal<Taddress_t           >  ** out_EVENT_ADDRESS                  ;
+  sc_signal<Taddress_t           >  ** out_EVENT_ADDRESS_NEXT             ;
+  sc_signal<Tcontrol_t           >  ** out_EVENT_ADDRESS_NEXT_VAL         ;
+  sc_signal<Tcontrol_t           >  ** out_EVENT_IS_DS_TAKE               ;
+  sc_signal<Tcontrol_t           >  ** out_SPR_EVENT_VAL                  ;
+  sc_signal<Tcontrol_t           >  **  in_SPR_EVENT_ACK                  ;
+  sc_signal<Tspr_t               >  ** out_SPR_EVENT_EPCR                 ;
+  sc_signal<Tcontrol_t           >  ** out_SPR_EVENT_EEAR_WEN             ;
+  sc_signal<Tspr_t               >  ** out_SPR_EVENT_EEAR                 ;
+  sc_signal<Tcontrol_t           >  ** out_SPR_EVENT_SR_DSX               ;
+  sc_signal<Tcontrol_t           >  ** out_SPR_EVENT_SR_TO_ESR            ;
+  sc_signal<Tcounter_t           >  **  in_NB_INST_COMMIT_ALL             ;
+  sc_signal<Tcounter_t           >  **  in_NB_INST_COMMIT_MEM             ;
+  sc_signal<Tcounter_t           >  ** out_NB_INST_DECOD_ALL              ;
+  sc_signal<Tdepth_t             >  ** out_DEPTH_MIN                      ;
+  sc_signal<Tdepth_t             >  ** out_DEPTH_MAX                      ;
+  sc_signal<Tcontrol_t           >  ** out_DEPTH_FULL                     ;
+  sc_signal<Tcontrol_t           >  **  in_SPR_SR_IEE                     ;
+  sc_signal<Tcontrol_t           >  **  in_SPR_SR_EPH                     ;
+  sc_signal<Tcontrol_t           >  **  in_INTERRUPT_ENABLE               ;
 
   ALLOC1_SC_SIGNAL(out_ICACHE_REQ_VAL                 ,"out_ICACHE_REQ_VAL                 ",Tcontrol_t           ,_param->_nb_context);
@@ -68,7 +145,5 @@
   ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE               ,"out_DECOD_NO_EXECUTE               ",Tcontrol_t           ,_param->_sum_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT            ,"out_DECOD_IS_DELAY_SLOT            ",Tcontrol_t           ,_param->_sum_inst_decod);
-#ifdef DEBUG
   ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS                  ,"out_DECOD_ADDRESS                  ",Tgeneral_data_t      ,_param->_sum_inst_decod);
-#endif
   ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT             ,"out_DECOD_ADDRESS_NEXT             ",Tgeneral_data_t      ,_param->_sum_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT             ,"out_DECOD_HAS_IMMEDIAT             ",Tcontrol_t           ,_param->_sum_inst_decod);
@@ -325,7 +400,5 @@
   DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE               ,_param->_sum_inst_decod);
   DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT            ,_param->_sum_inst_decod);
-#ifdef DEBUG
   DELETE1_SC_SIGNAL(out_DECOD_ADDRESS                  ,_param->_sum_inst_decod);
-#endif
   DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT             ,_param->_sum_inst_decod);
   DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT             ,_param->_sum_inst_decod);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp	(revision 128)
@@ -109,7 +109,7 @@
         DELETE1_SIGNAL(out_NB_INST_DECOD_ALL                ,_param->_nb_context,_param->_size_nb_inst_decod);
 
-        DELETE1_SIGNAL(out_DEPTH_MIN                        ,_param->_nb_context,_param->_size_depth  );
-        DELETE1_SIGNAL(out_DEPTH_MAX                        ,_param->_nb_context,_param->_size_depth+1);
-        DELETE1_SIGNAL(out_DEPTH_FULL                       ,_param->_nb_context,_param->_size_depth+1);
+        DELETE1_SIGNAL(out_DEPTH_MIN                        ,_param->_nb_context,_param->_size_depth);
+        DELETE1_SIGNAL(out_DEPTH_MAX                        ,_param->_nb_context,_param->_size_depth);
+        DELETE1_SIGNAL(out_DEPTH_FULL                       ,_param->_nb_context,1);
 
         DELETE1_SIGNAL( in_SPR_SR_IEE                       ,_param->_nb_context,1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp	(revision 128)
@@ -7,4 +7,5 @@
 
 #include "Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h"
+#include "Behavioural/include/Allocation.h"
 #include "Common/include/Max.h"
 
@@ -110,9 +111,9 @@
     uint32_t size_instruction_address   = size_general_data - 2;
 
-    _array_size_depth                   = new uint32_t [_nb_context];
+    ALLOC1(_array_size_depth            ,uint32_t,_nb_context);
     for (uint32_t i=0; i<_nb_context; i++)
       _array_size_depth [i] = log2(_upt_size_queue[i]);
     
-    _array_size_nb_inst_decod = new uint32_t [_nb_decod_unit];
+    ALLOC1(_array_size_nb_inst_decod    ,uint32_t,_nb_decod_unit);
     for (uint32_t i=0; i<_nb_decod_unit; i++)
       _array_size_nb_inst_decod [i] = log2(_size_decod_queue[i]+1);
@@ -159,15 +160,15 @@
        );
 
-    _translate_context_id_from_decod_unit= new std::vector<uint32_t> [_nb_decod_unit];
+    ALLOC1(_translate_context_id_from_decod_unit,std::vector<uint32_t>,_nb_decod_unit);
 
     for (uint32_t i=0; i<_nb_context; ++i)
       _translate_context_id_from_decod_unit [_link_context_to_decod_unit[i]].push_back(i);
 
-    _decod_unit_nb_context               = new uint32_t    [_nb_decod_unit];
-    _decod_unit_nb_inst_fetch            = new uint32_t *  [_nb_decod_unit];
-    _decod_unit_nb_branch_speculated     = new uint32_t *  [_nb_decod_unit];
-//     _decod_unit_depth                    = new uint32_t *  [_nb_decod_unit];
-    _decod_unit_instruction_implemeted   = new bool     ** [_nb_decod_unit];
-//     _have_port_decod_unit_context_id     = new bool        [_nb_decod_unit];
+    ALLOC1(_decod_unit_nb_context            ,uint32_t,_nb_decod_unit);
+    ALLOC2(_decod_unit_nb_inst_fetch         ,uint32_t,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size());
+    ALLOC2(_decod_unit_nb_branch_speculated  ,uint32_t,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size());
+//  ALLOC2(_decod_unit_depth                 ,uint32_t,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size());
+    ALLOC3(_decod_unit_instruction_implemeted,bool    ,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size(),NB_INSTRUCTION);
+//  ALLOC2(_have_port_decod_unit_context_id  ,bool    ,_nb_decod_unit);
     _sum_inst_decod                      = 0;
     
@@ -179,9 +180,5 @@
 
         _decod_unit_nb_context             [i] = size;
-        _decod_unit_nb_inst_fetch          [i] = new uint32_t   [size];
-//         _decod_unit_depth                  [i] = new uint32_t   [size];
-        _decod_unit_nb_branch_speculated   [i] = new uint32_t   [size];
-        _decod_unit_instruction_implemeted [i] = new bool     * [size];
-//         _have_port_decod_unit_context_id   [i] = size > 0;
+//      _have_port_decod_unit_context_id   [i] = size > 0;
 
         for (uint32_t j=0; j<size; ++j)
@@ -191,6 +188,5 @@
             _decod_unit_nb_inst_fetch          [i][j] = _nb_inst_fetch  [x];
             _decod_unit_nb_branch_speculated   [i][j] = _upt_size_queue [x];
-//             _decod_unit_depth                  [i][j] = log2(_upt_size_queue[x]);
-            _decod_unit_instruction_implemeted [i][j] = new bool [NB_INSTRUCTION];
+//          _decod_unit_depth                  [i][j] = log2(_upt_size_queue[x]);
 
             for (uint32_t k=0; k<NB_INSTRUCTION; ++k)
@@ -302,25 +298,14 @@
     delete [] _param_ifetch_unit    ;
 
-//     delete [] _size_ifetch_queue_ptr;
-//     delete [] _size_nb_inst_decod;
-    delete [] _array_size_depth;
-    for (uint32_t i=0; i<_nb_context; ++i)
-      {
-        for (uint32_t j=0; j<_translate_context_id_from_decod_unit [i].size(); ++j)
-          delete [] _decod_unit_instruction_implemeted [i][j];
-
-        delete [] _decod_unit_nb_inst_fetch          [i];
-//         delete [] _decod_unit_depth                  [i];
-        delete [] _decod_unit_nb_branch_speculated   [i];
-        delete [] _decod_unit_instruction_implemeted [i];
-      }
-    delete [] _decod_unit_nb_inst_fetch         ;
-//     delete [] _decod_unit_depth                 ;
-    delete [] _decod_unit_nb_branch_speculated  ;
-    delete [] _decod_unit_instruction_implemeted;
-
-//     delete [] _have_port_decod_unit_context_id;
-    delete [] _decod_unit_nb_context               ;
-    delete [] _translate_context_id_from_decod_unit;
+//  DELETE2(_have_port_decod_unit_context_id     ,_nb_decod_unit);
+    DELETE3(_decod_unit_instruction_implemeted   ,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size(),NB_INSTRUCTION);
+//  DELETE2(_decod_unit_depth                    ,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size());
+    DELETE2(_decod_unit_nb_branch_speculated     ,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size());
+    DELETE2(_decod_unit_nb_inst_fetch            ,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size());
+    DELETE1(_decod_unit_nb_context               ,_nb_decod_unit);
+
+    DELETE1(_translate_context_id_from_decod_unit,_nb_decod_unit);
+    DELETE1(_array_size_nb_inst_decod            ,_nb_decod_unit);
+    DELETE1(_array_size_depth                    ,_nb_context);
 
     log_end(Front_end,FUNCTION);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp	(revision 128)
@@ -142,4 +142,6 @@
       
       test (name,param);
+
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp	(revision 128)
@@ -29,5 +29,5 @@
 #endif
 
-  simulation_init(0,0);
+  simulation_init(0,0,0,false,false);
 
   debug_idle_cycle = CYCLE_MAX;
@@ -62,4 +62,139 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
+  sc_signal<Tcontrol_t        > ***  in_INSERT_VAL                     ;
+  sc_signal<Tcontrol_t        > *** out_INSERT_ACK                     ;
+  sc_signal<Tcontext_t        > ***  in_INSERT_FRONT_END_ID            ;
+  sc_signal<Tcontext_t        > ***  in_INSERT_CONTEXT_ID              ;
+  sc_signal<Tpacket_t         > *** out_INSERT_PACKET_ID               ;
+//sc_signal<Tcontext_t        > ***  in_INSERT_RENAME_UNIT_ID          ;
+  sc_signal<Tdepth_t          > ***  in_INSERT_DEPTH                   ;
+  sc_signal<Ttype_t           > ***  in_INSERT_TYPE                    ;
+  sc_signal<Toperation_t      > ***  in_INSERT_OPERATION               ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_NO_EXECUTE              ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_LAST_EVENT              ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_IS_DELAY_SLOT           ;
+  sc_signal<Taddress_t        > ***  in_INSERT_ADDRESS                 ;
+  sc_signal<Taddress_t        > ***  in_INSERT_ADDRESS_NEXT            ;
+  sc_signal<Texception_t      > ***  in_INSERT_EXCEPTION               ;
+  sc_signal<Texception_t      > ***  in_INSERT_EXCEPTION_USE           ;
+  sc_signal<Tlsq_ptr_t        > ***  in_INSERT_STORE_QUEUE_PTR_WRITE   ;
+  sc_signal<Tlsq_ptr_t        > ***  in_INSERT_LOAD_QUEUE_PTR_WRITE    ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_READ_RA                 ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RA_LOG          ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RA_PHY          ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_READ_RB                 ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RB_LOG          ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RB_PHY          ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_READ_RC                 ;
+  sc_signal<Tspecial_address_t> ***  in_INSERT_NUM_REG_RC_LOG          ;
+  sc_signal<Tspecial_address_t> ***  in_INSERT_NUM_REG_RC_PHY          ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_WRITE_RD                ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RD_LOG          ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RD_PHY_OLD      ;
+  sc_signal<Tgeneral_address_t> ***  in_INSERT_NUM_REG_RD_PHY_NEW      ;
+  sc_signal<Tcontrol_t        > ***  in_INSERT_WRITE_RE                ;
+  sc_signal<Tspecial_address_t> ***  in_INSERT_NUM_REG_RE_LOG          ;
+  sc_signal<Tspecial_address_t> ***  in_INSERT_NUM_REG_RE_PHY_OLD      ;
+  sc_signal<Tspecial_address_t> ***  in_INSERT_NUM_REG_RE_PHY_NEW      ;
+
+  sc_signal<Tcontrol_t        > *** out_RETIRE_VAL                     ;
+  sc_signal<Tcontrol_t        > ***  in_RETIRE_ACK                     ;
+  sc_signal<Tcontext_t        > *** out_RETIRE_FRONT_END_ID            ;
+  sc_signal<Tcontext_t        > *** out_RETIRE_CONTEXT_ID              ;
+//sc_signal<Tcontext_t        > *** out_RETIRE_RENAME_UNIT_ID          ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_USE_STORE_QUEUE         ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_USE_LOAD_QUEUE          ;
+  sc_signal<Tlsq_ptr_t        > *** out_RETIRE_STORE_QUEUE_PTR_WRITE   ;
+  sc_signal<Tlsq_ptr_t        > *** out_RETIRE_LOAD_QUEUE_PTR_WRITE    ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_READ_RA                 ;
+  sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RA_PHY          ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_READ_RB                 ;
+  sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RB_PHY          ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_READ_RC                 ;
+  sc_signal<Tspecial_address_t> *** out_RETIRE_NUM_REG_RC_PHY          ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_WRITE_RD                ;
+  sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RD_LOG          ;
+  sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RD_PHY_OLD      ;
+  sc_signal<Tgeneral_address_t> *** out_RETIRE_NUM_REG_RD_PHY_NEW      ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_WRITE_RE                ;
+  sc_signal<Tspecial_address_t> *** out_RETIRE_NUM_REG_RE_LOG          ;
+  sc_signal<Tspecial_address_t> *** out_RETIRE_NUM_REG_RE_PHY_OLD      ;
+  sc_signal<Tspecial_address_t> *** out_RETIRE_NUM_REG_RE_PHY_NEW      ;
+
+  sc_signal<Tcontrol_t        > *** out_RETIRE_EVENT_VAL               ;
+  sc_signal<Tcontrol_t        > ***  in_RETIRE_EVENT_ACK               ;
+  sc_signal<Tevent_state_t    > *** out_RETIRE_EVENT_STATE             ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_EVENT_STOP              ;
+
+  sc_signal<Tcontrol_t        >  **  in_COMMIT_VAL                     ;
+  sc_signal<Tcontrol_t        >  ** out_COMMIT_ACK                     ;
+  sc_signal<Tcontrol_t        >  **  in_COMMIT_WEN                     ;
+  sc_signal<Tpacket_t         >  **  in_COMMIT_PACKET_ID               ;
+//sc_signal<Toperation_t      >  **  in_COMMIT_OPERATION               ;
+//sc_signal<Ttype_t           >  **  in_COMMIT_TYPE                    ;
+  sc_signal<Tspecial_data_t   >  **  in_COMMIT_FLAGS                   ;
+  sc_signal<Texception_t      >  **  in_COMMIT_EXCEPTION               ;
+  sc_signal<Tcontrol_t        >  **  in_COMMIT_NO_SEQUENCE             ;
+  sc_signal<Taddress_t        >  **  in_COMMIT_ADDRESS                 ;
+  sc_signal<Tgeneral_address_t>  ** out_COMMIT_NUM_REG_RD              ;
+
+  sc_signal<Tcontrol_t        >  ** out_REEXECUTE_VAL                  ;
+  sc_signal<Tcontrol_t        >  **  in_REEXECUTE_ACK                  ;
+  sc_signal<Tcontext_t        >  ** out_REEXECUTE_CONTEXT_ID           ;
+  sc_signal<Tcontext_t        >  ** out_REEXECUTE_FRONT_END_ID         ;
+  sc_signal<Tpacket_t         >  ** out_REEXECUTE_PACKET_ID            ;
+  sc_signal<Toperation_t      >  ** out_REEXECUTE_OPERATION            ;
+  sc_signal<Ttype_t           >  ** out_REEXECUTE_TYPE                 ;
+  sc_signal<Tlsq_ptr_t        >  ** out_REEXECUTE_STORE_QUEUE_PTR_WRITE;
+
+  sc_signal<Tcontrol_t        >  ** out_BRANCH_COMPLETE_VAL            ;
+  sc_signal<Tcontrol_t        >  **  in_BRANCH_COMPLETE_ACK            ;
+  sc_signal<Tcontext_t        >  ** out_BRANCH_COMPLETE_CONTEXT_ID     ;
+  sc_signal<Tcontext_t        >  ** out_BRANCH_COMPLETE_FRONT_END_ID   ;
+  sc_signal<Tdepth_t          >  ** out_BRANCH_COMPLETE_DEPTH          ;
+  sc_signal<Taddress_t        >  ** out_BRANCH_COMPLETE_ADDRESS        ;
+  sc_signal<Tcontrol_t        >  ** out_BRANCH_COMPLETE_NO_SEQUENCE    ;
+  sc_signal<Tcontrol_t        >  **  in_BRANCH_COMPLETE_MISS_PREDICTION;
+
+  sc_signal<Tcontrol_t        >   * out_UPDATE_VAL                     ;
+  sc_signal<Tcontrol_t        >   *  in_UPDATE_ACK                     ;
+  sc_signal<Tcontext_t        >   * out_UPDATE_CONTEXT_ID              ;
+  sc_signal<Tcontext_t        >   * out_UPDATE_FRONT_END_ID            ;
+  sc_signal<Tdepth_t          >   * out_UPDATE_DEPTH                   ;
+  sc_signal<Tevent_type_t     >   * out_UPDATE_TYPE                    ;
+  sc_signal<Tcontrol_t        >   * out_UPDATE_IS_DELAY_SLOT           ;
+  sc_signal<Taddress_t        >   * out_UPDATE_ADDRESS                 ;
+  sc_signal<Tcontrol_t        >   * out_UPDATE_ADDRESS_EPCR_VAL        ;
+  sc_signal<Taddress_t        >   * out_UPDATE_ADDRESS_EPCR            ;
+  sc_signal<Tcontrol_t        >   * out_UPDATE_ADDRESS_EEAR_VAL        ;
+  sc_signal<Tgeneral_data_t   >   * out_UPDATE_ADDRESS_EEAR            ;
+
+  sc_signal<Tcontrol_t        > ***  in_EVENT_VAL                      ;
+  sc_signal<Tcontrol_t        > *** out_EVENT_ACK                      ;
+  sc_signal<Taddress_t        > ***  in_EVENT_ADDRESS                  ;
+  sc_signal<Taddress_t        > ***  in_EVENT_ADDRESS_NEXT             ;
+  sc_signal<Tcontrol_t        > ***  in_EVENT_ADDRESS_NEXT_VAL         ;
+  sc_signal<Tcontrol_t        > ***  in_EVENT_IS_DS_TAKE               ;
+
+  sc_signal<Tcounter_t        > *** out_NB_INST_COMMIT_ALL             ;
+  sc_signal<Tcounter_t        > *** out_NB_INST_COMMIT_MEM             ;
+  sc_signal<Tcounter_t        > ***  in_NB_INST_DECOD_ALL              ;
+  sc_signal<Tdepth_t          > ***  in_DEPTH_MIN                      ;
+  sc_signal<Tdepth_t          > ***  in_DEPTH_MAX                      ;
+  sc_signal<Tcontrol_t        > ***  in_DEPTH_FULL                     ;
+
+  sc_signal<Tcontrol_t        > ***  in_SPR_READ_SR_OVE                ;
+
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_VAL                  ;
+  sc_signal<Tcontrol_t        > ***  in_SPR_WRITE_ACK                  ;
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_SR_F_VAL             ;
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_SR_F                 ;
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_SR_CY_VAL            ;
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_SR_CY                ;
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_SR_OV_VAL            ;
+  sc_signal<Tcontrol_t        > *** out_SPR_WRITE_SR_OV                ;
+
+  sc_signal<bool              >   * out_INFO_ROB_EMPTY                 ;
+
   ALLOC2_SC_SIGNAL( in_INSERT_VAL                     ," in_INSERT_VAL                     ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   ALLOC2_SC_SIGNAL(out_INSERT_ACK                     ,"out_INSERT_ACK                     ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -72,8 +207,7 @@
   ALLOC2_SC_SIGNAL( in_INSERT_OPERATION               ," in_INSERT_OPERATION               ",Toperation_t      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   ALLOC2_SC_SIGNAL( in_INSERT_NO_EXECUTE              ," in_INSERT_NO_EXECUTE              ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  ALLOC2_SC_SIGNAL( in_INSERT_LAST_EVENT              ," in_INSERT_LAST_EVENT              ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   ALLOC2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT           ," in_INSERT_IS_DELAY_SLOT           ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#ifdef DEBUG
   ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS                 ," in_INSERT_ADDRESS                 ",Taddress_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#endif
   ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT            ," in_INSERT_ADDRESS_NEXT            ",Taddress_t        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION               ," in_INSERT_EXCEPTION               ",Texception_t      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -125,4 +259,5 @@
   ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_ACK               ," in_RETIRE_EVENT_ACK               ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_context[it1]);
   ALLOC2_SC_SIGNAL(out_RETIRE_EVENT_STATE             ,"out_RETIRE_EVENT_STATE             ",Tevent_state_t    ,_param->_nb_front_end,_param->_nb_context[it1]);
+  ALLOC2_SC_SIGNAL(out_RETIRE_EVENT_STOP              ,"out_RETIRE_EVENT_STOP              ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_context[it1]);
 
   ALLOC1_SC_SIGNAL( in_COMMIT_VAL                     ," in_COMMIT_VAL               ",Tcontrol_t        ,_param->_nb_inst_commit);
@@ -137,4 +272,5 @@
   ALLOC1_SC_SIGNAL( in_COMMIT_ADDRESS                 ," in_COMMIT_ADDRESS           ",Taddress_t        ,_param->_nb_inst_commit);
   ALLOC1_SC_SIGNAL(out_COMMIT_NUM_REG_RD              ,"out_COMMIT_NUM_REG_RD        ",Tgeneral_address_t,_param->_nb_inst_commit);
+
   ALLOC1_SC_SIGNAL(out_REEXECUTE_VAL                  ,"out_REEXECUTE_VAL                  ",Tcontrol_t        ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL( in_REEXECUTE_ACK                  ," in_REEXECUTE_ACK                  ",Tcontrol_t        ,_param->_nb_inst_reexecute);
@@ -191,4 +327,6 @@
   ALLOC2_SC_SIGNAL(out_SPR_WRITE_SR_OV                ,"out_SPR_WRITE_SR_OV                ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_context[it1]);
 
+  ALLOC0_SC_SIGNAL(out_INFO_ROB_EMPTY                 ,"out_INFO_ROB_EMPTY                 ",bool              );
+
   /********************************************************
    * Instanciation
@@ -215,4 +353,5 @@
   INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_IS_DELAY_SLOT           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NO_EXECUTE              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_LAST_EVENT              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
 #ifdef DEBUG
   INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -272,4 +411,5 @@
   INSTANCE2_SC_SIGNAL(_Commit_unit, in_RETIRE_EVENT_ACK               ,_param->_nb_front_end,_param->_nb_context[it1]);
   INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_EVENT_STATE             ,_param->_nb_front_end,_param->_nb_context[it1]);
+  INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_EVENT_STOP              ,_param->_nb_front_end,_param->_nb_context[it1]);
   INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_VAL                     ,_param->_nb_inst_commit);
   INSTANCE1_SC_SIGNAL(_Commit_unit,out_COMMIT_ACK                     ,_param->_nb_inst_commit);
@@ -351,4 +491,8 @@
   INSTANCE2_SC_SIGNAL(_Commit_unit,out_SPR_WRITE_SR_OV                ,_param->_nb_front_end,_param->_nb_context[it1]);
 
+#ifdef DEBUG_TEST
+  INSTANCE0_SC_SIGNAL(_Commit_unit,out_INFO_ROB_EMPTY                 );
+#endif
+
   msg(_("<%s> : Start Simulation ............\n"),name.c_str());
     
@@ -378,4 +522,5 @@
   in_NRESET->write(1);  
 
+#ifdef SELFTEST
   LABEL("Loop of Test");
   for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
@@ -435,4 +580,5 @@
 		  in_INSERT_IS_DELAY_SLOT           [i][j]->write(0);
 		  in_INSERT_NO_EXECUTE              [i][j]->write(0);
+		  in_INSERT_LAST_EVENT              [i][j]->write(0);
 		  in_INSERT_ADDRESS_NEXT            [i][j]->write(addr);
 		  in_INSERT_EXCEPTION               [i][j]->write(0);
@@ -608,4 +754,7 @@
 
     }
+#else
+  SC_START(10);
+#endif
 
   /********************************************************
@@ -631,8 +780,7 @@
   DELETE2_SC_SIGNAL( in_INSERT_OPERATION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_NO_EXECUTE              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  DELETE2_SC_SIGNAL( in_INSERT_LAST_EVENT              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#ifdef DEBUG
   DELETE2_SC_SIGNAL( in_INSERT_ADDRESS                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#endif
   DELETE2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_EXCEPTION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -666,10 +814,10 @@
   DELETE2_SC_SIGNAL(out_RETIRE_STORE_QUEUE_PTR_WRITE   ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
   DELETE2_SC_SIGNAL(out_RETIRE_LOAD_QUEUE_PTR_WRITE    ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
-//   DELETE2_SC_SIGNAL(out_RETIRE_READ_RA                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
-//   DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RA_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
-//   DELETE2_SC_SIGNAL(out_RETIRE_READ_RB                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
-//   DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RB_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
-//   DELETE2_SC_SIGNAL(out_RETIRE_READ_RC                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
-//   DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RC_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//DELETE2_SC_SIGNAL(out_RETIRE_READ_RA                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RA_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//DELETE2_SC_SIGNAL(out_RETIRE_READ_RB                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RB_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//DELETE2_SC_SIGNAL(out_RETIRE_READ_RC                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RC_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
   DELETE2_SC_SIGNAL(out_RETIRE_WRITE_RD                ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
   DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RD_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
@@ -683,4 +831,5 @@
   DELETE2_SC_SIGNAL( in_RETIRE_EVENT_ACK               ,_param->_nb_front_end,_param->_nb_context[it1]);
   DELETE2_SC_SIGNAL(out_RETIRE_EVENT_STATE             ,_param->_nb_front_end,_param->_nb_context[it1]);
+  DELETE2_SC_SIGNAL(out_RETIRE_EVENT_STOP              ,_param->_nb_front_end,_param->_nb_context[it1]);
   DELETE1_SC_SIGNAL( in_COMMIT_VAL               ,_param->_nb_inst_commit);
   DELETE1_SC_SIGNAL(out_COMMIT_ACK               ,_param->_nb_inst_commit);
@@ -747,4 +896,6 @@
   DELETE2_SC_SIGNAL(out_SPR_WRITE_SR_OV_VAL            ,_param->_nb_front_end,_param->_nb_context[it1]);
   DELETE2_SC_SIGNAL(out_SPR_WRITE_SR_OV                ,_param->_nb_front_end,_param->_nb_context[it1]);
+
+  DELETE0_SC_SIGNAL(out_INFO_ROB_EMPTY                 );
     }
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 128)
@@ -239,9 +239,12 @@
 
 #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true)
-    for (uint32_t i=0; i<_param->_nb_thread; ++i)
-      if (_param->_have_thread [i])
-        {
-          instruction_log_file [i].close();
-        }
+    {   
+      for (uint32_t i=0; i<_param->_nb_thread; ++i)
+        if (_param->_have_thread [i])
+          {
+            instruction_log_file [i].close();
+          }
+      delete [] instruction_log_file;
+    }
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 128)
@@ -52,5 +52,5 @@
       for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
         {
-          spr_write_val [i][j] = 0;
+          spr_write_val       [i][j] = 0;
           spr_write_sr_f_val  [i][j] = 0;
           spr_write_sr_cy_val [i][j] = 0;
@@ -63,5 +63,7 @@
     for (uint32_t i=0; i<_param->_nb_bank; i++)
       {
-	uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank;
+        uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank;
+
+        log_printf(TRACE,Commit_unit,FUNCTION,"  * BANK [%d]",num_bank);
 
         // Test if have instruction
@@ -72,127 +74,159 @@
 	    uint32_t   x     = entry->rename_unit_id;
 	    uint32_t   y     = num_inst_retire [x];
-	    bool       bypass= false;
-            // test if :
-            //  * can retire (all previous instruction is retired)
-            //  * all structure is ok (not busy)
-	    if (can_retire [x] and // in-order
-		(y < _param->_nb_inst_retire [x]) and
-		PORT_READ(in_RETIRE_ACK [x][y])) // not busy
-	      {
-		rob_state_t state        = entry->state;
-                Tcontext_t  front_end_id = entry->front_end_id;
-                Tcontext_t  context_id   = entry->context_id;  
+
+            log_printf(TRACE,Commit_unit,FUNCTION,"    * num_rename_unit        : %d",x);
+            log_printf(TRACE,Commit_unit,FUNCTION,"    * num_inst_retire        : %d",y);
+
+            if (y < _param->_nb_inst_retire [x])
+              {
+#ifdef DEBUG_TEST
+                if (x >= _param->_nb_rename_unit)
+                  throw ERRORMORPHEO(FUNCTION,toString(_("Invalid rename_unit number (%d, max is %d).\n"),x,_param->_nb_rename_unit));
+#endif
+                bool       bypass= false;
+
+                log_printf(TRACE,Commit_unit,FUNCTION,"    * can_retire             : %d",can_retire [x]);
+                log_printf(TRACE,Commit_unit,FUNCTION,"    * RETIRE_ACK             : %d",PORT_READ(in_RETIRE_ACK [x][y]));
+
+                // test if :
+                //  * can retire (all previous instruction is retired)
+                //  * all structure is ok (not busy)
+                if (can_retire [x] and // in-order
+                    PORT_READ(in_RETIRE_ACK [x][y])) // not busy
+                  {
+                    log_printf(TRACE,Commit_unit,FUNCTION,"    * valid !!!");
+
+                    rob_state_t state        = entry->state;
+                    Tcontext_t  front_end_id = entry->front_end_id;
+                    Tcontext_t  context_id   = entry->context_id;  
+
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * state                : %s",toString(state).c_str());
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * front_end_id         : %d",front_end_id);
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * context_id           : %d",context_id  );
+                    
+                    if ((state == ROB_END_OK         ) or 
+                        (state == ROB_END_KO         ) or 
+                        (state == ROB_END_BRANCH_MISS) or 
+                        (state == ROB_END_LOAD_MISS  ) or 
+                        (state == ROB_END_MISS       )//  or 
+// 		        (state == ROB_END_EXCEPTION)
+                        )
+                      {
+                        Tcontrol_t         write_re       = entry->write_re;
+                        Tspecial_address_t num_reg_re_log = entry->num_reg_re_log;
+                        
+                        // if state is ok, when write flags in the SR regsiters
+                        bool spr_write_ack = true;
+                        
+                        // Write in SR the good flag
+                        if ((state == ROB_END_OK  ) and write_re)
+                          // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE
+                          {
+                            log_printf(TRACE,Commit_unit,FUNCTION,"      * need write SR flags");
+                            log_printf(TRACE,Commit_unit,FUNCTION,"      * SPR_WRITE_ACK        : %d",PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]));
+
+                            spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]);
+                            
+                            // retire_ack is set !!!
+                            spr_write_val       [front_end_id][context_id] = 1;
+                            
+                            Tspecial_data_t flags = entry->flags;
+                            
+                            switch (num_reg_re_log)
+                              {
+                              case SPR_LOGIC_SR_F     : 
+                                {
+                                  spr_write_sr_f_val  [front_end_id][context_id] = 1;
+                                  spr_write_sr_f      [front_end_id][context_id] = (flags & FLAG_F )!=0;
+                                  
+                                  break;
+                                }
+                              case SPR_LOGIC_SR_CY_OV :
+                                {
+                                  spr_write_sr_cy_val [front_end_id][context_id] = 1;
+                                  spr_write_sr_ov_val [front_end_id][context_id] = 1;	
+                                  spr_write_sr_cy     [front_end_id][context_id] = (flags & FLAG_CY)!=0;
+                                  spr_write_sr_ov     [front_end_id][context_id] = (flags & FLAG_OV)!=0;
+                                  
+                                  break;
+                                }
+                              default : 
+                                {
+#ifdef DEBUG_TEST
+                                  throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n"));
+#endif
+                                }
+                              }
+                          }
+                        
+                        // find an instruction can be retire, and in order
+                        
+                        if (spr_write_ack)
+                          {
+                            retire_val [x][y] = 1;
+                            num_inst_retire [x] ++;
+                            internal_BANK_RETIRE_VAL [num_bank] = true;
+                          }
+                        
+                        internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x;
+                        internal_BANK_RETIRE_NUM_INST        [num_bank] = y;
+                        
+                        if (_param->_have_port_front_end_id)
+                        PORT_WRITE(out_RETIRE_FRONT_END_ID          [x][y], front_end_id                );
+                        if (_param->_have_port_context_id)
+                        PORT_WRITE(out_RETIRE_CONTEXT_ID            [x][y], context_id                  );
+// 		        PORT_WRITE(out_RETIRE_RENAME_UNIT_ID        [x][y], entry->rename_unit_id       );
+                        PORT_WRITE(out_RETIRE_USE_STORE_QUEUE       [x][y], entry->use_store_queue      );
+                        PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE        [x][y], entry->use_load_queue       );
+                        PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write);
+                        if (_param->_have_port_load_queue_ptr)
+		        PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE  [x][y], entry->load_queue_ptr_write );
+//                      PORT_WRITE(out_RETIRE_READ_RA               [x][y], entry->read_ra              );
+//                      PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY        [x][y], entry->num_reg_ra_phy       );
+//                      PORT_WRITE(out_RETIRE_READ_RB               [x][y], entry->read_rb              );
+//                      PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY        [x][y], entry->num_reg_rb_phy       );
+//                      PORT_WRITE(out_RETIRE_READ_RC               [x][y], entry->read_rc              );
+//                      PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY        [x][y], entry->num_reg_rc_phy       );
+                        PORT_WRITE(out_RETIRE_WRITE_RD              [x][y], entry->write_rd             );
+                        PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG        [x][y], entry->num_reg_rd_log       );
+                        PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD    [x][y], entry->num_reg_rd_phy_old   );
+                        PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW    [x][y], entry->num_reg_rd_phy_new   );
+                        PORT_WRITE(out_RETIRE_WRITE_RE              [x][y], write_re                    );
+                        PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG        [x][y], num_reg_re_log              );
+                        PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD    [x][y], entry->num_reg_re_phy_old   );
+                        PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW    [x][y], entry->num_reg_re_phy_new   );
+                        
+                        // Event -> rob must be manage this event
+                        if ((state == ROB_END_BRANCH_MISS) or
+                            (state == ROB_END_LOAD_MISS))
+                          can_retire [x] = false;
+                      }
+
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * bypass (before)      : %d",bypass);
+
+                    bypass = ((state == ROB_END              ) or 
+                              (state == ROB_STORE_OK         ) or 
+                              (state == ROB_STORE_KO         ) or
+                              (state == ROB_STORE_OK_WAIT_END) or 
+                              (state == ROB_STORE_KO_WAIT_END));
+
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * bypass (after)       : %d",bypass);
+                    
+                    uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank);
+
+                    log_printf(TRACE,Commit_unit,FUNCTION,"      * packet               : %d",packet);
+                    
+                    // if future event, don't update after this event
+                    if ((reg_EVENT_STATE  [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and
+                        (reg_EVENT_PACKET [front_end_id][context_id] == packet))
+                      {
+                        log_printf(TRACE,Commit_unit,FUNCTION,"      * is the event instruction, stop bypass !!!");
+                        bypass = false;
+                      }
+                  }
                 
-                  if ((state == ROB_END_OK         ) or 
-                      (state == ROB_END_KO         ) or 
-                      (state == ROB_END_BRANCH_MISS) or 
-                      (state == ROB_END_LOAD_MISS  ) or 
-                      (state == ROB_END_MISS       )//  or 
-// 		      (state == ROB_END_EXCEPTION)
-                      )
-                    {
-                      Tcontrol_t         write_re       = entry->write_re;
-                      Tspecial_address_t num_reg_re_log = entry->num_reg_re_log;
-                      
-                      // if state is ok, when write flags in the SR regsiters
-                      bool spr_write_ack = true;
-                      
-                      // Write in SR the good flag
-                      if ((state == ROB_END_OK  ) and write_re)
-                        // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE
-                        {
-                          spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]);
-                          
-                          // retire_ack is set !!!
-                          spr_write_val       [front_end_id][context_id] = 1;
-                          
-                          Tspecial_data_t flags = entry->flags;
-                          
-                          switch (num_reg_re_log)
-                            {
-                            case SPR_LOGIC_SR_F     : 
-                              {
-                                spr_write_sr_f_val  [front_end_id][context_id] = 1;
-                                spr_write_sr_f      [front_end_id][context_id] = (flags & FLAG_F )!=0;
-                                
-                                break;
-                              }
-                            case SPR_LOGIC_SR_CY_OV :
-                              {
-                                spr_write_sr_cy_val [front_end_id][context_id] = 1;
-                                spr_write_sr_ov_val [front_end_id][context_id] = 1;	
-                                spr_write_sr_cy     [front_end_id][context_id] = (flags & FLAG_CY)!=0;
-                                spr_write_sr_ov     [front_end_id][context_id] = (flags & FLAG_OV)!=0;
-                                
-                                break;
-                              }
-                            default : 
-                              {
-#ifdef DEBUG_TEST
-                                throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n"));
-#endif
-                              }
-                            }
-                        }
-                      
-                      // find an instruction can be retire, and in order
-                      
-                      if (spr_write_ack)
-                        {
-                          retire_val [x][y] = 1;
-                          num_inst_retire [x] ++;
-                          internal_BANK_RETIRE_VAL [num_bank] = true;
-                        }
-                      
-                      internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x;
-                      internal_BANK_RETIRE_NUM_INST        [num_bank] = y;
-                      
-                      if (_param->_have_port_front_end_id)
-                      PORT_WRITE(out_RETIRE_FRONT_END_ID          [x][y], front_end_id                );
-                      if (_param->_have_port_context_id)
-                      PORT_WRITE(out_RETIRE_CONTEXT_ID            [x][y], context_id                  );
-// 		      PORT_WRITE(out_RETIRE_RENAME_UNIT_ID        [x][y], entry->rename_unit_id       );
-                      PORT_WRITE(out_RETIRE_USE_STORE_QUEUE       [x][y], entry->use_store_queue      );
-                      PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE        [x][y], entry->use_load_queue       );
-                      PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write);
-                      if (_param->_have_port_load_queue_ptr)
-		      PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE  [x][y], entry->load_queue_ptr_write );
-//                       PORT_WRITE(out_RETIRE_READ_RA               [x][y], entry->read_ra              );
-//                       PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY        [x][y], entry->num_reg_ra_phy       );
-//                       PORT_WRITE(out_RETIRE_READ_RB               [x][y], entry->read_rb              );
-//                       PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY        [x][y], entry->num_reg_rb_phy       );
-//                       PORT_WRITE(out_RETIRE_READ_RC               [x][y], entry->read_rc              );
-//                       PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY        [x][y], entry->num_reg_rc_phy       );
-                      PORT_WRITE(out_RETIRE_WRITE_RD              [x][y], entry->write_rd             );
-                      PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG        [x][y], entry->num_reg_rd_log       );
-                      PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD    [x][y], entry->num_reg_rd_phy_old   );
-                      PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW    [x][y], entry->num_reg_rd_phy_new   );
-                      PORT_WRITE(out_RETIRE_WRITE_RE              [x][y], write_re                    );
-                      PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG        [x][y], num_reg_re_log              );
-                      PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD    [x][y], entry->num_reg_re_phy_old   );
-                      PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW    [x][y], entry->num_reg_re_phy_new   );
-
-                      // Event -> rob must be manage this event
-                      if ((state == ROB_END_BRANCH_MISS) or
-                          (state == ROB_END_LOAD_MISS))
-                        can_retire [x] = false;
-                    }
-
-                  bypass = ((state == ROB_END              ) or 
-                            (state == ROB_STORE_OK         ) or 
-                            (state == ROB_STORE_KO         ) or
-                            (state == ROB_STORE_OK_WAIT_END) or 
-                            (state == ROB_STORE_KO_WAIT_END));
-                  
-                  uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank);
-
-                  // if future event, don't update after this event
-                  if ((reg_EVENT_STATE  [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and
-                      (reg_EVENT_PACKET [entry->front_end_id][entry->context_id] == packet))
-                    bypass = false;
-	      }
-
-	    // Retire "in-order"
-	    can_retire [x]  &= (retire_val [x][y] or bypass);
+                // Retire "in-order"
+                can_retire [x]  &= (retire_val [x][y] or bypass);
+              }
 	  }
       }
@@ -219,4 +253,8 @@
           for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++)
             PORT_WRITE(out_RETIRE_VAL [i][j],0);
+
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            PORT_WRITE(out_SPR_WRITE_VAL [i][j], 0);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 128)
@@ -54,8 +54,15 @@
 //            reg_EVENT_FLUSH           [i][j] = false;
 //            reg_EVENT_STOP            [i][j] = false;
+              reg_EVENT_NUM_BANK        [i][j] = 0; // not necessary
+              reg_EVENT_NUM_PTR         [i][j] = 0; // not necessary
+            //reg_EVENT_CAN_RESTART     [i][j] = 0; // not necessary
+              reg_EVENT_PACKET          [i][j] = 0; // not necessary
               reg_EVENT_NB_INST         [i][j] = 0;
               reg_EVENT_LAST            [i][j] = false;
+              reg_EVENT_LAST_NUM_BANK   [i][j] = 0; // not necessary
+              reg_EVENT_LAST_NUM_PTR    [i][j] = 0; // not necessary
 
               reg_EVENT_NEXT_STOP       [i][j] = false;
+              reg_EVENT_NEXT_PACKET     [i][j] = 0; // not necessary
 
 //            reg_PC_PREVIOUS           [i][j] = (0x100-4)>>2;
@@ -274,8 +281,12 @@
 	              entry->num_reg_re_phy_old      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD    [x][y]);
 	              entry->num_reg_re_phy_new      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW    [x][y]);
+
+                      entry->flags                   = 0; // not necessary
                       entry->no_sequence             = type == TYPE_BRANCH;
 //                    entry->speculative             = true;
 #ifdef DEBUG        
 	              entry->address                 = PORT_READ(in_INSERT_ADDRESS               [x][y]);
+#else
+                      entry->address                 = 0; // not necessary
 #endif                
 	              entry->address_next            = PORT_READ(in_INSERT_ADDRESS_NEXT          [x][y]);
@@ -1339,5 +1350,5 @@
                              (*it)->flags         ,
                              (*it)->no_sequence   ,
-//                              (*it)->speculative   ,
+//                           (*it)->speculative   ,
                              (*it)->address       ,
                              (*it)->address<<2    ,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/test.cpp	(revision 128)
@@ -57,4 +57,6 @@
   sc_signal<Ttype_t           > ***  in_ISSUE_IN_TYPE                  ;
   sc_signal<Tlsq_ptr_t        > ***  in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ;
+  sc_signal<Tlsq_ptr_t        > ***  in_ISSUE_IN_STORE_QUEUE_PTR_READ  ;
+  sc_signal<Tcontrol_t        > ***  in_ISSUE_IN_STORE_QUEUE_EMPTY     ;
   sc_signal<Tlsq_ptr_t        > ***  in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE  ;
   sc_signal<Tcontrol_t        > ***  in_ISSUE_IN_HAS_IMMEDIAT          ;
@@ -78,4 +80,6 @@
   sc_signal<Ttype_t           >  **  in_REEXECUTE_TYPE                 ;
   sc_signal<Tlsq_ptr_t        >  **  in_REEXECUTE_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t        >  **  in_REEXECUTE_STORE_QUEUE_PTR_READ ;
+  sc_signal<Tcontrol_t        >  **  in_REEXECUTE_STORE_QUEUE_EMPTY    ;
   sc_signal<Tlsq_ptr_t        >  **  in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ;
   sc_signal<Tcontrol_t        >  **  in_REEXECUTE_HAS_IMMEDIAT         ;
@@ -99,4 +103,6 @@
   sc_signal<Ttype_t           >  ** out_ISSUE_OUT_TYPE                 ;
   sc_signal<Tlsq_ptr_t        >  ** out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t        >  ** out_ISSUE_OUT_STORE_QUEUE_PTR_READ ;
+  sc_signal<Tcontrol_t        >  ** out_ISSUE_OUT_STORE_QUEUE_EMPTY    ;
   sc_signal<Tlsq_ptr_t        >  ** out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ;
   sc_signal<Tcontrol_t        >  ** out_ISSUE_OUT_HAS_IMMEDIAT         ;
@@ -121,4 +127,6 @@
   ALLOC2_SC_SIGNAL( in_ISSUE_IN_TYPE                  ," in_ISSUE_IN_TYPE                  ",Ttype_t           ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]);
   ALLOC2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ," in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t        ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]);
+  ALLOC2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_PTR_READ  ," in_ISSUE_IN_STORE_QUEUE_PTR_READ  ",Tlsq_ptr_t        ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]);
+  ALLOC2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_EMPTY     ," in_ISSUE_IN_STORE_QUEUE_EMPTY     ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]);
   ALLOC2_SC_SIGNAL( in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE  ," in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE  ",Tlsq_ptr_t        ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]);
   ALLOC2_SC_SIGNAL( in_ISSUE_IN_HAS_IMMEDIAT          ," in_ISSUE_IN_HAS_IMMEDIAT          ",Tcontrol_t        ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]);
@@ -142,4 +150,6 @@
   ALLOC1_SC_SIGNAL( in_REEXECUTE_TYPE                 ," in_REEXECUTE_TYPE                 ",Ttype_t           ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_PTR_WRITE," in_REEXECUTE_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t        ,_param->_nb_inst_reexecute);
+  ALLOC1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_PTR_READ ," in_REEXECUTE_STORE_QUEUE_PTR_READ ",Tlsq_ptr_t        ,_param->_nb_inst_reexecute);
+  ALLOC1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_EMPTY    ," in_REEXECUTE_STORE_QUEUE_EMPTY    ",Tcontrol_t        ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL( in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ," in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t        ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL( in_REEXECUTE_HAS_IMMEDIAT         ," in_REEXECUTE_HAS_IMMEDIAT         ",Tcontrol_t        ,_param->_nb_inst_reexecute);
@@ -163,4 +173,6 @@
   ALLOC1_SC_SIGNAL(out_ISSUE_OUT_TYPE                 ,"out_ISSUE_OUT_TYPE                 ",Ttype_t           ,_param->_nb_inst_issue);
   ALLOC1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE,"out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t        ,_param->_nb_inst_issue);
+  ALLOC1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_PTR_READ ,"out_ISSUE_OUT_STORE_QUEUE_PTR_READ ",Tlsq_ptr_t        ,_param->_nb_inst_issue);
+  ALLOC1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_EMPTY    ,"out_ISSUE_OUT_STORE_QUEUE_EMPTY    ",Tcontrol_t        ,_param->_nb_inst_issue);
   ALLOC1_SC_SIGNAL(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ,"out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t        ,_param->_nb_inst_issue);
   ALLOC1_SC_SIGNAL(out_ISSUE_OUT_HAS_IMMEDIAT         ,"out_ISSUE_OUT_HAS_IMMEDIAT         ",Tcontrol_t        ,_param->_nb_inst_issue);
@@ -197,4 +209,6 @@
   INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_TYPE                  ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
   INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
+  INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_STORE_QUEUE_PTR_READ  ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
+  INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_STORE_QUEUE_EMPTY     ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE  ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
@@ -223,4 +237,6 @@
   INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_TYPE                 ,_param->_nb_inst_reexecute);
   INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute);
+  INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_STORE_QUEUE_PTR_READ ,_param->_nb_inst_reexecute);
+  INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_STORE_QUEUE_EMPTY    ,_param->_nb_inst_reexecute);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute);
@@ -249,4 +265,6 @@
   INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_TYPE                 ,_param->_nb_inst_issue);
   INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_issue);
+  INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_STORE_QUEUE_PTR_READ ,_param->_nb_inst_issue);
+  INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_STORE_QUEUE_EMPTY    ,_param->_nb_inst_issue);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_issue);
@@ -423,4 +441,6 @@
   DELETE2_SC_SIGNAL( in_ISSUE_IN_TYPE                  ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
   DELETE2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
+  DELETE2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_PTR_READ  ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
+  DELETE2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_EMPTY     ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
   DELETE2_SC_SIGNAL( in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE  ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
   DELETE2_SC_SIGNAL( in_ISSUE_IN_HAS_IMMEDIAT          ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);
@@ -445,4 +465,6 @@
   DELETE1_SC_SIGNAL( in_REEXECUTE_TYPE                 ,_param->_nb_inst_reexecute);
   DELETE1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute);
+  DELETE1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_PTR_READ ,_param->_nb_inst_reexecute);
+  DELETE1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_EMPTY    ,_param->_nb_inst_reexecute);
   DELETE1_SC_SIGNAL( in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute);
   DELETE1_SC_SIGNAL( in_REEXECUTE_HAS_IMMEDIAT         ,_param->_nb_inst_reexecute);
@@ -467,4 +489,6 @@
   DELETE1_SC_SIGNAL(out_ISSUE_OUT_TYPE                 ,_param->_nb_inst_issue);
   DELETE1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_issue);
+  DELETE1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_PTR_READ ,_param->_nb_inst_issue);
+  DELETE1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_EMPTY    ,_param->_nb_inst_issue);
   DELETE1_SC_SIGNAL(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_issue);
   DELETE1_SC_SIGNAL(out_ISSUE_OUT_HAS_IMMEDIAT         ,_param->_nb_inst_issue);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp	(revision 128)
@@ -156,8 +156,4 @@
 
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-    ALLOC1(internal_BANK_IN_ACK             ,Tcontrol_t,_param->_nb_bank);
-    ALLOC1(internal_BANK_IN_NUM_RENAME_UNIT ,uint32_t  ,_param->_nb_bank);
-    ALLOC1(internal_BANK_IN_NUM_INST        ,uint32_t  ,_param->_nb_bank);
-
     ALLOC1(internal_ISSUE_OUT_VAL           ,Tcontrol_t,_param->_nb_inst_issue);
     ALLOC1(internal_ISSUE_OUT_FROM_REEXECUTE,Tcontrol_t,_param->_nb_inst_issue);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp	(revision 128)
@@ -101,4 +101,10 @@
 
         // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+	while (not _reexecute_queue.empty())
+	  {
+	    delete _reexecute_queue.front();
+	    _reexecute_queue.pop_front();
+	  }
+
         DELETE1(_issue_queue                     ,_param->_nb_bank);
         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_transition.cpp	(revision 128)
@@ -105,9 +105,9 @@
                 log_printf(TRACE,Issue_queue,FUNCTION,"  * ISSUE_OUT [%d] - From issue_queue [%d]",i,num_bank);
                 
+                delete entry;
+                
                 _issue_queue [num_bank].remove(entry);
-                
+
                 reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank;
-                
-                delete entry;
               } 
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_transition.cpp	(revision 128)
@@ -101,6 +101,7 @@
                 log_printf(TRACE,Issue_queue,FUNCTION,"  * ISSUE_OUT [%d] - From issue_queue [%d]",i,num_bank);
                 
+                delete entry;
+
                 _issue_queue [num_bank].remove(entry);
-                delete entry;
               } 
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/main.cpp	(revision 128)
@@ -108,4 +108,6 @@
       
       test (name,param);
+
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/test.cpp	(revision 128)
@@ -48,4 +48,127 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
+  sc_signal<Tcontext_t         > ***  in_RENAME_FRONT_END_ID                     ;
+  sc_signal<Tcontext_t         > *** out_RENAME_RENAME_UNIT_FRONT_END_ID         ;
+
+  sc_signal<Tcontrol_t         >  ** out_INSERT_VAL                              ;
+  sc_signal<Tcontrol_t         >  **  in_INSERT_ACK                              ;
+  sc_signal<Tcontrol_t         >  ** out_INSERT_RD_USE                           ;
+  sc_signal<Tgeneral_address_t >  ** out_INSERT_RD_NUM_REG                       ;
+  sc_signal<Tcontrol_t         >  ** out_INSERT_RE_USE                           ;
+  sc_signal<Tspecial_address_t >  ** out_INSERT_RE_NUM_REG                       ;
+
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_VAL                  ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_RENAME_UNIT_ACK                  ;
+  sc_signal<Tcontext_t         > ***  in_INSERT_RENAME_UNIT_FRONT_END_ID         ;
+  sc_signal<Tcontext_t         > ***  in_INSERT_RENAME_UNIT_CONTEXT_ID           ;
+  sc_signal<Ttype_t            > ***  in_INSERT_RENAME_UNIT_TYPE                 ;
+  sc_signal<Toperation_t       > ***  in_INSERT_RENAME_UNIT_OPERATION            ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_NO_EXECUTE           ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_HAS_IMMEDIAT         ;
+  sc_signal<Tgeneral_data_t    > ***  in_INSERT_RENAME_UNIT_IMMEDIAT             ;
+  sc_signal<Tlsq_ptr_t         > ***  in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t         > ***  in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY    ;
+  sc_signal<Tlsq_ptr_t         > ***  in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_READ_RA              ;
+  sc_signal<Tgeneral_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RA_PHY       ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_READ_RB              ;
+  sc_signal<Tgeneral_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RB_PHY       ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_READ_RC              ;
+  sc_signal<Tspecial_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RC_PHY       ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_WRITE_RD             ;
+  sc_signal<Tgeneral_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_OLD   ;
+  sc_signal<Tgeneral_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_NEW   ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_RENAME_UNIT_WRITE_RE             ;
+  sc_signal<Tspecial_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_OLD   ;
+  sc_signal<Tspecial_address_t > ***  in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW   ;
+
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_VAL                  ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_COMMIT_UNIT_ACK                  ;
+  sc_signal<Tcontext_t         > *** out_INSERT_COMMIT_UNIT_FRONT_END_ID         ;
+  sc_signal<Tcontext_t         > *** out_INSERT_COMMIT_UNIT_CONTEXT_ID           ;
+//sc_signal<Tcontext_t         > *** out_INSERT_COMMIT_UNIT_RENAME_UNIT_ID       ;
+  sc_signal<Ttype_t            > *** out_INSERT_COMMIT_UNIT_TYPE                 ;
+  sc_signal<Toperation_t       > *** out_INSERT_COMMIT_UNIT_OPERATION            ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_NO_EXECUTE           ;
+  sc_signal<Tlsq_ptr_t         > *** out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE;
+//   sc_signal<Tlsq_ptr_t         > *** out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_READ ;
+//   sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_STORE_QUEUE_EMPTY    ;
+  sc_signal<Tlsq_ptr_t         > *** out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_READ_RA              ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RA_PHY       ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_READ_RB              ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RB_PHY       ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_READ_RC              ;
+  sc_signal<Tspecial_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RC_PHY       ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_WRITE_RD             ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_OLD   ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_NEW   ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_COMMIT_UNIT_WRITE_RE             ;
+  sc_signal<Tspecial_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_OLD   ;
+  sc_signal<Tspecial_address_t > *** out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_NEW   ;
+
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_VAL                  ;
+  sc_signal<Tcontrol_t         > ***  in_INSERT_ISSUE_QUEUE_ACK                  ;
+  sc_signal<Tcontext_t         > *** out_INSERT_ISSUE_QUEUE_CONTEXT_ID           ;
+  sc_signal<Tcontext_t         > *** out_INSERT_ISSUE_QUEUE_FRONT_END_ID         ;
+  sc_signal<Toperation_t       > *** out_INSERT_ISSUE_QUEUE_OPERATION            ;
+  sc_signal<Ttype_t            > *** out_INSERT_ISSUE_QUEUE_TYPE                 ;
+  sc_signal<Tlsq_ptr_t         > *** out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t         > *** out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY    ;
+  sc_signal<Tlsq_ptr_t         > *** out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT         ;
+  sc_signal<Tgeneral_data_t    > *** out_INSERT_ISSUE_QUEUE_IMMEDIAT             ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_READ_RA              ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_ISSUE_QUEUE_NUM_REG_RA           ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_READ_RB              ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_ISSUE_QUEUE_NUM_REG_RB           ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_READ_RC              ;
+  sc_signal<Tspecial_address_t > *** out_INSERT_ISSUE_QUEUE_NUM_REG_RC           ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_WRITE_RD             ;
+  sc_signal<Tgeneral_address_t > *** out_INSERT_ISSUE_QUEUE_NUM_REG_RD           ;
+  sc_signal<Tcontrol_t         > *** out_INSERT_ISSUE_QUEUE_WRITE_RE             ;
+  sc_signal<Tspecial_address_t > *** out_INSERT_ISSUE_QUEUE_NUM_REG_RE           ;
+
+//sc_signal<Tcontrol_t         >  ** out_RETIRE_VAL                              ;
+//sc_signal<Tcontrol_t         >  **  in_RETIRE_ACK                              ;
+//sc_signal<Tcontrol_t         >  ** out_RETIRE_RD_OLD_USE                       ;
+//sc_signal<Tgeneral_address_t >  ** out_RETIRE_RD_OLD_NUM_REG                   ;
+//sc_signal<Tcontrol_t         >  ** out_RETIRE_RD_NEW_USE                       ;
+//sc_signal<Tgeneral_address_t >  ** out_RETIRE_RD_NEW_NUM_REG                   ;
+//sc_signal<Tcontrol_t         >  ** out_RETIRE_RE_OLD_USE                       ;
+//sc_signal<Tspecial_address_t >  ** out_RETIRE_RE_OLD_NUM_REG                   ;
+//sc_signal<Tcontrol_t         >  ** out_RETIRE_RE_NEW_USE                       ;
+//sc_signal<Tspecial_address_t >  ** out_RETIRE_RE_NEW_NUM_REG                   ;
+
+//sc_signal<Tcontrol_t         > *** out_RETIRE_RENAME_UNIT_VAL                  ;
+//sc_signal<Tcontrol_t         > ***  in_RETIRE_RENAME_UNIT_ACK                  ;
+//sc_signal<Tcontext_t         > *** out_RETIRE_RENAME_UNIT_FRONT_END_ID         ;
+//sc_signal<Tcontrol_t         > *** out_RETIRE_RENAME_UNIT_WRITE_RD             ;
+//sc_signal<Tgeneral_address_t > *** out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_OLD   ;
+//sc_signal<Tgeneral_address_t > *** out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_NEW   ;
+//sc_signal<Tcontrol_t         > *** out_RETIRE_RENAME_UNIT_WRITE_RE             ;
+//sc_signal<Tspecial_address_t > *** out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_OLD   ;
+//sc_signal<Tspecial_address_t > *** out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_NEW   ;
+//sc_signal<Tevent_state_t     > *** out_RETIRE_RENAME_UNIT_EVENT_STATE          ;
+
+//sc_signal<Tcontrol_t         > ***  in_RETIRE_COMMIT_UNIT_VAL                  ;
+//sc_signal<Tcontrol_t         > *** out_RETIRE_COMMIT_UNIT_ACK                  ;
+//sc_signal<Tcontext_t         > ***  in_RETIRE_COMMIT_UNIT_FRONT_END_ID         ;
+//sc_signal<Tcontrol_t         > ***  in_RETIRE_COMMIT_UNIT_WRITE_RD             ;
+//sc_signal<Tgeneral_address_t > ***  in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_OLD   ;
+//sc_signal<Tgeneral_address_t > ***  in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_NEW   ;
+//sc_signal<Tcontrol_t         > ***  in_RETIRE_COMMIT_UNIT_WRITE_RE             ;
+//sc_signal<Tspecial_address_t > ***  in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_OLD   ;
+//sc_signal<Tspecial_address_t > ***  in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW   ;
+//sc_signal<Tevent_state_t     > ***  in_RETIRE_COMMIT_UNIT_EVENT_STATE          ;
+
+  sc_signal<Tcontrol_t         > *** out_SPR_SR_IEE                              ;
+  sc_signal<Tcontrol_t         > *** out_SPR_SR_EPH                              ;
+  sc_signal<Tspr_t             > *** out_SPR_RENAME_UNIT_SR                      ;
+  sc_signal<Tcontrol_t         > *** out_SPR_COMMIT_UNIT_SR_OVE                  ;
+  sc_signal<Tspr_t             > ***  in_SPR_SPECIAL_REGISTER_UNIT_SR            ;
+
   ALLOC2_SC_SIGNAL( in_RENAME_FRONT_END_ID                     ," in_RENAME_FRONT_END_ID                     ",Tcontext_t         ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);                               
   ALLOC2_SC_SIGNAL(out_RENAME_RENAME_UNIT_FRONT_END_ID         ,"out_RENAME_RENAME_UNIT_FRONT_END_ID         ",Tcontext_t         ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);                               
@@ -68,4 +191,6 @@
   ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_IMMEDIAT             ," in_INSERT_RENAME_UNIT_IMMEDIAT             ",Tgeneral_data_t    ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE," in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
+  ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ ," in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ ",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
+  ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY    ," in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY    ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE ," in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_READ_RA              ," in_INSERT_RENAME_UNIT_READ_RA              ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
@@ -91,4 +216,6 @@
   ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NO_EXECUTE           ,"out_INSERT_COMMIT_UNIT_NO_EXECUTE           ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE,"out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
+//   ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_READ ,"out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_READ ",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
+//   ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_EMPTY    ,"out_INSERT_COMMIT_UNIT_STORE_QUEUE_EMPTY    ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE ,"out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_READ_RA              ,"out_INSERT_COMMIT_UNIT_READ_RA              ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
@@ -112,4 +239,6 @@
   ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_TYPE                 ,"out_INSERT_ISSUE_QUEUE_TYPE                 ",Ttype_t            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE,"out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
+  ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ ,"out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ ",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
+  ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY    ,"out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY    ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ,"out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
   ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT         ,"out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT         ",Tcontrol_t         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);                            
@@ -199,4 +328,6 @@
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_IMMEDIAT                  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -225,4 +356,6 @@
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_NO_EXECUTE                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+//   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+//   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -251,4 +384,6 @@
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_TYPE                      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -399,4 +534,6 @@
   DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_IMMEDIAT                  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_READ_RA                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -422,4 +559,6 @@
   DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NO_EXECUTE                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+//   DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+//   DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_READ_RA                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -443,4 +582,6 @@
   DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_TYPE                      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+  DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
   DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_deallocation.cpp	(revision 128)
@@ -71,4 +71,5 @@
         DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_TYPE                      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type            );
         DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_OPERATION                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_operation       );
+        DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_NO_EXECUTE                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1);
         DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr );
         DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr  );
@@ -95,4 +96,6 @@
         DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_TYPE                      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type            );
         DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr );
+        DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_READ      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr );
+        DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_EMPTY         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1);
         DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr  );
         DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                             );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert.cpp	(revision 128)
@@ -54,6 +54,6 @@
           Tspecial_address_t NUM_REG_RE_PHY_NEW    = PORT_READ(in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW    [i][j]);
 
-          Tgeneral_address_t general_address_msb   = FRONT_END_ID << _param->_size_general_register;
-          Tspecial_address_t special_address_msb   = FRONT_END_ID << _param->_size_special_register;
+          Tgeneral_address_t general_address_msb   = i << _param->_size_general_register;
+          Tspecial_address_t special_address_msb   = i << _param->_size_special_register;
           
           PORT_WRITE(out_INSERT_RD_USE                            [x]   ,WRITE_RD);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters.cpp	(revision 128)
@@ -7,4 +7,5 @@
 
 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Parameters.h"
+#include "Behavioural/include/Allocation.h"
 #include "Common/include/Max.h"
 #include "Common/include/BitManipulation.h"
@@ -61,5 +62,5 @@
       }
 
-    _translate_front_end_id_to_rename_unit  = new uint32_t [_nb_front_end];
+    ALLOC1(_translate_front_end_id_to_rename_unit,uint32_t,_nb_front_end);
     
     for (uint32_t i=0; i<_nb_front_end; i++)
@@ -119,5 +120,7 @@
   {
     log_begin(OOO_Engine_Glue,FUNCTION);
-    delete _translate_front_end_id_to_rename_unit;
+
+    DELETE1(_translate_front_end_id_to_rename_unit,_nb_front_end);
+ 
     log_end(OOO_Engine_Glue,FUNCTION);
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/main.cpp	(revision 128)
@@ -101,4 +101,6 @@
       
       test (name,param);
+
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/test.cpp	(revision 128)
@@ -137,4 +137,75 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
+  sc_signal<Tcontrol_t         > ***  in_EXECUTE_LOOP_VAL                     ;
+  sc_signal<Tcontrol_t         > *** out_EXECUTE_LOOP_ACK                     ;
+  sc_signal<Tcontext_t         > ***  in_EXECUTE_LOOP_CONTEXT_ID              ;
+  sc_signal<Tcontext_t         > ***  in_EXECUTE_LOOP_FRONT_END_ID            ;
+  sc_signal<Tpacket_t          > ***  in_EXECUTE_LOOP_PACKET_ID               ;
+//sc_signal<Toperation_t       > ***  in_EXECUTE_LOOP_OPERATION               ;
+//sc_signal<Ttype_t            > ***  in_EXECUTE_LOOP_TYPE                    ;
+  sc_signal<Tspecial_data_t    > ***  in_EXECUTE_LOOP_FLAGS                   ;
+  sc_signal<Texception_t       > ***  in_EXECUTE_LOOP_EXCEPTION               ;
+  sc_signal<Tcontrol_t         > ***  in_EXECUTE_LOOP_NO_SEQUENCE             ;
+  sc_signal<Tgeneral_data_t    > ***  in_EXECUTE_LOOP_ADDRESS                 ;
+  sc_signal<Tgeneral_data_t    > ***  in_EXECUTE_LOOP_DATA                    ;
+
+  sc_signal<Tcontrol_t         >  ** out_COMMIT_VAL                           ;
+  sc_signal<Tcontrol_t         >  **  in_COMMIT_ACK                           ;
+  sc_signal<Tcontrol_t         >  ** out_COMMIT_WEN                           ;
+  sc_signal<Tcontext_t         >  ** out_COMMIT_CONTEXT_ID                    ;
+  sc_signal<Tcontext_t         >  ** out_COMMIT_FRONT_END_ID                  ;
+  sc_signal<Tpacket_t          >  ** out_COMMIT_PACKET_ID                     ;
+//sc_signal<Toperation_t       >  ** out_COMMIT_OPERATION                     ;
+//sc_signal<Ttype_t            >  ** out_COMMIT_TYPE                          ;
+  sc_signal<Tspecial_data_t    >  ** out_COMMIT_FLAGS                         ;
+  sc_signal<Texception_t       >  ** out_COMMIT_EXCEPTION                     ;
+  sc_signal<Tcontrol_t         >  ** out_COMMIT_NO_SEQUENCE                   ;
+  sc_signal<Tgeneral_data_t    >  ** out_COMMIT_ADDRESS                       ;
+  sc_signal<Tgeneral_address_t >  **  in_COMMIT_NUM_REG_RD                    ;
+
+  sc_signal<Tcontrol_t         >  ** out_SPR_VAL                              ;
+  sc_signal<Tcontrol_t         >  **  in_SPR_ACK                              ;
+  sc_signal<Tcontrol_t         >  ** out_SPR_WEN                              ;
+  sc_signal<Tcontext_t         >  ** out_SPR_CONTEXT_ID                       ;
+  sc_signal<Tcontext_t         >  ** out_SPR_FRONT_END_ID                     ;
+  sc_signal<Tspr_address_t     >  ** out_SPR_NUM_GROUP                        ;
+  sc_signal<Tspr_address_t     >  ** out_SPR_NUM_REG                          ;
+  sc_signal<Tspr_t             >  ** out_SPR_WDATA                            ;
+  sc_signal<Tspr_t             >  **  in_SPR_RDATA                            ;
+  sc_signal<Tcontrol_t         >  **  in_SPR_INVALID                          ;
+
+  sc_signal<Tcontrol_t         >  **  in_REEXECUTE_ROB_VAL                    ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_ROB_ACK                    ;
+  sc_signal<Tcontext_t         >  **  in_REEXECUTE_ROB_CONTEXT_ID             ;
+  sc_signal<Tcontext_t         >  **  in_REEXECUTE_ROB_FRONT_END_ID           ;
+  sc_signal<Tpacket_t          >  **  in_REEXECUTE_ROB_PACKET_ID              ;
+  sc_signal<Toperation_t       >  **  in_REEXECUTE_ROB_OPERATION              ;
+  sc_signal<Ttype_t            >  **  in_REEXECUTE_ROB_TYPE                   ;
+  sc_signal<Tlsq_ptr_t         >  **  in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE  ;
+
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_VAL                        ;
+  sc_signal<Tcontrol_t         >  **  in_REEXECUTE_ACK                        ;
+  sc_signal<Tcontext_t         >  ** out_REEXECUTE_CONTEXT_ID                 ;
+  sc_signal<Tcontext_t         >  ** out_REEXECUTE_FRONT_END_ID               ;
+  sc_signal<Tpacket_t          >  ** out_REEXECUTE_PACKET_ID                  ;
+  sc_signal<Toperation_t       >  ** out_REEXECUTE_OPERATION                  ;
+  sc_signal<Ttype_t            >  ** out_REEXECUTE_TYPE                       ;
+  sc_signal<Tlsq_ptr_t         >  ** out_REEXECUTE_STORE_QUEUE_PTR_WRITE      ;
+  sc_signal<Tlsq_ptr_t         >  ** out_REEXECUTE_STORE_QUEUE_PTR_READ       ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_STORE_QUEUE_EMPTY          ;
+  sc_signal<Tlsq_ptr_t         >  ** out_REEXECUTE_LOAD_QUEUE_PTR_WRITE       ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_HAS_IMMEDIAT               ;
+  sc_signal<Tgeneral_data_t    >  ** out_REEXECUTE_IMMEDIAT                   ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_READ_RA                    ;
+  sc_signal<Tgeneral_address_t >  ** out_REEXECUTE_NUM_REG_RA                 ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_READ_RB                    ;
+  sc_signal<Tgeneral_address_t >  ** out_REEXECUTE_NUM_REG_RB                 ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_READ_RC                    ;
+  sc_signal<Tspecial_address_t >  ** out_REEXECUTE_NUM_REG_RC                 ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_WRITE_RD                   ;
+  sc_signal<Tgeneral_address_t >  ** out_REEXECUTE_NUM_REG_RD                 ;
+  sc_signal<Tcontrol_t         >  ** out_REEXECUTE_WRITE_RE                   ;
+  sc_signal<Tspecial_address_t >  ** out_REEXECUTE_NUM_REG_RE                 ;
+
   ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_VAL                     ," in_EXECUTE_LOOP_VAL                   ",Tcontrol_t         ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]);
   ALLOC2_SC_SIGNAL(out_EXECUTE_LOOP_ACK                     ,"out_EXECUTE_LOOP_ACK                   ",Tcontrol_t         ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]);
@@ -192,4 +263,6 @@
   ALLOC1_SC_SIGNAL(out_REEXECUTE_TYPE                       ,"out_REEXECUTE_TYPE                     ",Ttype_t            ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE      ,"out_REEXECUTE_STORE_QUEUE_PTR_WRITE    ",Tlsq_ptr_t         ,_param->_nb_inst_reexecute);
+  ALLOC1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_READ       ,"out_REEXECUTE_STORE_QUEUE_PTR_READ     ",Tlsq_ptr_t         ,_param->_nb_inst_reexecute);
+  ALLOC1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_EMPTY          ,"out_REEXECUTE_STORE_QUEUE_EMPTY        ",Tcontrol_t         ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE       ,"out_REEXECUTE_LOAD_QUEUE_PTR_WRITE     ",Tlsq_ptr_t         ,_param->_nb_inst_reexecute);
   ALLOC1_SC_SIGNAL(out_REEXECUTE_HAS_IMMEDIAT               ,"out_REEXECUTE_HAS_IMMEDIAT             ",Tcontrol_t         ,_param->_nb_inst_reexecute);
@@ -284,4 +357,6 @@
   INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_TYPE                       ,_param->_nb_inst_reexecute);
   INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_STORE_QUEUE_PTR_WRITE      ,_param->_nb_inst_reexecute);
+  INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_STORE_QUEUE_PTR_READ       ,_param->_nb_inst_reexecute);
+  INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_STORE_QUEUE_EMPTY          ,_param->_nb_inst_reexecute);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_LOAD_QUEUE_PTR_WRITE       ,_param->_nb_inst_reexecute);
@@ -475,4 +550,6 @@
 		TEST(Tcontrol_t        ,out_REEXECUTE_HAS_IMMEDIAT          [i]->read(), 1);
 		TEST(Tlsq_ptr_t        ,out_REEXECUTE_STORE_QUEUE_PTR_WRITE [i]->read(), 0);
+		TEST(Tlsq_ptr_t        ,out_REEXECUTE_STORE_QUEUE_PTR_READ  [i]->read(), 0);
+		TEST(Tlsq_ptr_t        ,out_REEXECUTE_STORE_QUEUE_EMPTY     [i]->read(), 0);
 		TEST(Tlsq_ptr_t        ,out_REEXECUTE_LOAD_QUEUE_PTR_WRITE  [i]->read(), 0);
 		TEST(Tcontrol_t        ,out_REEXECUTE_READ_RA               [i]->read(), 0);
@@ -568,4 +645,6 @@
   DELETE1_SC_SIGNAL(out_REEXECUTE_TYPE                       ,_param->_nb_inst_reexecute);
   DELETE1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE      ,_param->_nb_inst_reexecute);
+  DELETE1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_READ       ,_param->_nb_inst_reexecute);
+  DELETE1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_EMPTY          ,_param->_nb_inst_reexecute);
   DELETE1_SC_SIGNAL(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE       ,_param->_nb_inst_reexecute);
   DELETE1_SC_SIGNAL(out_REEXECUTE_HAS_IMMEDIAT               ,_param->_nb_inst_reexecute);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_statistics_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_statistics_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_statistics_deallocation.cpp	(revision 128)
@@ -29,4 +29,5 @@
     delete _stat;
    
+    delete [] _stat_bank_spr_nb_elt;
     delete [] _stat_bank_gpr_nb_elt;
  
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/main.cpp	(revision 128)
@@ -67,4 +67,6 @@
       
       test (name,param);
+
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp	(revision 128)
@@ -50,4 +50,48 @@
   sc_clock              *  in_CLOCK  = new sc_clock ("clock", 1.0, 0.5);	 
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
+
+  sc_signal<Tcontrol_t        >  **  in_RENAME_VAL               ;
+  sc_signal<Tcontrol_t        >  ** out_RENAME_ACK               ;
+  sc_signal<Tcontext_t        >  **  in_RENAME_FRONT_END_ID      ;
+  sc_signal<Tcontext_t        >  **  in_RENAME_CONTEXT_ID        ;
+  sc_signal<Tgeneral_address_t>  **  in_RENAME_NUM_REG_RA_LOG    ;
+  sc_signal<Tgeneral_address_t>  **  in_RENAME_NUM_REG_RB_LOG    ;
+  sc_signal<Tspecial_address_t>  **  in_RENAME_NUM_REG_RC_LOG    ;
+  sc_signal<Tgeneral_address_t>  **  in_RENAME_NUM_REG_RD_LOG    ;
+  sc_signal<Tspecial_address_t>  **  in_RENAME_NUM_REG_RE_LOG    ;
+  sc_signal<Tgeneral_address_t>  ** out_RENAME_NUM_REG_RA_PHY    ;
+  sc_signal<Tgeneral_address_t>  ** out_RENAME_NUM_REG_RB_PHY    ;
+  sc_signal<Tspecial_address_t>  ** out_RENAME_NUM_REG_RC_PHY    ;
+  sc_signal<Tgeneral_address_t>  ** out_RENAME_NUM_REG_RD_PHY_OLD;
+  sc_signal<Tspecial_address_t>  ** out_RENAME_NUM_REG_RE_PHY_OLD;
+
+  sc_signal<Tcontrol_t        >  **  in_INSERT_VAL               ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_ACK               ;
+//sc_signal<Tcontext_t        >  **  in_INSERT_FRONT_END_ID      ;
+//sc_signal<Tcontext_t        >  **  in_INSERT_CONTEXT_ID        ;
+  sc_signal<Tcontrol_t        >  **  in_INSERT_WRITE_RD          ;
+  sc_signal<Tcontrol_t        >  **  in_INSERT_WRITE_RE          ;
+  sc_signal<Tgeneral_address_t>  **  in_INSERT_NUM_REG_RD_LOG    ;
+  sc_signal<Tspecial_address_t>  **  in_INSERT_NUM_REG_RE_LOG    ;
+  sc_signal<Tgeneral_address_t>  **  in_INSERT_NUM_REG_RD_PHY    ;
+  sc_signal<Tspecial_address_t>  **  in_INSERT_NUM_REG_RE_PHY    ;
+
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_VAL               ;
+  sc_signal<Tcontrol_t        >  ** out_RETIRE_ACK               ;
+  sc_signal<Tcontext_t        >  **  in_RETIRE_FRONT_END_ID      ;
+  sc_signal<Tcontext_t        >  **  in_RETIRE_CONTEXT_ID        ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_WRITE_RD          ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_WRITE_RE          ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RD_LOG    ;
+  sc_signal<Tspecial_address_t>  **  in_RETIRE_NUM_REG_RE_LOG    ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RD_PHY_NEW;
+  sc_signal<Tspecial_address_t>  **  in_RETIRE_NUM_REG_RE_PHY_NEW;
+  sc_signal<Tcontrol_t        >  ** out_RETIRE_RESTORE_RD_PHY_OLD;
+  sc_signal<Tcontrol_t        >  ** out_RETIRE_RESTORE_RE_PHY_OLD;
+  sc_signal<Tcontrol_t        >  ** out_RETIRE_RESTORE           ;
+
+  sc_signal<Tcontrol_t        > ***  in_RETIRE_EVENT_VAL         ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_EVENT_ACK         ;
+  sc_signal<Tevent_state_t    > ***  in_RETIRE_EVENT_STATE       ;
 
   ALLOC1_SC_SIGNAL( in_RENAME_VAL               ," in_RENAME_VAL               ",Tcontrol_t        ,_param->_nb_inst_insert);
@@ -85,6 +129,6 @@
   ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_LOG    ," in_RETIRE_NUM_REG_RD_LOG    ",Tgeneral_address_t,_param->_nb_inst_retire);
   ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_LOG    ," in_RETIRE_NUM_REG_RE_LOG    ",Tspecial_address_t,_param->_nb_inst_retire);
-  ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD," in_RETIRE_NUM_REG_RD_PHY_OLD",Tgeneral_address_t,_param->_nb_inst_retire);
-  ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD," in_RETIRE_NUM_REG_RE_PHY_OLD",Tspecial_address_t,_param->_nb_inst_retire);
+  ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW," in_RETIRE_NUM_REG_RD_PHY_NEW",Tgeneral_address_t,_param->_nb_inst_retire);
+  ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW," in_RETIRE_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_nb_inst_retire);
   ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE_RD_PHY_OLD,"out_RETIRE_RESTORE_RD_PHY_OLD",Tcontrol_t        ,_param->_nb_inst_retire);
   ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE_RE_PHY_OLD,"out_RETIRE_RESTORE_RE_PHY_OLD",Tcontrol_t        ,_param->_nb_inst_retire);
@@ -144,6 +188,6 @@
   INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RD_LOG    ,_param->_nb_inst_retire);
   INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RE_LOG    ,_param->_nb_inst_retire);
-  INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire);
-  INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire);
+  INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RD_PHY_NEW,_param->_nb_inst_retire);
+  INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire);
   INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire);
   INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire);
@@ -272,6 +316,6 @@
 	      in_RETIRE_NUM_REG_RD_LOG     [i]->write(rand() % _param->_nb_general_register_logic);
 	      in_RETIRE_NUM_REG_RE_LOG     [i]->write(rand() % _param->_nb_special_register_logic);
-	      in_RETIRE_NUM_REG_RD_PHY_OLD [i]->write(rand() % _param->_nb_general_register);
-	      in_RETIRE_NUM_REG_RE_PHY_OLD [i]->write(rand() % _param->_nb_special_register);
+	      in_RETIRE_NUM_REG_RD_PHY_NEW [i]->write(rand() % _param->_nb_general_register);
+	      in_RETIRE_NUM_REG_RE_PHY_NEW [i]->write(rand() % _param->_nb_special_register);
 
 	      in_RETIRE_EVENT_STATE        [front_end_id][context_id]->write(EVENT_STATE_NO_EVENT);
@@ -409,6 +453,6 @@
 	      in_RETIRE_NUM_REG_RD_LOG     [i]->write(rand() % _param->_nb_general_register_logic);
 	      in_RETIRE_NUM_REG_RE_LOG     [i]->write(rand() % _param->_nb_special_register_logic);
-	      in_RETIRE_NUM_REG_RD_PHY_OLD [i]->write(rand() % _param->_nb_general_register);
-	      in_RETIRE_NUM_REG_RE_PHY_OLD [i]->write(rand() % _param->_nb_special_register);
+	      in_RETIRE_NUM_REG_RD_PHY_NEW [i]->write(rand() % _param->_nb_general_register);
+	      in_RETIRE_NUM_REG_RE_PHY_NEW [i]->write(rand() % _param->_nb_special_register);
 
               in_RETIRE_EVENT_STATE [retire_front_end_id [i]][retire_context_id [i]]->write(EVENT_STATE_WAITEND);
@@ -451,5 +495,5 @@
 
 		      if (rat_gpr_updt [front_end_id][context_id][in_RETIRE_NUM_REG_RD_LOG[i]->read()] == false)
-			rat_gpr[front_end_id][context_id][in_RETIRE_NUM_REG_RD_LOG[i]->read()] = in_RETIRE_NUM_REG_RD_PHY_OLD[i]->read();
+			rat_gpr[front_end_id][context_id][in_RETIRE_NUM_REG_RD_LOG[i]->read()] = in_RETIRE_NUM_REG_RD_PHY_NEW[i]->read();
 		      rat_gpr_updt [front_end_id][context_id][in_RETIRE_NUM_REG_RD_LOG[i]->read()] = true;
 		    }
@@ -459,5 +503,5 @@
 
 		      if (rat_spr_updt [front_end_id][context_id][in_RETIRE_NUM_REG_RE_LOG[i]->read()] == false)
-			rat_spr[front_end_id][context_id][in_RETIRE_NUM_REG_RE_LOG[i]->read()] = in_RETIRE_NUM_REG_RE_PHY_OLD[i]->read();
+			rat_spr[front_end_id][context_id][in_RETIRE_NUM_REG_RE_LOG[i]->read()] = in_RETIRE_NUM_REG_RE_PHY_NEW[i]->read();
 		      rat_spr_updt [front_end_id][context_id][in_RETIRE_NUM_REG_RE_LOG[i]->read()] = true;
 		    }
@@ -498,53 +542,48 @@
   delete in_NRESET;
 
-  delete []  in_RENAME_VAL               ;
-  delete [] out_RENAME_ACK               ;
-  if (_param->_have_port_front_end_id)
-  delete []  in_RENAME_FRONT_END_ID      ;
-  if (_param->_have_port_context_id)
-  delete []  in_RENAME_CONTEXT_ID        ;
-  delete []  in_RENAME_NUM_REG_RA_LOG    ;
-  delete []  in_RENAME_NUM_REG_RB_LOG    ;
-  delete []  in_RENAME_NUM_REG_RC_LOG    ;
-  delete []  in_RENAME_NUM_REG_RD_LOG    ;
-  delete []  in_RENAME_NUM_REG_RE_LOG    ;
-  delete [] out_RENAME_NUM_REG_RA_PHY    ;
-  delete [] out_RENAME_NUM_REG_RB_PHY    ;
-  delete [] out_RENAME_NUM_REG_RC_PHY    ;
-  delete [] out_RENAME_NUM_REG_RD_PHY_OLD;
-  delete [] out_RENAME_NUM_REG_RE_PHY_OLD;
-
-  delete []  in_INSERT_VAL               ;
-  delete [] out_INSERT_ACK               ;
-//if (_param->_have_port_front_end_id)
-//delete []  in_INSERT_FRONT_END_ID      ;
-//if (_param->_have_port_context_id)
-//delete []  in_INSERT_CONTEXT_ID        ;
-  delete []  in_INSERT_WRITE_RD          ;
-  delete []  in_INSERT_WRITE_RE          ;
-  delete []  in_INSERT_NUM_REG_RD_LOG    ;
-  delete []  in_INSERT_NUM_REG_RE_LOG    ;
-  delete []  in_INSERT_NUM_REG_RD_PHY    ;
-  delete []  in_INSERT_NUM_REG_RE_PHY    ;
-
-  delete []  in_RETIRE_VAL               ;
-  delete [] out_RETIRE_ACK               ;
-  if (_param->_have_port_front_end_id)
-  delete []  in_RETIRE_FRONT_END_ID      ;
-  if (_param->_have_port_context_id)
-  delete []  in_RETIRE_CONTEXT_ID        ;
-  delete []  in_RETIRE_WRITE_RD          ;
-  delete []  in_RETIRE_WRITE_RE          ;
-  delete []  in_RETIRE_NUM_REG_RD_LOG    ;
-  delete []  in_RETIRE_NUM_REG_RE_LOG    ;
-  delete []  in_RETIRE_NUM_REG_RD_PHY_OLD;
-  delete []  in_RETIRE_NUM_REG_RE_PHY_OLD;
-  delete [] out_RETIRE_RESTORE_RD_PHY_OLD;
-  delete [] out_RETIRE_RESTORE_RE_PHY_OLD;
-  delete [] out_RETIRE_RESTORE           ;
-
-  DELETE2_SC_SIGNAL( in_RETIRE_EVENT_VAL            ,_param->_nb_front_end, _param->_nb_context[it1]);
-  DELETE2_SC_SIGNAL(out_RETIRE_EVENT_ACK            ,_param->_nb_front_end, _param->_nb_context[it1]);
-  DELETE2_SC_SIGNAL( in_RETIRE_EVENT_STATE          ,_param->_nb_front_end, _param->_nb_context[it1]);
+
+  DELETE1_SC_SIGNAL( in_RENAME_VAL               ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_RENAME_ACK               ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_FRONT_END_ID      ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_CONTEXT_ID        ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_NUM_REG_RA_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_NUM_REG_RB_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_NUM_REG_RC_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_NUM_REG_RD_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_RENAME_NUM_REG_RE_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_RENAME_NUM_REG_RA_PHY    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_RENAME_NUM_REG_RB_PHY    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_RENAME_NUM_REG_RC_PHY    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_RENAME_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_RENAME_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert);
+
+  DELETE1_SC_SIGNAL( in_INSERT_VAL               ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_ACK               ,_param->_nb_inst_insert);
+//DELETE1_SC_SIGNAL( in_INSERT_FRONT_END_ID      ,_param->_nb_inst_insert);
+//DELETE1_SC_SIGNAL( in_INSERT_CONTEXT_ID        ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_WRITE_RD          ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_WRITE_RE          ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_NUM_REG_RD_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_NUM_REG_RE_LOG    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_NUM_REG_RD_PHY    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_NUM_REG_RE_PHY    ,_param->_nb_inst_insert);
+
+  DELETE1_SC_SIGNAL( in_RETIRE_VAL               ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL(out_RETIRE_ACK               ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_FRONT_END_ID      ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_CONTEXT_ID        ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_WRITE_RD          ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_WRITE_RE          ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_LOG    ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_LOG    ,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL(out_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL(out_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire);
+  DELETE1_SC_SIGNAL(out_RETIRE_RESTORE           ,_param->_nb_inst_retire);
+
+  DELETE2_SC_SIGNAL( in_RETIRE_EVENT_VAL         ,_param->_nb_front_end,_param->_nb_context[it1]);
+  DELETE2_SC_SIGNAL(out_RETIRE_EVENT_ACK         ,_param->_nb_front_end,_param->_nb_context[it1]);
+  DELETE2_SC_SIGNAL( in_RETIRE_EVENT_STATE       ,_param->_nb_front_end,_param->_nb_context[it1]);
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp	(revision 128)
@@ -36,4 +36,6 @@
 	      rat_gpr_not_speculative   [i][j][0] = 0;
               rat_gpr_speculative_valid [i][j][0] = false;
+              rat_gpr_speculative       [i][j][0] = 0    ; // not necessary
+              rat_gpr_update_table      [i][j][0] = false; // not necessary
 
 	      for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters.cpp	(revision 128)
@@ -127,9 +127,9 @@
     log_printf(FUNC,Register_translation_unit,FUNCTION,"Begin");
 
-    delete [] _param_dependency_checking_unit;
-    delete [] _param_free_list_unit;
-    delete [] _param_register_address_translation_unit;
-    delete [] _param_stat_list_unit;    
-    delete [] _param_register_translation_unit_glue;
+    delete _param_dependency_checking_unit;
+    delete _param_free_list_unit;
+    delete _param_register_address_translation_unit;
+    delete _param_stat_list_unit;    
+    delete _param_register_translation_unit_glue;
 
     log_printf(FUNC,Register_translation_unit,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp	(revision 128)
@@ -135,4 +135,6 @@
       
       test (name,param);
+      
+      delete param;
     }
   catch (morpheo::ErrorMorpheo & error)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp	(revision 128)
@@ -48,4 +48,97 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_VAL               ;
+  sc_signal<Tcontrol_t        > *** out_RENAME_IN_ACK               ;
+  sc_signal<Tcontext_t        > ***  in_RENAME_IN_FRONT_END_ID      ;
+  sc_signal<Tcontext_t        > ***  in_RENAME_IN_CONTEXT_ID        ;
+  sc_signal<Tdepth_t          > ***  in_RENAME_IN_DEPTH             ;
+  sc_signal<Ttype_t           > ***  in_RENAME_IN_TYPE              ;
+  sc_signal<Toperation_t      > ***  in_RENAME_IN_OPERATION         ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_NO_EXECUTE        ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_LAST_EVENT        ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_IS_DELAY_SLOT     ;
+  sc_signal<Tgeneral_data_t   > ***  in_RENAME_IN_ADDRESS           ;
+  sc_signal<Tgeneral_data_t   > ***  in_RENAME_IN_ADDRESS_NEXT      ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_HAS_IMMEDIAT      ;
+  sc_signal<Tgeneral_data_t   > ***  in_RENAME_IN_IMMEDIAT          ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_READ_RA           ;
+  sc_signal<Tgeneral_address_t> ***  in_RENAME_IN_NUM_REG_RA        ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_READ_RB           ;
+  sc_signal<Tgeneral_address_t> ***  in_RENAME_IN_NUM_REG_RB        ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_READ_RC           ;
+  sc_signal<Tspecial_address_t> ***  in_RENAME_IN_NUM_REG_RC        ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_WRITE_RD          ;
+  sc_signal<Tgeneral_address_t> ***  in_RENAME_IN_NUM_REG_RD        ;
+  sc_signal<Tcontrol_t        > ***  in_RENAME_IN_WRITE_RE          ;
+  sc_signal<Tspecial_address_t> ***  in_RENAME_IN_NUM_REG_RE        ;
+  sc_signal<Texception_t      > ***  in_RENAME_IN_EXCEPTION_USE     ;
+  sc_signal<Texception_t      > ***  in_RENAME_IN_EXCEPTION         ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_VAL                  ;
+  sc_signal<Tcontrol_t        >  **  in_INSERT_ACK                  ;
+  sc_signal<Tcontext_t        >  ** out_INSERT_FRONT_END_ID         ;
+  sc_signal<Tcontext_t        >  ** out_INSERT_CONTEXT_ID           ;
+  sc_signal<Tdepth_t          >  ** out_INSERT_DEPTH                ;
+  sc_signal<Ttype_t           >  ** out_INSERT_TYPE                 ;
+  sc_signal<Toperation_t      >  ** out_INSERT_OPERATION            ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_NO_EXECUTE           ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_LAST_EVENT           ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_IS_DELAY_SLOT        ;
+  sc_signal<Tgeneral_data_t   >  ** out_INSERT_ADDRESS              ;
+  sc_signal<Tgeneral_data_t   >  ** out_INSERT_ADDRESS_NEXT         ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_HAS_IMMEDIAT         ;
+  sc_signal<Tgeneral_data_t   >  ** out_INSERT_IMMEDIAT             ;
+  sc_signal<Tlsq_ptr_t        >  ** out_INSERT_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t        >  ** out_INSERT_STORE_QUEUE_PTR_READ ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_STORE_QUEUE_EMPTY    ;
+  sc_signal<Tlsq_ptr_t        >  ** out_INSERT_LOAD_QUEUE_PTR_WRITE ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_READ_RA              ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RA_LOG       ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RA_PHY       ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_READ_RB              ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RB_LOG       ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RB_PHY       ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_READ_RC              ;
+  sc_signal<Tspecial_address_t>  ** out_INSERT_NUM_REG_RC_LOG       ;
+  sc_signal<Tspecial_address_t>  ** out_INSERT_NUM_REG_RC_PHY       ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_WRITE_RD             ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RD_LOG       ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RD_PHY_OLD   ;
+  sc_signal<Tgeneral_address_t>  ** out_INSERT_NUM_REG_RD_PHY_NEW   ;
+  sc_signal<Tcontrol_t        >  ** out_INSERT_WRITE_RE             ;
+  sc_signal<Tspecial_address_t>  ** out_INSERT_NUM_REG_RE_LOG       ;
+  sc_signal<Tspecial_address_t>  ** out_INSERT_NUM_REG_RE_PHY_OLD   ;
+  sc_signal<Tspecial_address_t>  ** out_INSERT_NUM_REG_RE_PHY_NEW   ;
+  sc_signal<Texception_t      >  ** out_INSERT_EXCEPTION_USE        ;
+  sc_signal<Texception_t      >  ** out_INSERT_EXCEPTION            ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_VAL                  ;
+  sc_signal<Tcontrol_t        >  ** out_RETIRE_ACK                  ;
+  sc_signal<Tcontext_t        >  **  in_RETIRE_FRONT_END_ID         ;
+  sc_signal<Tcontext_t        >  **  in_RETIRE_CONTEXT_ID           ;
+//sc_signal<Ttype_t           >  **  in_RETIRE_TYPE                 ;
+//sc_signal<Toperation_t      >  **  in_RETIRE_OPERATION            ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_USE_STORE_QUEUE      ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_USE_LOAD_QUEUE       ;
+  sc_signal<Tlsq_ptr_t        >  **  in_RETIRE_STORE_QUEUE_PTR_WRITE;
+  sc_signal<Tlsq_ptr_t        >  **  in_RETIRE_LOAD_QUEUE_PTR_WRITE ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_READ_RA              ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RA_PHY       ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_READ_RB              ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RB_PHY       ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_READ_RC              ;
+  sc_signal<Tspecial_address_t>  **  in_RETIRE_NUM_REG_RC_PHY       ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_WRITE_RD             ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RD_LOG       ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RD_PHY_OLD   ;
+  sc_signal<Tgeneral_address_t>  **  in_RETIRE_NUM_REG_RD_PHY_NEW   ;
+  sc_signal<Tcontrol_t        >  **  in_RETIRE_WRITE_RE             ;
+  sc_signal<Tspecial_address_t>  **  in_RETIRE_NUM_REG_RE_LOG       ;
+  sc_signal<Tspecial_address_t>  **  in_RETIRE_NUM_REG_RE_PHY_OLD   ;
+  sc_signal<Tspecial_address_t>  **  in_RETIRE_NUM_REG_RE_PHY_NEW   ;
+  sc_signal<Tcontrol_t        > ***  in_RETIRE_EVENT_VAL            ;
+  sc_signal<Tcontrol_t        > *** out_RETIRE_EVENT_ACK            ;
+  sc_signal<Tevent_state_t    > ***  in_RETIRE_EVENT_STATE          ;
+  sc_signal<Tspr_t            > ***  in_SPR_READ_SR                 ;
+  sc_signal<bool              >   *  in_INFO_ROB_EMPTY              ;
+
   ALLOC2_SC_SIGNAL( in_RENAME_IN_VAL               ," in_RENAME_IN_VAL               ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
   ALLOC2_SC_SIGNAL(out_RENAME_IN_ACK               ,"out_RENAME_IN_ACK               ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
@@ -56,8 +149,7 @@
   ALLOC2_SC_SIGNAL( in_RENAME_IN_OPERATION         ," in_RENAME_IN_OPERATION         ",Toperation_t      ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
   ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE        ," in_RENAME_IN_NO_EXECUTE        ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
+  ALLOC2_SC_SIGNAL( in_RENAME_IN_LAST_EVENT        ," in_RENAME_IN_LAST_EVENT        ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
   ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT     ," in_RENAME_IN_IS_DELAY_SLOT     ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
-#ifdef DEBUG
   ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS           ," in_RENAME_IN_ADDRESS           ",Tgeneral_data_t   ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
-#endif
   ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT      ," in_RENAME_IN_ADDRESS_NEXT      ",Tgeneral_data_t   ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
   ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT      ," in_RENAME_IN_HAS_IMMEDIAT      ",Tcontrol_t        ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
@@ -83,12 +175,13 @@
   ALLOC1_SC_SIGNAL(out_INSERT_OPERATION            ,"out_INSERT_OPERATION            ",Toperation_t      ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_NO_EXECUTE           ,"out_INSERT_NO_EXECUTE           ",Tcontrol_t        ,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL(out_INSERT_LAST_EVENT           ,"out_INSERT_LAST_EVENT           ",Tcontrol_t        ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT        ,"out_INSERT_IS_DELAY_SLOT        ",Tcontrol_t        ,_param->_nb_inst_insert);
-#ifdef DEBUG
   ALLOC1_SC_SIGNAL(out_INSERT_ADDRESS              ,"out_INSERT_ADDRESS              ",Tgeneral_data_t   ,_param->_nb_inst_insert);
-#endif
   ALLOC1_SC_SIGNAL(out_INSERT_ADDRESS_NEXT         ,"out_INSERT_ADDRESS_NEXT         ",Tgeneral_data_t   ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT         ,"out_INSERT_HAS_IMMEDIAT         ",Tcontrol_t        ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_IMMEDIAT             ,"out_INSERT_IMMEDIAT             ",Tgeneral_data_t   ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_STORE_QUEUE_PTR_WRITE,"out_INSERT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t        ,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL(out_INSERT_STORE_QUEUE_PTR_READ ,"out_INSERT_STORE_QUEUE_PTR_READ ",Tlsq_ptr_t        ,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL(out_INSERT_STORE_QUEUE_EMPTY    ,"out_INSERT_STORE_QUEUE_EMPTY    ",Tcontrol_t        ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_LOAD_QUEUE_PTR_WRITE ,"out_INSERT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t        ,_param->_nb_inst_insert);
   ALLOC1_SC_SIGNAL(out_INSERT_READ_RA              ,"out_INSERT_READ_RA              ",Tcontrol_t        ,_param->_nb_inst_insert);
@@ -139,4 +232,5 @@
   ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_STATE          ," in_RETIRE_EVENT_STATE          ",Tevent_state_t    ,_param->_nb_front_end,_param->_nb_context[it1]);
   ALLOC2_SC_SIGNAL( in_SPR_READ_SR                 ," in_SPR_READ_SR                 ",Tspr_t            ,_param->_nb_front_end,_param->_nb_context[it1]);
+  ALLOC0_SC_SIGNAL( in_INFO_ROB_EMPTY              ," in_INFO_ROB_EMPTY              ",bool              );
   
   /********************************************************
@@ -160,4 +254,5 @@
   INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_OPERATION         ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
   INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_NO_EXECUTE        ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
+  INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_LAST_EVENT        ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
   INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_IS_DELAY_SLOT     ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
 #ifdef DEBUG
@@ -191,4 +286,5 @@
   INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_OPERATION            ,_param->_nb_inst_insert);
   INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NO_EXECUTE           ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_LAST_EVENT           ,_param->_nb_inst_insert);
   INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_IS_DELAY_SLOT        ,_param->_nb_inst_insert);
 #ifdef DEBUG
@@ -199,4 +295,6 @@
   INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_IMMEDIAT             ,_param->_nb_inst_insert);
   INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_STORE_QUEUE_PTR_READ ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_STORE_QUEUE_EMPTY    ,_param->_nb_inst_insert);
   if (_param->_have_port_load_queue_ptr)
   INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_insert);
@@ -261,4 +359,7 @@
   INSTANCE2_SC_SIGNAL(_Rename_unit,in_SPR_READ_SR                  ,_param->_nb_front_end, _param->_nb_context[it1]);
 
+#ifdef DEBUG_TEST
+  INSTANCE0_SC_SIGNAL(_Rename_unit,in_INFO_ROB_EMPTY               );
+#endif
 
   msg(_("<%s> : Start Simulation ............\n"),name.c_str());
@@ -314,8 +415,7 @@
   DELETE2_SC_SIGNAL( in_RENAME_IN_OPERATION         ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
   DELETE2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE        ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
+  DELETE2_SC_SIGNAL( in_RENAME_IN_LAST_EVENT        ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
   DELETE2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT     ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
-#ifdef DEBUG
   DELETE2_SC_SIGNAL( in_RENAME_IN_ADDRESS           ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
-#endif
   DELETE2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT      ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
   DELETE2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT      ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);
@@ -342,12 +442,13 @@
   DELETE1_SC_SIGNAL(out_INSERT_OPERATION            ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_NO_EXECUTE           ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_LAST_EVENT           ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT        ,_param->_nb_inst_insert);
-#ifdef DEBUG
   DELETE1_SC_SIGNAL(out_INSERT_ADDRESS              ,_param->_nb_inst_insert);
-#endif
   DELETE1_SC_SIGNAL(out_INSERT_ADDRESS_NEXT         ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT         ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_IMMEDIAT             ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_STORE_QUEUE_PTR_READ ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_STORE_QUEUE_EMPTY    ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_insert);
   DELETE1_SC_SIGNAL(out_INSERT_EXCEPTION_USE        ,_param->_nb_inst_insert);
@@ -401,4 +502,6 @@
 
   DELETE2_SC_SIGNAL(in_SPR_READ_SR                  ,_param->_nb_front_end, _param->_nb_context[it1]);
+
+  DELETE0_SC_SIGNAL(in_INFO_ROB_EMPTY               );
     }
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp	(revision 128)
@@ -20,5 +20,5 @@
 #endif
 
-  simulation_init(0,0);
+  simulation_init(0,0,0,false,false);
 
   debug_idle_cycle = CYCLE_MAX;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/test.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/test.cpp	(revision 128)
@@ -47,4 +47,34 @@
   sc_clock              *  in_CLOCK  = new sc_clock ("clock", 1.0, 0.5);	 
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
+
+  sc_signal<Tcontrol_t    >   **  in_SPR_ACCESS_VAL         ;
+  sc_signal<Tcontrol_t    >   ** out_SPR_ACCESS_ACK         ;
+  sc_signal<Tcontext_t    >   **  in_SPR_ACCESS_FRONT_END_ID;
+  sc_signal<Tcontext_t    >   **  in_SPR_ACCESS_CONTEXT_ID  ;
+  sc_signal<Tcontrol_t    >   **  in_SPR_ACCESS_WEN         ;
+  sc_signal<Tspr_address_t>   **  in_SPR_ACCESS_NUM_GROUP   ;
+  sc_signal<Tspr_address_t>   **  in_SPR_ACCESS_NUM_REG     ;
+  sc_signal<Tspr_t        >   **  in_SPR_ACCESS_WDATA       ;
+  sc_signal<Tspr_t        >   ** out_SPR_ACCESS_RDATA       ;
+  sc_signal<Tcontrol_t    >   ** out_SPR_ACCESS_INVALID     ;
+
+  sc_signal<Tspr_t        >  *** out_SPR_READ_SR            ;
+
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_VAL         ;
+  sc_signal<Tcontrol_t    >  *** out_SPR_COMMIT_ACK         ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_SR_F_VAL    ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_SR_F        ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_SR_CY_VAL   ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_SR_CY       ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_SR_OV_VAL   ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_COMMIT_SR_OV       ;
+
+  sc_signal<Tcontrol_t    >  ***  in_SPR_EVENT_VAL          ;
+  sc_signal<Tcontrol_t    >  *** out_SPR_EVENT_ACK          ;
+  sc_signal<Tspr_t        >  ***  in_SPR_EVENT_EPCR         ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_EVENT_EEAR_WEN     ;
+  sc_signal<Tspr_t        >  ***  in_SPR_EVENT_EEAR         ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_EVENT_SR_DSX       ;
+  sc_signal<Tcontrol_t    >  ***  in_SPR_EVENT_SR_TO_ESR    ;
 
   ALLOC1_SC_SIGNAL( in_SPR_ACCESS_VAL         ," in_SPR_ACCESS_VAL         ",Tcontrol_t    ,_param->_nb_inst_reexecute);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h	(revision 128)
@@ -578,4 +578,5 @@
   public : void   reset (void  ) 
     {
+      thread_id = 0; // not necessary
     };
   public : Tspr_t read  (void  )
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp	(revision 128)
@@ -158,4 +158,6 @@
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+    for (uint32_t i=0; i<_param->_nb_rename_unit; ++i)
+    delete    _component_rename_unit [i]       ;
     delete [] _component_rename_unit           ;
     delete    _component_commit_unit           ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp	(revision 128)
@@ -411,4 +411,6 @@
     delete [] _link_front_end_with_rename_unit             ;
 
+    for (uint32_t i=0; i<_nb_rename_unit; i++)
+    delete    _param_rename_unit [i]      ;
     delete [] _param_rename_unit          ;
     delete    _param_commit_unit          ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp	(revision 128)
@@ -61,16 +61,16 @@
     delete _component;
 
-//     delete    _component_glue;
-//     delete    _component_dcache_access;
-//     delete    _component_icache_access;
-//     for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
-//     delete    _component_execute_loop [i];
-//     delete [] _component_execute_loop;
-//     for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
-//     delete    _component_ooo_engine [i];
-//     delete [] _component_ooo_engine;
-//     for (uint32_t i=0; i<_param->_nb_front_end; ++i)
-//     delete    _component_front_end [i];
-//     delete [] _component_front_end;
+    delete    _component_glue;
+    delete    _component_dcache_access;
+    delete    _component_icache_access;
+    for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
+    delete    _component_execute_loop [i];
+    delete [] _component_execute_loop;
+    for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
+    delete    _component_ooo_engine [i];
+    delete [] _component_ooo_engine;
+    for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+    delete    _component_front_end [i];
+    delete [] _component_front_end;
 
     log_end(Core,FUNCTION);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp	(revision 128)
@@ -394,9 +394,13 @@
         _link_thread_with_context [x.first][x.second] = i;
       }
+
+//     log_printf(TRACE,Core,FUNCTION,_("  * _link_decod_unit_with_decod_bloc"));
     for (uint32_t i=0; i<_nb_decod_bloc; ++i)
       {
         pair_dual x = _link_decod_unit_with_decod_bloc[i];
         _link_decod_bloc_with_decod_unit [x.first][x.second] = i;
+//         log_printf(TRACE,Core,FUNCTION,_("    [%d][%d] -> %d"),x.first,x.second,i);
       }
+
     for (uint32_t i=0; i<_nb_rename_bloc; ++i)
       {
@@ -803,4 +807,6 @@
     ALLOC2(_front_end_context_select_load_balancing       ,Tload_balancing_t,_nb_front_end,_nb_decod_unit[it1]);
 
+    log_printf(TRACE,Core,FUNCTION,_("  * decod_unit"));
+
     for (uint32_t i=0; i<_nb_front_end; ++i)
       {
@@ -813,5 +819,7 @@
           {
             uint32_t num_decod_bloc=_link_decod_bloc_with_decod_unit[i][j];
-            
+           
+            log_printf(TRACE,Core,FUNCTION,_("  [%d][%d] -> %d"),i,j,num_decod_bloc);
+ 
             _front_end_size_decod_queue              [i][j] = _size_decod_queue              [num_decod_bloc];
             _front_end_decod_queue_scheme            [i][j] = _decod_queue_scheme            [num_decod_bloc];
@@ -1827,13 +1835,15 @@
           uint32_t num_load_store_unit = _list_load_store_unit_with_execute_unit [i][j];
           
-          uint32_t num_thread;
-          for (num_thread = 0; num_thread<_nb_thread; ++num_thread)
-            if (_link_load_store_unit_with_thread [num_thread] == num_load_store_unit)
-              break;
-          
+          {
+            uint32_t num_thread;
+            for (num_thread = 0; num_thread<_nb_thread; ++num_thread)
+              if (_link_load_store_unit_with_thread [num_thread] == num_load_store_unit)
+                break;
 #ifdef DEBUG_TEST
-          if (num_thread == _nb_thread)
-            throw ERRORMORPHEO(FUNCTION,toString(_("Load_store_unit [%d] is not link with a thread.\n"),num_load_store_unit));
+            if (num_thread == _nb_thread)
+              throw ERRORMORPHEO(FUNCTION,toString(_("Load_store_unit [%d] is not link with a thread.\n"),num_load_store_unit));
 #endif 
+          }
+
           // init with an invalid thread_id
           for (uint32_t k=0; k<_dcache_access_nb_context [i]; ++k)
@@ -1858,9 +1868,12 @@
                       uint32_t num_thread = _link_thread_with_context [num_front_end][num_context];
                       
-                      uint32_t index = ((num_ooo_engine<<(_size_context_id + _size_front_end_id )) |
-                                        (num_front_end <<(_size_context_id)) |
-                                        (num_context));
-                      
-                      _dcache_access_translate_load_store_unit_to_thread [i][j][index] = num_thread;
+                      if (_link_load_store_unit_with_thread [num_thread] == num_load_store_unit)
+                        {
+                          uint32_t index = ((num_ooo_engine<<(_size_context_id + _size_front_end_id )) |
+                                            (num_front_end <<(_size_context_id)) |
+                                            (num_context));
+                          
+                          _dcache_access_translate_load_store_unit_to_thread [i][j][index] = num_thread;
+                        }
                     }
                 }
@@ -1960,5 +1973,5 @@
         _nb_thread                                 ,
         _link_thread_with_context               [i]
-        );
+         );
 
     ALLOC1(_nb_inst_issue_queue,uint32_t,_nb_ooo_engine);
@@ -2181,17 +2194,19 @@
     log_begin(Core,FUNCTION);
 
-//     for (uint32_t i=0; i<_nb_front_end; ++i)
-//     delete    _param_front_end [i];
-//     delete [] _param_front_end;
-//     for (uint32_t i=0; i<_nb_ooo_engine; ++i)
-//     delete    _param_ooo_engine [i];
-//     delete [] _param_ooo_engine;
-//     for (uint32_t i=0; i<_nb_execute_loop; ++i)
-//     delete    _param_execute_loop [i];
-//     delete [] _param_execute_loop;
-//     delete    _param_icache_access;
-//     delete    _param_dcache_access;
-//     delete    _param_glue;
-
+    for (uint32_t i=0; i<_nb_front_end; ++i)
+    delete    _param_front_end [i];
+    delete [] _param_front_end;
+    for (uint32_t i=0; i<_nb_ooo_engine; ++i)
+    delete    _param_ooo_engine [i];
+    delete [] _param_ooo_engine;
+    for (uint32_t i=0; i<_nb_execute_loop; ++i)
+    delete    _param_execute_loop [i];
+    delete [] _param_execute_loop;
+    delete    _param_icache_access;
+    delete    _param_dcache_access;
+    delete    _param_glue;
+
+    DELETE1(_nb_inst_issue_queue                                    ,_nb_ooo_engine);
+    DELETE1(_issue_queue_in_order                                   ,_nb_ooo_engine);
     DELETE3(_dcache_access_translate_load_store_unit_to_thread      ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1],_dcache_access_nb_context[it1]);
     DELETE1(_dcache_access_nb_context                               ,_nb_execute_loop);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_msg_error.cpp	(revision 127)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_msg_error.cpp	(revision 128)
@@ -59,6 +59,25 @@
       // set link
       for (uint32_t i=0; i<_nb_decod_bloc; ++i)
-        nb_link_decod_unit[_link_decod_unit_with_decod_bloc[i].first][_link_decod_unit_with_decod_bloc[i].second] ++;
-
+        {
+          uint32_t num_front_end  = _link_decod_unit_with_decod_bloc[i].first;
+          uint32_t num_decod_unit = _link_decod_unit_with_decod_bloc[i].second;
+
+          bool error = false;
+
+          if (num_front_end >= _nb_front_end)
+            {
+              error = true;
+              test.error(toString(_("Decod_bloc [%d] is connected with an invalid front_end (%d).\n"),i,num_front_end));
+            }
+
+          if (num_decod_unit >= _nb_decod_unit[num_front_end])
+            {
+              error = true;
+              test.error(toString(_("Decod_bloc [%d] is connected with an invalid decod_unit (%d.%d).\n"),i,num_front_end,num_decod_unit));
+            }
+
+          if (not error)
+            nb_link_decod_unit[num_front_end][num_decod_unit] ++;
+        }
       // test
       for (uint32_t i=0; i<_nb_front_end; ++i)
