Changeset 131 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic
- Timestamp:
- Jul 8, 2009, 8:40:08 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic
- Files:
-
- 2 added
- 13 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp
r113 r131 32 32 exit (EXIT_FAILURE); 33 33 } 34 35 _model.set_model(MODEL_SYSTEMC,true); 34 36 35 37 Tusage_t _usage = USE_ALL; … … 123 125 // Initialisation 124 126 125 sc_start(0);127 SC_START(0); 126 128 127 129 for (uint32_t i=0; i<_param->_nb_port_write; i++) … … 134 136 NRESET.write(0); 135 137 136 sc_start(5);138 SC_START(5); 137 139 138 140 NRESET.write(1); 139 141 142 for (uint32_t i=0; i<_param->_nb_port_write; i++) 143 TEST(Tcontrol_t,WRITE_ACK [i],1); 144 for (uint32_t i=0; i<_param->_nb_port_read; i++) 145 TEST(Tcontrol_t,READ_ACK [i],1); 146 for (uint32_t i=0; i<_param->_nb_port_read_write; i++) 147 TEST(Tcontrol_t,READ_WRITE_ACK [i],1); 140 148 141 149 for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++) … … 159 167 while (nb_ack < _param->_nb_word) 160 168 { 169 161 170 cout << "cycle : " << static_cast<uint32_t> (simulation_cycle()) << endl; 162 171 … … 196 205 } 197 206 198 sc_start(1);207 SC_START(1); 199 208 200 209 // reset write_val port … … 219 228 } 220 229 221 sc_start(0);230 // SC_START(0); 222 231 } 223 232 … … 266 275 267 276 268 sc_start(1);277 SC_START(1); 269 278 270 279 // reset write_val port … … 297 306 } 298 307 299 sc_start(0);308 // SC_START(0); 300 309 } 301 310 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h
r82 r131 114 114 115 115 #ifdef SYSTEMC 116 public : void constant (void); 116 117 public : void transition (void); 117 118 //public : void genMoore (void) {/* empty */}; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp
r123 r131 56 56 if (usage_is_set(_usage,USE_SYSTEMC)) 57 57 { 58 59 # ifdef SYSTEMCASS_SPECIFIC 60 constant(); 61 #else 62 SC_METHOD (constant); 63 // dont_initialize (); 64 #endif 65 58 66 SC_METHOD (transition); 59 67 dont_initialize (); 60 68 sensitive << (*(in_CLOCK)).pos(); 61 69 62 70 SC_METHOD (genMealy_read); 63 71 dont_initialize (); … … 93 101 } 94 102 # endif 95 96 for (uint32_t i=0; i<_param->_nb_port_read ; i++)97 PORT_WRITE(out_READ_ACK [i], 1);98 for (uint32_t i=0; i<_param->_nb_port_write ; i++)99 PORT_WRITE(out_WRITE_ACK [i], 1);100 for (uint32_t i=0; i<_param->_nb_port_read_write ; i++)101 PORT_WRITE(out_READ_WRITE_ACK [i], 1);102 103 } 103 104 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp
r128 r131 114 114 115 115 #if defined(DEBUG_RegisterFile_Monolithic) and DEBUG_RegisterFile_Monolithic and (DEBUG >= DEBUG_TRACE) 116 if (0) 116 # if 1 117 117 { 118 118 log_printf(TRACE,RegisterFile,FUNCTION," * Dump RegisterFile"); … … 136 136 } 137 137 } 138 # endif 138 139 #endif 139 140 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp
r113 r131 23 23 #endif 24 24 25 _model.set_model(MODEL_SYSTEMC,true); 26 25 27 Tusage_t _usage = USE_ALL; 26 28 … … 30 32 // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); 31 33 // _usage = usage_unset(_usage,USE_POSITION ); 32 _usage = usage_unset(_usage,USE_STATISTICS );34 // _usage = usage_unset(_usage,USE_STATISTICS ); 33 35 // _usage = usage_unset(_usage,USE_INFORMATION ); 34 36 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/src/test.cpp
r113 r131 21 21 morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics(5,50); 22 22 #endif 23 24 _model.set_model(MODEL_SYSTEMC,true); 23 25 24 26 Tusage_t _usage = USE_ALL; … … 170 172 } 171 173 172 SC_START(0);174 // SC_START(0); 173 175 } 174 176 … … 219 221 } 220 222 221 SC_START(0);223 // SC_START(0); 222 224 } 223 225 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_allocation.cpp
r82 r131 3 3 * $Id$ 4 4 * 5 * [ 5 * [ Description ] 6 6 * 7 7 */ 8 8 9 9 #include "Behavioural/Generic/RegisterFile/include/RegisterFile.h" 10 #include "Behavioural/include/Allocation.h" 10 11 11 12 namespace morpheo { … … 13 14 namespace generic { 14 15 namespace registerfile { 15 16 16 17 17 void RegisterFile::allocation ( … … 27 27 log_printf(FUNC,RegisterFile,"allocation","Begin"); 28 28 29 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 #ifdef SYSTEMCASS_SPECIFIC 30 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 30 31 { 31 in_CLOCK = new SC_CLOCK ("in_CLOCK");32 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET");32 __ALLOC0_SIGNAL(in_CLOCK ,"in_CLOCK" ,SC_CLOCK ); 33 __ALLOC0_SIGNAL(in_NRESET,"in_NRESET",SC_IN (Tcontrol_t)); 33 34 } 34 // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 35 // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 36 { 37 __ALLOC1_INTERFACE_BEGIN("READ",_param->_nb_port_read); 35 38 36 in_READ_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read];37 out_READ_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read];38 if (_param->_have_port_address == true)39 in_READ_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read];40 out_READ_DATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read];39 __ALLOC1_SIGNAL_IN ( in_READ_VAL ,"VAL" ,Tcontrol_t); 40 __ALLOC1_SIGNAL_OUT(out_READ_ACK ,"ACK" ,Tcontrol_t); 41 if (_param->_have_port_address) 42 __ALLOC1_SIGNAL_IN ( in_READ_ADDRESS,"ADDRESS",Taddress_t); 43 __ALLOC1_SIGNAL_OUT(out_READ_DATA ,"DATA" ,Tdata_t ); 41 44 42 for (uint32_t i=0; i<_param->_nb_port_read; i++) 43 { 44 rename = "in_READ_"+toString(i)+"_VAL" ; 45 in_READ_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 46 rename = "out_READ_"+toString(i)+"_ACK" ; 47 out_READ_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 48 if (_param->_have_port_address == true) 49 { 50 rename = "in_READ_"+toString(i)+"_ADDRESS"; 51 in_READ_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 52 } 53 rename = "out_READ_"+toString(i)+"_DATA" ; 54 out_READ_DATA [i] = new SC_OUT(Tdata_t ) (rename.c_str()); 55 } 45 __ALLOC1_INTERFACE_END(_param->_nb_port_read); 46 } 56 47 57 // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 48 // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 49 { 50 __ALLOC1_INTERFACE_BEGIN("WRITE",_param->_nb_port_write); 58 51 59 in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_write]; 60 out_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_write]; 61 if (_param->_have_port_address == true) 62 in_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_write]; 63 in_WRITE_DATA = new SC_IN (Tdata_t ) * [_param->_nb_port_write]; 64 65 for (uint32_t i=0; i<_param->_nb_port_write; i++) 66 { 67 rename = "in_WRITE_"+toString(i)+"_VAL" ; 68 in_WRITE_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 69 rename = "out_WRITE_"+toString(i)+"_ACK" ; 70 out_WRITE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 71 if (_param->_have_port_address == true) 72 { 73 rename = "in_WRITE_"+toString(i)+"_ADDRESS"; 74 in_WRITE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 75 } 76 rename = "in_WRITE_"+toString(i)+"_DATA" ; 77 in_WRITE_DATA [i] = new SC_IN (Tdata_t ) (rename.c_str()); 78 } 52 __ALLOC1_SIGNAL_IN ( in_WRITE_VAL ,"VAL" ,Tcontrol_t); 53 __ALLOC1_SIGNAL_OUT(out_WRITE_ACK ,"ACK" ,Tcontrol_t); 54 if (_param->_have_port_address) 55 __ALLOC1_SIGNAL_IN ( in_WRITE_ADDRESS,"ADDRESS",Taddress_t); 56 __ALLOC1_SIGNAL_IN ( in_WRITE_DATA ,"DATA" ,Tdata_t ); 79 57 80 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 58 __ALLOC1_INTERFACE_END(_param->_nb_port_write); 59 } 60 #endif 61 62 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 81 63 if (_param->_instance == instance_RegisterFile_Monolithic) 82 64 // =====[ component_RegisterFile_Monolithic ]========================= … … 106 88 // =====[ Component_RegisterFile_Monolithic - Instanciation ]========= 107 89 { 108 (*(component_RegisterFile_Monolithic ->in_CLOCK )) (*(in_CLOCK )); 90 #ifdef SYSTEMCASS_SPECIFIC 91 (*(component_RegisterFile_Monolithic ->in_CLOCK )) (*(in_CLOCK )); 109 92 (*(component_RegisterFile_Monolithic ->in_NRESET)) (*(in_NRESET)); 110 93 … … 126 109 (*(component_RegisterFile_Monolithic -> in_WRITE_DATA [i])) (*( in_WRITE_DATA [i])); 127 110 } 111 #else 112 in_CLOCK = component_RegisterFile_Monolithic-> in_CLOCK ; 113 in_NRESET = component_RegisterFile_Monolithic-> in_NRESET ; 114 115 in_READ_VAL = component_RegisterFile_Monolithic-> in_READ_VAL ; 116 out_READ_ACK = component_RegisterFile_Monolithic->out_READ_ACK ; 117 in_READ_ADDRESS = component_RegisterFile_Monolithic-> in_READ_ADDRESS ; 118 out_READ_DATA = component_RegisterFile_Monolithic->out_READ_DATA ; 119 120 in_WRITE_VAL = component_RegisterFile_Monolithic-> in_WRITE_VAL ; 121 out_WRITE_ACK = component_RegisterFile_Monolithic->out_WRITE_ACK ; 122 in_WRITE_ADDRESS = component_RegisterFile_Monolithic-> in_WRITE_ADDRESS; 123 in_WRITE_DATA = component_RegisterFile_Monolithic-> in_WRITE_DATA ; 124 #endif 128 125 } 129 126 else 130 127 // =====[ Component_RegisterFile_Multi_Banked - Instanciation ]======= 131 128 { 129 #ifdef SYSTEMCASS_SPECIFIC 132 130 (*(component_RegisterFile_Multi_Banked->in_CLOCK )) (*(in_CLOCK )); 133 131 (*(component_RegisterFile_Multi_Banked->in_NRESET)) (*(in_NRESET)); … … 150 148 (*(component_RegisterFile_Multi_Banked-> in_WRITE_DATA [i])) (*( in_WRITE_DATA [i])); 151 149 } 150 #else 151 in_CLOCK = component_RegisterFile_Multi_Banked-> in_CLOCK ; 152 in_NRESET = component_RegisterFile_Multi_Banked-> in_NRESET ; 153 154 in_READ_VAL = component_RegisterFile_Multi_Banked-> in_READ_VAL ; 155 out_READ_ACK = component_RegisterFile_Multi_Banked->out_READ_ACK ; 156 in_READ_ADDRESS = component_RegisterFile_Multi_Banked-> in_READ_ADDRESS ; 157 out_READ_DATA = component_RegisterFile_Multi_Banked->out_READ_DATA ; 158 159 in_WRITE_VAL = component_RegisterFile_Multi_Banked-> in_WRITE_VAL ; 160 out_WRITE_ACK = component_RegisterFile_Multi_Banked->out_WRITE_ACK ; 161 in_WRITE_ADDRESS = component_RegisterFile_Multi_Banked-> in_WRITE_ADDRESS; 162 in_WRITE_DATA = component_RegisterFile_Multi_Banked-> in_WRITE_DATA ; 163 #endif 164 152 165 } 153 166 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_deallocation.cpp
r128 r131 3 3 * $Id$ 4 4 * 5 * [ 5 * [ Description ] 6 6 * 7 7 */ … … 19 19 log_printf(FUNC,RegisterFile,"deallocation","Begin"); 20 20 21 #ifdef SYSTEMCASS_SPECIFIC 21 22 delete in_CLOCK; 22 23 delete in_NRESET; … … 52 53 delete [] in_WRITE_ADDRESS; 53 54 delete [] in_WRITE_DATA ; 55 #endif 54 56 55 // ~~~~~[ 57 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 56 58 57 59 // delete _component; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed.cpp
r97 r131 69 69 SC_METHOD (transition); 70 70 dont_initialize (); 71 sensitive _pos << *(in_CLOCK);71 sensitive << (*(in_CLOCK)).pos(); 72 72 # endif 73 73 … … 76 76 SC_METHOD (genMealy_entity); 77 77 dont_initialize (); 78 //sensitive_pos << *(in_CLOCK);79 78 for (uint32_t i=0; i<_param->_nb_entity; i++) 80 79 sensitive << *(in_VAL [i]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Victim_Pseudo_LRU.h
r88 r131 116 116 117 117 #ifdef SYSTEMC 118 public : void constant (void); 118 119 public : void transition (void); 119 120 public : void genMealy (void); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU.cpp
r123 r131 63 63 if (usage_is_set(_usage,USE_SYSTEMC)) 64 64 { 65 // Constant - ack is always at one 66 for (uint32_t i=0; i<_param->_nb_access; i++) 67 { 68 internal_ACCESS_ACK [i] = 1; 69 PORT_WRITE (out_ACCESS_ACK [i], internal_ACCESS_ACK [i]); 70 } 65 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Definition of sc_method"); 71 66 72 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Definition of sc_method"); 67 #ifdef SYSTEMCASS_SPECIFIC 68 constant(); 69 #else 70 SC_METHOD (constant); 71 // dont_initialize (); 72 #endif 73 73 74 SC_METHOD (transition); 74 75 dont_initialize (); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim_allocation.cpp
r112 r131 28 28 log_printf(FUNC,Victim,FUNCTION,"Begin"); 29 29 30 30 #ifdef SYSTEMCASS_SPECIFIC 31 31 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 32 { 33 __ALLOC0_SIGNAL (in_CLOCK ,"in_CLOCK" ,SC_CLOCK );34 __ALLOC0_SIGNAL (in_NRESET,"in_NRESET",SC_IN(Tcontrol_t));33 __ALLOC0_SIGNAL (in_CLOCK ,"in_CLOCK" ,SC_CLOCK ); 34 __ALLOC0_SIGNAL (in_NRESET,"in_NRESET",SC_IN(Tcontrol_t)); 35 35 } 36 36 … … 49 49 __ALLOC1_INTERFACE_END(_param->_nb_access); 50 50 } 51 #endif 51 52 52 53 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 88 89 case VICTIM_PSEUDO_LRU : 89 90 { 91 #ifdef SYSTEMCASS_SPECIFIC 90 92 { 91 93 (*(_component_victim_pseudo_lru-> in_CLOCK )) (*( in_CLOCK)); … … 103 105 (*(_component_victim_pseudo_lru->out_ACCESS_VICTIM [i])) (*(out_ACCESS_VICTIM [i])); 104 106 } 105 107 #else 108 in_CLOCK = _component_victim_pseudo_lru-> in_CLOCK ; 109 in_NRESET = _component_victim_pseudo_lru-> in_NRESET ; 110 in_ACCESS_VAL = _component_victim_pseudo_lru-> in_ACCESS_VAL ; 111 out_ACCESS_ACK = _component_victim_pseudo_lru->out_ACCESS_ACK ; 112 in_ACCESS_ADDRESS = _component_victim_pseudo_lru-> in_ACCESS_ADDRESS; 113 in_ACCESS_HIT = _component_victim_pseudo_lru-> in_ACCESS_HIT ; 114 in_ACCESS_ENTITY = _component_victim_pseudo_lru-> in_ACCESS_ENTITY ; 115 out_ACCESS_VICTIM = _component_victim_pseudo_lru->out_ACCESS_VICTIM ; 116 #endif 106 117 break; 107 118 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim_deallocation.cpp
r128 r131 35 35 if (usage_is_set(_usage,USE_SYSTEMC)) 36 36 { 37 #ifdef SYSTEMCASS_SPECIFIC 37 38 delete in_CLOCK ; 38 39 delete in_NRESET; … … 56 57 delete [] in_ACCESS_ENTITY ; 57 58 delete [] out_ACCESS_VICTIM ; 59 #endif 58 60 } 59 61
Note: See TracChangeset
for help on using the changeset viewer.