Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue.cpp	(revision 135)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue.cpp	(revision 136)
@@ -74,4 +74,27 @@
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
+        // Function pointer
+        switch (_param->_queue_scheme)
+          {
+          case IFETCH_QUEUE_SCHEME_NO_ASSOC :
+            {
+              function_transition         = &morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue::function_no_assoc_transition        ;
+              function_genMoore           = &morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue::function_no_assoc_genMoore          ;
+              
+              break;
+            }
+          case IFETCH_QUEUE_SCHEME_FULL_ASSOC :
+            {
+              function_transition         = &morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue::function_full_assoc_transition        ;
+              function_genMoore           = &morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue::function_full_assoc_genMoore          ;
+              
+              break;
+            }
+          default :
+            {
+              break;
+            }
+          }
+
 	log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Method - constant"),_name.c_str());
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp	(revision 135)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp	(revision 136)
@@ -84,19 +84,23 @@
       ALLOC1_VALACK_OUT(out_DECOD_VAL        ,VAL);
       ALLOC1_VALACK_IN ( in_DECOD_ACK        ,ACK);
-      ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION,"instruction",Tinstruction_t,_param->_size_instruction);
+      ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION                ,"instruction"                ,Tinstruction_t    ,_param->_size_instruction);
+      ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address);
+      ALLOC1_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
+      ALLOC1_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
+      ALLOC1_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
 
       ALLOC1_INTERFACE_END(_param->_nb_instruction);
     }
-    {
-      ALLOC0_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage."));
+//     {
+//       ALLOC0_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage."));
       
-      ALLOC0_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address         );
-      ALLOC0_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr );
-      ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state    );
-      ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth           );
-      ALLOC0_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
+//       ALLOC0_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address         );
+//       ALLOC0_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr );
+//       ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state    );
+//       ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth           );
+//       ALLOC0_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
 
-      ALLOC0_INTERFACE_END();
-    }
+//       ALLOC0_INTERFACE_END();
+//     }
 
     // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -132,6 +136,11 @@
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
-        ALLOC1(internal_DECOD_VAL,Tcontrol_t,_param->_nb_instruction);
-        
+        ALLOC1(internal_DECOD_VAL ,Tcontrol_t,_param->_nb_instruction);
+	if (_param->_queue_scheme == IFETCH_QUEUE_SCHEME_FULL_ASSOC)
+	  {
+        ALLOC1(internal_DECOD_PTR ,uint32_t  ,_param->_nb_instruction);
+        ALLOC1(internal_DECOD_SLOT,uint32_t  ,_param->_nb_instruction);
+	  }
+
         _queue = new ifetch_queue_entry_t * [_param->_size_queue];
         for (uint32_t i=0;i<_param->_size_queue; i++)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp	(revision 135)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp	(revision 136)
@@ -41,9 +41,13 @@
         DELETE1_SIGNAL( in_DECOD_ACK                        ,_param->_nb_instruction,1);
         DELETE1_SIGNAL(out_DECOD_INSTRUCTION                ,_param->_nb_instruction,_param->_size_instruction);
-        DELETE0_SIGNAL(out_DECOD_ADDRESS                    ,_param->_size_instruction_address);
-        DELETE0_SIGNAL(out_DECOD_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr );
-        DELETE0_SIGNAL(out_DECOD_BRANCH_STATE               ,_param->_size_branch_state    );
-        DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth           );
-        DELETE0_SIGNAL(out_DECOD_EXCEPTION                  ,_param->_size_exception_ifetch);
+        DELETE1_SIGNAL(out_DECOD_ADDRESS                    ,_param->_nb_instruction,_param->_size_instruction_address);
+        DELETE1_SIGNAL(out_DECOD_BRANCH_STATE               ,_param->_nb_instruction,_param->_size_branch_state);
+        DELETE1_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_instruction,_param->_size_depth);
+        DELETE1_SIGNAL(out_DECOD_EXCEPTION                  ,_param->_nb_instruction,_param->_size_exception_ifetch);
+//         DELETE0_SIGNAL(out_DECOD_ADDRESS                    ,_param->_size_instruction_address);
+//         DELETE0_SIGNAL(out_DECOD_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr );
+//         DELETE0_SIGNAL(out_DECOD_BRANCH_STATE               ,_param->_size_branch_state    );
+//         DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth           );
+//         DELETE0_SIGNAL(out_DECOD_EXCEPTION                  ,_param->_size_exception_ifetch);
 
         DELETE0_SIGNAL( in_ICACHE_RSP_VAL        ,1);
@@ -60,5 +64,10 @@
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
-        DELETE1(internal_DECOD_VAL,_param->_nb_instruction);
+        DELETE1(internal_DECOD_VAL ,_param->_nb_instruction);
+	if (_param->_queue_scheme == IFETCH_QUEUE_SCHEME_FULL_ASSOC)
+	  {
+        DELETE1(internal_DECOD_PTR ,_param->_nb_instruction);
+        DELETE1(internal_DECOD_SLOT,_param->_nb_instruction);
+	  }
        
         for (uint32_t i=0;i<_param->_size_queue; i++)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_full_assoc_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_full_assoc_genMoore.cpp	(revision 136)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_full_assoc_genMoore.cpp	(revision 136)
@@ -0,0 +1,132 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_front_end {
+namespace front_end {
+namespace ifetch_unit {
+namespace ifetch_queue {
+
+#undef  FUNCTION
+#define FUNCTION "Ifetch_queue::function_full_assoc_genMoore"
+  void Ifetch_queue::function_full_assoc_genMoore (void)
+  {
+    log_begin(Ifetch_queue,FUNCTION);
+    log_function(Ifetch_queue,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET))
+      {
+    // ==========================================================
+    // =====[ ADDRESS ]==========================================
+    // ==========================================================
+    {
+      internal_ADDRESS_ACK = (_queue[reg_PTR_WRITE]->_state == IFETCH_QUEUE_STATE_EMPTY);
+ 
+      log_printf(TRACE,Ifetch_queue,FUNCTION,"  * ADDRESS_ACK : %d",internal_ADDRESS_ACK);
+     
+      if (_param->_have_port_ifetch_queue_ptr)
+      PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE);
+    }
+
+    // ==========================================================
+    // =====[ DECOD ]============================================
+    // ==========================================================
+    {
+      bool     stop = false;
+      uint32_t inst = 0;
+
+      // init
+      for (uint32_t i=0; i<_param->_nb_instruction; ++i)
+	internal_DECOD_VAL [i] = 0;
+
+      for (uint32_t i=0; i<_param->_size_queue; ++i)
+	{	
+	  uint32_t ptr = (reg_PTR_READ+i)%_param->_size_queue;
+  
+	  // Test if have an respons
+	  if (_queue[ptr]->_state == IFETCH_QUEUE_STATE_HAVE_RSP)
+	    {
+	      for (uint32_t j=0; j<_param->_nb_instruction; j++)
+		{
+		  // test if instruction is enable
+		  if (_queue[ptr]->_instruction_enable [j])
+		    {
+		      log_printf(TRACE,Ifetch_queue,FUNCTION,"  * DECOD_VAL [%d] : ifetch_queue[%d][%d]",inst,ptr,j);
+		      
+		      // Find an valid instruction
+		      internal_DECOD_VAL [inst] = true;
+		      internal_DECOD_PTR [inst] = ptr;
+		      internal_DECOD_SLOT[inst] = j;
+		      
+		      // Get info
+		      Tgeneral_address_t address                     = _queue[ptr]->_address;
+		      Tinst_ifetch_ptr_t inst_ifetch_ptr             = _queue[ptr]->_inst_ifetch_ptr;
+		      Tbranch_state_t    branch_state                = _queue[ptr]->_branch_state;
+		      Tprediction_ptr_t  branch_update_prediction_id = _queue[ptr]->_branch_update_prediction_id;
+		      Texception_t       exception                   = _queue[ptr]->_exception;
+		      
+		      PORT_WRITE(out_DECOD_INSTRUCTION                [inst],_queue[ptr]->_instruction [j]);
+		      PORT_WRITE(out_DECOD_ADDRESS                    [inst],address+j);
+		      
+		      // Warning : ONE BRANCH PER SLOT
+		      if (inst_ifetch_ptr == j)
+		      PORT_WRITE(out_DECOD_BRANCH_STATE               [inst],branch_state);
+		      else
+		      PORT_WRITE(out_DECOD_BRANCH_STATE               [inst],BRANCH_STATE_NONE);
+		      if (_param->_have_port_depth)
+		      PORT_WRITE(out_DECOD_BRANCH_UPDATE_PREDICTION_ID[inst],branch_update_prediction_id);
+		      PORT_WRITE(out_DECOD_EXCEPTION                  [inst],exception); // all is same
+		      
+		      inst ++;
+		      
+		      // Test if have all slot
+		      if (inst >= _param->_nb_instruction)
+			stop = true;
+		    }
+		  if (stop)
+		    break;
+		}
+	    }
+	  else
+	    stop = true; // slot have not respons -> exit the loop
+	 
+	  // if not find an valid instruction, break the loop
+	  if (stop)
+	    break;
+	}
+    }
+      }
+    else
+      {
+        // Reset
+        internal_ADDRESS_ACK = 0;
+        for (uint32_t i=0; i<_param->_nb_instruction; i++)
+          internal_DECOD_VAL [i] = 0;
+        
+      }
+
+    // Write Output
+    PORT_WRITE(out_ADDRESS_ACK  , internal_ADDRESS_ACK);
+    for (uint32_t i=0; i<_param->_nb_instruction; i++)
+    PORT_WRITE(out_DECOD_VAL [i], internal_DECOD_VAL [i]);
+
+    log_end(Ifetch_queue,FUNCTION);
+  };
+
+}; // end namespace ifetch_queue
+}; // end namespace ifetch_unit
+}; // end namespace front_end
+}; // end namespace multi_front_end
+}; // end namespace core
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_full_assoc_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_full_assoc_transition.cpp	(revision 136)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_full_assoc_transition.cpp	(revision 136)
@@ -0,0 +1,239 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_front_end {
+namespace front_end {
+namespace ifetch_unit {
+namespace ifetch_queue {
+
+
+#undef  FUNCTION
+#define FUNCTION "Ifetch_queue::function_full_assoc_transition"
+  void Ifetch_queue::function_full_assoc_transition (void)
+  {
+    log_begin(Ifetch_queue,FUNCTION);
+    log_function(Ifetch_queue,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET) == 0)
+      {
+	reg_PTR_READ  = 0;
+	reg_PTR_WRITE = 0;
+
+	for (uint32_t i=0; i<_param->_size_queue; i++)
+          {
+            _queue [i]->_state = IFETCH_QUEUE_STATE_EMPTY;
+            _queue [i]->_address                     = 0; // not necessary
+            _queue [i]->_inst_ifetch_ptr             = 0; // not necessary
+            _queue [i]->_branch_state                = 0; // not necessary
+            _queue [i]->_branch_update_prediction_id = 0; // not necessary
+            _queue [i]->_exception                   = 0; // not necessary
+
+	    for (uint32_t j=0; j<_param->_nb_instruction; j++)
+              {
+            _queue [i]->_instruction             [j] = 0; // not necessary
+            _queue [i]->_instruction_enable      [j] = 0; // not necessary
+              }
+          }
+      }
+    else
+      {
+	// ==========================================================
+	// =====[ ADDRESS ]==========================================
+	// ==========================================================
+	if (PORT_READ(in_ADDRESS_VAL) and internal_ADDRESS_ACK)
+	  {
+	    log_printf(TRACE,Ifetch_queue,FUNCTION,"  * ADDRESS : Transaction");
+	    log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_WRITE : %d",reg_PTR_WRITE);
+            log_printf(TRACE,Ifetch_queue,FUNCTION,"    * ADDRESS       : 0x%x",PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS));
+
+	    // New slot in ifetch_queue is allocated
+	    
+	    _queue[reg_PTR_WRITE]->_state = IFETCH_QUEUE_STATE_WAIT_RSP;
+	      
+#ifdef STATISTICS
+	    if (usage_is_set(_usage,USE_STATISTICS))
+              (*_sum_transaction_address) ++;
+#endif
+
+	    for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	      {
+		Tcontrol_t enable = PORT_READ(in_ADDRESS_INSTRUCTION_ENABLE [i]);
+#ifdef STATISTICS
+                if (usage_is_set(_usage,USE_STATISTICS))
+                  (*_sum_inst_enable) += enable;
+#endif
+		_queue[reg_PTR_WRITE]->_instruction_enable [i]      = enable;
+	      }
+
+	    _queue[reg_PTR_WRITE]->_address                     = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS);
+	    _queue[reg_PTR_WRITE]->_inst_ifetch_ptr             = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR            ):0;
+	    _queue[reg_PTR_WRITE]->_branch_state                = PORT_READ(in_ADDRESS_BRANCH_STATE);
+	    _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_depth)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0;
+	    
+	    reg_PTR_WRITE = (reg_PTR_WRITE+1)%_param->_size_queue;
+	  }
+
+	// ==========================================================
+	// =====[ DECOD ]============================================
+	// ==========================================================
+	bool have_instruction_decod  = false;
+	bool have_instruction_enable = false;
+	uint32_t last_ptr = reg_PTR_READ;
+
+	for (uint32_t i=0; i<_param->_nb_instruction; ++i)
+	  {
+	    if (internal_DECOD_VAL [i] and PORT_READ(in_DECOD_ACK[i]))
+	      {
+                log_printf(TRACE,Ifetch_queue,FUNCTION,"  * DECOD [%d] : Transaction",i);
+
+		uint32_t ptr  = internal_DECOD_PTR [i];
+		uint32_t slot = internal_DECOD_SLOT[i];
+
+		have_instruction_decod = true;
+		last_ptr               = ptr;
+
+		_queue[ptr]->_instruction_enable [slot] = false;
+	      }
+	    have_instruction_enable |= _queue[reg_PTR_READ]->_instruction_enable [i];
+	  }
+
+	// Test if all is decoded
+	if (have_instruction_decod)
+	  {
+	    // Invalid all ptr
+	    while (reg_PTR_READ != last_ptr)
+	      {
+#ifdef DEBUG_TEST
+		bool have_instruction_enable = false;
+		for (uint32_t i=0; i<_param->_nb_instruction; ++i)
+		  have_instruction_enable |= _queue[reg_PTR_READ]->_instruction_enable [i];
+		
+		if (have_instruction_enable)
+		  throw ERRORMORPHEO(FUNCTION,toString("Can't free : Ifetch_queue[%d] content an valid instruction.\n",reg_PTR_READ));
+#endif
+		
+		_queue[reg_PTR_READ]->_state = IFETCH_QUEUE_STATE_EMPTY;
+		reg_PTR_READ = (reg_PTR_READ+1)%_param->_size_queue;
+	      }
+	    
+	    // For last ptr, test if all instruction is disable
+	    bool have_instruction_enable = false;
+	    for (uint32_t i=0; i<_param->_nb_instruction; ++i)
+	      have_instruction_enable |= _queue[reg_PTR_READ]->_instruction_enable [i];
+	    
+	    if (not have_instruction_enable)
+	      {
+		_queue[reg_PTR_READ]->_state = IFETCH_QUEUE_STATE_EMPTY;
+		reg_PTR_READ = (reg_PTR_READ+1)%_param->_size_queue;
+	      }
+	  }
+	  
+	// ==========================================================
+	// =====[ ICACHE_RSP ]=======================================
+	// ==========================================================
+	if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK)
+	  {
+	    log_printf(TRACE,Ifetch_queue,FUNCTION,"  * ICACHE_RSP : Transaction");
+
+	    Tpacket_t ptr = (_param->_have_port_ifetch_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0;
+	    
+	    for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	      _queue[ptr]->_instruction [i]      = PORT_READ(in_ICACHE_RSP_INSTRUCTION [i]);
+	    
+	    switch (PORT_READ(in_ICACHE_RSP_ERROR))
+	      {
+	      case ICACHE_ERROR_NONE      : _queue[ptr]->_exception = EXCEPTION_IFETCH_NONE     ; break;
+	      case ICACHE_ERROR_BUS_ERROR : _queue[ptr]->_exception = EXCEPTION_IFETCH_BUS_ERROR; break;
+	      default : throw ERRORMORPHEO(FUNCTION,"icache_rsp_error : unknow value.");
+	      }
+
+	    switch (_queue[ptr]->_state)
+	      {
+	      case IFETCH_QUEUE_STATE_WAIT_RSP       : _queue[ptr]->_state = IFETCH_QUEUE_STATE_HAVE_RSP; break;
+	      case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_EMPTY   ; break;
+	      default : throw ERRORMORPHEO(FUNCTION,"icache_rsp : invalid ifetch_queue state.");
+	      }
+	  }
+
+	// ==========================================================
+	// =====[ EVENT_RESET ]======================================
+	// ==========================================================
+	if (PORT_READ(in_EVENT_RESET_VAL) and internal_EVENT_RESET_ACK)
+	  {
+	    log_printf(TRACE,Ifetch_queue,FUNCTION,"  * EVENT_RESET : Transaction");
+
+	    // Scan all entry of queue and test the status
+	    for (uint32_t i=0; i<_param->_size_queue; i++)
+	      switch (_queue[i]->_state)
+	      {
+	      case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP :                                                        break;
+	      case IFETCH_QUEUE_STATE_WAIT_RSP       : _queue[i]->_state = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP; break;
+	      default                                : _queue[i]->_state = IFETCH_QUEUE_STATE_EMPTY         ; break;
+	      }
+
+	    // all entry is empty (or wait respons to flush)
+	    // reset ptr
+	    //   1) reg_PTR_READ = reg_PTR_WRITE =  = 0
+	    //   2) reg_PTR_READ = reg_PTR_WRITE
+	    // In method 1), the probalitie than the entry pointed by reg_PTR_WRITE is a slot with state "error_wait_rsp" is more importate that the method 2)
+	    reg_PTR_READ = reg_PTR_WRITE;
+	  }
+
+#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE)
+	log_printf(TRACE,Ifetch_queue,FUNCTION,"  * Dump ifetch_queue");
+	log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_WRITE : %d",reg_PTR_WRITE);
+	log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_READ  : %d",reg_PTR_READ );
+	for (uint32_t i=0; i<_param->_size_queue; i++)
+	  {
+            log_printf(TRACE,Ifetch_queue,FUNCTION,"    * [%d] 0x%.8x (0x%.8x) %d - %d %d %d - %s",
+                       i, 
+                       _queue [i]->_address,
+                       _queue [i]->_address<<2,
+                       _queue [i]->_inst_ifetch_ptr,
+                       _queue [i]->_branch_state,
+                       _queue [i]->_branch_update_prediction_id,
+                       _queue [i]->_exception,
+                       toString(_queue [i]->_state).c_str()
+                       );
+	    
+	    for (uint32_t j=0; j<_param->_nb_instruction; j++)
+	      log_printf(TRACE,Ifetch_queue,FUNCTION,"      * %d 0x%.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]);
+	  }
+#endif
+
+#ifdef STATISTICS
+        if (usage_is_set(_usage,USE_STATISTICS))
+          for (uint32_t i=0; i<_param->_size_queue; i++)
+            switch (_queue[i]->_state)
+              {
+              case IFETCH_QUEUE_STATE_EMPTY          : break;
+              case IFETCH_QUEUE_STATE_WAIT_RSP       : (*_sum_use_queue_wait_rsp      ) ++; break;
+              case IFETCH_QUEUE_STATE_HAVE_RSP       : (*_sum_use_queue_have_rsp      ) ++; break;
+              case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break;
+              default : break;
+              }
+#endif
+      }
+
+    log_end(Ifetch_queue,FUNCTION);
+  };
+
+}; // end namespace ifetch_queue
+}; // end namespace ifetch_unit
+}; // end namespace front_end
+}; // end namespace multi_front_end
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_no_assoc_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_no_assoc_genMoore.cpp	(revision 136)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_no_assoc_genMoore.cpp	(revision 136)
@@ -0,0 +1,99 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_front_end {
+namespace front_end {
+namespace ifetch_unit {
+namespace ifetch_queue {
+
+#undef  FUNCTION
+#define FUNCTION "Ifetch_queue::function_no_assoc_genMoore"
+  void Ifetch_queue::function_no_assoc_genMoore (void)
+  {
+    log_begin(Ifetch_queue,FUNCTION);
+    log_function(Ifetch_queue,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET))
+      {
+    // ==========================================================
+    // =====[ ADDRESS ]==========================================
+    // ==========================================================
+    {
+      internal_ADDRESS_ACK = (_queue[reg_PTR_WRITE]->_state == IFETCH_QUEUE_STATE_EMPTY);
+ 
+      log_printf(TRACE,Ifetch_queue,FUNCTION,"  * ADDRESS_ACK : %d",internal_ADDRESS_ACK);
+     
+      if (_param->_have_port_ifetch_queue_ptr)
+      PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE);
+    }
+
+    // ==========================================================
+    // =====[ DECOD ]============================================
+    // ==========================================================
+    {
+      bool ack = (_queue[reg_PTR_READ]->_state == IFETCH_QUEUE_STATE_HAVE_RSP);
+
+      Tgeneral_address_t address                       = _queue[reg_PTR_READ]->_address;
+      Tinst_ifetch_ptr_t inst_ifetch_ptr               = _queue[reg_PTR_READ]->_inst_ifetch_ptr;
+      Tbranch_state_t    branch_state                  = _queue[reg_PTR_READ]->_branch_state;
+      Tprediction_ptr_t  branch_update_prediction_id   = _queue[reg_PTR_READ]->_branch_update_prediction_id;
+      Texception_t       exception                     = _queue[reg_PTR_READ]->_exception;
+      
+      for (uint32_t i=0; i<_param->_nb_instruction; i++)
+        {
+          internal_DECOD_VAL [i] = ack and _queue[reg_PTR_READ]->_instruction_enable [i];
+
+          log_printf(TRACE,Ifetch_queue,FUNCTION,"  * DECOD_VAL [%d] : %d",i,internal_DECOD_VAL [i]);
+
+          PORT_WRITE(out_DECOD_INSTRUCTION                [i],_queue[reg_PTR_READ]->_instruction [i]);
+	  PORT_WRITE(out_DECOD_ADDRESS                    [i],address+i);
+	  if (inst_ifetch_ptr == i)
+	    {
+	  PORT_WRITE(out_DECOD_BRANCH_STATE               [i],branch_state);
+	    }
+	  else
+	    {
+	  PORT_WRITE(out_DECOD_BRANCH_STATE               [i], BRANCH_STATE_NONE);
+	    }
+	  if (_param->_have_port_depth)
+	  PORT_WRITE(out_DECOD_BRANCH_UPDATE_PREDICTION_ID[i],branch_update_prediction_id);
+	  PORT_WRITE(out_DECOD_EXCEPTION                  [i],exception); // all is same
+        }
+      
+    }
+      }
+    else
+      {
+        // Reset
+        internal_ADDRESS_ACK = 0;
+        for (uint32_t i=0; i<_param->_nb_instruction; i++)
+          internal_DECOD_VAL [i] = 0;
+        
+      }
+
+    // Write Output
+    PORT_WRITE(out_ADDRESS_ACK  , internal_ADDRESS_ACK);
+    for (uint32_t i=0; i<_param->_nb_instruction; i++)
+    PORT_WRITE(out_DECOD_VAL [i], internal_DECOD_VAL [i]);
+
+    log_end(Ifetch_queue,FUNCTION);
+  };
+
+}; // end namespace ifetch_queue
+}; // end namespace ifetch_unit
+}; // end namespace front_end
+}; // end namespace multi_front_end
+}; // end namespace core
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_no_assoc_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_no_assoc_transition.cpp	(revision 136)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_no_assoc_transition.cpp	(revision 136)
@@ -0,0 +1,209 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_front_end {
+namespace front_end {
+namespace ifetch_unit {
+namespace ifetch_queue {
+
+
+#undef  FUNCTION
+#define FUNCTION "Ifetch_queue::function_no_assoc_transition"
+  void Ifetch_queue::function_no_assoc_transition (void)
+  {
+    log_begin(Ifetch_queue,FUNCTION);
+    log_function(Ifetch_queue,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET) == 0)
+      {
+	reg_PTR_READ  = 0;
+	reg_PTR_WRITE = 0;
+
+	for (uint32_t i=0; i<_param->_size_queue; i++)
+          {
+            _queue [i]->_state = IFETCH_QUEUE_STATE_EMPTY;
+            _queue [i]->_address                     = 0; // not necessary
+            _queue [i]->_inst_ifetch_ptr             = 0; // not necessary
+            _queue [i]->_branch_state                = 0; // not necessary
+            _queue [i]->_branch_update_prediction_id = 0; // not necessary
+            _queue [i]->_exception                   = 0; // not necessary
+
+	    for (uint32_t j=0; j<_param->_nb_instruction; j++)
+              {
+            _queue [i]->_instruction             [j] = 0; // not necessary
+            _queue [i]->_instruction_enable      [j] = 0; // not necessary
+              }
+          }
+      }
+    else
+      {
+	// ==========================================================
+	// =====[ ADDRESS ]==========================================
+	// ==========================================================
+	if (PORT_READ(in_ADDRESS_VAL) and internal_ADDRESS_ACK)
+	  {
+	    log_printf(TRACE,Ifetch_queue,FUNCTION,"  * ADDRESS : Transaction");
+	    log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_WRITE : %d",reg_PTR_WRITE);
+            log_printf(TRACE,Ifetch_queue,FUNCTION,"    * ADDRESS       : 0x%x",PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS));
+
+	    // New slot in ifetch_queue is allocated
+	    
+	    _queue[reg_PTR_WRITE]->_state = IFETCH_QUEUE_STATE_WAIT_RSP;
+	      
+#ifdef STATISTICS
+	    if (usage_is_set(_usage,USE_STATISTICS))
+              (*_sum_transaction_address) ++;
+#endif
+
+	    for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	      {
+		Tcontrol_t enable = PORT_READ(in_ADDRESS_INSTRUCTION_ENABLE [i]);
+#ifdef STATISTICS
+                if (usage_is_set(_usage,USE_STATISTICS))
+                  (*_sum_inst_enable) += enable;
+#endif
+		_queue[reg_PTR_WRITE]->_instruction_enable [i]      = enable;
+	      }
+
+	    _queue[reg_PTR_WRITE]->_address                     = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS);
+	    _queue[reg_PTR_WRITE]->_inst_ifetch_ptr             = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR            ):0;
+	    _queue[reg_PTR_WRITE]->_branch_state                = PORT_READ(in_ADDRESS_BRANCH_STATE);
+	    _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_depth)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0;
+	    
+	    reg_PTR_WRITE = (reg_PTR_WRITE+1)%_param->_size_queue;
+	  }
+
+	// ==========================================================
+	// =====[ DECOD ]============================================
+	// ==========================================================
+	bool have_instruction_decod  = false;
+	bool have_instruction_enable = false;
+	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	  {
+	    if (internal_DECOD_VAL [i] and PORT_READ(in_DECOD_ACK[i]))
+	      {
+                log_printf(TRACE,Ifetch_queue,FUNCTION,"  * DECOD [%d] : Transaction",i);
+
+		have_instruction_decod = true;
+		_queue[reg_PTR_READ]->_instruction_enable [i] = false;
+	      }
+	    have_instruction_enable |= _queue[reg_PTR_READ]->_instruction_enable [i];
+	  }
+
+	// Test if all is decoded
+	if (have_instruction_decod and not have_instruction_enable)
+	  {
+	    // all is decod
+	    _queue[reg_PTR_READ]->_state = IFETCH_QUEUE_STATE_EMPTY;
+	    reg_PTR_READ = (reg_PTR_READ+1)%_param->_size_queue;
+	  }
+	  
+	// ==========================================================
+	// =====[ ICACHE_RSP ]=======================================
+	// ==========================================================
+	if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK)
+	  {
+	    log_printf(TRACE,Ifetch_queue,FUNCTION,"  * ICACHE_RSP : Transaction");
+
+	    Tpacket_t ptr = (_param->_have_port_ifetch_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0;
+	    
+	    for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	      _queue[ptr]->_instruction [i]      = PORT_READ(in_ICACHE_RSP_INSTRUCTION [i]);
+	    
+	    switch (PORT_READ(in_ICACHE_RSP_ERROR))
+	      {
+	      case ICACHE_ERROR_NONE      : _queue[ptr]->_exception = EXCEPTION_IFETCH_NONE     ; break;
+	      case ICACHE_ERROR_BUS_ERROR : _queue[ptr]->_exception = EXCEPTION_IFETCH_BUS_ERROR; break;
+	      default : ERRORMORPHEO(FUNCTION,"icache_rsp_error : unknow value.");
+	      }
+
+	    switch (_queue[ptr]->_state)
+	      {
+	      case IFETCH_QUEUE_STATE_WAIT_RSP       : _queue[ptr]->_state = IFETCH_QUEUE_STATE_HAVE_RSP; break;
+	      case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_EMPTY   ; break;
+	      default : ERRORMORPHEO(FUNCTION,"icache_rsp : invalid ifetch_queue state.");
+	      }
+	  }
+
+	// ==========================================================
+	// =====[ EVENT_RESET ]======================================
+	// ==========================================================
+	if (PORT_READ(in_EVENT_RESET_VAL) and internal_EVENT_RESET_ACK)
+	  {
+	    log_printf(TRACE,Ifetch_queue,FUNCTION,"  * EVENT_RESET : Transaction");
+
+	    // Scan all entry of queue and test the status
+	    for (uint32_t i=0; i<_param->_size_queue; i++)
+	      switch (_queue[i]->_state)
+	      {
+	      case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP :                                                        break;
+	      case IFETCH_QUEUE_STATE_WAIT_RSP       : _queue[i]->_state = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP; break;
+	      default                                : _queue[i]->_state = IFETCH_QUEUE_STATE_EMPTY         ; break;
+	      }
+
+	    // all entry is empty (or wait respons to flush)
+	    // reset ptr
+	    //   1) reg_PTR_READ = reg_PTR_WRITE =  = 0
+	    //   2) reg_PTR_READ = reg_PTR_WRITE
+	    // In method 1), the probalitie than the entry pointed by reg_PTR_WRITE is a slot with state "error_wait_rsp" is more importate that the method 2)
+	    reg_PTR_READ = reg_PTR_WRITE;
+	  }
+
+#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE)
+	log_printf(TRACE,Ifetch_queue,FUNCTION,"  * Dump ifetch_queue");
+	log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_WRITE : %d",reg_PTR_WRITE);
+	log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_READ  : %d",reg_PTR_READ );
+	for (uint32_t i=0; i<_param->_size_queue; i++)
+	  {
+            log_printf(TRACE,Ifetch_queue,FUNCTION,"    * [%d] 0x%.8x (0x%.8x) %d - %d %d %d - %s",
+                       i, 
+                       _queue [i]->_address,
+                       _queue [i]->_address<<2,
+                       _queue [i]->_inst_ifetch_ptr,
+                       _queue [i]->_branch_state,
+                       _queue [i]->_branch_update_prediction_id,
+                       _queue [i]->_exception,
+                       toString(_queue [i]->_state).c_str()
+                       );
+	    
+	    for (uint32_t j=0; j<_param->_nb_instruction; j++)
+	      log_printf(TRACE,Ifetch_queue,FUNCTION,"      * %d 0x%.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]);
+	  }
+#endif
+
+#ifdef STATISTICS
+        if (usage_is_set(_usage,USE_STATISTICS))
+          for (uint32_t i=0; i<_param->_size_queue; i++)
+            switch (_queue[i]->_state)
+              {
+              case IFETCH_QUEUE_STATE_EMPTY          : break;
+              case IFETCH_QUEUE_STATE_WAIT_RSP       : (*_sum_use_queue_wait_rsp      ) ++; break;
+              case IFETCH_QUEUE_STATE_HAVE_RSP       : (*_sum_use_queue_have_rsp      ) ++; break;
+              case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break;
+              default : break;
+              }
+#endif
+      }
+
+    log_end(Ifetch_queue,FUNCTION);
+  };
+
+}; // end namespace ifetch_queue
+}; // end namespace ifetch_unit
+}; // end namespace front_end
+}; // end namespace multi_front_end
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_genMoore.cpp	(revision 135)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_genMoore.cpp	(revision 136)
@@ -24,55 +24,5 @@
     log_function(Ifetch_queue,FUNCTION,_name.c_str());
 
-    if (PORT_READ(in_NRESET))
-      {
-    // ==========================================================
-    // =====[ ADDRESS ]==========================================
-    // ==========================================================
-    {
-      internal_ADDRESS_ACK = (_queue[reg_PTR_WRITE]->_state == IFETCH_QUEUE_STATE_EMPTY);
- 
-      log_printf(TRACE,Ifetch_queue,FUNCTION,"  * ADDRESS_ACK : %d",internal_ADDRESS_ACK);
-     
-      if (_param->_have_port_ifetch_queue_ptr)
-      PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE);
-    }
-
-    // ==========================================================
-    // =====[ DECOD ]============================================
-    // ==========================================================
-    {
-      bool ack = (_queue[reg_PTR_READ]->_state == IFETCH_QUEUE_STATE_HAVE_RSP);
-      
-      for (uint32_t i=0; i<_param->_nb_instruction; i++)
-        {
-          internal_DECOD_VAL [i] = ack and _queue[reg_PTR_READ]->_instruction_enable [i];
-
-          log_printf(TRACE,Ifetch_queue,FUNCTION,"  * DECOD_VAL [%d] : %d",i,internal_DECOD_VAL [i]);
-
-          PORT_WRITE(out_DECOD_INSTRUCTION [i],         _queue[reg_PTR_READ]->_instruction        [i]);
-        }
-      
-      PORT_WRITE(out_DECOD_ADDRESS                    , _queue[reg_PTR_READ]->_address                    );
-      if (_param->_have_port_inst_ifetch_ptr)
-      PORT_WRITE(out_DECOD_INST_IFETCH_PTR            , _queue[reg_PTR_READ]->_inst_ifetch_ptr            );
-      PORT_WRITE(out_DECOD_BRANCH_STATE               , _queue[reg_PTR_READ]->_branch_state               );
-      if (_param->_have_port_depth)
-      PORT_WRITE(out_DECOD_BRANCH_UPDATE_PREDICTION_ID, _queue[reg_PTR_READ]->_branch_update_prediction_id);
-      PORT_WRITE(out_DECOD_EXCEPTION                  , _queue[reg_PTR_READ]->_exception                  );
-    }
-      }
-    else
-      {
-        // Reset
-        internal_ADDRESS_ACK = 0;
-        for (uint32_t i=0; i<_param->_nb_instruction; i++)
-          internal_DECOD_VAL [i] = 0;
-        
-      }
-
-    // Write Output
-    PORT_WRITE(out_ADDRESS_ACK  , internal_ADDRESS_ACK);
-    for (uint32_t i=0; i<_param->_nb_instruction; i++)
-    PORT_WRITE(out_DECOD_VAL [i], internal_DECOD_VAL [i]);
+    (this->*function_genMoore) ();
 
     log_end(Ifetch_queue,FUNCTION);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp	(revision 135)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp	(revision 136)
@@ -25,174 +25,5 @@
     log_function(Ifetch_queue,FUNCTION,_name.c_str());
 
-    if (PORT_READ(in_NRESET) == 0)
-      {
-	reg_PTR_READ  = 0;
-	reg_PTR_WRITE = 0;
-
-	for (uint32_t i=0; i<_param->_size_queue; i++)
-          {
-            _queue [i]->_state = IFETCH_QUEUE_STATE_EMPTY;
-            _queue [i]->_address                     = 0; // not necessary
-            _queue [i]->_inst_ifetch_ptr             = 0; // not necessary
-            _queue [i]->_branch_state                = 0; // not necessary
-            _queue [i]->_branch_update_prediction_id = 0; // not necessary
-            _queue [i]->_exception                   = 0; // not necessary
-
-	    for (uint32_t j=0; j<_param->_nb_instruction; j++)
-              {
-            _queue [i]->_instruction             [j] = 0; // not necessary
-            _queue [i]->_instruction_enable      [j] = 0; // not necessary
-              }
-          }
-      }
-    else
-      {
-	// ==========================================================
-	// =====[ ADDRESS ]==========================================
-	// ==========================================================
-	if (PORT_READ(in_ADDRESS_VAL) and internal_ADDRESS_ACK)
-	  {
-	    log_printf(TRACE,Ifetch_queue,FUNCTION,"  * ADDRESS : Transaction");
-	    log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_WRITE : %d",reg_PTR_WRITE);
-            log_printf(TRACE,Ifetch_queue,FUNCTION,"    * ADDRESS       : 0x%x",PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS));
-
-	    // New slot in ifetch_queue is allocated
-	    
-	    _queue[reg_PTR_WRITE]->_state = IFETCH_QUEUE_STATE_WAIT_RSP;
-	      
-#ifdef STATISTICS
-	    if (usage_is_set(_usage,USE_STATISTICS))
-              (*_sum_transaction_address) ++;
-#endif
-
-	    for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	      {
-		Tcontrol_t enable = PORT_READ(in_ADDRESS_INSTRUCTION_ENABLE [i]);
-#ifdef STATISTICS
-                if (usage_is_set(_usage,USE_STATISTICS))
-                  (*_sum_inst_enable) += enable;
-#endif
-		_queue[reg_PTR_WRITE]->_instruction_enable [i]      = enable;
-	      }
-
-	    _queue[reg_PTR_WRITE]->_address                     = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS);
-	    _queue[reg_PTR_WRITE]->_inst_ifetch_ptr             = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR            ):0;
-	    _queue[reg_PTR_WRITE]->_branch_state                = PORT_READ(in_ADDRESS_BRANCH_STATE);
-	    _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_depth)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0;
-	    
-	    reg_PTR_WRITE = (reg_PTR_WRITE+1)%_param->_size_queue;
-	  }
-
-	// ==========================================================
-	// =====[ DECOD ]============================================
-	// ==========================================================
-	bool have_instruction_decod  = false;
-	bool have_instruction_enable = false;
-	for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	  {
-	    if (internal_DECOD_VAL [i] and PORT_READ(in_DECOD_ACK[i]))
-	      {
-                log_printf(TRACE,Ifetch_queue,FUNCTION,"  * DECOD [%d] : Transaction",i);
-
-		have_instruction_decod = true;
-		_queue[reg_PTR_READ]->_instruction_enable [i] = false;
-	      }
-	    have_instruction_enable |= _queue[reg_PTR_READ]->_instruction_enable [i];
-	  }
-
-	// Test if all is decoded
-	if (have_instruction_decod and not have_instruction_enable)
-	  {
-	    // all is decod
-	    _queue[reg_PTR_READ]->_state = IFETCH_QUEUE_STATE_EMPTY;
-	    reg_PTR_READ = (reg_PTR_READ+1)%_param->_size_queue;
-	  }
-	  
-	// ==========================================================
-	// =====[ ICACHE_RSP ]=======================================
-	// ==========================================================
-	if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK)
-	  {
-	    log_printf(TRACE,Ifetch_queue,FUNCTION,"  * ICACHE_RSP : Transaction");
-
-	    Tpacket_t ptr = (_param->_have_port_ifetch_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0;
-	    
-	    for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	      _queue[ptr]->_instruction [i]      = PORT_READ(in_ICACHE_RSP_INSTRUCTION [i]);
-	    
-	    switch (PORT_READ(in_ICACHE_RSP_ERROR))
-	      {
-	      case ICACHE_ERROR_NONE      : _queue[ptr]->_exception = EXCEPTION_IFETCH_NONE     ; break;
-	      case ICACHE_ERROR_BUS_ERROR : _queue[ptr]->_exception = EXCEPTION_IFETCH_BUS_ERROR; break;
-	      default : ERRORMORPHEO(FUNCTION,"icache_rsp_error : unknow value.");
-	      }
-
-	    switch (_queue[ptr]->_state)
-	      {
-	      case IFETCH_QUEUE_STATE_WAIT_RSP       : _queue[ptr]->_state = IFETCH_QUEUE_STATE_HAVE_RSP; break;
-	      case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_EMPTY   ; break;
-	      default : ERRORMORPHEO(FUNCTION,"icache_rsp : invalid ifetch_queue state.");
-	      }
-	  }
-
-	// ==========================================================
-	// =====[ EVENT_RESET ]======================================
-	// ==========================================================
-	if (PORT_READ(in_EVENT_RESET_VAL) and internal_EVENT_RESET_ACK)
-	  {
-	    log_printf(TRACE,Ifetch_queue,FUNCTION,"  * EVENT_RESET : Transaction");
-
-	    // Scan all entry of queue and test the status
-	    for (uint32_t i=0; i<_param->_size_queue; i++)
-	      switch (_queue[i]->_state)
-	      {
-	      case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP :                                                        break;
-	      case IFETCH_QUEUE_STATE_WAIT_RSP       : _queue[i]->_state = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP; break;
-	      default                                : _queue[i]->_state = IFETCH_QUEUE_STATE_EMPTY         ; break;
-	      }
-
-	    // all entry is empty (or wait respons to flush)
-	    // reset ptr
-	    //   1) reg_PTR_READ = reg_PTR_WRITE =  = 0
-	    //   2) reg_PTR_READ = reg_PTR_WRITE
-	    // In method 1), the probalitie than the entry pointed by reg_PTR_WRITE is a slot with state "error_wait_rsp" is more importate that the method 2)
-	    reg_PTR_READ = reg_PTR_WRITE;
-	  }
-
-#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE)
-	log_printf(TRACE,Ifetch_queue,FUNCTION,"  * Dump ifetch_queue");
-	log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_WRITE : %d",reg_PTR_WRITE);
-	log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_READ  : %d",reg_PTR_READ );
-	for (uint32_t i=0; i<_param->_size_queue; i++)
-	  {
-            log_printf(TRACE,Ifetch_queue,FUNCTION,"    * [%d] 0x%.8x (0x%.8x) %d - %d %d %d - %s",
-                       i, 
-                       _queue [i]->_address,
-                       _queue [i]->_address<<2,
-                       _queue [i]->_inst_ifetch_ptr,
-                       _queue [i]->_branch_state,
-                       _queue [i]->_branch_update_prediction_id,
-                       _queue [i]->_exception,
-                       toString(_queue [i]->_state).c_str()
-                       );
-	    
-	    for (uint32_t j=0; j<_param->_nb_instruction; j++)
-	      log_printf(TRACE,Ifetch_queue,FUNCTION,"      * %d 0x%.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]);
-	  }
-#endif
-
-#ifdef STATISTICS
-        if (usage_is_set(_usage,USE_STATISTICS))
-          for (uint32_t i=0; i<_param->_size_queue; i++)
-            switch (_queue[i]->_state)
-              {
-              case IFETCH_QUEUE_STATE_EMPTY          : break;
-              case IFETCH_QUEUE_STATE_WAIT_RSP       : (*_sum_use_queue_wait_rsp      ) ++; break;
-              case IFETCH_QUEUE_STATE_HAVE_RSP       : (*_sum_use_queue_have_rsp      ) ++; break;
-              case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break;
-              default : break;
-              }
-#endif
-      }
+    (this->*function_transition) ();
     
 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters.cpp	(revision 135)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters.cpp	(revision 136)
@@ -19,9 +19,10 @@
 #undef  FUNCTION
 #define FUNCTION "Ifetch_queue::Parameters"
-  Parameters::Parameters (uint32_t size_queue                   ,
-			  uint32_t nb_instruction               ,
-			  uint32_t size_branch_update_prediction,
-			  uint32_t size_general_data            ,
-                          bool     is_toplevel)
+  Parameters::Parameters (uint32_t               size_queue                   ,
+			  Tifetch_queue_scheme_t queue_scheme                 ,
+			  uint32_t               nb_instruction               ,
+			  uint32_t               size_branch_update_prediction,
+			  uint32_t               size_general_data            ,
+			  bool                   is_toplevel)
   {
     log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
@@ -29,4 +30,5 @@
     _nb_instruction_in_queue               = size_queue                   ;
     _size_queue                            = size_queue/nb_instruction    ;
+    _queue_scheme                          = queue_scheme                 ;
     _nb_instruction                        = nb_instruction               ;
 //  _size_branch_update_prediction         = size_branch_update_prediction;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_msg_error.cpp	(revision 135)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_msg_error.cpp	(revision 136)
@@ -29,4 +29,18 @@
       test.error(_("Size of ifetch queue must be a multiple of nb_instruction.\n"));
 
+    switch (_queue_scheme)
+      {
+      case IFETCH_QUEUE_SCHEME_NO_ASSOC :
+      case IFETCH_QUEUE_SCHEME_FULL_ASSOC :
+        {
+          break;
+        }
+      default :
+	{
+ 	  test.error(toString(_("Ifetch queue scheme '%s' is not supported. Please wait a next revision.\n"),toString(_queue_scheme).c_str()));
+	  break;
+	}
+      }
+
     if (_size_queue == 1)
       test.warning(_("To best perfomance, size_queue must be > 1.\n"));
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_print.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_print.cpp	(revision 135)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_print.cpp	(revision 136)
@@ -28,4 +28,5 @@
     xml.balise_open("ifetch_queue");
     xml.singleton_begin("size_queue                   "); xml.attribut("value",toString(_size_queue                   )); xml.singleton_end();
+    xml.singleton_begin("queue_scheme                 "); xml.attribut("value",toString(_queue_scheme                 )); xml.singleton_end();
     xml.singleton_begin("nb_instruction               "); xml.attribut("value",toString(_nb_instruction               )); xml.singleton_end();
 //  xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end();
