Changeset 138 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit
- Timestamp:
- May 12, 2010, 7:34:01 PM (14 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit
- Files:
-
- 8 edited
- 5 moved
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
r136 r138 181 181 // Registers 182 182 public : Tlsq_ptr_t * reg_STORE_QUEUE_NB_CHECK ;//[size_store_queue] 183 //public : Tcontrol_t * reg_STORE_QUEUE_INVALID ;//[size_store_queue] 183 184 public : Tlsq_ptr_t reg_STORE_QUEUE_PTR_READ ; 184 185 //public : Tlsq_ptr_t reg_LOAD_QUEUE_PTR_READ ; … … 236 237 public : void genMealy_retire (void); 237 238 238 public : void function_speculative_load_ commit_transition (void);239 public : void function_speculative_load_ commit_genMoore (void);240 public : void function_speculative_load_ commit_genMealy_dcache (void);241 public : void function_speculative_load_ commit_genMealy_insert (void);242 public : void function_speculative_load_ commit_genMealy_retire (void);239 public : void function_speculative_load_access_transition (void); 240 public : void function_speculative_load_access_genMoore (void); 241 public : void function_speculative_load_access_genMealy_dcache (void); 242 public : void function_speculative_load_access_genMealy_insert (void); 243 public : void function_speculative_load_access_genMealy_retire (void); 243 244 #endif 244 245 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h
r124 r138 27 27 { 28 28 //-----[ fields ]------------------------------------------------------------ 29 public : uint32_t _size_store_queue ; 30 public : uint32_t _size_load_queue ; 31 public : uint32_t _size_speculative_access_queue; 32 public : uint32_t _nb_port_check ; 33 public : Tspeculative_load_t _speculative_load ; 34 public : uint32_t _nb_bypass_memory ; 35 public : uint32_t _nb_cache_port ; 36 public : uint32_t _nb_inst_memory ; 37 public : uint32_t _nb_context ; 38 public : uint32_t _nb_front_end ; 39 public : uint32_t _nb_ooo_engine ; 40 public : uint32_t _nb_packet ; 41 //public : uint32_t _size_general_data ; 42 //public : uint32_t _size_special_data ; 43 public : uint32_t _nb_general_register ; 44 public : uint32_t _nb_special_register ; 45 public : uint32_t _nb_thread ; 46 public : bool * _num_thread_valid ; //[nb_thread] 29 public : uint32_t _size_store_queue ; 30 public : uint32_t _size_load_queue ; 31 public : uint32_t _size_speculative_access_queue ; 32 public : uint32_t _nb_store_queue_bank ; 33 public : uint32_t _nb_load_queue_bank ; 34 public : uint32_t _nb_port_check ; 35 public : Tspeculative_load_t _speculative_load ; 36 public : Tpredictor_t _speculative_commit_predictor_scheme; 37 public : uint32_t * _lsu_pht_size_counter ;//[1] 38 public : uint32_t * _lsu_pht_nb_counter ;//[1] 39 public : uint32_t _nb_bypass_memory ; 40 public : uint32_t _nb_cache_port ; 41 public : uint32_t _nb_inst_memory ; 42 public : uint32_t _nb_context ; 43 public : uint32_t _nb_front_end ; 44 public : uint32_t _nb_ooo_engine ; 45 public : uint32_t _nb_packet ; 46 //public : uint32_t _size_general_data ; 47 //public : uint32_t _size_special_data ; 48 public : uint32_t _nb_general_register ; 49 public : uint32_t _nb_special_register ; 50 public : uint32_t _nb_thread ; 51 public : bool * _num_thread_valid ; //[nb_thread] 47 52 48 53 //public : uint32_t _size_address_store_queue ; … … 70 75 71 76 //-----[ methods ]----------------------------------------------------------- 72 public : Parameters (uint32_t size_store_queue , 73 uint32_t size_load_queue , 74 uint32_t size_speculative_access_queue, 75 uint32_t nb_port_check , 76 Tspeculative_load_t speculative_load , 77 uint32_t nb_bypass_memory , 78 uint32_t nb_cache_port , 79 uint32_t nb_inst_memory , 80 uint32_t nb_context , 81 uint32_t nb_front_end , 82 uint32_t nb_ooo_engine , 83 uint32_t nb_packet , 84 uint32_t size_general_data , 85 uint32_t size_special_data , 86 uint32_t nb_general_register , 87 uint32_t nb_special_register , 88 uint32_t nb_thread , 89 bool * num_thread_valid , //[nb_thread] 77 public : Parameters (uint32_t size_store_queue , 78 uint32_t size_load_queue , 79 uint32_t size_speculative_access_queue , 80 uint32_t nb_store_queue_bank , 81 uint32_t nb_load_queue_bank , 82 uint32_t nb_port_check , 83 Tspeculative_load_t speculative_load , 84 Tpredictor_t speculative_commit_predictor_scheme, 85 uint32_t * lsu_pht_size_counter ,//[1] 86 uint32_t * lsu_pht_nb_counter ,//[1] 87 uint32_t nb_bypass_memory , 88 uint32_t nb_cache_port , 89 uint32_t nb_inst_memory , 90 uint32_t nb_context , 91 uint32_t nb_front_end , 92 uint32_t nb_ooo_engine , 93 uint32_t nb_packet , 94 uint32_t size_general_data , 95 uint32_t size_special_data , 96 uint32_t nb_general_register , 97 uint32_t nb_special_register , 98 uint32_t nb_thread , 99 bool * num_thread_valid , //[nb_thread] 90 100 bool is_toplevel=false); 91 101 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h
r136 r138 35 35 NO_SPECULATIVE_LOAD //each load wait all previous store before the data cache access 36 36 ,SPECULATIVE_LOAD_ACCESS //each load wait all previous store before the commiting 37 37 //,SPECULATIVE_LOAD_COMMIT //each load commit the result before the end of dependence's check 38 38 //,SPECULATIVE_LOAD_BYPASS //each load bypass the result before the end of dependence's check 39 39 } Tspeculative_load_t; … … 184 184 public : Tgeneral_address_t _num_reg_rd ; 185 185 public : Texception_t _exception ; 186 public : Tcontrol_t _can_speculative_commit; 186 187 187 188 friend std::ostream & operator << (std::ostream& os, const Tload_queue_entry_t & x) … … 194 195 << " * exception : " << toString(x._exception) << std::endl 195 196 << " * check_hit, check_hit_byte : " << toString(x._check_hit) << " - " << toString(x._check_hit_byte) << std::endl 197 << " * can_speculative_commit : " << toString(x._can_speculative_commit) << std::endl 196 198 << std::hex 197 199 << " * address : " << toString(x._address)<< std::endl … … 217 219 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD : return "no_speculative_load" ; break; 218 220 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS : return "speculative_load_access"; break; 219 220 // 221 // case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT : return "speculative_load_commit"; break; 222 // case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS : return "speculative_load_bypass"; break; 221 223 default : return "" ; break; 222 224 } … … 225 227 template<> inline morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tspeculative_load_t fromString<morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tspeculative_load_t>(const std::string& x) 226 228 { 227 if ( 228 (x.compare("no_speculative_load")== 0))229 if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD ))) == 0) or 230 (x.compare(toString( morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD )) == 0)) 229 231 return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD; 230 if ( 231 (x.compare("speculative_load_access") == 0))232 if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS))) == 0) or 233 (x.compare(toString( morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS )) == 0)) 232 234 return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS; 233 if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT))) == 0) or234 (x.compare("speculative_load_commit") == 0))235 236 // if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS)))) or237 // (x.compare("speculative_load_bypass") == 0))238 // 235 // if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT))) == 0) or 236 // (x.compare(toString( morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT )) == 0)) 237 // return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT; 238 // if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS))) == 0) or 239 // (x.compare(toString( morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS )) == 0)) 240 // return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS; 239 241 240 242 throw (ErrorMorpheo ("<fromString> : Unknow string : \""+x+"\"")); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp
r132 r138 77 77 switch (_param->_speculative_load) 78 78 { 79 case SPECULATIVE_LOAD_ COMMIT:79 case SPECULATIVE_LOAD_ACCESS : 80 80 { 81 function_transition = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_ commit_transition ;82 function_genMoore = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_ commit_genMoore ;83 function_genMealy_dcache = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_ commit_genMealy_dcache;84 function_genMealy_insert = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_ commit_genMealy_insert;85 function_genMealy_retire = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_ commit_genMealy_retire;81 function_transition = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_transition ; 82 function_genMoore = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_genMoore ; 83 function_genMealy_dcache = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_genMealy_dcache; 84 function_genMealy_insert = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_genMealy_insert; 85 function_genMealy_retire = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_genMealy_retire; 86 86 break; 87 87 } 88 88 case NO_SPECULATIVE_LOAD : 89 case SPECULATIVE_LOAD_ACCESS:90 89 // case SPECULATIVE_LOAD_COMMIT : 90 //case SPECULATIVE_LOAD_BYPASS : 91 91 default : 92 92 { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
r136 r138 160 160 161 161 ALLOC1(reg_STORE_QUEUE_NB_CHECK ,Tlsq_ptr_t ,_param->_size_store_queue); 162 // ALLOC1(reg_STORE_QUEUE_INVALID ,Tcontrol_t ,_param->_size_store_queue); 162 163 163 164 // ALLOC1(internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ,Tlsq_ptr_t ,_param->_nb_cache_port); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
r136 r138 106 106 107 107 DELETE1(reg_STORE_QUEUE_NB_CHECK ,_param->_size_store_queue); 108 // DELETE1(reg_STORE_QUEUE_INVALID ,_param->_size_store_queue); 108 109 109 110 // DELETE1(internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ,_param->_nb_cache_port); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_dcache.cpp
r137 r138 21 21 22 22 #undef FUNCTION 23 #define FUNCTION "Load_store_unit::function_speculative_load_ commit_genMealy_dcache"24 void Load_store_unit::function_speculative_load_ commit_genMealy_dcache (void)23 #define FUNCTION "Load_store_unit::function_speculative_load_access_genMealy_dcache" 24 void Load_store_unit::function_speculative_load_access_genMealy_dcache (void) 25 25 { 26 26 log_begin(Load_store_unit,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_insert.cpp
r137 r138 21 21 22 22 #undef FUNCTION 23 #define FUNCTION "Load_store_unit::function_speculative_load_ commit_genMealy_insert"24 void Load_store_unit::function_speculative_load_ commit_genMealy_insert (void)23 #define FUNCTION "Load_store_unit::function_speculative_load_access_genMealy_insert" 24 void Load_store_unit::function_speculative_load_access_genMealy_insert (void) 25 25 { 26 26 log_begin(Load_store_unit,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_retire.cpp
r137 r138 21 21 22 22 #undef FUNCTION 23 #define FUNCTION "Load_store_unit::function_speculative_load_ commit_genMealy_retire"24 void Load_store_unit::function_speculative_load_ commit_genMealy_retire (void)23 #define FUNCTION "Load_store_unit::function_speculative_load_access_genMealy_retire" 24 void Load_store_unit::function_speculative_load_access_genMealy_retire (void) 25 25 { 26 26 log_begin(Load_store_unit,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMoore.cpp
r137 r138 21 21 22 22 #undef FUNCTION 23 #define FUNCTION "Load_store_unit::function_speculative_load_ commit_genMoore"24 void Load_store_unit::function_speculative_load_ commit_genMoore (void)23 #define FUNCTION "Load_store_unit::function_speculative_load_access_genMoore" 24 void Load_store_unit::function_speculative_load_access_genMoore (void) 25 25 { 26 26 log_begin(Load_store_unit,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_transition.cpp
r137 r138 228 228 229 229 #undef FUNCTION 230 #define FUNCTION "Load_store_unit::function_speculative_load_ commit_transition"231 void Load_store_unit::function_speculative_load_ commit_transition (void)230 #define FUNCTION "Load_store_unit::function_speculative_load_access_transition" 231 void Load_store_unit::function_speculative_load_access_transition (void) 232 232 { 233 233 log_begin(Load_store_unit,FUNCTION); … … 245 245 { 246 246 reg_STORE_QUEUE_NB_CHECK [i] = 0; 247 // reg_STORE_QUEUE_INVALID [i] = 0; 247 248 _store_queue [i]._state = STORE_QUEUE_EMPTY; 248 249 _store_queue [i]._context_id = 0; // not necessary … … 283 284 _load_queue [i]._num_reg_rd = 0; // not necessary 284 285 _load_queue [i]._exception = 0; // not necessary 286 _load_queue [i]._can_speculative_commit= 0; // not necessary 285 287 } 286 288 … … 407 409 408 410 // find a entry that it need a check 409 Tlsq_ptr_t store_queue_ptr_write = _load_queue[index_load_queue]._store_queue_ptr_write;410 Tlsq_ptr_t store_queue_ptr_read = _load_queue[index_load_queue]._store_queue_ptr_read ;411 Tlsq_ptr_t store_queue_empty = _load_queue[index_load_queue]._store_queue_empty ;411 Tlsq_ptr_t store_queue_ptr_write = _load_queue[index_load_queue]._store_queue_ptr_write; 412 Tlsq_ptr_t store_queue_ptr_read = _load_queue[index_load_queue]._store_queue_ptr_read ; 413 Tlsq_ptr_t store_queue_empty = _load_queue[index_load_queue]._store_queue_empty ; 412 414 // Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write; 413 415 … … 442 444 443 445 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_write : %d",store_queue_ptr_write); 446 447 bool test_thread_id = true; 448 449 // Test thread id 450 if (_param->_have_port_context_id) 451 test_thread_id &= (_load_queue[index_load_queue]._context_id == _store_queue[store_queue_ptr_write]._context_id); 452 if (_param->_have_port_front_end_id) 453 test_thread_id &= (_load_queue[index_load_queue]._front_end_id == _store_queue[store_queue_ptr_write]._front_end_id); 454 if (_param->_have_port_ooo_engine_id) 455 test_thread_id &= (_load_queue[index_load_queue]._ooo_engine_id == _store_queue[store_queue_ptr_write]._ooo_engine_id); 444 456 445 457 // switch on store_queue state … … 450 462 case STORE_QUEUE_VALID_SPECULATIVE : 451 463 { 452 453 log_printf(TRACE,Load_store_unit,FUNCTION," * store have a valid entry"); 464 log_printf(TRACE,Load_store_unit,FUNCTION," * store have a valid entry"); 454 465 455 466 // TODO : MMU - nous considérons que les adresses sont physique 456 bool test_thread_id = true;457 458 // Test thread id459 if (_param->_have_port_context_id)460 test_thread_id &= (_load_queue[index_load_queue]._context_id == _store_queue[store_queue_ptr_write]._context_id);461 if (_param->_have_port_front_end_id)462 test_thread_id &= (_load_queue[index_load_queue]._front_end_id == _store_queue[store_queue_ptr_write]._front_end_id);463 if (_param->_have_port_ooo_engine_id)464 test_thread_id &= (_load_queue[index_load_queue]._ooo_engine_id == _store_queue[store_queue_ptr_write]._ooo_engine_id);465 466 467 if (test_thread_id) 467 468 { … … 481 482 { 482 483 log_printf(TRACE,Load_store_unit,FUNCTION," * address_msb is the same."); 484 483 485 // all case - [] : store, () : load 484 486 // (1) store_max >= load_max and store_min <= load_min ...[...(...)...]... Ok - inclusion in store … … 533 535 log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_min : %d",store_num_byte_min); 534 536 log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_max : %d",store_num_byte_max); 535 536 // uint32_t load_nb_byte = (1<<memory_access(_load_queue[index_load_queue]._operation));537 538 // uint32_t load_num_byte_min = (load_addr & _param->_mask_address_lsb);539 // uint32_t load_num_byte_max = load_num_byte_min+load_nb_byte;540 541 // log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_min : %d",load_num_byte_min);542 // log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_max : %d",load_num_byte_max);543 544 // for (uint32_t num_load_byte=load_num_byte_min; num_load_byte<load_num_byte_max; num_load_byte ++)545 // {546 // // Make a mask547 // uint32_t num_store_byte = num_load_byte;548 549 537 550 538 … … 671 659 // The check is finish if all bit is set 672 660 end_check = (_load_queue[index_load_queue]._check_hit_byte == _param->_mask_check_hit_byte); 673 674 661 } 675 662 } … … 679 666 } 680 667 case STORE_QUEUE_EMPTY : 668 { 669 log_printf(TRACE,Load_store_unit,FUNCTION," * store is empty ... wait."); 670 break; 671 } 672 681 673 case STORE_QUEUE_NO_VALID_NO_SPECULATIVE : 682 674 { 683 log_printf(TRACE,Load_store_unit,FUNCTION," * store have an invalid entry"); 675 log_printf(TRACE,Load_store_unit,FUNCTION," * store have an invalid entry"); 676 677 if (test_thread_id) 678 { 679 end_check = true; // previous store is invalid -> exception 680 change_state = true; 681 } 682 else 683 next = true; 684 684 685 break; 685 686 } … … 852 853 case STORE_QUEUE_EMPTY : 853 854 { 855 // reg_STORE_QUEUE_INVALID [index] = false; // new first store instruction 856 854 857 if (is_operation_memory_store_head(operation) == true) 855 858 { … … 858 861 // test if is a speculation 859 862 if (operation == OPERATION_MEMORY_STORE_HEAD_KO) 860 new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; 863 { 864 new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; 865 // reg_STORE_QUEUE_INVALID [index] = true; 866 } 861 867 else 862 868 new_exception = EXCEPTION_MEMORY_NONE; … … 901 907 #endif 902 908 if (operation == OPERATION_MEMORY_STORE_HEAD_KO) 903 new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; // great prioritary 904 909 { 910 new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; // great prioritary 911 // reg_STORE_QUEUE_INVALID [index] = true; 912 } 913 905 914 if (new_exception != EXCEPTION_MEMORY_NONE) 906 915 new_state = STORE_QUEUE_COMMIT; … … 913 922 case STORE_QUEUE_COMMIT : 914 923 { 915 throw ERRORMORPHEO(FUNCTION,"<Load_store_unit::function_speculative_load_ commit_transition> Invalid state and operation");924 throw ERRORMORPHEO(FUNCTION,"<Load_store_unit::function_speculative_load_access_transition> Invalid state and operation"); 916 925 } 917 926 } … … 1115 1124 _load_queue [ptr_write]._exception = exception; 1116 1125 _load_queue [ptr_write]._rdata = address; // to the exception 1126 1127 switch (_param->_speculative_commit_predictor_scheme) 1128 { 1129 1130 case PREDICTOR_NEVER_TAKE : {_load_queue [ptr_write]._can_speculative_commit = false; break;} 1131 case PREDICTOR_ALWAYS_TAKE : {_load_queue [ptr_write]._can_speculative_commit = true ; break;} 1132 case PREDICTOR_COUNTER : {_load_queue [ptr_write]._can_speculative_commit = false; break;} // TODO 1133 default : 1134 { 1135 // throw ERRORMORPHEO(FUNCTION,_("Invalid predictor scheme.\n")); 1136 _load_queue [ptr_write]._can_speculative_commit = false; 1137 break; 1138 } 1139 } 1117 1140 1118 1141 log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
r124 r138 20 20 #undef FUNCTION 21 21 #define FUNCTION "Load_store_unit::Parameters" 22 Parameters::Parameters (uint32_t size_store_queue , 23 uint32_t size_load_queue , 24 uint32_t size_speculative_access_queue, 25 uint32_t nb_port_check , 26 Tspeculative_load_t speculative_load , 27 uint32_t nb_bypass_memory , 28 uint32_t nb_cache_port , 29 uint32_t nb_inst_memory , 30 uint32_t nb_context , 31 uint32_t nb_front_end , 32 uint32_t nb_ooo_engine , 33 uint32_t nb_packet , 34 uint32_t size_general_data , 35 uint32_t size_special_data , 36 uint32_t nb_general_register , 37 uint32_t nb_special_register , 38 uint32_t nb_thread , 39 bool * num_thread_valid , //[nb_thread] 22 Parameters::Parameters (uint32_t size_store_queue , 23 uint32_t size_load_queue , 24 uint32_t size_speculative_access_queue , 25 uint32_t nb_store_queue_bank , 26 uint32_t nb_load_queue_bank , 27 uint32_t nb_port_check , 28 Tspeculative_load_t speculative_load , 29 Tpredictor_t speculative_commit_predictor_scheme, 30 uint32_t * lsu_pht_size_counter ,//[1] 31 uint32_t * lsu_pht_nb_counter ,//[1] 32 uint32_t nb_bypass_memory , 33 uint32_t nb_cache_port , 34 uint32_t nb_inst_memory , 35 uint32_t nb_context , 36 uint32_t nb_front_end , 37 uint32_t nb_ooo_engine , 38 uint32_t nb_packet , 39 uint32_t size_general_data , 40 uint32_t size_special_data , 41 uint32_t nb_general_register , 42 uint32_t nb_special_register , 43 uint32_t nb_thread , 44 bool * num_thread_valid , //[nb_thread] 40 45 bool is_toplevel) 41 46 { 42 47 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 43 48 44 _size_store_queue = size_store_queue ; 45 _size_load_queue = size_load_queue ; 46 _size_speculative_access_queue = size_speculative_access_queue; 47 _nb_port_check = nb_port_check ; 48 _speculative_load = speculative_load ; 49 _nb_bypass_memory = nb_bypass_memory ; 50 _nb_cache_port = nb_cache_port ; 51 _nb_inst_memory = nb_inst_memory ; 52 _nb_context = nb_context ; 53 _nb_front_end = nb_front_end ; 54 _nb_ooo_engine = nb_ooo_engine ; 55 _nb_packet = nb_packet ; 56 _nb_general_register = nb_general_register ; 57 _nb_special_register = nb_special_register ; 58 _nb_thread = nb_thread ; 59 _num_thread_valid = num_thread_valid ; 49 _size_store_queue = size_store_queue ; 50 _size_load_queue = size_load_queue ; 51 _size_speculative_access_queue = size_speculative_access_queue ; 52 _nb_store_queue_bank = nb_store_queue_bank ; 53 _nb_load_queue_bank = nb_load_queue_bank ; 54 _nb_port_check = nb_port_check ; 55 _speculative_load = speculative_load ; 56 _speculative_commit_predictor_scheme = speculative_commit_predictor_scheme; 57 _lsu_pht_size_counter = lsu_pht_size_counter ; 58 _lsu_pht_nb_counter = lsu_pht_nb_counter ; 59 _nb_bypass_memory = nb_bypass_memory ; 60 _nb_cache_port = nb_cache_port ; 61 _nb_inst_memory = nb_inst_memory ; 62 _nb_context = nb_context ; 63 _nb_front_end = nb_front_end ; 64 _nb_ooo_engine = nb_ooo_engine ; 65 _nb_packet = nb_packet ; 66 _nb_general_register = nb_general_register ; 67 _nb_special_register = nb_special_register ; 68 _nb_thread = nb_thread ; 69 _num_thread_valid = num_thread_valid ; 60 70 61 71 _size_speculative_access_queue_ptr = log2(size_speculative_access_queue); … … 99 109 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); 100 110 }; 101 102 // #undef FUNCTION103 // #define FUNCTION "Load_store_unit::Parameters (copy)"104 // Parameters::Parameters (Parameters & param):105 // _size_store_queue (param._size_store_queue ),106 // _size_load_queue (param._size_load_queue ),107 // _size_speculative_access_queue (param._size_speculative_access_queue),108 // _nb_port_check (param._nb_port_check ),109 // _speculative_load (param._speculative_load ),110 // _nb_bypass_memory (param._nb_bypass_memory ),111 // _nb_cache_port (param._nb_cache_port ),112 // _nb_inst_memory (param._nb_inst_memory ),113 // _nb_context (param._nb_context ),114 // _nb_front_end (param._nb_front_end ),115 // _nb_ooo_engine (param._nb_ooo_engine ),116 // _nb_packet (param._nb_packet ),117 // _size_general_data (param._size_general_data ),118 // _size_special_data (param._size_special_data ),119 // _nb_general_register (param._nb_general_register ),120 // _nb_special_register (param._nb_special_register ),121 122 // _size_address_store_queue (param._size_address_store_queue ),123 // _size_address_load_queue (param._size_address_load_queue ),124 // _size_address_speculative_access_queue (param._size_address_speculative_access_queue),125 126 // _size_context_id (param._size_context_id ),127 // _size_front_end_id (param._size_front_end_id ),128 // _size_ooo_engine_id (param._size_ooo_engine_id ),129 // _size_packet_id (param._size_packet_id ),130 // _size_general_register (param._size_general_register ),131 // _size_special_register (param._size_special_register ),132 // _size_dcache_context_id (param._size_dcache_context_id ),133 // _size_dcache_packet_id (param._size_dcache_packet_id ),134 135 // _have_port_context_id (param._have_port_context_id ),136 // _have_port_front_end_id (param._have_port_front_end_id ),137 // _have_port_ooo_engine_id (param._have_port_ooo_engine_id),138 // _have_port_packet_id (param._have_port_packet_id ),139 // _have_port_dcache_context_id(param._have_port_dcache_context_id),140 // _have_port_load_queue_ptr(param._have_port_load_queue_ptr),141 142 // _mask_address_lsb (param._mask_address_lsb),143 // _mask_address_msb (param._mask_address_msb)144 // {145 // log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");146 // test();147 // log_printf(FUNC,Load_store_unit,FUNCTION,"End");148 // };149 111 150 112 #undef FUNCTION -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp
r88 r138 6 6 */ 7 7 8 #include "Behavioural/include/Test.h" 8 9 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h" 9 10 #include <sstream> … … 29 30 switch (_speculative_load) 30 31 { 31 case SPECULATIVE_LOAD_ COMMIT:32 case SPECULATIVE_LOAD_ACCESS : 32 33 { 33 34 if (not (_nb_bypass_memory == 0)) … … 37 38 } 38 39 case NO_SPECULATIVE_LOAD : 39 case SPECULATIVE_LOAD_ACCESS :40 40 // case SPECULATIVE_LOAD_BYPASS : 41 // case SPECULATIVE_LOAD_COMMIT : 41 42 default : 42 43 { … … 55 56 test.error(_("Bypass number must be less than load_queue's size.\n")); 56 57 58 if (not is_multiple(_nb_store_queue_bank,_nb_inst_memory)) 59 test.error(_("Number of bank of store queue must be a multiple of number input instruction.\n")); 60 61 if (not is_multiple(_nb_load_queue_bank,_nb_inst_memory)) 62 test.error(_("Number of bank of load queue must be a multiple of number input instruction.\n")); 63 64 switch (_speculative_commit_predictor_scheme) 65 { 66 case PREDICTOR_NEVER_TAKE : 67 case PREDICTOR_ALWAYS_TAKE : 68 case PREDICTOR_COUNTER : 69 { 70 break; 71 } 72 case PREDICTOR_STATIC : 73 case PREDICTOR_LAST_TAKE : 74 case PREDICTOR_LOCAL : 75 case PREDICTOR_GLOBAL : 76 case PREDICTOR_META : 77 case PREDICTOR_CUSTOM : 78 { 79 test.error(toString(_("Predictor scheme \"%s\" is unsupported for load scheme.\n"),toString(_speculative_commit_predictor_scheme).c_str())); 80 break; 81 } 82 } 83 57 84 if (_nb_cache_port > 1) 58 85 test.warning(_("nb_cache_port > 1 is unsupported (Coming Soon).\n"));
Note: See TracChangeset
for help on using the changeset viewer.