Changeset 138 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest
- Timestamp:
- May 12, 2010, 7:34:01 PM (14 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info
r137 r138 3 3 target_dep all RegisterFile_Multi_Banked_00.ngc 4 4 target_dep RegisterFile_Multi_Banked_00.ngc RegisterFile_Multi_Banked_00.prj 5 target_dep RegisterFile_Multi_Banked_00.prj RegisterFile_Multi_Banked_00_bank_Pack.vhdl RegisterFile_Multi_Banked_00_bank.vhdl RegisterFile_Multi_Banked_00_Pack.vhdl RegisterFile_Multi_Banked_00_select_ 12_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_12_ports.vhdl RegisterFile_Multi_Banked_00_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_6_ports.vhdl RegisterFile_Multi_Banked_00.vhdl5 target_dep RegisterFile_Multi_Banked_00.prj RegisterFile_Multi_Banked_00_bank_Pack.vhdl RegisterFile_Multi_Banked_00_bank.vhdl RegisterFile_Multi_Banked_00_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports.vhdl RegisterFile_Multi_Banked_00.vhdl 6 6 7 7 # RegisterFile_Multi_Banked_01 8 8 target_dep all RegisterFile_Multi_Banked_01.ngc 9 9 target_dep RegisterFile_Multi_Banked_01.ngc RegisterFile_Multi_Banked_01.prj 10 target_dep RegisterFile_Multi_Banked_01.prj RegisterFile_Multi_Banked_01_bank_Pack.vhdl RegisterFile_Multi_Banked_01_bank.vhdl RegisterFile_Multi_Banked_01_Pack.vhdl RegisterFile_Multi_Banked_01_select_ 6_ports_Pack.vhdl RegisterFile_Multi_Banked_01_select_6_ports.vhdl RegisterFile_Multi_Banked_01.vhdl10 target_dep RegisterFile_Multi_Banked_01.prj RegisterFile_Multi_Banked_01_bank_Pack.vhdl RegisterFile_Multi_Banked_01_bank.vhdl RegisterFile_Multi_Banked_01_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports.vhdl RegisterFile_Multi_Banked_01.vhdl 11 11 12 12 # RegisterFile_Multi_Banked_02 13 13 target_dep all RegisterFile_Multi_Banked_02.ngc 14 14 target_dep RegisterFile_Multi_Banked_02.ngc RegisterFile_Multi_Banked_02.prj 15 target_dep RegisterFile_Multi_Banked_02.prj RegisterFile_Multi_Banked_02_bank_Pack.vhdl RegisterFile_Multi_Banked_02_bank.vhdl RegisterFile_Multi_Banked_02_Pack.vhdl RegisterFile_Multi_Banked_02_select_ 1_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_1_ports.vhdl RegisterFile_Multi_Banked_02_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_2_ports.vhdl RegisterFile_Multi_Banked_02.vhdl15 target_dep RegisterFile_Multi_Banked_02.prj RegisterFile_Multi_Banked_02_bank_Pack.vhdl RegisterFile_Multi_Banked_02_bank.vhdl RegisterFile_Multi_Banked_02_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports.vhdl RegisterFile_Multi_Banked_02.vhdl 16 16 17 17 # RegisterFile_Multi_Banked_03 18 18 target_dep all RegisterFile_Multi_Banked_03.ngc 19 19 target_dep RegisterFile_Multi_Banked_03.ngc RegisterFile_Multi_Banked_03.prj 20 target_dep RegisterFile_Multi_Banked_03.prj RegisterFile_Multi_Banked_03_bank_Pack.vhdl RegisterFile_Multi_Banked_03_bank.vhdl RegisterFile_Multi_Banked_03_Pack.vhdl RegisterFile_Multi_Banked_03_select_ 2_ports_Pack.vhdl RegisterFile_Multi_Banked_03_select_2_ports.vhdl RegisterFile_Multi_Banked_03.vhdl20 target_dep RegisterFile_Multi_Banked_03.prj RegisterFile_Multi_Banked_03_bank_Pack.vhdl RegisterFile_Multi_Banked_03_bank.vhdl RegisterFile_Multi_Banked_03_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports.vhdl RegisterFile_Multi_Banked_03.vhdl 21 21 22 22 # RegisterFile_Multi_Banked_04 23 23 target_dep all RegisterFile_Multi_Banked_04.ngc 24 24 target_dep RegisterFile_Multi_Banked_04.ngc RegisterFile_Multi_Banked_04.prj 25 target_dep RegisterFile_Multi_Banked_04.prj RegisterFile_Multi_Banked_04_bank_Pack.vhdl RegisterFile_Multi_Banked_04_bank.vhdl RegisterFile_Multi_Banked_04_Pack.vhdl RegisterFile_Multi_Banked_04_select_ 1_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_1_ports.vhdl RegisterFile_Multi_Banked_04_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_2_ports.vhdl RegisterFile_Multi_Banked_04.vhdl25 target_dep RegisterFile_Multi_Banked_04.prj RegisterFile_Multi_Banked_04_bank_Pack.vhdl RegisterFile_Multi_Banked_04_bank.vhdl RegisterFile_Multi_Banked_04_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports.vhdl RegisterFile_Multi_Banked_04.vhdl 26 26 27 27 # RegisterFile_Multi_Banked_05 28 28 target_dep all RegisterFile_Multi_Banked_05.ngc 29 29 target_dep RegisterFile_Multi_Banked_05.ngc RegisterFile_Multi_Banked_05.prj 30 target_dep RegisterFile_Multi_Banked_05.prj RegisterFile_Multi_Banked_05_bank_Pack.vhdl RegisterFile_Multi_Banked_05_bank.vhdl RegisterFile_Multi_Banked_05_Pack.vhdl RegisterFile_Multi_Banked_05_select_ 12_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_12_ports.vhdl RegisterFile_Multi_Banked_05_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_6_ports.vhdl RegisterFile_Multi_Banked_05.vhdl30 target_dep RegisterFile_Multi_Banked_05.prj RegisterFile_Multi_Banked_05_bank_Pack.vhdl RegisterFile_Multi_Banked_05_bank.vhdl RegisterFile_Multi_Banked_05_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports.vhdl RegisterFile_Multi_Banked_05.vhdl 31 31 32 32 # RegisterFile_Multi_Banked_06 33 33 target_dep all RegisterFile_Multi_Banked_06.ngc 34 34 target_dep RegisterFile_Multi_Banked_06.ngc RegisterFile_Multi_Banked_06.prj 35 target_dep RegisterFile_Multi_Banked_06.prj RegisterFile_Multi_Banked_06_bank_Pack.vhdl RegisterFile_Multi_Banked_06_bank.vhdl RegisterFile_Multi_Banked_06_Pack.vhdl RegisterFile_Multi_Banked_06_select_ 3_ports_Pack.vhdl RegisterFile_Multi_Banked_06_select_3_ports.vhdl RegisterFile_Multi_Banked_06.vhdl35 target_dep RegisterFile_Multi_Banked_06.prj RegisterFile_Multi_Banked_06_bank_Pack.vhdl RegisterFile_Multi_Banked_06_bank.vhdl RegisterFile_Multi_Banked_06_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports.vhdl RegisterFile_Multi_Banked_06.vhdl 36 36 37 37 # RegisterFile_Multi_Banked_07 38 38 target_dep all RegisterFile_Multi_Banked_07.ngc 39 39 target_dep RegisterFile_Multi_Banked_07.ngc RegisterFile_Multi_Banked_07.prj 40 target_dep RegisterFile_Multi_Banked_07.prj RegisterFile_Multi_Banked_07_bank_Pack.vhdl RegisterFile_Multi_Banked_07_bank.vhdl RegisterFile_Multi_Banked_07_Pack.vhdl RegisterFile_Multi_Banked_07_select_ 2_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports.vhdl RegisterFile_Multi_Banked_07.vhdl40 target_dep RegisterFile_Multi_Banked_07.prj RegisterFile_Multi_Banked_07_bank_Pack.vhdl RegisterFile_Multi_Banked_07_bank.vhdl RegisterFile_Multi_Banked_07_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports.vhdl RegisterFile_Multi_Banked_07_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports.vhdl RegisterFile_Multi_Banked_07.vhdl 41 41 42 42 # RegisterFile_Multi_Banked_08 43 43 target_dep all RegisterFile_Multi_Banked_08.ngc 44 44 target_dep RegisterFile_Multi_Banked_08.ngc RegisterFile_Multi_Banked_08.prj 45 target_dep RegisterFile_Multi_Banked_08.prj RegisterFile_Multi_Banked_08_bank_Pack.vhdl RegisterFile_Multi_Banked_08_bank.vhdl RegisterFile_Multi_Banked_08_Pack.vhdl RegisterFile_Multi_Banked_08_select_1 _ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_1_ports.vhdl RegisterFile_Multi_Banked_08_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_2_ports.vhdl RegisterFile_Multi_Banked_08.vhdl45 target_dep RegisterFile_Multi_Banked_08.prj RegisterFile_Multi_Banked_08_bank_Pack.vhdl RegisterFile_Multi_Banked_08_bank.vhdl RegisterFile_Multi_Banked_08_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports.vhdl RegisterFile_Multi_Banked_08_select_22_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_22_ports.vhdl RegisterFile_Multi_Banked_08.vhdl 46 46 47 47 # RegisterFile_Multi_Banked_09 48 48 target_dep all RegisterFile_Multi_Banked_09.ngc 49 49 target_dep RegisterFile_Multi_Banked_09.ngc RegisterFile_Multi_Banked_09.prj 50 target_dep RegisterFile_Multi_Banked_09.prj RegisterFile_Multi_Banked_09_bank_Pack.vhdl RegisterFile_Multi_Banked_09_bank.vhdl RegisterFile_Multi_Banked_09_Pack.vhdl RegisterFile_Multi_Banked_09_select_ 6_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_6_ports.vhdl RegisterFile_Multi_Banked_09.vhdl50 target_dep RegisterFile_Multi_Banked_09.prj RegisterFile_Multi_Banked_09_bank_Pack.vhdl RegisterFile_Multi_Banked_09_bank.vhdl RegisterFile_Multi_Banked_09_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports.vhdl RegisterFile_Multi_Banked_09_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_3_ports.vhdl RegisterFile_Multi_Banked_09_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_4_ports.vhdl RegisterFile_Multi_Banked_09.vhdl 51 51 52 52 # RegisterFile_Multi_Banked_10 53 53 target_dep all RegisterFile_Multi_Banked_10.ngc 54 54 target_dep RegisterFile_Multi_Banked_10.ngc RegisterFile_Multi_Banked_10.prj 55 target_dep RegisterFile_Multi_Banked_10.prj RegisterFile_Multi_Banked_10_bank_Pack.vhdl RegisterFile_Multi_Banked_10_bank.vhdl RegisterFile_Multi_Banked_10_Pack.vhdl RegisterFile_Multi_Banked_10_select_ 3_ports_Pack.vhdl RegisterFile_Multi_Banked_10_select_3_ports.vhdl RegisterFile_Multi_Banked_10.vhdl55 target_dep RegisterFile_Multi_Banked_10.prj RegisterFile_Multi_Banked_10_bank_Pack.vhdl RegisterFile_Multi_Banked_10_bank.vhdl RegisterFile_Multi_Banked_10_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports.vhdl RegisterFile_Multi_Banked_10.vhdl 56 56 57 # RegisterFile_Multi_Banked_11 58 target_dep all RegisterFile_Multi_Banked_11.ngc 59 target_dep RegisterFile_Multi_Banked_11.ngc RegisterFile_Multi_Banked_11.prj 60 target_dep RegisterFile_Multi_Banked_11.prj RegisterFile_Multi_Banked_11_bank_Pack.vhdl RegisterFile_Multi_Banked_11_bank.vhdl RegisterFile_Multi_Banked_11_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports.vhdl RegisterFile_Multi_Banked_11_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_2_ports.vhdl RegisterFile_Multi_Banked_11.vhdl 61
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