Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h	(revision 138)
@@ -50,6 +50,9 @@
   public    : Stat                           * _stat;
     
-  private   : counter_t                      * _stat_nb_read;
-  private   : counter_t                      * _stat_nb_write;
+  // private   : counter_t                      * _stat_nb_read;
+  // private   : counter_t                      * _stat_nb_write;
+  private   : counters_t                     * _stat_port_read;
+  private   : counters_t                     * _stat_port_write;
+  private   : counters_t                     * _stat_port_read_write;
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_statistics_declaration.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_statistics_declaration.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_statistics_declaration.cpp	(revision 138)
@@ -21,12 +21,32 @@
 		      param_statistics);
 
-    _stat_nb_read           = _stat->create_variable("nb_read" );
-    _stat_nb_write          = _stat->create_variable("nb_write");
+    if (_param->_nb_port_read>0)
+    _stat_port_read         = _stat->create_counters("port_read",_param->_nb_port_read,"",
+                                                     _("Usage of read port %d."),
+                                                     _("Percent of usage read port %d."),
+                                                     _("Average of usage read port.")
+                                                     );
 
-    _stat->create_expr_average_by_cycle("average_read" , "nb_read" , "", _("Average read by cycle" ));
-    _stat->create_expr_average_by_cycle("average_write", "nb_write", "", _("Average write by cycle"));
+    if (_param->_nb_port_write>0)
+    _stat_port_write        = _stat->create_counters("port_write",_param->_nb_port_write,"",
+                                                     _("Usage of write port %d."),
+                                                     _("Percent of usage write port %d."),
+                                                     _("Average of usage write port.")
+                                                     );
+    if (_param->_nb_port_read_write>0)
+    _stat_port_read_write   = _stat->create_counters("port_read_write",_param->_nb_port_read_write,"",
+                                                     _("Usage of read_write port."),
+                                                     _("Percent of usage read_write port %d."),
+                                                     _("Average of usage read_write port.")
+                                                     );
 
-    _stat->create_expr_percent         ("percent_use_read" , "average_read" , toString(_param->_nb_port_read +_param->_nb_port_read_write), _("Percent read by cycle" ));
-    _stat->create_expr_percent         ("percent_use_write", "average_write", toString(_param->_nb_port_write+_param->_nb_port_read_write), _("Percent write by cycle"));
+    // _stat_nb_read           = _stat->create_variable("nb_read" );
+    // _stat_nb_write          = _stat->create_variable("nb_write");
+
+    // _stat->create_expr_average_by_cycle("average_read" , "nb_read" , "", _("Average read by cycle" ));
+    // _stat->create_expr_average_by_cycle("average_write", "nb_write", "", _("Average write by cycle"));
+
+    // _stat->create_expr_percent         ("percent_use_read" , "average_read" , toString(_param->_nb_port_read +_param->_nb_port_read_write), _("Percent read by cycle" ));
+    // _stat->create_expr_percent         ("percent_use_write", "average_write", toString(_param->_nb_port_write+_param->_nb_port_read_write), _("Percent write by cycle"));
 
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp	(revision 138)
@@ -37,4 +37,9 @@
     else
       {
+#ifdef STATISTICS
+        uint32_t stat_nb_read      =0;
+        uint32_t stat_nb_write     =0;
+        uint32_t stat_nb_read_write=0;
+#endif
         for (uint32_t i=0; i<_param->_nb_port_write; i++)
           {
@@ -45,7 +50,11 @@
               {
 #ifdef STATISTICS
-                if (usage_is_set(_usage,USE_STATISTICS))
-                  (*_stat_nb_write) ++;
-#endif    
+                stat_nb_write++;
+#endif
+
+// #ifdef STATISTICS
+//                 if (usage_is_set(_usage,USE_STATISTICS))
+//                   (*_stat_nb_write) ++;
+// #endif    
 
                 Taddress_t address = (_param->_have_port_address)?PORT_READ(in_WRITE_ADDRESS[i]):0;
@@ -74,10 +83,14 @@
             if (PORT_READ(in_READ_WRITE_VAL[i]) == true)
               {
+#ifdef STATISTICS
+                stat_nb_read_write++;
+#endif
+
                 if (PORT_READ(in_READ_WRITE_RW [i]) == RW_WRITE)
                   {
-#ifdef STATISTICS
-                    if (usage_is_set(_usage,USE_STATISTICS))
-                      (*_stat_nb_write) ++;
-#endif    
+// #ifdef STATISTICS
+//                     if (usage_is_set(_usage,USE_STATISTICS))
+//                       (*_stat_nb_write) ++;
+// #endif    
                     
                     Taddress_t address = (_param->_have_port_address)?PORT_READ(in_READ_WRITE_ADDRESS[i]):0;
@@ -95,21 +108,34 @@
                     reg_DATA[address] = data;
                   }
-#ifdef STATISTICS
-                else
-                  {
-                    if (usage_is_set(_usage,USE_STATISTICS))
-                      (*_stat_nb_read) ++;
-                  }
-#endif    
+// #ifdef STATISTICS
+//                 else
+//                   {
+//                     if (usage_is_set(_usage,USE_STATISTICS))
+//                       (*_stat_nb_read) ++;
+//                   }
+// #endif    
               }
           }
+
+        
+#ifdef STATISTICS
+        if (usage_is_set(_usage,USE_STATISTICS))
+          {
+            for (uint32_t i=0; i<_param->_nb_port_read; i++)
+              if ( PORT_READ(in_READ_VAL [i]) == 1)
+                {
+                  stat_nb_read ++;
+                  // (*_stat_nb_read) ++;
+                }
+
+            if (_param->_nb_port_read>0)
+            (*_stat_port_read      ) += stat_nb_read;
+            if (_param->_nb_port_write>0)
+            (*_stat_port_write     ) += stat_nb_write;
+            if (_param->_nb_port_read_write>0)
+            (*_stat_port_read_write) += stat_nb_read_write;
+          }
+#endif    
       }
-
-#ifdef STATISTICS
-    if (usage_is_set(_usage,USE_STATISTICS))
-      for (uint32_t i=0; i<_param->_nb_port_read; i++)
-        if ( PORT_READ(in_READ_VAL [i]) == 1)
-          (*_stat_nb_read) ++;
-#endif    
 
 #if defined(DEBUG_RegisterFile_Monolithic) and DEBUG_RegisterFile_Monolithic and (DEBUG >= DEBUG_TRACE)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info	(revision 138)
@@ -3,54 +3,59 @@
 target_dep	all	RegisterFile_Multi_Banked_00.ngc
 target_dep	RegisterFile_Multi_Banked_00.ngc	RegisterFile_Multi_Banked_00.prj
-target_dep	RegisterFile_Multi_Banked_00.prj	RegisterFile_Multi_Banked_00_bank_Pack.vhdl RegisterFile_Multi_Banked_00_bank.vhdl RegisterFile_Multi_Banked_00_Pack.vhdl RegisterFile_Multi_Banked_00_select_12_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_12_ports.vhdl RegisterFile_Multi_Banked_00_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_6_ports.vhdl RegisterFile_Multi_Banked_00.vhdl
+target_dep	RegisterFile_Multi_Banked_00.prj	RegisterFile_Multi_Banked_00_bank_Pack.vhdl RegisterFile_Multi_Banked_00_bank.vhdl RegisterFile_Multi_Banked_00_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports.vhdl RegisterFile_Multi_Banked_00.vhdl
 
 # RegisterFile_Multi_Banked_01
 target_dep	all	RegisterFile_Multi_Banked_01.ngc
 target_dep	RegisterFile_Multi_Banked_01.ngc	RegisterFile_Multi_Banked_01.prj
-target_dep	RegisterFile_Multi_Banked_01.prj	RegisterFile_Multi_Banked_01_bank_Pack.vhdl RegisterFile_Multi_Banked_01_bank.vhdl RegisterFile_Multi_Banked_01_Pack.vhdl RegisterFile_Multi_Banked_01_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_01_select_6_ports.vhdl RegisterFile_Multi_Banked_01.vhdl
+target_dep	RegisterFile_Multi_Banked_01.prj	RegisterFile_Multi_Banked_01_bank_Pack.vhdl RegisterFile_Multi_Banked_01_bank.vhdl RegisterFile_Multi_Banked_01_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports.vhdl RegisterFile_Multi_Banked_01.vhdl
 
 # RegisterFile_Multi_Banked_02
 target_dep	all	RegisterFile_Multi_Banked_02.ngc
 target_dep	RegisterFile_Multi_Banked_02.ngc	RegisterFile_Multi_Banked_02.prj
-target_dep	RegisterFile_Multi_Banked_02.prj	RegisterFile_Multi_Banked_02_bank_Pack.vhdl RegisterFile_Multi_Banked_02_bank.vhdl RegisterFile_Multi_Banked_02_Pack.vhdl RegisterFile_Multi_Banked_02_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_1_ports.vhdl RegisterFile_Multi_Banked_02_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_2_ports.vhdl RegisterFile_Multi_Banked_02.vhdl
+target_dep	RegisterFile_Multi_Banked_02.prj	RegisterFile_Multi_Banked_02_bank_Pack.vhdl RegisterFile_Multi_Banked_02_bank.vhdl RegisterFile_Multi_Banked_02_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports.vhdl RegisterFile_Multi_Banked_02.vhdl
 
 # RegisterFile_Multi_Banked_03
 target_dep	all	RegisterFile_Multi_Banked_03.ngc
 target_dep	RegisterFile_Multi_Banked_03.ngc	RegisterFile_Multi_Banked_03.prj
-target_dep	RegisterFile_Multi_Banked_03.prj	RegisterFile_Multi_Banked_03_bank_Pack.vhdl RegisterFile_Multi_Banked_03_bank.vhdl RegisterFile_Multi_Banked_03_Pack.vhdl RegisterFile_Multi_Banked_03_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_03_select_2_ports.vhdl RegisterFile_Multi_Banked_03.vhdl
+target_dep	RegisterFile_Multi_Banked_03.prj	RegisterFile_Multi_Banked_03_bank_Pack.vhdl RegisterFile_Multi_Banked_03_bank.vhdl RegisterFile_Multi_Banked_03_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports.vhdl RegisterFile_Multi_Banked_03.vhdl
 
 # RegisterFile_Multi_Banked_04
 target_dep	all	RegisterFile_Multi_Banked_04.ngc
 target_dep	RegisterFile_Multi_Banked_04.ngc	RegisterFile_Multi_Banked_04.prj
-target_dep	RegisterFile_Multi_Banked_04.prj	RegisterFile_Multi_Banked_04_bank_Pack.vhdl RegisterFile_Multi_Banked_04_bank.vhdl RegisterFile_Multi_Banked_04_Pack.vhdl RegisterFile_Multi_Banked_04_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_1_ports.vhdl RegisterFile_Multi_Banked_04_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_2_ports.vhdl RegisterFile_Multi_Banked_04.vhdl
+target_dep	RegisterFile_Multi_Banked_04.prj	RegisterFile_Multi_Banked_04_bank_Pack.vhdl RegisterFile_Multi_Banked_04_bank.vhdl RegisterFile_Multi_Banked_04_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports.vhdl RegisterFile_Multi_Banked_04.vhdl
 
 # RegisterFile_Multi_Banked_05
 target_dep	all	RegisterFile_Multi_Banked_05.ngc
 target_dep	RegisterFile_Multi_Banked_05.ngc	RegisterFile_Multi_Banked_05.prj
-target_dep	RegisterFile_Multi_Banked_05.prj	RegisterFile_Multi_Banked_05_bank_Pack.vhdl RegisterFile_Multi_Banked_05_bank.vhdl RegisterFile_Multi_Banked_05_Pack.vhdl RegisterFile_Multi_Banked_05_select_12_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_12_ports.vhdl RegisterFile_Multi_Banked_05_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_6_ports.vhdl RegisterFile_Multi_Banked_05.vhdl
+target_dep	RegisterFile_Multi_Banked_05.prj	RegisterFile_Multi_Banked_05_bank_Pack.vhdl RegisterFile_Multi_Banked_05_bank.vhdl RegisterFile_Multi_Banked_05_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports.vhdl RegisterFile_Multi_Banked_05.vhdl
 
 # RegisterFile_Multi_Banked_06
 target_dep	all	RegisterFile_Multi_Banked_06.ngc
 target_dep	RegisterFile_Multi_Banked_06.ngc	RegisterFile_Multi_Banked_06.prj
-target_dep	RegisterFile_Multi_Banked_06.prj	RegisterFile_Multi_Banked_06_bank_Pack.vhdl RegisterFile_Multi_Banked_06_bank.vhdl RegisterFile_Multi_Banked_06_Pack.vhdl RegisterFile_Multi_Banked_06_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_06_select_3_ports.vhdl RegisterFile_Multi_Banked_06.vhdl
+target_dep	RegisterFile_Multi_Banked_06.prj	RegisterFile_Multi_Banked_06_bank_Pack.vhdl RegisterFile_Multi_Banked_06_bank.vhdl RegisterFile_Multi_Banked_06_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports.vhdl RegisterFile_Multi_Banked_06.vhdl
 
 # RegisterFile_Multi_Banked_07
 target_dep	all	RegisterFile_Multi_Banked_07.ngc
 target_dep	RegisterFile_Multi_Banked_07.ngc	RegisterFile_Multi_Banked_07.prj
-target_dep	RegisterFile_Multi_Banked_07.prj	RegisterFile_Multi_Banked_07_bank_Pack.vhdl RegisterFile_Multi_Banked_07_bank.vhdl RegisterFile_Multi_Banked_07_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports.vhdl RegisterFile_Multi_Banked_07.vhdl
+target_dep	RegisterFile_Multi_Banked_07.prj	RegisterFile_Multi_Banked_07_bank_Pack.vhdl RegisterFile_Multi_Banked_07_bank.vhdl RegisterFile_Multi_Banked_07_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports.vhdl RegisterFile_Multi_Banked_07_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports.vhdl RegisterFile_Multi_Banked_07.vhdl
 
 # RegisterFile_Multi_Banked_08
 target_dep	all	RegisterFile_Multi_Banked_08.ngc
 target_dep	RegisterFile_Multi_Banked_08.ngc	RegisterFile_Multi_Banked_08.prj
-target_dep	RegisterFile_Multi_Banked_08.prj	RegisterFile_Multi_Banked_08_bank_Pack.vhdl RegisterFile_Multi_Banked_08_bank.vhdl RegisterFile_Multi_Banked_08_Pack.vhdl RegisterFile_Multi_Banked_08_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_1_ports.vhdl RegisterFile_Multi_Banked_08_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_2_ports.vhdl RegisterFile_Multi_Banked_08.vhdl
+target_dep	RegisterFile_Multi_Banked_08.prj	RegisterFile_Multi_Banked_08_bank_Pack.vhdl RegisterFile_Multi_Banked_08_bank.vhdl RegisterFile_Multi_Banked_08_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports.vhdl RegisterFile_Multi_Banked_08_select_22_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_22_ports.vhdl RegisterFile_Multi_Banked_08.vhdl
 
 # RegisterFile_Multi_Banked_09
 target_dep	all	RegisterFile_Multi_Banked_09.ngc
 target_dep	RegisterFile_Multi_Banked_09.ngc	RegisterFile_Multi_Banked_09.prj
-target_dep	RegisterFile_Multi_Banked_09.prj	RegisterFile_Multi_Banked_09_bank_Pack.vhdl RegisterFile_Multi_Banked_09_bank.vhdl RegisterFile_Multi_Banked_09_Pack.vhdl RegisterFile_Multi_Banked_09_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_6_ports.vhdl RegisterFile_Multi_Banked_09.vhdl
+target_dep	RegisterFile_Multi_Banked_09.prj	RegisterFile_Multi_Banked_09_bank_Pack.vhdl RegisterFile_Multi_Banked_09_bank.vhdl RegisterFile_Multi_Banked_09_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports.vhdl RegisterFile_Multi_Banked_09_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_3_ports.vhdl RegisterFile_Multi_Banked_09_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_4_ports.vhdl RegisterFile_Multi_Banked_09.vhdl
 
 # RegisterFile_Multi_Banked_10
 target_dep	all	RegisterFile_Multi_Banked_10.ngc
 target_dep	RegisterFile_Multi_Banked_10.ngc	RegisterFile_Multi_Banked_10.prj
-target_dep	RegisterFile_Multi_Banked_10.prj	RegisterFile_Multi_Banked_10_bank_Pack.vhdl RegisterFile_Multi_Banked_10_bank.vhdl RegisterFile_Multi_Banked_10_Pack.vhdl RegisterFile_Multi_Banked_10_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_10_select_3_ports.vhdl RegisterFile_Multi_Banked_10.vhdl
+target_dep	RegisterFile_Multi_Banked_10.prj	RegisterFile_Multi_Banked_10_bank_Pack.vhdl RegisterFile_Multi_Banked_10_bank.vhdl RegisterFile_Multi_Banked_10_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports.vhdl RegisterFile_Multi_Banked_10.vhdl
 
+# RegisterFile_Multi_Banked_11
+target_dep	all	RegisterFile_Multi_Banked_11.ngc
+target_dep	RegisterFile_Multi_Banked_11.ngc	RegisterFile_Multi_Banked_11.prj
+target_dep	RegisterFile_Multi_Banked_11.prj	RegisterFile_Multi_Banked_11_bank_Pack.vhdl RegisterFile_Multi_Banked_11_bank.vhdl RegisterFile_Multi_Banked_11_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports.vhdl RegisterFile_Multi_Banked_11_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_2_ports.vhdl RegisterFile_Multi_Banked_11.vhdl
+
