Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameters.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameters.h	(revision 138)
@@ -59,4 +59,5 @@
     // Read bloc
   public : uint32_t                _nb_read_bloc                                  ;//
+  public : uint32_t              * _nb_inst_read                                  ;//[nb_read_bloc]
   public : uint32_t              * _size_read_queue                               ;//[nb_read_bloc]
   public : uint32_t              * _size_reservation_station                      ;//[nb_read_bloc]
@@ -65,4 +66,5 @@
     // Write bloc
   public : uint32_t                _nb_write_bloc                                 ;//
+  public : uint32_t              * _nb_inst_write                                 ;//[nb_write_bloc]
   public : uint32_t              * _size_write_queue                              ;//[nb_write_bloc]
   public : uint32_t              * _size_execute_queue                            ;//[nb_write_bloc]
@@ -76,7 +78,12 @@
   public : uint32_t              * _size_load_queue                               ;//[nb_load_store_unit]
   public : uint32_t              * _size_speculative_access_queue                 ;//[nb_load_store_unit]
+  public : uint32_t              * _nb_store_queue_bank                           ;//[nb_load_store_unit]
+  public : uint32_t              * _nb_load_queue_bank                            ;//[nb_load_store_unit]
   public : uint32_t              * _nb_port_check                                 ;//[nb_load_store_unit]
   public : core::multi_execute_loop::execute_loop::Tspeculative_load_t  
                                  * _speculative_load                              ;//[nb_load_store_unit]
+  public : Tpredictor_t          * _speculative_commit_predictor_scheme           ;//[nb_load_store_unit]
+  public : uint32_t             ** _lsu_pht_size_counter                          ;//[nb_load_store_unit][1]
+  public : uint32_t             ** _lsu_pht_nb_counter                            ;//[nb_load_store_unit][1]
   public : uint32_t              * _nb_bypass_memory                              ;//[nb_load_store_unit]
   public : uint32_t              * _nb_cache_port                                 ;//[nb_load_store_unit]
@@ -130,4 +137,6 @@
   public : uint32_t              * _size_re_order_buffer                          ;//[nb_ooo_engine]
   public : uint32_t              * _nb_re_order_buffer_bank                       ;//[nb_ooo_engine]
+  public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Tretire_ooo_scheme_t
+                                 * _retire_ooo_scheme                             ;//[nb_ooo_engine]
   public : Tpriority_t           * _commit_priority                               ;//[nb_ooo_engine]
   public : Tload_balancing_t     * _commit_load_balancing                         ;//[nb_ooo_engine]
@@ -139,6 +148,4 @@
   public : Tload_balancing_t     * _issue_load_balancing                          ;//[nb_ooo_engine]
   public : uint32_t              * _size_reexecute_queue                          ;//[nb_ooo_engine]
-  public : Tpriority_t           * _reexecute_priority                            ;//[nb_ooo_engine]
-  public : Tload_balancing_t     * _reexecute_load_balancing                      ;//[nb_ooo_engine]
  
     // Execute_loop
@@ -166,8 +173,8 @@
   public : uint32_t              * _link_decod_bloc_with_thread                   ;//[nb_thread]
   public : uint32_t              * _link_rename_bloc_with_front_end               ;//[nb_front_end]
-  public : bool                *** _table_dispatch                                ;//[nb_ooo_engine][nb_inst_issue][nb_read_bloc]
-  public : bool                 ** _link_read_bloc_and_load_store_unit            ;//[nb_read_bloc][nb_load_store_unit]
+//public : bool                *** _table_dispatch                                ;//[nb_ooo_engine][nb_issue_queue_bank][nb_read_bloc]
+  public : uint32_t              * _link_read_bloc_with_load_store_unit           ;//[nb_load_store_unit]
   public : bool                 ** _link_read_bloc_and_functionnal_unit           ;//[nb_read_bloc][nb_functionnal_unit]
-  public : bool                 ** _link_write_bloc_and_load_store_unit           ;//[nb_write_bloc][nb_load_store_unit]
+  public : uint32_t              * _link_write_bloc_with_load_store_unit          ;//[nb_load_store_unit]
   public : bool                 ** _link_write_bloc_and_functionnal_unit          ;//[nb_write_bloc][nb_functionnal_unit]
   public : uint32_t              * _link_load_store_unit_with_thread              ;//[nb_thread]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp	(revision 138)
@@ -46,5 +46,5 @@
                 fromString<uint32_t>         (_simulator->getParam("debug_idle_time")));
 
-    log_init(fromString<bool>(_simulator->getParam("debug_log_file_generate")),
+    log_init(fromString<bool>  (_simulator->getParam("debug_log_file_generate")),
              fromString<bool>  (_simulator->getParam("simulation_file_with_date")),
              fromString<bool>  (_simulator->getParam("simulation_file_with_pid")),
@@ -91,9 +91,10 @@
     // Simulation condition stop 
     //--------------------------------------------------
-    simulation_init (fromString<double>(_simulator->getParam("simulation_nb_cycle")),
-                     fromString<double>(_simulator->getParam("debug_nb_cycle")),
-                     fromString<double>(_simulator->getParam("simulation_nb_instruction")),
-                     fromString<bool>  (_simulator->getParam("simulation_file_with_date")),
-                     fromString<bool>  (_simulator->getParam("simulation_file_with_pid"))
+    simulation_init (fromString<double>     (_simulator->getParam("simulation_nb_cycle")),
+                     fromString<double>     (_simulator->getParam("debug_nb_cycle")),
+                     fromString<double>     (_simulator->getParam("simulation_nb_instruction")),
+                     fromString<stop_type_t>(_simulator->getParam("simulation_stop_type")),
+                     fromString<bool>       (_simulator->getParam("simulation_file_with_date")),
+                     fromString<bool>       (_simulator->getParam("simulation_file_with_pid"))
                      );
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance.cpp	(revision 138)
@@ -74,8 +74,8 @@
         DELETE1(_param->_link_load_store_unit_with_thread       ,_param->_nb_thread);
         DELETE2(_param->_link_write_bloc_and_functionnal_unit   ,_param->_nb_write_bloc,_param->_nb_functionnal_unit);
-        DELETE2(_param->_link_write_bloc_and_load_store_unit    ,_param->_nb_write_bloc,_param->_nb_load_store_unit);
+        DELETE1(_param->_link_write_bloc_with_load_store_unit   ,_param->_nb_load_store_unit);
         DELETE2(_param->_link_read_bloc_and_functionnal_unit    ,_param->_nb_read_bloc,_param->_nb_functionnal_unit);
-        DELETE2(_param->_link_read_bloc_and_load_store_unit     ,_param->_nb_read_bloc,_param->_nb_load_store_unit);
-        DELETE3(_param->_table_dispatch                         ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_nb_read_bloc);
+        DELETE1(_param->_link_read_bloc_with_load_store_unit    ,_param->_nb_load_store_unit);
+//      DELETE3(_param->_table_dispatch                         ,_param->_nb_ooo_engine,_param->_nb_issue_queue_bank[it1],_param->_nb_read_bloc);
         DELETE1(_param->_link_rename_bloc_with_front_end        ,_param->_nb_front_end);
         DELETE1(_param->_link_decod_bloc_with_thread            ,_param->_nb_thread);
@@ -98,6 +98,4 @@
         DELETE1(_param->_nb_execute_unit                        ,_param->_nb_execute_loop);
         DELETE1(_param->_nb_read_unit                           ,_param->_nb_execute_loop);
-        DELETE1(_param->_reexecute_load_balancing               ,_param->_nb_ooo_engine);
-        DELETE1(_param->_reexecute_priority                     ,_param->_nb_ooo_engine);
         DELETE1(_param->_size_reexecute_queue                   ,_param->_nb_ooo_engine);
         DELETE1(_param->_issue_load_balancing                   ,_param->_nb_ooo_engine);
@@ -108,4 +106,5 @@
         DELETE1(_param->_commit_load_balancing                  ,_param->_nb_ooo_engine);
         DELETE1(_param->_commit_priority                        ,_param->_nb_ooo_engine);
+        DELETE1(_param->_retire_ooo_scheme                      ,_param->_nb_ooo_engine);
         DELETE1(_param->_nb_re_order_buffer_bank                ,_param->_nb_ooo_engine);
         DELETE1(_param->_size_re_order_buffer                   ,_param->_nb_ooo_engine);
@@ -136,19 +135,27 @@
         DELETE3(_param->_timing                                 ,_param->_nb_functionnal_unit,MAX_TYPE,MAX_OPERATION);
         DELETE1(_param->_nb_inst_functionnal_unit               ,_param->_nb_functionnal_unit);
-        DELETE1(_param->_speculative_load                       ,_param->_nb_load_store_unit);
         DELETE1(_param->_nb_inst_memory                         ,_param->_nb_load_store_unit);
         DELETE1(_param->_nb_cache_port                          ,_param->_nb_load_store_unit);
         DELETE1(_param->_nb_bypass_memory                       ,_param->_nb_load_store_unit);
+        DELETE2(_param->_lsu_pht_nb_counter                     ,_param->_nb_load_store_unit,1);
+        DELETE2(_param->_lsu_pht_size_counter                   ,_param->_nb_load_store_unit,1);
+        DELETE1(_param->_speculative_commit_predictor_scheme    ,_param->_nb_load_store_unit);
+        DELETE1(_param->_speculative_load                       ,_param->_nb_load_store_unit);
         DELETE1(_param->_nb_port_check                          ,_param->_nb_load_store_unit);
+        DELETE1(_param->_nb_load_queue_bank                     ,_param->_nb_load_store_unit);
+        DELETE1(_param->_nb_store_queue_bank                    ,_param->_nb_load_store_unit);
         DELETE1(_param->_size_speculative_access_queue          ,_param->_nb_load_store_unit);
         DELETE1(_param->_size_load_queue                        ,_param->_nb_load_store_unit);
         DELETE1(_param->_size_store_queue                       ,_param->_nb_load_store_unit);
+
         DELETE1(_param->_write_queue_scheme                     ,_param->_nb_write_bloc);
         DELETE1(_param->_nb_bypass_write                        ,_param->_nb_write_bloc);
         DELETE1(_param->_size_execute_queue                     ,_param->_nb_write_bloc);
         DELETE1(_param->_size_write_queue                       ,_param->_nb_write_bloc);
+        DELETE1(_param->_nb_inst_write                          ,_param->_nb_write_bloc);
         DELETE1(_param->_nb_inst_retire_reservation_station     ,_param->_nb_read_bloc);
         DELETE1(_param->_size_reservation_station               ,_param->_nb_read_bloc);
         DELETE1(_param->_size_read_queue                        ,_param->_nb_read_bloc);
+        DELETE1(_param->_nb_inst_read                           ,_param->_nb_read_bloc);
 //      DELETE1(_param->_size_read_counter                      ,_param->_nb_rename_bloc);
         DELETE1(_param->_nb_rename_unit_bank                    ,_param->_nb_rename_bloc);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp	(revision 138)
@@ -138,4 +138,5 @@
     // Read_bloc
     //-----------------------------------------------------
+    ALLOC1(_param->_nb_inst_read                      ,uint32_t,_param->_nb_read_bloc);
     ALLOC1(_param->_size_read_queue                   ,uint32_t,_param->_nb_read_bloc);
     ALLOC1(_param->_size_reservation_station          ,uint32_t,_param->_nb_read_bloc);
@@ -146,4 +147,5 @@
       //log_printf(INFO,Configuration,FUNCTION,_("READ_BLOC [%d]"),i);
 
+        _param->_nb_inst_read                       [i] = fromString<uint32_t> (getParam("nb_inst_read"                      ,"read_bloc",toString(i).c_str(),""));
         _param->_size_read_queue                    [i] = fromString<uint32_t> (getParam("size_read_queue"                   ,"read_bloc",toString(i).c_str(),""));
         _param->_size_reservation_station           [i] = fromString<uint32_t> (getParam("size_reservation_station"          ,"read_bloc",toString(i).c_str(),""));
@@ -154,4 +156,5 @@
     // Write_bloc
     //-----------------------------------------------------
+    ALLOC1(_param->_nb_inst_write     ,uint32_t,_param->_nb_write_bloc);
     ALLOC1(_param->_size_write_queue  ,uint32_t,_param->_nb_write_bloc);
     ALLOC1(_param->_size_execute_queue,uint32_t,_param->_nb_write_bloc);
@@ -163,4 +166,5 @@
       //log_printf(INFO,Configuration,FUNCTION,_("WRITE_BLOC [%d]"),i);
 
+        _param->_nb_inst_write      [i] = fromString<uint32_t> (getParam("nb_inst_write"     ,"write_bloc",toString(i).c_str(),""));
         _param->_size_write_queue   [i] = fromString<uint32_t> (getParam("size_write_queue"  ,"write_bloc",toString(i).c_str(),""));
         _param->_size_execute_queue [i] = fromString<uint32_t> (getParam("size_execute_queue","write_bloc",toString(i).c_str(),""));
@@ -172,12 +176,17 @@
     // load_store_unit
     //-----------------------------------------------------
-    ALLOC1(_param->_size_store_queue             ,uint32_t,_param->_nb_load_store_unit);
-    ALLOC1(_param->_size_load_queue              ,uint32_t,_param->_nb_load_store_unit);
-    ALLOC1(_param->_size_speculative_access_queue,uint32_t,_param->_nb_load_store_unit);
-    ALLOC1(_param->_nb_port_check                ,uint32_t,_param->_nb_load_store_unit);
-    ALLOC1(_param->_nb_bypass_memory             ,uint32_t,_param->_nb_load_store_unit);
-    ALLOC1(_param->_nb_cache_port                ,uint32_t,_param->_nb_load_store_unit);
-    ALLOC1(_param->_nb_inst_memory               ,uint32_t,_param->_nb_load_store_unit);
-    ALLOC1(_param->_speculative_load             ,core::multi_execute_loop::execute_loop::Tspeculative_load_t,_param->_nb_load_store_unit);
+    ALLOC1(_param->_size_store_queue                   ,uint32_t    ,_param->_nb_load_store_unit);
+    ALLOC1(_param->_size_load_queue                    ,uint32_t    ,_param->_nb_load_store_unit);
+    ALLOC1(_param->_size_speculative_access_queue      ,uint32_t    ,_param->_nb_load_store_unit);
+    ALLOC1(_param->_nb_store_queue_bank                ,uint32_t    ,_param->_nb_load_store_unit);
+    ALLOC1(_param->_nb_load_queue_bank                 ,uint32_t    ,_param->_nb_load_store_unit);
+    ALLOC1(_param->_nb_port_check                      ,uint32_t    ,_param->_nb_load_store_unit);
+    ALLOC1(_param->_speculative_load                   ,core::multi_execute_loop::execute_loop::Tspeculative_load_t,_param->_nb_load_store_unit);
+    ALLOC1(_param->_speculative_commit_predictor_scheme,Tpredictor_t,_param->_nb_load_store_unit);
+    ALLOC2(_param->_lsu_pht_size_counter               ,uint32_t    ,_param->_nb_load_store_unit,1);
+    ALLOC2(_param->_lsu_pht_nb_counter                 ,uint32_t    ,_param->_nb_load_store_unit,1);
+    ALLOC1(_param->_nb_bypass_memory                   ,uint32_t    ,_param->_nb_load_store_unit);
+    ALLOC1(_param->_nb_cache_port                      ,uint32_t    ,_param->_nb_load_store_unit);
+    ALLOC1(_param->_nb_inst_memory                     ,uint32_t    ,_param->_nb_load_store_unit);
 
     for (uint32_t i=0; i<_param->_nb_load_store_unit; ++i)
@@ -185,13 +194,35 @@
       //log_printf(INFO,Configuration,FUNCTION,_("LOAD_STORE_UNIT [%d]"),i);
 
-        _param->_size_store_queue              [i] = fromString<uint32_t> (getParam("size_store_queue"             ,"load_store_unit",toString(i).c_str(),""));
-        _param->_size_load_queue               [i] = fromString<uint32_t> (getParam("size_load_queue"              ,"load_store_unit",toString(i).c_str(),""));
-        _param->_size_speculative_access_queue [i] = fromString<uint32_t> (getParam("size_speculative_access_queue","load_store_unit",toString(i).c_str(),""));
-        _param->_nb_port_check                 [i] = fromString<uint32_t> (getParam("nb_port_check"                ,"load_store_unit",toString(i).c_str(),""));
-        _param->_nb_bypass_memory              [i] = fromString<uint32_t> (getParam("nb_bypass_memory"             ,"load_store_unit",toString(i).c_str(),""));
-        _param->_nb_cache_port                 [i] = fromString<uint32_t> (getParam("nb_cache_port"                ,"load_store_unit",toString(i).c_str(),""));
-        _param->_nb_inst_memory                [i] = fromString<uint32_t> (getParam("nb_inst_memory"               ,"load_store_unit",toString(i).c_str(),""));
-
-        _param->_speculative_load [i] = fromString<core::multi_execute_loop::execute_loop::Tspeculative_load_t> (getParam("speculative_load","load_store_unit",toString(i).c_str(),""));
+        _param->_size_store_queue                    [i] = fromString<uint32_t    > (getParam("size_store_queue"                   ,"load_store_unit",toString(i).c_str(),""));
+        _param->_size_load_queue                     [i] = fromString<uint32_t    > (getParam("size_load_queue"                    ,"load_store_unit",toString(i).c_str(),""));
+        _param->_size_speculative_access_queue       [i] = fromString<uint32_t    > (getParam("size_speculative_access_queue"      ,"load_store_unit",toString(i).c_str(),""));
+        _param->_nb_store_queue_bank                 [i] = fromString<uint32_t    > (getParam("nb_store_queue_bank"                ,"load_store_unit",toString(i).c_str(),""));
+        _param->_nb_load_queue_bank                  [i] = fromString<uint32_t    > (getParam("nb_load_queue_bank"                 ,"load_store_unit",toString(i).c_str(),""));
+        _param->_speculative_load                    [i] = fromString<core::multi_execute_loop::execute_loop::Tspeculative_load_t> 
+                                                                                    (getParam("speculative_load"                   ,"load_store_unit",toString(i).c_str(),""));
+        _param->_speculative_commit_predictor_scheme [i] = fromString<Tpredictor_t> 
+                                                                                    (getParam("speculative_commit_predictor_scheme","load_store_unit",toString(i).c_str(),""));
+        _param->_nb_port_check                       [i] = fromString<uint32_t    > (getParam("nb_port_check"                      ,"load_store_unit",toString(i).c_str(),""));
+        
+        // just read !!!
+        try
+          {
+            getParam("nb_predictor","load_store_unit",toString(i).c_str(), "");
+          }
+        catch (morpheo::ErrorMorpheo & error)
+          {
+          }
+
+        const uint32_t max_nb_predictor=1;
+        for (uint32_t j=0; j<max_nb_predictor; ++j)
+          {
+          //log_printf(INFO,Configuration,FUNCTION,_("PREDICTOR [%d][%d]"),i,j);
+        _param->_lsu_pht_size_counter             [i][j] = fromString<uint32_t    > (getParam("lsu_pht_size_counter"               ,"load_store_unit",toString(i).c_str(),"predictor",toString(j).c_str(), ""));
+        _param->_lsu_pht_nb_counter               [i][j] = fromString<uint32_t    > (getParam("lsu_pht_nb_counter"                 ,"load_store_unit",toString(i).c_str(),"predictor",toString(j).c_str(), ""));
+          }
+
+        _param->_nb_bypass_memory                    [i] = fromString<uint32_t    > (getParam("nb_bypass_memory"                   ,"load_store_unit",toString(i).c_str(),""));
+        _param->_nb_cache_port                       [i] = fromString<uint32_t    > (getParam("nb_cache_port"                      ,"load_store_unit",toString(i).c_str(),""));
+        _param->_nb_inst_memory                      [i] = fromString<uint32_t    > (getParam("nb_inst_memory"                     ,"load_store_unit",toString(i).c_str(),""));
       }   
 
@@ -318,5 +349,6 @@
           }
 
-        for (uint32_t j=0; j<3; ++j)
+        const uint32_t max_nb_predictor=3;
+        for (uint32_t j=0; j<max_nb_predictor; ++j)
           {
           //log_printf(INFO,Configuration,FUNCTION,_("PREDICTOR [%d][%d]"),i,j);
@@ -345,4 +377,6 @@
     ALLOC1(_param->_size_re_order_buffer    ,uint32_t         ,_param->_nb_ooo_engine);
     ALLOC1(_param->_nb_re_order_buffer_bank ,uint32_t         ,_param->_nb_ooo_engine);
+    ALLOC1(_param->_retire_ooo_scheme       ,morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Tretire_ooo_scheme_t
+                                                              ,_param->_nb_ooo_engine);
     ALLOC1(_param->_commit_priority         ,Tpriority_t      ,_param->_nb_ooo_engine);
     ALLOC1(_param->_commit_load_balancing   ,Tload_balancing_t,_param->_nb_ooo_engine);
@@ -354,6 +388,4 @@
     ALLOC1(_param->_issue_load_balancing    ,Tload_balancing_t,_param->_nb_ooo_engine);
     ALLOC1(_param->_size_reexecute_queue    ,uint32_t         ,_param->_nb_ooo_engine);
-    ALLOC1(_param->_reexecute_priority      ,Tpriority_t      ,_param->_nb_ooo_engine);
-    ALLOC1(_param->_reexecute_load_balancing,Tload_balancing_t,_param->_nb_ooo_engine);
 
     for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
@@ -370,4 +402,6 @@
         _param->_size_re_order_buffer    [i] = fromString<uint32_t         >(getParam("size_re_order_buffer"    ,"ooo_engine",toString(i).c_str(), ""));
         _param->_nb_re_order_buffer_bank [i] = fromString<uint32_t         >(getParam("nb_re_order_buffer_bank" ,"ooo_engine",toString(i).c_str(), ""));
+        _param->_retire_ooo_scheme       [i] = fromString<morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Tretire_ooo_scheme_t>
+                                                                            (getParam("retire_ooo_scheme"       ,"ooo_engine",toString(i).c_str(), ""));
         _param->_commit_priority         [i] = fromString<Tpriority_t      >(getParam("commit_priority"         ,"ooo_engine",toString(i).c_str(), ""));
         _param->_commit_load_balancing   [i] = fromString<Tload_balancing_t>(getParam("commit_load_balancing"   ,"ooo_engine",toString(i).c_str(), ""));
@@ -379,6 +413,4 @@
         _param->_issue_load_balancing    [i] = fromString<Tload_balancing_t>(getParam("issue_load_balancing"    ,"ooo_engine",toString(i).c_str(), ""));
         _param->_size_reexecute_queue    [i] = fromString<uint32_t         >(getParam("size_reexecute_queue"    ,"ooo_engine",toString(i).c_str(), ""));
-        _param->_reexecute_priority      [i] = fromString<Tpriority_t      >(getParam("reexecute_priority"      ,"ooo_engine",toString(i).c_str(), ""));
-        _param->_reexecute_load_balancing[i] = fromString<Tload_balancing_t>(getParam("reexecute_load_balancing","ooo_engine",toString(i).c_str(), ""));
       }   
 
@@ -434,8 +466,8 @@
     ALLOC1(_param->_link_decod_bloc_with_thread            ,uint32_t ,_param->_nb_thread);
     ALLOC1(_param->_link_rename_bloc_with_front_end        ,uint32_t ,_param->_nb_front_end);
-    ALLOC3(_param->_table_dispatch                         ,bool     ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_nb_read_bloc);
-    ALLOC2(_param->_link_read_bloc_and_load_store_unit     ,bool     ,_param->_nb_read_bloc,_param->_nb_load_store_unit);
+//  ALLOC3(_param->_table_dispatch                         ,bool     ,_param->_nb_ooo_engine,_param->_nb_issue_queue_bank[it1],_param->_nb_read_bloc);
+    ALLOC1(_param->_link_read_bloc_with_load_store_unit    ,uint32_t ,_param->_nb_load_store_unit);
     ALLOC2(_param->_link_read_bloc_and_functionnal_unit    ,bool     ,_param->_nb_read_bloc,_param->_nb_functionnal_unit);
-    ALLOC2(_param->_link_write_bloc_and_load_store_unit    ,bool     ,_param->_nb_write_bloc,_param->_nb_load_store_unit);
+    ALLOC1(_param->_link_write_bloc_with_load_store_unit   ,uint32_t ,_param->_nb_load_store_unit);
     ALLOC2(_param->_link_write_bloc_and_functionnal_unit   ,bool     ,_param->_nb_write_bloc,_param->_nb_functionnal_unit);
     ALLOC1(_param->_link_load_store_unit_with_thread       ,uint32_t ,_param->_nb_thread);
@@ -497,10 +529,13 @@
             _param->_link_read_bloc_and_functionnal_unit [i][j] = fromString<bool>(dest[0]);
           }
-
-        for (uint32_t j=0; j<_param->_nb_load_store_unit; ++j)
-          {
-            getLink_1("link_read_bloc_and_load_store_unit",toString(i).c_str(),toString(j).c_str(), "");
-            _param->_link_read_bloc_and_load_store_unit [i][j] = fromString<bool>(dest[0]);
-          }
+      }
+
+    for (uint32_t i=0; i<_param->_nb_load_store_unit; ++i)
+      {
+        getLink_1("link_read_bloc_with_load_store_unit",toString(i).c_str(), "");
+        _param->_link_read_bloc_with_load_store_unit [i] = fromString<uint32_t>(dest[0]);
+
+        getLink_1("link_write_bloc_with_load_store_unit",toString(i).c_str(), "");
+        _param->_link_write_bloc_with_load_store_unit [i] = fromString<uint32_t>(dest[0]);
       }
 
@@ -516,10 +551,4 @@
             _param->_link_write_bloc_and_functionnal_unit [i][j] = fromString<bool>(dest[0]);
           }
-
-        for (uint32_t j=0; j<_param->_nb_load_store_unit; ++j)
-          {
-            getLink_1("link_write_bloc_and_load_store_unit",toString(i).c_str(),toString(j).c_str(), "");
-            _param->_link_write_bloc_and_load_store_unit [i][j] = fromString<bool>(dest[0]);
-          }
       }
 
@@ -550,11 +579,11 @@
       }
 
-    for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
-      for (uint32_t j=0; j<_param->_nb_inst_issue[i]; ++j)
-        for (uint32_t k=0; k<_param->_nb_read_bloc; ++k)
-          {
-            getLink_1("table_dispatch",toString(i).c_str(),toString(j).c_str(),toString(k).c_str(),"");
-            _param->_table_dispatch [i][j][k] = fromString<bool>(dest[0]);
-          }
+    // for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
+    //   for (uint32_t j=0; j<_param->_nb_issue_queue_bank[i]; ++j)
+    //     for (uint32_t k=0; k<_param->_nb_read_bloc; ++k)
+    //       {
+    //         getLink_1("table_dispatch",toString(i).c_str(),toString(j).c_str(),toString(k).c_str(),"");
+    //         _param->_table_dispatch [i][j][k] = fromString<bool>(dest[0]);
+    //       }
 
     test_use ();
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Parameters.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Parameters.h	(revision 138)
@@ -34,5 +34,5 @@
   public : uint32_t              * _nb_inst_reexecute                    ;//[nb_ooo_engine]
   public : uint32_t              * _nb_inst_issue_queue                  ;//[nb_ooo_engine]
-  public : uint32_t              * _nb_inst_issue_slot                   ;//[nb_ooo_engine]
+//public : uint32_t              * _nb_inst_issue_slot                   ;//[nb_ooo_engine]
   public : uint32_t             ** _nb_inst_execute                      ;//[nb_ooo_engine][ooo_engine_nb_execute_loop]
   public : bool                  * _issue_queue_in_order                 ;//[nb_ooo_engine]
@@ -52,9 +52,12 @@
   public : Tpriority_t             _dispatch_priority                    ;
   public : Tload_balancing_t       _dispatch_load_balancing              ;
-  public : bool               **** _table_dispatch                       ;//[nb_ooo_engine][nb_inst_issue_slot][execute_loop][nb_read_unit]
+//public : bool               **** _table_dispatch                       ;//[nb_ooo_engine][nb_inst_issue_slot][execute_loop][nb_read_unit]
   public : bool                *** _table_issue_type                     ;//                                   [execute_loop][nb_read_unit][nb_type]
+  public : bool                *** _table_issue_thread                   ;//                                   [execute_loop][nb_read_unit][nb_thread]
+
   public : uint32_t             ** _translate_ooo_engine_num_front_end   ;//[nb_ooo_engine][ooo_engine_nb_front_end]
   public : uint32_t             ** _translate_ooo_engine_num_execute_loop;//[nb_ooo_engine][ooo_engine_nb_execute_loop]
   public : uint32_t             ** _translate_execute_loop_num_ooo_engine;//[nb_execute_loop][execute_loop_nb_ooo_engine]
+  public : uint32_t            *** _translate_num_context_to_num_thread  ;//[nb_ooo_engine][ooo_engine_nb_front_end][nb_context]
 
   public : uint32_t              * _link_ooo_engine_with_front_end                          ;//[nb_front_end]
@@ -65,5 +68,5 @@
 
 //public : uint32_t             ** _execute_loop_nb_inst_insert                             ;//[nb_execute_loop][execute_loop_nb_ooo_engine]
-  public : uint32_t             ** _execute_loop_nb_inst_issue_slot                         ;//[nb_execute_loop][execute_loop_nb_ooo_engine]
+//public : uint32_t             ** _execute_loop_nb_inst_issue_slot                         ;//[nb_execute_loop][execute_loop_nb_ooo_engine]
 //public : uint32_t              * _link_execute_loop_with_ooo_engine                       ;//[nb_ooo_engine]
 
@@ -75,5 +78,5 @@
 //public : uint32_t                _max_nb_inst_insert                    ;
   public : uint32_t                _max_nb_inst_issue_queue               ;
-  public : uint32_t                _max_nb_inst_issue_slot                ;
+//public : uint32_t                _max_nb_inst_issue_slot                ;
   public : uint32_t                _max_nb_read_unit                      ;
 
@@ -90,8 +93,8 @@
    uint32_t              * front_end_nb_inst_branch_complete    ,//[nb_front_end]
    uint32_t              * ooo_engine_nb_inst_branch_complete   ,//[nb_ooo_engine]
-//    uint32_t              * nb_inst_insert                       ,//[nb_ooo_engine]
+// uint32_t              * nb_inst_insert                       ,//[nb_ooo_engine]
    uint32_t              * nb_inst_reexecute                    ,//[nb_ooo_engine]
    uint32_t              * nb_inst_issue_queue                  ,//[nb_ooo_engine]
-   uint32_t              * nb_inst_issue_slot                   ,//[nb_ooo_engine]
+// uint32_t              * nb_inst_issue_slot                   ,//[nb_ooo_engine]
    uint32_t             ** nb_inst_execute                      ,//[nb_ooo_engine][ooo_engine_nb_execute_loop]
    bool                  * issue_queue_in_order                 ,//[nb_ooo_engine]
@@ -108,10 +111,12 @@
    Tpriority_t             dispatch_priority                    ,
    Tload_balancing_t       dispatch_load_balancing              ,
-   bool               **** table_dispatch                       ,//[nb_ooo_engine][nb_inst_issue_slot][execute_loop][nb_read_unit]
+// bool               **** table_dispatch                       ,//[nb_ooo_engine][nb_inst_issue_slot][execute_loop][nb_read_unit]
    bool                *** table_issue_type                     ,//                                   [execute_loop][nb_read_unit][nb_type]
-// bool                *** table_issue_thread                   ,//                                   [execute_loop][nb_read_unit][nb_thread]
+   bool                *** table_issue_thread                   ,//                                   [execute_loop][nb_read_unit][nb_thread]
    uint32_t             ** translate_ooo_engine_num_front_end   ,//[nb_ooo_engine][ooo_engine_nb_front_end]
    uint32_t             ** translate_ooo_engine_num_execute_loop,//[nb_ooo_engine][ooo_engine_nb_execute_loop]
    uint32_t             ** translate_execute_loop_num_ooo_engine,//[nb_execute_loop][execute_loop_nb_ooo_engine]
+   uint32_t            *** translate_num_context_to_num_thread  ,//[nb_ooo_engine][ooo_engine_nb_front_end][nb_context]
+
    bool                    is_toplevel=false);
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_issue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_issue.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_issue.cpp	(revision 138)
@@ -16,28 +16,28 @@
 
   /*
-      OOO        SLOT     Execute Loop                                  
-    ---+                      +-----
-       |  +-----+     +-----+ |     
-      -+->|     |     |     |-+->   
-       |  |     |-()->|     | |     
-      -+->| _ _ |     |     |-+->   
-       |  | _X_ |-()->|     | |     
-      -+->|     |     |     | +-----
-       |  |     |-()->|     |       
-      -+->|     |     |     | +-----
-       |  +-----+     |     | |     
-    ---+  crossbar    | _ _ |-+->   
-                      | _X_ | |     
-    ---+              |     |-+->   
-       |  +-----+     |     | |     
-      -+->|     |     |     | +-----
-       |  |     |-()->|     |       
-      -+->| _ _ |     |     | +-----
-       |  | _X_ |-()->|     | |     
-      -+->|     |     |     |-+->   
-       |  |     |-()->|     | |     
-      -+->|     |     |     |-+->   
-       |  +-----+     +-----+ |     
-    ---+  crossbar   dispatch +-----
+      OOO     Execute Loop                                  
+    ---+          +-----
+       |  +-----+ |     
+      -+->|     |-+->   
+       |  |     | |     
+      -+->|     |-+->   
+       |  |     | |     
+      -+->|     | +-----
+       |  |     |       
+      -+->|     | +-----
+       |  |     | |     
+    ---+  | _ _ |-+->   
+          | _X_ | |     
+    ---+  |     |-+->   
+       |  |     | |     
+      -+->|     | +-----
+       |  |     |       
+      -+->|     | +-----
+       |  |     | |     
+      -+->|     |-+->   
+       |  |     | |     
+      -+->|     |-+->   
+       |  +-----+ |     
+    ---+ dispatch +-----
   */
 
@@ -75,11 +75,6 @@
       {
     Tcontrol_t READ_UNIT_ENABLE       [_param->_nb_execute_loop][_param->_max_nb_read_unit];
-    Tcontrol_t SLOT_ENABLE            [_param->_nb_ooo_engine  ][_param->_max_nb_inst_issue_slot];
     
     // Init -> all at 0
-    for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
-      for (uint32_t j=0; j<_param->_nb_inst_issue_slot[i]; ++j)
-        SLOT_ENABLE [i][j] = 1;         
-
     for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
       for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j)
@@ -90,39 +85,4 @@
         }
 
-//     std::list<num_read_unit_t> SLOT_TYPE [_param->_nb_ooo_engine][_param->_max_nb_inst_issue_slot][_param->_nb_type];
-
-//     // for each read_unit
-//     for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
-//       for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j)
-//         // test if this read_unit can receive an instruction
-//         if (PORT_READ(in_ISSUE_EXECUTE_LOOP_ACK [i][j]) == 1)
-//           for (uint32_t x=0; x<_nb_ooo_engine; ++x)
-//             for (uint32_t y=0; y<_nb_inst_issue_slot[y]; ++y)
-//               // test if can dispatch
-//               if (_param->_table_dispatch [x][y][i][j])
-//                 for (uint32_t k=0;k<_param->_nb_type; ++k)
-//                   // Can receive this type
-//                   if (_param->_table_dispatch [i][j][k])
-//                     SLOT_TYPE[x][y][k].push_back(num_read_unit_t(i,j));
-
-//     // Select an issue_slot of an ooo_engine
-//     std::list<generic::priority::select_t> * select_ooo_engine = _priority_ooo_engine->select();
-//     for (std::list<generic::priority::select_t>::iterator it_ooo_engine=select_ooo_engine->begin();
-//          it_ooo_engine!=select_ooo_engine->end();
-//          ++it_ooo_engine)
-//       { 
-//         // ... get id of the most priotary
-//         const uint32_t num_ooo_engine      = it_ooo_engine->grp;
-//         const uint32_t num_inst_issue_slot = it_ooo_engine->elt;
-
-//         // Test if this ooo_engine is enable (can be desable if issue in_order)
-//         if (OOO_ENGINE_ENABLE[num_ooo_engine])
-//           {
-
-//           }
-//       }
-
-//     for (uint32_t num_ooo_engine=0; num_ooo_engine<_param->_nb_ooo_engine; ++num_ooo_engine)
-
     std::list<generic::priority::select_t> * select_ooo_engine = _priority_ooo_engine->select();
     for (std::list<generic::priority::select_t>::iterator it_ooo_engine=select_ooo_engine->begin();
@@ -130,100 +90,98 @@
          ++it_ooo_engine)
       {
-        uint32_t num_ooo_engine      = it_ooo_engine->grp;
+        // select the most priotary 
+        uint32_t num_ooo_engine = it_ooo_engine->grp;
 
         for (uint32_t num_inst_issue_queue=0; num_inst_issue_queue<_param->_nb_inst_issue_queue[num_ooo_engine]; ++num_inst_issue_queue)
           {
+            // init stop condition
             bool find = false;
             
-            Tcontrol_t val  = PORT_READ(in_ISSUE_OOO_ENGINE_VAL  [num_ooo_engine][num_inst_issue_queue]);
-            Ttype_t    type = PORT_READ(in_ISSUE_OOO_ENGINE_TYPE [num_ooo_engine][num_inst_issue_queue]);
+            // Read request information from issue_queue
+            Tcontrol_t val          = PORT_READ(in_ISSUE_OOO_ENGINE_VAL  [num_ooo_engine][num_inst_issue_queue]);
+            Ttype_t    type         = PORT_READ(in_ISSUE_OOO_ENGINE_TYPE [num_ooo_engine][num_inst_issue_queue]);
+            Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_ISSUE_OOO_ENGINE_CONTEXT_ID   [num_ooo_engine][num_inst_issue_queue]):0;
+            Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_ISSUE_OOO_ENGINE_FRONT_END_ID [num_ooo_engine][num_inst_issue_queue]):0;
+            uint32_t   num_thread    = _param->_translate_num_context_to_num_thread[num_ooo_engine][front_end_id][context_id];
             
             log_printf(TRACE,Core_Glue,FUNCTION,"  * num_ooo_engine                : %d",num_ooo_engine      );
             log_printf(TRACE,Core_Glue,FUNCTION,"  * num_inst_issue_queue          : %d",num_inst_issue_queue);
             log_printf(TRACE,Core_Glue,FUNCTION,"    * val                         : %d",val);
-            log_printf(TRACE,Core_Glue,FUNCTION,"    * type                        : %d",type);
-            
+            log_printf(TRACE,Core_Glue,FUNCTION,"    * type                        : %d",type);  
+            log_printf(TRACE,Core_Glue,FUNCTION,"    * context_id                  : %d",context_id);
+            log_printf(TRACE,Core_Glue,FUNCTION,"    * front_end_id                : %d",front_end_id);
+            log_printf(TRACE,Core_Glue,FUNCTION,"    * num_thread                  : %d",num_thread);
+          
             if (val)
-              for (uint32_t num_inst_issue_slot=0; num_inst_issue_slot<_param->_nb_inst_issue_slot[num_ooo_engine]; ++num_inst_issue_slot)
+              // for each execute_loop
+              for (uint32_t num_execute_loop=0; num_execute_loop<_param->_nb_execute_loop; ++num_execute_loop)
                 {
-                  log_printf(TRACE,Core_Glue,FUNCTION,"    * num_inst_issue_slot         : %d",num_inst_issue_slot);
-                  
-                  // scan all read_unit
-                  
-                  if (SLOT_ENABLE [num_ooo_engine][num_inst_issue_slot])
-                    for (uint32_t num_execute_loop=0; num_execute_loop<_param->_nb_execute_loop; ++num_execute_loop)
-                      {
-                        std::list<generic::priority::select_t> * select_read_unit = _priority_read_unit[num_execute_loop]->select();
-                        for (std::list<generic::priority::select_t>::iterator it_read_unit=select_read_unit->begin();
-                             it_read_unit!=select_read_unit->end();
-                             ++it_read_unit)
-                          {
-                            // get the most priotary ...
-                            uint32_t num_read_unit = it_read_unit->grp;
-                            Tcontrol_t ack = READ_UNIT_ENABLE [num_execute_loop][num_read_unit];
-                            
-                            log_printf(TRACE,Core_Glue,FUNCTION,"      * num_execute_loop          : %d",num_execute_loop);
-                            log_printf(TRACE,Core_Glue,FUNCTION,"      * num_read_unit             : %d",num_read_unit   );
-                            log_printf(TRACE,Core_Glue,FUNCTION,"        * read_unit_enable        : %d",ack             );
-                            
-                            // test if :
-                            //  * read_unit can accept an instruction (valid and no previous instruction)
-                            //  * slot can issue an instruction at this read_unit
-                            //  * read_unit can accept this type
-                            if (ack and
-                                _param->_table_dispatch [num_ooo_engine][num_inst_issue_slot][num_execute_loop][num_read_unit] and
-                                _param->_table_issue_type [num_execute_loop][num_read_unit][type])
-                              {
-                                log_printf(TRACE,Core_Glue,FUNCTION,"  * find !!!");
-                                
-                                // find !
-                                // Transaction
-                                READ_UNIT_ENABLE       [num_execute_loop][num_read_unit] = false; // now, this read_unit is busy
-                                ISSUE_EXECUTE_LOOP_VAL [num_execute_loop][num_read_unit] = 1; // = val
-                                ISSUE_OOO_ENGINE_ACK   [num_ooo_engine][num_inst_issue_queue] = 1; // = ack
-                                SLOT_ENABLE            [num_ooo_engine][num_inst_issue_slot]  = false; // now this slot is used
-                                      
-                                if (_param->_have_port_context_id)
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_CONTEXT_ID            [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_CONTEXT_ID            [num_ooo_engine][num_inst_issue_queue]));
-			        if (_param->_have_port_front_end_id)
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_FRONT_END_ID          [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_FRONT_END_ID          [num_ooo_engine][num_inst_issue_queue]));
-			        if (_param->_have_port_ooo_engine_id)
-                                  {
-                                Tcontext_t ooo_engine_id = _param->_translate_num_ooo_engine_to_execute_loop_ooo_engine_id [num_ooo_engine][num_execute_loop];
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID         [num_execute_loop][num_read_unit],ooo_engine_id);
-                                  }
-			        if (_param->_have_port_rob_ptr)
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_PACKET_ID             [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_PACKET_ID             [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OPERATION             [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_OPERATION             [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_TYPE                  [num_execute_loop][num_read_unit],type);
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_CANCEL                [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_CANCEL                [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_READ  [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ  [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_EMPTY     [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY     [num_ooo_engine][num_inst_issue_queue]));
-			        if (_param->_have_port_load_queue_ptr)
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE  [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE  [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT          [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT          [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_IMMEDIAT              [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_IMMEDIAT              [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RA               [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RA               [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RA            [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RA            [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RB               [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RB               [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RB            [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RB            [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RC               [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RC               [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RC            [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RC            [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RD              [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RD              [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RD            [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RD            [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RE              [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RE              [num_ooo_engine][num_inst_issue_queue]));
-			        PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RE            [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RE            [num_ooo_engine][num_inst_issue_queue]));
-                              
-                                
-                                find = true;
-                                break;
-                              }
-                            //if (find)
-                            //  break;
-                          }
-                        if (find)
+                  // for each read_unit
+                  std::list<generic::priority::select_t> * select_read_unit = _priority_read_unit[num_execute_loop]->select();
+                  for (std::list<generic::priority::select_t>::iterator it_read_unit=select_read_unit->begin();
+                       it_read_unit!=select_read_unit->end();
+                       ++it_read_unit)
+                    {
+                      // get the most priotary ...
+                      uint32_t num_read_unit = it_read_unit->grp;
+                      Tcontrol_t ack = READ_UNIT_ENABLE [num_execute_loop][num_read_unit];
+                      
+                      log_printf(TRACE,Core_Glue,FUNCTION,"      * num_execute_loop          : %d",num_execute_loop);
+                      log_printf(TRACE,Core_Glue,FUNCTION,"      * num_read_unit             : %d",num_read_unit   );
+                      log_printf(TRACE,Core_Glue,FUNCTION,"        * read_unit_enable        : %d",ack             );
+                      
+                      // test if :
+                      //  * read_unit can accept an instruction (valid and no previous instruction)
+                      //  * read_unit can accept this type
+                      if (ack and
+                          _param->_table_issue_type   [num_execute_loop][num_read_unit][type] and
+                          _param->_table_issue_thread [num_execute_loop][num_read_unit][num_thread])
+                        {
+                          log_printf(TRACE,Core_Glue,FUNCTION,"  * find !!!");
+                          
+                          // find !
+                          // Transaction
+                          find = true;
+
+                          READ_UNIT_ENABLE       [num_execute_loop][num_read_unit] = false; // now, this read_unit is busy
+                          ISSUE_EXECUTE_LOOP_VAL [num_execute_loop][num_read_unit] = 1; // = val
+                          ISSUE_OOO_ENGINE_ACK   [num_ooo_engine][num_inst_issue_queue] = 1; // = ack
+                          
+                          if (_param->_have_port_context_id)
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_CONTEXT_ID            [num_execute_loop][num_read_unit],context_id);
+                          if (_param->_have_port_front_end_id)
+			  PORT_WRITE(out_ISSUE_EXECUTE_LOOP_FRONT_END_ID          [num_execute_loop][num_read_unit],front_end_id);
+                          if (_param->_have_port_ooo_engine_id)
+                            {
+                          Tcontext_t ooo_engine_id = _param->_translate_num_ooo_engine_to_execute_loop_ooo_engine_id [num_ooo_engine][num_execute_loop];
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID         [num_execute_loop][num_read_unit],ooo_engine_id);
+                            }
+                          if (_param->_have_port_rob_ptr)
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_PACKET_ID             [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_PACKET_ID             [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OPERATION             [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_OPERATION             [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_TYPE                  [num_execute_loop][num_read_unit],type);
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_CANCEL                [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_CANCEL                [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_READ  [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_READ  [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_EMPTY     [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_EMPTY     [num_ooo_engine][num_inst_issue_queue]));
+                          if (_param->_have_port_load_queue_ptr)
+			  PORT_WRITE(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE  [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE  [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT          [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT          [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_IMMEDIAT              [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_IMMEDIAT              [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RA               [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RA               [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RA            [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RA            [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RB               [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RB               [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RB            [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RB            [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RC               [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RC               [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RC            [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RC            [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RD              [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RD              [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RD            [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RD            [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RE              [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RE              [num_ooo_engine][num_inst_issue_queue]));
+                          PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RE            [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RE            [num_ooo_engine][num_inst_issue_queue]));
                           break;
-                      }
+                        }
+                      //if (find)
+                      //  break;
+                    }
                   if (find)
                     break;
@@ -240,5 +198,5 @@
           }
       }
-
+    
       }
 
@@ -260,151 +218,2 @@
 }; // end namespace morpheo              
 #endif
-
-    /*
-    bool       OOO_ENGINE_ENABLE      [_param->_nb_ooo_engine  ];
-    Tcontrol_t SLOT_ENABLE            [_param->_nb_ooo_engine  ][_param->_max_nb_inst_issue_slot];
-    bool       READ_UNIT_ENABLE       [_param->_nb_execute_loop][_param->_max_nb_read_unit];
-
-    // Init -> all at 0
-    for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
-      {
-        OOO_ENGINE_ENABLE [i] = true;
-
-        for (uint32_t j=0; j<_param->_nb_inst_issue_slot[i]; ++j)
-          SLOT_ENABLE [i][j] = 1;         
-      }
-
-    for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
-      for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j)
-        {
-          // Read unit is enable is signal ack is set
-          READ_UNIT_ENABLE       [i][j] = (PORT_READ(in_ISSUE_EXECUTE_LOOP_ACK [i][j]) == 1);
-	  log_printf(TRACE,Core_Glue,FUNCTION,"  * Read_unit [%d][%d].enable : %d",i,j,READ_UNIT_ENABLE[i][j]);
-        }
-
-
-    // for each execute_loop
-    for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
-      {
-        // Scan all read_unit
-        std::list<generic::priority::select_t> * select_read_unit = _priority_read_unit[i]->select();
-        for (std::list<generic::priority::select_t>::iterator it_read_unit=select_read_unit->begin();
-             it_read_unit!=select_read_unit->end();
-             ++it_read_unit)
-          {
-            // get the most priotary ...
-            uint32_t num_read_unit = it_read_unit->grp;
-            
-            log_printf(TRACE,Core_Glue,FUNCTION,"  * read_unit [%d][%d]",i,num_read_unit);
-
-            // ... and test if this read_unit is valid
-            if (READ_UNIT_ENABLE [i][num_read_unit])
-              {
-                bool find = false;
-                
-                // This read_unit is valid, now find an valid instruction
-                // for each issue of each ooo_engine ...
-                std::list<generic::priority::select_t> * select_ooo_engine = _priority_ooo_engine[i]->select();
-                for (std::list<generic::priority::select_t>::iterator it_ooo_engine=select_ooo_engine->begin();
-                     it_ooo_engine!=select_ooo_engine->end();
-                     ++it_ooo_engine)
-                  { 
-                    // ... get id of the most priotary
-                    const uint32_t ooo_engine_id       = it_ooo_engine->grp;
-                    const uint32_t num_ooo_engine      = _param->_translate_execute_loop_num_ooo_engine [i][ooo_engine_id];
-                    const uint32_t num_inst_issue_slot = it_ooo_engine->elt;
-                    
-                    log_printf(TRACE,Core_Glue,FUNCTION,"    * num_ooo_engine [%d (%d)][%d]",num_ooo_engine, ooo_engine_id,num_inst_issue_slot);
-                    
-                    if (OOO_ENGINE_ENABLE [num_ooo_engine] and SLOT_ENABLE [num_ooo_engine][num_inst_issue_slot])
-                      {
-                        uint32_t num_inst_issue_queue = 0;
-                        for (; num_inst_issue_queue < _param->_nb_inst_issue_queue [num_ooo_engine]; num_inst_issue_queue ++)
-                          {
-                            // Test if this instruction is not previously send at a read_unit
-                            if (not ISSUE_OOO_ENGINE_ACK [num_ooo_engine][num_inst_issue_queue])
-                              {
-                                Tcontrol_t ooo_engine_val = PORT_READ(in_ISSUE_OOO_ENGINE_VAL  [num_ooo_engine][num_inst_issue_queue]);
-                                Ttype_t    type           = PORT_READ(in_ISSUE_OOO_ENGINE_TYPE [num_ooo_engine][num_inst_issue_queue]);
-                                // Test if have an link and read unit is enable
-                                bool can_dispatch   = _param->_table_dispatch [num_ooo_engine][num_inst_issue_slot][i][num_read_unit];
-                                bool can_issue_type = _param->_table_issue_type [i][num_read_unit][type];
-                                
-                                log_printf(TRACE,Core_Glue,FUNCTION,"      * num_ooo_engine_queue  : %d",num_inst_issue_queue);
-                                log_printf(TRACE,Core_Glue,FUNCTION,"      * type                  : %s",toString(type).c_str());
-                                log_printf(TRACE,Core_Glue,FUNCTION,"      * ISSUE_OOO_ENGINE_VAL  : %d",ooo_engine_val);
-                                log_printf(TRACE,Core_Glue,FUNCTION,"      * table_dispatch        : %d",can_dispatch);
-                                log_printf(TRACE,Core_Glue,FUNCTION,"      * table_issue_type      : %d",can_issue_type);
-                                
-                                
-                                // test if have a request ?
-                                // and test if have a link between the issue slot and read_unit 
-                                // and if the read_unit accept this instruction's type
-                                if (ooo_engine_val and 
-                                    can_dispatch   and
-                                    can_issue_type)
-                                  {
-//                                     log_printf(TRACE,Core_Glue,FUNCTION,"          * find !!!");
-                                    
-                                    // Transaction
-                                    READ_UNIT_ENABLE       [i][num_read_unit] = false; // now, this read_unit is busy
-                                    ISSUE_EXECUTE_LOOP_VAL [i][num_read_unit] = ooo_engine_val;
-                                    ISSUE_OOO_ENGINE_ACK   [num_ooo_engine][num_inst_issue_queue] = 1;
-                                    SLOT_ENABLE            [num_ooo_engine][num_inst_issue_slot]  = 0; // now this slot is used
-                                      
-			            if (_param->_have_port_context_id)
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_CONTEXT_ID            [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_CONTEXT_ID            [num_ooo_engine][num_inst_issue_queue]));
-			            if (_param->_have_port_front_end_id)
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_FRONT_END_ID          [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_FRONT_END_ID          [num_ooo_engine][num_inst_issue_queue]));
-			            if (_param->_have_port_ooo_engine_id)
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID         [i][num_read_unit],ooo_engine_id);
-			            if (_param->_have_port_rob_ptr)
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_PACKET_ID             [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_PACKET_ID             [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OPERATION             [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_OPERATION             [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_TYPE                  [i][num_read_unit],type);
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE [num_ooo_engine][num_inst_issue_queue]));
-			            if (_param->_have_port_load_queue_ptr)
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE  [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE  [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT          [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT          [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_IMMEDIAT              [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_IMMEDIAT              [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RA               [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RA               [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RA            [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RA            [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RB               [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RB               [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RB            [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RB            [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RC               [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RC               [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RC            [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RC            [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RD              [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RD              [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RD            [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RD            [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RE              [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RE              [num_ooo_engine][num_inst_issue_queue]));
-			            PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RE            [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RE            [num_ooo_engine][num_inst_issue_queue]));
-                                    
-                                    find = true;// find : stop scan read_unit
-                                  }
-                              }
-                            if (find)
-                              break;
-                          }
-
-                        if (find)
-                          {
-                            log_printf(TRACE,Core_Glue,FUNCTION,"    * find !!!");
-                            break;
-                          }
-                        else
-                          {
-                            log_printf(TRACE,Core_Glue,FUNCTION,"    * not find !!!");
-                            log_printf(TRACE,Core_Glue,FUNCTION,"      * issue_queue_in_order: %d",_param->_issue_queue_in_order [num_ooo_engine]);
-                            log_printf(TRACE,Core_Glue,FUNCTION,"      * num_inst_issue_queue: %d",num_inst_issue_queue);
-                            log_printf(TRACE,Core_Glue,FUNCTION,"      * nb_inst_reexecute   : %d",_param->_nb_inst_reexecute [num_ooo_engine]);
-
-                            if (_param->_issue_queue_in_order [num_ooo_engine] and
-                                (num_inst_issue_queue >= _param->_nb_inst_reexecute [num_ooo_engine]))
-                                OOO_ENGINE_ENABLE [num_ooo_engine] = false;
-                          }
-                      }
-                  }
-              }
-          }
-      }
-    */ 
-
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters.cpp	(revision 138)
@@ -32,5 +32,5 @@
    uint32_t              * nb_inst_reexecute                    ,//[nb_ooo_engine]
    uint32_t              * nb_inst_issue_queue                  ,//[nb_ooo_engine]
-   uint32_t              * nb_inst_issue_slot                   ,//[nb_ooo_engine]
+// uint32_t              * nb_inst_issue_slot                   ,//[nb_ooo_engine]
    uint32_t             ** nb_inst_execute                      ,//[nb_ooo_engine][ooo_engine_nb_execute_loop]
    bool                  * issue_queue_in_order                 ,//[nb_ooo_engine]
@@ -47,9 +47,11 @@
    Tpriority_t             dispatch_priority                    ,
    Tload_balancing_t       dispatch_load_balancing              ,
-   bool               **** table_dispatch                       ,//[nb_ooo_engine][nb_inst_issue_slot][execute_loop][nb_read_unit]
+// bool               **** table_dispatch                       ,//[nb_ooo_engine][nb_inst_issue_slot][execute_loop][nb_read_unit]
    bool                *** table_issue_type                     ,//                                   [execute_loop][nb_read_unit][nb_type]
+   bool                *** table_issue_thread                   ,//                                   [execute_loop][nb_read_unit][nb_thread]
    uint32_t             ** translate_ooo_engine_num_front_end   ,//[nb_ooo_engine][ooo_engine_nb_front_end]
    uint32_t             ** translate_ooo_engine_num_execute_loop,//[nb_ooo_engine][ooo_engine_nb_execute_loop]
    uint32_t             ** translate_execute_loop_num_ooo_engine,//[nb_execute_loop][execute_loop_nb_ooo_engine]
+   uint32_t            *** translate_num_context_to_num_thread  ,//[nb_ooo_engine][ooo_engine_nb_front_end][nb_context]
    bool                    is_toplevel)
   {
@@ -69,5 +71,5 @@
     _nb_inst_reexecute                     = nb_inst_reexecute                    ;
     _nb_inst_issue_queue                   = nb_inst_issue_queue                  ;
-    _nb_inst_issue_slot                    = nb_inst_issue_slot                   ;
+//  _nb_inst_issue_slot                    = nb_inst_issue_slot                   ;
     _nb_inst_execute                       = nb_inst_execute                      ;
     _issue_queue_in_order                  = issue_queue_in_order                 ;
@@ -76,9 +78,11 @@
     _dispatch_priority                     = dispatch_priority                    ;
     _dispatch_load_balancing               = dispatch_load_balancing              ;
-    _table_dispatch                        = table_dispatch                       ;
+//  _table_dispatch                        = table_dispatch                       ;
     _table_issue_type                      = table_issue_type                     ;
+    _table_issue_thread                    = table_issue_thread                   ;
     _translate_ooo_engine_num_front_end    = translate_ooo_engine_num_front_end   ;
     _translate_ooo_engine_num_execute_loop = translate_ooo_engine_num_execute_loop;
     _translate_execute_loop_num_ooo_engine = translate_execute_loop_num_ooo_engine;
+    _translate_num_context_to_num_thread   = translate_num_context_to_num_thread  ;
 
     test();
@@ -118,13 +122,13 @@
 
 //  ALLOC2(_execute_loop_nb_inst_insert,uint32_t,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]);
-    ALLOC2(_execute_loop_nb_inst_issue_slot ,uint32_t,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]);
-
-    for (uint32_t i=0; i<_nb_execute_loop; ++i)
-      for (uint32_t j=0; j<_execute_loop_nb_ooo_engine[i]; ++j)
-        {
-          uint32_t num_ooo_engine = _translate_execute_loop_num_ooo_engine [i][j];
-          _execute_loop_nb_inst_issue_slot [i][j] = _nb_inst_issue_slot [num_ooo_engine];
-//        _execute_loop_nb_inst_insert     [i][j] = _nb_inst_insert     [num_ooo_engine];
-        }
+//  ALLOC2(_execute_loop_nb_inst_issue_slot ,uint32_t,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]);
+
+//     for (uint32_t i=0; i<_nb_execute_loop; ++i)
+//       for (uint32_t j=0; j<_execute_loop_nb_ooo_engine[i]; ++j)
+//         {
+//           uint32_t num_ooo_engine = _translate_execute_loop_num_ooo_engine [i][j];
+//           _execute_loop_nb_inst_issue_slot [i][j] = _nb_inst_issue_slot [num_ooo_engine];
+//           _execute_loop_nb_inst_insert     [i][j] = _nb_inst_insert     [num_ooo_engine];
+//         }
 
     _max_ooo_engine_nb_inst_branch_complete = max<uint32_t>(_ooo_engine_nb_inst_branch_complete,_nb_ooo_engine);
@@ -135,5 +139,5 @@
 //  _max_nb_inst_insert                     = max<uint32_t>(_nb_inst_insert            ,_nb_ooo_engine);
     _max_nb_inst_issue_queue                = max<uint32_t>(_nb_inst_issue_queue       ,_nb_ooo_engine);
-    _max_nb_inst_issue_slot                 = max<uint32_t>(_nb_inst_issue_slot        ,_nb_ooo_engine);
+//  _max_nb_inst_issue_slot                 = max<uint32_t>(_nb_inst_issue_slot        ,_nb_ooo_engine);
     _max_nb_read_unit                       = max<uint32_t>(_nb_read_unit              ,_nb_execute_loop);
 
@@ -188,5 +192,5 @@
     log_begin(Core_Glue,FUNCTION);
 
-    DELETE2(_execute_loop_nb_inst_issue_slot                         ,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]);
+//  DELETE2(_execute_loop_nb_inst_issue_slot                         ,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]);
 //  DELETE2(_execute_loop_nb_inst_insert                             ,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]);
     DELETE2(_translate_num_ooo_engine_to_execute_loop_ooo_engine_id  ,_nb_ooo_engine,_nb_execute_loop);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters_msg_error.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters_msg_error.cpp	(revision 138)
@@ -8,4 +8,5 @@
 #include "Behavioural/include/Types.h"
 #include "Behavioural/Core/Core_Glue/include/Parameters.h"
+#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Types.h"
 #include <sstream>
 
@@ -58,4 +59,25 @@
         }
 
+    {
+      bool issue_queue_can_ooo [_nb_ooo_engine];
+      for (uint32_t i=0; i<_nb_ooo_engine; ++i)
+        issue_queue_can_ooo [i] = true;
+
+      for (uint32_t i=0; i<_nb_execute_loop; ++i)
+        for (uint32_t j=0; j<_execute_loop_nb_ooo_engine[i]; ++j)
+          {
+            Tcontext_t num_ooo_engine = _translate_execute_loop_num_ooo_engine [i][j];
+            
+            // Test if multiple ooo_engine for this execute loop
+            if (_execute_loop_nb_ooo_engine[i]>1)
+              issue_queue_can_ooo [num_ooo_engine] = false;
+          }
+
+      for (uint32_t i=0; i<_nb_ooo_engine; ++i)
+        if (not _issue_queue_in_order [i] and // out of order
+            not issue_queue_can_ooo [i])
+          test.error(toString(_("The scheme of Issue queue in ooo_engine [%d] must be \"%s\" because, the execute loop can be access with multiple ooo_engine (deadlock is possible).\n"),i,toString(core::multi_ooo_engine::ooo_engine::issue_queue::ISSUE_QUEUE_SCHEME_IN_ORDER).c_str()));
+    }
+
     if (_dispatch_load_balancing != LOAD_BALANCING_MAXIMUM_FOR_PRIORITY)
       test.error(toString(_("distpatch load_balancing scheme \"%s\" is not yet supported.\n"),toString(_dispatch_load_balancing).c_str()));
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 138)
@@ -181,4 +181,5 @@
     // Registers
   public    : Tlsq_ptr_t                    * reg_STORE_QUEUE_NB_CHECK     ;//[size_store_queue]
+//public    : Tcontrol_t                    * reg_STORE_QUEUE_INVALID      ;//[size_store_queue]
   public    : Tlsq_ptr_t                      reg_STORE_QUEUE_PTR_READ     ;
 //public    : Tlsq_ptr_t                      reg_LOAD_QUEUE_PTR_READ      ;
@@ -236,9 +237,9 @@
   public  : void     genMealy_retire           (void);
    
-  public  : void     function_speculative_load_commit_transition      (void);
-  public  : void     function_speculative_load_commit_genMoore        (void);
-  public  : void     function_speculative_load_commit_genMealy_dcache (void);
-  public  : void     function_speculative_load_commit_genMealy_insert (void);
-  public  : void     function_speculative_load_commit_genMealy_retire (void);
+  public  : void     function_speculative_load_access_transition      (void);
+  public  : void     function_speculative_load_access_genMoore        (void);
+  public  : void     function_speculative_load_access_genMealy_dcache (void);
+  public  : void     function_speculative_load_access_genMealy_insert (void);
+  public  : void     function_speculative_load_access_genMealy_retire (void);
 #endif					       
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h	(revision 138)
@@ -27,22 +27,27 @@
   {
     //-----[ fields ]------------------------------------------------------------
-  public : uint32_t            _size_store_queue             ;
-  public : uint32_t            _size_load_queue              ;
-  public : uint32_t            _size_speculative_access_queue;
-  public : uint32_t            _nb_port_check                ;
-  public : Tspeculative_load_t _speculative_load             ;
-  public : uint32_t            _nb_bypass_memory             ;
-  public : uint32_t            _nb_cache_port                ;
-  public : uint32_t            _nb_inst_memory               ;
-  public : uint32_t            _nb_context                   ;
-  public : uint32_t            _nb_front_end                 ;
-  public : uint32_t            _nb_ooo_engine                ;
-  public : uint32_t            _nb_packet                    ;
-//public : uint32_t            _size_general_data            ;
-//public : uint32_t            _size_special_data            ;
-  public : uint32_t            _nb_general_register          ;
-  public : uint32_t            _nb_special_register          ;
-  public : uint32_t            _nb_thread                    ;
-  public : bool              * _num_thread_valid             ; //[nb_thread]
+  public : uint32_t            _size_store_queue                   ;
+  public : uint32_t            _size_load_queue                    ;
+  public : uint32_t            _size_speculative_access_queue      ;
+  public : uint32_t            _nb_store_queue_bank                ;
+  public : uint32_t            _nb_load_queue_bank                 ;
+  public : uint32_t            _nb_port_check                      ;
+  public : Tspeculative_load_t _speculative_load                   ;
+  public : Tpredictor_t        _speculative_commit_predictor_scheme;
+  public : uint32_t          * _lsu_pht_size_counter               ;//[1]
+  public : uint32_t          * _lsu_pht_nb_counter                 ;//[1]
+  public : uint32_t            _nb_bypass_memory                   ;
+  public : uint32_t            _nb_cache_port                      ;
+  public : uint32_t            _nb_inst_memory                     ;
+  public : uint32_t            _nb_context                         ;
+  public : uint32_t            _nb_front_end                       ;
+  public : uint32_t            _nb_ooo_engine                      ;
+  public : uint32_t            _nb_packet                          ;
+//public : uint32_t            _size_general_data                  ;
+//public : uint32_t            _size_special_data                  ;
+  public : uint32_t            _nb_general_register                ;
+  public : uint32_t            _nb_special_register                ;
+  public : uint32_t            _nb_thread                          ;
+  public : bool              * _num_thread_valid                   ; //[nb_thread]
 
 //public : uint32_t            _size_address_store_queue             ;
@@ -70,22 +75,27 @@
 
     //-----[ methods ]-----------------------------------------------------------
-  public : Parameters  (uint32_t            size_store_queue       ,
-			uint32_t            size_load_queue        ,
-			uint32_t            size_speculative_access_queue,
-			uint32_t            nb_port_check          ,
-			Tspeculative_load_t speculative_load       ,
-			uint32_t            nb_bypass_memory       ,
-			uint32_t            nb_cache_port          ,
-			uint32_t            nb_inst_memory         ,
-			uint32_t            nb_context             ,
-			uint32_t            nb_front_end           ,
-			uint32_t            nb_ooo_engine          ,
-			uint32_t            nb_packet              ,
-			uint32_t            size_general_data      ,
-			uint32_t            size_special_data      ,
-			uint32_t            nb_general_register    ,
-			uint32_t            nb_special_register    ,
-                        uint32_t            nb_thread              ,
-                        bool              * num_thread_valid       , //[nb_thread]
+  public : Parameters  (uint32_t            size_store_queue                   ,
+			uint32_t            size_load_queue                    ,
+			uint32_t            size_speculative_access_queue      ,
+                        uint32_t            nb_store_queue_bank                ,
+                        uint32_t            nb_load_queue_bank                 ,
+                        uint32_t            nb_port_check                      ,
+                        Tspeculative_load_t speculative_load                   ,
+                        Tpredictor_t        speculative_commit_predictor_scheme,
+                        uint32_t          * lsu_pht_size_counter               ,//[1]
+                        uint32_t          * lsu_pht_nb_counter                 ,//[1]
+			uint32_t            nb_bypass_memory                   ,
+			uint32_t            nb_cache_port                      ,
+			uint32_t            nb_inst_memory                     ,
+			uint32_t            nb_context                         ,
+			uint32_t            nb_front_end                       ,
+			uint32_t            nb_ooo_engine                      ,
+			uint32_t            nb_packet                          ,
+			uint32_t            size_general_data                  ,
+			uint32_t            size_special_data                  ,
+			uint32_t            nb_general_register                ,
+			uint32_t            nb_special_register                ,
+                        uint32_t            nb_thread                          ,
+                        bool              * num_thread_valid                   , //[nb_thread]
                         bool                is_toplevel=false);
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h	(revision 138)
@@ -35,5 +35,5 @@
        NO_SPECULATIVE_LOAD     //each load wait all previous store before the data cache access
       ,SPECULATIVE_LOAD_ACCESS //each load wait all previous store before the commiting
-      ,SPECULATIVE_LOAD_COMMIT //each load commit the result before the end of dependence's check
+    //,SPECULATIVE_LOAD_COMMIT //each load commit the result before the end of dependence's check
     //,SPECULATIVE_LOAD_BYPASS //each load bypass the result before the end of dependence's check
     } Tspeculative_load_t; 
@@ -184,4 +184,5 @@
   public    : Tgeneral_address_t   _num_reg_rd       ;
   public    : Texception_t         _exception        ;
+  public    : Tcontrol_t           _can_speculative_commit;
 
     friend std::ostream & operator << (std::ostream& os, const Tload_queue_entry_t & x)
@@ -194,4 +195,5 @@
 		<< "   * exception                         : " << toString(x._exception) << std::endl
 		<< "   * check_hit, check_hit_byte         : " << toString(x._check_hit) << " - " << toString(x._check_hit_byte) << std::endl
+		<< "   * can_speculative_commit            : " << toString(x._can_speculative_commit) << std::endl
 		<< std::hex
 		<< "   * address                           : " << toString(x._address)<< std::endl
@@ -217,6 +219,6 @@
       case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD     : return "no_speculative_load"    ; break;
       case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS : return "speculative_load_access"; break;
-      case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT : return "speculative_load_commit"; break;
-//       case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS : return "speculative_load_bypass"; break;
+//    case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT : return "speculative_load_commit"; break;
+//    case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS : return "speculative_load_bypass"; break;
       default    : return ""      ; break;
       }
@@ -225,16 +227,16 @@
   template<> inline morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tspeculative_load_t fromString<morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tspeculative_load_t>(const std::string& x)
   {
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD    ))) == 0) or
-         (x.compare("no_speculative_load")     == 0))
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD    ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD     )) == 0))
       return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS))) == 0) or
-         (x.compare("speculative_load_access") == 0))
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS )) == 0))
       return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT))) == 0) or
-         (x.compare("speculative_load_commit") == 0))
-      return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT;
-//     if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS)))) or
-//          (x.compare("speculative_load_bypass") == 0))
-//       return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS;
+//  if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT))) == 0) or
+//      (x.compare(toString(                      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT )) == 0))
+//    return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT;
+//  if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS))) == 0) or
+//      (x.compare(toString(                      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS )) == 0))
+//    return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS;
     
     throw (ErrorMorpheo ("<fromString> : Unknow string : \""+x+"\""));
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp	(revision 138)
@@ -77,16 +77,16 @@
     switch (_param->_speculative_load)
       {
-      case SPECULATIVE_LOAD_COMMIT :
+      case SPECULATIVE_LOAD_ACCESS :
 	{
-	  function_transition      = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_transition     ;
-	  function_genMoore        = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_genMoore       ;
-	  function_genMealy_dcache = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_genMealy_dcache;
-	  function_genMealy_insert = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_genMealy_insert;
-	  function_genMealy_retire = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_genMealy_retire;
+	  function_transition      = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_transition     ;
+	  function_genMoore        = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_genMoore       ;
+	  function_genMealy_dcache = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_genMealy_dcache;
+	  function_genMealy_insert = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_genMealy_insert;
+	  function_genMealy_retire = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_genMealy_retire;
 	  break;
 	}
       case NO_SPECULATIVE_LOAD     :
-      case SPECULATIVE_LOAD_ACCESS :
-	//case SPECULATIVE_LOAD_BYPASS :
+      // case SPECULATIVE_LOAD_COMMIT :
+      //case SPECULATIVE_LOAD_BYPASS :
       default                      :
 	{
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 138)
@@ -160,4 +160,5 @@
 
         ALLOC1(reg_STORE_QUEUE_NB_CHECK                  ,Tlsq_ptr_t     ,_param->_size_store_queue);
+//      ALLOC1(reg_STORE_QUEUE_INVALID                   ,Tcontrol_t     ,_param->_size_store_queue);
 
 //      ALLOC1(internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ,Tlsq_ptr_t     ,_param->_nb_cache_port);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 138)
@@ -106,4 +106,5 @@
 
     DELETE1(reg_STORE_QUEUE_NB_CHECK                  ,_param->_size_store_queue);
+//  DELETE1(reg_STORE_QUEUE_INVALID                   ,_param->_size_store_queue);
 
 //  DELETE1(internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ,_param->_nb_cache_port);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_dcache.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_dcache.cpp	(revision 138)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_dcache.cpp	(revision 138)
@@ -0,0 +1,40 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_access_genMealy_dcache"
+  void Load_store_unit::function_speculative_load_access_genMealy_dcache (void)
+  {
+    log_begin(Load_store_unit,FUNCTION);
+    log_end  (Load_store_unit,FUNCTION);
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_insert.cpp	(revision 138)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_insert.cpp	(revision 138)
@@ -0,0 +1,76 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_access_genMealy_insert"
+  void Load_store_unit::function_speculative_load_access_genMealy_insert (void)
+  {
+    log_begin(Load_store_unit,FUNCTION);
+    log_function(Load_store_unit,FUNCTION,_name.c_str());
+
+    // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    
+    // Initialisation
+    internal_MEMORY_IN_PORT = 0;
+    Tcontrol_t ack [_param->_nb_inst_memory];
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      ack [i] = 0;
+
+    if (PORT_READ(in_NRESET))
+      {
+    // find first valid entry
+    // store queue is never full (pointer is manage by rename stage)
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      if (PORT_READ(in_MEMORY_IN_VAL [i]))
+	{
+	  internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION [i])) or not _speculative_access_queue_control->full();
+
+	  if (internal_MEMORY_IN_ACK)
+	    {
+	      ack [i] = 1;
+	      internal_MEMORY_IN_PORT = i;
+	      break; // end
+	    }
+	}
+      }
+    else
+      {
+        internal_MEMORY_IN_ACK = 0;
+//         internal_MEMORY_IN_PORT = i;
+      }
+
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      PORT_WRITE(out_MEMORY_IN_ACK [i], ack [i]);
+
+    log_end(Load_store_unit,FUNCTION);
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_retire.cpp	(revision 138)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_retire.cpp	(revision 138)
@@ -0,0 +1,40 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_access_genMealy_retire"
+  void Load_store_unit::function_speculative_load_access_genMealy_retire (void)
+  {
+    log_begin(Load_store_unit,FUNCTION);
+    log_end  (Load_store_unit,FUNCTION);
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMoore.cpp	(revision 138)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMoore.cpp	(revision 138)
@@ -0,0 +1,284 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_access_genMoore"
+  void Load_store_unit::function_speculative_load_access_genMoore (void)
+  {
+    log_begin(Load_store_unit,FUNCTION);
+    log_function(Load_store_unit,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET))
+      {
+    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+    Tcontext_t         memory_out_context_id    = 0;
+    Tcontext_t         memory_out_front_end_id  = 0;
+    Tcontext_t         memory_out_ooo_engine_id = 0;
+    Tpacket_t          memory_out_packet_id     = 0;
+    Tcontrol_t         memory_out_cancel        = 0;
+    Tcontrol_t         memory_out_write_rd      = 0;
+    Tgeneral_address_t memory_out_num_reg_rd    = 0;
+    Tgeneral_data_t    memory_out_data_rd       = 0;
+//  Tcontrol_t         memory_out_write_re      = 0;
+//  Tspecial_address_t memory_out_num_reg_re    = 0;
+//  Tspecial_data_t    memory_out_data_re       = 0;
+    Tcontrol_t         memory_out_no_sequence   = 0;
+    Texception_t       memory_out_exception     = 0;
+
+    internal_MEMORY_OUT_VAL = 0;
+
+    // Test store and load queue
+
+    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test MEMORY_OUT");
+
+    log_printf(TRACE,Load_store_unit,FUNCTION,"    * Load  queue");
+    for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++)
+//     for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++)
+      {
+// 	internal_MEMORY_OUT_PTR = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
+	internal_MEMORY_OUT_VAL = ((_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK) or
+				   (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT));
+	
+	if (internal_MEMORY_OUT_VAL)
+	  {
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
+	    internal_MEMORY_OUT_SELECT_QUEUE = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?SELECT_LOAD_QUEUE_SPECULATIVE:SELECT_LOAD_QUEUE;
+	    
+	    memory_out_context_id    = _load_queue [internal_MEMORY_OUT_PTR]._context_id;
+	    memory_out_front_end_id  = _load_queue [internal_MEMORY_OUT_PTR]._front_end_id;
+	    memory_out_ooo_engine_id = _load_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
+	    memory_out_packet_id     = _load_queue [internal_MEMORY_OUT_PTR]._packet_id ;
+	    memory_out_cancel        = _load_queue [internal_MEMORY_OUT_PTR]._cancel    ;
+	    memory_out_write_rd      = _load_queue [internal_MEMORY_OUT_PTR]._write_rd  ;
+	    memory_out_num_reg_rd    = _load_queue [internal_MEMORY_OUT_PTR]._num_reg_rd;
+
+	    Tdcache_data_t data_old = _load_queue [internal_MEMORY_OUT_PTR]._rdata;
+	    Tdcache_data_t data_new = extend<Tdcache_data_t>(_param->_size_general_data,
+							     data_old >> _load_queue [internal_MEMORY_OUT_PTR]._shift,
+							     _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed,
+							     _load_queue [internal_MEMORY_OUT_PTR]._access_size);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (old) : %.8x",data_old);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (new) : %.8x",data_new);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * address      : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._address);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * rdata        : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * shift        : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * signed?      : %d",_load_queue [internal_MEMORY_OUT_PTR]._is_load_signed);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * access_size  : %d",_load_queue [internal_MEMORY_OUT_PTR]._access_size);
+
+	    Texception_t exception      = _load_queue [internal_MEMORY_OUT_PTR]._exception;
+	    bool         have_exception = ((exception != EXCEPTION_MEMORY_NONE) and
+					   (exception != EXCEPTION_MEMORY_MISS_SPECULATION));
+
+	    // if exception, rdata content the address of load, else content read data.
+	    memory_out_data_rd       = (have_exception)?data_old:data_new;
+	    memory_out_exception     = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?EXCEPTION_MEMORY_LOAD_SPECULATIVE:exception;
+
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",exception);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",memory_out_exception);
+
+	    break; // we have find a entry !!! stop the search
+	  }
+      }
+
+    if (not internal_MEMORY_OUT_VAL)
+      {
+	log_printf(TRACE,Load_store_unit,FUNCTION,"    * Store queue");
+
+	for (uint32_t i=0; i<_param->_size_store_queue; ++i)
+	  {
+	    internal_MEMORY_OUT_PTR = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
+	    // Can retire an store instruction if :
+	    //  * state is commit
+	    //  * none load must check this store
+
+
+	    bool val_head = ((i==0) and
+			     (_store_queue [internal_MEMORY_OUT_PTR]._state       == STORE_QUEUE_COMMIT) and
+			     (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == true) and
+			     (reg_STORE_QUEUE_NB_CHECK [internal_MEMORY_OUT_PTR] == 0)
+			     );
+
+	    bool val_commit = ((_store_queue [internal_MEMORY_OUT_PTR]._state       != STORE_QUEUE_EMPTY) and
+			       (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == false));
+
+	    if (val_head or val_commit)
+	      {
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
+		
+		internal_MEMORY_OUT_VAL          = 1;
+		internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
+		
+		memory_out_context_id    = _store_queue [internal_MEMORY_OUT_PTR]._context_id;
+		memory_out_front_end_id  = _store_queue [internal_MEMORY_OUT_PTR]._front_end_id;
+		memory_out_ooo_engine_id = _store_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
+		memory_out_packet_id     = _store_queue [internal_MEMORY_OUT_PTR]._packet_id ;
+		memory_out_cancel        = _store_queue [internal_MEMORY_OUT_PTR]._cancel;
+//              memory_out_write_rd  	 
+//              memory_out_num_reg_rd	 
+		memory_out_data_rd       = _store_queue [internal_MEMORY_OUT_PTR]._address; // to the exception
+		memory_out_exception     = _store_queue [internal_MEMORY_OUT_PTR]._exception;
+		memory_out_no_sequence   = val_commit;
+		break; // find an entry
+	      }
+
+	  }
+      }
+
+    // write output
+    if (_param->_have_port_context_id)
+    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   [0], memory_out_context_id   );
+    if (_param->_have_port_front_end_id)
+    PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id );
+    if (_param->_have_port_ooo_engine_id)
+    PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id);
+    if (_param->_have_port_rob_ptr)
+    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    [0], memory_out_packet_id    );
+//  PORT_WRITE(out_MEMORY_OUT_OPERATION    [0], memory_out_operation    );
+//  PORT_WRITE(out_MEMORY_OUT_TYPE         [0], TYPE_MEMORY             );
+    PORT_WRITE(out_MEMORY_OUT_CANCEL       [0], memory_out_cancel       );
+    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     [0], memory_out_write_rd     );
+    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   [0], memory_out_num_reg_rd   );
+    PORT_WRITE(out_MEMORY_OUT_DATA_RD      [0], memory_out_data_rd      );
+//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], memory_out_write_re     );
+//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], memory_out_num_reg_re   );
+//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], memory_out_data_re      );
+    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    [0], memory_out_exception    );
+    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  [0], memory_out_no_sequence  );// hack
+#ifdef DEBUG
+    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], memory_out_data_rd);
+#else
+    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], 0);
+#endif
+
+    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+    Tcontext_t        dcache_req_context_id = 0;
+    Tpacket_t         dcache_req_packet_id  = 0;
+    Tdcache_address_t dcache_req_address    = 0;
+    Tdcache_type_t    dcache_req_type       = 0;
+    Tdcache_data_t    dcache_req_wdata      = 0;
+
+    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test DCACHE_REQ");
+
+    internal_DCACHE_REQ_VAL = 0;
+
+    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = (*_speculative_access_queue_control)[0];
+
+    // Test store and load queue
+    if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE)
+      {
+	log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);
+
+	internal_DCACHE_REQ_VAL          = 1;
+	internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
+
+	if (_param->_have_port_dcache_context_id)
+	  {
+	    Tcontext_t context_id    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
+	    Tcontext_t front_end_id  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
+	    Tcontext_t ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
+	    
+	    dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
+				     (front_end_id <<(_param->_size_context_id)) |
+				     (context_id));
+	  }
+
+	dcache_req_packet_id  = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write);
+	dcache_req_address    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb;
+	dcache_req_type       = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation);
+
+// 	log_printf(TRACE,Load_store_unit,FUNCTION,"      * address            : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address);
+//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * mask               : %.8x",_param->_mask_address_msb);
+        log_printf(TRACE,Load_store_unit,FUNCTION,"      * dcache_req_address : %.8x",dcache_req_address);
+
+#ifdef SYSTEMC_VHDL_COMPATIBILITY
+	dcache_req_wdata      = 0;
+#endif
+      }
+    else
+      {
+	// Test an store must be commited.
+	if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE)
+	  {
+	    internal_DCACHE_REQ_VAL          = 1;
+	    internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE;
+	    
+	    if (_param->_have_port_dcache_context_id)
+	      {
+		Tcontext_t context_id    = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id;
+		Tcontext_t front_end_id  = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id;
+		Tcontext_t ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id;
+		
+		dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
+					 (front_end_id <<(_param->_size_context_id)) |
+					 (context_id));
+	      }
+
+	    // FIXME : il peut avoir plusieurs store avec le même paquet_id ... pour l'instant pas très grave car pas de retour (enfin seul les bus error sont des retours)
+	    dcache_req_packet_id  = DCACHE_REQ_IS_STORE(reg_STORE_QUEUE_PTR_READ);
+	    dcache_req_address    = _store_queue [reg_STORE_QUEUE_PTR_READ]._address;
+	    dcache_req_type       = operation_to_dcache_type(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation);
+	    dcache_req_wdata      = _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata;
+	  }
+      }
+
+    if (_param->_have_port_dcache_context_id)
+    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id);
+    PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id );
+    PORT_WRITE(out_DCACHE_REQ_ADDRESS   [0], dcache_req_address   );
+    PORT_WRITE(out_DCACHE_REQ_TYPE      [0], dcache_req_type      );
+    PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
+      }
+    else
+      {
+        // Reset
+    internal_MEMORY_OUT_VAL = 0;
+//  internal_MEMORY_OUT_PTR =0
+//  internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
+
+    internal_DCACHE_REQ_VAL = 0;
+    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = 0;
+//  internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
+      }
+
+    // Write output
+    PORT_WRITE(out_MEMORY_OUT_VAL [0], internal_MEMORY_OUT_VAL);
+    PORT_WRITE(out_DCACHE_REQ_VAL [0], internal_DCACHE_REQ_VAL);
+
+
+    log_end(Load_store_unit,FUNCTION);
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_transition.cpp	(revision 138)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_transition.cpp	(revision 138)
@@ -0,0 +1,1424 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+#include "Behavioural/include/Identification.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+template <typename T>
+T swapBytes (T data, uint32_t size_data, uint32_t size_access)
+{
+  uint64_t x = static_cast<uint64_t>(data);
+
+//   switch (size_data)
+//     {
+//     case 2 : // 16 bits
+//       {
+//         switch (size_access)
+//           {
+//           case 2 : 
+//             {
+//               x = ((((x>> 8)&0xff) <<  0) |
+//                    (((x>> 0)&0xff) <<  8) );
+//               break;
+//             }
+//           default :
+//             {
+//               break;
+//             }
+//           }
+//         break;
+//       }
+//     case 4 : // 32 bits
+//       {
+//         switch (size_access)
+//           {
+//           case 2 : 
+//             {
+//               x = ((((x>> 8)&0xff) <<  0) |
+//                    (((x>> 0)&0xff) <<  8) |
+//                    (((x>>24)&0xff) << 16) |
+//                    (((x>>16)&0xff) << 24) );
+//               break;
+//             }
+//           case 4 : 
+//             {
+//               x = ((((x>>24)&0xff) <<  0) |
+//                    (((x>>16)&0xff) <<  8) |
+//                    (((x>> 8)&0xff) << 16) |
+//                    (((x>> 0)&0xff) << 24) );
+//               break;
+//             }
+//           default :
+//             {
+//               break;
+//             }
+//           }
+//         break;
+//       }
+//     case 8 : // 64 bits
+//       {
+//         switch (size_access)
+//           {
+//           case 2 : 
+//             {
+//               x = ((((x>> 8)&0xff) <<  0) |
+//                    (((x>> 0)&0xff) <<  8) |
+//                    (((x>>24)&0xff) << 16) |
+//                    (((x>>16)&0xff) << 24) |
+//                    (((x>>40)&0xff) << 32) |
+//                    (((x>>32)&0xff) << 40) |
+//                    (((x>>56)&0xff) << 48) |
+//                    (((x>>48)&0xff) << 56) );
+//               break;
+//             }
+//           case 4 : 
+//             {
+//               x = ((((x>>24)&0xff) <<  0) |
+//                    (((x>>16)&0xff) <<  8) |
+//                    (((x>> 8)&0xff) << 16) |
+//                    (((x>> 0)&0xff) << 24) |
+//                    (((x>>56)&0xff) << 32) |
+//                    (((x>>48)&0xff) << 40) |
+//                    (((x>>40)&0xff) << 48) |
+//                    (((x>>32)&0xff) << 56) );
+//               break;
+//             }
+//           case 8 : 
+//             {
+//               x = ((((x>>56)&0xff) <<  0) |
+//                    (((x>>48)&0xff) <<  8) |
+//                    (((x>>40)&0xff) << 16) |
+//                    (((x>>32)&0xff) << 24) |
+//                    (((x>>24)&0xff) << 32) |
+//                    (((x>>16)&0xff) << 40) |
+//                    (((x>> 8)&0xff) << 48) |
+//                    (((x>> 0)&0xff) << 56) );
+//               break;
+//             }
+//           default :
+//             {
+//               break;
+//             }
+//           }
+//         break;
+//       }
+//     default :
+//       {
+//         break;
+//       }
+//     }
+
+
+  uint64_t y=0;
+
+  for (uint32_t i=0; i<size_data; i+=size_access)
+    {
+      uint32_t offset = i<<3;
+
+      switch (size_access)
+        {
+        case 1 :
+          {
+            y = x;
+            break;
+          }
+        case 2 : 
+          {
+            y |= ((((x>>( 8+offset))&0xff) << ( 0+offset)) |
+                  (((x>>( 0+offset))&0xff) << ( 8+offset)) );
+            break;
+          }
+        case 4 : 
+          {
+            y |= ((((x>>(24+offset))&0xff) << ( 0+offset)) |
+                  (((x>>(16+offset))&0xff) << ( 8+offset)) |
+                  (((x>>( 8+offset))&0xff) << (16+offset)) |
+                  (((x>>( 0+offset))&0xff) << (24+offset)) );
+            break;
+          }
+        case 8 : 
+          {
+            y |= ((((x>>(56+offset))&0xff) << ( 0+offset)) |
+                  (((x>>(48+offset))&0xff) << ( 8+offset)) |
+                  (((x>>(40+offset))&0xff) << (16+offset)) |
+                  (((x>>(32+offset))&0xff) << (24+offset)) |
+                  (((x>>(24+offset))&0xff) << (32+offset)) |
+                  (((x>>(16+offset))&0xff) << (40+offset)) |
+                  (((x>>( 8+offset))&0xff) << (48+offset)) |
+                  (((x>>( 0+offset))&0xff) << (56+offset)) );
+            break;
+          }
+        default :
+            {
+              break;
+            }
+        }
+    }
+
+  return static_cast<T>(y);
+}
+
+template <typename T>
+T swapBits (T data, uint32_t size_data, uint32_t size_access)
+{
+  uint8_t x = static_cast<uint8_t>(data);
+
+  uint8_t y=0;
+
+  for (uint32_t i=0; i<size_data; i+=size_access)
+    {
+      uint32_t offset = i;
+
+      switch (size_access)
+        {
+        case 1 :
+          {
+            y = x;
+            break;
+          }
+        case 2 : 
+          {
+            y |= ((((x>>( 1+offset))&0x1) << ( 0+offset)) |
+                  (((x>>( 0+offset))&0x1) << ( 1+offset)) );
+            break;
+          }
+        case 4 : 
+          {
+            y |= ((((x>>( 3+offset))&0x1) << ( 0+offset)) |
+                  (((x>>( 2+offset))&0x1) << ( 1+offset)) |
+                  (((x>>( 1+offset))&0x1) << ( 2+offset)) |
+                  (((x>>( 0+offset))&0x1) << ( 3+offset)) );
+            break;
+          }
+        case 8 : 
+          {
+            y |= ((((x>>( 7+offset))&0x1) << ( 0+offset)) |
+                  (((x>>( 6+offset))&0x1) << ( 1+offset)) |
+                  (((x>>( 5+offset))&0x1) << ( 2+offset)) |
+                  (((x>>( 4+offset))&0x1) << ( 3+offset)) |
+                  (((x>>( 3+offset))&0x1) << ( 4+offset)) |
+                  (((x>>( 2+offset))&0x1) << ( 5+offset)) |
+                  (((x>>( 1+offset))&0x1) << ( 6+offset)) |
+                  (((x>>( 0+offset))&0x1) << ( 7+offset)) );
+            break;
+          }
+        default :
+            {
+              break;
+            }
+        }
+    }
+
+  return static_cast<T>(y);
+}
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_access_transition"
+  void Load_store_unit::function_speculative_load_access_transition (void)
+  {
+    log_begin(Load_store_unit,FUNCTION);
+    log_function(Load_store_unit,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET) == 0)
+      {
+	// Reset : clear all queue
+	_speculative_access_queue_control->clear();
+
+	reg_STORE_QUEUE_PTR_READ       = 0;
+	reg_LOAD_QUEUE_CHECK_PRIORITY  = 0;
+
+	for (uint32_t i=0; i< _param->_size_store_queue             ; i++)
+          {
+            reg_STORE_QUEUE_NB_CHECK  [i] = 0;
+//          reg_STORE_QUEUE_INVALID   [i] = 0;
+  	    _store_queue              [i]._state                 = STORE_QUEUE_EMPTY;
+  	    _store_queue              [i]._context_id            = 0; // not necessary
+  	    _store_queue              [i]._front_end_id          = 0; // not necessary
+  	    _store_queue              [i]._ooo_engine_id         = 0; // not necessary
+  	    _store_queue              [i]._packet_id             = 0; // not necessary
+  	    _store_queue              [i]._operation             = 0; // not necessary
+  	    _store_queue              [i]._cancel                = 0; // not necessary
+  	    _store_queue              [i]._load_queue_ptr_write  = 0; // not necessary
+  	    _store_queue              [i]._address               = 0; // not necessary
+  	    _store_queue              [i]._wdata                 = 0; // not necessary
+//	    _store_queue              [i]._write_rd              = 0; // not necessary
+//	    _store_queue              [i]._num_reg_rd            = 0; // not necessary
+  	    _store_queue              [i]._exception             = 0; // not necessary
+  	    _store_queue              [i]._send_commit           = 0; // not necessary
+          }
+
+	for (uint32_t i=0; i< _param->_size_load_queue              ; i++)
+          {
+            _load_queue               [i]._state                 = LOAD_QUEUE_EMPTY;
+            _load_queue               [i]._context_id            = 0; // not necessary
+            _load_queue               [i]._front_end_id          = 0; // not necessary
+            _load_queue               [i]._ooo_engine_id         = 0; // not necessary
+            _load_queue               [i]._packet_id             = 0; // not necessary
+            _load_queue               [i]._operation             = 0; // not necessary
+            _load_queue               [i]._cancel                = 0; // not necessary
+            _load_queue               [i]._store_queue_ptr_write = 0; // not necessary
+            _load_queue               [i]._store_queue_ptr_read  = 0; // not necessary
+            _load_queue               [i]._store_queue_empty     = 0; // not necessary
+            _load_queue               [i]._address               = 0; // not necessary
+            _load_queue               [i]._check_hit_byte        = 0; // not necessary 
+            _load_queue               [i]._check_hit             = 0; // not necessary
+            _load_queue               [i]._shift                 = 0; // not necessary
+            _load_queue               [i]._is_load_signed        = 0; // not necessary
+            _load_queue               [i]._access_size           = 0; // not necessary
+            _load_queue               [i]._rdata                 = 0; // not necessary
+            _load_queue               [i]._write_rd              = 0; // not necessary
+            _load_queue               [i]._num_reg_rd            = 0; // not necessary
+            _load_queue               [i]._exception             = 0; // not necessary
+            _load_queue               [i]._can_speculative_commit= 0; // not necessary
+          }
+
+	for (uint32_t i=0; i< _param->_size_speculative_access_queue; i++)
+          {
+            _speculative_access_queue [i]._state                 = SPECULATIVE_ACCESS_QUEUE_EMPTY;
+            _speculative_access_queue [i]._context_id            = 0; // not necessary
+            _speculative_access_queue [i]._front_end_id          = 0; // not necessary
+            _speculative_access_queue [i]._ooo_engine_id         = 0; // not necessary
+            _speculative_access_queue [i]._packet_id             = 0; // not necessary
+            _speculative_access_queue [i]._operation             = 0; // not necessary
+            _speculative_access_queue [i]._cancel                = 0; // not necessary
+            _speculative_access_queue [i]._load_queue_ptr_write  = 0; // not necessary
+            _speculative_access_queue [i]._store_queue_ptr_write = 0; // not necessary
+            _speculative_access_queue [i]._store_queue_ptr_read  = 0; // not necessary
+            _speculative_access_queue [i]._store_queue_empty     = 0; // not necessary
+            _speculative_access_queue [i]._address               = 0; // not necessary
+            _speculative_access_queue [i]._write_rd              = 0; // not necessary
+            _speculative_access_queue [i]._num_reg_rd            = 0; // not necessary
+            _speculative_access_queue [i]._exception             = 0; // not necessary
+          }
+      }
+    else
+      {
+        // load_queue_push if speculative_access_queue have access at the dcache, or they have an event
+	bool load_queue_push = (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE);
+
+	//================================================================
+	// Interface "MEMORY_OUT"
+	//================================================================
+
+        if ((    internal_MEMORY_OUT_VAL  == 1) and
+            (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1))
+          {
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_OUT[0] transaction");
+
+	    switch (internal_MEMORY_OUT_SELECT_QUEUE)
+	      {
+	      case SELECT_STORE_QUEUE :
+		{
+		  // =======================
+		  // ===== STORE_QUEUE =====
+		  // =======================
+		  
+		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue [%d]",internal_MEMORY_OUT_PTR);
+	    
+		  // Entry flush and increase the read pointer
+		  if (_store_queue [internal_MEMORY_OUT_PTR]._send_commit)
+		    {
+		      _store_queue [internal_MEMORY_OUT_PTR]._state = STORE_QUEUE_EMPTY;
+		      reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue;
+		    }
+		  else
+		    _store_queue [internal_MEMORY_OUT_PTR]._send_commit = true;
+
+		  break;
+		}
+	      case SELECT_LOAD_QUEUE :
+		{
+		  // ======================
+		  // ===== LOAD_QUEUE =====
+		  // ======================
+		  
+		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * load_queue  [%d]",internal_MEMORY_OUT_PTR);
+		  
+		  // Entry flush and increase the read pointer
+		  
+		  _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY;
+		  
+		  // reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
+
+		  break;
+		}
+	      case SELECT_LOAD_QUEUE_SPECULATIVE :
+		{
+		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * load_queue  [%d] (speculative)",internal_MEMORY_OUT_PTR);
+		  
+                  // !!! WARNING !!!
+                  // !!! Test special case :
+                  // !!! in a cycle an instruction can check the last store AND commit instruction
+                  // !!! also the memory_out is before the port_check
+
+		  _load_queue [internal_MEMORY_OUT_PTR]._state    = LOAD_QUEUE_CHECK;
+		  // NOTE : a speculative load write in the register file.
+		  // if the speculation is a miss, write_rd is re set at 1.
+		  _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0;
+
+#ifdef STATISTICS
+                  if (usage_is_set(_usage,USE_STATISTICS))
+                    (*_stat_nb_inst_load_commit_speculative) ++;
+#endif
+
+		  break;
+		}
+
+		break;
+	      }
+	  }
+
+	//================================================================
+	// Interface "PORT_CHECK"
+	//================================================================
+	
+	// Plusieurs moyens de faire la verification de dépendance entre les loads et les stores.
+	//  1) un load ne peut vérifier qu'un store par cycle. Dans ce cas port_check <= size_load_queue
+	//  2) un load tente de vérifier le maximum de store par cycle. Dans ce cas ce n'est pas du pointeur d'écriture qu'il lui faut mais un vecteur de bit indiquant quel store à déjà été testé. De plus il faut un bit indiquant qu'il y a un match mais que ce n'est pas forcément le premier.
+
+	// solution 1)
+ 	log_printf(TRACE,Load_store_unit,FUNCTION,"  * CHECK");
+	for (uint32_t i=0, nb_check=0; (nb_check<_param->_nb_port_check) and (i<_param->_size_load_queue); i++)
+	  {
+            // Get an index from load queue
+	    uint32_t index_load_queue = (i + reg_LOAD_QUEUE_CHECK_PRIORITY)%_param->_size_load_queue;
+
+            // Test if this load must ckecked store queue
+	    if (((_load_queue[index_load_queue]._state == LOAD_QUEUE_WAIT_CHECK) or
+		 (_load_queue[index_load_queue]._state == LOAD_QUEUE_COMMIT_CHECK) or
+		 (_load_queue[index_load_queue]._state == LOAD_QUEUE_CHECK)) and
+		is_operation_memory_load(_load_queue[index_load_queue]._operation))
+	      {
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * Find a load : %d",index_load_queue);
+
+		nb_check++; // use one port
+
+		// find a entry that it need a check
+		Tlsq_ptr_t store_queue_ptr_write     = _load_queue[index_load_queue]._store_queue_ptr_write;
+		Tlsq_ptr_t store_queue_ptr_read      = _load_queue[index_load_queue]._store_queue_ptr_read ;
+ 		Tlsq_ptr_t store_queue_empty         = _load_queue[index_load_queue]._store_queue_empty    ;
+// 		Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write;
+
+                // Init variable
+		bool       end_check    = false;
+		bool       change_state = false;
+		bool       next         = false;
+
+		// At the first store queue empty, stop check.
+		// Explication :
+		//  * rename logic keep a empty case in the store queue (also size_store_queue > 1)
+		//  * when a store is out of store queue, also it was in head of re order buffer. Also, they are none previous load.
+
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_ptr_write    : %d",store_queue_ptr_write);
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_ptr_read     : %d",store_queue_ptr_read );
+// 		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_empty        : %d",store_queue_empty );
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * reg_STORE_QUEUE_PTR_READ : %d",reg_STORE_QUEUE_PTR_READ);
+
+ 		if ((store_queue_ptr_write ==     store_queue_ptr_read) or
+		    (store_queue_ptr_write == reg_STORE_QUEUE_PTR_READ))
+// 		if (store_queue_empty)
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write == store_queue_ptr_read");
+		    end_check    = true;
+		    change_state = true;
+		  }
+		else
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write != store_queue_ptr_read");
+
+		    store_queue_ptr_write = (store_queue_ptr_write-1)%(_param->_size_store_queue); // store_queue_ptr_write target the next slot to write, also the slot is not significatif when the load is renaming
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write : %d",store_queue_ptr_write);
+
+                    bool test_thread_id = true;
+                    
+                    // Test thread id
+                    if (_param->_have_port_context_id)
+                      test_thread_id &= (_load_queue[index_load_queue]._context_id    == _store_queue[store_queue_ptr_write]._context_id);
+                    if (_param->_have_port_front_end_id)
+                      test_thread_id &= (_load_queue[index_load_queue]._front_end_id  == _store_queue[store_queue_ptr_write]._front_end_id);
+                    if (_param->_have_port_ooo_engine_id)
+                      test_thread_id &= (_load_queue[index_load_queue]._ooo_engine_id == _store_queue[store_queue_ptr_write]._ooo_engine_id);
+		    
+                    // switch on store_queue state
+		    switch (_store_queue[store_queue_ptr_write]._state)
+		      {
+		      case STORE_QUEUE_VALID_NO_SPECULATIVE : 
+		      case STORE_QUEUE_COMMIT :
+		      case STORE_QUEUE_VALID_SPECULATIVE :
+			{
+                          log_printf(TRACE,Load_store_unit,FUNCTION,"      * store have a valid entry");
+			  
+			  // TODO : MMU - nous considérons que les adresses sont physique
+			  if (test_thread_id)
+			    {
+			      // the load and store are in the same thread. Now, we must test address.
+
+			      log_printf(TRACE,Load_store_unit,FUNCTION,"        * load and store is the same thread.");
+			      Tdcache_address_t load_addr  = _load_queue [index_load_queue ]._address;
+			      Tdcache_address_t store_addr = _store_queue[store_queue_ptr_write]._address;
+			      
+			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * load_addr                     : %.8x.",load_addr );
+			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * store_addr                    : %.8x.",store_addr);
+			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * load_addr  & mask_address_msb : %.8x.",load_addr  & _param->_mask_address_msb);
+			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * store_addr & mask_address_msb : %.8x.",store_addr & _param->_mask_address_msb);
+			      // Test if the both address target the same "word"
+			      if ((load_addr  & _param->_mask_address_msb) == 
+				  (store_addr & _param->_mask_address_msb))
+				{
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * address_msb is the same.");
+
+				  // all case - [] : store, () : load
+				  // (1) store_max >= load_max and store_min <= load_min  ...[...(...)...]... Ok - inclusion in store
+				  // (2) store_min >  load_max                            ...[...]...(...)... Ok - no conflit
+				  // (3) store_max <  load_min                            ...(...)...[...]... Ok - no conflit
+				  // (4) store_max <  load_max and store_min >  load_min  ...(...[...]...)... Ko - inclusion in load
+				  // (5) store_max >= load_max and store_min >  load_min  ...[...(...]...)... Ko - conflit
+				  // (6) store_max <  load_max and store_min <= load_min  ...(...[...)...]... Ko - conflit
+				  // but :
+				  // load in the cache is a word !
+				  // the mask can be make when the load is commited. Also, the rdata content a full word.
+				  // the only case is (4)
+				  
+                                  // Read data
+                                  bool is_big_endian = true;
+
+				  Tgeneral_data_t   load_data      = _load_queue [index_load_queue ]._rdata  ;
+				  Tgeneral_data_t   store_data     = _store_queue[store_queue_ptr_write]._wdata  ;
+                                  Tdcache_address_t check_hit_byte = _load_queue [index_load_queue ]._check_hit_byte;
+                                  Tcontrol_t        check_hit      = _load_queue [index_load_queue ]._check_hit;
+                                  uint32_t          load_size_access  = memory_size(_load_queue [index_load_queue ]._operation)>>3;
+                                  uint32_t          store_size_access = memory_size(_store_queue[store_queue_ptr_write]._operation)>>3;
+
+                                  log_printf(TRACE,Load_store_unit,FUNCTION,"            * is_big_endian           : %d",is_big_endian);
+                                  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data               : 0x%.8x",load_data);
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_data              : 0x%.8x",store_data);
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte          : %x",check_hit_byte);
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit               : %d",check_hit);
+
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_size_access        : %d",load_size_access );
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_size_access       : %d",store_size_access);
+
+                                  if (is_big_endian)
+                                    {
+                                      // swap in little endian
+                                      load_data      = swapBytes<Tgeneral_data_t  >(load_data     , _param->_size_general_data>>3,load_size_access);
+                                      store_data     = swapBytes<Tgeneral_data_t  >(store_data    , _param->_size_general_data>>3,store_size_access);
+                                      check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access);
+                                      
+                                      
+                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data      (swap 1) : 0x%.8x",load_data);
+                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_data     (swap 1) : 0x%.8x",store_data);
+                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte (swap 1) : %x",check_hit_byte);
+                                    }
+
+                                  uint32_t store_nb_byte     = (1<<memory_access(_store_queue[store_queue_ptr_write]._operation));
+
+                                  // Take interval to the store
+				  uint32_t store_num_byte_min = (store_addr & _param->_mask_address_lsb);
+				  uint32_t store_num_byte_max = store_num_byte_min+store_nb_byte;
+
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_num_byte_min      : %d",store_num_byte_min);
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_num_byte_max      : %d",store_num_byte_max);
+
+
+				  // The bypass is checked byte per byte
+                                  // Is same endianness : because to change endianness, we must write in special register. Also the pipeline is flushed.
+				  for (uint32_t num_store_byte=store_num_byte_min; num_store_byte<store_num_byte_max; num_store_byte ++)
+				    {
+                                      // Make a mask
+                                      uint32_t num_load_byte = num_store_byte;
+
+//                                       if (is_big_endian)
+//                                         {
+//                                           // sd 0 : 0 1 2 3 4 5 6 7
+//                                           // ld 0 : 0 1 2 3 4 5 6 7 >>  0 
+//                                           // lw 0 :         0 1 2 3 >>  0 -4
+//                                           // lw 4 : 4 5 6 7         >> 32 +4
+//                                           // lh 0 :             0 1 >>  0 -6
+//                                           // lh 2 :         2 3     >> 16 -2
+//                                           // lh 4 :     4 5         >> 32 +2
+//                                           // lh 6 : 6 7             >> 48 +6
+//                                           // lb 0 :               0 >>  0 -7
+//                                           // lb 1 :             1   >>  8 -5
+//                                           // lb 2 :           2     >> 16 -3
+//                                           // lb 3 :         3       >> 24 -1
+//                                           // lb 4 :       4         >> 32 +1
+//                                           // lb 5 :     5           >> 40 +3
+//                                           // lb 6 :   6             >> 48 +5
+//                                           // lb 7 : 7               >> 56 +7
+
+//                                           // diff : (store_nb_byte + load_nb_byte) - 2*nb_load_byte*((num_store_byte+1)
+
+//                                           // store duplicate = all store access can be see as full size_data store
+// //                                           uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load_queue ]._operation));
+
+// //                                           int32_t diff = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1));
+
+// //                                           num_load_byte =num_store_byte+diff;
+
+// //                                           log_printf(TRACE,Load_store_unit,FUNCTION,"              * load_nb_byte   : %d",load_nb_byte);
+// //                                           log_printf(TRACE,Load_store_unit,FUNCTION,"              * diff           : %d",diff);
+
+
+//                                           num_load_byte = num_store_byte;
+//                                         }
+//                                       else
+//                                         {
+//                                           // sd 0 : 0 1 2 3 4 5 6 7
+//                                           // ld 0 : 0 1 2 3 4 5 6 7 >>  0
+//                                           // lw 0 :         4 5 6 7 >>  0
+//                                           // lw 4 : 0 1 2 3         >> 32
+//                                           // lh 0 :             6 7 >>  0
+//                                           // lh 2 :         4 5     >> 16
+//                                           // lh 4 :     2 3         >> 32
+//                                           // lh 6 : 0 1             >> 48
+//                                           // lb 0 :               7 >>  0
+//                                           // lb 1 :             6   >>  8
+//                                           // lb 2 :           5     >> 16
+//                                           // lb 3 :         4       >> 24
+//                                           // lb 4 :       3         >> 32
+//                                           // lb 5 :     2           >> 40
+//                                           // lb 6 :   1             >> 48
+//                                           // lb 7 : 0               >> 56
+                                          
+//                                           num_load_byte = num_store_byte;
+//                                         }
+
+				      uint32_t mask  = 1<<num_load_byte;
+
+				      log_printf(TRACE,Load_store_unit,FUNCTION,"              * num_store_byte : %d",num_store_byte);
+				      log_printf(TRACE,Load_store_unit,FUNCTION,"              * num_load_byte  : %d",num_load_byte);
+				      log_printf(TRACE,Load_store_unit,FUNCTION,"              * mask           : %d",mask);
+
+				      // Accept the bypass if :
+                                      //   * they have not a previous bypass with an another store
+                                      //   * it's a valid request of load
+				      if ((check_hit_byte&mask)==0)
+					{
+                                          // Note : Store is duplicate = all store access can be see as full size_data store
+
+                                          uint32_t num_store_bit_min = num_store_byte<<3; //*8
+//                                        uint32_t num_store_bit_max = num_store_bit_min+8-1;
+                                          uint32_t num_load_bit_min  = num_load_byte <<3; //*8
+                                          uint32_t num_load_bit_max  = num_load_bit_min+8-1;
+
+					  log_printf(TRACE,Load_store_unit,FUNCTION,"              * bypass !!!");
+//                                        log_printf(TRACE,Load_store_unit,FUNCTION,"              * interval store : [%d:%d]",num_store_bit_max,num_store_bit_min);
+                                          log_printf(TRACE,Load_store_unit,FUNCTION,"              * interval store : [..:%d]",num_store_bit_min);
+                                          log_printf(TRACE,Load_store_unit,FUNCTION,"              * interval load  : [%d:%d]",num_load_bit_max,num_load_bit_min);
+					  log_printf(TRACE,Load_store_unit,FUNCTION,"                * rdata_old : 0x%.8x", load_data);
+
+					  load_data = ((((store_data>>num_store_bit_min) & 0xff) << num_load_bit_min) |
+                                                       mask_not<Tdcache_data_t>(load_data,num_load_bit_max,num_load_bit_min));
+
+					  check_hit_byte |= mask;
+					  check_hit       = 1;
+					  change_state = true;
+
+					  log_printf(TRACE,Load_store_unit,FUNCTION,"                * rdata_new : 0x%.8x", load_data);
+					}
+				    }
+
+                                  if (is_big_endian)
+                                    {
+                                      // swap in little endian
+                                      load_data      = swapBytes<Tgeneral_data_t  >(load_data     , _param->_size_general_data>>3,load_size_access);
+                                      check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access);
+                                      
+                                      
+                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data      (swap 2) : 0x%.8x",load_data);
+                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte (swap 2) : %x",check_hit_byte);
+                                    }
+
+				  _load_queue[index_load_queue]._rdata          = load_data;
+                                  _load_queue[index_load_queue]._check_hit_byte = check_hit_byte;
+                                  _load_queue[index_load_queue]._check_hit      = check_hit;
+
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data  (after) : 0x%.8x",load_data);
+
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit          : %x",check_hit);
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte     : %x",check_hit_byte);
+
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * mask_end_check     : %x",(-1& _param->_mask_address_lsb));
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * mask_check_hit_byte: %x",_param->_mask_check_hit_byte);
+				  // The check is finish if all bit is set
+				  end_check = (_load_queue[index_load_queue]._check_hit_byte == _param->_mask_check_hit_byte);
+				}
+			    }
+			  
+			  next = true;
+			  break;
+			}
+		      case STORE_QUEUE_EMPTY :
+			{
+			  log_printf(TRACE,Load_store_unit,FUNCTION,"      * store is empty ... wait.");
+			  break;
+			}
+
+		      case STORE_QUEUE_NO_VALID_NO_SPECULATIVE :
+			{
+                          log_printf(TRACE,Load_store_unit,FUNCTION,"      * store have an invalid entry");
+
+			  if (test_thread_id)
+                            {
+                              end_check    = true; // previous store is invalid -> exception
+                              change_state = true;
+                            }
+                          else
+                            next = true;
+                            
+			  break;
+			}
+		      }
+		  }
+
+		if (next)
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * next");
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * new store_queue_ptr_write : %d",store_queue_ptr_write);
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * update reg_STORE_QUEUE_NB_CHECK");
+#ifdef DEBUG
+                    if (reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write] == 0)
+                      throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
+#endif
+
+                    reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write] --;
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 1 [%d] <- %d", store_queue_ptr_write,reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write]);
+
+		    if ((store_queue_ptr_write ==     store_queue_ptr_read) or
+			(store_queue_ptr_write == reg_STORE_QUEUE_PTR_READ))
+		      {
+// 			store_queue_empty = true;
+			end_check         = true;
+			change_state      = true;
+		      }
+
+// 		    if (_load_queue[index_load_queue]._store_queue_ptr_write == 0)
+// 		      _load_queue[index_load_queue]._store_queue_ptr_write = _param->_size_store_queue-1;
+// 		    else
+// 		      _load_queue[index_load_queue]._store_queue_ptr_write --;
+		    _load_queue[index_load_queue]._store_queue_ptr_write = store_queue_ptr_write; // because the index store have be decrease
+ 		    _load_queue[index_load_queue]._store_queue_empty     = store_queue_empty; // because the index store have be decrease
+
+		    // FIXME : peut n'est pas obliger de faire cette comparaison. Au prochain cycle on le détectera que les pointeur sont égaux. Ceci évitera d'avoir deux comparateurs avec le registre "store_queue_ptr_read"
+		  }
+
+		if (change_state)
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * change_state");
+                    log_printf(TRACE,Load_store_unit,FUNCTION,"              * end_check : %d",end_check);
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * state old : %s",toString(_load_queue[index_load_queue]._state).c_str());
+
+		    switch (_load_queue[index_load_queue]._state)
+		      {
+		      case LOAD_QUEUE_WAIT_CHECK   : 
+                        {
+			  if (end_check)
+                            _load_queue[index_load_queue]._state = LOAD_QUEUE_WAIT  ; 
+                          break;
+                        }
+		      case LOAD_QUEUE_COMMIT_CHECK : 
+			{
+			  if (end_check)
+			    _load_queue[index_load_queue]._state = LOAD_QUEUE_COMMIT; 
+			  else
+			    _load_queue[index_load_queue]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end
+			  break;
+			}
+		      case LOAD_QUEUE_CHECK        : 
+			{
+			  if (end_check)
+			    _load_queue[index_load_queue]._state     = LOAD_QUEUE_COMMIT;
+
+			  // check find a bypass. A speculative load have been committed : report a speculation miss.
+			  if ((_load_queue[index_load_queue]._check_hit != 0) and 
+                              (_load_queue[index_load_queue]._write_rd  == 0) // is commit
+                              )
+			    {
+			      _load_queue[index_load_queue]._exception = EXCEPTION_MEMORY_MISS_SPECULATION;
+			      _load_queue[index_load_queue]._write_rd  = 1; // write the good result
+
+#ifdef STATISTICS
+                              if (usage_is_set(_usage,USE_STATISTICS))
+                                (*_stat_nb_inst_load_commit_miss) ++;
+#endif
+			    }
+			  
+			  break;
+			}
+		      default : break;
+		      }
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * state new : %s",toString(_load_queue[index_load_queue]._state).c_str());
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * exception : %d",_load_queue[index_load_queue]._exception);
+
+                    if (end_check//  and not store_queue_empty
+			)
+                      {
+                        log_printf(TRACE,Load_store_unit,FUNCTION,"                * end check, decrease all nb_check");
+                        
+                        uint32_t i=store_queue_ptr_write;
+                        while (i!=store_queue_ptr_read)
+                          {
+                            i=((i==0)?_param->_size_store_queue:i)-1;
+                            
+#ifdef DEBUG
+                            if (reg_STORE_QUEUE_NB_CHECK [i] == 0)
+                              throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
+#endif
+			    
+                            reg_STORE_QUEUE_NB_CHECK [i] --;
+
+			    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 2 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
+
+                            //i=(i+1)%_param->_size_store_queue;
+                          }
+			
+			_load_queue[index_load_queue]._store_queue_empty = true; // end of check
+                      }
+		  }
+	      }
+	    // else : don't use a port
+	  }
+	
+	//================================================================
+	// Interface "MEMORY_IN"
+	//================================================================
+	
+        if ((PORT_READ(in_MEMORY_IN_VAL [internal_MEMORY_IN_PORT]) == 1) and
+            (    internal_MEMORY_IN_ACK  == 1))
+          {
+            log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_IN [%d]",internal_MEMORY_IN_PORT);
+
+	    // Test operation :
+	    //~~~~~~~~~~~~~~~~~
+	    //  store  in store_queue
+	    //  load   in speculation_access_queue
+	    //  others in speculation_access_queue
+
+#ifdef DEBUG_TEST
+	    if (PORT_READ(in_MEMORY_IN_TYPE [internal_MEMORY_IN_PORT]) != TYPE_MEMORY)
+	      throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'");
+#endif
+	    Toperation_t    operation            = PORT_READ(in_MEMORY_IN_OPERATION[internal_MEMORY_IN_PORT]);
+	    Tcontrol_t      cancel               = PORT_READ(in_MEMORY_IN_CANCEL   [internal_MEMORY_IN_PORT]);
+	    Tgeneral_data_t address              = (PORT_READ(in_MEMORY_IN_IMMEDIAT[internal_MEMORY_IN_PORT]) +
+						    PORT_READ(in_MEMORY_IN_DATA_RA [internal_MEMORY_IN_PORT]));
+	    bool            exception_alignement = (mask_memory_access(operation) & address) != 0;
+						    
+	    if (is_operation_memory_store(operation) == true)
+	      {
+		// =======================
+		// ===== STORE_QUEUE =====
+		// =======================
+		// There a two store request type :
+		//   - first is operation with address and data
+		//   - second is the information of re order buffer : the store become not speculative and can access at the data cache
+
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue");
+		log_printf(TRACE,Load_store_unit,FUNCTION,"      * PUSH");
+		
+		// Write pointer is define in rename stage :
+		Tlsq_ptr_t           index         = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
+		log_printf(TRACE,Load_store_unit,FUNCTION,"      * index         : %d",index);
+		
+		// Need read : state and exception.
+		Tstore_queue_state_t old_state     = _store_queue [index]._state;
+		Tstore_queue_state_t new_state     = old_state;
+		bool                 update_info   = false;
+
+		Texception_t         old_exception = _store_queue [index]._exception;
+		Texception_t         new_exception = old_exception;
+
+		// Compute next state
+		switch (old_state)
+		  {
+		  case STORE_QUEUE_EMPTY                   :
+		    {
+//                    reg_STORE_QUEUE_INVALID [index] = false; // new first store instruction
+
+		      if (is_operation_memory_store_head(operation) == true)
+			{
+			  new_state = STORE_QUEUE_NO_VALID_NO_SPECULATIVE;
+
+			  // test if is a speculation
+			  if (operation == OPERATION_MEMORY_STORE_HEAD_KO)
+                            {
+                              new_exception = EXCEPTION_MEMORY_MISS_SPECULATION;
+//                            reg_STORE_QUEUE_INVALID [index] = true;
+                            }
+			  else
+			    new_exception = EXCEPTION_MEMORY_NONE;
+			}
+		      else
+			{
+			  new_state = STORE_QUEUE_VALID_SPECULATIVE;
+
+			  // Test if have an exception
+			  if (exception_alignement == true)
+			    new_exception = EXCEPTION_MEMORY_ALIGNMENT;
+			  else
+			    new_exception = EXCEPTION_MEMORY_NONE;
+
+			  update_info = true;
+			}
+		      break;
+		    }
+		  case STORE_QUEUE_NO_VALID_NO_SPECULATIVE :
+		    {
+#ifdef DEBUG_TEST
+		      if (is_operation_memory_store_head(operation) == true)
+			throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_NO_VALID_NO_SPECULATIVE\", also a previous store_head have been receiveid. But this operation is a store_head."));
+#endif
+		      // Test if have a new exception (priority : miss_speculation)
+		      if ((exception_alignement == true) and (old_exception == EXCEPTION_MEMORY_NONE))
+			new_exception = EXCEPTION_MEMORY_ALIGNMENT;
+		      
+		      if (new_exception != EXCEPTION_MEMORY_NONE)
+			new_state = STORE_QUEUE_COMMIT;
+		      else
+			new_state = STORE_QUEUE_VALID_NO_SPECULATIVE;
+		      
+		      update_info = true;
+		      break;
+		    }
+		  case STORE_QUEUE_VALID_SPECULATIVE       :
+		    {
+#ifdef DEBUG_TEST
+		      if (is_operation_memory_store_head(operation) == false)
+			throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_VALID_SPECULATIVE\", also a previous access with register and address have been receiveid. But this operation is a not store_head."));
+#endif
+		      if (operation == OPERATION_MEMORY_STORE_HEAD_KO)
+                        {
+                          new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; // great prioritary
+//                        reg_STORE_QUEUE_INVALID [index] = true;
+                        }
+
+		      if (new_exception != EXCEPTION_MEMORY_NONE)
+			new_state = STORE_QUEUE_COMMIT;
+		      else
+			new_state = STORE_QUEUE_VALID_NO_SPECULATIVE;
+		      
+		      break;
+		    }
+		  case STORE_QUEUE_VALID_NO_SPECULATIVE    :
+		  case STORE_QUEUE_COMMIT                  :
+		    {
+		      throw ERRORMORPHEO(FUNCTION,"<Load_store_unit::function_speculative_load_access_transition> Invalid state and operation");
+		    }
+		  }
+
+		_store_queue [index]._state     = new_state;
+		_store_queue [index]._exception = new_exception;
+		
+		if (update_info == true)
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * Update information");
+
+		    _store_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID   [internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._packet_id            = (not _param->_have_port_rob_ptr      )?0:PORT_READ(in_MEMORY_IN_PACKET_ID    [internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._operation            = operation;
+		    _store_queue [index]._cancel               = cancel   ;
+		    _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._address              = address;
+		    _store_queue [index]._send_commit          = false;
+
+		    // reordering data
+		    _store_queue [index]._wdata                = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0); 
+//                  _store_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  [internal_MEMORY_IN_PORT]);
+		  }
+	      }
+	    else
+	      {
+		// ====================================
+		// ===== SPECULATIVE_ACCESS_QUEUE =====
+		// ====================================
+
+		// In speculative access queue, they are many type's request
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue");
+		log_printf(TRACE,Load_store_unit,FUNCTION,"      * PUSH");
+		
+		// Write in reservation station
+		uint32_t     index = _speculative_access_queue_control->push();
+
+		log_printf(TRACE,Load_store_unit,FUNCTION,"      * index : %d", index);
+
+		Texception_t exception;
+
+		if (exception_alignement == true)
+		  exception = EXCEPTION_MEMORY_ALIGNMENT;
+		else
+		  exception = EXCEPTION_MEMORY_NONE;
+				
+		// if exception, don't access at the cache
+		// NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits)
+		_speculative_access_queue [index]._state                = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE;
+		_speculative_access_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID   [internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._packet_id            = (not _param->_have_port_rob_ptr      )?0:PORT_READ(in_MEMORY_IN_PACKET_ID    [internal_MEMORY_IN_PORT]);
+
+		_speculative_access_queue [index]._operation            = operation;
+		_speculative_access_queue [index]._cancel               = cancel   ;
+		_speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._store_queue_ptr_read = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_READ [internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._store_queue_empty    = PORT_READ(in_MEMORY_IN_STORE_QUEUE_EMPTY    [internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._address              = address;
+		// NOTE : is operation is a load, then they are a result and must write in the register file
+		_speculative_access_queue [index]._write_rd             = is_operation_memory_load(operation);
+		_speculative_access_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  [internal_MEMORY_IN_PORT]);
+
+		_speculative_access_queue [index]._exception            = exception;
+	      }
+	  }
+
+	//================================================================
+	// Interface "DCACHE_REQ"
+	//================================================================
+        if ((    internal_DCACHE_REQ_VAL  == 1) and
+            (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1))
+          {
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_REQ [0]");
+
+	    switch (internal_DCACHE_REQ_SELECT_QUEUE)
+	      {
+	      case SELECT_STORE_QUEUE :
+		{
+		  // =======================
+		  // ===== STORE_QUEUE =====
+		  // =======================
+		  
+		  // Entry flush and increase the read pointer
+		  
+		  _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_COMMIT;
+
+#if defined(DEBUG) and defined(DEBUG_Load_store_unit) and (DEBUG_Load_store_unit == true)
+		  if (log_file_generate)
+	            {
+	              // log file
+                      Tcontext_t num_thread    = get_num_thread(_store_queue [reg_STORE_QUEUE_PTR_READ]._context_id   , _param->_size_context_id   ,
+                                                                _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id , _param->_size_front_end_id ,
+                                                                _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id, _param->_size_ooo_engine_id);
+
+	              memory_log_file [num_thread] 
+	            	<< "[" << simulation_cycle() << "] "
+	            	<< std::hex
+                        << "@ 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _store_queue [reg_STORE_QUEUE_PTR_READ]._address << " -[ Write ]-> 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata << " "
+	            	<< std::dec
+	            	<< "{" << toString(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation) << "}";
+	              
+	              memory_log_file [num_thread] << std::endl;
+	            }
+#endif	    
+
+
+		  break;
+		}
+	      case SELECT_LOAD_QUEUE_SPECULATIVE :
+		{
+		  // =========================================
+		  // ===== SELECT_LOAD_QUEUE_SPECULATIVE =====
+		  // =========================================
+
+		  load_queue_push = true;
+		  break;
+		}
+	      case SELECT_LOAD_QUEUE :
+		{
+		  throw ERRORMORPHEO(FUNCTION,_("Invalid selection"));
+		  break;
+		}
+
+		break;
+	      }
+	  }
+
+	if (load_queue_push)
+	  {
+            log_printf(TRACE,Load_store_unit,FUNCTION,"  * load_queue_push");
+
+	    Tlsq_ptr_t   ptr_write = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write;
+	    Toperation_t operation = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation;
+	    Texception_t exception = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._exception;
+	    bool         have_exception = (exception != EXCEPTION_MEMORY_NONE);
+            bool         need_check= false;
+            Tlsq_ptr_t   store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;
+            Tlsq_ptr_t   store_queue_ptr_read  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_read ;
+            Tcontrol_t   store_queue_empty     = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_empty    ;
+	    
+	    if (have_exception)
+	      _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT;
+	    else
+	      {
+		if (have_dcache_rsp(operation))
+		  {
+		    // load and synchronisation
+		    if (must_check(operation) and not store_queue_empty)
+		      {
+			// load
+                        need_check = true;
+			
+			_load_queue [ptr_write]._state = LOAD_QUEUE_WAIT_CHECK;
+		      }
+		    else
+		      {
+			// synchronisation
+			_load_queue [ptr_write]._state = LOAD_QUEUE_WAIT;
+		      }
+		  }
+		else
+		  {
+		    // lock, prefecth, flush and invalidate
+		    _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT;
+		  }
+	      }
+
+	    Tdcache_address_t address        = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;
+	    Tdcache_address_t address_lsb    = (address & _param->_mask_address_lsb);
+	    Tdcache_address_t check_hit_byte = gen_mask_not<Tdcache_address_t>(address_lsb+(memory_size(operation)>>3)-1,address_lsb) & _param->_mask_check_hit_byte;
+
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * address                 : 0x%.8x", address);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * address_lsb             : 0x%.8x", address_lsb);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * operation               : %d", operation);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * memory_size             : %d", memory_size(operation));
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * check_hit_byte          : 0x%x", check_hit_byte);
+
+	    _load_queue [ptr_write]._context_id            = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
+	    _load_queue [ptr_write]._front_end_id          = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
+	    _load_queue [ptr_write]._ooo_engine_id         = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
+	    _load_queue [ptr_write]._packet_id             = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._packet_id;
+	    _load_queue [ptr_write]._operation             = operation;
+	    _load_queue [ptr_write]._cancel                = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._cancel;
+	    _load_queue [ptr_write]._store_queue_ptr_write = store_queue_ptr_write;
+	    _load_queue [ptr_write]._store_queue_ptr_read  = store_queue_ptr_read ;
+ 	    _load_queue [ptr_write]._store_queue_empty     = store_queue_empty    ;
+	    _load_queue [ptr_write]._address               = address;
+	    _load_queue [ptr_write]._check_hit_byte        = check_hit_byte;
+	    _load_queue [ptr_write]._check_hit             = 0;
+	    _load_queue [ptr_write]._shift                 = address_lsb<<3;// *8
+	    _load_queue [ptr_write]._is_load_signed        = is_operation_memory_load_signed(operation);
+	    _load_queue [ptr_write]._access_size           = memory_size(operation);
+	    // NOTE : if have an exception, must write in register, because a depend instruction wait the load data.
+	    _load_queue [ptr_write]._write_rd              = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._write_rd             ;
+	    _load_queue [ptr_write]._num_reg_rd            = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._num_reg_rd           ;
+	    _load_queue [ptr_write]._exception             = exception;
+	    _load_queue [ptr_write]._rdata                 = address; // to the exception
+
+            switch (_param->_speculative_commit_predictor_scheme)
+              {
+
+              case PREDICTOR_NEVER_TAKE  : {_load_queue [ptr_write]._can_speculative_commit = false; break;}
+              case PREDICTOR_ALWAYS_TAKE : {_load_queue [ptr_write]._can_speculative_commit = true ; break;}
+              case PREDICTOR_COUNTER     : {_load_queue [ptr_write]._can_speculative_commit = false; break;} // TODO
+              default :
+                {
+                  // throw ERRORMORPHEO(FUNCTION,_("Invalid predictor scheme.\n"));
+                  _load_queue [ptr_write]._can_speculative_commit = false;
+                  break;
+                }
+              }
+	    
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue");
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * POP[%d]",(*_speculative_access_queue_control)[0]);
+	    
+	    _speculative_access_queue [(*_speculative_access_queue_control)[0]]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY;
+	    
+	    _speculative_access_queue_control->pop();
+
+#ifdef STATISTICS
+            if (usage_is_set(_usage,USE_STATISTICS))
+              (*_stat_nb_inst_load) ++;
+#endif
+
+            // Only load need check
+            if (need_check//  and not store_queue_empty
+		)
+//             if (is_operation_memory_load(_load_queue [ptr_write]._operation))
+              {
+                log_printf(TRACE,Load_store_unit,FUNCTION,"    * update nb_check");
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_ptr_write : %d",store_queue_ptr_write);
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_ptr_read  : %d",store_queue_ptr_read );
+		log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_empty     : %d",store_queue_empty    );
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      * reg_STORE_QUEUE_PTR_READ  : %d",reg_STORE_QUEUE_PTR_READ);
+                
+                uint32_t i=store_queue_ptr_write;
+                while (i!=store_queue_ptr_read)
+                  {
+                    i=((i==0)?_param->_size_store_queue:i)-1;
+                    
+                    log_printf(TRACE,Load_store_unit,FUNCTION,"      * i                         : %d",i);
+                    
+                    reg_STORE_QUEUE_NB_CHECK [i] ++;
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 3 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
+                  }
+              }
+          }
+
+	//================================================================
+	// Interface "DCACHE_RSP"
+	//================================================================
+        if ((PORT_READ(in_DCACHE_RSP_VAL[0])== 1) and
+            (    internal_DCACHE_RSP_ACK == 1))
+          {
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_RSP [0]");
+
+	    // don't use context_id : because there are one queue for all thread
+	    //Tcontext_t      context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID[0]); 
+	    Tpacket_t       packet_id  = PORT_READ(in_DCACHE_RSP_PACKET_ID [0]);
+	    Tdcache_data_t  rdata      = PORT_READ(in_DCACHE_RSP_RDATA     [0]);
+	    Tdcache_error_t error      = PORT_READ(in_DCACHE_RSP_ERROR     [0]);
+
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * original packet_id : %d"  , packet_id);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * packet_id          : %d"  , packet_id>>1);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * rdata              : %.8x", rdata);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * error              : %d"  , error);
+	    
+	    if (DCACHE_RSP_IS_LOAD(packet_id) == 1)
+	      {
+		packet_id >>= 1;
+
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * packet is a LOAD");
+ 
+#ifdef DEBUG_TEST
+		if (not have_dcache_rsp(_load_queue [packet_id]._operation))
+		  throw ERRORMORPHEO(FUNCTION,_("Receive of respons, but the corresponding operation don't wait a respons."));
+#endif
+
+                Tdcache_data_t data = _load_queue [packet_id]._rdata;
+
+                log_printf(TRACE,Load_store_unit,FUNCTION,"    * data construction");
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      * data from cache     : 0x%.8x",rdata);
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      * data (before)       : 0x%.8x", data);
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      * check_hit_byte      : 0x%x"  ,_load_queue [packet_id]._check_hit_byte);
+                for (uint32_t i=0;i<(_param->_size_general_data>>3)/*8*/; ++i)
+                  // Test if this byte has been checked
+                  if ((_load_queue [packet_id]._check_hit_byte & (1<<i)) == 0)
+                    {
+                      log_printf(TRACE,Load_store_unit,FUNCTION,"      * no previous check ]%d:%d]",(i+1)<<3,i<<3);
+                      data = insert<Tdcache_data_t>(data,rdata,((i+1)<<3)-1,i<<3);
+                    }
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      * data (after)        : 0x%.8x", data);
+                
+                _load_queue [packet_id]._rdata = data;
+		
+#if defined(DEBUG) and defined(DEBUG_Load_store_unit) and (DEBUG_Load_store_unit == true)
+		if (log_file_generate)
+		  {
+		    // log file
+		    Tcontext_t num_thread    = get_num_thread(_load_queue [packet_id]._context_id   , _param->_size_context_id   ,
+							      _load_queue [packet_id]._front_end_id , _param->_size_front_end_id ,
+							      _load_queue [packet_id]._ooo_engine_id, _param->_size_ooo_engine_id);
+		    
+		    memory_log_file [num_thread] 
+		      << "[" << simulation_cycle() << "] "
+		      << std::hex
+		      << "@ 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _load_queue [packet_id]._address << " -[ Read  ]-> 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _load_queue [packet_id]._rdata << " "
+		      << std::dec
+		      << "{" << toString(_load_queue [packet_id]._operation) << "}";
+		    
+		    memory_log_file [num_thread] << std::endl;
+		  }
+#endif	    
+
+		if (error != DCACHE_ERROR_NONE)
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"    * have a bus error !!!");
+
+		    _load_queue [packet_id]._exception = EXCEPTION_MEMORY_BUS_ERROR;
+		    _load_queue [packet_id]._state     = LOAD_QUEUE_COMMIT;
+
+                    
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write : %d", _load_queue[packet_id]._store_queue_ptr_write);
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_read  : %d", _load_queue[packet_id]._store_queue_ptr_read );
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_empty     : %d", _load_queue[packet_id]._store_queue_empty    );
+
+ 		    if (not _load_queue[packet_id]._store_queue_empty)
+		      {
+			uint32_t i=_load_queue[packet_id]._store_queue_ptr_write;
+			
+			while (i!=_load_queue[packet_id]._store_queue_ptr_read)
+			  {
+			    i=((i==0)?_param->_size_store_queue:i)-1;
+			    
+#ifdef DEBUG
+			    if (reg_STORE_QUEUE_NB_CHECK [i] == 0)
+			      throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
+#endif
+			    
+			    reg_STORE_QUEUE_NB_CHECK [i] --;
+
+			    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 4 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
+
+			    //i=(i+1)%_param->_size_store_queue;
+			  }
+			_load_queue[packet_id]._store_queue_empty = true; // end of check
+
+		      }
+		  }
+		else
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"    * have no bus error.");
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * previous state : %s",toString(_load_queue [packet_id]._state).c_str());
+
+		    // FIXME : convention : if bus error, the cache return the fautive address !
+		    // But, the load's address is aligned !
+
+		    switch (_load_queue [packet_id]._state)
+		      {
+		      case LOAD_QUEUE_WAIT_CHECK : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT_CHECK; break;
+		      case LOAD_QUEUE_WAIT       : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT      ; break;
+		      default : throw ERRORMORPHEO(FUNCTION,_("Illegal state (dcache_rsp).")); break;
+		      }
+		  }
+	      }
+	    else
+	      {
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * packet is a STORE");
+		
+		// TODO : les stores ne génére pas de réponse sauf quand c'est un bus error !!!
+		throw ERRORMORPHEO(FUNCTION,_("dcache_rsp : no respons to a write. (TODO : manage bus error to the store operation.)"));
+	      }
+	    
+	  }
+	
+	// this register is to manage the priority of check -> Round robin
+	reg_LOAD_QUEUE_CHECK_PRIORITY = (reg_LOAD_QUEUE_CHECK_PRIORITY+1)%_param->_size_load_queue;
+	
+	
+#if defined(DEBUG) and (DEBUG>=DEBUG_TRACE)
+	// ***** dump store queue
+        log_printf(TRACE,Load_store_unit,FUNCTION,"  * Dump STORE_QUEUE");
+        log_printf(TRACE,Load_store_unit,FUNCTION,"    * ptr_read : %d",reg_STORE_QUEUE_PTR_READ);
+	
+	for (uint32_t i=0; i<_param->_size_store_queue; i++)
+	  {
+	    uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
+
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d %.1d, %.4d, %.8x %.8x, %.2d %.1d, %.2d %s",
+                       j,
+                       _store_queue[j]._context_id          ,
+                       _store_queue[j]._front_end_id        ,
+                       _store_queue[j]._ooo_engine_id       ,
+                       _store_queue[j]._packet_id           ,
+                       _store_queue[j]._operation           ,
+                       _store_queue[j]._cancel              ,
+                       _store_queue[j]._load_queue_ptr_write,
+                       _store_queue[j]._address             ,
+                       _store_queue[j]._wdata               ,
+                     //_store_queue[j]._write_rd            ,
+                     //_store_queue[j]._num_reg_rd          ,
+                       _store_queue[j]._exception           ,
+                       _store_queue[j]._send_commit         ,
+                       reg_STORE_QUEUE_NB_CHECK  [j]        ,
+                       toString(_store_queue[j]._state).c_str());
+	  }
+
+	// ***** dump speculative_access queue
+	log_printf(TRACE,Load_store_unit,FUNCTION,"  * Dump SPECULATIVE_ACCESS_QUEUE");
+	
+	for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
+	  {
+	    uint32_t j = (*_speculative_access_queue_control)[i];
+
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d %.1d, %.4d %.4d %.4d %.1d, %.8x, %.1d %.4d, %.2d, %s",
+                       j,
+                       _speculative_access_queue[j]._context_id          ,
+                       _speculative_access_queue[j]._front_end_id        ,
+                       _speculative_access_queue[j]._ooo_engine_id       ,
+                       _speculative_access_queue[j]._packet_id           ,
+                       _speculative_access_queue[j]._operation           ,
+                       _speculative_access_queue[j]._cancel              ,
+                       _speculative_access_queue[j]._load_queue_ptr_write,
+                       _speculative_access_queue[j]._store_queue_ptr_write,
+                       _speculative_access_queue[j]._store_queue_ptr_read ,
+                       _speculative_access_queue[j]._store_queue_empty    ,
+                       _speculative_access_queue[j]._address             ,
+                       _speculative_access_queue[j]._write_rd            ,
+                       _speculative_access_queue[j]._num_reg_rd          ,
+                       _speculative_access_queue[j]._exception           ,
+                       toString(_speculative_access_queue[j]._state).c_str());
+	  }
+
+	// ***** dump load queue
+	log_printf(TRACE,Load_store_unit,FUNCTION,"  * Dump LOAD_QUEUE");
+        log_printf(TRACE,Load_store_unit,FUNCTION,"    * ptr_read_check_priority : %d",reg_LOAD_QUEUE_CHECK_PRIORITY);
+	
+	for (uint32_t i=0; i<_param->_size_load_queue; i++)
+	  {
+	    uint32_t j = i;
+
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d %.1d, %.4d %.4d %.1d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s",
+                       j,
+                       _load_queue[j]._context_id          ,
+                       _load_queue[j]._front_end_id        ,
+                       _load_queue[j]._ooo_engine_id       ,
+                       _load_queue[j]._packet_id           ,
+                       _load_queue[j]._operation           ,
+                       _load_queue[j]._cancel              ,
+                       _load_queue[j]._store_queue_ptr_write,
+                       _load_queue[j]._store_queue_ptr_read ,
+		       _load_queue[j]._store_queue_empty    ,
+                       _load_queue[j]._address             ,
+                       _load_queue[j]._check_hit_byte      , 
+                       _load_queue[j]._check_hit           ,
+                       _load_queue[j]._shift               ,
+                       _load_queue[j]._is_load_signed      ,
+                       _load_queue[j]._access_size         ,
+                       _load_queue[j]._rdata               ,
+                       _load_queue[j]._write_rd            ,
+                       _load_queue[j]._num_reg_rd          ,
+                       _load_queue[j]._exception           ,
+                       toString(_load_queue[j]._state).c_str());
+	  }
+#endif
+	
+#ifdef STATISTICS
+        if (usage_is_set(_usage,USE_STATISTICS))
+          {
+            for (uint32_t i=0; i<_param->_size_store_queue; i++)
+              if (_store_queue[i]._state != STORE_QUEUE_EMPTY)
+                (*_stat_use_store_queue) ++;
+            for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
+              if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY)
+                (*_stat_use_speculative_access_queue) ++;
+            for (uint32_t i=0; i<_param->_size_load_queue; i++)
+              if (_load_queue[i]._state != LOAD_QUEUE_EMPTY)
+                (*_stat_use_load_queue) ++;
+          }
+#endif
+      }
+
+    log_end(Load_store_unit,FUNCTION);
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp	(revision 137)
+++ 	(revision )
@@ -1,40 +1,0 @@
-#ifdef SYSTEMC
-//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
-/*
- * $Id$
- *
- * [ Description ]
- * 
- */
-
-#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
-
-namespace morpheo                    {
-namespace behavioural {
-namespace core {
-namespace multi_execute_loop {
-namespace execute_loop {
-namespace multi_execute_unit {
-namespace execute_unit {
-namespace load_store_unit {
-
-
-#undef  FUNCTION
-#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMealy_dcache"
-  void Load_store_unit::function_speculative_load_commit_genMealy_dcache (void)
-  {
-    log_begin(Load_store_unit,FUNCTION);
-    log_end  (Load_store_unit,FUNCTION);
-  };
-
-}; // end namespace load_store_unit
-}; // end namespace execute_unit
-}; // end namespace multi_execute_unit
-}; // end namespace execute_loop
-}; // end namespace multi_execute_loop
-}; // end namespace core
-
-}; // end namespace behavioural
-}; // end namespace morpheo              
-#endif
-//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp	(revision 137)
+++ 	(revision )
@@ -1,76 +1,0 @@
-#ifdef SYSTEMC
-//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
-/*
- * $Id$
- *
- * [ Description ]
- * 
- */
-
-#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
-
-namespace morpheo                    {
-namespace behavioural {
-namespace core {
-namespace multi_execute_loop {
-namespace execute_loop {
-namespace multi_execute_unit {
-namespace execute_unit {
-namespace load_store_unit {
-
-
-#undef  FUNCTION
-#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMealy_insert"
-  void Load_store_unit::function_speculative_load_commit_genMealy_insert (void)
-  {
-    log_begin(Load_store_unit,FUNCTION);
-    log_function(Load_store_unit,FUNCTION,_name.c_str());
-
-    // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-    
-    // Initialisation
-    internal_MEMORY_IN_PORT = 0;
-    Tcontrol_t ack [_param->_nb_inst_memory];
-    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
-      ack [i] = 0;
-
-    if (PORT_READ(in_NRESET))
-      {
-    // find first valid entry
-    // store queue is never full (pointer is manage by rename stage)
-    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
-      if (PORT_READ(in_MEMORY_IN_VAL [i]))
-	{
-	  internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION [i])) or not _speculative_access_queue_control->full();
-
-	  if (internal_MEMORY_IN_ACK)
-	    {
-	      ack [i] = 1;
-	      internal_MEMORY_IN_PORT = i;
-	      break; // end
-	    }
-	}
-      }
-    else
-      {
-        internal_MEMORY_IN_ACK = 0;
-//         internal_MEMORY_IN_PORT = i;
-      }
-
-    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
-      PORT_WRITE(out_MEMORY_IN_ACK [i], ack [i]);
-
-    log_end(Load_store_unit,FUNCTION);
-  };
-
-}; // end namespace load_store_unit
-}; // end namespace execute_unit
-}; // end namespace multi_execute_unit
-}; // end namespace execute_loop
-}; // end namespace multi_execute_loop
-}; // end namespace core
-
-}; // end namespace behavioural
-}; // end namespace morpheo              
-#endif
-//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp	(revision 137)
+++ 	(revision )
@@ -1,40 +1,0 @@
-#ifdef SYSTEMC
-//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
-/*
- * $Id$
- *
- * [ Description ]
- * 
- */
-
-#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
-
-namespace morpheo                    {
-namespace behavioural {
-namespace core {
-namespace multi_execute_loop {
-namespace execute_loop {
-namespace multi_execute_unit {
-namespace execute_unit {
-namespace load_store_unit {
-
-
-#undef  FUNCTION
-#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMealy_retire"
-  void Load_store_unit::function_speculative_load_commit_genMealy_retire (void)
-  {
-    log_begin(Load_store_unit,FUNCTION);
-    log_end  (Load_store_unit,FUNCTION);
-  };
-
-}; // end namespace load_store_unit
-}; // end namespace execute_unit
-}; // end namespace multi_execute_unit
-}; // end namespace execute_loop
-}; // end namespace multi_execute_loop
-}; // end namespace core
-
-}; // end namespace behavioural
-}; // end namespace morpheo              
-#endif
-//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 137)
+++ 	(revision )
@@ -1,284 +1,0 @@
-#ifdef SYSTEMC
-//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
-/*
- * $Id$
- *
- * [ Description ]
- * 
- */
-
-#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
-
-namespace morpheo                    {
-namespace behavioural {
-namespace core {
-namespace multi_execute_loop {
-namespace execute_loop {
-namespace multi_execute_unit {
-namespace execute_unit {
-namespace load_store_unit {
-
-
-#undef  FUNCTION
-#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMoore"
-  void Load_store_unit::function_speculative_load_commit_genMoore (void)
-  {
-    log_begin(Load_store_unit,FUNCTION);
-    log_function(Load_store_unit,FUNCTION,_name.c_str());
-
-    if (PORT_READ(in_NRESET))
-      {
-    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-    Tcontext_t         memory_out_context_id    = 0;
-    Tcontext_t         memory_out_front_end_id  = 0;
-    Tcontext_t         memory_out_ooo_engine_id = 0;
-    Tpacket_t          memory_out_packet_id     = 0;
-    Tcontrol_t         memory_out_cancel        = 0;
-    Tcontrol_t         memory_out_write_rd      = 0;
-    Tgeneral_address_t memory_out_num_reg_rd    = 0;
-    Tgeneral_data_t    memory_out_data_rd       = 0;
-//  Tcontrol_t         memory_out_write_re      = 0;
-//  Tspecial_address_t memory_out_num_reg_re    = 0;
-//  Tspecial_data_t    memory_out_data_re       = 0;
-    Tcontrol_t         memory_out_no_sequence   = 0;
-    Texception_t       memory_out_exception     = 0;
-
-    internal_MEMORY_OUT_VAL = 0;
-
-    // Test store and load queue
-
-    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test MEMORY_OUT");
-
-    log_printf(TRACE,Load_store_unit,FUNCTION,"    * Load  queue");
-    for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++)
-//     for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++)
-      {
-// 	internal_MEMORY_OUT_PTR = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
-	internal_MEMORY_OUT_VAL = ((_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK) or
-				   (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT));
-	
-	if (internal_MEMORY_OUT_VAL)
-	  {
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
-	    internal_MEMORY_OUT_SELECT_QUEUE = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?SELECT_LOAD_QUEUE_SPECULATIVE:SELECT_LOAD_QUEUE;
-	    
-	    memory_out_context_id    = _load_queue [internal_MEMORY_OUT_PTR]._context_id;
-	    memory_out_front_end_id  = _load_queue [internal_MEMORY_OUT_PTR]._front_end_id;
-	    memory_out_ooo_engine_id = _load_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
-	    memory_out_packet_id     = _load_queue [internal_MEMORY_OUT_PTR]._packet_id ;
-	    memory_out_cancel        = _load_queue [internal_MEMORY_OUT_PTR]._cancel    ;
-	    memory_out_write_rd      = _load_queue [internal_MEMORY_OUT_PTR]._write_rd  ;
-	    memory_out_num_reg_rd    = _load_queue [internal_MEMORY_OUT_PTR]._num_reg_rd;
-
-	    Tdcache_data_t data_old = _load_queue [internal_MEMORY_OUT_PTR]._rdata;
-	    Tdcache_data_t data_new = extend<Tdcache_data_t>(_param->_size_general_data,
-							     data_old >> _load_queue [internal_MEMORY_OUT_PTR]._shift,
-							     _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed,
-							     _load_queue [internal_MEMORY_OUT_PTR]._access_size);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (old) : %.8x",data_old);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (new) : %.8x",data_new);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * address      : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._address);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * rdata        : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * shift        : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * signed?      : %d",_load_queue [internal_MEMORY_OUT_PTR]._is_load_signed);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * access_size  : %d",_load_queue [internal_MEMORY_OUT_PTR]._access_size);
-
-	    Texception_t exception      = _load_queue [internal_MEMORY_OUT_PTR]._exception;
-	    bool         have_exception = ((exception != EXCEPTION_MEMORY_NONE) and
-					   (exception != EXCEPTION_MEMORY_MISS_SPECULATION));
-
-	    // if exception, rdata content the address of load, else content read data.
-	    memory_out_data_rd       = (have_exception)?data_old:data_new;
-	    memory_out_exception     = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?EXCEPTION_MEMORY_LOAD_SPECULATIVE:exception;
-
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",exception);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",memory_out_exception);
-
-	    break; // we have find a entry !!! stop the search
-	  }
-      }
-
-    if (not internal_MEMORY_OUT_VAL)
-      {
-	log_printf(TRACE,Load_store_unit,FUNCTION,"    * Store queue");
-
-	for (uint32_t i=0; i<_param->_size_store_queue; ++i)
-	  {
-	    internal_MEMORY_OUT_PTR = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
-	    // Can retire an store instruction if :
-	    //  * state is commit
-	    //  * none load must check this store
-
-
-	    bool val_head = ((i==0) and
-			     (_store_queue [internal_MEMORY_OUT_PTR]._state       == STORE_QUEUE_COMMIT) and
-			     (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == true) and
-			     (reg_STORE_QUEUE_NB_CHECK [internal_MEMORY_OUT_PTR] == 0)
-			     );
-
-	    bool val_commit = ((_store_queue [internal_MEMORY_OUT_PTR]._state       != STORE_QUEUE_EMPTY) and
-			       (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == false));
-
-	    if (val_head or val_commit)
-	      {
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
-		
-		internal_MEMORY_OUT_VAL          = 1;
-		internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
-		
-		memory_out_context_id    = _store_queue [internal_MEMORY_OUT_PTR]._context_id;
-		memory_out_front_end_id  = _store_queue [internal_MEMORY_OUT_PTR]._front_end_id;
-		memory_out_ooo_engine_id = _store_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
-		memory_out_packet_id     = _store_queue [internal_MEMORY_OUT_PTR]._packet_id ;
-		memory_out_cancel        = _store_queue [internal_MEMORY_OUT_PTR]._cancel;
-//              memory_out_write_rd  	 
-//              memory_out_num_reg_rd	 
-		memory_out_data_rd       = _store_queue [internal_MEMORY_OUT_PTR]._address; // to the exception
-		memory_out_exception     = _store_queue [internal_MEMORY_OUT_PTR]._exception;
-		memory_out_no_sequence   = val_commit;
-		break; // find an entry
-	      }
-
-	  }
-      }
-
-    // write output
-    if (_param->_have_port_context_id)
-    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   [0], memory_out_context_id   );
-    if (_param->_have_port_front_end_id)
-    PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id );
-    if (_param->_have_port_ooo_engine_id)
-    PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id);
-    if (_param->_have_port_rob_ptr)
-    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    [0], memory_out_packet_id    );
-//  PORT_WRITE(out_MEMORY_OUT_OPERATION    [0], memory_out_operation    );
-//  PORT_WRITE(out_MEMORY_OUT_TYPE         [0], TYPE_MEMORY             );
-    PORT_WRITE(out_MEMORY_OUT_CANCEL       [0], memory_out_cancel       );
-    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     [0], memory_out_write_rd     );
-    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   [0], memory_out_num_reg_rd   );
-    PORT_WRITE(out_MEMORY_OUT_DATA_RD      [0], memory_out_data_rd      );
-//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], memory_out_write_re     );
-//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], memory_out_num_reg_re   );
-//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], memory_out_data_re      );
-    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], 0);
-    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], 0);
-    PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], 0);
-    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    [0], memory_out_exception    );
-    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  [0], memory_out_no_sequence  );// hack
-#ifdef DEBUG
-    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], memory_out_data_rd);
-#else
-    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], 0);
-#endif
-
-    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-    Tcontext_t        dcache_req_context_id = 0;
-    Tpacket_t         dcache_req_packet_id  = 0;
-    Tdcache_address_t dcache_req_address    = 0;
-    Tdcache_type_t    dcache_req_type       = 0;
-    Tdcache_data_t    dcache_req_wdata      = 0;
-
-    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test DCACHE_REQ");
-
-    internal_DCACHE_REQ_VAL = 0;
-
-    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = (*_speculative_access_queue_control)[0];
-
-    // Test store and load queue
-    if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE)
-      {
-	log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);
-
-	internal_DCACHE_REQ_VAL          = 1;
-	internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
-
-	if (_param->_have_port_dcache_context_id)
-	  {
-	    Tcontext_t context_id    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
-	    Tcontext_t front_end_id  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
-	    Tcontext_t ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
-	    
-	    dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
-				     (front_end_id <<(_param->_size_context_id)) |
-				     (context_id));
-	  }
-
-	dcache_req_packet_id  = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write);
-	dcache_req_address    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb;
-	dcache_req_type       = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation);
-
-// 	log_printf(TRACE,Load_store_unit,FUNCTION,"      * address            : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address);
-//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * mask               : %.8x",_param->_mask_address_msb);
-        log_printf(TRACE,Load_store_unit,FUNCTION,"      * dcache_req_address : %.8x",dcache_req_address);
-
-#ifdef SYSTEMC_VHDL_COMPATIBILITY
-	dcache_req_wdata      = 0;
-#endif
-      }
-    else
-      {
-	// Test an store must be commited.
-	if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE)
-	  {
-	    internal_DCACHE_REQ_VAL          = 1;
-	    internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE;
-	    
-	    if (_param->_have_port_dcache_context_id)
-	      {
-		Tcontext_t context_id    = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id;
-		Tcontext_t front_end_id  = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id;
-		Tcontext_t ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id;
-		
-		dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
-					 (front_end_id <<(_param->_size_context_id)) |
-					 (context_id));
-	      }
-
-	    // FIXME : il peut avoir plusieurs store avec le même paquet_id ... pour l'instant pas très grave car pas de retour (enfin seul les bus error sont des retours)
-	    dcache_req_packet_id  = DCACHE_REQ_IS_STORE(reg_STORE_QUEUE_PTR_READ);
-	    dcache_req_address    = _store_queue [reg_STORE_QUEUE_PTR_READ]._address;
-	    dcache_req_type       = operation_to_dcache_type(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation);
-	    dcache_req_wdata      = _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata;
-	  }
-      }
-
-    if (_param->_have_port_dcache_context_id)
-    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id);
-    PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id );
-    PORT_WRITE(out_DCACHE_REQ_ADDRESS   [0], dcache_req_address   );
-    PORT_WRITE(out_DCACHE_REQ_TYPE      [0], dcache_req_type      );
-    PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
-      }
-    else
-      {
-        // Reset
-    internal_MEMORY_OUT_VAL = 0;
-//  internal_MEMORY_OUT_PTR =0
-//  internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
-
-    internal_DCACHE_REQ_VAL = 0;
-    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = 0;
-//  internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
-      }
-
-    // Write output
-    PORT_WRITE(out_MEMORY_OUT_VAL [0], internal_MEMORY_OUT_VAL);
-    PORT_WRITE(out_DCACHE_REQ_VAL [0], internal_DCACHE_REQ_VAL);
-
-
-    log_end(Load_store_unit,FUNCTION);
-  };
-
-}; // end namespace load_store_unit
-}; // end namespace execute_unit
-}; // end namespace multi_execute_unit
-}; // end namespace execute_loop
-}; // end namespace multi_execute_loop
-}; // end namespace core
-
-}; // end namespace behavioural
-}; // end namespace morpheo              
-#endif
-//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 137)
+++ 	(revision )
@@ -1,1401 +1,0 @@
-#ifdef SYSTEMC
-/*
- * $Id$
- *
- * [ Description ]
- * 
- */
-
-#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
-#include "Behavioural/include/Identification.h"
-
-namespace morpheo                    {
-namespace behavioural {
-namespace core {
-namespace multi_execute_loop {
-namespace execute_loop {
-namespace multi_execute_unit {
-namespace execute_unit {
-namespace load_store_unit {
-
-template <typename T>
-T swapBytes (T data, uint32_t size_data, uint32_t size_access)
-{
-  uint64_t x = static_cast<uint64_t>(data);
-
-//   switch (size_data)
-//     {
-//     case 2 : // 16 bits
-//       {
-//         switch (size_access)
-//           {
-//           case 2 : 
-//             {
-//               x = ((((x>> 8)&0xff) <<  0) |
-//                    (((x>> 0)&0xff) <<  8) );
-//               break;
-//             }
-//           default :
-//             {
-//               break;
-//             }
-//           }
-//         break;
-//       }
-//     case 4 : // 32 bits
-//       {
-//         switch (size_access)
-//           {
-//           case 2 : 
-//             {
-//               x = ((((x>> 8)&0xff) <<  0) |
-//                    (((x>> 0)&0xff) <<  8) |
-//                    (((x>>24)&0xff) << 16) |
-//                    (((x>>16)&0xff) << 24) );
-//               break;
-//             }
-//           case 4 : 
-//             {
-//               x = ((((x>>24)&0xff) <<  0) |
-//                    (((x>>16)&0xff) <<  8) |
-//                    (((x>> 8)&0xff) << 16) |
-//                    (((x>> 0)&0xff) << 24) );
-//               break;
-//             }
-//           default :
-//             {
-//               break;
-//             }
-//           }
-//         break;
-//       }
-//     case 8 : // 64 bits
-//       {
-//         switch (size_access)
-//           {
-//           case 2 : 
-//             {
-//               x = ((((x>> 8)&0xff) <<  0) |
-//                    (((x>> 0)&0xff) <<  8) |
-//                    (((x>>24)&0xff) << 16) |
-//                    (((x>>16)&0xff) << 24) |
-//                    (((x>>40)&0xff) << 32) |
-//                    (((x>>32)&0xff) << 40) |
-//                    (((x>>56)&0xff) << 48) |
-//                    (((x>>48)&0xff) << 56) );
-//               break;
-//             }
-//           case 4 : 
-//             {
-//               x = ((((x>>24)&0xff) <<  0) |
-//                    (((x>>16)&0xff) <<  8) |
-//                    (((x>> 8)&0xff) << 16) |
-//                    (((x>> 0)&0xff) << 24) |
-//                    (((x>>56)&0xff) << 32) |
-//                    (((x>>48)&0xff) << 40) |
-//                    (((x>>40)&0xff) << 48) |
-//                    (((x>>32)&0xff) << 56) );
-//               break;
-//             }
-//           case 8 : 
-//             {
-//               x = ((((x>>56)&0xff) <<  0) |
-//                    (((x>>48)&0xff) <<  8) |
-//                    (((x>>40)&0xff) << 16) |
-//                    (((x>>32)&0xff) << 24) |
-//                    (((x>>24)&0xff) << 32) |
-//                    (((x>>16)&0xff) << 40) |
-//                    (((x>> 8)&0xff) << 48) |
-//                    (((x>> 0)&0xff) << 56) );
-//               break;
-//             }
-//           default :
-//             {
-//               break;
-//             }
-//           }
-//         break;
-//       }
-//     default :
-//       {
-//         break;
-//       }
-//     }
-
-
-  uint64_t y=0;
-
-  for (uint32_t i=0; i<size_data; i+=size_access)
-    {
-      uint32_t offset = i<<3;
-
-      switch (size_access)
-        {
-        case 1 :
-          {
-            y = x;
-            break;
-          }
-        case 2 : 
-          {
-            y |= ((((x>>( 8+offset))&0xff) << ( 0+offset)) |
-                  (((x>>( 0+offset))&0xff) << ( 8+offset)) );
-            break;
-          }
-        case 4 : 
-          {
-            y |= ((((x>>(24+offset))&0xff) << ( 0+offset)) |
-                  (((x>>(16+offset))&0xff) << ( 8+offset)) |
-                  (((x>>( 8+offset))&0xff) << (16+offset)) |
-                  (((x>>( 0+offset))&0xff) << (24+offset)) );
-            break;
-          }
-        case 8 : 
-          {
-            y |= ((((x>>(56+offset))&0xff) << ( 0+offset)) |
-                  (((x>>(48+offset))&0xff) << ( 8+offset)) |
-                  (((x>>(40+offset))&0xff) << (16+offset)) |
-                  (((x>>(32+offset))&0xff) << (24+offset)) |
-                  (((x>>(24+offset))&0xff) << (32+offset)) |
-                  (((x>>(16+offset))&0xff) << (40+offset)) |
-                  (((x>>( 8+offset))&0xff) << (48+offset)) |
-                  (((x>>( 0+offset))&0xff) << (56+offset)) );
-            break;
-          }
-        default :
-            {
-              break;
-            }
-        }
-    }
-
-  return static_cast<T>(y);
-}
-
-template <typename T>
-T swapBits (T data, uint32_t size_data, uint32_t size_access)
-{
-  uint8_t x = static_cast<uint8_t>(data);
-
-  uint8_t y=0;
-
-  for (uint32_t i=0; i<size_data; i+=size_access)
-    {
-      uint32_t offset = i;
-
-      switch (size_access)
-        {
-        case 1 :
-          {
-            y = x;
-            break;
-          }
-        case 2 : 
-          {
-            y |= ((((x>>( 1+offset))&0x1) << ( 0+offset)) |
-                  (((x>>( 0+offset))&0x1) << ( 1+offset)) );
-            break;
-          }
-        case 4 : 
-          {
-            y |= ((((x>>( 3+offset))&0x1) << ( 0+offset)) |
-                  (((x>>( 2+offset))&0x1) << ( 1+offset)) |
-                  (((x>>( 1+offset))&0x1) << ( 2+offset)) |
-                  (((x>>( 0+offset))&0x1) << ( 3+offset)) );
-            break;
-          }
-        case 8 : 
-          {
-            y |= ((((x>>( 7+offset))&0x1) << ( 0+offset)) |
-                  (((x>>( 6+offset))&0x1) << ( 1+offset)) |
-                  (((x>>( 5+offset))&0x1) << ( 2+offset)) |
-                  (((x>>( 4+offset))&0x1) << ( 3+offset)) |
-                  (((x>>( 3+offset))&0x1) << ( 4+offset)) |
-                  (((x>>( 2+offset))&0x1) << ( 5+offset)) |
-                  (((x>>( 1+offset))&0x1) << ( 6+offset)) |
-                  (((x>>( 0+offset))&0x1) << ( 7+offset)) );
-            break;
-          }
-        default :
-            {
-              break;
-            }
-        }
-    }
-
-  return static_cast<T>(y);
-}
-
-#undef  FUNCTION
-#define FUNCTION "Load_store_unit::function_speculative_load_commit_transition"
-  void Load_store_unit::function_speculative_load_commit_transition (void)
-  {
-    log_begin(Load_store_unit,FUNCTION);
-    log_function(Load_store_unit,FUNCTION,_name.c_str());
-
-    if (PORT_READ(in_NRESET) == 0)
-      {
-	// Reset : clear all queue
-	_speculative_access_queue_control->clear();
-
-	reg_STORE_QUEUE_PTR_READ       = 0;
-	reg_LOAD_QUEUE_CHECK_PRIORITY  = 0;
-
-	for (uint32_t i=0; i< _param->_size_store_queue             ; i++)
-          {
-            reg_STORE_QUEUE_NB_CHECK  [i] = 0;
-  	    _store_queue              [i]._state                 = STORE_QUEUE_EMPTY;
-  	    _store_queue              [i]._context_id            = 0; // not necessary
-  	    _store_queue              [i]._front_end_id          = 0; // not necessary
-  	    _store_queue              [i]._ooo_engine_id         = 0; // not necessary
-  	    _store_queue              [i]._packet_id             = 0; // not necessary
-  	    _store_queue              [i]._operation             = 0; // not necessary
-  	    _store_queue              [i]._cancel                = 0; // not necessary
-  	    _store_queue              [i]._load_queue_ptr_write  = 0; // not necessary
-  	    _store_queue              [i]._address               = 0; // not necessary
-  	    _store_queue              [i]._wdata                 = 0; // not necessary
-//	    _store_queue              [i]._write_rd              = 0; // not necessary
-//	    _store_queue              [i]._num_reg_rd            = 0; // not necessary
-  	    _store_queue              [i]._exception             = 0; // not necessary
-  	    _store_queue              [i]._send_commit           = 0; // not necessary
-          }
-
-	for (uint32_t i=0; i< _param->_size_load_queue              ; i++)
-          {
-            _load_queue               [i]._state                 = LOAD_QUEUE_EMPTY;
-            _load_queue               [i]._context_id            = 0; // not necessary
-            _load_queue               [i]._front_end_id          = 0; // not necessary
-            _load_queue               [i]._ooo_engine_id         = 0; // not necessary
-            _load_queue               [i]._packet_id             = 0; // not necessary
-            _load_queue               [i]._operation             = 0; // not necessary
-            _load_queue               [i]._cancel                = 0; // not necessary
-            _load_queue               [i]._store_queue_ptr_write = 0; // not necessary
-            _load_queue               [i]._store_queue_ptr_read  = 0; // not necessary
-            _load_queue               [i]._store_queue_empty     = 0; // not necessary
-            _load_queue               [i]._address               = 0; // not necessary
-            _load_queue               [i]._check_hit_byte        = 0; // not necessary 
-            _load_queue               [i]._check_hit             = 0; // not necessary
-            _load_queue               [i]._shift                 = 0; // not necessary
-            _load_queue               [i]._is_load_signed        = 0; // not necessary
-            _load_queue               [i]._access_size           = 0; // not necessary
-            _load_queue               [i]._rdata                 = 0; // not necessary
-            _load_queue               [i]._write_rd              = 0; // not necessary
-            _load_queue               [i]._num_reg_rd            = 0; // not necessary
-            _load_queue               [i]._exception             = 0; // not necessary
-          }
-
-	for (uint32_t i=0; i< _param->_size_speculative_access_queue; i++)
-          {
-            _speculative_access_queue [i]._state                 = SPECULATIVE_ACCESS_QUEUE_EMPTY;
-            _speculative_access_queue [i]._context_id            = 0; // not necessary
-            _speculative_access_queue [i]._front_end_id          = 0; // not necessary
-            _speculative_access_queue [i]._ooo_engine_id         = 0; // not necessary
-            _speculative_access_queue [i]._packet_id             = 0; // not necessary
-            _speculative_access_queue [i]._operation             = 0; // not necessary
-            _speculative_access_queue [i]._cancel                = 0; // not necessary
-            _speculative_access_queue [i]._load_queue_ptr_write  = 0; // not necessary
-            _speculative_access_queue [i]._store_queue_ptr_write = 0; // not necessary
-            _speculative_access_queue [i]._store_queue_ptr_read  = 0; // not necessary
-            _speculative_access_queue [i]._store_queue_empty     = 0; // not necessary
-            _speculative_access_queue [i]._address               = 0; // not necessary
-            _speculative_access_queue [i]._write_rd              = 0; // not necessary
-            _speculative_access_queue [i]._num_reg_rd            = 0; // not necessary
-            _speculative_access_queue [i]._exception             = 0; // not necessary
-          }
-      }
-    else
-      {
-        // load_queue_push if speculative_access_queue have access at the dcache, or they have an event
-	bool load_queue_push = (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE);
-
-	//================================================================
-	// Interface "MEMORY_OUT"
-	//================================================================
-
-        if ((    internal_MEMORY_OUT_VAL  == 1) and
-            (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1))
-          {
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_OUT[0] transaction");
-
-	    switch (internal_MEMORY_OUT_SELECT_QUEUE)
-	      {
-	      case SELECT_STORE_QUEUE :
-		{
-		  // =======================
-		  // ===== STORE_QUEUE =====
-		  // =======================
-		  
-		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue [%d]",internal_MEMORY_OUT_PTR);
-	    
-		  // Entry flush and increase the read pointer
-		  if (_store_queue [internal_MEMORY_OUT_PTR]._send_commit)
-		    {
-		      _store_queue [internal_MEMORY_OUT_PTR]._state = STORE_QUEUE_EMPTY;
-		      reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue;
-		    }
-		  else
-		    _store_queue [internal_MEMORY_OUT_PTR]._send_commit = true;
-
-		  break;
-		}
-	      case SELECT_LOAD_QUEUE :
-		{
-		  // ======================
-		  // ===== LOAD_QUEUE =====
-		  // ======================
-		  
-		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * load_queue  [%d]",internal_MEMORY_OUT_PTR);
-		  
-		  // Entry flush and increase the read pointer
-		  
-		  _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY;
-		  
-		  // reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
-
-		  break;
-		}
-	      case SELECT_LOAD_QUEUE_SPECULATIVE :
-		{
-		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * load_queue  [%d] (speculative)",internal_MEMORY_OUT_PTR);
-		  
-                  // !!! WARNING !!!
-                  // !!! Test special case :
-                  // !!! in a cycle an instruction can check the last store AND commit instruction
-                  // !!! also the memory_out is before the port_check
-
-		  _load_queue [internal_MEMORY_OUT_PTR]._state    = LOAD_QUEUE_CHECK;
-		  // NOTE : a speculative load write in the register file.
-		  // if the speculation is a miss, write_rd is re set at 1.
-		  _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0;
-
-#ifdef STATISTICS
-                  if (usage_is_set(_usage,USE_STATISTICS))
-                    (*_stat_nb_inst_load_commit_speculative) ++;
-#endif
-
-		  break;
-		}
-
-		break;
-	      }
-	  }
-
-	//================================================================
-	// Interface "PORT_CHECK"
-	//================================================================
-	
-	// Plusieurs moyens de faire la verification de dépendance entre les loads et les stores.
-	//  1) un load ne peut vérifier qu'un store par cycle. Dans ce cas port_check <= size_load_queue
-	//  2) un load tente de vérifier le maximum de store par cycle. Dans ce cas ce n'est pas du pointeur d'écriture qu'il lui faut mais un vecteur de bit indiquant quel store à déjà été testé. De plus il faut un bit indiquant qu'il y a un match mais que ce n'est pas forcément le premier.
-
-	// solution 1)
- 	log_printf(TRACE,Load_store_unit,FUNCTION,"  * CHECK");
-	for (uint32_t i=0, nb_check=0; (nb_check<_param->_nb_port_check) and (i<_param->_size_load_queue); i++)
-	  {
-            // Get an index from load queue
-	    uint32_t index_load_queue = (i + reg_LOAD_QUEUE_CHECK_PRIORITY)%_param->_size_load_queue;
-
-            // Test if this load must ckecked store queue
-	    if (((_load_queue[index_load_queue]._state == LOAD_QUEUE_WAIT_CHECK) or
-		 (_load_queue[index_load_queue]._state == LOAD_QUEUE_COMMIT_CHECK) or
-		 (_load_queue[index_load_queue]._state == LOAD_QUEUE_CHECK)) and
-		is_operation_memory_load(_load_queue[index_load_queue]._operation))
-	      {
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * Find a load : %d",index_load_queue);
-
-		nb_check++; // use one port
-
-		// find a entry that it need a check
-		Tlsq_ptr_t store_queue_ptr_write = _load_queue[index_load_queue]._store_queue_ptr_write;
-		Tlsq_ptr_t store_queue_ptr_read  = _load_queue[index_load_queue]._store_queue_ptr_read ;
- 		Tlsq_ptr_t store_queue_empty     = _load_queue[index_load_queue]._store_queue_empty    ;
-// 		Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write;
-
-                // Init variable
-		bool       end_check    = false;
-		bool       change_state = false;
-		bool       next         = false;
-
-		// At the first store queue empty, stop check.
-		// Explication :
-		//  * rename logic keep a empty case in the store queue (also size_store_queue > 1)
-		//  * when a store is out of store queue, also it was in head of re order buffer. Also, they are none previous load.
-
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_ptr_write    : %d",store_queue_ptr_write);
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_ptr_read     : %d",store_queue_ptr_read );
-// 		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_empty        : %d",store_queue_empty );
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * reg_STORE_QUEUE_PTR_READ : %d",reg_STORE_QUEUE_PTR_READ);
-
- 		if ((store_queue_ptr_write ==     store_queue_ptr_read) or
-		    (store_queue_ptr_write == reg_STORE_QUEUE_PTR_READ))
-// 		if (store_queue_empty)
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write == store_queue_ptr_read");
-		    end_check    = true;
-		    change_state = true;
-		  }
-		else
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write != store_queue_ptr_read");
-
-		    store_queue_ptr_write = (store_queue_ptr_write-1)%(_param->_size_store_queue); // store_queue_ptr_write target the next slot to write, also the slot is not significatif when the load is renaming
-
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write : %d",store_queue_ptr_write);
-		    
-                    // switch on store_queue state
-		    switch (_store_queue[store_queue_ptr_write]._state)
-		      {
-		      case STORE_QUEUE_VALID_NO_SPECULATIVE : 
-		      case STORE_QUEUE_COMMIT :
-		      case STORE_QUEUE_VALID_SPECULATIVE :
-			{
-			  
-			  log_printf(TRACE,Load_store_unit,FUNCTION,"      * store have a valid entry");
-			  
-			  // TODO : MMU - nous considérons que les adresses sont physique
-			  bool test_thread_id = true;
-			  
-			  // Test thread id
-			  if (_param->_have_port_context_id)
-			    test_thread_id &= (_load_queue[index_load_queue]._context_id    == _store_queue[store_queue_ptr_write]._context_id);
-			  if (_param->_have_port_front_end_id)
-			    test_thread_id &= (_load_queue[index_load_queue]._front_end_id  == _store_queue[store_queue_ptr_write]._front_end_id);
-			  if (_param->_have_port_ooo_engine_id)
-			    test_thread_id &= (_load_queue[index_load_queue]._ooo_engine_id == _store_queue[store_queue_ptr_write]._ooo_engine_id);
-			  
-			  if (test_thread_id)
-			    {
-			      // the load and store are in the same thread. Now, we must test address.
-
-			      log_printf(TRACE,Load_store_unit,FUNCTION,"        * load and store is the same thread.");
-			      Tdcache_address_t load_addr  = _load_queue [index_load_queue ]._address;
-			      Tdcache_address_t store_addr = _store_queue[store_queue_ptr_write]._address;
-			      
-			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * load_addr                     : %.8x.",load_addr );
-			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * store_addr                    : %.8x.",store_addr);
-			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * load_addr  & mask_address_msb : %.8x.",load_addr  & _param->_mask_address_msb);
-			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * store_addr & mask_address_msb : %.8x.",store_addr & _param->_mask_address_msb);
-			      // Test if the both address target the same "word"
-			      if ((load_addr  & _param->_mask_address_msb) == 
-				  (store_addr & _param->_mask_address_msb))
-				{
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * address_msb is the same.");
-				  // all case - [] : store, () : load
-				  // (1) store_max >= load_max and store_min <= load_min  ...[...(...)...]... Ok - inclusion in store
-				  // (2) store_min >  load_max                            ...[...]...(...)... Ok - no conflit
-				  // (3) store_max <  load_min                            ...(...)...[...]... Ok - no conflit
-				  // (4) store_max <  load_max and store_min >  load_min  ...(...[...]...)... Ko - inclusion in load
-				  // (5) store_max >= load_max and store_min >  load_min  ...[...(...]...)... Ko - conflit
-				  // (6) store_max <  load_max and store_min <= load_min  ...(...[...)...]... Ko - conflit
-				  // but :
-				  // load in the cache is a word !
-				  // the mask can be make when the load is commited. Also, the rdata content a full word.
-				  // the only case is (4)
-				  
-                                  // Read data
-                                  bool is_big_endian = true;
-
-				  Tgeneral_data_t   load_data      = _load_queue [index_load_queue ]._rdata  ;
-				  Tgeneral_data_t   store_data     = _store_queue[store_queue_ptr_write]._wdata  ;
-                                  Tdcache_address_t check_hit_byte = _load_queue [index_load_queue ]._check_hit_byte;
-                                  Tcontrol_t        check_hit      = _load_queue [index_load_queue ]._check_hit;
-                                  uint32_t          load_size_access  = memory_size(_load_queue [index_load_queue ]._operation)>>3;
-                                  uint32_t          store_size_access = memory_size(_store_queue[store_queue_ptr_write]._operation)>>3;
-
-                                  log_printf(TRACE,Load_store_unit,FUNCTION,"            * is_big_endian           : %d",is_big_endian);
-                                  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data               : 0x%.8x",load_data);
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_data              : 0x%.8x",store_data);
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte          : %x",check_hit_byte);
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit               : %d",check_hit);
-
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_size_access        : %d",load_size_access );
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_size_access       : %d",store_size_access);
-
-                                  if (is_big_endian)
-                                    {
-                                      // swap in little endian
-                                      load_data      = swapBytes<Tgeneral_data_t  >(load_data     , _param->_size_general_data>>3,load_size_access);
-                                      store_data     = swapBytes<Tgeneral_data_t  >(store_data    , _param->_size_general_data>>3,store_size_access);
-                                      check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access);
-                                      
-                                      
-                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data      (swap 1) : 0x%.8x",load_data);
-                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_data     (swap 1) : 0x%.8x",store_data);
-                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte (swap 1) : %x",check_hit_byte);
-                                    }
-
-                                  uint32_t store_nb_byte     = (1<<memory_access(_store_queue[store_queue_ptr_write]._operation));
-
-                                  // Take interval to the store
-				  uint32_t store_num_byte_min = (store_addr & _param->_mask_address_lsb);
-				  uint32_t store_num_byte_max = store_num_byte_min+store_nb_byte;
-
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_num_byte_min      : %d",store_num_byte_min);
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_num_byte_max      : %d",store_num_byte_max);
-
-//                                   uint32_t load_nb_byte      = (1<<memory_access(_load_queue[index_load_queue]._operation));
-
-// 				  uint32_t load_num_byte_min = (load_addr & _param->_mask_address_lsb);
-// 				  uint32_t load_num_byte_max = load_num_byte_min+load_nb_byte;
-
-// 				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_num_byte_min       : %d",load_num_byte_min);
-// 				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_num_byte_max       : %d",load_num_byte_max);
-
-// 				  for (uint32_t num_load_byte=load_num_byte_min; num_load_byte<load_num_byte_max; num_load_byte ++)
-// 				    {
-//                                       // Make a mask
-//                                       uint32_t num_store_byte = num_load_byte;
-                                      
-
-
-				  // The bypass is checked byte per byte
-                                  // Is same endianness : because to change endianness, we must write in special register. Also the pipeline is flushed.
-				  for (uint32_t num_store_byte=store_num_byte_min; num_store_byte<store_num_byte_max; num_store_byte ++)
-				    {
-                                      // Make a mask
-                                      uint32_t num_load_byte = num_store_byte;
-
-//                                       if (is_big_endian)
-//                                         {
-//                                           // sd 0 : 0 1 2 3 4 5 6 7
-//                                           // ld 0 : 0 1 2 3 4 5 6 7 >>  0 
-//                                           // lw 0 :         0 1 2 3 >>  0 -4
-//                                           // lw 4 : 4 5 6 7         >> 32 +4
-//                                           // lh 0 :             0 1 >>  0 -6
-//                                           // lh 2 :         2 3     >> 16 -2
-//                                           // lh 4 :     4 5         >> 32 +2
-//                                           // lh 6 : 6 7             >> 48 +6
-//                                           // lb 0 :               0 >>  0 -7
-//                                           // lb 1 :             1   >>  8 -5
-//                                           // lb 2 :           2     >> 16 -3
-//                                           // lb 3 :         3       >> 24 -1
-//                                           // lb 4 :       4         >> 32 +1
-//                                           // lb 5 :     5           >> 40 +3
-//                                           // lb 6 :   6             >> 48 +5
-//                                           // lb 7 : 7               >> 56 +7
-
-//                                           // diff : (store_nb_byte + load_nb_byte) - 2*nb_load_byte*((num_store_byte+1)
-
-//                                           // store duplicate = all store access can be see as full size_data store
-// //                                           uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load_queue ]._operation));
-
-// //                                           int32_t diff = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1));
-
-// //                                           num_load_byte =num_store_byte+diff;
-
-// //                                           log_printf(TRACE,Load_store_unit,FUNCTION,"              * load_nb_byte   : %d",load_nb_byte);
-// //                                           log_printf(TRACE,Load_store_unit,FUNCTION,"              * diff           : %d",diff);
-
-
-//                                           num_load_byte = num_store_byte;
-//                                         }
-//                                       else
-//                                         {
-//                                           // sd 0 : 0 1 2 3 4 5 6 7
-//                                           // ld 0 : 0 1 2 3 4 5 6 7 >>  0
-//                                           // lw 0 :         4 5 6 7 >>  0
-//                                           // lw 4 : 0 1 2 3         >> 32
-//                                           // lh 0 :             6 7 >>  0
-//                                           // lh 2 :         4 5     >> 16
-//                                           // lh 4 :     2 3         >> 32
-//                                           // lh 6 : 0 1             >> 48
-//                                           // lb 0 :               7 >>  0
-//                                           // lb 1 :             6   >>  8
-//                                           // lb 2 :           5     >> 16
-//                                           // lb 3 :         4       >> 24
-//                                           // lb 4 :       3         >> 32
-//                                           // lb 5 :     2           >> 40
-//                                           // lb 6 :   1             >> 48
-//                                           // lb 7 : 0               >> 56
-                                          
-//                                           num_load_byte = num_store_byte;
-//                                         }
-
-				      uint32_t mask  = 1<<num_load_byte;
-
-				      log_printf(TRACE,Load_store_unit,FUNCTION,"              * num_store_byte : %d",num_store_byte);
-				      log_printf(TRACE,Load_store_unit,FUNCTION,"              * num_load_byte  : %d",num_load_byte);
-				      log_printf(TRACE,Load_store_unit,FUNCTION,"              * mask           : %d",mask);
-
-				      // Accept the bypass if :
-                                      //   * they have not a previous bypass with an another store
-                                      //   * it's a valid request of load
-				      if ((check_hit_byte&mask)==0)
-					{
-                                          // Note : Store is duplicate = all store access can be see as full size_data store
-
-                                          uint32_t num_store_bit_min = num_store_byte<<3; //*8
-//                                        uint32_t num_store_bit_max = num_store_bit_min+8-1;
-                                          uint32_t num_load_bit_min  = num_load_byte <<3; //*8
-                                          uint32_t num_load_bit_max  = num_load_bit_min+8-1;
-
-					  log_printf(TRACE,Load_store_unit,FUNCTION,"              * bypass !!!");
-//                                        log_printf(TRACE,Load_store_unit,FUNCTION,"              * interval store : [%d:%d]",num_store_bit_max,num_store_bit_min);
-                                          log_printf(TRACE,Load_store_unit,FUNCTION,"              * interval store : [..:%d]",num_store_bit_min);
-                                          log_printf(TRACE,Load_store_unit,FUNCTION,"              * interval load  : [%d:%d]",num_load_bit_max,num_load_bit_min);
-					  log_printf(TRACE,Load_store_unit,FUNCTION,"                * rdata_old : 0x%.8x", load_data);
-
-					  load_data = ((((store_data>>num_store_bit_min) & 0xff) << num_load_bit_min) |
-                                                       mask_not<Tdcache_data_t>(load_data,num_load_bit_max,num_load_bit_min));
-
-					  check_hit_byte |= mask;
-					  check_hit       = 1;
-					  change_state = true;
-
-					  log_printf(TRACE,Load_store_unit,FUNCTION,"                * rdata_new : 0x%.8x", load_data);
-					}
-				    }
-
-                                  if (is_big_endian)
-                                    {
-                                      // swap in little endian
-                                      load_data      = swapBytes<Tgeneral_data_t  >(load_data     , _param->_size_general_data>>3,load_size_access);
-                                      check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access);
-                                      
-                                      
-                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data      (swap 2) : 0x%.8x",load_data);
-                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte (swap 2) : %x",check_hit_byte);
-                                    }
-
-				  _load_queue[index_load_queue]._rdata          = load_data;
-                                  _load_queue[index_load_queue]._check_hit_byte = check_hit_byte;
-                                  _load_queue[index_load_queue]._check_hit      = check_hit;
-
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data  (after) : 0x%.8x",load_data);
-
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit          : %x",check_hit);
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte     : %x",check_hit_byte);
-
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * mask_end_check     : %x",(-1& _param->_mask_address_lsb));
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * mask_check_hit_byte: %x",_param->_mask_check_hit_byte);
-				  // The check is finish if all bit is set
-				  end_check = (_load_queue[index_load_queue]._check_hit_byte == _param->_mask_check_hit_byte);
-
-				}
-			    }
-			  
-			  next = true;
-			  break;
-			}
-		      case STORE_QUEUE_EMPTY :
-		      case STORE_QUEUE_NO_VALID_NO_SPECULATIVE :
-			{
-			  log_printf(TRACE,Load_store_unit,FUNCTION,"      * store have an invalid entry");
-			  break;
-			}
-		      }
-		  }
-
-		if (next)
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * next");
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * new store_queue_ptr_write : %d",store_queue_ptr_write);
-
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * update reg_STORE_QUEUE_NB_CHECK");
-#ifdef DEBUG
-                    if (reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write] == 0)
-                      throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
-#endif
-
-                    reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write] --;
-
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 1 [%d] <- %d", store_queue_ptr_write,reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write]);
-
-		    if ((store_queue_ptr_write ==     store_queue_ptr_read) or
-			(store_queue_ptr_write == reg_STORE_QUEUE_PTR_READ))
-		      {
-// 			store_queue_empty = true;
-			end_check         = true;
-			change_state      = true;
-		      }
-
-// 		    if (_load_queue[index_load_queue]._store_queue_ptr_write == 0)
-// 		      _load_queue[index_load_queue]._store_queue_ptr_write = _param->_size_store_queue-1;
-// 		    else
-// 		      _load_queue[index_load_queue]._store_queue_ptr_write --;
-		    _load_queue[index_load_queue]._store_queue_ptr_write = store_queue_ptr_write; // because the index store have be decrease
- 		    _load_queue[index_load_queue]._store_queue_empty     = store_queue_empty; // because the index store have be decrease
-
-		    // FIXME : peut n'est pas obliger de faire cette comparaison. Au prochain cycle on le détectera que les pointeur sont égaux. Ceci évitera d'avoir deux comparateurs avec le registre "store_queue_ptr_read"
-		  }
-
-		if (change_state)
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * change_state");
-                    log_printf(TRACE,Load_store_unit,FUNCTION,"              * end_check : %d",end_check);
-
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * state old : %s",toString(_load_queue[index_load_queue]._state).c_str());
-
-		    switch (_load_queue[index_load_queue]._state)
-		      {
-		      case LOAD_QUEUE_WAIT_CHECK   : 
-                        {
-			  if (end_check)
-                            _load_queue[index_load_queue]._state = LOAD_QUEUE_WAIT  ; 
-                          break;
-                        }
-		      case LOAD_QUEUE_COMMIT_CHECK : 
-			{
-			  if (end_check)
-			    _load_queue[index_load_queue]._state = LOAD_QUEUE_COMMIT; 
-			  else
-			    _load_queue[index_load_queue]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end
-			  break;
-			}
-		      case LOAD_QUEUE_CHECK        : 
-			{
-			  if (end_check)
-			    _load_queue[index_load_queue]._state     = LOAD_QUEUE_COMMIT;
-
-			  // check find a bypass. A speculative load have been committed : report a speculation miss.
-			  if ((_load_queue[index_load_queue]._check_hit != 0) and 
-                              (_load_queue[index_load_queue]._write_rd  == 0) // is commit
-                              )
-			    {
-			      _load_queue[index_load_queue]._exception = EXCEPTION_MEMORY_MISS_SPECULATION;
-			      _load_queue[index_load_queue]._write_rd  = 1; // write the good result
-
-#ifdef STATISTICS
-                              if (usage_is_set(_usage,USE_STATISTICS))
-                                (*_stat_nb_inst_load_commit_miss) ++;
-#endif
-			    }
-			  
-			  break;
-			}
-		      default : break;
-		      }
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * state new : %s",toString(_load_queue[index_load_queue]._state).c_str());
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * exception : %d",_load_queue[index_load_queue]._exception);
-
-                    if (end_check//  and not store_queue_empty
-			)
-                      {
-                        log_printf(TRACE,Load_store_unit,FUNCTION,"                * end check, decrease all nb_check");
-                        
-                        uint32_t i=store_queue_ptr_write;
-                        while (i!=store_queue_ptr_read)
-                          {
-                            i=((i==0)?_param->_size_store_queue:i)-1;
-                            
-#ifdef DEBUG
-                            if (reg_STORE_QUEUE_NB_CHECK [i] == 0)
-                              throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
-#endif
-			    
-                            reg_STORE_QUEUE_NB_CHECK [i] --;
-
-			    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 2 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
-
-                            //i=(i+1)%_param->_size_store_queue;
-                          }
-			
-			_load_queue[index_load_queue]._store_queue_empty = true; // end of check
-                      }
-		  }
-	      }
-	    // else : don't use a port
-	  }
-	
-	//================================================================
-	// Interface "MEMORY_IN"
-	//================================================================
-	
-        if ((PORT_READ(in_MEMORY_IN_VAL [internal_MEMORY_IN_PORT]) == 1) and
-            (    internal_MEMORY_IN_ACK  == 1))
-          {
-            log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_IN [%d]",internal_MEMORY_IN_PORT);
-
-	    // Test operation :
-	    //~~~~~~~~~~~~~~~~~
-	    //  store  in store_queue
-	    //  load   in speculation_access_queue
-	    //  others in speculation_access_queue
-
-#ifdef DEBUG_TEST
-	    if (PORT_READ(in_MEMORY_IN_TYPE [internal_MEMORY_IN_PORT]) != TYPE_MEMORY)
-	      throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'");
-#endif
-	    Toperation_t    operation            = PORT_READ(in_MEMORY_IN_OPERATION[internal_MEMORY_IN_PORT]);
-	    Tcontrol_t      cancel               = PORT_READ(in_MEMORY_IN_CANCEL   [internal_MEMORY_IN_PORT]);
-	    Tgeneral_data_t address              = (PORT_READ(in_MEMORY_IN_IMMEDIAT[internal_MEMORY_IN_PORT]) +
-						    PORT_READ(in_MEMORY_IN_DATA_RA [internal_MEMORY_IN_PORT]));
-	    bool            exception_alignement = (mask_memory_access(operation) & address) != 0;
-						    
-	    if (is_operation_memory_store(operation) == true)
-	      {
-		// =======================
-		// ===== STORE_QUEUE =====
-		// =======================
-		// There a two store request type :
-		//   - first is operation with address and data
-		//   - second is the information of re order buffer : the store become not speculative and can access at the data cache
-
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue");
-		log_printf(TRACE,Load_store_unit,FUNCTION,"      * PUSH");
-		
-		// Write pointer is define in rename stage :
-		Tlsq_ptr_t           index         = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
-		log_printf(TRACE,Load_store_unit,FUNCTION,"      * index         : %d",index);
-		
-		// Need read : state and exception.
-		Tstore_queue_state_t old_state     = _store_queue [index]._state;
-		Tstore_queue_state_t new_state     = old_state;
-		bool                 update_info   = false;
-
-		Texception_t         old_exception = _store_queue [index]._exception;
-		Texception_t         new_exception = old_exception;
-
-		// Compute next state
-		switch (old_state)
-		  {
-		  case STORE_QUEUE_EMPTY                   :
-		    {
-		      if (is_operation_memory_store_head(operation) == true)
-			{
-			  new_state = STORE_QUEUE_NO_VALID_NO_SPECULATIVE;
-
-			  // test if is a speculation
-			  if (operation == OPERATION_MEMORY_STORE_HEAD_KO)
-			    new_exception = EXCEPTION_MEMORY_MISS_SPECULATION;
-			  else
-			    new_exception = EXCEPTION_MEMORY_NONE;
-			}
-		      else
-			{
-			  new_state = STORE_QUEUE_VALID_SPECULATIVE;
-
-			  // Test if have an exception
-			  if (exception_alignement == true)
-			    new_exception = EXCEPTION_MEMORY_ALIGNMENT;
-			  else
-			    new_exception = EXCEPTION_MEMORY_NONE;
-
-			  update_info = true;
-			}
-		      break;
-		    }
-		  case STORE_QUEUE_NO_VALID_NO_SPECULATIVE :
-		    {
-#ifdef DEBUG_TEST
-		      if (is_operation_memory_store_head(operation) == true)
-			throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_NO_VALID_NO_SPECULATIVE\", also a previous store_head have been receiveid. But this operation is a store_head."));
-#endif
-		      // Test if have a new exception (priority : miss_speculation)
-		      if ((exception_alignement == true) and (old_exception == EXCEPTION_MEMORY_NONE))
-			new_exception = EXCEPTION_MEMORY_ALIGNMENT;
-		      
-		      if (new_exception != EXCEPTION_MEMORY_NONE)
-			new_state = STORE_QUEUE_COMMIT;
-		      else
-			new_state = STORE_QUEUE_VALID_NO_SPECULATIVE;
-		      
-		      update_info = true;
-		      break;
-		    }
-		  case STORE_QUEUE_VALID_SPECULATIVE       :
-		    {
-#ifdef DEBUG_TEST
-		      if (is_operation_memory_store_head(operation) == false)
-			throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_VALID_SPECULATIVE\", also a previous access with register and address have been receiveid. But this operation is a not store_head."));
-#endif
-		      if (operation == OPERATION_MEMORY_STORE_HEAD_KO)
-			new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; // great prioritary
-		      
-		      if (new_exception != EXCEPTION_MEMORY_NONE)
-			new_state = STORE_QUEUE_COMMIT;
-		      else
-			new_state = STORE_QUEUE_VALID_NO_SPECULATIVE;
-		      
-		      break;
-		    }
-		  case STORE_QUEUE_VALID_NO_SPECULATIVE    :
-		  case STORE_QUEUE_COMMIT                  :
-		    {
-		      throw ERRORMORPHEO(FUNCTION,"<Load_store_unit::function_speculative_load_commit_transition> Invalid state and operation");
-		    }
-		  }
-
-		_store_queue [index]._state     = new_state;
-		_store_queue [index]._exception = new_exception;
-		
-		if (update_info == true)
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * Update information");
-
-		    _store_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID   [internal_MEMORY_IN_PORT]);
-		    _store_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
-		    _store_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
-		    _store_queue [index]._packet_id            = (not _param->_have_port_rob_ptr      )?0:PORT_READ(in_MEMORY_IN_PACKET_ID    [internal_MEMORY_IN_PORT]);
-		    _store_queue [index]._operation            = operation;
-		    _store_queue [index]._cancel               = cancel   ;
-		    _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
-		    _store_queue [index]._address              = address;
-		    _store_queue [index]._send_commit          = false;
-
-		    // reordering data
-		    _store_queue [index]._wdata                = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0); 
-//                  _store_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  [internal_MEMORY_IN_PORT]);
-		  }
-	      }
-	    else
-	      {
-		// ====================================
-		// ===== SPECULATIVE_ACCESS_QUEUE =====
-		// ====================================
-
-		// In speculative access queue, they are many type's request
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue");
-		log_printf(TRACE,Load_store_unit,FUNCTION,"      * PUSH");
-		
-		// Write in reservation station
-		uint32_t     index = _speculative_access_queue_control->push();
-
-		log_printf(TRACE,Load_store_unit,FUNCTION,"      * index : %d", index);
-
-		Texception_t exception;
-
-		if (exception_alignement == true)
-		  exception = EXCEPTION_MEMORY_ALIGNMENT;
-		else
-		  exception = EXCEPTION_MEMORY_NONE;
-				
-		// if exception, don't access at the cache
-		// NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits)
-		_speculative_access_queue [index]._state                = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE;
-		_speculative_access_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID   [internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._packet_id            = (not _param->_have_port_rob_ptr      )?0:PORT_READ(in_MEMORY_IN_PACKET_ID    [internal_MEMORY_IN_PORT]);
-
-		_speculative_access_queue [index]._operation            = operation;
-		_speculative_access_queue [index]._cancel               = cancel   ;
-		_speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._store_queue_ptr_read = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_READ [internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._store_queue_empty    = PORT_READ(in_MEMORY_IN_STORE_QUEUE_EMPTY    [internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._address              = address;
-		// NOTE : is operation is a load, then they are a result and must write in the register file
-		_speculative_access_queue [index]._write_rd             = is_operation_memory_load(operation);
-		_speculative_access_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  [internal_MEMORY_IN_PORT]);
-
-		_speculative_access_queue [index]._exception            = exception;
-	      }
-	  }
-
-	//================================================================
-	// Interface "DCACHE_REQ"
-	//================================================================
-        if ((    internal_DCACHE_REQ_VAL  == 1) and
-            (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1))
-          {
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_REQ [0]");
-
-	    switch (internal_DCACHE_REQ_SELECT_QUEUE)
-	      {
-	      case SELECT_STORE_QUEUE :
-		{
-		  // =======================
-		  // ===== STORE_QUEUE =====
-		  // =======================
-		  
-		  // Entry flush and increase the read pointer
-		  
-		  _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_COMMIT;
-
-#if defined(DEBUG) and defined(DEBUG_Load_store_unit) and (DEBUG_Load_store_unit == true)
-		  if (log_file_generate)
-	            {
-	              // log file
-                      Tcontext_t num_thread    = get_num_thread(_store_queue [reg_STORE_QUEUE_PTR_READ]._context_id   , _param->_size_context_id   ,
-                                                                _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id , _param->_size_front_end_id ,
-                                                                _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id, _param->_size_ooo_engine_id);
-
-	              memory_log_file [num_thread] 
-	            	<< "[" << simulation_cycle() << "] "
-	            	<< std::hex
-                        << "@ 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _store_queue [reg_STORE_QUEUE_PTR_READ]._address << " -[ Write ]-> 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata << " "
-	            	<< std::dec
-	            	<< "{" << toString(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation) << "}";
-	              
-	              memory_log_file [num_thread] << std::endl;
-	            }
-#endif	    
-
-
-		  break;
-		}
-	      case SELECT_LOAD_QUEUE_SPECULATIVE :
-		{
-		  // =========================================
-		  // ===== SELECT_LOAD_QUEUE_SPECULATIVE =====
-		  // =========================================
-
-		  load_queue_push = true;
-		  break;
-		}
-	      case SELECT_LOAD_QUEUE :
-		{
-		  throw ERRORMORPHEO(FUNCTION,_("Invalid selection"));
-		  break;
-		}
-
-		break;
-	      }
-	  }
-
-	if (load_queue_push)
-	  {
-            log_printf(TRACE,Load_store_unit,FUNCTION,"  * load_queue_push");
-
-	    Tlsq_ptr_t   ptr_write = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write;
-	    Toperation_t operation = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation;
-	    Texception_t exception = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._exception;
-	    bool         have_exception = (exception != EXCEPTION_MEMORY_NONE);
-            bool         need_check= false;
-            Tlsq_ptr_t   store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;
-            Tlsq_ptr_t   store_queue_ptr_read  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_read ;
-            Tcontrol_t   store_queue_empty     = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_empty    ;
-	    
-	    if (have_exception)
-	      _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT;
-	    else
-	      {
-		if (have_dcache_rsp(operation))
-		  {
-		    // load and synchronisation
-		    if (must_check(operation) and not store_queue_empty)
-		      {
-			// load
-                        need_check = true;
-			
-			_load_queue [ptr_write]._state = LOAD_QUEUE_WAIT_CHECK;
-		      }
-		    else
-		      {
-			// synchronisation
-			_load_queue [ptr_write]._state = LOAD_QUEUE_WAIT;
-		      }
-		  }
-		else
-		  {
-		    // lock, prefecth, flush and invalidate
-		    _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT;
-		  }
-	      }
-
-	    Tdcache_address_t address        = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;
-	    Tdcache_address_t address_lsb    = (address & _param->_mask_address_lsb);
-	    Tdcache_address_t check_hit_byte = gen_mask_not<Tdcache_address_t>(address_lsb+(memory_size(operation)>>3)-1,address_lsb) & _param->_mask_check_hit_byte;
-
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * address                 : 0x%.8x", address);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * address_lsb             : 0x%.8x", address_lsb);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * operation               : %d", operation);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * memory_size             : %d", memory_size(operation));
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * check_hit_byte          : 0x%x", check_hit_byte);
-
-	    _load_queue [ptr_write]._context_id            = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
-	    _load_queue [ptr_write]._front_end_id          = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
-	    _load_queue [ptr_write]._ooo_engine_id         = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
-	    _load_queue [ptr_write]._packet_id             = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._packet_id;
-	    _load_queue [ptr_write]._operation             = operation;
-	    _load_queue [ptr_write]._cancel                = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._cancel;
-	    _load_queue [ptr_write]._store_queue_ptr_write = store_queue_ptr_write;
-	    _load_queue [ptr_write]._store_queue_ptr_read  = store_queue_ptr_read ;
- 	    _load_queue [ptr_write]._store_queue_empty     = store_queue_empty    ;
-	    _load_queue [ptr_write]._address               = address;
-	    _load_queue [ptr_write]._check_hit_byte        = check_hit_byte;
-	    _load_queue [ptr_write]._check_hit             = 0;
-	    _load_queue [ptr_write]._shift                 = address_lsb<<3;// *8
-	    _load_queue [ptr_write]._is_load_signed        = is_operation_memory_load_signed(operation);
-	    _load_queue [ptr_write]._access_size           = memory_size(operation);
-	    // NOTE : if have an exception, must write in register, because a depend instruction wait the load data.
-	    _load_queue [ptr_write]._write_rd              = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._write_rd             ;
-	    _load_queue [ptr_write]._num_reg_rd            = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._num_reg_rd           ;
-	    _load_queue [ptr_write]._exception             = exception;
-	    _load_queue [ptr_write]._rdata                 = address; // to the exception
-	    
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue");
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * POP[%d]",(*_speculative_access_queue_control)[0]);
-	    
-	    _speculative_access_queue [(*_speculative_access_queue_control)[0]]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY;
-	    
-	    _speculative_access_queue_control->pop();
-
-#ifdef STATISTICS
-            if (usage_is_set(_usage,USE_STATISTICS))
-              (*_stat_nb_inst_load) ++;
-#endif
-
-            // Only load need check
-            if (need_check//  and not store_queue_empty
-		)
-//             if (is_operation_memory_load(_load_queue [ptr_write]._operation))
-              {
-                log_printf(TRACE,Load_store_unit,FUNCTION,"    * update nb_check");
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_ptr_write : %d",store_queue_ptr_write);
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_ptr_read  : %d",store_queue_ptr_read );
-		log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_empty     : %d",store_queue_empty    );
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      * reg_STORE_QUEUE_PTR_READ  : %d",reg_STORE_QUEUE_PTR_READ);
-                
-                uint32_t i=store_queue_ptr_write;
-                while (i!=store_queue_ptr_read)
-                  {
-                    i=((i==0)?_param->_size_store_queue:i)-1;
-                    
-                    log_printf(TRACE,Load_store_unit,FUNCTION,"      * i                         : %d",i);
-                    
-                    reg_STORE_QUEUE_NB_CHECK [i] ++;
-
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 3 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
-                  }
-              }
-          }
-
-	//================================================================
-	// Interface "DCACHE_RSP"
-	//================================================================
-        if ((PORT_READ(in_DCACHE_RSP_VAL[0])== 1) and
-            (    internal_DCACHE_RSP_ACK == 1))
-          {
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_RSP [0]");
-
-	    // don't use context_id : because there are one queue for all thread
-	    //Tcontext_t      context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID[0]); 
-	    Tpacket_t       packet_id  = PORT_READ(in_DCACHE_RSP_PACKET_ID [0]);
-	    Tdcache_data_t  rdata      = PORT_READ(in_DCACHE_RSP_RDATA     [0]);
-	    Tdcache_error_t error      = PORT_READ(in_DCACHE_RSP_ERROR     [0]);
-
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * original packet_id : %d"  , packet_id);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * packet_id          : %d"  , packet_id>>1);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * rdata              : %.8x", rdata);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * error              : %d"  , error);
-	    
-	    if (DCACHE_RSP_IS_LOAD(packet_id) == 1)
-	      {
-		packet_id >>= 1;
-
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * packet is a LOAD");
- 
-#ifdef DEBUG_TEST
-		if (not have_dcache_rsp(_load_queue [packet_id]._operation))
-		  throw ERRORMORPHEO(FUNCTION,_("Receive of respons, but the corresponding operation don't wait a respons."));
-#endif
-
-                Tdcache_data_t data = _load_queue [packet_id]._rdata;
-
-                log_printf(TRACE,Load_store_unit,FUNCTION,"    * data construction");
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      * data from cache     : 0x%.8x",rdata);
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      * data (before)       : 0x%.8x", data);
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      * check_hit_byte      : 0x%x"  ,_load_queue [packet_id]._check_hit_byte);
-                for (uint32_t i=0;i<(_param->_size_general_data>>3)/*8*/; ++i)
-                  // Test if this byte has been checked
-                  if ((_load_queue [packet_id]._check_hit_byte & (1<<i)) == 0)
-                    {
-                      log_printf(TRACE,Load_store_unit,FUNCTION,"      * no previous check ]%d:%d]",(i+1)<<3,i<<3);
-                      data = insert<Tdcache_data_t>(data,rdata,((i+1)<<3)-1,i<<3);
-                    }
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      * data (after)        : 0x%.8x", data);
-                
-                _load_queue [packet_id]._rdata = data;
-		
-#if defined(DEBUG) and defined(DEBUG_Load_store_unit) and (DEBUG_Load_store_unit == true)
-		if (log_file_generate)
-		  {
-		    // log file
-		    Tcontext_t num_thread    = get_num_thread(_load_queue [packet_id]._context_id   , _param->_size_context_id   ,
-							      _load_queue [packet_id]._front_end_id , _param->_size_front_end_id ,
-							      _load_queue [packet_id]._ooo_engine_id, _param->_size_ooo_engine_id);
-		    
-		    memory_log_file [num_thread] 
-		      << "[" << simulation_cycle() << "] "
-		      << std::hex
-		      << "@ 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _load_queue [packet_id]._address << " -[ Read  ]-> 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _load_queue [packet_id]._rdata << " "
-		      << std::dec
-		      << "{" << toString(_load_queue [packet_id]._operation) << "}";
-		    
-		    memory_log_file [num_thread] << std::endl;
-		  }
-#endif	    
-
-		if (error != DCACHE_ERROR_NONE)
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"    * have a bus error !!!");
-
-		    _load_queue [packet_id]._exception = EXCEPTION_MEMORY_BUS_ERROR;
-		    _load_queue [packet_id]._state     = LOAD_QUEUE_COMMIT;
-
-                    
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write : %d", _load_queue[packet_id]._store_queue_ptr_write);
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_read  : %d", _load_queue[packet_id]._store_queue_ptr_read );
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_empty     : %d", _load_queue[packet_id]._store_queue_empty    );
-
- 		    if (not _load_queue[packet_id]._store_queue_empty)
-		      {
-			uint32_t i=_load_queue[packet_id]._store_queue_ptr_write;
-			
-			while (i!=_load_queue[packet_id]._store_queue_ptr_read)
-			  {
-			    i=((i==0)?_param->_size_store_queue:i)-1;
-			    
-#ifdef DEBUG
-			    if (reg_STORE_QUEUE_NB_CHECK [i] == 0)
-			      throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
-#endif
-			    
-			    reg_STORE_QUEUE_NB_CHECK [i] --;
-
-			    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 4 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
-
-			    //i=(i+1)%_param->_size_store_queue;
-			  }
-			_load_queue[packet_id]._store_queue_empty = true; // end of check
-
-		      }
-		  }
-		else
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"    * have no bus error.");
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * previous state : %s",toString(_load_queue [packet_id]._state).c_str());
-
-		    // FIXME : convention : if bus error, the cache return the fautive address !
-		    // But, the load's address is aligned !
-
-		    switch (_load_queue [packet_id]._state)
-		      {
-		      case LOAD_QUEUE_WAIT_CHECK : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT_CHECK; break;
-		      case LOAD_QUEUE_WAIT       : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT      ; break;
-		      default : throw ERRORMORPHEO(FUNCTION,_("Illegal state (dcache_rsp).")); break;
-		      }
-		  }
-	      }
-	    else
-	      {
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * packet is a STORE");
-		
-		// TODO : les stores ne génére pas de réponse sauf quand c'est un bus error !!!
-		throw ERRORMORPHEO(FUNCTION,_("dcache_rsp : no respons to a write. (TODO : manage bus error to the store operation.)"));
-	      }
-	    
-	  }
-	
-	// this register is to manage the priority of check -> Round robin
-	reg_LOAD_QUEUE_CHECK_PRIORITY = (reg_LOAD_QUEUE_CHECK_PRIORITY+1)%_param->_size_load_queue;
-	
-	
-#if defined(DEBUG) and (DEBUG>=DEBUG_TRACE)
-	// ***** dump store queue
-        log_printf(TRACE,Load_store_unit,FUNCTION,"  * Dump STORE_QUEUE");
-        log_printf(TRACE,Load_store_unit,FUNCTION,"    * ptr_read : %d",reg_STORE_QUEUE_PTR_READ);
-	
-	for (uint32_t i=0; i<_param->_size_store_queue; i++)
-	  {
-	    uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
-
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d %.1d, %.4d, %.8x %.8x, %.2d %.1d, %.2d %s",
-                       j,
-                       _store_queue[j]._context_id          ,
-                       _store_queue[j]._front_end_id        ,
-                       _store_queue[j]._ooo_engine_id       ,
-                       _store_queue[j]._packet_id           ,
-                       _store_queue[j]._operation           ,
-                       _store_queue[j]._cancel              ,
-                       _store_queue[j]._load_queue_ptr_write,
-                       _store_queue[j]._address             ,
-                       _store_queue[j]._wdata               ,
-                     //_store_queue[j]._write_rd            ,
-                     //_store_queue[j]._num_reg_rd          ,
-                       _store_queue[j]._exception           ,
-                       _store_queue[j]._send_commit         ,
-                       reg_STORE_QUEUE_NB_CHECK  [j]        ,
-                       toString(_store_queue[j]._state).c_str());
-	  }
-
-	// ***** dump speculative_access queue
-	log_printf(TRACE,Load_store_unit,FUNCTION,"  * Dump SPECULATIVE_ACCESS_QUEUE");
-	
-	for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
-	  {
-	    uint32_t j = (*_speculative_access_queue_control)[i];
-
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d %.1d, %.4d %.4d %.4d %.1d, %.8x, %.1d %.4d, %.2d, %s",
-                       j,
-                       _speculative_access_queue[j]._context_id          ,
-                       _speculative_access_queue[j]._front_end_id        ,
-                       _speculative_access_queue[j]._ooo_engine_id       ,
-                       _speculative_access_queue[j]._packet_id           ,
-                       _speculative_access_queue[j]._operation           ,
-                       _speculative_access_queue[j]._cancel              ,
-                       _speculative_access_queue[j]._load_queue_ptr_write,
-                       _speculative_access_queue[j]._store_queue_ptr_write,
-                       _speculative_access_queue[j]._store_queue_ptr_read ,
-                       _speculative_access_queue[j]._store_queue_empty    ,
-                       _speculative_access_queue[j]._address             ,
-                       _speculative_access_queue[j]._write_rd            ,
-                       _speculative_access_queue[j]._num_reg_rd          ,
-                       _speculative_access_queue[j]._exception           ,
-                       toString(_speculative_access_queue[j]._state).c_str());
-	  }
-
-	// ***** dump load queue
-	log_printf(TRACE,Load_store_unit,FUNCTION,"  * Dump LOAD_QUEUE");
-        log_printf(TRACE,Load_store_unit,FUNCTION,"    * ptr_read_check_priority : %d",reg_LOAD_QUEUE_CHECK_PRIORITY);
-	
-	for (uint32_t i=0; i<_param->_size_load_queue; i++)
-	  {
-	    uint32_t j = i;
-
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d %.1d, %.4d %.4d %.1d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s",
-                       j,
-                       _load_queue[j]._context_id          ,
-                       _load_queue[j]._front_end_id        ,
-                       _load_queue[j]._ooo_engine_id       ,
-                       _load_queue[j]._packet_id           ,
-                       _load_queue[j]._operation           ,
-                       _load_queue[j]._cancel              ,
-                       _load_queue[j]._store_queue_ptr_write,
-                       _load_queue[j]._store_queue_ptr_read ,
-		       _load_queue[j]._store_queue_empty    ,
-                       _load_queue[j]._address             ,
-                       _load_queue[j]._check_hit_byte      , 
-                       _load_queue[j]._check_hit           ,
-                       _load_queue[j]._shift               ,
-                       _load_queue[j]._is_load_signed      ,
-                       _load_queue[j]._access_size         ,
-                       _load_queue[j]._rdata               ,
-                       _load_queue[j]._write_rd            ,
-                       _load_queue[j]._num_reg_rd          ,
-                       _load_queue[j]._exception           ,
-                       toString(_load_queue[j]._state).c_str());
-	  }
-#endif
-	
-#ifdef STATISTICS
-        if (usage_is_set(_usage,USE_STATISTICS))
-          {
-            for (uint32_t i=0; i<_param->_size_store_queue; i++)
-              if (_store_queue[i]._state != STORE_QUEUE_EMPTY)
-                (*_stat_use_store_queue) ++;
-            for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
-              if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY)
-                (*_stat_use_speculative_access_queue) ++;
-            for (uint32_t i=0; i<_param->_size_load_queue; i++)
-              if (_load_queue[i]._state != LOAD_QUEUE_EMPTY)
-                (*_stat_use_load_queue) ++;
-          }
-#endif
-      }
-
-    log_end(Load_store_unit,FUNCTION);
-  };
-
-}; // end namespace load_store_unit
-}; // end namespace execute_unit
-}; // end namespace multi_execute_unit
-}; // end namespace execute_loop
-}; // end namespace multi_execute_loop
-}; // end namespace core
-
-}; // end namespace behavioural
-}; // end namespace morpheo              
-#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp	(revision 138)
@@ -20,42 +20,52 @@
 #undef  FUNCTION
 #define FUNCTION "Load_store_unit::Parameters"
-  Parameters::Parameters (uint32_t            size_store_queue       ,
-			  uint32_t            size_load_queue        ,
-			  uint32_t            size_speculative_access_queue,
-			  uint32_t            nb_port_check          ,
-			  Tspeculative_load_t speculative_load       ,
-			  uint32_t            nb_bypass_memory       ,
-			  uint32_t            nb_cache_port          ,
-			  uint32_t            nb_inst_memory         ,
-			  uint32_t            nb_context             ,
-			  uint32_t            nb_front_end           ,
-			  uint32_t            nb_ooo_engine          ,
-			  uint32_t            nb_packet              ,
-			  uint32_t            size_general_data      ,
-			  uint32_t            size_special_data      ,
-			  uint32_t            nb_general_register    ,
-			  uint32_t            nb_special_register    ,
-                          uint32_t            nb_thread              ,
-                          bool              * num_thread_valid       , //[nb_thread]
+  Parameters::Parameters (uint32_t            size_store_queue                   ,
+			  uint32_t            size_load_queue                    ,
+			  uint32_t            size_speculative_access_queue      ,
+                          uint32_t            nb_store_queue_bank                ,
+                          uint32_t            nb_load_queue_bank                 ,
+                          uint32_t            nb_port_check                      ,
+                          Tspeculative_load_t speculative_load                   ,
+                          Tpredictor_t        speculative_commit_predictor_scheme,
+                          uint32_t          * lsu_pht_size_counter               ,//[1]
+                          uint32_t          * lsu_pht_nb_counter                 ,//[1]
+			  uint32_t            nb_bypass_memory                   ,
+			  uint32_t            nb_cache_port                      ,
+			  uint32_t            nb_inst_memory                     ,
+			  uint32_t            nb_context                         ,
+			  uint32_t            nb_front_end                       ,
+			  uint32_t            nb_ooo_engine                      ,
+			  uint32_t            nb_packet                          ,
+			  uint32_t            size_general_data                  ,
+			  uint32_t            size_special_data                  ,
+			  uint32_t            nb_general_register                ,
+			  uint32_t            nb_special_register                ,
+                          uint32_t            nb_thread                          ,
+                          bool              * num_thread_valid                   , //[nb_thread]
                           bool                is_toplevel)
   {
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
 
-    _size_store_queue                      = size_store_queue       ;
-    _size_load_queue                       = size_load_queue        ;
-    _size_speculative_access_queue         = size_speculative_access_queue;
-    _nb_port_check                         = nb_port_check          ;
-    _speculative_load                      = speculative_load       ;
-    _nb_bypass_memory                      = nb_bypass_memory       ;
-    _nb_cache_port                         = nb_cache_port          ;
-    _nb_inst_memory                        = nb_inst_memory         ;
-    _nb_context                            = nb_context             ;
-    _nb_front_end                          = nb_front_end           ;
-    _nb_ooo_engine                         = nb_ooo_engine          ;
-    _nb_packet                             = nb_packet              ;
-    _nb_general_register                   = nb_general_register    ;
-    _nb_special_register                   = nb_special_register    ;
-    _nb_thread                             = nb_thread              ;
-    _num_thread_valid                      = num_thread_valid       ;
+    _size_store_queue                      = size_store_queue                   ;
+    _size_load_queue                       = size_load_queue                    ;
+    _size_speculative_access_queue         = size_speculative_access_queue      ;
+    _nb_store_queue_bank                   = nb_store_queue_bank                ;
+    _nb_load_queue_bank                    = nb_load_queue_bank                 ;
+    _nb_port_check                         = nb_port_check                      ;
+    _speculative_load                      = speculative_load                   ;
+    _speculative_commit_predictor_scheme   = speculative_commit_predictor_scheme;
+    _lsu_pht_size_counter                  = lsu_pht_size_counter               ;
+    _lsu_pht_nb_counter                    = lsu_pht_nb_counter                 ;
+    _nb_bypass_memory                      = nb_bypass_memory                   ;
+    _nb_cache_port                         = nb_cache_port                      ;
+    _nb_inst_memory                        = nb_inst_memory                     ;
+    _nb_context                            = nb_context                         ;
+    _nb_front_end                          = nb_front_end                       ;
+    _nb_ooo_engine                         = nb_ooo_engine                      ;
+    _nb_packet                             = nb_packet                          ;
+    _nb_general_register                   = nb_general_register                ;
+    _nb_special_register                   = nb_special_register                ;
+    _nb_thread                             = nb_thread                          ;
+    _num_thread_valid                      = num_thread_valid                   ;
     
     _size_speculative_access_queue_ptr     = log2(size_speculative_access_queue);
@@ -99,52 +109,4 @@
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
   };
-  
-// #undef  FUNCTION
-// #define FUNCTION "Load_store_unit::Parameters (copy)"
-//   Parameters::Parameters (Parameters & param):
-//     _size_store_queue        (param._size_store_queue       ),
-//     _size_load_queue         (param._size_load_queue        ),
-//     _size_speculative_access_queue (param._size_speculative_access_queue),
-//     _nb_port_check           (param._nb_port_check          ),
-//     _speculative_load        (param._speculative_load       ),
-//     _nb_bypass_memory        (param._nb_bypass_memory       ),
-//     _nb_cache_port           (param._nb_cache_port          ),
-//     _nb_inst_memory          (param._nb_inst_memory         ),
-//     _nb_context              (param._nb_context             ),
-//     _nb_front_end            (param._nb_front_end           ),
-//     _nb_ooo_engine           (param._nb_ooo_engine          ),
-//     _nb_packet               (param._nb_packet              ),
-//     _size_general_data       (param._size_general_data      ),
-//     _size_special_data       (param._size_special_data      ),
-//     _nb_general_register     (param._nb_general_register    ),
-//     _nb_special_register     (param._nb_special_register    ),
-
-//     _size_address_store_queue              (param._size_address_store_queue             ),
-//     _size_address_load_queue               (param._size_address_load_queue              ),
-//     _size_address_speculative_access_queue (param._size_address_speculative_access_queue),
-
-//     _size_context_id         (param._size_context_id        ),
-//     _size_front_end_id       (param._size_front_end_id      ),
-//     _size_ooo_engine_id      (param._size_ooo_engine_id     ),
-//     _size_packet_id          (param._size_packet_id         ),
-//     _size_general_register   (param._size_general_register  ),
-//     _size_special_register   (param._size_special_register  ),
-//     _size_dcache_context_id  (param._size_dcache_context_id ),
-//     _size_dcache_packet_id   (param._size_dcache_packet_id  ),
-
-//     _have_port_context_id    (param._have_port_context_id   ),
-//     _have_port_front_end_id  (param._have_port_front_end_id ),
-//     _have_port_ooo_engine_id (param._have_port_ooo_engine_id),
-//     _have_port_packet_id     (param._have_port_packet_id    ),
-//     _have_port_dcache_context_id(param._have_port_dcache_context_id),
-//     _have_port_load_queue_ptr(param._have_port_load_queue_ptr),
-
-//     _mask_address_lsb        (param._mask_address_lsb),
-//     _mask_address_msb        (param._mask_address_msb)
-//   {
-//     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
-//     test();
-//     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
-//   };
 
 #undef  FUNCTION
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp	(revision 138)
@@ -6,4 +6,5 @@
  */
 
+#include "Behavioural/include/Test.h"
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h"
 #include <sstream>
@@ -29,5 +30,5 @@
     switch (_speculative_load)
       {
-      case SPECULATIVE_LOAD_COMMIT :
+      case SPECULATIVE_LOAD_ACCESS :
 	{
 	  if (not (_nb_bypass_memory == 0))
@@ -37,6 +38,6 @@
 	}
       case NO_SPECULATIVE_LOAD     :
-      case SPECULATIVE_LOAD_ACCESS :
       // case SPECULATIVE_LOAD_BYPASS :
+      // case SPECULATIVE_LOAD_COMMIT :
       default                      :
 	{
@@ -55,4 +56,30 @@
       test.error(_("Bypass number must be less than load_queue's size.\n"));
 
+    if (not is_multiple(_nb_store_queue_bank,_nb_inst_memory))
+      test.error(_("Number of bank of store queue must be a multiple of number input instruction.\n"));
+
+    if (not is_multiple(_nb_load_queue_bank,_nb_inst_memory))
+      test.error(_("Number of bank of load queue must be a multiple of number input instruction.\n"));
+    
+    switch (_speculative_commit_predictor_scheme)
+      {
+      case PREDICTOR_NEVER_TAKE  :
+      case PREDICTOR_ALWAYS_TAKE :
+      case PREDICTOR_COUNTER     :
+        {
+          break;
+        }
+      case PREDICTOR_STATIC      :
+      case PREDICTOR_LAST_TAKE   :
+      case PREDICTOR_LOCAL       :
+      case PREDICTOR_GLOBAL      :
+      case PREDICTOR_META        :
+      case PREDICTOR_CUSTOM      :
+        {
+          test.error(toString(_("Predictor scheme \"%s\" is unsupported for load scheme.\n"),toString(_speculative_commit_predictor_scheme).c_str()));
+          break;
+        }
+      }
+    
     if (_nb_cache_port > 1)
       test.warning(_("nb_cache_port > 1 is unsupported (Coming Soon).\n")); 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/include/Parameters.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/include/Parameters.h	(revision 138)
@@ -26,4 +26,5 @@
   {
     //-----[ fields ]------------------------------------------------------------
+  public : uint32_t    _nb_inst_read            ;
   public : uint32_t    _size_read_queue         ;
   public : uint32_t    _size_reservation_station;
@@ -63,5 +64,6 @@
 
     //-----[ methods ]-----------------------------------------------------------
-  public : Parameters  (uint32_t size_read_queue         ,
+  public : Parameters  (uint32_t nb_inst_read            ,
+                        uint32_t size_read_queue         ,
 			uint32_t size_reservation_station,
 			uint32_t nb_context              ,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Parameters.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Parameters.cpp	(revision 138)
@@ -19,5 +19,6 @@
 #undef  FUNCTION
 #define FUNCTION "Read_unit::Parameters"
-  Parameters::Parameters (uint32_t size_read_queue         ,
+  Parameters::Parameters (uint32_t nb_inst_read            ,
+                          uint32_t size_read_queue         ,
                           uint32_t size_reservation_station,
                           uint32_t nb_context              ,
@@ -40,4 +41,5 @@
     log_printf(FUNC,Read_unit,FUNCTION,"Begin");
 
+    _nb_inst_read             = nb_inst_read            ;
     _size_read_queue          = size_read_queue         ;
     _size_reservation_station = size_reservation_station;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Parameters_msg_error.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Parameters_msg_error.cpp	(revision 138)
@@ -27,4 +27,7 @@
     Parameters_test test ("Read_unit");
 
+    if (_nb_inst_read != 1)
+      test.error(_("nb_inst_read must be equal at 1.\n"));
+
     log_printf(FUNC,Read_unit,FUNCTION,"End");
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Parameters.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Parameters.h	(revision 138)
@@ -28,4 +28,5 @@
   {
     //-----[ fields ]------------------------------------------------------------
+  public : uint32_t              _nb_inst_write                ;
   public : uint32_t              _size_write_queue             ;
   public : uint32_t              _size_execute_queue           ;
@@ -61,5 +62,6 @@
 
     //-----[ methods ]-----------------------------------------------------------
-  public : Parameters  (uint32_t              size_write_queue   ,
+  public : Parameters  (uint32_t              nb_inst_write      ,
+                        uint32_t              size_write_queue   ,
 			uint32_t              size_execute_queue ,
 			uint32_t              nb_context         ,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Parameters.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Parameters.cpp	(revision 138)
@@ -19,5 +19,6 @@
 #undef  FUNCTION
 #define FUNCTION "Write_unit::Parameters"
-  Parameters::Parameters (uint32_t              size_write_queue   ,
+  Parameters::Parameters (uint32_t              nb_inst_write      ,
+                          uint32_t              size_write_queue   ,
 			  uint32_t              size_execute_queue ,
 			  uint32_t              nb_context         ,
@@ -36,4 +37,5 @@
     log_printf(FUNC,Write_unit,FUNCTION,"Begin");
 
+    _nb_inst_write                = nb_inst_write      ;
     _size_write_queue             = size_write_queue   ;
     _size_execute_queue           = size_execute_queue ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Parameters_msg_error.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Parameters_msg_error.cpp	(revision 138)
@@ -27,5 +27,8 @@
 
     if (_size_write_queue == 0)
-      test.error("Write queue must have a less one entry.");
+      test.error(_("Write queue must have a less one entry.\n"));
+
+    if (_nb_inst_write != 1)
+      test.error(_("nb_inst_write must be equal at 1.\n"));
 
     log_printf(FUNC,Write_unit,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Parameters.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Parameters.h	(revision 138)
@@ -54,10 +54,16 @@
   public : uint32_t            * _size_load_queue                               ; //[nb_load_store_unit]
   public : uint32_t            * _size_speculative_access_queue                 ; //[nb_load_store_unit]
+  public : uint32_t            * _nb_store_queue_bank                           ; //[nb_load_store_unit]
+  public : uint32_t            * _nb_load_queue_bank                            ; //[nb_load_store_unit]
   public : uint32_t            * _nb_port_check                                 ; //[nb_load_store_unit]
   public : Tspeculative_load_t * _speculative_load                              ; //[nb_load_store_unit]
+  public : Tpredictor_t        * _speculative_commit_predictor_scheme           ; //[nb_load_store_unit]
+  public : uint32_t           ** _lsu_pht_size_counter                          ; //[nb_load_store_unit][1]
+  public : uint32_t           ** _lsu_pht_nb_counter                            ; //[nb_load_store_unit][1]
   public : uint32_t            * _nb_bypass_memory                              ; //[nb_load_store_unit]
   public : uint32_t            * _nb_cache_port                                 ; //[nb_load_store_unit]
   public : uint32_t            * _nb_inst_memory                                ; //[nb_load_store_unit]
     //  * read_unit                                                                   
+  public : uint32_t            * _nb_inst_read                                  ; //[nb_read_unit]
   public : uint32_t            * _size_read_queue                               ; //[nb_read_unit]
   public : uint32_t            * _size_reservation_station                      ; //[nb_read_unit]
@@ -70,4 +76,5 @@
   public : bool               ** _link_read_unit_with_thread                    ; //[nb_read_unit][nb_thread]
     //  * write_unit                                                                  
+  public : uint32_t            * _nb_inst_write                                 ; //[nb_write_unit]
   public : uint32_t            * _size_write_queue                              ; //[nb_write_unit]
   public : uint32_t            * _size_execute_queue                            ; //[nb_write_unit]
@@ -158,4 +165,5 @@
                         uint32_t              size_special_data                             ,
                         
+                        uint32_t            * nb_inst_read                                  ,//[nb_read_unit]
                         uint32_t            * size_read_queue                               ,//[nb_read_unit]
                         uint32_t            * size_reservation_station                      ,//[nb_read_unit]
@@ -169,10 +177,16 @@
                         uint32_t            * size_load_queue                               ,//[nb_load_store_unit]
                         uint32_t            * size_speculative_access_queue                 ,//[nb_load_store_unit]
+                        uint32_t            * nb_store_queue_bank                           ,//[nb_load_store_unit]
+                        uint32_t            * nb_load_queue_bank                            ,//[nb_load_store_unit]
                         uint32_t            * nb_port_check                                 ,//[nb_load_store_unit]
                         Tspeculative_load_t * speculative_load                              ,//[nb_load_store_unit]
+                        Tpredictor_t        * speculative_commit_predictor_scheme           ,//[nb_load_store_unit]
+                        uint32_t           ** lsu_pht_size_counter                          ,//[nb_load_store_unit][1]
+                        uint32_t           ** lsu_pht_nb_counter                            ,//[nb_load_store_unit][1]
                         uint32_t            * nb_bypass_memory                              ,//[nb_load_store_unit]
                         uint32_t            * nb_cache_port                                 ,//[nb_load_store_unit]
                         uint32_t            * nb_inst_memory                                ,//[nb_load_store_unit]
                         
+                        uint32_t            * nb_inst_write                                 ,//[nb_write_unit]
                         uint32_t            * size_write_queue                              ,//[nb_write_unit]
                         uint32_t            * size_execute_queue                            ,//[nb_write_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp	(revision 138)
@@ -31,4 +31,5 @@
 			  uint32_t              size_special_data                         ,
 			  
+			  uint32_t            * nb_inst_read                              ,//[nb_read_unit]
 			  uint32_t            * size_read_queue                           ,//[nb_read_unit]
 			  uint32_t            * size_reservation_station                  ,//[nb_read_unit]
@@ -42,10 +43,16 @@
 			  uint32_t            * size_load_queue                           ,//[nb_load_store_unit]
 			  uint32_t            * size_speculative_access_queue             ,//[nb_load_store_unit]
-			  uint32_t            * nb_port_check                             ,//[nb_load_store_unit]
-			  Tspeculative_load_t * speculative_load                          ,//[nb_load_store_unit]
+                          uint32_t            * nb_store_queue_bank                       ,//[nb_load_store_unit]
+                          uint32_t            * nb_load_queue_bank                        ,//[nb_load_store_unit]
+                          uint32_t            * nb_port_check                             ,//[nb_load_store_unit]
+                          Tspeculative_load_t * speculative_load                          ,//[nb_load_store_unit]
+                          Tpredictor_t        * speculative_commit_predictor_scheme       ,//[nb_load_store_unit]
+                          uint32_t           ** lsu_pht_size_counter                      ,//[nb_load_store_unit][1]
+                          uint32_t           ** lsu_pht_nb_counter                        ,//[nb_load_store_unit][1]
 			  uint32_t            * nb_bypass_memory                          ,//[nb_load_store_unit]
 			  uint32_t            * nb_cache_port                             ,//[nb_load_store_unit]
 			  uint32_t            * nb_inst_memory                            ,//[nb_load_store_unit]
 
+			  uint32_t            * nb_inst_write                             ,//[nb_write_unit]
 			  uint32_t            * size_write_queue                          ,//[nb_write_unit]
 			  uint32_t            * size_execute_queue                        ,//[nb_write_unit]
@@ -92,4 +99,5 @@
     _nb_packet                                  = nb_packet                            ;
                                                 
+    _nb_inst_read                               = nb_inst_read                         ;
     _size_read_queue                            = size_read_queue                      ;
     _size_reservation_station                   = size_reservation_station             ;
@@ -100,9 +108,15 @@
     _get_custom_information                     = get_custom_information               ;
                                                 
+    _nb_inst_write                              = nb_inst_write                        ;
     _size_store_queue                           = size_store_queue                     ;
     _size_load_queue                            = size_load_queue                      ;
     _size_speculative_access_queue              = size_speculative_access_queue        ;
+    _nb_store_queue_bank                        = nb_store_queue_bank                  ;
+    _nb_load_queue_bank                         = nb_load_queue_bank                   ;
     _nb_port_check                              = nb_port_check                        ;
     _speculative_load                           = speculative_load                     ;
+    _speculative_commit_predictor_scheme        = speculative_commit_predictor_scheme  ;
+    _lsu_pht_size_counter                       = lsu_pht_size_counter                 ;
+    _lsu_pht_nb_counter                         = lsu_pht_nb_counter                   ;
     _nb_bypass_memory                           = nb_bypass_memory                     ;
     _nb_cache_port                              = nb_cache_port                        ;
@@ -379,5 +393,6 @@
     for (uint32_t i=0; i<_nb_read_unit; i++)
       _param_read_unit [i] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::Parameters 
-	(_size_read_queue               [i],
+	(_nb_inst_read                  [i],
+         _size_read_queue               [i],
 	 _size_reservation_station      [i],
 	 _nb_context                       ,
@@ -421,22 +436,28 @@
         else
 	  _param_load_store_unit [x] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters
-	    (_size_store_queue              [x],
-	     _size_load_queue               [x],
-	     _size_speculative_access_queue [x],
-	     _nb_port_check                 [x],
-	     _speculative_load              [x],
-	     _nb_bypass_memory              [x],
-	     _nb_cache_port                 [x],
-	     _nb_inst_memory                [x],
-	     _nb_context                       ,
-	     _nb_front_end                     ,
-	     _nb_ooo_engine                    ,
-	     _nb_packet                        ,
-	      size_general_data                ,
-	      size_special_data                ,
-	     _max_nb_special_register          ,
-	     _max_nb_general_register          ,
-             _nb_thread                        ,
-             _num_thread_valid                 );
+	    (_size_store_queue                    [x],
+	     _size_load_queue                     [x],
+	     _size_speculative_access_queue       [x],
+
+	     _nb_store_queue_bank                 [x],
+	     _nb_load_queue_bank                  [x],
+	     _nb_port_check                       [x],
+	     _speculative_load                    [x],
+	     _speculative_commit_predictor_scheme [x],
+	     _lsu_pht_size_counter                [x],
+	     _lsu_pht_nb_counter                  [x],
+	     _nb_bypass_memory                    [x],
+	     _nb_cache_port                       [x],
+	     _nb_inst_memory                      [x],
+	     _nb_context                             ,
+	     _nb_front_end                           ,
+	     _nb_ooo_engine                          ,
+	     _nb_packet                              ,
+	      size_general_data                      ,
+	      size_special_data                      ,
+	     _max_nb_special_register                ,
+	     _max_nb_general_register                ,
+             _nb_thread                              ,
+             _num_thread_valid                       );
       }
 
@@ -446,5 +467,6 @@
     for (uint32_t i=0; i<_nb_write_unit; i++)
       _param_write_unit [i] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::Parameters
-	(_size_write_queue        [i],
+	(_nb_inst_write           [i],
+	 _size_write_queue        [i],
 	 _size_execute_queue      [i],
 	 _nb_context                 ,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit.cpp	(revision 138)
@@ -72,5 +72,5 @@
 #endif
 
-#ifdef SYSTEMC
+#if defined(SYSTEMC) and (defined(STATISTICS) or defined(VHDL_TESTBENCH))
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
@@ -84,7 +84,7 @@
 	// List dependency information
 # endif    
-	
+      }
 #endif
-      }
+
     log_end(Decod_unit,FUNCTION);
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit.cpp	(revision 138)
@@ -70,5 +70,5 @@
 #endif
 
-#ifdef SYSTEMC
+#if defined(SYSTEMC) and (defined(STATISTICS) or defined(VHDL_TESTBENCH))
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
@@ -82,7 +82,6 @@
 	// List dependency information
 # endif    
-	
+      }
 #endif
-      }
     log_printf(FUNC,Ifetch_unit,FUNCTION,"End");
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer.cpp	(revision 138)
@@ -71,5 +71,5 @@
 #endif
 
-#ifdef SYSTEMC
+#if defined(SYSTEMC) and (defined(STATISTICS) or defined(VHDL_TESTBENCH))
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
@@ -83,7 +83,6 @@
 	// List dependency information
 # endif    
-	
+      }
 #endif
-      }
     log_printf(FUNC,Branch_Target_Buffer,FUNCTION,"End");
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor.cpp	(revision 138)
@@ -68,5 +68,5 @@
 #endif
 
-#ifdef SYSTEMC
+#if defined(SYSTEMC) and (defined(STATISTICS) or defined(VHDL_TESTBENCH))
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
@@ -80,7 +80,6 @@
 	// List dependency information
 # endif    
-	
+      }
 #endif
-      }
     log_end(Meta_Predictor,FUNCTION);
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction.cpp	(revision 138)
@@ -71,5 +71,5 @@
 #endif
 
-#ifdef SYSTEMC
+#if defined(SYSTEMC) and (defined(STATISTICS) or defined(VHDL_TESTBENCH))
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
@@ -83,7 +83,6 @@
 	// List dependency information
 # endif    
-	
+      }
 #endif
-      }
     log_printf(FUNC,Direction,FUNCTION,"End");
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit.cpp	(revision 138)
@@ -70,5 +70,5 @@
 #endif
 
-#ifdef SYSTEMC
+#if defined(SYSTEMC) and (defined(STATISTICS) or defined(VHDL_TESTBENCH))
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
@@ -82,7 +82,6 @@
 	// List dependency information
 # endif    
-	
+      }
 #endif
-      }
     log_printf(FUNC,Prediction_unit,FUNCTION,"End");
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end.cpp	(revision 138)
@@ -71,5 +71,5 @@
 #endif
 
-#ifdef SYSTEMC
+#if defined(SYSTEMC) and (defined(STATISTICS) or defined(VHDL_TESTBENCH))
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
@@ -83,7 +83,6 @@
 	// List dependency information
 # endif    
-	
+      }
 #endif
-      }
     log_end(Front_end,FUNCTION);
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 138)
@@ -208,10 +208,10 @@
 
     // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-  public    : SC_IN (Tcontrol_t        )  ***  in_EVENT_VAL                        ;//[nb_front_end][nb_context]
-  public    : SC_OUT(Tcontrol_t        )  *** out_EVENT_ACK                        ;//[nb_front_end][nb_context]
-  public    : SC_IN (Taddress_t        )  ***  in_EVENT_ADDRESS                    ;//[nb_front_end][nb_context]
-  public    : SC_IN (Taddress_t        )  ***  in_EVENT_ADDRESS_NEXT               ;//[nb_front_end][nb_context] 
-  public    : SC_IN (Tcontrol_t        )  ***  in_EVENT_ADDRESS_NEXT_VAL           ;//[nb_front_end][nb_context]
-  public    : SC_IN (Tcontrol_t        )  ***  in_EVENT_IS_DS_TAKE                 ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t         ) ***  in_EVENT_VAL                        ;//[nb_front_end][nb_context]
+  public    : SC_OUT(Tcontrol_t         ) *** out_EVENT_ACK                        ;//[nb_front_end][nb_context]
+  public    : SC_IN (Taddress_t         ) ***  in_EVENT_ADDRESS                    ;//[nb_front_end][nb_context]
+  public    : SC_IN (Taddress_t         ) ***  in_EVENT_ADDRESS_NEXT               ;//[nb_front_end][nb_context] 
+  public    : SC_IN (Tcontrol_t         ) ***  in_EVENT_ADDRESS_NEXT_VAL           ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t         ) ***  in_EVENT_IS_DS_TAKE                 ;//[nb_front_end][nb_context]
 
     // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h	(revision 138)
@@ -24,81 +24,82 @@
   {
     //-----[ fields ]------------------------------------------------------------
-  public : uint32_t            _nb_front_end                       ;
-  public : uint32_t          * _nb_context                         ;//[nb_front_end]
-  public : uint32_t            _nb_rename_unit                     ;
-  public : uint32_t            _size_queue                         ;
-  public : uint32_t            _nb_bank                            ;
-  public : uint32_t          * _nb_inst_insert                     ;//[nb_rename_unit]
-  public : uint32_t          * _nb_inst_retire	                   ;//[nb_rename_unit]
-  public : uint32_t            _nb_inst_commit                     ;
-  public : uint32_t            _nb_inst_reexecute                  ;
-  public : uint32_t            _nb_inst_branch_complete            ;
-  public : uint32_t         ** _nb_branch_speculated               ;//[nb_front_end][nb_context]
-//public : uint32_t            _size_general_data                  ;
-//public : uint32_t            _size_store_queue_ptr               ;
-//public : uint32_t            _size_load_queue_ptr                ;
-//public : uint32_t            _size_general_register              ;
-//public : uint32_t            _size_special_register              ;
-  public : Tpriority_t         _priority                           ;
-  public : Tload_balancing_t   _load_balancing                     ;
-  public : uint32_t            _nb_rename_unit_select              ;
-  public : uint32_t            _nb_thread                          ;
-  public : uint32_t         ** _translate_num_context_to_num_thread; //[nb_front_end][nb_context]
-  public : const uint32_t      _nb_bank_access_commit              ;
-  public : const retire_ooo_t  _retire_ooo                         ;
-
-  public : uint32_t            _max_nb_context          ;
-  public : uint32_t            _max_nb_inst_insert      ;
-  public : uint32_t            _max_nb_inst_retire      ;
-//public : uint32_t            _size_address            ;
-//public : uint32_t            _size_front_end_id       ;
-//public : uint32_t            _size_context_id         ;
-  public : uint32_t            _size_rename_unit_id     ;    
-  public : uint32_t            _size_bank               ;
-//public : uint32_t            _size_nb_inst            ;
-//public : uint32_t            _size_packet_id          ;
-  public : uint32_t         ** _array_size_depth        ;//[nb_front_end][nb_context]
-//public : uint32_t            _max_size_depth          ;
-
-//public : Tpacket_t           _shift_num_bank          ;
-  public : Tpacket_t           _mask_num_bank           ;
-  public : Tpacket_t           _shift_num_slot          ;
-//public : Tpacket_t           _mask_num_slot           ;
-    
-
-//public : bool                _have_port_front_end_id  ;
-//public : bool                _have_port_context_id    ;
-//public : bool                _have_port_packet_id     ;
-  public : bool                _have_port_rename_unit_id;
-//public : bool                _have_port_load_queue_ptr;
-//public : bool                _have_port_max_depth     ;
-//public : bool             ** _have_port_depth         ;//[nb_front_end][nb_context]
-
-  public : bool              * _have_thread             ;//[nb_thread]
+  public : uint32_t             _nb_front_end                       ;
+  public : uint32_t           * _nb_context                         ;//[nb_front_end]
+  public : uint32_t             _nb_rename_unit                     ;
+  public : uint32_t             _size_queue                         ;
+  public : uint32_t             _nb_bank                            ;
+  public : Tretire_ooo_scheme_t _retire_ooo_scheme                  ;
+  public : uint32_t           * _nb_inst_insert                     ;//[nb_rename_unit]
+  public : uint32_t           * _nb_inst_retire	                    ;//[nb_rename_unit]
+  public : uint32_t             _nb_inst_commit                     ;
+  public : uint32_t             _nb_inst_reexecute                  ;
+  public : uint32_t             _nb_inst_branch_complete            ;
+  public : uint32_t          ** _nb_branch_speculated               ;//[nb_front_end][nb_context]
+//public : uint32_t             _size_general_data                  ;
+//public : uint32_t             _size_store_queue_ptr               ;
+//public : uint32_t             _size_load_queue_ptr                ;
+//public : uint32_t             _size_general_register              ;
+//public : uint32_t             _size_special_register              ;
+  public : Tpriority_t          _priority                           ;
+  public : Tload_balancing_t    _load_balancing                     ;
+  public : uint32_t             _nb_rename_unit_select              ;
+  public : uint32_t             _nb_thread                          ;
+  public : uint32_t          ** _translate_num_context_to_num_thread; //[nb_front_end][nb_context]
+  public : const uint32_t       _nb_bank_access_commit              ;
+                             
+  public : uint32_t             _max_nb_context          ;
+  public : uint32_t             _max_nb_inst_insert      ;
+  public : uint32_t             _max_nb_inst_retire      ;
+//public : uint32_t             _size_address            ;
+//public : uint32_t             _size_front_end_id       ;
+//public : uint32_t             _size_context_id         ;
+  public : uint32_t             _size_rename_unit_id     ;    
+  public : uint32_t             _size_bank               ;
+//public : uint32_t             _size_nb_inst            ;
+//public : uint32_t             _size_packet_id          ;
+  public : uint32_t          ** _array_size_depth        ;//[nb_front_end][nb_context]
+//public : uint32_t             _max_size_depth          ;
+                             
+//public : Tpacket_t            _shift_num_bank          ;
+  public : Tpacket_t            _mask_num_bank           ;
+  public : Tpacket_t            _shift_num_slot          ;
+//public : Tpacket_t            _mask_num_slot           ;
+                             
+                             
+//public : bool                 _have_port_front_end_id  ;
+//public : bool                 _have_port_context_id    ;
+//public : bool                 _have_port_packet_id     ;
+  public : bool                 _have_port_rename_unit_id;
+//public : bool                 _have_port_load_queue_ptr;
+//public : bool                 _have_port_max_depth     ;
+//public : bool              ** _have_port_depth         ;//[nb_front_end][nb_context]
+                             
+  public : bool               * _have_thread             ;//[nb_thread]
 
     //-----[ methods ]-----------------------------------------------------------
-  public : Parameters  (uint32_t            nb_front_end                       ,
-			uint32_t          * nb_context                         ,//[nb_front_end]
-			uint32_t            nb_rename_unit                     ,
-			uint32_t            size_queue                         ,
-			uint32_t            nb_bank                            ,
-			uint32_t          * nb_inst_insert                     ,//[nb_rename_unit]
-			uint32_t          * nb_inst_retire                     ,//[nb_rename_unit]
-			uint32_t            nb_inst_commit                     ,
-			uint32_t            nb_inst_reexecute                  ,
-			uint32_t            nb_inst_branch_complete            ,
-			uint32_t         ** nb_branch_speculated               ,//[nb_front_end][nb_context]
-                        uint32_t            size_nb_inst_decod                 ,
-			uint32_t            size_general_data                  ,
-			uint32_t            size_store_queue_ptr               ,
-			uint32_t            size_load_queue_ptr                ,
-			uint32_t            size_general_register              ,
-			uint32_t            size_special_register              ,
-			Tpriority_t         priority                           ,
-			Tload_balancing_t   load_balancing                     ,
-			uint32_t            nb_rename_unit_select              ,
-                        uint32_t            nb_thread                          ,
-                        uint32_t         ** translate_num_context_to_num_thread, //[nb_front_end][nb_context]
-                        bool                is_toplevel=false
+  public : Parameters  (uint32_t             nb_front_end                       ,
+			uint32_t           * nb_context                         ,//[nb_front_end]
+			uint32_t             nb_rename_unit                     ,
+			uint32_t             size_queue                         ,
+			uint32_t             nb_bank                            ,
+                        Tretire_ooo_scheme_t retire_ooo_scheme                  ,
+			uint32_t           * nb_inst_insert                     ,//[nb_rename_unit]
+			uint32_t           * nb_inst_retire                     ,//[nb_rename_unit]
+			uint32_t             nb_inst_commit                     ,
+			uint32_t             nb_inst_reexecute                  ,
+			uint32_t             nb_inst_branch_complete            ,
+			uint32_t          ** nb_branch_speculated               ,//[nb_front_end][nb_context]
+                        uint32_t             size_nb_inst_decod                 ,
+			uint32_t             size_general_data                  ,
+			uint32_t             size_store_queue_ptr               ,
+			uint32_t             size_load_queue_ptr                ,
+			uint32_t             size_general_register              ,
+			uint32_t             size_special_register              ,
+			Tpriority_t          priority                           ,
+			Tload_balancing_t    load_balancing                     ,
+			uint32_t             nb_rename_unit_select              ,
+                        uint32_t             nb_thread                          ,
+                        uint32_t          ** translate_num_context_to_num_thread, //[nb_front_end][nb_context]
+                        bool                 is_toplevel=false
 			);
 //   public : Parameters  (Parameters & param) ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 138)
@@ -23,5 +23,5 @@
       RETIRE_OOO_RENAME_UNIT,
       RETIRE_OOO_CONTEXT
-    } retire_ooo_t;
+    } Tretire_ooo_scheme_t;
 
   typedef enum
@@ -142,4 +142,32 @@
 }; // end namespace core
 }; // end namespace behavioural
+
+  template<> inline std::string toString<morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Tretire_ooo_scheme_t>(const morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Tretire_ooo_scheme_t& x)
+  {
+    switch (x)
+      {
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::RETIRE_IN_ORDER        : return "retire_in_order"       ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::RETIRE_OOO_RENAME_UNIT : return "retire_ooo_rename_unit"; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::RETIRE_OOO_CONTEXT     : return "retire_ooo_context"    ; break;
+      default    : return ""      ; break;
+      }
+  };
+
+  template<> inline morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Tretire_ooo_scheme_t fromString<morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Tretire_ooo_scheme_t>(const std::string& x)
+  {
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::RETIRE_IN_ORDER       ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::RETIRE_IN_ORDER        )) == 0))
+      return morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::RETIRE_IN_ORDER;
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::RETIRE_OOO_RENAME_UNIT))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::RETIRE_OOO_RENAME_UNIT )) == 0))
+      return morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::RETIRE_OOO_RENAME_UNIT;
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::RETIRE_OOO_CONTEXT    ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::RETIRE_OOO_CONTEXT     )) == 0))
+      return morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::RETIRE_OOO_CONTEXT;
+
+    throw (ERRORMORPHEO ("fromString","Unknow string : \""+x+"\""));
+  };
 
  template<> inline std::string toString<morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::rob_state_t>(const morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::rob_state_t& x)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp	(revision 138)
@@ -21,29 +21,29 @@
 #undef  FUNCTION
 #define FUNCTION "Commit_unit::Parameters"
-  Parameters::Parameters (uint32_t            nb_front_end                       ,
-			  uint32_t          * nb_context                         ,
-			  uint32_t            nb_rename_unit                     ,
-			  uint32_t            size_queue                         ,
-			  uint32_t            nb_bank                            ,
-			  uint32_t          * nb_inst_insert                     ,
-			  uint32_t          * nb_inst_retire                     ,
-			  uint32_t            nb_inst_commit                     ,
-			  uint32_t            nb_inst_reexecute                  ,
-			  uint32_t            nb_inst_branch_complete            ,
-			  uint32_t         ** nb_branch_speculated               ,
-                          uint32_t            size_nb_inst_decod                 ,
-			  uint32_t            size_general_data                  ,
-			  uint32_t            size_store_queue_ptr               ,
-			  uint32_t            size_load_queue_ptr                ,
-			  uint32_t            size_general_register              ,
-			  uint32_t            size_special_register              ,
-			  Tpriority_t         priority                           ,
-			  Tload_balancing_t   load_balancing                     ,
-			  uint32_t            nb_rename_unit_select              ,
-                          uint32_t            nb_thread                          ,
-                          uint32_t         ** translate_num_context_to_num_thread,
-                          bool                is_toplevel):
-    _nb_bank_access_commit (1              ),
-    _retire_ooo            (RETIRE_IN_ORDER)
+  Parameters::Parameters (uint32_t             nb_front_end                       ,
+			  uint32_t           * nb_context                         ,
+			  uint32_t             nb_rename_unit                     ,
+			  uint32_t             size_queue                         ,
+			  uint32_t             nb_bank                            ,
+                          Tretire_ooo_scheme_t retire_ooo_scheme                  ,
+			  uint32_t           * nb_inst_insert                     ,
+			  uint32_t           * nb_inst_retire                     ,
+			  uint32_t             nb_inst_commit                     ,
+			  uint32_t             nb_inst_reexecute                  ,
+			  uint32_t             nb_inst_branch_complete            ,
+			  uint32_t          ** nb_branch_speculated               ,
+                          uint32_t             size_nb_inst_decod                 ,
+			  uint32_t             size_general_data                  ,
+			  uint32_t             size_store_queue_ptr               ,
+			  uint32_t             size_load_queue_ptr                ,
+			  uint32_t             size_general_register              ,
+			  uint32_t             size_special_register              ,
+			  Tpriority_t          priority                           ,
+			  Tload_balancing_t    load_balancing                     ,
+			  uint32_t             nb_rename_unit_select              ,
+                          uint32_t             nb_thread                          ,
+                          uint32_t          ** translate_num_context_to_num_thread,
+                          bool                 is_toplevel):
+    _nb_bank_access_commit (1              )
   {
     log_begin(Commit_unit,FUNCTION);
@@ -54,4 +54,5 @@
     _size_queue                          = size_queue                         ;
     _nb_bank                             = nb_bank                            ;
+    _retire_ooo_scheme                   = retire_ooo_scheme                  ;
     _nb_inst_insert                      = nb_inst_insert                     ;
     _nb_inst_retire                      = nb_inst_retire                     ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp	(revision 138)
@@ -40,4 +40,7 @@
       test.error(_("nb_bank must be a multiple of size_queue.\n"));
 
+    if (_retire_ooo_scheme != RETIRE_IN_ORDER)
+      test.error(toString(_("retire_ooo_scheme \"%s\" is not yet implemented.\n"),toString(_retire_ooo_scheme).c_str()));
+
 //     if (_nb_inst_reexecute != 1)
 //       test.error(_("nb_inst_reexecute must be set at 1. Anothers value is unsupported.\n"));
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_print.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_print.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_print.cpp	(revision 138)
@@ -25,30 +25,30 @@
     std::string str = "";
     
-    str += toString(MSG_INFORMATION)+"  * nb_front_end            : "+toString<uint32_t         >(_nb_front_end           )+"\n";
+    str += toString(MSG_INFORMATION)+"  * nb_front_end            : "+toString<uint32_t            >(_nb_front_end           )+"\n";
     for (uint32_t i=0; i<_nb_front_end; ++i)
     str += toString(MSG_INFORMATION)+"  * nb_context                ["+toString(i)+"] : "+toString<uint32_t         >(_nb_context [i])+"\n";//[nb_front_end]
-    str += toString(MSG_INFORMATION)+"  * nb_rename_unit          : "+toString<uint32_t         >(_nb_rename_unit         )+"\n";
-    str += toString(MSG_INFORMATION)+"  * size_queue              : "+toString<uint32_t         >(_size_queue             )+"\n";
-    str += toString(MSG_INFORMATION)+"  * nb_bank                 : "+toString<uint32_t         >(_nb_bank                )+"\n";
+    str += toString(MSG_INFORMATION)+"  * nb_rename_unit          : "+toString<uint32_t            >(_nb_rename_unit         )+"\n";
+    str += toString(MSG_INFORMATION)+"  * size_queue              : "+toString<uint32_t            >(_size_queue             )+"\n";
+    str += toString(MSG_INFORMATION)+"  * nb_bank                 : "+toString<uint32_t            >(_nb_bank                )+"\n";
     for (uint32_t i=0; i<_nb_rename_unit; ++i)
     str += toString(MSG_INFORMATION)+"  * nb_inst_insert            ["+toString(i)+"] : "+toString<uint32_t         >(_nb_inst_insert[i])+"\n";//[nb_rename_unit]
     for (uint32_t i=0; i<_nb_rename_unit; ++i)
     str += toString(MSG_INFORMATION)+"  * nb_inst_retire            ["+toString(i)+"] : "+toString<uint32_t         >(_nb_inst_retire[i])+"\n";//[nb_rename_unit]
-    str += toString(MSG_INFORMATION)+"  * nb_inst_commit          : "+toString<uint32_t         >(_nb_inst_commit         )+"\n";
-    str += toString(MSG_INFORMATION)+"  * nb_inst_reexecute       : "+toString<uint32_t         >(_nb_inst_reexecute      )+"\n";
-    str += toString(MSG_INFORMATION)+"  * nb_inst_branch_complete : "+toString<uint32_t         >(_nb_inst_branch_complete)+"\n";
+    str += toString(MSG_INFORMATION)+"  * nb_inst_commit          : "+toString<uint32_t            >(_nb_inst_commit         )+"\n";
+    str += toString(MSG_INFORMATION)+"  * nb_inst_reexecute       : "+toString<uint32_t            >(_nb_inst_reexecute      )+"\n";
+    str += toString(MSG_INFORMATION)+"  * nb_inst_branch_complete : "+toString<uint32_t            >(_nb_inst_branch_complete)+"\n";
     for (uint32_t i=0; i<_nb_front_end; ++i)
     for (uint32_t j=0; j<_nb_context[i]; ++j)
     str += toString(MSG_INFORMATION)+"  * nb_branch_speculated      ["+toString(i)+"]["+toString(j)+"] : "+toString<uint32_t         >(_nb_branch_speculated[i][j])+"\n";//[nb_front_end][nb_context]
-    str += toString(MSG_INFORMATION)+"  * size_general_data       : "+toString<uint32_t         >(_size_general_data      )+"\n";
-    str += toString(MSG_INFORMATION)+"  * size_store_queue_ptr    : "+toString<uint32_t         >(_size_store_queue_ptr   )+"\n";
-    str += toString(MSG_INFORMATION)+"  * size_load_queue_ptr     : "+toString<uint32_t         >(_size_load_queue_ptr    )+"\n";
-    str += toString(MSG_INFORMATION)+"  * size_general_register   : "+toString<uint32_t         >(_size_general_register  )+"\n";
-    str += toString(MSG_INFORMATION)+"  * size_special_register   : "+toString<uint32_t         >(_size_special_register  )+"\n";
-    str += toString(MSG_INFORMATION)+"  * priority                : "+toString<Tpriority_t      >(_priority               )+"\n";
-    str += toString(MSG_INFORMATION)+"  * load_balancing          : "+toString<Tload_balancing_t>(_load_balancing         )+"\n";
-    str += toString(MSG_INFORMATION)+"  * nb_rename_unit_select   : "+toString<uint32_t         >(_nb_rename_unit_select  )+"\n";
-    str += toString(MSG_INFORMATION)+"  * nb_bank_access_commit   : "+toString<uint32_t         >(_nb_bank_access_commit  )+"\n";
-    str += toString(MSG_INFORMATION)+"  * retire_ooo              : "+toString<retire_ooo_t     >(_retire_ooo             )+"\n";
+    str += toString(MSG_INFORMATION)+"  * size_general_data       : "+toString<uint32_t            >(_size_general_data      )+"\n";
+    str += toString(MSG_INFORMATION)+"  * size_store_queue_ptr    : "+toString<uint32_t            >(_size_store_queue_ptr   )+"\n";
+    str += toString(MSG_INFORMATION)+"  * size_load_queue_ptr     : "+toString<uint32_t            >(_size_load_queue_ptr    )+"\n";
+    str += toString(MSG_INFORMATION)+"  * size_general_register   : "+toString<uint32_t            >(_size_general_register  )+"\n";
+    str += toString(MSG_INFORMATION)+"  * size_special_register   : "+toString<uint32_t            >(_size_special_register  )+"\n";
+    str += toString(MSG_INFORMATION)+"  * priority                : "+toString<Tpriority_t         >(_priority               )+"\n";
+    str += toString(MSG_INFORMATION)+"  * load_balancing          : "+toString<Tload_balancing_t   >(_load_balancing         )+"\n";
+    str += toString(MSG_INFORMATION)+"  * nb_rename_unit_select   : "+toString<uint32_t            >(_nb_rename_unit_select  )+"\n";
+    str += toString(MSG_INFORMATION)+"  * nb_bank_access_commit   : "+toString<uint32_t            >(_nb_bank_access_commit  )+"\n";
+    str += toString(MSG_INFORMATION)+"  * retire_ooo_scheme       : "+toString<Tretire_ooo_scheme_t>(_retire_ooo_scheme      )+"\n";
 
     /*
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h	(revision 138)
@@ -149,5 +149,5 @@
     // in_order implementation only
     // out_of_order implementation only
-  private   : generic::priority::Priority   * _priority_reg;
+//private   : generic::priority::Priority   * _priority_reg;
   private   : generic::priority::Priority   * _priority_out;
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp	(revision 138)
@@ -191,8 +191,8 @@
 						     _param->_nb_bank);
 
-    _priority_reg = new generic::priority::Priority (_name+"_priority_reg"  ,
-						     _param->_priority      ,
-						     _param->_nb_bank,
-						     _param->_nb_bank);
+    // _priority_reg = new generic::priority::Priority (_name+"_priority_reg"  ,
+    //     					     _param->_priority      ,
+    //     					     _param->_nb_bank,
+    //     					     _param->_nb_bank);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp	(revision 138)
@@ -136,5 +136,5 @@
       {
         delete    _priority_out;
-        delete    _priority_reg;
+        // delete    _priority_reg;
       }
     delete    _component;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_genMoore.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_genMoore.cpp	(revision 138)
@@ -45,5 +45,5 @@
           ack [i][j] = false;
     
-      std::list<generic::priority::select_t> * select_reg = _priority_reg->select(); // same select for all issue
+      // std::list<generic::priority::select_t> * select_reg = _priority_reg->select(); // same select for all issue
       
       // issue_in interface
@@ -60,9 +60,12 @@
           
           // scan all bank
-          for (std::list<generic::priority::select_t>::iterator it=select_reg->begin();
-               it!=select_reg->end();
-               it++)
+          // for (std::list<generic::priority::select_t>::iterator it=select_reg->begin();
+          //      it!=select_reg->end();
+          //      it++)
+          for (uint32_t num_bank=0;
+               num_bank<_param->_nb_bank;
+               ++num_bank)
             {
-              uint32_t num_bank  = it->grp;
+              // uint32_t num_bank  = it->grp;
 
               log_printf(TRACE,Issue_queue,FUNCTION,"    * BANK [%d]",num_bank);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_transition.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_transition.cpp	(revision 138)
@@ -28,5 +28,5 @@
 // 	_priority_in ->reset();
 	_priority_out->reset();
-	_priority_reg->reset();
+//      _priority_reg->reset();
 	
 	for (uint32_t i=0; i<_param->_nb_bank; i++)
@@ -37,5 +37,5 @@
 // 	_priority_in ->transition();
  	_priority_out->transition();
-	_priority_reg->transition();
+//	_priority_reg->transition();
 
 	// ===================================================================
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp	(revision 138)
@@ -41,7 +41,7 @@
       }
 
-    if (// (_queue_scheme == ISSUE_QUEUE_SCHEME_IN_BUNDLE_ORDER) or
-        (_queue_scheme == ISSUE_QUEUE_SCHEME_OUT_OF_ORDER   ))
-      test.error(toString(_("Can have deadlock with the queue scheme \"%s\".\n"),toString(_queue_scheme).c_str()));
+    // if (// (_queue_scheme == ISSUE_QUEUE_SCHEME_IN_BUNDLE_ORDER) or
+    //     (_queue_scheme == ISSUE_QUEUE_SCHEME_OUT_OF_ORDER   ))
+    //   test.error(toString(_("Can have deadlock with the queue scheme \"%s\".\n"),toString(_queue_scheme).c_str()));
 
     if (not is_multiple(_size_queue, _nb_bank))
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h	(revision 138)
@@ -134,6 +134,6 @@
    morpheo::behavioural::Tusage_t                usage
    );
-  public  :          ~Load_Store_pointer_unit             (void);
-					       
+  public  :            ~Load_Store_pointer_unit   (void);
+
   private : void        allocation                (
 #ifdef STATISTICS
@@ -146,15 +146,15 @@
 					       
 #ifdef SYSTEMC				       
-  public  : void        constant                 (void);
+  public  : void        constant                  (void);
   public  : void        transition                (void);
   public  : void        genMealy_insert           (void);
   public  : void        genMealy_retire           (void);
-#endif					       
+#endif
 
-#if VHDL				       
+#if VHDL
   public  : void        vhdl                      (void);
   private : void        vhdl_declaration          (Vhdl * & vhdl);
   private : void        vhdl_body                 (Vhdl * & vhdl);
-#endif					       
+#endif
 
 #ifdef STATISTICS
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp	(revision 138)
@@ -54,83 +54,90 @@
         log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"  * INSERT [%d]",i);
 
-	Tcontrol_t ack                   = false;
+	Tcontrol_t ack  = false;
+        bool       find = false;
 
-	if ((PORT_READ(in_INSERT_VAL  [i]) == true       ) and
-	    (PORT_READ(in_INSERT_TYPE [i]) == TYPE_MEMORY))
-	  {
-            log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * type is memory");
-
-	    Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [i]):0;
-	    Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_INSERT_CONTEXT_ID   [i]):0;
-	    uint32_t   lsq          = _param->_link_load_store_unit_with_thread[front_end_id][context_id];
-
+	if (PORT_READ(in_INSERT_VAL [i]) == true)
+          {
+            Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [i]):0;
+            Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_INSERT_CONTEXT_ID   [i]):0; 
+            uint32_t   lsq          = _param->_link_load_store_unit_with_thread[front_end_id][context_id];
+            
             log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * front_end_id : %d",front_end_id);
             log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * context_id   : %d",context_id  );
             log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * lsq          : %d",lsq         );
+            
+            PORT_WRITE(out_INSERT_STORE_QUEUE_PTR_WRITE [i], STORE_QUEUE_PTR_WRITE [lsq]);
+//          PORT_WRITE(out_INSERT_STORE_QUEUE_PTR_READ  [i], ((reg_STORE_QUEUE_PTR_READ  [front_end_id][context_id]+1)%_param->_size_load_queue[lsq]));
+            PORT_WRITE(out_INSERT_STORE_QUEUE_PTR_READ  [i], reg_STORE_QUEUE_PTR_READ  [front_end_id][context_id]);
+            PORT_WRITE(out_INSERT_STORE_QUEUE_EMPTY     [i], reg_STORE_QUEUE_EMPTY     [front_end_id][context_id]);
+            if (_param->_have_port_load_queue_ptr)
+            PORT_WRITE(out_INSERT_LOAD_QUEUE_PTR_WRITE  [i], LOAD_QUEUE_PTR_WRITE  [lsq]);
 
-	    // Test if a previous instruction use the same lsq
-	    // Authorize once memory access by load store unit
-	    if (nb_use_lsq [lsq] > 0)
-	      {
-		nb_use_lsq [lsq] --;
+            if (PORT_READ(in_INSERT_TYPE [i]) == TYPE_MEMORY)
+              {
+                log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * type is memory");
+               
+                find = true;
+                
+                // Test if a previous instruction use the same lsq
+                // Authorize once memory access by load store unit
+                if (nb_use_lsq [lsq] > 0)
+                  {
+                    nb_use_lsq [lsq] --;
+                    
+                    uint32_t   ptr;
+                    
+                    log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * sq_ptr_write : %d",STORE_QUEUE_PTR_WRITE [lsq]);
+                    log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * lq_ptr_write : %d",LOAD_QUEUE_PTR_WRITE [lsq]);
+                    
+                    // operation became of decod_stage. Also operation is != store_head_ok and store_head_ko
+                    if (is_operation_memory_store(PORT_READ(in_INSERT_OPERATION [i])))
+                      {
+                        log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * USE_STORE_QUEUE");
+                        
+                        internal_INSERT_OPERATION_USE [i] = OPERATION_USE_STORE_QUEUE;
+                        
+                        ptr = STORE_QUEUE_PTR_WRITE [lsq];
+                        ack = not STORE_QUEUE_USE [lsq][ptr] and (static_cast<uint32_t>(STORE_QUEUE_NB_USE [lsq]+1) < _param->_size_store_queue[lsq]);
+                        
+                        if (ack)
+                          {
+                            STORE_QUEUE_PTR_WRITE [lsq]      = (ptr+1)%_param->_size_store_queue[lsq];
+                            STORE_QUEUE_NB_USE    [lsq]      ++;
+                            STORE_QUEUE_USE       [lsq][ptr] = true;
+                          }
+                      }
+                    else
+                      {
+                        log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * USE_LOAD_QUEUE");
+                        
+                        internal_INSERT_OPERATION_USE [i] = OPERATION_USE_LOAD_QUEUE;
+                        
+                        ptr = LOAD_QUEUE_PTR_WRITE [lsq];
+                        ack = (not LOAD_QUEUE_USE [lsq][ptr]);
+                        
+                        if (ack)
+                          {
+                            LOAD_QUEUE_PTR_WRITE [lsq]      = (ptr+1)%_param->_size_load_queue[lsq];
+                            LOAD_QUEUE_USE       [lsq][ptr] = true;
+                          }
+                      }
+                    
+                    log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * ptr          : %d",ptr         );
+                    log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * ack          : %d",ack         );
+                    
+                    internal_INSERT_LSQ [i] = lsq;
+                    internal_INSERT_PTR [i] = ptr;
+                  }
+              }
+          }
 
-		uint32_t   ptr;
+        if (not find)
+          {
+            ack = true;
+            
+            internal_INSERT_OPERATION_USE [i] = OPERATION_USE_NONE;
+          }
 
-                PORT_WRITE(out_INSERT_STORE_QUEUE_PTR_WRITE [i],     STORE_QUEUE_PTR_WRITE [lsq]);
-//                 PORT_WRITE(out_INSERT_STORE_QUEUE_PTR_READ  [i], ((reg_STORE_QUEUE_PTR_READ  [front_end_id][context_id]+1)%_param->_size_load_queue[lsq]));
-                PORT_WRITE(out_INSERT_STORE_QUEUE_PTR_READ  [i], reg_STORE_QUEUE_PTR_READ  [front_end_id][context_id]);
-                PORT_WRITE(out_INSERT_STORE_QUEUE_EMPTY     [i], reg_STORE_QUEUE_EMPTY     [front_end_id][context_id]);
-                if (_param->_have_port_load_queue_ptr)
-                PORT_WRITE(out_INSERT_LOAD_QUEUE_PTR_WRITE  [i], LOAD_QUEUE_PTR_WRITE  [lsq]);
-
-                log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * sq_ptr_write : %d",STORE_QUEUE_PTR_WRITE [lsq]);
-                log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * lq_ptr_write : %d",LOAD_QUEUE_PTR_WRITE [lsq]);
-		
-		// operation became of decod_stage. Also operation is != store_head_ok and store_head_ko
-		if (is_operation_memory_store(PORT_READ(in_INSERT_OPERATION [i])))
-		  {
-                    log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * USE_STORE_QUEUE");
-                
-		    internal_INSERT_OPERATION_USE [i] = OPERATION_USE_STORE_QUEUE;
-		    
-		    ptr = STORE_QUEUE_PTR_WRITE [lsq];
-		    ack = not STORE_QUEUE_USE [lsq][ptr] and (static_cast<uint32_t>(STORE_QUEUE_NB_USE [lsq]+1) < _param->_size_store_queue[lsq]);
-
-                    if (ack)
-                      {
-                        STORE_QUEUE_PTR_WRITE [lsq]      = (ptr+1)%_param->_size_store_queue[lsq];
-                        STORE_QUEUE_NB_USE    [lsq]      ++;
-                        STORE_QUEUE_USE       [lsq][ptr] = true;
-                      }
-		  }
-		else
-		  {
-                    log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * USE_LOAD_QUEUE");
-
-		    internal_INSERT_OPERATION_USE [i] = OPERATION_USE_LOAD_QUEUE;
-		    
-		    ptr = LOAD_QUEUE_PTR_WRITE [lsq];
-		    ack = (not LOAD_QUEUE_USE [lsq][ptr]);
-
-                    if (ack)
-                      {
-                        LOAD_QUEUE_PTR_WRITE [lsq]      = (ptr+1)%_param->_size_load_queue[lsq];
-                        LOAD_QUEUE_USE       [lsq][ptr] = true;
-                      }
-		  }
-
-                log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * ptr          : %d",ptr         );
-                log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"    * ack          : %d",ack         );
-		
-		internal_INSERT_LSQ [i] = lsq;
-		internal_INSERT_PTR [i] = ptr;
-	      }
-	  }
-	else
-	  {
-	    ack = true;
-
-	    internal_INSERT_OPERATION_USE [i] = OPERATION_USE_NONE;
-	  }
 
 	// Write output
@@ -142,5 +149,4 @@
         for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
           internal_INSERT_ACK [i] = 0;
-
       }
     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue.cpp	(revision 138)
@@ -186,9 +186,7 @@
 	// List dependency information
 # endif    
-
-
-	
-#endif
       }
+#endif
+
     log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"End");
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit.cpp	(revision 138)
@@ -71,5 +71,5 @@
 #endif
 
-#ifdef SYSTEMC
+#if defined(SYSTEMC) and (defined(STATISTICS) or defined(VHDL_TESTBENCH))
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
@@ -83,7 +83,6 @@
 	// List dependency information
 # endif    
-	
+      }
 #endif
-      }
     log_printf(FUNC,Register_translation_unit,FUNCTION,"End");
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit.cpp	(revision 138)
@@ -72,5 +72,5 @@
 #endif
 
-#ifdef SYSTEMC
+#if defined(SYSTEMC) and (defined(STATISTICS) or defined(VHDL_TESTBENCH))
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
@@ -84,7 +84,6 @@
 	// List dependency information
 # endif    
-	
+      }
 #endif
-      }
     log_end(Rename_unit,FUNCTION);
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/Makefile.deps
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/Makefile.deps	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/Makefile.deps	(revision 138)
@@ -11,18 +11,18 @@
 
 ifndef Behavioural
-include 			$(DIR_MORPHEO)/Behavioural/Makefile.deps
+include 				$(DIR_MORPHEO)/Behavioural/Makefile.deps
 endif
 
 #-----[ Directory ]----------------------------------------
 
-Special_Register_unit_DIR			=	$(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit
+Special_Register_unit_DIR		=	$(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit
 
 #-----[ Library ]------------------------------------------
 
 Special_Register_unit_LIBRARY		= 	-lSpecial_Register_unit	\
-					$(Behavioural_LIBRARY)	
+						$(Behavioural_LIBRARY)	
 
-Special_Register_unit_DIR_LIBRARY		=	-L$(Special_Register_unit_DIR)/lib	\
-					$(Behavioural_DIR_LIBRARY)
+Special_Register_unit_DIR_LIBRARY	=	-L$(Special_Register_unit_DIR)/lib	\
+						$(Behavioural_DIR_LIBRARY)
 
 #-----[ Rules ]--------------------------------------------
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h	(revision 138)
@@ -449,4 +449,9 @@
   public : void   write (Tspr_t x) 
     {
+      // old flag 
+      Tspr_t   old_ov = ov;
+      Tspr_t   old_cy = cy;
+      Tspr_t   old_f  = f;
+      
       cid   = x >> 28;
       sumra = x >> 16;
@@ -466,4 +471,9 @@
       tee   = x >>  1;
       sm    = x >>  0;
+
+      if ((old_ov != ov) or
+          (old_cy != cy) or
+          (old_f  != f))
+        msgWarning(_("Flag OV, CY and F are renamed. You can't modify this flag with the instruction l.mtspr.\n"));
     };
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h	(revision 138)
@@ -53,4 +53,6 @@
   public : uint32_t              _size_re_order_buffer             ;
   public : uint32_t              _nb_re_order_buffer_bank          ;
+  public : commit_unit::Tretire_ooo_scheme_t
+                                 _retire_ooo_scheme                ;
   public : Tpriority_t           _commit_priority                  ;
   public : Tload_balancing_t     _commit_load_balancing            ;
@@ -66,6 +68,4 @@
     // Reexecute
   public : uint32_t              _size_reexecute_queue             ;
-  public : Tpriority_t           _reexecute_priority               ;
-  public : Tload_balancing_t     _reexecute_load_balancing         ;
     // Rename_unit
   public : Tpriority_t         * _rename_select_priority           ;//[nb_rename_unit]
@@ -150,4 +150,6 @@
                         uint32_t              size_re_order_buffer             ,
                         uint32_t              nb_re_order_buffer_bank          ,
+                        commit_unit::Tretire_ooo_scheme_t
+                                              retire_ooo_scheme                ,
                         Tpriority_t           commit_priority                  ,
                         Tload_balancing_t     commit_load_balancing            ,
@@ -163,6 +165,4 @@
                         // Reexecute
                         uint32_t              size_reexecute_queue             ,
-                        Tpriority_t           reexecute_priority               ,
-                        Tload_balancing_t     reexecute_load_balancing         ,
                         // Rename_unit
                         Tpriority_t         * rename_select_priority           ,//[nb_rename_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine.cpp	(revision 138)
@@ -71,5 +71,5 @@
 #endif
 
-#ifdef SYSTEMC
+#if defined(SYSTEMC) and (defined(STATISTICS) or defined(VHDL_TESTBENCH))
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
@@ -83,7 +83,6 @@
 	// List dependency information
 # endif    
-	
+      }
 #endif
-      }
     log_end(OOO_Engine,FUNCTION);
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp	(revision 138)
@@ -40,4 +40,6 @@
                           uint32_t              size_re_order_buffer             ,
                           uint32_t              nb_re_order_buffer_bank          ,
+                          commit_unit::Tretire_ooo_scheme_t
+                                                retire_ooo_scheme                ,
                           Tpriority_t           commit_priority                  ,
                           Tload_balancing_t     commit_load_balancing            ,
@@ -53,6 +55,4 @@
                           // Reexecute
                           uint32_t              size_reexecute_queue             ,
-                          Tpriority_t           reexecute_priority               ,
-                          Tload_balancing_t     reexecute_load_balancing         ,
                           // Rename_unit
                           Tpriority_t         * rename_select_priority           ,//[nb_rename_unit]
@@ -100,4 +100,5 @@
     _size_re_order_buffer              = size_re_order_buffer             ;
     _nb_re_order_buffer_bank           = nb_re_order_buffer_bank          ;
+    _retire_ooo_scheme                 = retire_ooo_scheme                ;
     _commit_priority                   = commit_priority                  ;
     _commit_load_balancing             = commit_load_balancing            ;
@@ -110,6 +111,4 @@
 //     _table_issue_type                  = table_issue_type                 ;
     _size_reexecute_queue              = size_reexecute_queue             ;
-    _reexecute_priority                = reexecute_priority               ;
-    _reexecute_load_balancing          = reexecute_load_balancing         ;
     _rename_select_priority            = rename_select_priority           ;
     _rename_select_load_balancing      = rename_select_load_balancing     ;
@@ -256,4 +255,5 @@
        _size_re_order_buffer    ,
        _nb_re_order_buffer_bank ,
+       _retire_ooo_scheme       ,
        _nb_inst_insert          ,
        _nb_inst_retire          ,
@@ -268,6 +268,6 @@
         size_general_register   ,
         size_special_register   ,
-       _commit_priority         ,
-       _commit_load_balancing   ,
+       _issue_priority          ,
+       _issue_load_balancing    ,
        _nb_rename_unit_select   ,
        _nb_thread               ,
@@ -312,6 +312,6 @@
        _nb_inst_reexecute       ,
        _nb_execute_loop_select  ,
-       _reexecute_priority      ,
-       _reexecute_load_balancing,
+       _commit_priority         ,
+       _commit_load_balancing   ,
         size_general_register   ,//+_size_rename_id
         size_special_register   ,//+_size_rename_id
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp	(revision 138)
@@ -65,6 +65,4 @@
 //  str+= toString(MSG_INFORMATION)+"   * table_issue_type                   ["+toString(i)+"]["+toString(j)+"] : "+toString<bool             >(_table_issue_type [i][j]          )+"\n";//[nb_inst_issue][nb_type]
     str+= toString(MSG_INFORMATION)+"   * size_reexecute_queue             : "+toString<uint32_t         >(_size_reexecute_queue             )+"\n";
-    str+= toString(MSG_INFORMATION)+"   * reexecute_priority               : "+toString<Tpriority_t      >(_reexecute_priority               )+"\n";
-    str+= toString(MSG_INFORMATION)+"   * reexecute_load_balancing         : "+toString<Tload_balancing_t>(_reexecute_load_balancing         )+"\n";
     for (uint32_t i=0; i<_nb_rename_unit; ++i)
     str+= toString(MSG_INFORMATION)+"   * rename_select_priority             ["+toString(i)+"] : "+toString<Tpriority_t      >(_rename_select_priority           [i])+"\n";//[nb_rename_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h	(revision 138)
@@ -28,5 +28,4 @@
 
 namespace core {
-
 
   class Parameters : public morpheo::behavioural::Parameters
@@ -75,4 +74,5 @@
   // Read bloc
   public : uint32_t                _nb_read_bloc                                  ;//
+  public : uint32_t              * _nb_inst_read                                  ;//[nb_read_bloc]
   public : uint32_t              * _size_read_queue                               ;//[nb_read_bloc]
   public : uint32_t              * _size_reservation_station                      ;//[nb_read_bloc]
@@ -81,4 +81,5 @@
   // Write bloc
   public : uint32_t                _nb_write_bloc                                 ;//
+  public : uint32_t              * _nb_inst_write                                 ;//[nb_write_bloc]
   public : uint32_t              * _size_write_queue                              ;//[nb_write_bloc]
   public : uint32_t              * _size_execute_queue                            ;//[nb_write_bloc]
@@ -91,7 +92,12 @@
   public : uint32_t              * _size_load_queue                               ;//[nb_load_store_unit]
   public : uint32_t              * _size_speculative_access_queue                 ;//[nb_load_store_unit]
+  public : uint32_t              * _nb_store_queue_bank                           ;//[nb_load_store_unit]
+  public : uint32_t              * _nb_load_queue_bank                            ;//[nb_load_store_unit]
   public : uint32_t              * _nb_port_check                                 ;//[nb_load_store_unit]
   public : multi_execute_loop::execute_loop::Tspeculative_load_t  
                                  * _speculative_load                              ;//[nb_load_store_unit]
+  public : Tpredictor_t          * _speculative_commit_predictor_scheme           ;//[nb_load_store_unit]
+  public : uint32_t             ** _lsu_pht_size_counter                          ;//[nb_load_store_unit][1]
+  public : uint32_t             ** _lsu_pht_nb_counter                            ;//[nb_load_store_unit][1]
   public : uint32_t              * _nb_bypass_memory                              ;//[nb_load_store_unit]
   public : uint32_t              * _nb_cache_port                                 ;//[nb_load_store_unit]
@@ -138,5 +144,5 @@
   public : uint32_t              * _nb_rename_unit                                ;//[nb_ooo_engine]
   public : uint32_t              * _nb_inst_issue_queue                           ;//[nb_ooo_engine]
-  public : uint32_t              * _nb_inst_issue_slot                            ;//[nb_ooo_engine]
+//public : uint32_t              * _nb_inst_issue_slot                            ;//[nb_ooo_engine]
   public : uint32_t              * _nb_inst_reexecute                             ;//[nb_ooo_engine]
   public : uint32_t              * _nb_inst_commit                                ;//[nb_ooo_engine]
@@ -146,4 +152,6 @@
   public : uint32_t              * _size_re_order_buffer                          ;//[nb_ooo_engine]
   public : uint32_t              * _nb_re_order_buffer_bank                       ;//[nb_ooo_engine]
+  public : multi_ooo_engine::ooo_engine::commit_unit::Tretire_ooo_scheme_t
+                                 * _retire_ooo_scheme                             ;//[nb_ooo_engine]
   public : Tpriority_t           * _commit_priority                               ;//[nb_ooo_engine]
   public : Tload_balancing_t     * _commit_load_balancing                         ;//[nb_ooo_engine]
@@ -156,6 +164,4 @@
   public : Tload_balancing_t     * _issue_load_balancing                          ;//[nb_ooo_engine]
   public : uint32_t              * _size_reexecute_queue                          ;//[nb_ooo_engine]
-  public : Tpriority_t           * _reexecute_priority                            ;//[nb_ooo_engine]
-  public : Tload_balancing_t     * _reexecute_load_balancing                      ;//[nb_ooo_engine]
 
   //Execute_loop
@@ -183,8 +189,8 @@
   public : uint32_t              * _link_decod_bloc_with_thread                   ;//[nb_thread]
   public : uint32_t              * _link_rename_bloc_with_front_end               ;//[nb_front_end]
-  public : bool                *** _table_dispatch                                ;//[nb_ooo_engine][nb_inst_issue_slot][nb_read_bloc]
-  public : bool                 ** _link_read_bloc_and_load_store_unit            ;//[nb_read_bloc][nb_load_store_unit]
+//public : bool                *** _table_dispatch                                ;//[nb_ooo_engine][nb_inst_issue_slot][nb_read_bloc]
+  public : uint32_t              * _link_read_bloc_with_load_store_unit           ;//[nb_load_store_unit]
   public : bool                 ** _link_read_bloc_and_functionnal_unit           ;//[nb_read_bloc][nb_functionnal_unit]
-  public : bool                 ** _link_write_bloc_and_load_store_unit           ;//[nb_write_bloc][nb_load_store_unit]
+  public : uint32_t              * _link_write_bloc_with_load_store_unit          ;//[nb_load_store_unit]
   public : bool                 ** _link_write_bloc_and_functionnal_unit          ;//[nb_write_bloc][nb_functionnal_unit]
   public : uint32_t              * _link_load_store_unit_with_thread              ;//[nb_thread]
@@ -276,4 +282,5 @@
   public : uint32_t              * _execute_loop_nb_thread                                 ;//[nb_execute_loop]
   public : uint32_t              * _execute_loop_nb_packet                                 ;//[nb_execute_loop]
+  public : uint32_t             ** _execute_loop_nb_inst_read                              ;//[nb_execute_loop][nb_read_unit]
   public : uint32_t             ** _execute_loop_size_read_queue                           ;//[nb_execute_loop][nb_read_unit]
   public : uint32_t             ** _execute_loop_size_reservation_station                  ;//[nb_execute_loop][nb_read_unit]
@@ -285,10 +292,16 @@
   public : uint32_t             ** _execute_loop_size_load_queue                           ;//[nb_execute_loop][execute_loop_nb_load_store_unit]
   public : uint32_t             ** _execute_loop_size_speculative_access_queue             ;//[nb_execute_loop][execute_loop_nb_load_store_unit]
+  public : uint32_t             ** _execute_loop_nb_store_queue_bank                       ;//[nb_execute_loop][execute_loop_nb_load_store_unit]
+  public : uint32_t             ** _execute_loop_nb_load_queue_bank                        ;//[nb_execute_loop][execute_loop_nb_load_store_unit]
   public : uint32_t             ** _execute_loop_nb_port_check                             ;//[nb_execute_loop][execute_loop_nb_load_store_unit]
   public : multi_execute_loop::execute_loop::Tspeculative_load_t
                                 ** _execute_loop_speculative_load                          ;//[nb_execute_loop][execute_loop_nb_load_store_unit]
+  public : Tpredictor_t         ** _execute_loop_speculative_commit_predictor_scheme       ;//[nb_execute_loop][execute_loop_nb_load_store_unit]
+  public : uint32_t            *** _execute_loop_lsu_pht_size_counter                      ;//[nb_execute_loop][execute_loop_nb_load_store_unit][1]
+  public : uint32_t            *** _execute_loop_lsu_pht_nb_counter                        ;//[nb_execute_loop][execute_loop_nb_load_store_unit][1]
   public : uint32_t             ** _execute_loop_nb_bypass_memory                          ;//[nb_execute_loop][execute_loop_nb_load_store_unit]
   public : uint32_t             ** _execute_loop_nb_cache_port                             ;//[nb_execute_loop][execute_loop_nb_load_store_unit]
   public : uint32_t             ** _execute_loop_nb_inst_memory                            ;//[nb_execute_loop][execute_loop_nb_load_store_unit]
+  public : uint32_t             ** _execute_loop_nb_inst_write                             ;//[nb_execute_loop][nb_write_unit]
   public : uint32_t             ** _execute_loop_size_write_queue                          ;//[nb_execute_loop][nb_write_unit]
   public : uint32_t             ** _execute_loop_size_execute_queue                        ;//[nb_execute_loop][nb_write_unit]
@@ -325,5 +338,5 @@
   public : uint32_t             ** _dcache_access_size_packet_id                  ;//[nb_execute_loop][execute_loop_nb_load_store_unit]
   public : uint32_t            *** _dcache_access_table_routing                   ;//[nb_execute_loop][execute_loop_nb_load_store_unit][execute_loop_nb_cache_port]
-  public : uint32_t              * _dcache_access_nb_context                         ;//[nb_execute_loop]
+  public : uint32_t              * _dcache_access_nb_context                      ;//[nb_execute_loop]
   public : uint32_t            *** _dcache_access_translate_load_store_unit_to_thread;//[nb_execute_loop][execute_loop_nb_load_store_unit][dcache_access_nb_context]
 
@@ -338,7 +351,7 @@
 
 
-  public : bool               **** _network_table_dispatch                        ;//[nb_ooo_engine][nb_inst_issue_slot][nb_execute_loop][nb_read_unit]
+//public : bool               **** _network_table_dispatch                        ;//[nb_ooo_engine][nb_inst_issue_slot][nb_execute_loop][nb_read_unit]
   public : bool                *** _network_table_issue_type                      ;//                                   [nb_execute_loop][nb_read_unit][nb_type]
-
+  public : bool                *** _network_table_issue_thread                    ;//                                   [nb_execute_loop][nb_read_unit][nb_thread]
 
   // Translate
@@ -398,4 +411,5 @@
   // Read bloc
   uint32_t                nb_read_bloc                                  ,//
+  uint32_t              * nb_inst_read                                  ,//[nb_read_bloc]
   uint32_t              * size_read_queue                               ,//[nb_read_bloc]
   uint32_t              * size_reservation_station                      ,//[nb_read_bloc]
@@ -404,4 +418,5 @@
   // Write bloc
   uint32_t                nb_write_bloc                                 ,//
+  uint32_t              * nb_inst_write                                 ,//[nb_write_bloc]
   uint32_t              * size_write_queue                              ,//[nb_write_bloc]
   uint32_t              * size_execute_queue                            ,//[nb_write_bloc]
@@ -414,7 +429,12 @@
   uint32_t              * size_load_queue                               ,//[nb_load_store_unit]
   uint32_t              * size_speculative_access_queue                 ,//[nb_load_store_unit]
+  uint32_t              * nb_store_queue_bank                           ,//[nb_load_store_unit]
+  uint32_t              * nb_load_queue_bank                            ,//[nb_load_store_unit]
   uint32_t              * nb_port_check                                 ,//[nb_load_store_unit]
   multi_execute_loop::execute_loop::Tspeculative_load_t  
                         * speculative_load                              ,//[nb_load_store_unit]
+  Tpredictor_t          * speculative_commit_predictor_scheme           ,//[nb_load_store_unit]
+  uint32_t             ** lsu_pht_size_counter                          ,//[nb_load_store_unit][1]
+  uint32_t             ** lsu_pht_nb_counter                            ,//[nb_load_store_unit][1]
   uint32_t              * nb_bypass_memory                              ,//[nb_load_store_unit]
   uint32_t              * nb_cache_port                                 ,//[nb_load_store_unit]
@@ -460,5 +480,5 @@
   uint32_t                nb_ooo_engine                                 ,
   uint32_t              * nb_rename_unit                                ,//[nb_ooo_engine]
-  uint32_t              * nb_inst_issue_slot                            ,//[nb_ooo_engine]
+//uint32_t              * nb_inst_issue_slot                            ,//[nb_ooo_engine]
   uint32_t              * nb_inst_reexecute                             ,//[nb_ooo_engine]
   uint32_t              * nb_inst_commit                                ,//[nb_ooo_engine]
@@ -468,4 +488,6 @@
   uint32_t              * size_re_order_buffer                          ,//[nb_ooo_engine]
   uint32_t              * nb_re_order_buffer_bank                       ,//[nb_ooo_engine]
+  multi_ooo_engine::ooo_engine::commit_unit::Tretire_ooo_scheme_t
+                        * retire_ooo_scheme                             ,//[nb_ooo_engine]
   Tpriority_t           * commit_priority                               ,//[nb_ooo_engine]
   Tload_balancing_t     * commit_load_balancing                         ,//[nb_ooo_engine]
@@ -477,6 +499,4 @@
   Tload_balancing_t     * issue_load_balancing                          ,//[nb_ooo_engine]
   uint32_t              * size_reexecute_queue                          ,//[nb_ooo_engine]
-  Tpriority_t           * reexecute_priority                            ,//[nb_ooo_engine]
-  Tload_balancing_t     * reexecute_load_balancing                      ,//[nb_ooo_engine]
 
   //Execute_loop
@@ -504,8 +524,8 @@
   uint32_t              * link_decod_bloc_with_thread                   ,//[nb_thread]
   uint32_t              * link_rename_bloc_with_front_end               ,//[nb_front_end]
-  bool                *** table_dispatch                                ,//[nb_ooo_engine][nb_inst_issue_slot][nb_read_bloc]
-  bool                 ** link_read_bloc_and_load_store_unit            ,//[nb_read_bloc][nb_load_store_unit]
+//bool                *** table_dispatch                                ,//[nb_ooo_engine][nb_inst_issue_slot][nb_read_bloc]
+  uint32_t              * link_read_bloc_with_load_store_unit           ,//[nb_load_store_unit]
   bool                 ** link_read_bloc_and_functionnal_unit           ,//[nb_read_bloc][nb_functionnal_unit]
-  bool                 ** link_write_bloc_and_load_store_unit           ,//[nb_write_bloc][nb_load_store_unit]
+  uint32_t              * link_write_bloc_with_load_store_unit          ,//[nb_load_store_unit]
   bool                 ** link_write_bloc_and_functionnal_unit          ,//[nb_write_bloc][nb_functionnal_unit]
   uint32_t              * link_load_store_unit_with_thread              ,//[nb_thread]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp	(revision 138)
@@ -67,4 +67,15 @@
   }
 
+#undef  FUNCTION
+#define FUNCTION "Core::sort_and_unique"
+  //template <typename T>
+  std::vector<uint32_t> sort_and_unique (std::vector<uint32_t> v)
+  {
+    sort (v.begin(), v.end());
+    std::vector<uint32_t>::iterator it=std::unique(v.begin(), v.end());
+    v.erase(it,v.end());
+
+    return v;
+  }
 
 #undef  FUNCTION
@@ -112,4 +123,5 @@
   // Read bloc
   uint32_t                nb_read_bloc                                  ,//
+  uint32_t              * nb_inst_read                                  ,//[nb_read_bloc]
   uint32_t              * size_read_queue                               ,//[nb_read_bloc]
   uint32_t              * size_reservation_station                      ,//[nb_read_bloc]
@@ -118,4 +130,5 @@
   // Write bloc
   uint32_t                nb_write_bloc                                 ,//
+  uint32_t              * nb_inst_write                                 ,//[nb_write_bloc]
   uint32_t              * size_write_queue                              ,//[nb_write_bloc]
   uint32_t              * size_execute_queue                            ,//[nb_write_bloc]
@@ -128,7 +141,12 @@
   uint32_t              * size_load_queue                               ,//[nb_load_store_unit]
   uint32_t              * size_speculative_access_queue                 ,//[nb_load_store_unit]
+  uint32_t              * nb_store_queue_bank                           ,//[nb_load_store_unit]
+  uint32_t              * nb_load_queue_bank                            ,//[nb_load_store_unit]
   uint32_t              * nb_port_check                                 ,//[nb_load_store_unit]
   multi_execute_loop::execute_loop::Tspeculative_load_t  
                         * speculative_load                              ,//[nb_load_store_unit]
+  Tpredictor_t          * speculative_commit_predictor_scheme           ,//[nb_load_store_unit]
+  uint32_t             ** lsu_pht_size_counter                          ,//[nb_load_store_unit][1]
+  uint32_t             ** lsu_pht_nb_counter                            ,//[nb_load_store_unit][1]
   uint32_t              * nb_bypass_memory                              ,//[nb_load_store_unit]
   uint32_t              * nb_cache_port                                 ,//[nb_load_store_unit]
@@ -174,5 +192,5 @@
   uint32_t                nb_ooo_engine                                 ,
   uint32_t              * nb_rename_unit                                ,//[nb_ooo_engine]
-  uint32_t              * nb_inst_issue_slot                            ,//[nb_ooo_engine]
+//uint32_t              * nb_inst_issue_slot                            ,//[nb_ooo_engine]
   uint32_t              * nb_inst_reexecute                             ,//[nb_ooo_engine]
   uint32_t              * nb_inst_commit                                ,//[nb_ooo_engine]
@@ -182,4 +200,6 @@
   uint32_t              * size_re_order_buffer                          ,//[nb_ooo_engine]
   uint32_t              * nb_re_order_buffer_bank                       ,//[nb_ooo_engine]
+  multi_ooo_engine::ooo_engine::commit_unit::Tretire_ooo_scheme_t
+                        * retire_ooo_scheme                             ,//[nb_ooo_engine]
   Tpriority_t           * commit_priority                               ,//[nb_ooo_engine]
   Tload_balancing_t     * commit_load_balancing                         ,//[nb_ooo_engine]
@@ -191,6 +211,4 @@
   Tload_balancing_t     * issue_load_balancing                          ,//[nb_ooo_engine]
   uint32_t              * size_reexecute_queue                          ,//[nb_ooo_engine]
-  Tpriority_t           * reexecute_priority                            ,//[nb_ooo_engine]
-  Tload_balancing_t     * reexecute_load_balancing                      ,//[nb_ooo_engine]
 
   //Execute_loop
@@ -218,8 +236,8 @@
   uint32_t              * link_decod_bloc_with_thread                   ,//[nb_thread]
   uint32_t              * link_rename_bloc_with_front_end               ,//[nb_front_end]
-  bool                *** table_dispatch                                ,//[nb_ooo_engine][nb_inst_issue_slot][nb_read_bloc]
-  bool                 ** link_read_bloc_and_load_store_unit            ,//[nb_read_bloc][nb_load_store_unit]
+//bool                *** table_dispatch                                ,//[nb_ooo_engine][nb_inst_issue_slot][nb_read_bloc]
+  uint32_t              * link_read_bloc_with_load_store_unit           ,//[nb_load_store_unit]
   bool                 ** link_read_bloc_and_functionnal_unit           ,//[nb_read_bloc][nb_functionnal_unit]
-  bool                 ** link_write_bloc_and_load_store_unit           ,//[nb_write_bloc][nb_load_store_unit]
+  uint32_t              * link_write_bloc_with_load_store_unit          ,//[nb_load_store_unit]
   bool                 ** link_write_bloc_and_functionnal_unit          ,//[nb_write_bloc][nb_functionnal_unit]
   uint32_t              * link_load_store_unit_with_thread              ,//[nb_thread]
@@ -268,4 +286,5 @@
 
     _nb_read_bloc                            = nb_read_bloc                            ;
+    _nb_inst_read                            = nb_inst_read                            ;
     _size_read_queue                         = size_read_queue                         ;
     _size_reservation_station                = size_reservation_station                ;
@@ -273,4 +292,5 @@
 
     _nb_write_bloc                           = nb_write_bloc                           ;
+    _nb_inst_write                           = nb_inst_write                           ;
     _size_write_queue                        = size_write_queue                        ;
     _size_execute_queue                      = size_execute_queue                      ;
@@ -282,6 +302,11 @@
     _size_load_queue                         = size_load_queue                         ;
     _size_speculative_access_queue           = size_speculative_access_queue           ;
+    _nb_store_queue_bank                     = nb_store_queue_bank                     ;
+    _nb_load_queue_bank                      = nb_load_queue_bank                      ;
     _nb_port_check                           = nb_port_check                           ;
     _speculative_load                        = speculative_load                        ;
+    _speculative_commit_predictor_scheme     = speculative_commit_predictor_scheme     ;
+    _lsu_pht_size_counter                    = lsu_pht_size_counter                    ;
+    _lsu_pht_nb_counter                      = lsu_pht_nb_counter                      ;
     _nb_bypass_memory                        = nb_bypass_memory                        ;
     _nb_cache_port                           = nb_cache_port                           ;
@@ -321,5 +346,5 @@
     _nb_ooo_engine                           = nb_ooo_engine                           ;
     _nb_rename_unit                          = nb_rename_unit                          ;
-    _nb_inst_issue_slot                      = nb_inst_issue_slot                      ;
+//  _nb_inst_issue_slot                      = nb_inst_issue_slot                      ;
     _nb_inst_reexecute                       = nb_inst_reexecute                       ;
     _nb_inst_commit                          = nb_inst_commit                          ;
@@ -329,4 +354,5 @@
     _size_re_order_buffer                    = size_re_order_buffer                    ;
     _nb_re_order_buffer_bank                 = nb_re_order_buffer_bank                 ;
+    _retire_ooo_scheme                       = retire_ooo_scheme                       ;
     _commit_priority                         = commit_priority                         ;
     _commit_load_balancing                   = commit_load_balancing                   ;
@@ -337,6 +363,4 @@
     _issue_load_balancing                    = issue_load_balancing                    ;
     _size_reexecute_queue                    = size_reexecute_queue                    ;
-    _reexecute_priority                      = reexecute_priority                      ;
-    _reexecute_load_balancing                = reexecute_load_balancing                ;
 
     _nb_execute_loop                         = nb_execute_loop                         ;
@@ -362,8 +386,8 @@
     _link_decod_bloc_with_thread             = link_decod_bloc_with_thread             ;
     _link_rename_bloc_with_front_end         = link_rename_bloc_with_front_end         ;
-    _table_dispatch                          = table_dispatch                          ;
-    _link_read_bloc_and_load_store_unit      = link_read_bloc_and_load_store_unit      ;
+//  _table_dispatch                          = table_dispatch                          ;
+    _link_read_bloc_with_load_store_unit     = link_read_bloc_with_load_store_unit     ;
     _link_read_bloc_and_functionnal_unit     = link_read_bloc_and_functionnal_unit     ;
-    _link_write_bloc_and_load_store_unit     = link_write_bloc_and_load_store_unit     ;
+    _link_write_bloc_with_load_store_unit    = link_write_bloc_with_load_store_unit    ;
     _link_write_bloc_and_functionnal_unit    = link_write_bloc_and_functionnal_unit    ;
     _link_load_store_unit_with_thread        = link_load_store_unit_with_thread        ;
@@ -885,35 +909,70 @@
 
     {
-      std::vector<uint32_t> list_execute_loop [_nb_ooo_engine];
-
       // initialization counter
       for (uint32_t i=0; i<_nb_ooo_engine; ++i)
         _ooo_engine_nb_execute_loop [i] = 0;
-
-      // scan the dispatch table
+            
+      std::vector<uint32_t> list_execute_loop [_nb_ooo_engine];
+
+      for (uint32_t i=0; i<_nb_thread; ++i)
+        {
+          uint32_t num_front_end    = _link_context_with_thread [i].first;
+          uint32_t num_rename_bloc  = _link_rename_bloc_with_front_end [num_front_end];
+          uint32_t num_ooo_engine   = _link_rename_unit_with_rename_bloc [num_rename_bloc].first;
+          uint32_t num_execute_loop = _link_execute_unit_with_load_store_unit [i].first;
+          list_execute_loop[num_ooo_engine].push_back(num_execute_loop);
+
+          // One execute per ooo_engine
+          // for (uint32_t j=0; j<_nb_functionnal_unit; ++j)
+          //   if (_link_thread_and_functionnal_unit [i][j])
+          //     {
+          //       uint32_t num_execute_loop = _link_execute_unit_with_functionnal_unit [i].first;
+          //       list_execute_loop[num_ooo_engine].push_back(num_execute_loop);
+          //     }
+        }
+
+      // Sort and erase duplicate value
       for (uint32_t i=0; i<_nb_ooo_engine; ++i)
         {
-          for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j)
-            for (uint32_t k=0; k<_nb_read_bloc; ++k)
-              {
-                // have route between this slot's ooo_engine and an read_bloc
-                if (_table_dispatch [i][j][k])
-                  {
-                    uint32_t num_execute_loop = _link_read_unit_with_read_bloc [k].first;
-                    
-                    list_execute_loop[i].push_back(num_execute_loop);
-                  }
-              }
-                
-          {
-            sort  (list_execute_loop[i].begin(),
-                   list_execute_loop[i].end());
-            std::vector<uint32_t>::iterator it=std::unique(list_execute_loop[i].begin(),
-                                                           list_execute_loop[i].end());
-            list_execute_loop[i].erase(it,list_execute_loop[i].end());
-          }
-
+          list_execute_loop[i] = sort_and_unique (list_execute_loop[i]);
+
+          // {
+          //   sort  (list_execute_loop[i].begin(),
+          //          list_execute_loop[i].end());
+          //   std::vector<uint32_t>::iterator it=std::unique(list_execute_loop[i].begin(),
+          //                                                  list_execute_loop[i].end());
+          //   list_execute_loop[i].erase(it,list_execute_loop[i].end());
+          // }
+          
           _ooo_engine_nb_execute_loop [i] = list_execute_loop[i].size();
         }
+
+#if 0
+      // // scan the dispatch table
+      // for (uint32_t i=0; i<_nb_ooo_engine; ++i)
+      //   {
+      //     for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j)
+      //       for (uint32_t k=0; k<_nb_read_bloc; ++k)
+      //         {
+      //           // have route between this slot's ooo_engine and an read_bloc
+      //           if (_table_dispatch [i][j][k])
+      //             {
+      //               uint32_t num_execute_loop = _link_read_unit_with_read_bloc [k].first;
+                    
+      //               list_execute_loop[i].push_back(num_execute_loop);
+      //             }
+      //         }
+                
+      //     {
+      //       sort  (list_execute_loop[i].begin(),
+      //              list_execute_loop[i].end());
+      //       std::vector<uint32_t>::iterator it=std::unique(list_execute_loop[i].begin(),
+      //                                                      list_execute_loop[i].end());
+      //       list_execute_loop[i].erase(it,list_execute_loop[i].end());
+      //     }
+
+      //     _ooo_engine_nb_execute_loop [i] = list_execute_loop[i].size();
+      //   }
+#endif
 
       log_printf(TRACE,Core,FUNCTION,_("  * translate_ooo_engine_num_execute_loop"));
@@ -1029,5 +1088,5 @@
       }
     
-    ALLOC4(_network_table_dispatch                        ,bool             ,_nb_ooo_engine,_nb_inst_issue_slot[it1],_nb_execute_loop,_nb_read_unit[it3]);
+//  ALLOC4(_network_table_dispatch                        ,bool             ,_nb_ooo_engine,_nb_inst_issue_slot[it1],_nb_execute_loop,_nb_read_unit[it3]);
 //  ALLOC3(_ooo_engine_table_routing                      ,bool             ,_nb_ooo_engine,_nb_rename_unit[it1],_nb_inst_issue_slot[it1]);
 //  ALLOC3(_ooo_engine_table_issue_type                   ,bool             ,_nb_ooo_engine,_nb_inst_issue_slot[it1],_nb_type);
@@ -1035,105 +1094,141 @@
     ALLOC2(_list_load_store_unit_with_rename_unit         ,std::vector<uint32_t>,_nb_ooo_engine,_nb_rename_unit[it1]);
 
+    for (uint32_t num_thread=0; num_thread<_nb_thread; ++num_thread)
+      {
+        uint32_t num_front_end    = _link_context_with_thread [num_thread].first;
+        uint32_t num_rename_bloc  = _link_rename_bloc_with_front_end [num_front_end];
+        uint32_t num_ooo_engine   = _link_rename_unit_with_rename_bloc [num_rename_bloc].first;
+        uint32_t num_rename_unit  = _link_rename_unit_with_rename_bloc [num_rename_bloc].second;
+        
+        {
+          uint32_t num_load_store_unit = _link_load_store_unit_with_thread [num_thread];
+          
+          log_printf(TRACE,Core,FUNCTION,_("  * list_load_store_unit_with_rename_unit [%d][%d] = %d"),
+                     num_ooo_engine,
+                     num_rename_unit,
+                     num_load_store_unit);
+          
+          _list_load_store_unit_with_rename_unit [num_ooo_engine][num_rename_unit].push_back(num_load_store_unit);
+        }
+        
+        for (uint32_t num_functionnal_unit=0;
+             num_functionnal_unit<_nb_functionnal_unit;
+             ++num_functionnal_unit)
+          if (_link_thread_and_functionnal_unit[num_thread][num_functionnal_unit])
+            {
+              log_printf(TRACE,Core,FUNCTION,_("  * list_functionnal_unit_with_rename_unit [%d][%d] = %d"),
+                         num_ooo_engine,
+                         num_rename_unit,
+                         num_functionnal_unit);
+              
+              _list_functionnal_unit_with_rename_unit [num_ooo_engine][num_rename_unit].push_back(num_functionnal_unit);
+            }
+      }
+
     for (uint32_t i=0; i<_nb_ooo_engine; ++i)
       {
-//         log_printf(TRACE,Core,FUNCTION,_("  * ooo_engine_table_issue_type [%d]"),i);
-
-        // Init
-        for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j)
-          {
-            for (uint32_t k=0; k<_nb_execute_loop; ++k)
-              for (uint32_t l=0; l<_nb_read_unit[k]; ++l)
-                _network_table_dispatch [i][j][k][l] = false;
-//             for (uint32_t k=0; k<_nb_rename_unit[i]; ++k)
-//               _ooo_engine_table_routing [i][k][j] = false;
-//             for (uint32_t k=0; k<_nb_type; ++k)
-//               _ooo_engine_table_issue_type [i][j][k] = false;
-          }
-
-        std::vector<uint32_t> list_thread_with_inst_issue [_nb_inst_issue_slot[i]];
+#if 0
+// //         log_printf(TRACE,Core,FUNCTION,_("  * ooo_engine_table_issue_type [%d]"),i);
+
+//         // Init
+//         for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j)
+//           {
+//             for (uint32_t k=0; k<_nb_execute_loop; ++k)
+//               for (uint32_t l=0; l<_nb_read_unit[k]; ++l)
+//                 _network_table_dispatch [i][j][k][l] = false;
+//             // for (uint32_t k=0; k<_nb_rename_unit[i]; ++k)
+//             //   _ooo_engine_table_routing [i][k][j] = false;
+//             // for (uint32_t k=0; k<_nb_type; ++k)
+//             //   _ooo_engine_table_issue_type [i][j][k] = false;
+//           }
+
+//         std::vector<uint32_t> list_thread_with_inst_issue [_nb_inst_issue_slot[i]];
         
-        for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j)
-          {
-            for (uint32_t k=0; k<_nb_read_bloc; ++k)
-              // Test if the issue slot is linked with the read_bloc
-              if (_table_dispatch[i][j][k])
-                {
-                  pair_dual x = _link_read_unit_with_read_bloc[k];
-                  _network_table_dispatch [i][j][x.first][x.second] = true;
-
-                  // Test functional unit connected with this read bloc
-                  for (uint32_t l=0; l<_nb_functionnal_unit; ++l)
-                    {
-                      // the issue slot [j] is connected with the read bloc [k] and it's connected with the functionnal_unit [l]
-                      if (_link_read_bloc_and_functionnal_unit [k][l])
-                        {
-                          // Scan timing table, test if have an instruction
-//                           for (uint32_t m=0; m<_nb_type; ++m)
-//                             for (uint32_t n=0; n<_nb_operation; ++n)
-//                               if (_timing[l][m][n]._latence > 0)
-//                                 {
-//                                   log_printf(TRACE,Core,FUNCTION,_("   [%d][%d] -> true"),j,m);
+//         for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j)
+//           {
+//             for (uint32_t k=0; k<_nb_read_bloc; ++k)
+//               // Test if the issue slot is linked with the read_bloc
+//               if (_table_dispatch[i][j][k])
+//                 {
+//                   pair_dual x = _link_read_unit_with_read_bloc[k];
+//                   _network_table_dispatch [i][j][x.first][x.second] = true;
+
+//                   // Test functional unit connected with this read bloc
+//                   for (uint32_t l=0; l<_nb_functionnal_unit; ++l)
+//                     {
+//                       // the issue slot [j] is connected with the read bloc [k] and it's connected with the functionnal_unit [l]
+//                       if (_link_read_bloc_and_functionnal_unit [k][l])
+//                         {
+//                           // Scan timing table, test if have an instruction
+// //                           for (uint32_t m=0; m<_nb_type; ++m)
+// //                             for (uint32_t n=0; n<_nb_operation; ++n)
+// //                               if (_timing[l][m][n]._latence > 0)
+// //                                 {
+// //                                   log_printf(TRACE,Core,FUNCTION,_("   [%d][%d] -> true"),j,m);
                                   
-//                                   _ooo_engine_table_issue_type [i][j][m] = true;
-//                                   break;
-//                                 }
+// //                                   _ooo_engine_table_issue_type [i][j][m] = true;
+// //                                   break;
+// //                                 }
                           
-                          for (uint32_t m=0; m<_nb_thread; ++m)
-                            {
-                              list_thread_with_inst_issue [j].push_back(m);
+//                           for (uint32_t m=0; m<_nb_thread; ++m)
+//                             {
+//                               list_thread_with_inst_issue [j].push_back(m);
                               
-                              uint32_t num_front_end   = _link_context_with_thread [m].first;
-                              uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end];
-                              uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second;
+//                               uint32_t num_front_end   = _link_context_with_thread [m].first;
+//                               uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end];
+//                               uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second;
                               
-                              _list_functionnal_unit_with_rename_unit [i][num_rename_unit].push_back(l);
-                            }
-                        }
-                    }
-
-                  // Test load store unit connected with this read bloc
-                  for (uint32_t l=0; l<_nb_load_store_unit; ++l)
-                    {
-                      // Test load store unit connected with this read bloc
-                      if (_link_read_bloc_and_load_store_unit [k][l])
-                       {
-//                        _ooo_engine_table_issue_type [i][j][TYPE_MEMORY] = true;
-//                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBS)._type][instruction_information(INSTRUCTION_L_LBS)._operation]._latence > 0);
-//                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBZ)._type][instruction_information(INSTRUCTION_L_LBZ)._operation]._latence > 0);
-//                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LD )._type][instruction_information(INSTRUCTION_L_LD )._operation]._latence > 0);
-//                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHS)._type][instruction_information(INSTRUCTION_L_LHS)._operation]._latence > 0);
-//                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHZ)._type][instruction_information(INSTRUCTION_L_LHZ)._operation]._latence > 0);
-//                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWS)._type][instruction_information(INSTRUCTION_L_LWS)._operation]._latence > 0);
-//                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWZ)._type][instruction_information(INSTRUCTION_L_LWZ)._operation]._latence > 0);
-//                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SB )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SB )._type][instruction_information(INSTRUCTION_L_SB )._operation]._latence > 0);
-//                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SD )._type][instruction_information(INSTRUCTION_L_SD )._operation]._latence > 0);
-//                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SH )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SH )._type][instruction_information(INSTRUCTION_L_SH )._operation]._latence > 0);
-//                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SW )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SW )._type][instruction_information(INSTRUCTION_L_SW )._operation]._latence > 0);
-
-                          // the issue slot [j] is connected with the read bloc [k] and it's connected with the load_store_unit [l]
-                          for (uint32_t m=0; m<_nb_thread; ++m)
-                            {
-                              list_thread_with_inst_issue [j].push_back(m);
+//                               _list_functionnal_unit_with_rename_unit [i][num_rename_unit].push_back(l);
+//                             }
+//                         }
+//                     }
+
+//                   // Test load store unit connected with this read bloc
+//                   for (uint32_t l=0; l<_nb_load_store_unit; ++l)
+//                     {
+//                       // Test load store unit connected with this read bloc
+//                       if (_link_read_bloc_and_load_store_unit [k][l])
+//                        {
+// //                        _ooo_engine_table_issue_type [i][j][TYPE_MEMORY] = true;
+// //                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBS)._type][instruction_information(INSTRUCTION_L_LBS)._operation]._latence > 0);
+// //                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBZ)._type][instruction_information(INSTRUCTION_L_LBZ)._operation]._latence > 0);
+// //                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LD )._type][instruction_information(INSTRUCTION_L_LD )._operation]._latence > 0);
+// //                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHS)._type][instruction_information(INSTRUCTION_L_LHS)._operation]._latence > 0);
+// //                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHZ)._type][instruction_information(INSTRUCTION_L_LHZ)._operation]._latence > 0);
+// //                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWS)._type][instruction_information(INSTRUCTION_L_LWS)._operation]._latence > 0);
+// //                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWZ)._type][instruction_information(INSTRUCTION_L_LWZ)._operation]._latence > 0);
+// //                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SB )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SB )._type][instruction_information(INSTRUCTION_L_SB )._operation]._latence > 0);
+// //                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SD )._type][instruction_information(INSTRUCTION_L_SD )._operation]._latence > 0);
+// //                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SH )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SH )._type][instruction_information(INSTRUCTION_L_SH )._operation]._latence > 0);
+// //                        _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SW )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SW )._type][instruction_information(INSTRUCTION_L_SW )._operation]._latence > 0);
+
+//                           // the issue slot [j] is connected with the read bloc [k] and it's connected with the load_store_unit [l]
+//                           for (uint32_t m=0; m<_nb_thread; ++m)
+//                             {
+//                               list_thread_with_inst_issue [j].push_back(m);
                               
-                              uint32_t num_front_end   = _link_context_with_thread [m].first;
-                              uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end];
-                              uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second;
+//                               uint32_t num_front_end   = _link_context_with_thread [m].first;
+//                               uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end];
+//                               uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second;
                               
-                              log_printf(TRACE,Core,FUNCTION,_("  * list_load_store_unit_with_rename_unit [%d][%d][%d] = %d"),i,num_rename_unit,_list_load_store_unit_with_rename_unit [i][num_rename_unit].size(),l);
-
-                              _list_load_store_unit_with_rename_unit [i][num_rename_unit].push_back(l);
-                            }
-                        }
-                    }
-                }
-            // sort and erase duplicate value
-            {
-              sort  (list_thread_with_inst_issue [j].begin(),
-                     list_thread_with_inst_issue [j].end());
-              std::vector<uint32_t>::iterator it=unique(list_thread_with_inst_issue [j].begin(),
-                                                        list_thread_with_inst_issue [j].end());
-              list_thread_with_inst_issue [j].erase(it,list_thread_with_inst_issue [j].end());
-            }
-          }
+//                               log_printf(TRACE,Core,FUNCTION,_("  * list_load_store_unit_with_rename_unit [%d][%d][%d] = %d"),i,num_rename_unit,_list_load_store_unit_with_rename_unit [i][num_rename_unit].size(),l);
+
+//                               _list_load_store_unit_with_rename_unit [i][num_rename_unit].push_back(l);
+//                             }
+//                         }
+//                     }
+//                 }
+//             // sort and erase duplicate value
+//             list_thread_with_inst_issue [j] = sort_and_unique (list_thread_with_inst_issue [j]);
+
+//             // {
+//             //   sort  (list_thread_with_inst_issue [j].begin(),
+//             //          list_thread_with_inst_issue [j].end());
+//             //   std::vector<uint32_t>::iterator it=unique(list_thread_with_inst_issue [j].begin(),
+//             //                                             list_thread_with_inst_issue [j].end());
+//             //   list_thread_with_inst_issue [j].erase(it,list_thread_with_inst_issue [j].end());
+//             // }
+//           }
+#endif
 
         log_printf(TRACE,Core,FUNCTION,_("  * ooo_engine_table_routing [%d]"),i);
@@ -1141,18 +1236,23 @@
           {
             // sort and erase duplicate value
-            {
-              sort  (_list_load_store_unit_with_rename_unit  [i][j].begin(),
-                     _list_load_store_unit_with_rename_unit  [i][j].end());
-              std::vector<uint32_t>::iterator it=unique(_list_load_store_unit_with_rename_unit  [i][j].begin(),
-                                                        _list_load_store_unit_with_rename_unit  [i][j].end());
-              _list_load_store_unit_with_rename_unit  [i][j].erase(it,_list_load_store_unit_with_rename_unit  [i][j].end());
-            }
-            {
-              sort  (_list_functionnal_unit_with_rename_unit  [i][j].begin(),
-                     _list_functionnal_unit_with_rename_unit  [i][j].end());
-              std::vector<uint32_t>::iterator it=unique(_list_functionnal_unit_with_rename_unit  [i][j].begin(),
-                                                        _list_functionnal_unit_with_rename_unit  [i][j].end());
-              _list_functionnal_unit_with_rename_unit  [i][j].erase(it,_list_functionnal_unit_with_rename_unit  [i][j].end());
-            }
+            _list_load_store_unit_with_rename_unit  [i][j] = sort_and_unique (_list_load_store_unit_with_rename_unit  [i][j]);
+
+            // {
+            //   sort  (_list_load_store_unit_with_rename_unit  [i][j].begin(),
+            //          _list_load_store_unit_with_rename_unit  [i][j].end());
+            //   std::vector<uint32_t>::iterator it=unique(_list_load_store_unit_with_rename_unit  [i][j].begin(),
+            //                                             _list_load_store_unit_with_rename_unit  [i][j].end());
+            //   _list_load_store_unit_with_rename_unit  [i][j].erase(it,_list_load_store_unit_with_rename_unit  [i][j].end());
+            // }
+
+            _list_functionnal_unit_with_rename_unit  [i][j] = sort_and_unique (_list_functionnal_unit_with_rename_unit  [i][j]);
+            
+            // {
+            //   sort  (_list_functionnal_unit_with_rename_unit  [i][j].begin(),
+            //          _list_functionnal_unit_with_rename_unit  [i][j].end());
+            //   std::vector<uint32_t>::iterator it=unique(_list_functionnal_unit_with_rename_unit  [i][j].begin(),
+            //                                             _list_functionnal_unit_with_rename_unit  [i][j].end());
+            //   _list_functionnal_unit_with_rename_unit  [i][j].erase(it,_list_functionnal_unit_with_rename_unit  [i][j].end());
+            // }
 
 //             uint32_t num_rename_bloc = _link_rename_bloc_with_rename_unit[i][j];
@@ -1175,15 +1275,8 @@
       }
     
-    log_printf(TRACE,Core,FUNCTION,_("  * network_table_dispatch [nb_ooo_engine][nb_inst_issue_slot][nb_execute_loop][nb_read_unit]"));
-    for (uint32_t i=0; i<_nb_ooo_engine; ++i)
-      for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j)
-        for (uint32_t k=0; k<_nb_execute_loop; ++k)
-          for (uint32_t l=0; l<_nb_read_unit[k]; ++l)
-            if (_network_table_dispatch [i][j][k][l] == true)
-              log_printf(TRACE,Core,FUNCTION,_("   Issue Slot [%d][%d] is connected with Read_unit [%d][%d]"),i,j,k,l);
-
-    ALLOC3(_network_table_issue_type,bool,_nb_execute_loop,_nb_read_unit[it1],_nb_type);
-
-    log_printf(TRACE,Core,FUNCTION,_("  * network_table_issue_type"));
+    ALLOC3(_network_table_issue_type  ,bool,_nb_execute_loop,_nb_read_unit[it1],_nb_type);
+    ALLOC3(_network_table_issue_thread,bool,_nb_execute_loop,_nb_read_unit[it1],_nb_thread);
+
+    log_printf(TRACE,Core,FUNCTION,_("  * network_table_issue_type and network_table_issue_thread"));
     for (uint32_t i=0; i<_nb_execute_loop; ++i)
       for (uint32_t j=0; j<_nb_read_unit[i]; ++j)
@@ -1191,5 +1284,7 @@
           // init
           for (uint32_t t=0; t<_nb_type; ++t)
-            _network_table_issue_type [i][j][t] = false;
+            _network_table_issue_type   [i][j][t] = false;
+          for (uint32_t t=0; t<_nb_thread; ++t)
+            _network_table_issue_thread [i][j][t] = false;
 
           // get number of read bloc
@@ -1199,26 +1294,45 @@
           for (uint32_t k=0; k<_nb_functionnal_unit; ++k)
             if (_link_read_bloc_and_functionnal_unit [num_read_bloc][k])
-              // Scan timing table, test if have an instruction
-              for (uint32_t t=0; t<_nb_type; ++t)
-                for (uint32_t o=0; o<_nb_operation; ++o)
-                  if (_timing[k][t][o]._latence > 0)
+              {
+                // Scan timing table, test if have an instruction
+                for (uint32_t t=0; t<_nb_type; ++t)
+                  for (uint32_t o=0; o<_nb_operation; ++o)
+                    if (_timing[k][t][o]._latence > 0)
+                      {
+                        log_printf(TRACE,Core,FUNCTION,_("  * network_table_issue_type   [%d][%d][%d] -> true"),i,j,t);
+                        
+                        _network_table_issue_type [i][j][t] = true;
+                        break; // operation
+                      }
+
+                for (uint32_t t=0; t<_nb_thread; ++t)
+                  if (_link_thread_and_functionnal_unit [t][k])
                     {
-                      log_printf(TRACE,Core,FUNCTION,_("   [%d][%d][%d] -> true"),i,j,t);
+                      log_printf(TRACE,Core,FUNCTION,_("  * network_table_issue_thread [%d][%d][%d] -> true"),i,j,t);
                       
-                      _network_table_issue_type [i][j][t] = true;
-                      break; // operation
+                      _network_table_issue_thread [i][j][t] = true;
                     }
+              }
           
           // Test load store unit connected with this read bloc
           for (uint32_t k=0; k<_nb_load_store_unit; ++k)
             // Test load store unit connected with this read bloc
-            if (_link_read_bloc_and_load_store_unit [num_read_bloc][k])
+            if (_link_read_bloc_with_load_store_unit [k] == num_read_bloc)
               {
-                uint32_t t = TYPE_MEMORY;
-                
-                log_printf(TRACE,Core,FUNCTION,_("   [%d][%d][%d] -> true"),i,j,t);
-                
-                _network_table_issue_type [i][j][t] = true;
-                break; // load_store_unit
+                {
+                  uint32_t t = TYPE_MEMORY;
+                  
+                  log_printf(TRACE,Core,FUNCTION,_("  * network_table_issue_type   [%d][%d][%d] -> true"),i,j,t);
+                  
+                  _network_table_issue_type [i][j][t] = true;
+                }
+
+                for (uint32_t t=0; t<_nb_thread; ++t)
+                  if (_link_load_store_unit_with_thread[t] == k)
+                    {
+                      log_printf(TRACE,Core,FUNCTION,_("  * network_table_issue_thread [%d][%d][%d] -> true"),i,j,t);
+                      
+                      _network_table_issue_thread [i][j][t] = true;
+                    }
               }
         }
@@ -1346,5 +1460,5 @@
     ALLOC1(_list_ooo_engine_with_execute_loop                      ,std::vector<uint32_t>,_nb_execute_loop);
     ALLOC1(_list_front_end_with_execute_loop                       ,std::vector<uint32_t>,_nb_execute_loop);
-    
+
     for (uint32_t i=0; i<_nb_ooo_engine; ++i)
       {
@@ -1366,18 +1480,23 @@
     for (uint32_t i=0; i<_nb_execute_loop; ++i)
       {
-        {
-          sort  (_list_ooo_engine_with_execute_loop[i].begin(),
-                 _list_ooo_engine_with_execute_loop[i].end());
-          std::vector<uint32_t>::iterator it=unique(_list_ooo_engine_with_execute_loop[i].begin(),
-                                                    _list_ooo_engine_with_execute_loop[i].end());
-          _list_ooo_engine_with_execute_loop[i].erase(it,_list_ooo_engine_with_execute_loop[i].end());
-        }
-        {
-          sort  (_list_front_end_with_execute_loop[i].begin(),
-                 _list_front_end_with_execute_loop[i].end());
-          std::vector<uint32_t>::iterator it=unique(_list_front_end_with_execute_loop[i].begin(),
-                                                    _list_front_end_with_execute_loop[i].end());
-          _list_front_end_with_execute_loop[i].erase(it,_list_front_end_with_execute_loop[i].end());
-        }
+        _list_ooo_engine_with_execute_loop[i] = sort_and_unique (_list_ooo_engine_with_execute_loop[i]);
+
+        // {
+        //   sort  (_list_ooo_engine_with_execute_loop[i].begin(),
+        //          _list_ooo_engine_with_execute_loop[i].end());
+        //   std::vector<uint32_t>::iterator it=unique(_list_ooo_engine_with_execute_loop[i].begin(),
+        //                                             _list_ooo_engine_with_execute_loop[i].end());
+        //   _list_ooo_engine_with_execute_loop[i].erase(it,_list_ooo_engine_with_execute_loop[i].end());
+        // }
+
+        _list_front_end_with_execute_loop[i] = sort_and_unique (_list_front_end_with_execute_loop[i]);
+
+        // {
+        //   sort  (_list_front_end_with_execute_loop[i].begin(),
+        //          _list_front_end_with_execute_loop[i].end());
+        //   std::vector<uint32_t>::iterator it=unique(_list_front_end_with_execute_loop[i].begin(),
+        //                                             _list_front_end_with_execute_loop[i].end());
+        //   _list_front_end_with_execute_loop[i].erase(it,_list_front_end_with_execute_loop[i].end());
+        // }
       }
 
@@ -1402,5 +1521,5 @@
     ALLOC1(_execute_loop_nb_packet                                 ,uint32_t,_nb_execute_loop);
     ALLOC1(_execute_loop_nb_thread                                 ,uint32_t,_nb_execute_loop);
-    
+
     for (uint32_t i=0; i<_nb_execute_loop; ++i)
       {
@@ -1453,4 +1572,5 @@
         }  
     
+    ALLOC2(_execute_loop_nb_inst_read                              ,uint32_t,_nb_execute_loop,_nb_read_unit[it1]);
     ALLOC2(_execute_loop_size_read_queue                           ,uint32_t,_nb_execute_loop,_nb_read_unit[it1]);
     ALLOC2(_execute_loop_size_reservation_station                  ,uint32_t,_nb_execute_loop,_nb_read_unit[it1]);
@@ -1468,4 +1588,5 @@
             log_printf(TRACE,Core,FUNCTION,_("      * num_read_bloc : %d"),num_read_bloc);
             
+            _execute_loop_nb_inst_read             [i][j] = _nb_inst_read             [num_read_bloc];
             _execute_loop_size_read_queue          [i][j] = _size_read_queue          [num_read_bloc];
             _execute_loop_size_reservation_station [i][j] = _size_reservation_station [num_read_bloc];
@@ -1538,13 +1659,18 @@
       }
     
-    ALLOC2(_execute_loop_size_store_queue                          ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
-    ALLOC2(_execute_loop_size_load_queue                           ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
-    ALLOC2(_execute_loop_size_speculative_access_queue             ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
-    ALLOC2(_execute_loop_nb_port_check                             ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+    ALLOC2(_execute_loop_size_store_queue                          ,uint32_t    ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+    ALLOC2(_execute_loop_size_load_queue                           ,uint32_t    ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+    ALLOC2(_execute_loop_size_speculative_access_queue             ,uint32_t    ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+    ALLOC2(_execute_loop_nb_store_queue_bank                       ,uint32_t    ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+    ALLOC2(_execute_loop_nb_load_queue_bank                        ,uint32_t    ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+    ALLOC2(_execute_loop_nb_port_check                             ,uint32_t    ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
     ALLOC2(_execute_loop_speculative_load                          ,multi_execute_loop::execute_loop::Tspeculative_load_t
-                                                                            ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
-    ALLOC2(_execute_loop_nb_bypass_memory                          ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
-    ALLOC2(_execute_loop_nb_cache_port                             ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
-    ALLOC2(_execute_loop_nb_inst_memory                            ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+                                                                                ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+    ALLOC2(_execute_loop_speculative_commit_predictor_scheme       ,Tpredictor_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+    ALLOC3(_execute_loop_lsu_pht_size_counter                      ,uint32_t    ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1],1);
+    ALLOC3(_execute_loop_lsu_pht_nb_counter                        ,uint32_t    ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1],1);
+    ALLOC2(_execute_loop_nb_bypass_memory                          ,uint32_t    ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+    ALLOC2(_execute_loop_nb_cache_port                             ,uint32_t    ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+    ALLOC2(_execute_loop_nb_inst_memory                            ,uint32_t    ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
     
     for (uint32_t i=0; i<_nb_execute_loop; ++i)
@@ -1556,14 +1682,23 @@
           log_printf(TRACE,Core,FUNCTION,_("    * nb_bypass_memory : %d"),_nb_bypass_memory[num_load_store_unit]);
 
-          _execute_loop_size_store_queue              [i][j] = _size_store_queue              [num_load_store_unit];
-          _execute_loop_size_load_queue               [i][j] = _size_load_queue               [num_load_store_unit];
-          _execute_loop_size_speculative_access_queue [i][j] = _size_speculative_access_queue [num_load_store_unit];
-          _execute_loop_nb_port_check                 [i][j] = _nb_port_check                 [num_load_store_unit];
-          _execute_loop_speculative_load              [i][j] = _speculative_load              [num_load_store_unit];
-          _execute_loop_nb_bypass_memory              [i][j] = _nb_bypass_memory              [num_load_store_unit];
-          _execute_loop_nb_cache_port                 [i][j] = _nb_cache_port                 [num_load_store_unit];
-          _execute_loop_nb_inst_memory                [i][j] = _nb_inst_memory                [num_load_store_unit];
+          _execute_loop_size_store_queue                    [i][j] = _size_store_queue                    [num_load_store_unit];
+          _execute_loop_size_load_queue                     [i][j] = _size_load_queue                     [num_load_store_unit];
+          _execute_loop_size_speculative_access_queue       [i][j] = _size_speculative_access_queue       [num_load_store_unit];
+          _execute_loop_nb_store_queue_bank                 [i][j] = _nb_store_queue_bank                 [num_load_store_unit];
+          _execute_loop_nb_load_queue_bank                  [i][j] = _nb_load_queue_bank                  [num_load_store_unit];
+          _execute_loop_nb_port_check                       [i][j] = _nb_port_check                       [num_load_store_unit];
+          _execute_loop_speculative_load                    [i][j] = _speculative_load                    [num_load_store_unit];
+          _execute_loop_speculative_commit_predictor_scheme [i][j] = _speculative_commit_predictor_scheme [num_load_store_unit];
+          for (uint32_t k=0; k<1; ++k)
+            {
+          _execute_loop_lsu_pht_size_counter             [i][j][k] = _lsu_pht_size_counter                [num_load_store_unit][k];
+          _execute_loop_lsu_pht_nb_counter               [i][j][k] = _lsu_pht_nb_counter                  [num_load_store_unit][k];
+            }
+          _execute_loop_nb_bypass_memory                    [i][j] = _nb_bypass_memory                    [num_load_store_unit];
+          _execute_loop_nb_cache_port                       [i][j] = _nb_cache_port                       [num_load_store_unit];
+          _execute_loop_nb_inst_memory                      [i][j] = _nb_inst_memory                      [num_load_store_unit];
         }
 
+    ALLOC2(_execute_loop_nb_inst_write                             ,uint32_t,_nb_execute_loop,_nb_write_unit[it1]);
     ALLOC2(_execute_loop_size_write_queue                          ,uint32_t,_nb_execute_loop,_nb_write_unit[it1]);
     ALLOC2(_execute_loop_size_execute_queue                        ,uint32_t,_nb_execute_loop,_nb_write_unit[it1]);
@@ -1576,4 +1711,5 @@
           uint32_t num_write_bloc = _link_write_bloc_with_write_unit [i][j];
     
+          _execute_loop_nb_inst_write      [i][j] = _nb_inst_write      [num_write_bloc];
           _execute_loop_size_write_queue   [i][j] = _size_write_queue   [num_write_bloc];
           _execute_loop_size_execute_queue [i][j] = _size_execute_queue [num_write_bloc];
@@ -1660,5 +1796,5 @@
               
               if (is_lsu)
-                link = _link_read_bloc_and_load_store_unit  [num_read_bloc][num_load_store_unit];
+                link = (_link_read_bloc_with_load_store_unit [num_load_store_unit] == num_read_bloc);
               else
                 link = _link_read_bloc_and_functionnal_unit [num_read_bloc][num_functionnal_unit];
@@ -1689,5 +1825,5 @@
               
               if (is_lsu)
-                link = _link_write_bloc_and_load_store_unit  [num_write_bloc][num_load_store_unit];
+                link = (_link_write_bloc_with_load_store_unit [num_load_store_unit] == num_write_bloc);
               else
                 link = _link_write_bloc_and_functionnal_unit [num_write_bloc][num_functionnal_unit];
@@ -1745,5 +1881,5 @@
               {
                 uint32_t num_write_bloc = _link_write_bloc_with_write_unit[i][k];
-                bool     have_link = (is_lsu)?(_link_write_bloc_and_load_store_unit [num_write_bloc][num_load_store_unit]):(_link_write_bloc_and_functionnal_unit [num_write_bloc][num_functionnal_unit]);
+                bool     have_link = (is_lsu)?(_link_write_bloc_with_load_store_unit [num_load_store_unit]==num_write_bloc):(_link_write_bloc_and_functionnal_unit [num_write_bloc][num_functionnal_unit]);
                   
                 if (have_link)
@@ -1997,5 +2133,5 @@
        _ooo_engine_nb_inst_insert                    [i],
        _ooo_engine_nb_inst_retire                    [i],
-//        _nb_inst_issue                                [i],
+//     _nb_inst_issue                                [i],
        _ooo_engine_nb_inst_execute                   [i],
        _nb_inst_reexecute                            [i],
@@ -2011,4 +2147,5 @@
        _size_re_order_buffer                         [i],
        _nb_re_order_buffer_bank                      [i],
+       _retire_ooo_scheme                            [i],
        _commit_priority                              [i],
        _commit_load_balancing                        [i],
@@ -2021,6 +2158,4 @@
 //        _ooo_engine_table_issue_type                  [i],
        _size_reexecute_queue                         [i],
-       _reexecute_priority                           [i],
-       _reexecute_load_balancing                     [i],
        _ooo_engine_rename_select_priority            [i],
        _ooo_engine_rename_select_load_balancing      [i],
@@ -2060,4 +2195,5 @@
          _size_special_data                                          ,
 
+         _execute_loop_nb_inst_read                               [i],
          _execute_loop_size_read_queue                            [i],
          _execute_loop_size_reservation_station                   [i],
@@ -2071,10 +2207,16 @@
          _execute_loop_size_load_queue                            [i],
          _execute_loop_size_speculative_access_queue              [i],
+         _execute_loop_nb_store_queue_bank                        [i],
+         _execute_loop_nb_load_queue_bank                         [i],
          _execute_loop_nb_port_check                              [i],
          _execute_loop_speculative_load                           [i],
+         _execute_loop_speculative_commit_predictor_scheme        [i],
+         _execute_loop_lsu_pht_size_counter                       [i],
+         _execute_loop_lsu_pht_nb_counter                         [i],
          _execute_loop_nb_bypass_memory                           [i],
          _execute_loop_nb_cache_port                              [i],
          _execute_loop_nb_inst_memory                             [i],
 
+         _execute_loop_nb_inst_write                              [i],
          _execute_loop_size_write_queue                           [i],
          _execute_loop_size_execute_queue                         [i],
@@ -2146,37 +2288,39 @@
     _param_glue          = new core::core_glue::Parameters 
       (
-       _nb_front_end                         ,
-       _nb_context                           ,//[nb_front_end]
-       _nb_ooo_engine                        ,
-       _nb_execute_loop                      ,
-       _ooo_engine_nb_front_end              ,//[nb_ooo_engine]
-       _ooo_engine_nb_execute_loop           ,//[nb_ooo_engine]
-       _execute_loop_nb_ooo_engine           ,//[nb_execute_loop]
-       _front_end_sum_inst_decod             ,//[nb_front_end] -> [sum_inst_decod]
-       _front_end_nb_inst_branch_complete    ,//[nb_front_end]
-       _nb_inst_branch_complete              ,//[nb_ooo_engine]
-//     _ooo_engine_nb_inst_insert_rob        ,//[nb_ooo_engine]
-       _nb_inst_reexecute                    ,//[nb_ooo_engine]
-       _nb_inst_issue_queue                  ,//[nb_ooo_engine]
-       _nb_inst_issue_slot                   ,//[nb_ooo_engine]
-       _ooo_engine_nb_inst_execute           ,//[nb_ooo_engine][ooo_engine_nb_execute_loop]
-       _issue_queue_in_order                 ,//[nb_ooo_engine]
-       _nb_read_unit                         ,//[nb_execute_loop]
-       _nb_write_unit                        ,//[nb_execute_loop]
-       _size_depth                           ,
-       _size_rob_ptr                         ,
-       _size_load_queue_ptr                  ,
-       _size_store_queue_ptr                 ,
-       _size_general_data                    ,
-       _size_special_data                    ,
-       _size_general_register                ,
-       _size_special_register                ,
-       _dispatch_priority                    ,
-       _dispatch_load_balancing              ,
-       _network_table_dispatch               ,//[nb_ooo_engine][nb_inst_issue_slot][nb_execute_loop][nb_read_unit]
-       _network_table_issue_type             ,//                                   [nb_execute_loop][nb_read_unit][nb_type]
-       _translate_ooo_engine_num_front_end   ,//[nb_ooo_engine][ooo_engine_nb_front_end]
-       _translate_ooo_engine_num_execute_loop,//[nb_ooo_engine][ooo_engine_nb_execute_loop]
-       _translate_execute_loop_num_ooo_engine //[nb_execute_loop][execute_loop_nb_ooo_engine]
+       _nb_front_end                                  ,
+       _nb_context                                    ,//[nb_front_end]
+       _nb_ooo_engine                                 ,
+       _nb_execute_loop                               ,
+       _ooo_engine_nb_front_end                       ,//[nb_ooo_engine]
+       _ooo_engine_nb_execute_loop                    ,//[nb_ooo_engine]
+       _execute_loop_nb_ooo_engine                    ,//[nb_execute_loop]
+       _front_end_sum_inst_decod                      ,//[nb_front_end] -> [sum_inst_decod]
+       _front_end_nb_inst_branch_complete             ,//[nb_front_end]
+       _nb_inst_branch_complete                       ,//[nb_ooo_engine]
+//     _ooo_engine_nb_inst_insert_rob                 ,//[nb_ooo_engine]
+       _nb_inst_reexecute                             ,//[nb_ooo_engine]
+       _nb_inst_issue_queue                           ,//[nb_ooo_engine]
+//     _nb_inst_issue_slot                            ,//[nb_ooo_engine]
+       _ooo_engine_nb_inst_execute                    ,//[nb_ooo_engine][ooo_engine_nb_execute_loop]
+       _issue_queue_in_order                          ,//[nb_ooo_engine]
+       _nb_read_unit                                  ,//[nb_execute_loop]
+       _nb_write_unit                                 ,//[nb_execute_loop]
+       _size_depth                                    ,
+       _size_rob_ptr                                  ,
+       _size_load_queue_ptr                           ,
+       _size_store_queue_ptr                          ,
+       _size_general_data                             ,
+       _size_special_data                             ,
+       _size_general_register                         ,
+       _size_special_register                         ,
+       _dispatch_priority                             ,
+       _dispatch_load_balancing                       ,
+//     _network_table_dispatch                        ,//[nb_ooo_engine][nb_inst_issue_slot][nb_execute_loop][nb_read_unit]
+       _network_table_issue_type                      ,//                                   [nb_execute_loop][nb_read_unit][nb_type]
+       _network_table_issue_thread                    ,//                                   [nb_execute_loop][nb_read_unit][nb_thread]
+       _translate_ooo_engine_num_front_end            ,//[nb_ooo_engine][ooo_engine_nb_front_end]
+       _translate_ooo_engine_num_execute_loop         ,//[nb_ooo_engine][ooo_engine_nb_execute_loop]
+       _translate_execute_loop_num_ooo_engine         ,//[nb_execute_loop][execute_loop_nb_ooo_engine]
+       _ooo_engine_translate_num_context_to_num_thread //[nb_ooo_engine][ooo_engine_nb_front_end][nb_context]
        );
     
@@ -2238,9 +2382,15 @@
     DELETE2(_execute_loop_size_execute_queue                        ,_nb_execute_loop,_nb_write_unit[it1]);
     DELETE2(_execute_loop_size_write_queue                          ,_nb_execute_loop,_nb_write_unit[it1]);
+    DELETE2(_execute_loop_nb_inst_write                             ,_nb_execute_loop,_nb_write_unit[it1]);
     DELETE2(_execute_loop_nb_inst_memory                            ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
     DELETE2(_execute_loop_nb_cache_port                             ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
     DELETE2(_execute_loop_nb_bypass_memory                          ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+    DELETE3(_execute_loop_lsu_pht_nb_counter                        ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1],1);
+    DELETE3(_execute_loop_lsu_pht_size_counter                      ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1],1);
+    DELETE2(_execute_loop_speculative_commit_predictor_scheme       ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
     DELETE2(_execute_loop_speculative_load                          ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
     DELETE2(_execute_loop_nb_port_check                             ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+    DELETE2(_execute_loop_nb_load_queue_bank                        ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
+    DELETE2(_execute_loop_nb_store_queue_bank                       ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
     DELETE2(_execute_loop_size_speculative_access_queue             ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
     DELETE2(_execute_loop_size_load_queue                           ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]);
@@ -2253,4 +2403,5 @@
     DELETE2(_execute_loop_size_reservation_station                  ,_nb_execute_loop,_nb_read_unit[it1]);
     DELETE2(_execute_loop_size_read_queue                           ,_nb_execute_loop,_nb_read_unit[it1]);
+    DELETE2(_execute_loop_nb_inst_read                              ,_nb_execute_loop,_nb_read_unit[it1]);
     DELETE2(_translate_execute_loop_num_ooo_engine                  ,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]);
     DELETE1(_execute_loop_nb_thread                                 ,_nb_execute_loop);
@@ -2273,6 +2424,7 @@
 //  DELETE3(_ooo_engine_table_issue_type                            ,_nb_ooo_engine,_nb_inst_issue_slot[it1],_nb_type);
 //  DELETE3(_ooo_engine_table_routing                               ,_nb_ooo_engine,_nb_rename_unit[it1],_nb_inst_issue_slot[it1]);
+    DELETE3(_network_table_issue_thread                                                                     ,_nb_execute_loop,_nb_read_unit[it1],_nb_thread);
     DELETE3(_network_table_issue_type                                                                       ,_nb_execute_loop,_nb_read_unit[it1],_nb_type);
-    DELETE4(_network_table_dispatch                                 ,_nb_ooo_engine,_nb_inst_issue_slot[it1],_nb_execute_loop,_nb_read_unit[it3]);
+//  DELETE4(_network_table_dispatch                                 ,_nb_ooo_engine,_nb_inst_issue_slot[it1],_nb_execute_loop,_nb_read_unit[it3]);
 //  DELETE2(_ooo_engine_size_read_counter                           ,_nb_ooo_engine,_nb_rename_unit[it1]);
     DELETE2(_ooo_engine_nb_rename_unit_bank                         ,_nb_ooo_engine,_nb_rename_unit[it1]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_msg_error.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_msg_error.cpp	(revision 138)
@@ -24,6 +24,5 @@
     Parameters_test test ("Core");
 
-    // TESTER SI LES VALEURS NE DEPASSE PAS DE L'INTERVALLE AUTORISE
-
+    // Test if value is valid
     {
       // initialisation
@@ -191,4 +190,6 @@
           uint32_t num_execute_loop = _link_execute_unit_with_load_store_unit [i].first;
           uint32_t num_execute_unit = _link_execute_unit_with_load_store_unit [i].second;
+
+          log_printf(TRACE,Core,FUNCTION,"  * _link_execute_unit_with_load_store_unit  [%d] = %d.%d",i,num_execute_loop,num_execute_unit);
 
           nb_link_execute_unit [num_execute_loop][num_execute_unit] ++;
@@ -224,69 +225,36 @@
     
     {
-      // initialisation
-      uint32_t nb_link_slot      [_nb_ooo_engine][max<uint32_t>(_nb_inst_issue_slot,_nb_ooo_engine)];
-      uint32_t nb_link_read_bloc [_nb_read_bloc];
-  
-      // initialisation
-      for (uint32_t i=0; i<_nb_ooo_engine; ++i)
-        for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j)
-          nb_link_slot [i][j] = 0;
+      bool     read_bloc_link_with_load_store_unit  [_nb_read_bloc];
+      bool     read_bloc_link_with_functionnal_unit [_nb_read_bloc];
+      uint32_t nb_link_functionnal_unit [_nb_functionnal_unit];
+      
       for (uint32_t i=0; i<_nb_read_bloc; ++i)
-        nb_link_read_bloc [i] = 0;
-
-      // set link
-      for (uint32_t i=0; i<_nb_ooo_engine; ++i)
-        for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j)
-          for (uint32_t k=0; k<_nb_read_bloc; ++k)
-            if (_table_dispatch [i][j][k])
-              {
-                nb_link_slot      [i][j] ++;
-                nb_link_read_bloc [k] ++;
-              }
-      
-      // test
-      for (uint32_t i=0; i<_nb_ooo_engine; ++i)
-        for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j)
-          if (nb_link_slot [i][j] == 0)
-            test.error(toString(_("In Out Of Order Engine [%d], the slot issue [%d] is not link with a read_bloc.\n"),i,j));
+        {
+          read_bloc_link_with_load_store_unit  [i] = false;
+          read_bloc_link_with_functionnal_unit [i] = false;
+        }
+      for (uint32_t i=0; i<_nb_functionnal_unit; ++i)
+        nb_link_functionnal_unit [i] = 0;
+      
+      for (uint32_t i=0; i<_nb_load_store_unit; ++i)
+        read_bloc_link_with_load_store_unit [_link_read_bloc_with_load_store_unit[i]] = true;
+      
       for (uint32_t i=0; i<_nb_read_bloc; ++i)
-        if (nb_link_read_bloc [i] == 0)
-          test.error(toString(_("Read_bloc [%d] is not link with a issue's slot.\n"),i));
-    }
-
-    {
-      uint32_t nb_link_read_bloc        [_nb_read_bloc];
-      uint32_t nb_link_load_store_unit  [_nb_load_store_unit];
-      uint32_t nb_link_functionnal_unit [_nb_functionnal_unit];
+        for (uint32_t j=0; j<_nb_functionnal_unit; ++j)
+          if (_link_read_bloc_and_functionnal_unit [i][j])
+            {
+              nb_link_functionnal_unit [j] ++;
+              read_bloc_link_with_functionnal_unit [i] = true;
+            }
 
       for (uint32_t i=0; i<_nb_read_bloc; ++i)
-        nb_link_read_bloc [i] = 0;
-      for (uint32_t i=0; i<_nb_load_store_unit; ++i)
-        nb_link_load_store_unit [i] = 0;
-      for (uint32_t i=0; i<_nb_functionnal_unit; ++i)
-        nb_link_functionnal_unit [i] = 0;
-
-      for (uint32_t i=0; i<_nb_read_bloc; ++i)
-        {
-          for (uint32_t j=0; j<_nb_load_store_unit; ++j)
-            if (_link_read_bloc_and_load_store_unit [i][j])
-              {
-                nb_link_read_bloc        [i] ++;
-                nb_link_load_store_unit  [j] ++;
-              }
-          for (uint32_t j=0; j<_nb_functionnal_unit; ++j)
-            if (_link_read_bloc_and_functionnal_unit [i][j])
-              {
-                nb_link_read_bloc        [i] ++;
-                nb_link_functionnal_unit [j] ++;
-              }
-        }
-
-      for (uint32_t i=0; i<_nb_read_bloc; ++i)
-        if (nb_link_read_bloc [i] == 0)
-          test.error(toString(_("Read_bloc [%d] is not link with an execute_unit.\n"),i));
-      for (uint32_t i=0; i<_nb_load_store_unit; ++i)
-        if (nb_link_load_store_unit [i] == 0)
-          test.error(toString(_("load_store_unit [%d] is not link with a read_bloc.\n"),i));
+        {
+          if (not read_bloc_link_with_load_store_unit  [i] and
+              not read_bloc_link_with_functionnal_unit [i])
+            test.error(toString(_("Read_bloc [%d] is not link with an execute_unit.\n"),i));
+          if (    read_bloc_link_with_load_store_unit  [i] and
+                  read_bloc_link_with_functionnal_unit [i])
+            test.error(toString(_("Read_bloc [%d] is linked with an load store unit and functionnal unit.\n"),i));
+        }
       for (uint32_t i=0; i<_nb_functionnal_unit; ++i)
         if (nb_link_functionnal_unit [i] == 0)
@@ -296,36 +264,25 @@
     {
       uint32_t nb_link_write_bloc       [_nb_write_bloc];
-      uint32_t nb_link_load_store_unit  [_nb_load_store_unit];
       uint32_t nb_link_functionnal_unit [_nb_functionnal_unit];
 
       for (uint32_t i=0; i<_nb_write_bloc; ++i)
         nb_link_write_bloc [i] = 0;
-      for (uint32_t i=0; i<_nb_load_store_unit; ++i)
-        nb_link_load_store_unit [i] = 0;
       for (uint32_t i=0; i<_nb_functionnal_unit; ++i)
         nb_link_functionnal_unit [i] = 0;
 
+      for (uint32_t i=0; i<_nb_load_store_unit; ++i)
+        nb_link_write_bloc [_link_write_bloc_with_load_store_unit[i]] = true;
+
       for (uint32_t i=0; i<_nb_write_bloc; ++i)
-        {
-          for (uint32_t j=0; j<_nb_load_store_unit; ++j)
-            if (_link_write_bloc_and_load_store_unit [i][j])
-              {
-                nb_link_write_bloc       [i] ++;
-                nb_link_load_store_unit  [j] ++;
-              }
-          for (uint32_t j=0; j<_nb_functionnal_unit; ++j)
-            if (_link_write_bloc_and_functionnal_unit [i][j])
-              {
-                nb_link_write_bloc       [i] ++;
-                nb_link_functionnal_unit [j] ++;
-              }
-        }
+        for (uint32_t j=0; j<_nb_functionnal_unit; ++j)
+          if (_link_write_bloc_and_functionnal_unit [i][j])
+            {
+              nb_link_write_bloc       [i] ++;
+              nb_link_functionnal_unit [j] ++;
+            }
 
       for (uint32_t i=0; i<_nb_write_bloc; ++i)
         if (nb_link_write_bloc [i] == 0)
           test.error(toString(_("Write_bloc [%d] is not link with an execute_unit.\n"),i));
-      for (uint32_t i=0; i<_nb_load_store_unit; ++i)
-        if (nb_link_load_store_unit [i] == 0)
-          test.error(toString(_("load_store_unit [%d] is not link with a write_bloc.\n"),i));
       for (uint32_t i=0; i<_nb_functionnal_unit; ++i)
         if (nb_link_functionnal_unit [i] == 0)
@@ -334,7 +291,9 @@
 
     {
-      uint32_t nb_link_thread           [_nb_thread];
-      uint32_t nb_link_load_store_unit  [_nb_load_store_unit];
-      uint32_t nb_link_functionnal_unit [_nb_functionnal_unit];
+      uint32_t nb_link_thread                      [_nb_thread];
+      uint32_t nb_link_load_store_unit             [_nb_load_store_unit];
+      uint32_t nb_link_functionnal_unit            [_nb_functionnal_unit];
+      bool     link_front_end_with_execute_loop    [_nb_front_end][_nb_execute_loop];
+      uint32_t nb_link_front_end_with_execute_loop [_nb_front_end];
 
       for (uint32_t i=0; i<_nb_thread; ++i)
@@ -344,12 +303,25 @@
       for (uint32_t i=0; i<_nb_functionnal_unit; ++i)
         nb_link_functionnal_unit [i] = 0;
-      
-      for (uint32_t i=0; i<_nb_thread; ++i)
-        {
+      for (uint32_t i=0; i<_nb_front_end; ++i)
+        {
+          nb_link_front_end_with_execute_loop [i] = 0;
+          for (uint32_t j=0; j<_nb_execute_loop; ++j)
+            link_front_end_with_execute_loop [i][j] = false;
+        }
+
+      for (uint32_t i=0; i<_nb_thread; ++i)
+        {
+          uint32_t num_front_end = _link_context_with_thread [i].first;
+
           {
             uint32_t num_load_store_unit = _link_load_store_unit_with_thread [i];
+            uint32_t num_execute_loop    = _link_execute_unit_with_load_store_unit [i].first;
             
             nb_link_thread           [i] ++;
             nb_link_load_store_unit  [num_load_store_unit] ++;
+
+            if (not link_front_end_with_execute_loop [num_front_end][num_execute_loop])
+              nb_link_front_end_with_execute_loop [num_front_end] ++;
+            link_front_end_with_execute_loop [num_front_end][num_execute_loop] = true;
           }
 
@@ -357,6 +329,12 @@
             if (_link_thread_and_functionnal_unit [i][j])
               {
+                uint32_t num_execute_loop = _link_execute_unit_with_functionnal_unit [i].first;
+
                 nb_link_thread           [i] ++;
                 nb_link_functionnal_unit [j] ++;
+                
+                if (not link_front_end_with_execute_loop [num_front_end][num_execute_loop])
+                  nb_link_front_end_with_execute_loop [num_front_end] ++;
+                link_front_end_with_execute_loop [num_front_end][num_execute_loop] = true;
               }
         }
@@ -371,4 +349,7 @@
         if (nb_link_functionnal_unit [i] == 0)
           test.error(toString(_("Functionnal_unit [%d] is not link with a thread.\n"),i));
+      for (uint32_t i=0; i<_nb_front_end; ++i)
+        if (nb_link_front_end_with_execute_loop [i] != 1)
+          test.error(toString(_("Front end [%d] is link with many execute_loop.\n"),i));
     }
     
@@ -395,5 +376,5 @@
       for (uint32_t i=0; i<_nb_load_store_unit; ++i)
         for (uint32_t j=0; j<_nb_cache_port[i]; ++j)
-        nb_link_dcache_port [_link_dcache_port_with_load_store_unit[i][j]] ++;
+          nb_link_dcache_port [_link_dcache_port_with_load_store_unit[i][j]] ++;
       
       for (uint32_t i=0; i<_nb_dcache_port; ++i)
@@ -402,24 +383,4 @@
     }
 
-
-//   public : pair_dual             * _link_context_with_thread                      ;//[nb_thread]
-//   public : pair_dual             * _link_decod_unit_with_decod_bloc               ;//[nb_decod_bloc]
-//   public : pair_dual             * _link_rename_unit_with_rename_bloc             ;//[nb_rename_bloc]
-//   public : pair_dual             * _link_read_unit_with_read_bloc                 ;//[nb_read_bloc]
-//   public : pair_dual             * _link_write_unit_with_write_bloc               ;//[nb_write_bloc]
-//   public : pair_dual             * _link_execute_unit_with_functionnal_unit       ;//[nb_functionnal_unit]
-//   public : pair_dual             * _link_execute_unit_with_load_store_unit        ;//[nb_load_store_unit]
-//   public : uint32_t              * _link_decod_bloc_with_thread                   ;//[nb_thread]
-//   public : uint32_t              * _link_rename_bloc_with_front_end               ;//[nb_front_end]
-//   public : bool                *** _table_dispatch                                ;//[nb_ooo_engine][nb_inst_issue][nb_read_bloc]
-//   public : bool                 ** _link_read_bloc_and_load_store_unit            ;//[nb_read_bloc][nb_load_store_unit]
-//   public : bool                 ** _link_read_bloc_and_functionnal_unit           ;//[nb_read_bloc][nb_functionnal_unit]
-//   public : bool                 ** _link_write_bloc_and_load_store_unit           ;//[nb_write_bloc][nb_load_store_unit]
-//   public : bool                 ** _link_write_bloc_and_functionnal_unit          ;//[nb_write_bloc][nb_functionnal_unit]
-//   public : uint32_t              * _link_load_store_unit_with_thread              ;//[nb_thread]
-//   public : bool                 ** _link_thread_and_functionnal_unit              ;//[nb_thread][nb_functionnal_unit]
-//   public : uint32_t              * _link_icache_port_with_thread                  ;//[nb_thread]
-//   public : uint32_t             ** _link_dcache_port_with_load_store_unit         ;//[nb_load_store_unit][nb_cache_port]
-
     log_end(Core,FUNCTION);
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp	(revision 138)
@@ -176,5 +176,4 @@
     str+= toString(MSG_INFORMATION)+"     * nb_rename_unit                              : "+toString<uint32_t         >(_nb_rename_unit          [i])+"\n";
     str+= toString(MSG_INFORMATION)+"     * nb_inst_issue_queue                         : "+toString<uint32_t         >(_nb_inst_issue_queue     [i])+"\n";
-    str+= toString(MSG_INFORMATION)+"     * nb_inst_issue_slot                          : "+toString<uint32_t         >(_nb_inst_issue_slot      [i])+"\n";
     str+= toString(MSG_INFORMATION)+"     * nb_inst_reexecute                           : "+toString<uint32_t         >(_nb_inst_reexecute       [i])+"\n";
     str+= toString(MSG_INFORMATION)+"     * nb_inst_commit                              : "+toString<uint32_t         >(_nb_inst_commit          [i])+"\n";
@@ -193,6 +192,4 @@
     str+= toString(MSG_INFORMATION)+"     * issue_load_balancing                        : "+toString<Tload_balancing_t>(_issue_load_balancing    [i])+"\n";
     str+= toString(MSG_INFORMATION)+"     * size_reexecute_queue                        : "+toString<uint32_t         >(_size_reexecute_queue    [i])+"\n";
-    str+= toString(MSG_INFORMATION)+"     * reexecute_priority                          : "+toString<Tpriority_t      >(_reexecute_priority      [i])+"\n";
-    str+= toString(MSG_INFORMATION)+"     * reexecute_load_balancing                    : "+toString<Tload_balancing_t>(_reexecute_load_balancing[i])+"\n";
       }
 
@@ -245,13 +242,11 @@
 
     
-    for (uint32_t i=0; i<_nb_read_bloc; ++i)
-      for (uint32_t j=0; j<_nb_load_store_unit; ++j)
-    str+= toString(MSG_INFORMATION)+"   * link_read_bloc_and_load_store_unit              ["+toString(i)+"]["+toString(j)+"] : "+toString(_link_read_bloc_and_load_store_unit  [i][j])+"\n";//[nb_read_bloc][nb_load_store_unit]
+    for (uint32_t i=0; i<_nb_load_store_unit; ++i)
+    str+= toString(MSG_INFORMATION)+"   * link_read_bloc_with_load_store_unit             ["+toString(i)+"] : "+toString(_link_read_bloc_with_load_store_unit  [i])+"\n";//[nb_load_store_unit]
     for (uint32_t i=0; i<_nb_read_bloc; ++i)
       for (uint32_t j=0; j<_nb_functionnal_unit; ++j)
     str+= toString(MSG_INFORMATION)+"   * link_read_bloc_and_functionnal_unit             ["+toString(i)+"]["+toString(j)+"] : "+toString(_link_read_bloc_and_functionnal_unit [i][j])+"\n";//[nb_read_bloc][nb_functionnal_unit]
-    for (uint32_t i=0; i<_nb_write_bloc; ++i)
-      for (uint32_t j=0; j<_nb_load_store_unit; ++j)
-    str+= toString(MSG_INFORMATION)+"   * link_write_bloc_and_load_store_unit             ["+toString(i)+"]["+toString(j)+"] : "+toString(_link_write_bloc_and_load_store_unit [i][j])+"\n";//[nb_write_bloc][nb_load_store_unit]
+    for (uint32_t i=0; i<_nb_load_store_unit; ++i)
+    str+= toString(MSG_INFORMATION)+"   * link_write_bloc_with_load_store_unit            ["+toString(i)+"] : "+toString(_link_write_bloc_with_load_store_unit [i])+"\n";//[nb_load_store_unit]
     for (uint32_t i=0; i<_nb_write_bloc; ++i)
       for (uint32_t j=0; j<_nb_functionnal_unit; ++j)
@@ -262,10 +257,4 @@
 
     str+= toString(MSG_INFORMATION)+" -----[ Dispatch ]---------------------------------\n";
-
-    for (uint32_t i=0; i<_nb_ooo_engine; ++i)
-      for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j)
-        for (uint32_t k=0; k<_nb_read_bloc; ++k)
-    str+= toString(MSG_INFORMATION)+"   * table_dispatch                                  ["+toString(i)+"]["+toString(j)+"]["+toString(k)+"] : "+toString(_table_dispatch                      [i][j][k])+"\n";//[nb_ooo_engine][nb_inst_issue][nb_read_bloc]
-
     str+= toString(MSG_INFORMATION)+"   * dispatch_priority                             : "+toString<Tpriority_t      >(_dispatch_priority      )+"\n";
     str+= toString(MSG_INFORMATION)+"   * dispatch_load_balancing                       : "+toString<Tload_balancing_t>(_dispatch_load_balancing);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h	(revision 138)
@@ -50,6 +50,9 @@
   public    : Stat                           * _stat;
     
-  private   : counter_t                      * _stat_nb_read;
-  private   : counter_t                      * _stat_nb_write;
+  // private   : counter_t                      * _stat_nb_read;
+  // private   : counter_t                      * _stat_nb_write;
+  private   : counters_t                     * _stat_port_read;
+  private   : counters_t                     * _stat_port_write;
+  private   : counters_t                     * _stat_port_read_write;
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_statistics_declaration.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_statistics_declaration.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_statistics_declaration.cpp	(revision 138)
@@ -21,12 +21,32 @@
 		      param_statistics);
 
-    _stat_nb_read           = _stat->create_variable("nb_read" );
-    _stat_nb_write          = _stat->create_variable("nb_write");
+    if (_param->_nb_port_read>0)
+    _stat_port_read         = _stat->create_counters("port_read",_param->_nb_port_read,"",
+                                                     _("Usage of read port %d."),
+                                                     _("Percent of usage read port %d."),
+                                                     _("Average of usage read port.")
+                                                     );
 
-    _stat->create_expr_average_by_cycle("average_read" , "nb_read" , "", _("Average read by cycle" ));
-    _stat->create_expr_average_by_cycle("average_write", "nb_write", "", _("Average write by cycle"));
+    if (_param->_nb_port_write>0)
+    _stat_port_write        = _stat->create_counters("port_write",_param->_nb_port_write,"",
+                                                     _("Usage of write port %d."),
+                                                     _("Percent of usage write port %d."),
+                                                     _("Average of usage write port.")
+                                                     );
+    if (_param->_nb_port_read_write>0)
+    _stat_port_read_write   = _stat->create_counters("port_read_write",_param->_nb_port_read_write,"",
+                                                     _("Usage of read_write port."),
+                                                     _("Percent of usage read_write port %d."),
+                                                     _("Average of usage read_write port.")
+                                                     );
 
-    _stat->create_expr_percent         ("percent_use_read" , "average_read" , toString(_param->_nb_port_read +_param->_nb_port_read_write), _("Percent read by cycle" ));
-    _stat->create_expr_percent         ("percent_use_write", "average_write", toString(_param->_nb_port_write+_param->_nb_port_read_write), _("Percent write by cycle"));
+    // _stat_nb_read           = _stat->create_variable("nb_read" );
+    // _stat_nb_write          = _stat->create_variable("nb_write");
+
+    // _stat->create_expr_average_by_cycle("average_read" , "nb_read" , "", _("Average read by cycle" ));
+    // _stat->create_expr_average_by_cycle("average_write", "nb_write", "", _("Average write by cycle"));
+
+    // _stat->create_expr_percent         ("percent_use_read" , "average_read" , toString(_param->_nb_port_read +_param->_nb_port_read_write), _("Percent read by cycle" ));
+    // _stat->create_expr_percent         ("percent_use_write", "average_write", toString(_param->_nb_port_write+_param->_nb_port_read_write), _("Percent write by cycle"));
 
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp	(revision 138)
@@ -37,4 +37,9 @@
     else
       {
+#ifdef STATISTICS
+        uint32_t stat_nb_read      =0;
+        uint32_t stat_nb_write     =0;
+        uint32_t stat_nb_read_write=0;
+#endif
         for (uint32_t i=0; i<_param->_nb_port_write; i++)
           {
@@ -45,7 +50,11 @@
               {
 #ifdef STATISTICS
-                if (usage_is_set(_usage,USE_STATISTICS))
-                  (*_stat_nb_write) ++;
-#endif    
+                stat_nb_write++;
+#endif
+
+// #ifdef STATISTICS
+//                 if (usage_is_set(_usage,USE_STATISTICS))
+//                   (*_stat_nb_write) ++;
+// #endif    
 
                 Taddress_t address = (_param->_have_port_address)?PORT_READ(in_WRITE_ADDRESS[i]):0;
@@ -74,10 +83,14 @@
             if (PORT_READ(in_READ_WRITE_VAL[i]) == true)
               {
+#ifdef STATISTICS
+                stat_nb_read_write++;
+#endif
+
                 if (PORT_READ(in_READ_WRITE_RW [i]) == RW_WRITE)
                   {
-#ifdef STATISTICS
-                    if (usage_is_set(_usage,USE_STATISTICS))
-                      (*_stat_nb_write) ++;
-#endif    
+// #ifdef STATISTICS
+//                     if (usage_is_set(_usage,USE_STATISTICS))
+//                       (*_stat_nb_write) ++;
+// #endif    
                     
                     Taddress_t address = (_param->_have_port_address)?PORT_READ(in_READ_WRITE_ADDRESS[i]):0;
@@ -95,21 +108,34 @@
                     reg_DATA[address] = data;
                   }
-#ifdef STATISTICS
-                else
-                  {
-                    if (usage_is_set(_usage,USE_STATISTICS))
-                      (*_stat_nb_read) ++;
-                  }
-#endif    
+// #ifdef STATISTICS
+//                 else
+//                   {
+//                     if (usage_is_set(_usage,USE_STATISTICS))
+//                       (*_stat_nb_read) ++;
+//                   }
+// #endif    
               }
           }
+
+        
+#ifdef STATISTICS
+        if (usage_is_set(_usage,USE_STATISTICS))
+          {
+            for (uint32_t i=0; i<_param->_nb_port_read; i++)
+              if ( PORT_READ(in_READ_VAL [i]) == 1)
+                {
+                  stat_nb_read ++;
+                  // (*_stat_nb_read) ++;
+                }
+
+            if (_param->_nb_port_read>0)
+            (*_stat_port_read      ) += stat_nb_read;
+            if (_param->_nb_port_write>0)
+            (*_stat_port_write     ) += stat_nb_write;
+            if (_param->_nb_port_read_write>0)
+            (*_stat_port_read_write) += stat_nb_read_write;
+          }
+#endif    
       }
-
-#ifdef STATISTICS
-    if (usage_is_set(_usage,USE_STATISTICS))
-      for (uint32_t i=0; i<_param->_nb_port_read; i++)
-        if ( PORT_READ(in_READ_VAL [i]) == 1)
-          (*_stat_nb_read) ++;
-#endif    
 
 #if defined(DEBUG_RegisterFile_Monolithic) and DEBUG_RegisterFile_Monolithic and (DEBUG >= DEBUG_TRACE)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info	(revision 138)
@@ -3,54 +3,59 @@
 target_dep	all	RegisterFile_Multi_Banked_00.ngc
 target_dep	RegisterFile_Multi_Banked_00.ngc	RegisterFile_Multi_Banked_00.prj
-target_dep	RegisterFile_Multi_Banked_00.prj	RegisterFile_Multi_Banked_00_bank_Pack.vhdl RegisterFile_Multi_Banked_00_bank.vhdl RegisterFile_Multi_Banked_00_Pack.vhdl RegisterFile_Multi_Banked_00_select_12_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_12_ports.vhdl RegisterFile_Multi_Banked_00_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_6_ports.vhdl RegisterFile_Multi_Banked_00.vhdl
+target_dep	RegisterFile_Multi_Banked_00.prj	RegisterFile_Multi_Banked_00_bank_Pack.vhdl RegisterFile_Multi_Banked_00_bank.vhdl RegisterFile_Multi_Banked_00_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports.vhdl RegisterFile_Multi_Banked_00.vhdl
 
 # RegisterFile_Multi_Banked_01
 target_dep	all	RegisterFile_Multi_Banked_01.ngc
 target_dep	RegisterFile_Multi_Banked_01.ngc	RegisterFile_Multi_Banked_01.prj
-target_dep	RegisterFile_Multi_Banked_01.prj	RegisterFile_Multi_Banked_01_bank_Pack.vhdl RegisterFile_Multi_Banked_01_bank.vhdl RegisterFile_Multi_Banked_01_Pack.vhdl RegisterFile_Multi_Banked_01_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_01_select_6_ports.vhdl RegisterFile_Multi_Banked_01.vhdl
+target_dep	RegisterFile_Multi_Banked_01.prj	RegisterFile_Multi_Banked_01_bank_Pack.vhdl RegisterFile_Multi_Banked_01_bank.vhdl RegisterFile_Multi_Banked_01_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports.vhdl RegisterFile_Multi_Banked_01.vhdl
 
 # RegisterFile_Multi_Banked_02
 target_dep	all	RegisterFile_Multi_Banked_02.ngc
 target_dep	RegisterFile_Multi_Banked_02.ngc	RegisterFile_Multi_Banked_02.prj
-target_dep	RegisterFile_Multi_Banked_02.prj	RegisterFile_Multi_Banked_02_bank_Pack.vhdl RegisterFile_Multi_Banked_02_bank.vhdl RegisterFile_Multi_Banked_02_Pack.vhdl RegisterFile_Multi_Banked_02_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_1_ports.vhdl RegisterFile_Multi_Banked_02_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_2_ports.vhdl RegisterFile_Multi_Banked_02.vhdl
+target_dep	RegisterFile_Multi_Banked_02.prj	RegisterFile_Multi_Banked_02_bank_Pack.vhdl RegisterFile_Multi_Banked_02_bank.vhdl RegisterFile_Multi_Banked_02_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports.vhdl RegisterFile_Multi_Banked_02.vhdl
 
 # RegisterFile_Multi_Banked_03
 target_dep	all	RegisterFile_Multi_Banked_03.ngc
 target_dep	RegisterFile_Multi_Banked_03.ngc	RegisterFile_Multi_Banked_03.prj
-target_dep	RegisterFile_Multi_Banked_03.prj	RegisterFile_Multi_Banked_03_bank_Pack.vhdl RegisterFile_Multi_Banked_03_bank.vhdl RegisterFile_Multi_Banked_03_Pack.vhdl RegisterFile_Multi_Banked_03_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_03_select_2_ports.vhdl RegisterFile_Multi_Banked_03.vhdl
+target_dep	RegisterFile_Multi_Banked_03.prj	RegisterFile_Multi_Banked_03_bank_Pack.vhdl RegisterFile_Multi_Banked_03_bank.vhdl RegisterFile_Multi_Banked_03_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports.vhdl RegisterFile_Multi_Banked_03.vhdl
 
 # RegisterFile_Multi_Banked_04
 target_dep	all	RegisterFile_Multi_Banked_04.ngc
 target_dep	RegisterFile_Multi_Banked_04.ngc	RegisterFile_Multi_Banked_04.prj
-target_dep	RegisterFile_Multi_Banked_04.prj	RegisterFile_Multi_Banked_04_bank_Pack.vhdl RegisterFile_Multi_Banked_04_bank.vhdl RegisterFile_Multi_Banked_04_Pack.vhdl RegisterFile_Multi_Banked_04_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_1_ports.vhdl RegisterFile_Multi_Banked_04_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_2_ports.vhdl RegisterFile_Multi_Banked_04.vhdl
+target_dep	RegisterFile_Multi_Banked_04.prj	RegisterFile_Multi_Banked_04_bank_Pack.vhdl RegisterFile_Multi_Banked_04_bank.vhdl RegisterFile_Multi_Banked_04_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports.vhdl RegisterFile_Multi_Banked_04.vhdl
 
 # RegisterFile_Multi_Banked_05
 target_dep	all	RegisterFile_Multi_Banked_05.ngc
 target_dep	RegisterFile_Multi_Banked_05.ngc	RegisterFile_Multi_Banked_05.prj
-target_dep	RegisterFile_Multi_Banked_05.prj	RegisterFile_Multi_Banked_05_bank_Pack.vhdl RegisterFile_Multi_Banked_05_bank.vhdl RegisterFile_Multi_Banked_05_Pack.vhdl RegisterFile_Multi_Banked_05_select_12_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_12_ports.vhdl RegisterFile_Multi_Banked_05_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_6_ports.vhdl RegisterFile_Multi_Banked_05.vhdl
+target_dep	RegisterFile_Multi_Banked_05.prj	RegisterFile_Multi_Banked_05_bank_Pack.vhdl RegisterFile_Multi_Banked_05_bank.vhdl RegisterFile_Multi_Banked_05_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports.vhdl RegisterFile_Multi_Banked_05.vhdl
 
 # RegisterFile_Multi_Banked_06
 target_dep	all	RegisterFile_Multi_Banked_06.ngc
 target_dep	RegisterFile_Multi_Banked_06.ngc	RegisterFile_Multi_Banked_06.prj
-target_dep	RegisterFile_Multi_Banked_06.prj	RegisterFile_Multi_Banked_06_bank_Pack.vhdl RegisterFile_Multi_Banked_06_bank.vhdl RegisterFile_Multi_Banked_06_Pack.vhdl RegisterFile_Multi_Banked_06_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_06_select_3_ports.vhdl RegisterFile_Multi_Banked_06.vhdl
+target_dep	RegisterFile_Multi_Banked_06.prj	RegisterFile_Multi_Banked_06_bank_Pack.vhdl RegisterFile_Multi_Banked_06_bank.vhdl RegisterFile_Multi_Banked_06_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports.vhdl RegisterFile_Multi_Banked_06.vhdl
 
 # RegisterFile_Multi_Banked_07
 target_dep	all	RegisterFile_Multi_Banked_07.ngc
 target_dep	RegisterFile_Multi_Banked_07.ngc	RegisterFile_Multi_Banked_07.prj
-target_dep	RegisterFile_Multi_Banked_07.prj	RegisterFile_Multi_Banked_07_bank_Pack.vhdl RegisterFile_Multi_Banked_07_bank.vhdl RegisterFile_Multi_Banked_07_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports.vhdl RegisterFile_Multi_Banked_07.vhdl
+target_dep	RegisterFile_Multi_Banked_07.prj	RegisterFile_Multi_Banked_07_bank_Pack.vhdl RegisterFile_Multi_Banked_07_bank.vhdl RegisterFile_Multi_Banked_07_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports.vhdl RegisterFile_Multi_Banked_07_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports.vhdl RegisterFile_Multi_Banked_07.vhdl
 
 # RegisterFile_Multi_Banked_08
 target_dep	all	RegisterFile_Multi_Banked_08.ngc
 target_dep	RegisterFile_Multi_Banked_08.ngc	RegisterFile_Multi_Banked_08.prj
-target_dep	RegisterFile_Multi_Banked_08.prj	RegisterFile_Multi_Banked_08_bank_Pack.vhdl RegisterFile_Multi_Banked_08_bank.vhdl RegisterFile_Multi_Banked_08_Pack.vhdl RegisterFile_Multi_Banked_08_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_1_ports.vhdl RegisterFile_Multi_Banked_08_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_2_ports.vhdl RegisterFile_Multi_Banked_08.vhdl
+target_dep	RegisterFile_Multi_Banked_08.prj	RegisterFile_Multi_Banked_08_bank_Pack.vhdl RegisterFile_Multi_Banked_08_bank.vhdl RegisterFile_Multi_Banked_08_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports.vhdl RegisterFile_Multi_Banked_08_select_22_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_22_ports.vhdl RegisterFile_Multi_Banked_08.vhdl
 
 # RegisterFile_Multi_Banked_09
 target_dep	all	RegisterFile_Multi_Banked_09.ngc
 target_dep	RegisterFile_Multi_Banked_09.ngc	RegisterFile_Multi_Banked_09.prj
-target_dep	RegisterFile_Multi_Banked_09.prj	RegisterFile_Multi_Banked_09_bank_Pack.vhdl RegisterFile_Multi_Banked_09_bank.vhdl RegisterFile_Multi_Banked_09_Pack.vhdl RegisterFile_Multi_Banked_09_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_6_ports.vhdl RegisterFile_Multi_Banked_09.vhdl
+target_dep	RegisterFile_Multi_Banked_09.prj	RegisterFile_Multi_Banked_09_bank_Pack.vhdl RegisterFile_Multi_Banked_09_bank.vhdl RegisterFile_Multi_Banked_09_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports.vhdl RegisterFile_Multi_Banked_09_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_3_ports.vhdl RegisterFile_Multi_Banked_09_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_4_ports.vhdl RegisterFile_Multi_Banked_09.vhdl
 
 # RegisterFile_Multi_Banked_10
 target_dep	all	RegisterFile_Multi_Banked_10.ngc
 target_dep	RegisterFile_Multi_Banked_10.ngc	RegisterFile_Multi_Banked_10.prj
-target_dep	RegisterFile_Multi_Banked_10.prj	RegisterFile_Multi_Banked_10_bank_Pack.vhdl RegisterFile_Multi_Banked_10_bank.vhdl RegisterFile_Multi_Banked_10_Pack.vhdl RegisterFile_Multi_Banked_10_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_10_select_3_ports.vhdl RegisterFile_Multi_Banked_10.vhdl
+target_dep	RegisterFile_Multi_Banked_10.prj	RegisterFile_Multi_Banked_10_bank_Pack.vhdl RegisterFile_Multi_Banked_10_bank.vhdl RegisterFile_Multi_Banked_10_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports.vhdl RegisterFile_Multi_Banked_10.vhdl
 
+# RegisterFile_Multi_Banked_11
+target_dep	all	RegisterFile_Multi_Banked_11.ngc
+target_dep	RegisterFile_Multi_Banked_11.ngc	RegisterFile_Multi_Banked_11.prj
+target_dep	RegisterFile_Multi_Banked_11.prj	RegisterFile_Multi_Banked_11_bank_Pack.vhdl RegisterFile_Multi_Banked_11_bank.vhdl RegisterFile_Multi_Banked_11_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports.vhdl RegisterFile_Multi_Banked_11_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_2_ports.vhdl RegisterFile_Multi_Banked_11.vhdl
+
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common	(revision 138)
@@ -29,6 +29,6 @@
 DIR_INC				= include
 DIR_SRC				= src
-DIR_OBJ				= $(DIR_TMP)/obj
-DIR_LIB                         = $(MORPHEO_PREFIX)/lib
+DIR_OBJ				= $(DIR_TMP)/obj/$(MORPHEO_TYPE)
+DIR_LIB                         = $(MORPHEO_PREFIX)/lib/$(MORPHEO_TYPE)
 DIR_SCRIPT			= $(MORPHEO_SCRIPT)
 
@@ -49,17 +49,18 @@
 
 #-----[ Variable ]-----------------------------------------
+PREFIX_OBJ			= $(ENTITY)_
 #OBJECTS_COMMON			= $(patsubst $(DIR_SRC)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SRC)/*.cpp))
 SOURCES				= $(wildcard $(DIR_SRC)/*.cpp)
-OBJECTS_COMMON			= $(addprefix $(DIR_OBJ)/$(ENTITY)_, $(addsuffix .o, $(basename $(notdir $(SOURCES)))))
+OBJECTS_COMMON			= $(addprefix $(DIR_OBJ)/$(PREFIX_OBJ), $(addsuffix .o, $(basename $(notdir $(SOURCES)))))
 
 HEADERS  			= $(wildcard $(DIR_INC)/*.h)
 
 #-----[ Rules ]--------------------------------------------
-.PRECIOUS			: $(DIR_OBJ)/$(ENTITY)_%.o
+.PRECIOUS			: $(DIR_OBJ)/$(PREFIX_OBJ)%.o
 
 test_env			:
 				@$(ECHO) "-------------------| $(ENTITY)"
 
-$(DIR_OBJ)/$(ENTITY)_%.o        : $(DIR_SRC)/%.cpp $(HEADERS)
+$(DIR_OBJ)/$(PREFIX_OBJ)%.o	: $(DIR_SRC)/%.cpp $(HEADERS)
 				@\
 				$(ECHO) "Compilation        : $*";\
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.deps
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.deps	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.deps	(revision 138)
@@ -23,5 +23,4 @@
 					-lCommon
                                         					
-
 Behavioural_DIR_LIBRARY		=	-L$(Behavioural_DIR)/lib	\
 					-L$(Common_DIR)/lib
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf	(revision 138)
@@ -6,22 +6,22 @@
 
 _Generic/Queue/SelfTest:
-	make all -C Generic/Queue/SelfTest
+	gmake all -C Generic/Queue/SelfTest
 
 _Generic/RegisterFile/RegisterFile_Monolithic/SelfTest:
-	make all -C Generic/RegisterFile/RegisterFile_Monolithic/SelfTest
+	gmake all -C Generic/RegisterFile/RegisterFile_Monolithic/SelfTest
 
 _Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest:
-	make all -C Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest
+	gmake all -C Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest
 
 clean:
-	make clean -C Generic/Queue/SelfTest
-	make clean -C Generic/RegisterFile/RegisterFile_Monolithic/SelfTest
-	make clean -C Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest
+	gmake clean -C Generic/Queue/SelfTest
+	gmake clean -C Generic/RegisterFile/RegisterFile_Monolithic/SelfTest
+	gmake clean -C Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest
 
 re: clean all
 
 install:
-	make install -C Generic/Queue/SelfTest
-	make install -C Generic/RegisterFile/RegisterFile_Monolithic/SelfTest
-	make install -C Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest
+	gmake install -C Generic/Queue/SelfTest
+	gmake install -C Generic/RegisterFile/RegisterFile_Monolithic/SelfTest
+	gmake install -C Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component.sh
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component.sh	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component.sh	(revision 138)
@@ -1,3 +1,3 @@
-#!/bin/sh
+#!/bin/bash
 
 SED_SCRIPT=".sed_script";
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/src/New_Component.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/src/New_Component.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/src/New_Component.cpp	(revision 138)
@@ -62,5 +62,5 @@
 #endif
 
-#ifdef SYSTEMC
+#if defined(SYSTEMC) and (defined(STATISTICS) or defined(VHDL_TESTBENCH))
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
@@ -74,7 +74,6 @@
 	// List dependency information
 # endif    
-	
+      }
 #endif
-      }
     log_end(@COMPONENT,FUNCTION);
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h	(revision 138)
@@ -143,4 +143,5 @@
 	}
     }
+#endif
 
 #undef  FUNCTION
@@ -184,5 +185,31 @@
       log_printf(FUNC,Behavioural,FUNCTION,"End");
     }
-#endif
+
+
+#undef  FUNCTION
+#define FUNCTION "Signal::alloc"
+  void              dealloc         (void)
+    {
+      log_printf(FUNC,Behavioural,FUNCTION,"Begin");
+
+      switch (_direction)
+        {
+        case INTERNAL :
+          switch (_type_info)
+            {
+            case BOOL     : delete (static_cast<sc_signal <bool    > *>(_sc_signal_map)); break; 
+            case UINT8_T  : delete (static_cast<sc_signal <uint8_t > *>(_sc_signal_map)); break; 
+            case UINT16_T : delete (static_cast<sc_signal <uint16_t> *>(_sc_signal_map)); break;
+            case UINT32_T : delete (static_cast<sc_signal <uint32_t> *>(_sc_signal_map)); break; 
+            case UINT64_T : delete (static_cast<sc_signal <uint64_t> *>(_sc_signal_map)); break; 
+            default       : throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow.\n"));
+            }
+        default : throw (ErrorMorpheo ("Signal \""+_name+"\" : invalid direction.\n"));
+
+
+        }
+
+      log_printf(FUNC,Behavioural,FUNCTION,"End");
+    }
 
 #ifdef VHDL
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Simulation.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Simulation.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Simulation.h	(revision 138)
@@ -19,8 +19,16 @@
 namespace behavioural          {
 
+  typedef enum
+    {
+      ALL_THREAD,
+      EACH_THREAD_AND_CONTINUE,
+      EACH_THREAD_AND_STOP
+    } stop_type_t;
+
   extern bool                _simulation_stop_exception;
   extern double              _simulation_nb_cycle;
   extern double              _simulation_nb_instruction;
   extern std::vector<double> _simulation_nb_instruction_commited;
+  extern stop_type_t         _simulation_stop_type;
   extern bool                _simulation_file_with_date;
   extern bool                _simulation_file_with_pid ;
@@ -29,10 +37,40 @@
 
   bool simulation_test_end (void);
-  void simulation_init     (double nb_cycle,
-                            double denug_nb_cycle,
-                            double nb_instruction,
-                            bool   file_with_date,
-                            bool   file_with_pid);
+  void simulation_init     (double      nb_cycle,
+                            double      denug_nb_cycle,
+                            double      nb_instruction,
+                            stop_type_t stop_type,
+                            bool        file_with_date,
+                            bool        file_with_pid);
 }; // end namespace behavioural          
+
+  template<> inline std::string toString<morpheo::behavioural::stop_type_t>(const morpheo::behavioural::stop_type_t& x)
+  {
+    switch (x)
+      {
+      case morpheo::behavioural::ALL_THREAD               : return "all_thread"; break;
+      case morpheo::behavioural::EACH_THREAD_AND_CONTINUE : return "each_thread_and_continue"; break;
+      case morpheo::behavioural::EACH_THREAD_AND_STOP     : return "each_thread_and_stop"; break;
+      default : return ""; break;
+      }
+  };
+
+  template<> inline morpheo::behavioural::stop_type_t fromString<morpheo::behavioural::stop_type_t>(const std::string& x)
+  {
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::ALL_THREAD))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::ALL_THREAD )) == 0))
+      return morpheo::behavioural::ALL_THREAD;
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::EACH_THREAD_AND_CONTINUE))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::EACH_THREAD_AND_CONTINUE )) == 0))
+      return morpheo::behavioural::EACH_THREAD_AND_CONTINUE;
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::EACH_THREAD_AND_STOP))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::EACH_THREAD_AND_STOP )) == 0))
+      return morpheo::behavioural::EACH_THREAD_AND_STOP;
+
+    throw (ERRORMORPHEO ("fromString","Unknow string : \""+x+"\""));
+  };
+
 }; // end namespace morpheo              
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Stat.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Stat.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Stat.h	(revision 138)
@@ -49,14 +49,16 @@
     private: const cycle_t                  _period;
     private: const bool                     _save_periodic;
+    private: bool                           _generate_file;
+
       // Tableau des variables
     private: std::map<std::string, var_t> * _list_operand;
       // Liste chaîné des expressions
     private: std::list<expr_t>            * _list_expr;
+      // List chaîné des "counters" (seulement pour la désallocation)
+    private: std::list<counters_t*>       * _list_counters;
 
     private: counter_t                    * _cycle;
 
     private: std::list<Stat *>            * _list_stat;
-
-    private: bool                           _generate_file;
 
     public :                     Stat                         (std::string name_instance,
@@ -73,4 +75,10 @@
 						               std::string unit,
 						               std::string description);
+    public  : counters_t *       create_counters              (std::string varname,
+                                                               uint32_t    nb_counter,
+						               std::string unit,
+						               std::string description_counter, // need one %d
+                                                               std::string description_percent, // need one %d
+                                                               std::string description_average);
     private : counter_t *        alloc_operand                (counter_type_t type,
 						               std::string varname,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Stat_type.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Stat_type.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Stat_type.h	(revision 138)
@@ -6,4 +6,5 @@
 #include <map>
 #include <utility>
+#include <cassert>
 
 namespace morpheo {
@@ -19,4 +20,62 @@
 //typedef std::pair<std::string, operator_t> pair_string_operator_t;
 
+  class counters_t
+  {
+  private : const uint32_t     _nb_counter;
+  private :       counter_t ** _counter;
+
+  public  : counters_t (uint32_t nb_counter):
+    _nb_counter (nb_counter+1)
+    {
+      assert(nb_counter>0);
+
+      _counter = new counter_t * [_nb_counter];
+    }
+
+  // public : counters_t (const counters_t & x):
+  //   _nb_counter (x._nb_counter)
+  //   {
+  //     _counter = new counter_t [_nb_counter];
+      
+  //     for (uint32_t i=0; i<_nb_counter; ++i)
+  //       _counter[i] = x._counter[i];
+  //   }
+    
+  public  : ~counters_t (void)
+    {
+      delete [] _counter;
+    }
+
+  public  : void set_counter (counter_t * counter,
+                              uint32_t    index)
+    {
+      assert((index >= 0) and (index < _nb_counter));
+
+      _counter [index] = counter;
+    }
+
+  // public : friend const counters_t  operator+ (const counters_t & left,
+  //                                              const uint32_t     right)
+  //   {
+  //     assert((right >= 0) and (right <= left._nb_counter));
+      
+  //     counters_t tmp=left;
+      
+  //     tmp._counter[right] ++;
+    
+  //     return tmp;
+  //   }
+
+  public : const counters_t & operator+= (const uint32_t value)
+    {
+      assert((value >= 0) and (value <= _nb_counter));
+      
+      (*_counter[value]) ++;
+      
+      return *this;
+    }
+
+  };
+
 };
 };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h	(revision 138)
@@ -172,10 +172,12 @@
   template<> inline morpheo::behavioural::Tpriority_t fromString<morpheo::behavioural::Tpriority_t>(const std::string& x)
   {
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PRIORITY_STATIC))) == 0) or
-         (x.compare("priority_static")      == 0))
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PRIORITY_STATIC))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::PRIORITY_STATIC )) == 0))
       return morpheo::behavioural::PRIORITY_STATIC;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PRIORITY_ROUND_ROBIN))) == 0) or
-         (x.compare("priority_round_robin") == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PRIORITY_ROUND_ROBIN))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::PRIORITY_ROUND_ROBIN )) == 0))
       return morpheo::behavioural::PRIORITY_ROUND_ROBIN;
+
     throw (ERRORMORPHEO ("fromString","Unknow string : \""+x+"\""));
   };
@@ -193,10 +195,12 @@
   template<> inline morpheo::behavioural::Tload_balancing_t fromString<morpheo::behavioural::Tload_balancing_t>(const std::string& x)
   {
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::LOAD_BALANCING_BALANCE))) == 0) or
-         (x.compare("load_balancing_balance") == 0))
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::LOAD_BALANCING_BALANCE))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::LOAD_BALANCING_BALANCE )) == 0))
       return morpheo::behavioural::LOAD_BALANCING_BALANCE;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::LOAD_BALANCING_MAXIMUM_FOR_PRIORITY))) == 0) or
-         (x.compare("load_balancing_maximum_for_priority") == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::LOAD_BALANCING_MAXIMUM_FOR_PRIORITY))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::LOAD_BALANCING_MAXIMUM_FOR_PRIORITY )) == 0))
       return morpheo::behavioural::LOAD_BALANCING_MAXIMUM_FOR_PRIORITY;
+
     throw (ERRORMORPHEO ("fromString","Unknow string : \""+x+"\""));
   };
@@ -218,22 +222,28 @@
   template<> inline morpheo::behavioural::Tvictim_t fromString<morpheo::behavioural::Tvictim_t>(const std::string& x)
   {
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::VICTIM_RANDOM     ))) == 0) or
-         (x.compare("victim_random")      == 0))
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::VICTIM_RANDOM     ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::VICTIM_RANDOM      )) == 0))
       return morpheo::behavioural::VICTIM_RANDOM;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::VICTIM_ROUND_ROBIN))) == 0) or
-         (x.compare("victim_round_robin") == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::VICTIM_ROUND_ROBIN))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::VICTIM_ROUND_ROBIN )) == 0))
       return morpheo::behavioural::VICTIM_ROUND_ROBIN;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::VICTIM_NLU        ))) == 0) or
-         (x.compare("victim_nlu")         == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::VICTIM_NLU        ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::VICTIM_NLU         )) == 0))
       return morpheo::behavioural::VICTIM_NLU;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::VICTIM_PSEUDO_LRU ))) == 0) or
-         (x.compare("victim_pseudo_lru")  == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::VICTIM_PSEUDO_LRU ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::VICTIM_PSEUDO_LRU  )) == 0))
       return morpheo::behavioural::VICTIM_PSEUDO_LRU;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::VICTIM_LRU        ))) == 0) or
-         (x.compare("victim_lru")         == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::VICTIM_LRU        ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::VICTIM_LRU         )) == 0))
       return morpheo::behavioural::VICTIM_LRU;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::VICTIM_FIFO       ))) == 0) or
-         (x.compare("victim_fifo")        == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::VICTIM_FIFO       ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::VICTIM_FIFO        )) == 0))
       return morpheo::behavioural::VICTIM_FIFO;
+
     throw (ERRORMORPHEO ("fromString","Unknow string : \""+x+"\""));
   };
@@ -258,31 +268,40 @@
   template<> inline morpheo::behavioural::Tpredictor_t fromString<morpheo::behavioural::Tpredictor_t>(const std::string& x)
   {
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_NEVER_TAKE ))) == 0) or
-         (x.compare("predictor_never_take")  == 0))
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_NEVER_TAKE ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::PREDICTOR_NEVER_TAKE  )) == 0))
       return morpheo::behavioural::PREDICTOR_NEVER_TAKE;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_ALWAYS_TAKE))) == 0) or
-         (x.compare("predictor_always_take") == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_ALWAYS_TAKE))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::PREDICTOR_ALWAYS_TAKE )) == 0))
       return morpheo::behavioural::PREDICTOR_ALWAYS_TAKE;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_STATIC     ))) == 0) or
-         (x.compare("predictor_static")      == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_STATIC     ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::PREDICTOR_STATIC      )) == 0))
       return morpheo::behavioural::PREDICTOR_STATIC;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_LAST_TAKE  ))) == 0) or
-         (x.compare("predictor_last_take")   == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_LAST_TAKE  ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::PREDICTOR_LAST_TAKE   )) == 0))
       return morpheo::behavioural::PREDICTOR_LAST_TAKE;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_COUNTER    ))) == 0) or
-         (x.compare("predictor_counter")     == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_COUNTER    ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::PREDICTOR_COUNTER     )) == 0))
       return morpheo::behavioural::PREDICTOR_COUNTER;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_LOCAL      ))) == 0) or
-         (x.compare("predictor_local")       == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_LOCAL      ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::PREDICTOR_LOCAL       )) == 0))
       return morpheo::behavioural::PREDICTOR_LOCAL;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_GLOBAL     ))) == 0) or
-         (x.compare("predictor_global")      == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_GLOBAL     ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::PREDICTOR_GLOBAL      )) == 0))
       return morpheo::behavioural::PREDICTOR_GLOBAL;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_META       ))) == 0) or
-         (x.compare("predictor_meta")        == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_META       ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::PREDICTOR_META        )) == 0))
       return morpheo::behavioural::PREDICTOR_META;
-    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_CUSTOM     ))) == 0) or
-         (x.compare("predictor_custom")      == 0))
+
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::PREDICTOR_CUSTOM     ))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::PREDICTOR_CUSTOM      )) == 0))
       return morpheo::behavioural::PREDICTOR_CUSTOM;
+
     throw (ERRORMORPHEO ("fromString","Unknow string : \""+x+"\""));
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Debug_signal.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Debug_signal.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Debug_signal.cpp	(revision 138)
@@ -38,10 +38,10 @@
   void debug_signal::print (void)
   {
-    msg("List of access signal\n");
+    msgInformation("List of access signal\n");
     for (std::list<std::string>::iterator it = _signal_access.begin();
          it != _signal_access.end();
          ++ it)
       {
-        msg(" * %s\n",(*it).c_str());
+        msgInformation(" * %s\n",(*it).c_str());
       }
   }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface.cpp	(revision 138)
@@ -77,5 +77,5 @@
         if ((_usage & USE_SYSTEMC) and 
             ((*it)->get_direction() == INTERNAL))
-          delete (*it)->get_sc_signal();
+          (*it)->dealloc();
         delete (*it);
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation.cpp	(revision 138)
@@ -18,4 +18,5 @@
   double              _simulation_nb_instruction;
   std::vector<double> _simulation_nb_instruction_commited;
+  stop_type_t         _simulation_stop_type;
   bool                _simulation_file_with_date;
   bool                _simulation_file_with_pid ;
@@ -23,9 +24,10 @@
   Model               _model;
 
-  void simulation_init (double nb_cycle,
-                        double debug_nb_cycle,
-                        double nb_instruction,
-                        bool   file_with_date,
-                        bool   file_with_pid )
+  void simulation_init (double      nb_cycle,
+                        double      debug_nb_cycle,
+                        double      nb_instruction,
+                        stop_type_t stop_type,
+                        bool        file_with_date,
+                        bool        file_with_pid )
   {
     if (not simulation_initialized)
@@ -44,4 +46,5 @@
         _simulation_nb_instruction          = nb_instruction;
 //      _simulation_nb_instruction_commited = new std::vector<double>;
+        _simulation_stop_type               = stop_type;
         _simulation_file_with_date          = file_with_date;
         _simulation_file_with_pid           = file_with_pid ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation_test_end.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation_test_end.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation_test_end.cpp	(revision 138)
@@ -35,12 +35,37 @@
       {
         end_inst = true;
+        std::vector<double>::iterator it=_simulation_nb_instruction_commited.begin();
 
-        std::vector<double>::iterator it=_simulation_nb_instruction_commited.begin();
-        
-        // Scan all context and test if all can finish
-        while (end_inst and it!=_simulation_nb_instruction_commited.end())
+        switch (_simulation_stop_type)
           {
-            end_inst &= (_simulation_nb_instruction <= *it);
-            it ++;
+          case ALL_THREAD :
+            {
+              double sum_inst = 0;
+
+              // Scan all context and test if all can finish
+              while (it!=_simulation_nb_instruction_commited.end())
+                {
+                  sum_inst += *it;
+                  it ++;
+                }
+              
+              // Stop if sum of all instruction is higher of "simulation_nb_instruction"
+              end_inst &= (_simulation_nb_instruction <= sum_inst);
+
+              break;
+            }
+          case EACH_THREAD_AND_CONTINUE :
+          case EACH_THREAD_AND_STOP :
+            {
+              // Scan all context and test if all can finish
+              while (end_inst and it!=_simulation_nb_instruction_commited.end())
+                {
+
+                  // Stop if all thread have executed more that "simulation_nb_instruction" instructions.
+                  end_inst &= (_simulation_nb_instruction <= *it);
+                  it ++;
+                }
+              break;
+            }
           }
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat.cpp	(revision 137)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat.cpp	(revision 138)
@@ -14,13 +14,14 @@
     _save_periodic         (_period>0)
   {
+    _generate_file = true;
+
     _list_operand  = new std::map<std::string, var_t>;
     _list_expr     = new std::list<expr_t>;
     _list_stat     = new std::list<Stat *>;
+    _list_counters = new std::list<counters_t *>;
 
     _cycle         = create_variable("cycle");
 //  _cycle         = create_counter("cycle","","");
     *_cycle        = 0; // for the first period
-
-    _generate_file = true;
   }
 
@@ -35,13 +36,14 @@
     _save_periodic         (period>0)
   {
+    _generate_file = true;
+
     _list_operand  = new std::map<std::string, var_t>;
     _list_expr     = new std::list<expr_t>;
     _list_stat     = new std::list<Stat *>;
+    _list_counters = new std::list<counters_t *>;
 
     _cycle         = create_variable("cycle");
 //  _cycle         = create_counter("cycle","","");
     *_cycle        = 0; // for the first period
-
-    _generate_file = true;
   }
 
@@ -68,4 +70,14 @@
       }
     delete _list_expr;
+
+    // parcourir la liste et desallouer les arbres
+    for (std::list<counters_t*>::iterator i=_list_counters->begin();
+	 i!= _list_counters->end();
+	 ++i)
+      {
+	delete *i;
+      }
+    delete _list_counters;
+
     delete _list_stat;
   }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_create_counters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_create_counters.cpp	(revision 138)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_create_counters.cpp	(revision 138)
@@ -0,0 +1,37 @@
+#ifdef STATISTICS
+#include "Behavioural/include/Stat.h"
+
+namespace morpheo {
+namespace behavioural {
+  counters_t * Stat::create_counters (std::string varname, 
+                                      uint32_t    nb_counter, 
+                                      std::string unit,
+                                      std::string description_counter,
+                                      std::string description_percent,
+                                      std::string description_average)
+  {
+    counters_t * counters = new counters_t (nb_counter);
+
+    _list_counters->push_back(counters);
+
+    std::string sum = "0";
+
+    for (uint32_t i=0; i<=nb_counter; ++i) // 0 and _nb_counter
+      {
+        std::string name=varname+"_"+toString(i);
+        
+        counters->set_counter(alloc_operand (TYPE_COUNTER, name, unit, toString(description_counter.c_str(),i)), i);
+
+        create_expr_percent("percent_"+name,name,"cycle",toString(description_percent.c_str(),i));
+
+        if (i!=0)
+          sum = "+ "+sum+" * "+toString(i)+" "+name; // "cycle"
+      }
+
+    create_expr_average_by_cycle("average_"+varname,sum,unit+" / cycle",description_average);
+
+    return counters;
+  }
+};
+};
+#endif
