Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp	(revision 141)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp	(revision 145)
@@ -71,4 +71,5 @@
     std::list<generic::priority::select_t> * select = _priority->select();
     std::list<generic::priority::select_t>::iterator it=select->begin();
+
     for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
       {
@@ -76,13 +77,14 @@
 
         bool ifetch_val = false;
-	while ((it != select->end())    and  // have a no scanned "slot_in" ?
+
+	while ((it != select->end())    and  // have a no scanned instruction from ifetch_unit ?
 // 	       (decod_val [i] == false) and  // have not a previous selected entry?
                (ifetch_val    == false) and  // not find ifetch instruction valid
-	       (context_event_val == false)) // Have not a context_event (spr_access, exception, ...)
+	       (context_event_val == false)) // Have not a context_event (spr_access, exception, ...) (ONCE CONTEXT PER CYCLE (context state moore easy))
 	  {
 // 	    predict_val [i] = false;
 
-	    Tcontext_t x = it->grp;
-	    uint32_t   y = it->elt;
+	    Tcontext_t x = it->grp; // num_front_end
+	    uint32_t   y = it->elt; // num_instruction
 
             log_printf(TRACE,Decod,FUNCTION,"    * IFETCH [%d][%d]",x,y);    
@@ -102,4 +104,5 @@
 		Tgeneral_data_t addr = PORT_READ(in_IFETCH_ADDRESS [x][y]);
 
+                // Read instruction and set default value
 		_decod_instruction->_instruction        = PORT_READ(in_IFETCH_INSTRUCTION [x][y]);
 		_decod_instruction->_context_id         = x;
@@ -132,13 +135,11 @@
 		_decod_instruction->_branch_direction   = 0; // not necessary
 		_decod_instruction->_event_type         = EVENT_TYPE_NONE; // not necessary
-		
-
-
-                // Test IFetch exception
+
+                // Test if ifetch_unit have an exception (per example : IBERR)
                 Texception_t ifetch_exception = PORT_READ(in_IFETCH_EXCEPTION [x][y]);
 
                 if (ifetch_exception == EXCEPTION_IFETCH_NONE)
                   {
-                    // Decod !
+                    // No exception, can Decod !
                     log_printf(TRACE,Decod,FUNCTION,"      * address                : %.8x (%.8x)",addr,(addr<<2));
                     log_printf(TRACE,Decod,FUNCTION,"      * is_delay_slot          : %d",internal_CONTEXT_IS_DELAY_SLOT [x]);
@@ -150,5 +151,11 @@
                 else
                   {
-                    // No decod : nop
+                    // Exception : transform this instruction in a nop
+                    //  * INSTRUCTION_TLB  
+                    //  * INSTRUCTION_PAGE 
+                    //  * BUS_ERROR        
+
+                    log_printf(TRACE,Decod,FUNCTION,"      * exception -> change instruction in a l.nop");
+                    
                     instruction_l_nop (_decod_instruction, _decod_param[x]);
 
@@ -156,7 +163,4 @@
                     _decod_instruction->_exception     = exception_ifetch_to_exception_decod(ifetch_exception);
                     
-                    // INSTRUCTION_TLB  
-                    // INSTRUCTION_PAGE 
-                    // BUS_ERROR        
                     if (_decod_instruction->_is_delay_slot)
                       _decod_instruction->_address_next       = _decod_instruction->_address_previous;
@@ -167,13 +171,23 @@
                   }
 
-		Ttype_t      type      = _decod_instruction->_type;
-                // Depth current. If have decod a branch and i can continue : depth = depth_next
-                Tdepth_t     depth     = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0;
-                // Tcontrol_t   save_rat  = internal_CONTEXT_SAVE_RAT [x];
-                Tcontrol_t   no_execute = _decod_instruction->_no_execute;
-
+		Ttype_t             type             = _decod_instruction->_type;
+                Tdepth_t            depth            = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0;
+                Tbranch_condition_t branch_condition = _decod_instruction->_branch_condition;
+                
+                // Save RAT if instruction is a branch and is conditionnal (not l.j and not l.jal)
+
+              //Tcontrol_t          save_rat         = internal_CONTEXT_SAVE_RAT [x];
+                // Tcontrol_t          save_rat         = ((type == TYPE_BRANCH) and 
+                //                                         not ((branch_condition==BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK) or
+                //                                              (branch_condition==BRANCH_CONDITION_NONE_WITH_WRITE_STACK)));
+
+                Tcontrol_t          save_rat         = ((type == TYPE_BRANCH) and 
+                                                        not (branch_condition==BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK));
+
+                // FIXME : depth+1 valid ???????
                 if ((_param->_nb_branch_speculated[x] > 0) and have_decod_branch [x])
                   depth = (depth+1)%_param->_nb_branch_speculated[x];
-                
+
+                // Write output
 		if (_param->_have_port_context_id)
 		PORT_WRITE(out_DECOD_CONTEXT_ID    [i], x);
@@ -185,16 +199,10 @@
 		PORT_WRITE(out_DECOD_TYPE          [i], type);
 		PORT_WRITE(out_DECOD_OPERATION     [i], _decod_instruction->_operation     );
- 		PORT_WRITE(out_DECOD_NO_EXECUTE    [i], no_execute);
+ 		PORT_WRITE(out_DECOD_NO_EXECUTE    [i], _decod_instruction->_no_execute    );
 		PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot );
-		// PORT_WRITE(out_DECOD_SAVE_RAT      [i], save_rat);
-                PORT_WRITE(out_DECOD_SAVE_RAT      [i], ((type == TYPE_BRANCH) and not no_execute));
+                PORT_WRITE(out_DECOD_SAVE_RAT      [i], save_rat);
 #ifdef DEBUG
  		PORT_WRITE(out_DECOD_ADDRESS       [i], addr);
 #endif
-//                 if ((type == TYPE_BRANCH) and
-//                     ((_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_SET) or
-//                      (_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_UNSET)))
-//                 PORT_WRITE(out_DECOD_ADDRESS_NEXT  [i], _decod_instruction->_address+2);
-//                 else
                 PORT_WRITE(out_DECOD_ADDRESS_NEXT  [i], _decod_instruction->_address_next  );
 		PORT_WRITE(out_DECOD_HAS_IMMEDIAT  [i], _decod_instruction->_has_immediat  );
@@ -206,5 +214,5 @@
 		PORT_WRITE(out_DECOD_READ_RC       [i], _decod_instruction->_read_rc       );
 		PORT_WRITE(out_DECOD_NUM_REG_RC    [i], _decod_instruction->_num_reg_rc    );
-		PORT_WRITE(out_DECOD_WRITE_RD      [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0);
+		PORT_WRITE(out_DECOD_WRITE_RD      [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0); // don't write in RD if RD=0
 		PORT_WRITE(out_DECOD_NUM_REG_RD    [i], _decod_instruction->_num_reg_rd    );
 		PORT_WRITE(out_DECOD_WRITE_RE      [i], _decod_instruction->_write_re      );
@@ -224,11 +232,9 @@
                     log_printf(TRACE,Decod,FUNCTION,"        * predict_val       : %d",ifetch_ack [x][y]);
                     log_printf(TRACE,Decod,FUNCTION,"        * predict_ack       : %d",PORT_READ(in_PREDICT_ACK [i]));
-                                                         
 		    log_printf(TRACE,Decod,FUNCTION,"        * address src       : %.8x (%.8x)",_decod_instruction->_address     ,_decod_instruction->_address     <<2);
 		    log_printf(TRACE,Decod,FUNCTION,"        * address dest      : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2);
                     
-                    // test if have already decod an branch : one branch per context
-		    predict_val [i]     = not have_decod_branch [x] and ifetch_ack  [x][y] // and decod_val [i]
-		      ;
+                    // test if have already decod an branch : ONCE BRANCH PER CONTEXT
+		    predict_val [i]     = not have_decod_branch [x] and ifetch_ack  [x][y]; // and decod_val [i]
                     decod_val   [i]    &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable 		    
                     ifetch_ack  [x][y] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack
@@ -252,5 +258,5 @@
 		if (_param->_have_port_depth)
                 PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x][y]));
-		PORT_WRITE(out_PREDICT_BRANCH_CONDITION            [i],_decod_instruction->_branch_condition  );
+		PORT_WRITE(out_PREDICT_BRANCH_CONDITION            [i],branch_condition);
 // 		PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE          [i],_decod_instruction->_branch_stack_write);
 		PORT_WRITE(out_PREDICT_BRANCH_DIRECTION            [i],_decod_instruction->_branch_direction  );
@@ -266,6 +272,5 @@
 		    // speculative jump at the exception handler
 		    // if type = TYPE_BRANCH, also event_type == EVENT_TYPE_NONE
-		    context_event_val   = ifetch_ack  [x][y] // and decod_val [i]
-		      ;
+		    context_event_val   = ifetch_ack  [x][y]; // and decod_val [i]
 		    decod_val   [i]    &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable 		  
 		    ifetch_ack  [x][y] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable and decod_ack
@@ -277,5 +282,4 @@
                     CONTEXT_EVENT_ADDRESS       = _decod_instruction->_address;
                     CONTEXT_EVENT_ADDRESS_EPCR  = _decod_instruction->_address_next ;
-                
 		  }
 
