Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp	(revision 139)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp	(revision 145)
@@ -131,14 +131,24 @@
     }
 
+    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);
+
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN                    ,"MIN"               ,Tdepth_t         ,_param->_size_depth       ,_param->_nb_front_end,_param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX                    ,"MAX"               ,Tdepth_t         ,_param->_size_depth       ,_param->_nb_front_end,_param->_nb_context[it1]); 
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL                   ,"FULL"              ,Tcontrol_t       ,1                         ,_param->_nb_front_end,_param->_nb_context[it1]); 
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]);
+    }
+
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
     ALLOC1(internal_RENAME_ACK       ,Tcontrol_t,_param->_nb_inst_insert);
-    ALLOC1(internal_RENAME_SAVE      ,Tcontrol_t,_param->_nb_inst_insert);
     ALLOC1(internal_INSERT_ACK       ,Tcontrol_t,_param->_nb_inst_insert);
     ALLOC1(internal_RETIRE_ACK       ,Tcontrol_t,_param->_nb_inst_retire);
     ALLOC2(internal_RETIRE_EVENT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]);
 
-    ALLOC3(rat_gpr_speculative      ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-    ALLOC3(rat_spr_speculative      ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+    ALLOC3(RAT_GPR_NOT_SPECULATIVE  ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
+    ALLOC3(RAT_SPR_NOT_SPECULATIVE  ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
 
     switch(_param->_rat_scheme)
@@ -150,9 +160,9 @@
       case RAT_ONE_SAVE   :
         {
-          ALLOC3(rat_gpr_not_speculative  ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-          ALLOC3(rat_gpr_speculative_valid,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-
-          ALLOC3(rat_spr_not_speculative  ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
-          ALLOC3(rat_spr_speculative_valid,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+          ALLOC4(RAT_GPR_SPECULATIVE      ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic);
+          ALLOC4(RAT_SPR_SPECULATIVE      ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic);
+
+          ALLOC4(RAT_GPR_SPECULATIVE_VALID,bool              ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic);
+          ALLOC4(RAT_SPR_SPECULATIVE_VALID,bool              ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic);
           
           break;
@@ -160,8 +170,13 @@
       case RAT_DEPTH_SAVE :
         {
-          ALLOC4(rat_gpr_save             ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
-          ALLOC4(rat_spr_save             ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
-          ALLOC2(rat_depth                ,Tdepth_t          ,_param->_nb_front_end,_param->_nb_context[it1]);
-    
+          ALLOC4(RAT_GPR_SPECULATIVE      ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
+          ALLOC4(RAT_SPR_SPECULATIVE      ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
+
+          ALLOC4(RAT_GPR_SPECULATIVE_VALID,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
+          ALLOC4(RAT_SPR_SPECULATIVE_VALID,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
+    
+          ALLOC3(reg_RAT_USE              ,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2]);
+          ALLOC2(reg_SAVE_RAT             ,bool              ,_param->_nb_front_end,_param->_nb_context[it1]);
+
           break;
         }
