Changeset 145 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src
- Timestamp:
- Oct 13, 2010, 8:15:51 PM (14 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src
- Files:
-
- 2 edited
-
Rename_unit_allocation.cpp (modified) (8 diffs)
-
Rename_unit_deallocation.cpp (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp
r139 r145 15 15 namespace ooo_engine { 16 16 namespace rename_unit { 17 18 19 17 20 18 #undef FUNCTION … … 101 99 ALLOC1_INTERFACE_BEGIN("insert",OUT,WEST , _("Instruction with physical register"), _param->_nb_inst_insert); 102 100 103 ALLOC1_VALACK_OUT(out_INSERT_VAL ,VAL); 104 ALLOC1_VALACK_IN ( in_INSERT_ACK ,ACK); 105 ALLOC1_SIGNAL_OUT(out_INSERT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 106 ALLOC1_SIGNAL_OUT(out_INSERT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 107 ALLOC1_SIGNAL_OUT(out_INSERT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); 108 #ifdef STATISTICS 109 ALLOC1_SIGNAL_OUT(out_INSERT_INSTRUCTION ,"instruction" ,uint32_t ,32); 110 #endif 111 ALLOC1_SIGNAL_OUT(out_INSERT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 112 ALLOC1_SIGNAL_OUT(out_INSERT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 113 ALLOC1_SIGNAL_OUT(out_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 114 ALLOC1_SIGNAL_OUT(out_INSERT_LAST_EVENT ,"last_event" ,Tcontrol_t ,1 ); 115 ALLOC1_SIGNAL_OUT(out_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ); 101 ALLOC1_VALACK_OUT (out_INSERT_VAL ,VAL); 102 ALLOC1_VALACK_IN ( in_INSERT_ACK ,ACK); 103 ALLOC1_SIGNAL_OUT (out_INSERT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 104 ALLOC1_SIGNAL_OUT (out_INSERT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 105 ALLOC1_SIGNAL_OUT (out_INSERT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); 106 #ifdef STATISTICS 107 ALLOC1_SIGNAL_OUT (out_INSERT_INSTRUCTION ,"instruction" ,uint32_t ,32); 108 #endif 109 ALLOC1_SIGNAL_OUT (out_INSERT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 110 ALLOC1_SIGNAL_OUT (out_INSERT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 111 ALLOC1_SIGNAL_OUT (out_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 112 ALLOC1_SIGNAL_OUT (out_INSERT_LAST_EVENT ,"last_event" ,Tcontrol_t ,1 ); 113 ALLOC1_SIGNAL_OUT (out_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ); 114 ALLOC1_SIGNAL_OUT_COND(out_INSERT_SAVE_RAT ,"save_rat" ,Tcontrol_t ,1 ,_param->_rat_scheme == RAT_DEPTH_SAVE); 116 115 #ifdef DEBUG 117 ALLOC1_SIGNAL_OUT (out_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address );118 #endif 119 ALLOC1_SIGNAL_OUT (out_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address );120 ALLOC1_SIGNAL_OUT (out_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 );121 ALLOC1_SIGNAL_OUT (out_INSERT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data );122 ALLOC1_SIGNAL_OUT (out_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr );123 ALLOC1_SIGNAL_OUT (out_INSERT_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t ,_param->_size_store_queue_ptr );124 ALLOC1_SIGNAL_OUT (out_INSERT_STORE_QUEUE_EMPTY ,"store_queue_empty" ,Tcontrol_t ,1 );125 ALLOC1_SIGNAL_OUT (out_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr );126 ALLOC1_SIGNAL_OUT (out_INSERT_EXCEPTION_USE ,"exception_use" ,Texception_t ,_param->_size_exception_use );127 ALLOC1_SIGNAL_OUT (out_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception );128 ALLOC1_SIGNAL_OUT (out_INSERT_READ_RA ,"read_ra" ,Tcontrol_t ,1 );129 #ifdef DEBUG 130 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RA_LOG ,"num_reg_ra_log" ,Tgeneral_address_t,_param->_size_general_register_logic);131 #endif 132 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register );133 ALLOC1_SIGNAL_OUT (out_INSERT_READ_RB ,"read_rb" ,Tcontrol_t ,1 );134 #ifdef DEBUG 135 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RB_LOG ,"num_reg_rb_log" ,Tgeneral_address_t,_param->_size_general_register_logic);136 #endif 137 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RB_PHY ,"num_reg_rb_phy" ,Tgeneral_address_t,_param->_size_general_register );138 ALLOC1_SIGNAL_OUT (out_INSERT_READ_RC ,"read_rc" ,Tcontrol_t ,1 );139 #ifdef DEBUG 140 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RC_LOG ,"num_reg_rc_log" ,Tspecial_address_t,_param->_size_special_register_logic);141 #endif 142 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RC_PHY ,"num_reg_rc_phy" ,Tspecial_address_t,_param->_size_special_register );143 ALLOC1_SIGNAL_OUT (out_INSERT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 );144 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RD_LOG ,"num_reg_rd_log" ,Tgeneral_address_t,_param->_size_general_register_logic);145 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RD_PHY_OLD ,"num_reg_rd_phy_old" ,Tgeneral_address_t,_param->_size_general_register );146 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RD_PHY_NEW ,"num_reg_rd_phy_new" ,Tgeneral_address_t,_param->_size_general_register );147 ALLOC1_SIGNAL_OUT (out_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 );148 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RE_LOG ,"num_reg_re_log" ,Tspecial_address_t,_param->_size_special_register_logic);149 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register );150 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register );116 ALLOC1_SIGNAL_OUT (out_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ); 117 #endif 118 ALLOC1_SIGNAL_OUT (out_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ); 119 ALLOC1_SIGNAL_OUT (out_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 120 ALLOC1_SIGNAL_OUT (out_INSERT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); 121 ALLOC1_SIGNAL_OUT (out_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); 122 ALLOC1_SIGNAL_OUT (out_INSERT_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t ,_param->_size_store_queue_ptr ); 123 ALLOC1_SIGNAL_OUT (out_INSERT_STORE_QUEUE_EMPTY ,"store_queue_empty" ,Tcontrol_t ,1 ); 124 ALLOC1_SIGNAL_OUT (out_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); 125 ALLOC1_SIGNAL_OUT (out_INSERT_EXCEPTION_USE ,"exception_use" ,Texception_t ,_param->_size_exception_use ); 126 ALLOC1_SIGNAL_OUT (out_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 127 ALLOC1_SIGNAL_OUT (out_INSERT_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); 128 #ifdef DEBUG 129 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RA_LOG ,"num_reg_ra_log" ,Tgeneral_address_t,_param->_size_general_register_logic); 130 #endif 131 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register ); 132 ALLOC1_SIGNAL_OUT (out_INSERT_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); 133 #ifdef DEBUG 134 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RB_LOG ,"num_reg_rb_log" ,Tgeneral_address_t,_param->_size_general_register_logic); 135 #endif 136 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RB_PHY ,"num_reg_rb_phy" ,Tgeneral_address_t,_param->_size_general_register ); 137 ALLOC1_SIGNAL_OUT (out_INSERT_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); 138 #ifdef DEBUG 139 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RC_LOG ,"num_reg_rc_log" ,Tspecial_address_t,_param->_size_special_register_logic); 140 #endif 141 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RC_PHY ,"num_reg_rc_phy" ,Tspecial_address_t,_param->_size_special_register ); 142 ALLOC1_SIGNAL_OUT (out_INSERT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 143 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RD_LOG ,"num_reg_rd_log" ,Tgeneral_address_t,_param->_size_general_register_logic); 144 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RD_PHY_OLD ,"num_reg_rd_phy_old" ,Tgeneral_address_t,_param->_size_general_register ); 145 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RD_PHY_NEW ,"num_reg_rd_phy_new" ,Tgeneral_address_t,_param->_size_general_register ); 146 ALLOC1_SIGNAL_OUT (out_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 147 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RE_LOG ,"num_reg_re_log" ,Tspecial_address_t,_param->_size_special_register_logic); 148 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ); 149 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ); 151 150 152 151 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); … … 210 209 211 210 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 211 } 212 213 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 214 { 215 ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); 216 217 _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); 218 _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); 219 _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL ,"FULL" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); 220 221 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); 212 222 } 213 223 … … 440 450 #endif 441 451 452 if (_param->_rat_scheme != RAT_DEPTH_SAVE) 442 453 COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_SAVE_RAT" , 443 454 dest, "in_RENAME_" +toString(i)+"_SAVE_RAT" ); … … 483 494 COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_DEPTH" , 484 495 dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_DEPTH" ); 496 if (_param->_rat_scheme == RAT_DEPTH_SAVE) 497 COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_SAVE_RAT" , 498 dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_SAVE_RAT" ); 485 499 COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_TYPE" , 486 500 dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_TYPE" ); … … 559 573 COMPONENT_MAP(_component,src , "in_RENAME_"+toString(i)+ "_DEPTH" , 560 574 dest,"out_INSERT_"+toString(i)+"_REGISTER_TRANSLATION_DEPTH" ); 575 if (_param->_rat_scheme == RAT_DEPTH_SAVE) 576 COMPONENT_MAP(_component,src , "in_RENAME_"+toString(i)+ "_SAVE_RAT" , 577 dest,"out_INSERT_"+toString(i)+"_REGISTER_TRANSLATION_SAVE_RAT" ); 561 578 562 579 // in_RENAME_SAVE_RAS - rename_select … … 733 750 } 734 751 752 for (uint32_t i=0; i<_param->_nb_front_end; i++) 753 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 754 { 755 dest = _name; 756 757 #ifdef POSITION 758 _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j), 759 dest,"depth_"+toString(i)+"_"+toString(j)); 760 #endif 761 if (_param->_have_port_depth) 762 { 763 PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" , 764 dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" ); 765 PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" , 766 dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" ); 767 } 768 PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL", 769 dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL"); 770 } 735 771 736 772 #ifdef DEBUG_TEST … … 909 945 PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_DEPTH" , 910 946 dest,"out_INSERT_"+toString(i)+"_DEPTH" ); 947 if (_param->_rat_scheme == RAT_DEPTH_SAVE) 948 PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_SAVE_RAT" , 949 dest,"out_INSERT_"+toString(i)+"_SAVE_RAT" ); 911 950 PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_TYPE" , 912 951 dest,"out_INSERT_"+toString(i)+"_TYPE" ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp
r139 r145 75 75 DELETE1_SIGNAL (out_INSERT_LAST_EVENT ,_param->_nb_inst_insert,1 ); 76 76 DELETE1_SIGNAL (out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert,1 ); 77 DELETE1_SIGNAL_COND(out_INSERT_SAVE_RAT ,_param->_nb_inst_insert,1 ,_param->_rat_scheme == RAT_DEPTH_SAVE); 77 78 #ifdef DEBUG 78 79 DELETE1_SIGNAL (out_INSERT_ADDRESS ,_param->_nb_inst_insert,_param->_size_instruction_address ); … … 147 148 DELETE2_SIGNAL_COND( in_RETIRE_EVENT_DEPTH ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth ,_param->_rat_scheme == RAT_DEPTH_SAVE); 148 149 149 DELETE2_SIGNAL (in_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr); 150 DELETE2_SIGNAL ( in_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr); 151 152 DELETE2_SIGNAL ( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth); 153 DELETE2_SIGNAL ( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth); 154 DELETE2_SIGNAL ( in_DEPTH_FULL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); 150 155 151 156 #ifdef DEBUG_TEST
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