Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,21 +1,0 @@
-Commit_unit
-1	1	+1	# nb_front_end            
-1	1	+1	# nb_context              [0]    [nb_front_end]
-1	1	+1	# nb_rename_unit          
-1	1	+1	# size_queue              
-1	1	+1	# nb_bank                 
-1	1	+1	# nb_inst_insert          [0]    [nb_rename_unit]
-1	1	+1	# nb_inst_retire	  [0]    [nb_rename_unit]
-1	1	+1	# nb_inst_commit
-1	1	+1	# nb_inst_reexecute	 
-1	1	+1	# nb_inst_branch_complete 
-0	0	+1	# nb_branch_speculated    [0][0] [nb_front_end][nb_context]
-1       1       +1      # size_nb_inst_decod
-32	32	+1	# size_general_data       
-1	1	+1	# size_store_queue_ptr    
-0	0	+1	# size_load_queue_ptr     
-5	5	+1	# size_general_register   
-1	1	+1	# size_special_register   
-1	1	+1	# priority              
-1	1	+1	# load_balancing        
-1	1	+1	# nb_rename_unit_select 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg	(revision 144)
+++ 	(revision )
@@ -1,21 +1,0 @@
-Commit_unit
-1	1	+1	# nb_front_end            
-1	1	+1	# nb_context              [0]    [nb_front_end]
-1	1	+1	# nb_rename_unit          
-64 	64	*2	# size_queue              
-4	8 	*2	# nb_bank                 
-1	4	*4	# nb_inst_insert          [0]    [nb_rename_unit]
-1	4	*4	# nb_inst_retire	  [0]    [nb_rename_unit]
-1	4	*4	# nb_inst_commit
-1	1	+1	# nb_inst_reexecute	 
-1	1	+1	# nb_inst_branch_complete 
-0	0	+1	# nb_branch_speculated    [0][0] [nb_front_end][nb_context]
-1       1       +1      # size_nb_inst_decod
-32	32	+1	# size_general_data       
-1	1	+1	# size_store_queue_ptr    
-0	0	+1	# size_load_queue_ptr     
-5	5	+1	# size_general_register   
-1	1	+1	# size_special_register   
-1	1	+1	# priority              
-1	1	+1	# load_balancing        
-1	1	+1	# nb_rename_unit_select 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,21 @@
+Commit_unit
+1	1	+1	# nb_front_end            
+1	1	+1	# nb_context              [0]    [nb_front_end]
+1	1	+1	# nb_rename_unit          
+1	1	+1	# size_queue              
+1	1	+1	# nb_bank                 
+1	1	+1	# nb_inst_insert          [0]    [nb_rename_unit]
+1	1	+1	# nb_inst_retire	  [0]    [nb_rename_unit]
+1	1	+1	# nb_inst_commit
+1	1	+1	# nb_inst_reexecute	 
+1	1	+1	# nb_inst_branch_complete 
+0	0	+1	# nb_branch_speculated    [0][0] [nb_front_end][nb_context]
+1       1       +1      # size_nb_inst_decod
+32	32	+1	# size_general_data       
+1	1	+1	# size_store_queue_ptr    
+0	0	+1	# size_load_queue_ptr     
+5	5	+1	# size_general_register   
+1	1	+1	# size_special_register   
+1	1	+1	# priority              
+1	1	+1	# load_balancing        
+1	1	+1	# nb_rename_unit_select 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/configuration/config_mono_rename_unit.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/configuration/config_mono_rename_unit.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/configuration/config_mono_rename_unit.gen	(revision 145)
@@ -0,0 +1,21 @@
+Commit_unit
+1	1	+1	# nb_front_end            
+1	1	+1	# nb_context              [0]    [nb_front_end]
+1	1	+1	# nb_rename_unit          
+64 	64	*2	# size_queue              
+4	8 	*2	# nb_bank                 
+1	4	*4	# nb_inst_insert          [0]    [nb_rename_unit]
+1	4	*4	# nb_inst_retire	  [0]    [nb_rename_unit]
+1	4	*4	# nb_inst_commit
+1	1	+1	# nb_inst_reexecute	 
+1	1	+1	# nb_inst_branch_complete 
+0	0	+1	# nb_branch_speculated    [0][0] [nb_front_end][nb_context]
+1       1       +1      # size_nb_inst_decod
+32	32	+1	# size_general_data       
+1	1	+1	# size_store_queue_ptr    
+0	0	+1	# size_load_queue_ptr     
+5	5	+1	# size_general_register   
+1	1	+1	# size_special_register   
+1	1	+1	# priority              
+1	1	+1	# load_balancing        
+1	1	+1	# nb_rename_unit_select 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 145)
@@ -74,5 +74,5 @@
   public    : counter_t                     ** _stat_nb_cycle_state_wait_end      ;//[nb_thread]
 
-// public    : uint32_t                       * _stat_last_inst                    ;//[nb_thread]
+//public    : uint32_t                       * _stat_last_inst                    ;//[nb_thread]
   public    : uint32_t                       * _stat_last_inst_type               ;//[nb_thread]
   public    : uint32_t                       * _stat_last_inst_operation          ;//[nb_thread]
@@ -97,4 +97,5 @@
 //public    : SC_IN (Tcontext_t         ) ***  in_INSERT_RENAME_UNIT_ID            ;//[nb_rename_unit][nb_inst_insert]
   public    : SC_IN (Tdepth_t           ) ***  in_INSERT_DEPTH                     ;//[nb_rename_unit][nb_inst_insert]
+  public    : SC_IN (Tcontrol_t         ) ***  in_INSERT_SAVE_RAT                  ;//[nb_rename_unit][nb_inst_insert]
 #ifdef STATISTICS
   public    : SC_IN (uint32_t           ) ***  in_INSERT_INSTRUCTION               ;//[nb_rename_unit][nb_inst_insert]
@@ -141,4 +142,5 @@
   public    : SC_OUT(Tcontext_t         ) *** out_RETIRE_CONTEXT_ID                ;//[nb_rename_unit][nb_inst_retire]
 //public    : SC_OUT(Tcontext_t         ) *** out_RETIRE_RENAME_UNIT_ID            ;//[nb_rename_unit][nb_inst_retire]
+//public    : SC_OUT(Tdepth_t           ) *** out_RETIRE_DEPTH                     ;//[nb_rename_unit][nb_inst_retire]
   public    : SC_OUT(Tcontrol_t         ) *** out_RETIRE_USE_STORE_QUEUE           ;//[nb_rename_unit][nb_inst_retire]
   public    : SC_OUT(Tcontrol_t         ) *** out_RETIRE_USE_LOAD_QUEUE            ;//[nb_rename_unit][nb_inst_retire]
@@ -234,8 +236,8 @@
   public    : SC_IN (Tcounter_t         ) ***  in_NB_INST_DECOD_ALL                ;//[nb_front_end][nb_context]
 										   
-    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
-  public    : SC_IN (Tdepth_t           ) ***  in_DEPTH_MIN                        ;//[nb_front_end][nb_context]
-  public    : SC_IN (Tdepth_t           ) ***  in_DEPTH_MAX                        ;//[nb_front_end][nb_context]
-  public    : SC_IN (Tcontrol_t         ) ***  in_DEPTH_FULL                       ;//[nb_front_end][nb_context]
+//  // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
+//public    : SC_IN (Tdepth_t           ) ***  in_DEPTH_MIN                        ;//[nb_front_end][nb_context]
+//public    : SC_IN (Tdepth_t           ) ***  in_DEPTH_MAX                        ;//[nb_front_end][nb_context]
+//public    : SC_IN (Tcontrol_t         ) ***  in_DEPTH_FULL                       ;//[nb_front_end][nb_context]
 
     // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -272,4 +274,5 @@
   private   : Tcounter_t                   ** reg_NB_INST_COMMIT_ALL               ;//[nb_front_end][nb_context]
   private   : Tcounter_t                   ** reg_NB_INST_COMMIT_MEM               ;//[nb_front_end][nb_context]
+  private   : Tcounter_t                  *** reg_NB_INST_DEPTH                    ;//[nb_front_end][nb_context][nb_branch_speculated]
 
   private   : Tcommit_event_state_t        ** reg_EVENT_STATE                      ;//[nb_front_end][nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h	(revision 145)
@@ -24,46 +24,49 @@
   {
     //-----[ fields ]------------------------------------------------------------
-  public : uint32_t             _nb_front_end                       ;
-  public : uint32_t           * _nb_context                         ;//[nb_front_end]
-  public : uint32_t             _nb_rename_unit                     ;
-  public : uint32_t             _size_queue                         ;
-  public : uint32_t             _nb_bank                            ;
-  public : Tretire_ooo_scheme_t _retire_ooo_scheme                  ;
-  public : uint32_t           * _nb_inst_insert                     ;//[nb_rename_unit]
-  public : uint32_t           * _nb_inst_retire	                    ;//[nb_rename_unit]
-  public : uint32_t             _nb_inst_commit                     ;
-  public : uint32_t             _nb_inst_reexecute                  ;
-  public : uint32_t             _nb_inst_branch_complete            ;
-  public : uint32_t          ** _nb_branch_speculated               ;//[nb_front_end][nb_context]
-//public : uint32_t             _size_general_data                  ;
-//public : uint32_t             _size_store_queue_ptr               ;
-//public : uint32_t             _size_load_queue_ptr                ;
-//public : uint32_t             _size_general_register              ;
-//public : uint32_t             _size_special_register              ;
-  public : Trat_scheme_t      * _rat_scheme                         ;//[nb_front_end]
-  public : Tpriority_t          _priority                           ;
-  public : Tload_balancing_t    _load_balancing                     ;
-  public : uint32_t             _nb_rename_unit_select              ;
-  public : uint32_t             _nb_thread                          ;
-  public : uint32_t          ** _translate_num_context_to_num_thread;//[nb_front_end][nb_context]
-  public : const uint32_t       _nb_bank_access_commit              ;
+  public : uint32_t               _nb_front_end                       ;
+  public : uint32_t             * _nb_context                         ;//[nb_front_end]
+  public : uint32_t               _nb_rename_unit                     ;
+  public : uint32_t               _size_queue                         ;
+  public : uint32_t               _nb_bank                            ;
+  public : Tretire_ooo_scheme_t   _retire_ooo_scheme                  ;
+  public : uint32_t             * _nb_inst_insert                     ;//[nb_rename_unit]
+  public : uint32_t             * _nb_inst_retire	                    ;//[nb_rename_unit]
+  public : uint32_t               _nb_inst_commit                     ;
+  public : uint32_t               _nb_inst_reexecute                  ;
+  public : uint32_t               _nb_inst_branch_complete            ;
+  public : uint32_t            ** _nb_branch_speculated               ;//[nb_front_end][nb_context]
+//public : uint32_t               _size_general_data                  ;
+//public : uint32_t               _size_store_queue_ptr               ;
+//public : uint32_t               _size_load_queue_ptr                ;
+//public : uint32_t               _size_general_register              ;
+//public : uint32_t               _size_special_register              ;
+  public : Trat_scheme_t        * _rat_scheme                         ;//[nb_rename_unit]
+  public : std::vector<uint32_t>* _link_front_end_with_rename_unit    ;//[nb_rename_unit]
 
-  public : uint32_t             _max_nb_context          ;
-  public : uint32_t             _max_nb_inst_insert      ;
-  public : uint32_t             _max_nb_inst_retire      ;
-//public : uint32_t             _size_address            ;
-//public : uint32_t             _size_front_end_id       ;
-//public : uint32_t             _size_context_id         ;
-  public : uint32_t             _size_rename_unit_id     ;    
-  public : uint32_t             _size_bank               ;
-//public : uint32_t             _size_nb_inst            ;
-//public : uint32_t             _size_packet_id          ;
-  public : uint32_t          ** _array_size_depth        ;//[nb_front_end][nb_context]
-//public : uint32_t             _max_size_depth          ;
-                             
-//public : Tpacket_t            _shift_num_bank          ;
-  public : Tpacket_t            _mask_num_bank           ;
-  public : Tpacket_t            _shift_num_slot          ;
-//public : Tpacket_t            _mask_num_slot           ;
+  public : Tpriority_t            _priority                           ;
+  public : Tload_balancing_t      _load_balancing                     ;
+  public : uint32_t               _nb_rename_unit_select              ;
+  public : uint32_t               _nb_thread                          ;
+  public : uint32_t            ** _translate_num_context_to_num_thread;//[nb_front_end][nb_context]
+  public : Trat_scheme_t        * _front_end_rat_scheme               ;//[nb_front_end]
+  public : const uint32_t         _nb_bank_access_commit              ;
+                               
+  public : uint32_t               _max_nb_context          ;
+  public : uint32_t               _max_nb_inst_insert      ;
+  public : uint32_t               _max_nb_inst_retire      ;
+//public : uint32_t               _size_address            ;
+//public : uint32_t               _size_front_end_id       ;
+//public : uint32_t               _size_context_id         ;
+  public : uint32_t               _size_rename_unit_id     ;    
+  public : uint32_t               _size_bank               ;
+//public : uint32_t               _size_nb_inst            ;
+//public : uint32_t               _size_packet_id          ;
+  public : uint32_t            ** _array_size_depth        ;//[nb_front_end][nb_context]
+//public : uint32_t               _max_size_depth          ;
+                               
+//public : Tpacket_t              _shift_num_bank          ;
+  public : Tpacket_t              _mask_num_bank           ;
+  public : Tpacket_t              _shift_num_slot          ;
+//public : Tpacket_t              _mask_num_slot           ;
                              
                              
@@ -79,29 +82,30 @@
 
     //-----[ methods ]-----------------------------------------------------------
-  public : Parameters  (uint32_t             nb_front_end                       ,
-			uint32_t           * nb_context                         ,//[nb_front_end]
-			uint32_t             nb_rename_unit                     ,
-			uint32_t             size_queue                         ,
-			uint32_t             nb_bank                            ,
-                        Tretire_ooo_scheme_t retire_ooo_scheme                  ,
-			uint32_t           * nb_inst_insert                     ,//[nb_rename_unit]
-			uint32_t           * nb_inst_retire                     ,//[nb_rename_unit]
-			uint32_t             nb_inst_commit                     ,
-			uint32_t             nb_inst_reexecute                  ,
-			uint32_t             nb_inst_branch_complete            ,
-			uint32_t          ** nb_branch_speculated               ,//[nb_front_end][nb_context]
-                        uint32_t             size_nb_inst_decod                 ,
-			uint32_t             size_general_data                  ,
-			uint32_t             size_store_queue_ptr               ,
-			uint32_t             size_load_queue_ptr                ,
-			uint32_t             size_general_register              ,
-			uint32_t             size_special_register              ,
-                        Trat_scheme_t      * rat_scheme                         ,//[nb_front_end]
-			Tpriority_t          priority                           ,
-			Tload_balancing_t    load_balancing                     ,
-			uint32_t             nb_rename_unit_select              ,
-                        uint32_t             nb_thread                          ,
-                        uint32_t          ** translate_num_context_to_num_thread, //[nb_front_end][nb_context]
-                        bool                 is_toplevel=false
+  public : Parameters  (uint32_t               nb_front_end                       ,
+			uint32_t             * nb_context                         ,//[nb_front_end]
+			uint32_t               nb_rename_unit                     ,
+			uint32_t               size_queue                         ,
+			uint32_t               nb_bank                            ,
+                        Tretire_ooo_scheme_t   retire_ooo_scheme                  ,
+			uint32_t             * nb_inst_insert                     ,//[nb_rename_unit]
+			uint32_t             * nb_inst_retire                     ,//[nb_rename_unit]
+			uint32_t               nb_inst_commit                     ,
+			uint32_t               nb_inst_reexecute                  ,
+			uint32_t               nb_inst_branch_complete            ,
+			uint32_t            ** nb_branch_speculated               ,//[nb_front_end][nb_context]
+                        uint32_t               size_nb_inst_decod                 ,
+			uint32_t               size_general_data                  ,
+			uint32_t               size_store_queue_ptr               ,
+			uint32_t               size_load_queue_ptr                ,
+			uint32_t               size_general_register              ,
+			uint32_t               size_special_register              ,
+                        Trat_scheme_t        * rat_scheme                         ,//[nb_rename_unit]
+                        std::vector<uint32_t>* link_front_end_with_rename_unit    ,//[nb_rename_unit]
+                        Tpriority_t            priority                           ,
+			Tload_balancing_t      load_balancing                     ,
+			uint32_t               nb_rename_unit_select              ,
+                        uint32_t               nb_thread                          ,
+                        uint32_t            ** translate_num_context_to_num_thread, //[nb_front_end][nb_context]
+                        bool                   is_toplevel=false
 			);
 //   public : Parameters  (Parameters & param) ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 145)
@@ -81,4 +81,6 @@
   public  : rob_state_t        state                   ;
   public  : rob_state_t        state_old               ;
+//public  : Tcontrol_t         restore                 ;
+
   public  : uint32_t           ptr                     ;
   public  : Tcontext_t         front_end_id            ;
@@ -207,4 +209,20 @@
   };
 
+  template<> inline std::string toString<morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Tcommit_event_state_t>(const morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Tcommit_event_state_t& x)
+  {
+    switch (x)
+      {
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_NO_EVENT      : return "COMMIT_EVENT_STATE_NO_EVENT"     ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_NOT_YET_EVENT : return "COMMIT_EVENT_STATE_NOT_YET_EVENT"; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_EVENT         : return "COMMIT_EVENT_STATE_EVENT"        ; break;
+//    case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_WAIT_DECOD    : return "COMMIT_EVENT_STATE_WAIT_DECOD"   ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_WAIT_END      : return "COMMIT_EVENT_STATE_WAIT_END"     ; break;
+//    case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_END           : return "COMMIT_EVENT_STATE_END"          ; break;
+
+      default    : return ""      ; break;
+      }
+  };
+
+
 }; // end namespace morpheo              
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp	(revision 145)
@@ -115,4 +115,19 @@
 	sensitive << (*(in_CLOCK)).neg() // need internal register
 		  << (*(in_NRESET));
+
+        for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
+          if (_param->_rat_scheme[i] == RAT_DEPTH_SAVE)
+            for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++)
+              {
+                if (_param->_have_port_front_end_id  )
+                sensitive << (*(in_INSERT_FRONT_END_ID [i][j]));
+                if (_param->_have_port_context_id  )
+                sensitive << (*(in_INSERT_CONTEXT_ID   [i][j]));
+                if (_param->_have_port_depth)
+                sensitive << (*(in_INSERT_DEPTH        [i][j]));
+                sensitive << (*(in_INSERT_SAVE_RAT     [i][j]));
+              }
+
+
 // 	for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
 // 	  for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 145)
@@ -59,48 +59,49 @@
       ALLOC2_INTERFACE_BEGIN("insert", IN, SOUTH, _("Interface with rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
 
-      _ALLOC2_VALACK_IN ( in_INSERT_VAL                     ,VAL,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_VALACK_OUT(out_INSERT_ACK                     ,ACK,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_FRONT_END_ID            ,"front_end_id"         ,Tcontext_t        ,_param->_size_front_end_id          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_CONTEXT_ID              ,"context_id"           ,Tcontext_t        ,_param->_size_context_id            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_OUT(out_INSERT_PACKET_ID               ,"packet_id"            ,Tpacket_t         ,_param->_size_rob_ptr               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-//    _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_ID          ,"rename_unit_id"       ,Tcontext_t        ,_param->_size_rename_unit_id        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_DEPTH                   ,"depth"                ,Tdepth_t          ,_param->_size_depth                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#ifdef STATISTICS
-      _ALLOC2_SIGNAL_IN ( in_INSERT_INSTRUCTION             ,"instruction"          ,uint32_t          ,32                                  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#endif
-      _ALLOC2_SIGNAL_IN ( in_INSERT_TYPE                    ,"type"                 ,Ttype_t           ,_param->_size_type                  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_OPERATION               ,"operation"            ,Toperation_t      ,_param->_size_operation             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NO_EXECUTE              ,"no_execute"           ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_LAST_EVENT              ,"last_event"           ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_IS_DELAY_SLOT           ,"is_delay_slot"        ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#ifdef DEBUG
-      _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS                 ,"address"              ,Taddress_t        ,_param->_size_instruction_address   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#endif
-      _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS_NEXT            ,"address_next"         ,Taddress_t        ,_param->_size_instruction_address   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION               ,"exception"            ,Texception_t      ,_param->_size_exception             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION_USE           ,"exception_use"        ,Texception_t      ,_param->_size_exception_use         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_STORE_QUEUE_PTR_WRITE   ,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr       ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_LOAD_QUEUE_PTR_WRITE    ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#ifdef DEBUG
-      _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RA                 ,"read_ra"              ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RA_LOG          ,"num_reg_ra_log"       ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RA_PHY          ,"num_reg_ra_phy"       ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#endif
-      _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RB                 ,"read_rb"              ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#ifdef DEBUG
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RB_LOG          ,"num_reg_rb_log"       ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RB_PHY          ,"num_reg_rb_phy"       ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RC                 ,"read_rc"              ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RC_LOG          ,"num_reg_rc_log"       ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RC_PHY          ,"num_reg_rc_phy"       ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#endif
-      _ALLOC2_SIGNAL_IN ( in_INSERT_WRITE_RD                ,"write_rd"             ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_LOG          ,"num_reg_rd_log"       ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY_OLD      ,"num_reg_rd_phy_old"   ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY_NEW      ,"num_reg_rd_phy_new"   ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_WRITE_RE                ,"write_re"             ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_LOG          ,"num_reg_re_log"       ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_OLD      ,"num_reg_re_phy_old"   ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_NEW      ,"num_reg_re_phy_new"   ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_VALACK_IN      ( in_INSERT_VAL                     ,VAL,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_VALACK_OUT     (out_INSERT_ACK                     ,ACK,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_FRONT_END_ID            ,"front_end_id"         ,Tcontext_t        ,_param->_size_front_end_id          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_CONTEXT_ID              ,"context_id"           ,Tcontext_t        ,_param->_size_context_id            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_OUT     (out_INSERT_PACKET_ID               ,"packet_id"            ,Tpacket_t         ,_param->_size_rob_ptr               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+//    _ALLOC2_SIGNAL_IN      ( in_INSERT_RENAME_UNIT_ID          ,"rename_unit_id"       ,Tcontext_t        ,_param->_size_rename_unit_id        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_DEPTH                   ,"depth"                ,Tdepth_t          ,_param->_size_depth                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN_COND ( in_INSERT_SAVE_RAT                ,"save_rat"             ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
+#ifdef STATISTICS            
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_INSTRUCTION             ,"instruction"          ,uint32_t          ,32                                  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#endif                       
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_TYPE                    ,"type"                 ,Ttype_t           ,_param->_size_type                  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_OPERATION               ,"operation"            ,Toperation_t      ,_param->_size_operation             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NO_EXECUTE              ,"no_execute"           ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_LAST_EVENT              ,"last_event"           ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_IS_DELAY_SLOT           ,"is_delay_slot"        ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#ifdef DEBUG                 
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_ADDRESS                 ,"address"              ,Taddress_t        ,_param->_size_instruction_address   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#endif                       
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_ADDRESS_NEXT            ,"address_next"         ,Taddress_t        ,_param->_size_instruction_address   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_EXCEPTION               ,"exception"            ,Texception_t      ,_param->_size_exception             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_EXCEPTION_USE           ,"exception_use"        ,Texception_t      ,_param->_size_exception_use         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_STORE_QUEUE_PTR_WRITE   ,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr       ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_LOAD_QUEUE_PTR_WRITE    ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#ifdef DEBUG                 
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_READ_RA                 ,"read_ra"              ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RA_LOG          ,"num_reg_ra_log"       ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RA_PHY          ,"num_reg_ra_phy"       ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#endif                       
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_READ_RB                 ,"read_rb"              ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#ifdef DEBUG                 
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RB_LOG          ,"num_reg_rb_log"       ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RB_PHY          ,"num_reg_rb_phy"       ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_READ_RC                 ,"read_rc"              ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RC_LOG          ,"num_reg_rc_log"       ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RC_PHY          ,"num_reg_rc_phy"       ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#endif                       
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_WRITE_RD                ,"write_rd"             ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RD_LOG          ,"num_reg_rd_log"       ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RD_PHY_OLD      ,"num_reg_rd_phy_old"   ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RD_PHY_NEW      ,"num_reg_rd_phy_new"   ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_WRITE_RE                ,"write_re"             ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RE_LOG          ,"num_reg_re_log"       ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RE_PHY_OLD      ,"num_reg_re_phy_old"   ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RE_PHY_NEW      ,"num_reg_re_phy_new"   ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
 
       ALLOC2_INTERFACE_END(_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -116,4 +117,5 @@
       _ALLOC2_SIGNAL_OUT(out_RETIRE_CONTEXT_ID              ,"context_id"           ,Tcontext_t        ,_param->_size_context_id            ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);    
 //    _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_ID          ,"rename_unit_id"       ,Tcontext_t        ,_param->_size_rename_unit_id        ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//    _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_DEPTH              ,"depth"                ,Tdepth_t          ,_param->_size_depth                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
       _ALLOC2_SIGNAL_OUT(out_RETIRE_USE_STORE_QUEUE         ,"use_store_queue"      ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
       _ALLOC2_SIGNAL_OUT(out_RETIRE_USE_LOAD_QUEUE          ,"use_load_queue"       ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
@@ -150,6 +152,6 @@
 //    _ALLOC2_SIGNAL_OUT     (out_RETIRE_EVENT_FLUSH ,"flush"      ,Tcontrol_t        ,1                        ,_param->_nb_front_end,_param->_nb_context[it1]);
       _ALLOC2_SIGNAL_OUT     (out_RETIRE_EVENT_STOP  ,"stop"       ,Tcontrol_t        ,1                        ,_param->_nb_front_end,_param->_nb_context[it1]);
-      _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_EVENT_TYPE  ,"type"       ,Tevent_type_t     ,_param->_size_event_type ,_param->_nb_front_end,_param->_nb_context[it1],_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
-      _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_EVENT_DEPTH ,"depth"      ,Tdepth_t          ,_param->_size_depth      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
+      _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_EVENT_TYPE  ,"type"       ,Tevent_type_t     ,_param->_size_event_type ,_param->_nb_front_end,_param->_nb_context[it1],_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE);
+      _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_EVENT_DEPTH ,"depth"      ,Tdepth_t          ,_param->_size_depth      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE);
 
       ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]);
@@ -255,14 +257,14 @@
     }
 
-    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-    {
-      ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);
-
-      _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN                     ,"min"      ,Tdepth_t           ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]);
-      _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX                     ,"max"      ,Tdepth_t           ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]);
-      _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL                    ,"full"     ,Tcontrol_t         ,1                  ,_param->_nb_front_end, _param->_nb_context[it1]);
-
-      ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
-    }
+//  // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+//  {
+//    ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);
+//
+//    _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN                     ,"min"      ,Tdepth_t           ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]);
+//    _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX                     ,"max"      ,Tdepth_t           ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]);
+//    _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL                    ,"full"     ,Tcontrol_t         ,1                  ,_param->_nb_front_end, _param->_nb_context[it1]);
+//
+//    ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
+//  }
 
 
@@ -332,37 +334,39 @@
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-    ALLOC2(_nb_cycle_idle           ,double               ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC1(_rob                     ,std::list<entry_t*>  ,_param->_nb_bank);
+    ALLOC2     (_nb_cycle_idle           ,double               ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC1     (_rob                     ,std::list<entry_t*>  ,_param->_nb_bank);
+               
+    ALLOC1     (reg_BANK_PTR             ,uint32_t             ,_param->_nb_bank);
+                                                          
+    ALLOC2     (reg_NB_INST_COMMIT_ALL   ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_NB_INST_COMMIT_MEM   ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC3_COND(reg_NB_INST_DEPTH        ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_branch_speculated[it1][it2],_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE);
+    ALLOC2     (reg_EVENT_STATE          ,Tcommit_event_state_t,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_TYPE           ,Tevent_type_t        ,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2     (reg_EVENT_FLUSH          ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2     (reg_EVENT_STOP           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2     (reg_EVENT_NUM_BANK       ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2     (reg_EVENT_NUM_PTR        ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2     (reg_EVENT_CAN_RESTART    ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_PACKET         ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_DEPTH          ,Tdepth_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_NB_INST        ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_LAST           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_LAST_NUM_BANK  ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_LAST_NUM_PTR   ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+               
+    ALLOC2     (reg_EVENT_NEXT_STOP      ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_NEXT_PACKET    ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+                                                               
+//  ALLOC2     (reg_PC_PREVIOUS          ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_PC_CURRENT           ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_PC_CURRENT_IS_DS     ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_PC_CURRENT_IS_DS_TAKE,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_PC_NEXT              ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+               
+    ALLOC3     (rat_gpr_update_table     ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_general_register_logic);
+    ALLOC3     (rat_spr_update_table     ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_special_register_logic);
+
     
-    ALLOC1(reg_BANK_PTR             ,uint32_t             ,_param->_nb_bank);
-                                                          
-    ALLOC2(reg_NB_INST_COMMIT_ALL   ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_NB_INST_COMMIT_MEM   ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-    
-    ALLOC2(reg_EVENT_STATE          ,Tcommit_event_state_t,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_TYPE           ,Tevent_type_t        ,_param->_nb_front_end,_param->_nb_context [it1]);
-//  ALLOC2(reg_EVENT_FLUSH          ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
-//  ALLOC2(reg_EVENT_STOP           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
-//  ALLOC2(reg_EVENT_NUM_BANK       ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-//  ALLOC2(reg_EVENT_NUM_PTR        ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-//  ALLOC2(reg_EVENT_CAN_RESTART    ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_PACKET         ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_DEPTH          ,Tdepth_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_NB_INST        ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_LAST           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_LAST_NUM_BANK  ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_LAST_NUM_PTR   ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-    ALLOC2(reg_EVENT_NEXT_STOP      ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_NEXT_PACKET    ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-                                                          
-//  ALLOC2(reg_PC_PREVIOUS          ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_CURRENT           ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_CURRENT_IS_DS     ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_CURRENT_IS_DS_TAKE,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_NEXT              ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-    ALLOC3(rat_gpr_update_table     ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_general_register_logic);
-    ALLOC3(rat_spr_update_table     ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_special_register_logic);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 145)
@@ -28,48 +28,49 @@
 	delete    in_NRESET;
 
-        DELETE2_SIGNAL( in_INSERT_VAL                     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL(out_INSERT_ACK                     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_FRONT_END_ID            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_front_end_id          );
-        DELETE2_SIGNAL( in_INSERT_CONTEXT_ID              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_context_id            );
-        DELETE2_SIGNAL(out_INSERT_PACKET_ID               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rob_ptr               );
-//      DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_ID          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rename_unit_id        );
-        DELETE2_SIGNAL( in_INSERT_DEPTH                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_depth                 );
-#ifdef STATISTICS
-        DELETE2_SIGNAL( in_INSERT_INSTRUCTION             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],32);
-#endif
-        DELETE2_SIGNAL( in_INSERT_TYPE                    ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type                  );
-        DELETE2_SIGNAL( in_INSERT_OPERATION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_operation             );
-        DELETE2_SIGNAL( in_INSERT_NO_EXECUTE              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_LAST_EVENT              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_IS_DELAY_SLOT           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-#ifdef DEBUG
-        DELETE2_SIGNAL( in_INSERT_ADDRESS                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address               );
-#endif
-        DELETE2_SIGNAL( in_INSERT_ADDRESS_NEXT            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address               );
-        DELETE2_SIGNAL( in_INSERT_EXCEPTION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception             );
-        DELETE2_SIGNAL( in_INSERT_EXCEPTION_USE           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception             );
-        DELETE2_SIGNAL( in_INSERT_STORE_QUEUE_PTR_WRITE   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr       );
-        DELETE2_SIGNAL( in_INSERT_LOAD_QUEUE_PTR_WRITE    ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr        );
-#ifdef DEBUG
-        DELETE2_SIGNAL( in_INSERT_READ_RA                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RA_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic);
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RA_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
-#endif
-        DELETE2_SIGNAL( in_INSERT_READ_RB                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-#ifdef DEBUG
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RB_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic);
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RB_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
-        DELETE2_SIGNAL( in_INSERT_READ_RC                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RC_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic);
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RC_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register      );
-#endif
-        DELETE2_SIGNAL( in_INSERT_WRITE_RD                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RD_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic);
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RD_PHY_OLD      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RD_PHY_NEW      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
-        DELETE2_SIGNAL( in_INSERT_WRITE_RE                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RE_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic);
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RE_PHY_OLD      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register      );
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RE_PHY_NEW      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register      );
+        DELETE2_SIGNAL     ( in_INSERT_VAL                     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     (out_INSERT_ACK                     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_FRONT_END_ID            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_front_end_id          );
+        DELETE2_SIGNAL     ( in_INSERT_CONTEXT_ID              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_context_id            );
+        DELETE2_SIGNAL     (out_INSERT_PACKET_ID               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rob_ptr               );
+//      DELETE2_SIGNAL     ( in_INSERT_RENAME_UNIT_ID          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rename_unit_id        );
+        DELETE2_SIGNAL     ( in_INSERT_DEPTH                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_depth                 );
+        DELETE2_SIGNAL_COND( in_INSERT_SAVE_RAT                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   ,_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
+#ifdef STATISTICS          
+        DELETE2_SIGNAL     ( in_INSERT_INSTRUCTION             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],32);
+#endif                     
+        DELETE2_SIGNAL     ( in_INSERT_TYPE                    ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type                  );
+        DELETE2_SIGNAL     ( in_INSERT_OPERATION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_operation             );
+        DELETE2_SIGNAL     ( in_INSERT_NO_EXECUTE              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_LAST_EVENT              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_IS_DELAY_SLOT           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+#ifdef DEBUG               
+        DELETE2_SIGNAL     ( in_INSERT_ADDRESS                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address   );
+#endif                     
+        DELETE2_SIGNAL     ( in_INSERT_ADDRESS_NEXT            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address   );
+        DELETE2_SIGNAL     ( in_INSERT_EXCEPTION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception             );
+        DELETE2_SIGNAL     ( in_INSERT_EXCEPTION_USE           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception             );
+        DELETE2_SIGNAL     ( in_INSERT_STORE_QUEUE_PTR_WRITE   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr       );
+        DELETE2_SIGNAL     ( in_INSERT_LOAD_QUEUE_PTR_WRITE    ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr        );
+#ifdef DEBUG               
+        DELETE2_SIGNAL     ( in_INSERT_READ_RA                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RA_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic);
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RA_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
+#endif                     
+        DELETE2_SIGNAL     ( in_INSERT_READ_RB                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+#ifdef DEBUG               
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RB_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic);
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RB_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
+        DELETE2_SIGNAL     ( in_INSERT_READ_RC                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RC_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic);
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RC_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register      );
+#endif                     
+        DELETE2_SIGNAL     ( in_INSERT_WRITE_RD                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RD_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic);
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RD_PHY_OLD      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RD_PHY_NEW      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
+        DELETE2_SIGNAL     ( in_INSERT_WRITE_RE                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RE_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic);
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RE_PHY_OLD      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register      );
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RE_PHY_NEW      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register      );
 
         DELETE2_SIGNAL(out_RETIRE_VAL                     ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
@@ -78,14 +79,15 @@
         DELETE2_SIGNAL(out_RETIRE_CONTEXT_ID              ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_context_id            );    
 //      DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_ID          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_rename_unit_id        );
+//      DELETE2_SIGNAL_COND(out_RETIRE_DEPTH              ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_depth                 ,_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
         DELETE2_SIGNAL(out_RETIRE_USE_STORE_QUEUE         ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
         DELETE2_SIGNAL(out_RETIRE_USE_LOAD_QUEUE          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
         DELETE2_SIGNAL(out_RETIRE_STORE_QUEUE_PTR_WRITE   ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_store_queue_ptr       );
         DELETE2_SIGNAL(out_RETIRE_LOAD_QUEUE_PTR_WRITE    ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_load_queue_ptr        );
-//         DELETE2_SIGNAL(out_RETIRE_READ_RA                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
-//         DELETE2_SIGNAL(out_RETIRE_NUM_REG_RA_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register      );
-//         DELETE2_SIGNAL(out_RETIRE_READ_RB                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
-//         DELETE2_SIGNAL(out_RETIRE_NUM_REG_RB_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register      );
-//         DELETE2_SIGNAL(out_RETIRE_READ_RC                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
-//         DELETE2_SIGNAL(out_RETIRE_NUM_REG_RC_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register      );
+//      DELETE2_SIGNAL(out_RETIRE_READ_RA                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
+//      DELETE2_SIGNAL(out_RETIRE_NUM_REG_RA_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register      );
+//      DELETE2_SIGNAL(out_RETIRE_READ_RB                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
+//      DELETE2_SIGNAL(out_RETIRE_NUM_REG_RB_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register      );
+//      DELETE2_SIGNAL(out_RETIRE_READ_RC                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
+//      DELETE2_SIGNAL(out_RETIRE_NUM_REG_RC_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register      );
         DELETE2_SIGNAL(out_RETIRE_WRITE_RD                ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
         DELETE2_SIGNAL(out_RETIRE_NUM_REG_RD_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register_logic);
@@ -105,6 +107,6 @@
 //      DELETE2_SIGNAL     (out_RETIRE_EVENT_FLUSH             ,_param->_nb_front_end,_param->_nb_context[it1],1);
         DELETE2_SIGNAL     (out_RETIRE_EVENT_STOP              ,_param->_nb_front_end,_param->_nb_context[it1],1);
-        DELETE2_SIGNAL_COND(out_RETIRE_EVENT_TYPE              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_event_type,_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
-        DELETE2_SIGNAL_COND(out_RETIRE_EVENT_DEPTH             ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth     ,_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
+        DELETE2_SIGNAL_COND(out_RETIRE_EVENT_TYPE              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_event_type,_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE);
+        DELETE2_SIGNAL_COND(out_RETIRE_EVENT_DEPTH             ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth     ,_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE);
 
         DELETE1_SIGNAL( in_COMMIT_VAL               ,_param->_nb_inst_commit,1                             );
@@ -164,7 +166,7 @@
         DELETE2_SIGNAL( in_NB_INST_DECOD_ALL              ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_decod);
 
-        DELETE2_SIGNAL( in_DEPTH_MIN                      ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth);
-        DELETE2_SIGNAL( in_DEPTH_MAX                      ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth);
-        DELETE2_SIGNAL( in_DEPTH_FULL                     ,_param->_nb_front_end, _param->_nb_context[it1],1);
+//      DELETE2_SIGNAL( in_DEPTH_MIN                      ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth);
+//      DELETE2_SIGNAL( in_DEPTH_MAX                      ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth);
+//      DELETE2_SIGNAL( in_DEPTH_FULL                     ,_param->_nb_front_end, _param->_nb_context[it1],1);
 
 	DELETE2_SIGNAL( in_SPR_READ_SR_OVE                ,_param->_nb_front_end, _param->_nb_context[it1],1);
@@ -221,35 +223,36 @@
 	    }
 
-        DELETE2(_nb_cycle_idle           ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE1(_rob                     ,_param->_nb_bank);
-        DELETE1(reg_BANK_PTR             ,_param->_nb_bank);
-        DELETE2(reg_NB_INST_COMMIT_ALL   ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_NB_INST_COMMIT_MEM   ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-        DELETE2(reg_EVENT_STATE          ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_TYPE           ,_param->_nb_front_end,_param->_nb_context [it1]);
-//      DELETE2(reg_EVENT_FLUSH          ,_param->_nb_front_end,_param->_nb_context [it1]);
-//      DELETE2(reg_EVENT_STOP           ,_param->_nb_front_end,_param->_nb_context [it1]);
-//      DELETE2(reg_EVENT_NUM_BANK       ,_param->_nb_front_end,_param->_nb_context [it1]);
-//      DELETE2(reg_EVENT_NUM_PTR        ,_param->_nb_front_end,_param->_nb_context [it1]);
-//      DELETE2(reg_EVENT_CAN_RESTART    ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_PACKET         ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_DEPTH          ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_NB_INST        ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_LAST           ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_LAST_NUM_BANK  ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_LAST_NUM_PTR   ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-        DELETE2(reg_EVENT_NEXT_STOP      ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_NEXT_PACKET    ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-//      DELETE2(reg_PC_PREVIOUS          ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_PC_CURRENT           ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_PC_CURRENT_IS_DS     ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_PC_CURRENT_IS_DS_TAKE,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_PC_NEXT              ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-        DELETE3(rat_gpr_update_table     ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_general_register_logic);
-        DELETE3(rat_spr_update_table     ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_special_register_logic);
+        DELETE2     (_nb_cycle_idle           ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE1     (_rob                     ,_param->_nb_bank);
+        DELETE1     (reg_BANK_PTR             ,_param->_nb_bank);
+        DELETE2     (reg_NB_INST_COMMIT_ALL   ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_NB_INST_COMMIT_MEM   ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE3_COND(reg_NB_INST_DEPTH        ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_branch_speculated[it1][it2],_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE);
+
+        DELETE2     (reg_EVENT_STATE          ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_TYPE           ,_param->_nb_front_end,_param->_nb_context [it1]);
+//      DELETE2     (reg_EVENT_FLUSH          ,_param->_nb_front_end,_param->_nb_context [it1]);
+//      DELETE2     (reg_EVENT_STOP           ,_param->_nb_front_end,_param->_nb_context [it1]);
+//      DELETE2     (reg_EVENT_NUM_BANK       ,_param->_nb_front_end,_param->_nb_context [it1]);
+//      DELETE2     (reg_EVENT_NUM_PTR        ,_param->_nb_front_end,_param->_nb_context [it1]);
+//      DELETE2     (reg_EVENT_CAN_RESTART    ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_PACKET         ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_DEPTH          ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_NB_INST        ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_LAST           ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_LAST_NUM_BANK  ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_LAST_NUM_PTR   ,_param->_nb_front_end,_param->_nb_context [it1]);
+                    
+        DELETE2     (reg_EVENT_NEXT_STOP      ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_NEXT_PACKET    ,_param->_nb_front_end,_param->_nb_context [it1]);
+                    
+//      DELETE2     (reg_PC_PREVIOUS          ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_PC_CURRENT           ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_PC_CURRENT_IS_DS     ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_PC_CURRENT_IS_DS_TAKE,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_PC_NEXT              ,_param->_nb_front_end,_param->_nb_context [it1]);
+                    
+        DELETE3     (rat_gpr_update_table     ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_general_register_logic);
+        DELETE3     (rat_spr_update_table     ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_special_register_logic);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 145)
@@ -101,20 +101,42 @@
                     if (not bank_full [num_bank])
                       {
-                        // find !!!
-                        insert_ack       [num_rename_unit][num_inst_insert] = true;
+                        bool cond = true;
+
+                        if (_param->_rat_scheme[num_rename_unit] == RAT_DEPTH_SAVE)
+                          {
+                            Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [num_rename_unit][num_inst_insert]):0;
+                            Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_INSERT_CONTEXT_ID   [num_rename_unit][num_inst_insert]):0;
+                            Tdepth_t   depth        = (_param->_have_port_depth       )?PORT_READ(in_INSERT_DEPTH        [num_rename_unit][num_inst_insert]):0;
+                            Tcontrol_t save_rat     =                                   PORT_READ(in_INSERT_SAVE_RAT     [num_rename_unit][num_inst_insert]);
+
+                            cond = not (save_rat and (reg_NB_INST_DEPTH[front_end_id][context_id][depth]>0));
+
+                            log_printf(TRACE,Commit_unit,FUNCTION,"        * front_end_id : %d",front_end_id);
+                            log_printf(TRACE,Commit_unit,FUNCTION,"        * context_id   : %d",context_id  );
+                            log_printf(TRACE,Commit_unit,FUNCTION,"        * depth        : %d",depth       );
+                            log_printf(TRACE,Commit_unit,FUNCTION,"        * save_rat     : %d",save_rat    );
+                            log_printf(TRACE,Commit_unit,FUNCTION,"        * cond         : %d",cond        );
+                            
+                          }
                         
-                        Tpacket_t packet_id = ((reg_BANK_PTR [num_bank] << _param->_shift_num_slot) | num_bank);
-                        
+                        if (cond)
+                          {
+                            // find !!!
+                            insert_ack       [num_rename_unit][num_inst_insert] = true;
+                            
+                            Tpacket_t packet_id = ((reg_BANK_PTR [num_bank] << _param->_shift_num_slot) | num_bank);
+                            
 #ifdef SYSTEMC_VHDL_COMPATIBILITY
-                        insert_packet_id [num_rename_unit][num_inst_insert] = packet_id;
+                            insert_packet_id [num_rename_unit][num_inst_insert] = packet_id;
 #else
-                        if (_param->_have_port_rob_ptr  )
-                        PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id);
+                            if (_param->_have_port_rob_ptr  )
+                              PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id);
 #endif
-                        internal_BANK_INSERT_VAL             [num_bank] = true;
-                        internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit;
-                        internal_BANK_INSERT_NUM_INST        [num_bank] = num_inst_insert;
-                        
-                        break;
+                            internal_BANK_INSERT_VAL             [num_bank] = true;
+                            internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit;
+                            internal_BANK_INSERT_NUM_INST        [num_bank] = num_inst_insert;
+                            
+                            break;
+                          }
                       }
                   }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 145)
@@ -225,4 +225,6 @@
                         PORT_WRITE(out_RETIRE_CONTEXT_ID            [x][y], context_id                  );
 // 		        PORT_WRITE(out_RETIRE_RENAME_UNIT_ID        [x][y], entry->rename_unit_id       );
+//                      if (_param->_have_port_depth and (_param->_rat_scheme[x] == RAT_DEPTH_SAVE))
+//                      PORT_WRITE(out_RETIRE_DEPTH                 [x][y], entry->depth                );
                         PORT_WRITE(out_RETIRE_USE_STORE_QUEUE       [x][y], entry->use_store_queue      );
                         PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE        [x][y], entry->use_load_queue       );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 145)
@@ -331,5 +331,5 @@
           PORT_WRITE(out_RETIRE_EVENT_STOP  [i][j], ((reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_NOT_YET_EVENT) or
                                                      reg_EVENT_NEXT_STOP [i][j]));
-          if (_param->_rat_scheme[i] == RAT_DEPTH_SAVE)
+          if (_param->_front_end_rat_scheme[i] == RAT_DEPTH_SAVE)
             {
           PORT_WRITE(out_RETIRE_EVENT_TYPE  [i][j], reg_EVENT_TYPE  [i][j]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp	(revision 145)
@@ -48,4 +48,6 @@
     uint32_t mask_operation = gen_mask<uint32_t>(SIZE_OPERATION  );
 
+    msgInformation("Number of iteration couple of instructions.\n");
+
     for (uint32_t i=0; i<_param->_nb_thread; ++i)
       for(stat_inst_fusion_t::iterator it = _stat_inst_fusion [i].begin();
@@ -64,15 +66,14 @@
               uint32_t operation_1 =                      inst                               &mask_operation ;
 
-              // log_printf(STAT,Commit_unit,FUNCTION,
               msgInformation(
                            //"  * %s - %s : %d\n"
                            //,toString_instruction((inst>>SIZE_INSTRUCTION)&mask_inst).c_str()
                            //,toString_instruction( inst                   &mask_inst).c_str(),value
-                             "  * %s.%s - %s.%s : %d\n"
+                             "  * (%d) \t%s.%s - %s.%s\n"
+                             ,value
                              ,toString          (type_0            ).c_str()
                              ,toString_operation(type_0,operation_0).c_str()
                              ,toString          (type_1            ).c_str()
                              ,toString_operation(type_1,operation_1).c_str()
-                             ,value
                              );
             }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 145)
@@ -48,7 +48,4 @@
               _nb_cycle_idle            [i][j] = 0;
 
-	      reg_NB_INST_COMMIT_ALL    [i][j] = 0;
-	      reg_NB_INST_COMMIT_MEM    [i][j] = 0;
-                                        
               reg_EVENT_STATE           [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
 //            reg_EVENT_FLUSH           [i][j] = false;
@@ -72,4 +69,11 @@
               reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0;
               reg_PC_NEXT               [i][j] = (0x100+4)>>2;
+
+	      reg_NB_INST_COMMIT_ALL    [i][j] = 0;
+	      reg_NB_INST_COMMIT_MEM    [i][j] = 0;
+                          
+              if (_param->_front_end_rat_scheme[i] == RAT_DEPTH_SAVE)
+                for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+                  reg_NB_INST_DEPTH [i][j][k] = 0;
 	    }
 
@@ -281,4 +285,5 @@
                       uint32_t  ptr   = reg_BANK_PTR [num_bank];
 
+	              // entry->restore                 = false;
 	              entry->ptr                     = ptr;
 	              entry->front_end_id            = front_end_id;
@@ -353,5 +358,5 @@
                               {
                               case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END  ; break;}
-                              case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store  ==1)?ROB_STORE_WAIT_END_OK:ROB_OTHER_WAIT_END); break;}
+                              case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store==1)?ROB_STORE_WAIT_END_OK:ROB_OTHER_WAIT_END); break;}
                               default          : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
                               }
@@ -378,5 +383,7 @@
                       if (type == TYPE_MEMORY)
                         reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++;
-                      
+
+                      if (_param->_front_end_rat_scheme[front_end_id] == RAT_DEPTH_SAVE)
+                      reg_NB_INST_DEPTH [front_end_id][context_id][entry->depth] ++;
 
                       // flush = present event or future event.
@@ -856,5 +863,6 @@
                     if (type == TYPE_MEMORY)
                     reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
-	            
+                    if (_param->_front_end_rat_scheme[front_end_id] == RAT_DEPTH_SAVE)
+	            reg_NB_INST_DEPTH      [front_end_id][context_id][entry->depth] --;
 	            // Update pointer
 	            reg_NUM_BANK_HEAD = (num_bank+1)%_param->_nb_bank;
@@ -1191,22 +1199,22 @@
                           switch (state)
                             {
-                            case ROB_BRANCH_WAIT_END             : {state = ROB_EVENT_WAIT_END; break;}
-                            case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS      ; break;}
+                            case ROB_BRANCH_WAIT_END             : {state = ROB_EVENT_WAIT_END   ; break;}
+                            case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS         ; break;}
                             case ROB_END_BRANCH_MISS             :
-                            case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS         ; break;}
                             case ROB_END_LOAD_MISS               :
                             case ROB_END_LOAD_MISS_UPDATE        :
-                            case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_MISS      ; break;}
-                            case ROB_STORE_OK                    : {state = ROB_STORE_KO      ; break;}
+                            case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_MISS         ; break;}
+                            case ROB_STORE_OK                    : {state = ROB_STORE_KO         ; break;}
                             case ROB_STORE_WAIT_END_OK           : {state = ROB_STORE_WAIT_END_KO; break;}
 			    case ROB_STORE_OK_WAIT_END           : {state = ROB_STORE_KO_WAIT_END; break;}
-                            case ROB_OTHER_WAIT_END              : {state = ROB_EVENT_WAIT_END; break;}
+                            case ROB_OTHER_WAIT_END              : {state = ROB_EVENT_WAIT_END   ; break;}
                             case ROB_END_OK                      :
-                            case ROB_END_OK_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_OK_SPECULATIVE          : {state = ROB_END_MISS         ; break;}
                             case ROB_END_KO                      :
-                            case ROB_END_KO_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_KO_SPECULATIVE          : {state = ROB_END_MISS         ; break;}
                             case ROB_END_EXCEPTION_UPDATE        :
                             case ROB_END_EXCEPTION               :
-                            case ROB_END_EXCEPTION_WAIT_HEAD     : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_EXCEPTION_WAIT_HEAD     : {state = ROB_END_MISS         ; break;}
                               
                               // don't change state -> wait
@@ -1348,5 +1356,6 @@
 //          log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT             : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]);
 //          log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_DEPTH       : %d - type %s",reg_EVENT_DEPTH [i][j],toString(reg_EVENT_TYPE [i][j]).c_str());
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_DEPTH       : %d",reg_EVENT_DEPTH [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_TYPE        : %s",toString(reg_EVENT_TYPE [i][j]).c_str());
             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_LAST        : %d - packet %d - ptr %d (bank %d, ptr %d)",reg_EVENT_LAST [i][j],reg_EVENT_PACKET[i][j],((reg_EVENT_LAST_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [i][j]), reg_EVENT_LAST_NUM_BANK [i][j],reg_EVENT_LAST_NUM_PTR [i][j]);
             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_NEXT        : stop : %d - packet : %d",reg_EVENT_NEXT_STOP  [i][j],reg_EVENT_NEXT_PACKET[i][j]);
@@ -1436,5 +1445,5 @@
         }
 
-      log_printf(TRACE,Commit_unit,FUNCTION,"  * Dump RAT Update Table");
+      log_printf(TRACE,Commit_unit,FUNCTION,"  * Dump RAT_Update Table");
       for (uint32_t i=0; i<_param->_nb_front_end; ++i)
         for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp	(revision 145)
@@ -21,29 +21,30 @@
 #undef  FUNCTION
 #define FUNCTION "Commit_unit::Parameters"
-  Parameters::Parameters (uint32_t             nb_front_end                       ,
-			  uint32_t           * nb_context                         ,//[nb_front_end]            
-			  uint32_t             nb_rename_unit                     ,                            
-			  uint32_t             size_queue                         ,                            
-			  uint32_t             nb_bank                            ,                            
-                          Tretire_ooo_scheme_t retire_ooo_scheme                  ,                            
-			  uint32_t           * nb_inst_insert                     ,//[nb_rename_unit]          
-			  uint32_t           * nb_inst_retire                     ,//[nb_rename_unit]
-			  uint32_t             nb_inst_commit                     ,                            
-			  uint32_t             nb_inst_reexecute                  ,                            
-			  uint32_t             nb_inst_branch_complete            ,                            
-			  uint32_t          ** nb_branch_speculated               ,//[nb_front_end][nb_context]
-                          uint32_t             size_nb_inst_decod                 ,
-			  uint32_t             size_general_data                  ,
-			  uint32_t             size_store_queue_ptr               ,
-			  uint32_t             size_load_queue_ptr                ,
-			  uint32_t             size_general_register              ,
-			  uint32_t             size_special_register              ,
-			  Trat_scheme_t      * rat_scheme                         ,//[nb_front_end]
-			  Tpriority_t          priority                           ,
-			  Tload_balancing_t    load_balancing                     ,
-			  uint32_t             nb_rename_unit_select              ,
-                          uint32_t             nb_thread                          ,
-                          uint32_t          ** translate_num_context_to_num_thread,//[nb_front_end][nb_context]
-                          bool                 is_toplevel):
+  Parameters::Parameters (uint32_t               nb_front_end                       ,
+			  uint32_t             * nb_context                         ,//[nb_front_end]            
+			  uint32_t               nb_rename_unit                     ,                            
+			  uint32_t               size_queue                         ,                            
+			  uint32_t               nb_bank                            ,                            
+                          Tretire_ooo_scheme_t   retire_ooo_scheme                  ,                            
+			  uint32_t             * nb_inst_insert                     ,//[nb_rename_unit]          
+			  uint32_t             * nb_inst_retire                     ,//[nb_rename_unit]
+			  uint32_t               nb_inst_commit                     ,                            
+			  uint32_t               nb_inst_reexecute                  ,                            
+			  uint32_t               nb_inst_branch_complete            ,                            
+			  uint32_t            ** nb_branch_speculated               ,//[nb_front_end][nb_context]
+                          uint32_t               size_nb_inst_decod                 ,
+			  uint32_t               size_general_data                  ,
+			  uint32_t               size_store_queue_ptr               ,
+			  uint32_t               size_load_queue_ptr                ,
+			  uint32_t               size_general_register              ,
+			  uint32_t               size_special_register              ,
+			  Trat_scheme_t        * rat_scheme                         ,//[nb_rename_unit]
+                          std::vector<uint32_t>* link_front_end_with_rename_unit    ,//[nb_rename_unit]
+			  Tpriority_t            priority                           ,
+			  Tload_balancing_t      load_balancing                     ,
+			  uint32_t               nb_rename_unit_select              ,
+                          uint32_t               nb_thread                          ,
+                          uint32_t            ** translate_num_context_to_num_thread,//[nb_front_end][nb_context]
+                          bool                   is_toplevel):
     _nb_bank_access_commit (1              )
   {
@@ -63,4 +64,5 @@
     _nb_branch_speculated                = nb_branch_speculated               ;
     _rat_scheme                          = rat_scheme                         ;
+    _link_front_end_with_rename_unit     = link_front_end_with_rename_unit    ;
     _priority                            = priority                           ;
     _load_balancing                      = load_balancing                     ;
@@ -81,4 +83,12 @@
 
     _have_port_rename_unit_id = _size_rename_unit_id > 0;
+
+    ALLOC1(_front_end_rat_scheme, Trat_scheme_t,_nb_front_end);
+    // one rename unit per front_end
+    for (uint32_t i=0; i<_nb_rename_unit; ++i)
+      for (std::vector<uint32_t>::iterator it=_link_front_end_with_rename_unit[i].begin();
+           it != _link_front_end_with_rename_unit[i].end();
+           ++it)
+        _front_end_rat_scheme[*it] = _rat_scheme[i];
 
     ALLOC2(_array_size_depth,uint32_t,_nb_front_end,_nb_context [it1]);
@@ -138,6 +148,7 @@
     log_begin(Commit_unit,FUNCTION);
 
-    DELETE1(_have_thread     ,_nb_thread);
-    DELETE2(_array_size_depth,_nb_front_end,_nb_context [it1]);
+    DELETE1(_have_thread         ,_nb_thread);
+    DELETE2(_array_size_depth    ,_nb_front_end,_nb_context [it1]);
+    DELETE1(_front_end_rat_scheme,_nb_front_end);
 
     log_end(Commit_unit,FUNCTION);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,19 +1,0 @@
-Issue_queue
-1	1	*2	# nb_context              
-1	1	*2	# nb_front_end            
-1	1	*2	# nb_rename_unit          
-1	1	*2	# size_queue              
-0       1       +1      # queue_scheme
-1	1	*2	# nb_bank                 
-0	0	*2	# size_packet             
-32	32	*2	# size_general_data       
-2	2	*2	# size_special_data       
-5	5	*2	# size_general_register   
-2	2	*2	# size_special_register   
-1	1	*2	# size_store_queue_ptr    
-0	0	*2	# size_load_queue_ptr     
-1	1	*2	# nb_inst_rename         [0]               [nb_rename_unit]
-1	1	*2	# nb_inst_reexecute       
-1	1	*2	# nb_rename_unit_select   
-1	1	*2	# priority                
-1	1	*2	# load_balancing          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_mono_rename_unit.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_mono_rename_unit.cfg	(revision 144)
+++ 	(revision )
@@ -1,19 +1,0 @@
-Issue_queue
-4	4	*2	# nb_context              
-4	4	*2	# nb_front_end            
-1	1	*2	# nb_rename_unit          
-16	32	*2	# size_queue              
-0       1       +1      # queue_scheme
-4	16	*2	# nb_bank                 
-0	0	*2	# size_packet             
-32	32	*2	# size_general_data       
-2	2	*2	# size_special_data       
-5	5	*2	# size_general_register   
-2	2	*2	# size_special_register   
-1	1	*2	# size_store_queue_ptr    
-0	0	*2	# size_load_queue_ptr     
-1	4	*4	# nb_inst_rename         [0]               [nb_rename_unit]
-1	4	*4	# nb_inst_reexecute       
-1	1	*2	# nb_rename_unit_select   
-1	1	*2	# priority                
-1	1	*2	# load_balancing          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_multi_rename_unit.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_multi_rename_unit.cfg	(revision 144)
+++ 	(revision )
@@ -1,22 +1,0 @@
-Issue_queue
-4	4	*2	# nb_context              
-4	4	*2	# nb_front_end            
-4	4	*2	# nb_rename_unit          
-64	64	*2	# size_queue              
-0       1       +1      # queue_scheme
-4	16	*2	# nb_bank                 
-0	0	*2	# size_packet             
-32	32	*2	# size_general_data       
-2	2	*2	# size_special_data       
-5	5	*2	# size_general_register   
-2	2	*2	# size_special_register   
-1	1	*2	# size_store_queue_ptr    
-0	0	*2	# size_load_queue_ptr     
-4	4	*4	# nb_inst_rename         [0]               [nb_rename_unit]
-1	1	*4	# nb_inst_rename         [1]               [nb_rename_unit]
-2	2	*4	# nb_inst_rename         [2]               [nb_rename_unit]
-8	8	*4	# nb_inst_rename         [3]               [nb_rename_unit]
-4	4	*4	# nb_inst_reexecute       
-1	4	+1	# nb_rename_unit_select   
-1	1	*2	# priority                
-1	1	*2	# load_balancing          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,19 @@
+Issue_queue
+1	1	*2	# nb_context              
+1	1	*2	# nb_front_end            
+1	1	*2	# nb_rename_unit          
+1	1	*2	# size_queue              
+0       1       +1      # queue_scheme
+1	1	*2	# nb_bank                 
+0	0	*2	# size_packet             
+32	32	*2	# size_general_data       
+2	2	*2	# size_special_data       
+5	5	*2	# size_general_register   
+2	2	*2	# size_special_register   
+1	1	*2	# size_store_queue_ptr    
+0	0	*2	# size_load_queue_ptr     
+1	1	*2	# nb_inst_rename         [0]               [nb_rename_unit]
+1	1	*2	# nb_inst_reexecute       
+1	1	*2	# nb_rename_unit_select   
+1	1	*2	# priority                
+1	1	*2	# load_balancing          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_mono_rename_unit.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_mono_rename_unit.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_mono_rename_unit.gen	(revision 145)
@@ -0,0 +1,19 @@
+Issue_queue
+4	4	*2	# nb_context              
+4	4	*2	# nb_front_end            
+1	1	*2	# nb_rename_unit          
+16	32	*2	# size_queue              
+0       1       +1      # queue_scheme
+4	16	*2	# nb_bank                 
+0	0	*2	# size_packet             
+32	32	*2	# size_general_data       
+2	2	*2	# size_special_data       
+5	5	*2	# size_general_register   
+2	2	*2	# size_special_register   
+1	1	*2	# size_store_queue_ptr    
+0	0	*2	# size_load_queue_ptr     
+1	4	*4	# nb_inst_rename         [0]               [nb_rename_unit]
+1	4	*4	# nb_inst_reexecute       
+1	1	*2	# nb_rename_unit_select   
+1	1	*2	# priority                
+1	1	*2	# load_balancing          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_multi_rename_unit.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_multi_rename_unit.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_multi_rename_unit.gen	(revision 145)
@@ -0,0 +1,22 @@
+Issue_queue
+4	4	*2	# nb_context              
+4	4	*2	# nb_front_end            
+4	4	*2	# nb_rename_unit          
+64	64	*2	# size_queue              
+0       1       +1      # queue_scheme
+4	16	*2	# nb_bank                 
+0	0	*2	# size_packet             
+32	32	*2	# size_general_data       
+2	2	*2	# size_special_data       
+5	5	*2	# size_general_register   
+2	2	*2	# size_special_register   
+1	1	*2	# size_store_queue_ptr    
+0	0	*2	# size_load_queue_ptr     
+4	4	*4	# nb_inst_rename         [0]               [nb_rename_unit]
+1	1	*4	# nb_inst_rename         [1]               [nb_rename_unit]
+2	2	*4	# nb_inst_rename         [2]               [nb_rename_unit]
+8	8	*4	# nb_inst_rename         [3]               [nb_rename_unit]
+4	4	*4	# nb_inst_reexecute       
+1	4	+1	# nb_rename_unit_select   
+1	1	*2	# priority                
+1	1	*2	# load_balancing          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_1.cfg	(revision 144)
+++ 	(revision )
@@ -1,15 +1,0 @@
-OOO_Engine_Glue
-1	1	*2	# nb_front_end                    
-1	1	*2	# nb_context                      [0] [nb_front_end]
-1	1	*2	# nb_rename_unit                     
-4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
-4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
-4	4	*2	# nb_inst_retire                  [0] [nb_rename_unit]
-32	32	*2	# size_general_data                  
-2	2	*2	# size_special_data                  
-0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
-2	2	*2	# size_packet_id                    
-8	8	*2	# size_general_register             
-4	4	*2	# size_special_register             
-4	4	*2	# size_store_queue_ptr              
-4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_4.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_4.cfg	(revision 144)
+++ 	(revision )
@@ -1,21 +1,0 @@
-OOO_Engine_Glue
-1	1	*2	# nb_front_end                    
-1	1	*2	# nb_context                      [0] [nb_front_end]
-4	4	*2	# nb_rename_unit                     
-4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
-4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
-2	2	*2	# nb_inst_insert                  [1] [nb_rename_unit]
-1	1	*2	# nb_inst_insert                  [2] [nb_rename_unit]
-4	4	*2	# nb_inst_insert                  [3] [nb_rename_unit]
-1	1	*2	# nb_inst_retire                  [0] [nb_rename_unit]
-8	8	*2	# nb_inst_retire                  [1] [nb_rename_unit]
-2	2	*2	# nb_inst_retire                  [2] [nb_rename_unit]
-4	4	*2	# nb_inst_retire                  [3] [nb_rename_unit]
-32	32	*2	# size_general_data                  
-2	2	*2	# size_special_data                  
-0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
-2	2	*2	# size_packet_id                    
-8	8	*2	# size_general_register             
-4	4	*2	# size_special_register             
-4	4	*2	# size_store_queue_ptr              
-4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_1.cfg	(revision 144)
+++ 	(revision )
@@ -1,24 +1,0 @@
-OOO_Engine_Glue
-4	4	*2	# nb_front_end                    
-4	4	*2	# nb_context                      [0] [nb_front_end]
-1	1	*2	# nb_context                      [1] [nb_front_end]
-2	2	*2	# nb_context                      [2] [nb_front_end]
-8	8	*2	# nb_context                      [3] [nb_front_end]
-1	1	*2	# nb_rename_unit                     
-4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
-2	2	*2	# nb_inst_decod                   [1] [nb_front_end]
-1	1	*2	# nb_inst_decod                   [2] [nb_front_end]
-4	4	*2	# nb_inst_decod                   [3] [nb_front_end]
-4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
-4	4	*2	# nb_inst_retire                  [0] [nb_rename_unit]
-32	32	*2	# size_general_data                  
-2	2	*2	# size_special_data                  
-0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
-0	0	*2	# link_rename_unit_with_front_end [1] [nb_front_end]
-0	0	*2	# link_rename_unit_with_front_end [2] [nb_front_end]
-0	0	*2	# link_rename_unit_with_front_end [3] [nb_front_end]
-2	2	*2	# size_packet_id                    
-8	8	*2	# size_general_register             
-4	4	*2	# size_special_register             
-4	4	*2	# size_store_queue_ptr              
-4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_4.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_4.cfg	(revision 144)
+++ 	(revision )
@@ -1,30 +1,0 @@
-OOO_Engine_Glue
-4	4	*2	# nb_front_end                    
-4	4	*2	# nb_context                      [0] [nb_front_end]
-1	1	*2	# nb_context                      [1] [nb_front_end]
-2	2	*2	# nb_context                      [2] [nb_front_end]
-8	8	*2	# nb_context                      [3] [nb_front_end]
-4	4	*2	# nb_rename_unit                     
-4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
-2	2	*2	# nb_inst_decod                   [1] [nb_front_end]
-1	1	*2	# nb_inst_decod                   [2] [nb_front_end]
-4	4	*2	# nb_inst_decod                   [3] [nb_front_end]
-4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
-2	2	*2	# nb_inst_insert                  [1] [nb_rename_unit]
-1	1	*2	# nb_inst_insert                  [2] [nb_rename_unit]
-4	4	*2	# nb_inst_insert                  [3] [nb_rename_unit]
-1	1	*2	# nb_inst_retire                  [0] [nb_rename_unit]
-8	8	*2	# nb_inst_retire                  [1] [nb_rename_unit]
-2	2	*2	# nb_inst_retire                  [2] [nb_rename_unit]
-4	4	*2	# nb_inst_retire                  [3] [nb_rename_unit]
-32	32	*2	# size_general_data                  
-2	2	*2	# size_special_data                  
-0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
-3	3	*2	# link_rename_unit_with_front_end [1] [nb_front_end]
-1	1	*2	# link_rename_unit_with_front_end [2] [nb_front_end]
-2	2	*2	# link_rename_unit_with_front_end [3] [nb_front_end]
-2	2	*2	# size_packet_id                    
-8	8	*2	# size_general_register             
-4	4	*2	# size_special_register             
-4	4	*2	# size_store_queue_ptr              
-4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,15 +1,0 @@
-OOO_Engine_Glue
-1	1	*2	# nb_front_end                    
-1	1	*2	# nb_context                      [0] [nb_front_end]
-1	1	*2	# nb_rename_unit                     
-1	1	*2	# nb_inst_decod                   [0] [nb_front_end]
-1	1	*2	# nb_inst_insert                  [0] [nb_rename_unit]
-1	1	*2	# nb_inst_retire                  [0] [nb_rename_unit]
-32	32	*2	# size_general_data                  
-2	2	*2	# size_special_data                  
-0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
-0	0	*2	# size_packet_id                    
-6	6	*2	# size_general_register             
-2	2	*2	# size_special_register             
-1	1	*2	# size_store_queue_ptr              
-0	0	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_1-rename_unit_1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_1-rename_unit_1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_1-rename_unit_1.gen	(revision 145)
@@ -0,0 +1,15 @@
+OOO_Engine_Glue
+1	1	*2	# nb_front_end                    
+1	1	*2	# nb_context                      [0] [nb_front_end]
+1	1	*2	# nb_rename_unit                     
+4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
+4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
+4	4	*2	# nb_inst_retire                  [0] [nb_rename_unit]
+32	32	*2	# size_general_data                  
+2	2	*2	# size_special_data                  
+0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
+2	2	*2	# size_packet_id                    
+8	8	*2	# size_general_register             
+4	4	*2	# size_special_register             
+4	4	*2	# size_store_queue_ptr              
+4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_1-rename_unit_4.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_1-rename_unit_4.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_1-rename_unit_4.gen	(revision 145)
@@ -0,0 +1,21 @@
+OOO_Engine_Glue
+1	1	*2	# nb_front_end                    
+1	1	*2	# nb_context                      [0] [nb_front_end]
+4	4	*2	# nb_rename_unit                     
+4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
+4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
+2	2	*2	# nb_inst_insert                  [1] [nb_rename_unit]
+1	1	*2	# nb_inst_insert                  [2] [nb_rename_unit]
+4	4	*2	# nb_inst_insert                  [3] [nb_rename_unit]
+1	1	*2	# nb_inst_retire                  [0] [nb_rename_unit]
+8	8	*2	# nb_inst_retire                  [1] [nb_rename_unit]
+2	2	*2	# nb_inst_retire                  [2] [nb_rename_unit]
+4	4	*2	# nb_inst_retire                  [3] [nb_rename_unit]
+32	32	*2	# size_general_data                  
+2	2	*2	# size_special_data                  
+0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
+2	2	*2	# size_packet_id                    
+8	8	*2	# size_general_register             
+4	4	*2	# size_special_register             
+4	4	*2	# size_store_queue_ptr              
+4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_4-rename_unit_1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_4-rename_unit_1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_4-rename_unit_1.gen	(revision 145)
@@ -0,0 +1,24 @@
+OOO_Engine_Glue
+4	4	*2	# nb_front_end                    
+4	4	*2	# nb_context                      [0] [nb_front_end]
+1	1	*2	# nb_context                      [1] [nb_front_end]
+2	2	*2	# nb_context                      [2] [nb_front_end]
+8	8	*2	# nb_context                      [3] [nb_front_end]
+1	1	*2	# nb_rename_unit                     
+4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
+2	2	*2	# nb_inst_decod                   [1] [nb_front_end]
+1	1	*2	# nb_inst_decod                   [2] [nb_front_end]
+4	4	*2	# nb_inst_decod                   [3] [nb_front_end]
+4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
+4	4	*2	# nb_inst_retire                  [0] [nb_rename_unit]
+32	32	*2	# size_general_data                  
+2	2	*2	# size_special_data                  
+0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
+0	0	*2	# link_rename_unit_with_front_end [1] [nb_front_end]
+0	0	*2	# link_rename_unit_with_front_end [2] [nb_front_end]
+0	0	*2	# link_rename_unit_with_front_end [3] [nb_front_end]
+2	2	*2	# size_packet_id                    
+8	8	*2	# size_general_register             
+4	4	*2	# size_special_register             
+4	4	*2	# size_store_queue_ptr              
+4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_4-rename_unit_4.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_4-rename_unit_4.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_4-rename_unit_4.gen	(revision 145)
@@ -0,0 +1,30 @@
+OOO_Engine_Glue
+4	4	*2	# nb_front_end                    
+4	4	*2	# nb_context                      [0] [nb_front_end]
+1	1	*2	# nb_context                      [1] [nb_front_end]
+2	2	*2	# nb_context                      [2] [nb_front_end]
+8	8	*2	# nb_context                      [3] [nb_front_end]
+4	4	*2	# nb_rename_unit                     
+4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
+2	2	*2	# nb_inst_decod                   [1] [nb_front_end]
+1	1	*2	# nb_inst_decod                   [2] [nb_front_end]
+4	4	*2	# nb_inst_decod                   [3] [nb_front_end]
+4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
+2	2	*2	# nb_inst_insert                  [1] [nb_rename_unit]
+1	1	*2	# nb_inst_insert                  [2] [nb_rename_unit]
+4	4	*2	# nb_inst_insert                  [3] [nb_rename_unit]
+1	1	*2	# nb_inst_retire                  [0] [nb_rename_unit]
+8	8	*2	# nb_inst_retire                  [1] [nb_rename_unit]
+2	2	*2	# nb_inst_retire                  [2] [nb_rename_unit]
+4	4	*2	# nb_inst_retire                  [3] [nb_rename_unit]
+32	32	*2	# size_general_data                  
+2	2	*2	# size_special_data                  
+0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
+3	3	*2	# link_rename_unit_with_front_end [1] [nb_front_end]
+1	1	*2	# link_rename_unit_with_front_end [2] [nb_front_end]
+2	2	*2	# link_rename_unit_with_front_end [3] [nb_front_end]
+2	2	*2	# size_packet_id                    
+8	8	*2	# size_general_register             
+4	4	*2	# size_special_register             
+4	4	*2	# size_store_queue_ptr              
+4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,15 @@
+OOO_Engine_Glue
+1	1	*2	# nb_front_end                    
+1	1	*2	# nb_context                      [0] [nb_front_end]
+1	1	*2	# nb_rename_unit                     
+1	1	*2	# nb_inst_decod                   [0] [nb_front_end]
+1	1	*2	# nb_inst_insert                  [0] [nb_rename_unit]
+1	1	*2	# nb_inst_retire                  [0] [nb_rename_unit]
+32	32	*2	# size_general_data                  
+2	2	*2	# size_special_data                  
+0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
+0	0	*2	# size_packet_id                    
+6	6	*2	# size_general_register             
+2	2	*2	# size_special_register             
+1	1	*2	# size_store_queue_ptr              
+0	0	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_1.cfg	(revision 144)
+++ 	(revision )
@@ -1,18 +1,0 @@
-Reexecute_unit
-0	0	+1	# size_context_id         
-0	0	+1	# size_front_end_id       
-6	6	+1	# size_packet_id          
-4	4	+1	# size_queue              
-1	1	+1	# nb_execute_loop         
-4	4	+1	# nb_inst_execute          [0] [nb_execute_loop]
-2	2	+1	# nb_inst_commit          
-2	2	+1	# nb_inst_reexecute       
-1	1	+1	# nb_execute_loop_select  
-0	1	+1	# priority                
-0	1	+1	# load_balancing          
-5	5	+1	# size_general_register_id
-1	1	+1	# size_special_register_id
-32	32	+1	# size_general_data       
-5	5	+1	# size_special_data       
-2	2	+1	# size_store_queue_ptr    
-2	2	+1	# size_load_queue_ptr     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_4.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_4.cfg	(revision 144)
+++ 	(revision )
@@ -1,21 +1,0 @@
-Reexecute_unit
-0	0	+1	# size_context_id         
-0	0	+1	# size_front_end_id       
-6	6	+1	# size_packet_id          
-8	8	+1	# size_queue              
-4	4	+1	# nb_execute_loop         
-4	4	+1	# nb_inst_execute          [0] [nb_execute_loop]
-1	1	+1	# nb_inst_execute          [1] [nb_execute_loop]
-3	3	+1	# nb_inst_execute          [2] [nb_execute_loop]
-8	8	+1	# nb_inst_execute          [3] [nb_execute_loop]
-4	4	+1	# nb_inst_commit          
-3 	3	+1	# nb_inst_reexecute       
-1	4	+1	# nb_execute_loop_select  
-0	1	+1	# priority                
-0	1	+1	# load_balancing          
-5	5	+1	# size_general_register_id
-1	1	+1	# size_special_register_id
-32	32	+1	# size_general_data       
-5	5	+1	# size_special_data       
-2	2	+1	# size_store_queue_ptr    
-2	2	+1	# size_load_queue_ptr     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,18 +1,0 @@
-Reexecute_unit
-0	0	+1	# size_context_id         
-0	0	+1	# size_front_end_id       
-0	0	+1	# size_packet_id          
-1	1	+1	# size_queue              
-1	1	+1	# nb_execute_loop         
-1	1	+1	# nb_inst_execute          [0] [nb_execute_loop]
-1	1	+1	# nb_inst_commit          
-1	1	+1	# nb_inst_reexecute       
-1	1	+1	# nb_execute_loop_select  
-0	1	+1	# priority                
-0	1	+1	# load_balancing          
-5	5	+1	# size_general_register_id
-1	1	+1	# size_special_register_id
-32	32	+1	# size_general_data       
-5	5	+1	# size_special_data       
-1	1	+1	# size_store_queue_ptr    
-0	0	+1	# size_load_queue_ptr     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-execute_loop_1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-execute_loop_1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-execute_loop_1.gen	(revision 145)
@@ -0,0 +1,18 @@
+Reexecute_unit
+0	0	+1	# size_context_id         
+0	0	+1	# size_front_end_id       
+6	6	+1	# size_packet_id          
+4	4	+1	# size_queue              
+1	1	+1	# nb_execute_loop         
+4	4	+1	# nb_inst_execute          [0] [nb_execute_loop]
+2	2	+1	# nb_inst_commit          
+2	2	+1	# nb_inst_reexecute       
+1	1	+1	# nb_execute_loop_select  
+0	1	+1	# priority                
+0	1	+1	# load_balancing          
+5	5	+1	# size_general_register_id
+1	1	+1	# size_special_register_id
+32	32	+1	# size_general_data       
+5	5	+1	# size_special_data       
+2	2	+1	# size_store_queue_ptr    
+2	2	+1	# size_load_queue_ptr     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-execute_loop_4.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-execute_loop_4.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-execute_loop_4.gen	(revision 145)
@@ -0,0 +1,21 @@
+Reexecute_unit
+0	0	+1	# size_context_id         
+0	0	+1	# size_front_end_id       
+6	6	+1	# size_packet_id          
+8	8	+1	# size_queue              
+4	4	+1	# nb_execute_loop         
+4	4	+1	# nb_inst_execute          [0] [nb_execute_loop]
+1	1	+1	# nb_inst_execute          [1] [nb_execute_loop]
+3	3	+1	# nb_inst_execute          [2] [nb_execute_loop]
+8	8	+1	# nb_inst_execute          [3] [nb_execute_loop]
+4	4	+1	# nb_inst_commit          
+3 	3	+1	# nb_inst_reexecute       
+1	4	+1	# nb_execute_loop_select  
+0	1	+1	# priority                
+0	1	+1	# load_balancing          
+5	5	+1	# size_general_register_id
+1	1	+1	# size_special_register_id
+32	32	+1	# size_general_data       
+5	5	+1	# size_special_data       
+2	2	+1	# size_store_queue_ptr    
+2	2	+1	# size_load_queue_ptr     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,18 @@
+Reexecute_unit
+0	0	+1	# size_context_id         
+0	0	+1	# size_front_end_id       
+0	0	+1	# size_packet_id          
+1	1	+1	# size_queue              
+1	1	+1	# nb_execute_loop         
+1	1	+1	# nb_inst_execute          [0] [nb_execute_loop]
+1	1	+1	# nb_inst_commit          
+1	1	+1	# nb_inst_reexecute       
+1	1	+1	# nb_execute_loop_select  
+0	1	+1	# priority                
+0	1	+1	# load_balancing          
+5	5	+1	# size_general_register_id
+1	1	+1	# size_special_register_id
+32	32	+1	# size_general_data       
+5	5	+1	# size_special_data       
+1	1	+1	# size_store_queue_ptr    
+0	0	+1	# size_load_queue_ptr     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Load_Store_pointer_unit
-1	1	*2	# nb_front_end                            
-1	1	*2	# nb_context                       [0]    [nb_front_end]
-1	1	*2	# nb_load_store_queue              
-2	4	*2	# size_store_queue                 [0]    [nb_load_store_queue]
-1	4	*2	# size_load_queue                  [0]    [nb_load_store_queue]
-1	4	*4	# nb_inst_memory                   [0]    [nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
-1	4	*4	# nb_inst_insert
-1	4	*4	# nb_inst_retire
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,10 @@
+Load_Store_pointer_unit
+1	1	*2	# nb_front_end                            
+1	1	*2	# nb_context                       [0]    [nb_front_end]
+1	1	*2	# nb_load_store_queue              
+2	4	*2	# size_store_queue                 [0]    [nb_load_store_queue]
+1	4	*2	# size_load_queue                  [0]    [nb_load_store_queue]
+1	4	*4	# nb_inst_memory                   [0]    [nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
+1	4	*4	# nb_inst_insert
+1	4	*4	# nb_inst_retire
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h	(revision 145)
@@ -112,5 +112,5 @@
   private   : uint32_t                       * internal_RETIRE_LSQ          ; // [nb_inst_retire]
   private   : Tlsq_ptr_t                     * internal_RETIRE_PTR          ; // [nb_inst_retire]
-  private   : Tcontrol_t                    ** internal_RETIRE_EVENT_ACK    ;//[nb_front_end][nb_context]
+  private   : Tcontrol_t                    ** internal_RETIRE_EVENT_ACK    ; //[nb_front_end][nb_context]
 
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp	(revision 145)
@@ -27,7 +27,6 @@
     if (PORT_READ(in_NRESET))
       {
-    // TODO : limité à nb_inst_memory le nombre d'accès par lsq !!!
-
-    uint32_t   nb_use_lsq            [_param->_nb_load_store_queue];
+    // Limit at nb_inst_memory access per load_store_queue
+    // uint32_t   nb_use_lsq            [_param->_nb_load_store_queue];
     Tlsq_ptr_t STORE_QUEUE_PTR_WRITE [_param->_nb_load_store_queue];
     bool       STORE_QUEUE_USE       [_param->_nb_load_store_queue][_param->_max_size_store_queue];
@@ -38,5 +37,5 @@
     for (uint32_t i=0; i<_param->_nb_load_store_queue; i++)
       {
-        nb_use_lsq            [i] = _param->_nb_inst_memory[i];
+        // nb_use_lsq            [i] = _param->_nb_inst_memory[i];
 
         STORE_QUEUE_PTR_WRITE [i] = reg_STORE_QUEUE_PTR_WRITE [i];
@@ -82,7 +81,7 @@
                 // Test if a previous instruction use the same lsq
                 // Authorize once memory access by load store unit
-                if (nb_use_lsq [lsq] > 0)
+                // if (nb_use_lsq [lsq] > 0)
                   {
-                    nb_use_lsq [lsq] --;
+                    // nb_use_lsq [lsq] --;
                     
                     uint32_t   ptr;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-Dependency_checking_unit
-1	4	*2	# nb_front_end       
-1	4	*2	# max_nb_context     
-64	64	*2	# nb_general_register
-16	16	*2	# nb_special_register
-1	8	*2	# nb_inst_insert     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,6 @@
+Dependency_checking_unit
+1	4	*2	# nb_front_end       
+1	4	*2	# max_nb_context     
+64	64	*2	# nb_general_register
+16	16	*2	# nb_special_register
+1	8	*2	# nb_inst_insert     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/config_mono_pop.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/config_mono_pop.cfg	(revision 144)
+++ 	(revision )
@@ -1,8 +1,0 @@
-Free_List_unit
-1	1	*2	# nb_thread          
-64	64	*2	# nb_general_register
-16	16	*2	# nb_special_register
-1	4	*2	# nb_bank            
-1	1	*2	# nb_pop             
-1	4	*2	# nb_push            
-0	1	+1  	# priority           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/config_multi_pop.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/config_multi_pop.cfg	(revision 144)
+++ 	(revision )
@@ -1,8 +1,0 @@
-Free_List_unit
-1	1	*2	# nb_thread          
-64	64	*2	# nb_general_register
-16	16	*2	# nb_special_register
-4	8	*2	# nb_bank            
-1	4	*2	# nb_pop             
-2	2	*2	# nb_push            
-0	1	+1  	# priority           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/configuration/config_mono_pop.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/configuration/config_mono_pop.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/configuration/config_mono_pop.gen	(revision 145)
@@ -0,0 +1,8 @@
+Free_List_unit
+1	1	*2	# nb_thread          
+64	64	*2	# nb_general_register
+16	16	*2	# nb_special_register
+1	4	*2	# nb_bank            
+1	1	*2	# nb_pop             
+1	4	*2	# nb_push            
+0	1	+1  	# priority           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/configuration/config_multi_pop.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/configuration/config_multi_pop.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/configuration/config_multi_pop.gen	(revision 145)
@@ -0,0 +1,8 @@
+Free_List_unit
+1	1	*2	# nb_thread          
+64	64	*2	# nb_general_register
+16	16	*2	# nb_special_register
+4	8	*2	# nb_bank            
+1	4	*2	# nb_pop             
+2	2	*2	# nb_push            
+0	1	+1  	# priority           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/config_mono_front_end.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/config_mono_front_end.cfg	(revision 144)
+++ 	(revision )
@@ -1,7 +1,0 @@
-Register_Address_Translation_unit
-1	1	+1	# nb_front_end          
-1	1	+1	# nb_context            [0] [nb_front_end]
-4 	4 	*2	# nb_general_register   
-4 	4 	*2	# nb_special_register   
-4	4	+1	# nb_inst_insert
-4	4	+1	# nb_inst_retire
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/config_multi_front_end.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/config_multi_front_end.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Register_Address_Translation_unit
-4	4	+1	# nb_front_end          
-1	1	+1	# nb_context            [0] [nb_front_end]
-2	2	+1	# nb_context            [1] [nb_front_end]
-1	1	+1	# nb_context            [2] [nb_front_end]
-4	4	+1	# nb_context            [3] [nb_front_end]
-64	64	*2	# nb_general_register   
-16	16	*2	# nb_special_register   
-4	4	+1	# nb_inst_insert
-4	4	+1	# nb_inst_retire
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/configuration/config_mono_front_end.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/configuration/config_mono_front_end.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/configuration/config_mono_front_end.gen	(revision 145)
@@ -0,0 +1,7 @@
+Register_Address_Translation_unit
+1	1	+1	# nb_front_end          
+1	1	+1	# nb_context            [0] [nb_front_end]
+4 	4 	*2	# nb_general_register   
+4 	4 	*2	# nb_special_register   
+4	4	+1	# nb_inst_insert
+4	4	+1	# nb_inst_retire
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/configuration/config_multi_front_end.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/configuration/config_multi_front_end.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/configuration/config_multi_front_end.gen	(revision 145)
@@ -0,0 +1,10 @@
+Register_Address_Translation_unit
+4	4	+1	# nb_front_end          
+1	1	+1	# nb_context            [0] [nb_front_end]
+2	2	+1	# nb_context            [1] [nb_front_end]
+1	1	+1	# nb_context            [2] [nb_front_end]
+4	4	+1	# nb_context            [3] [nb_front_end]
+64	64	*2	# nb_general_register   
+16	16	*2	# nb_special_register   
+4	4	+1	# nb_inst_insert
+4	4	+1	# nb_inst_retire
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Parameters.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Parameters.h	(revision 145)
@@ -36,4 +36,5 @@
     
   public : uint32_t         _max_nb_context        ;
+  public : uint32_t         _max_nb_branch_speculated;
 //public : uint32_t         _size_front_end_id     ;
 //public : uint32_t         _size_context_id       ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h	(revision 145)
@@ -107,28 +107,32 @@
 
     // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-  public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_VAL            ;//[nb_front_end][nb_context]
-  public    : SC_OUT(Tcontrol_t        )  *** out_RETIRE_EVENT_ACK            ;//[nb_front_end][nb_context]
-  public    : SC_IN (Tevent_state_t    )  ***  in_RETIRE_EVENT_STATE          ;//[nb_front_end][nb_context]
-  public    : SC_IN (Tevent_type_t     )  ***  in_RETIRE_EVENT_TYPE           ;//[nb_front_end][nb_context]
-  public    : SC_IN (Tdepth_t          )  ***  in_RETIRE_EVENT_DEPTH          ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_VAL         ;//[nb_front_end][nb_context]
+  public    : SC_OUT(Tcontrol_t        )  *** out_RETIRE_EVENT_ACK         ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tevent_state_t    )  ***  in_RETIRE_EVENT_STATE       ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tevent_type_t     )  ***  in_RETIRE_EVENT_TYPE        ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tdepth_t          )  ***  in_RETIRE_EVENT_DEPTH       ;//[nb_front_end][nb_context]
+
+    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MIN                   ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MAX                   ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_DEPTH_FULL                  ;//[nb_front_end][nb_context]
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-  private   : Tgeneral_address_t          *** rat_gpr_not_speculative;      //[nb_front_end][nb_context]                      [nb_general_register_logic]
-  private   : Tgeneral_address_t          *** rat_gpr_speculative;          //[nb_front_end][nb_context]                      [nb_general_register_logic]
-  private   : bool                        *** rat_gpr_speculative_valid;    //[nb_front_end][nb_context]                      [nb_general_register_logic]
-  private   : Tgeneral_address_t         **** rat_gpr_save;                 //[nb_front_end][nb_context][nb_branch_speculated][nb_general_register_logic]
-
-  private   : Tspecial_address_t          *** rat_spr_not_speculative;      //[nb_front_end][nb_context]                      [nb_special_register_logic]
-  private   : Tspecial_address_t          *** rat_spr_speculative;          //[nb_front_end][nb_context]                      [nb_special_register_logic]
-  private   : bool                        *** rat_spr_speculative_valid;    //[nb_front_end][nb_context]                      [nb_special_register_logic]
-  private   : Tspecial_address_t         **** rat_spr_save;                 //[nb_front_end][nb_context][nb_branch_speculated][nb_special_register_logic]
-
-  private   : Tdepth_t                     ** rat_depth;                    //[nb_front_end][nb_context]
+                                                                            //                                                                            NO ONE DEPTH
+  private   : Tgeneral_address_t          *** RAT_GPR_NOT_SPECULATIVE;      //[nb_front_end][nb_context]                      [nb_general_register_logic] X  X   X
+  private   : Tgeneral_address_t         **** RAT_GPR_SPECULATIVE;          //[nb_front_end][nb_context][nb_branch_speculated][nb_general_register_logic]    X   X
+  private   : bool                       **** RAT_GPR_SPECULATIVE_VALID;    //[nb_front_end][nb_context][nb_branch_speculated][nb_general_register_logic]    X   X
+
+  private   : Tspecial_address_t          *** RAT_SPR_NOT_SPECULATIVE;      //[nb_front_end][nb_context]                      [nb_special_register_logic] X  X   X
+  private   : Tspecial_address_t         **** RAT_SPR_SPECULATIVE;          //[nb_front_end][nb_context][nb_branch_speculated][nb_special_register_logic]    X   X
+  private   : bool                       **** RAT_SPR_SPECULATIVE_VALID;    //[nb_front_end][nb_context][nb_branch_speculated][nb_special_register_logic]    X   X
+
+  private   : bool                        *** reg_RAT_USE;                  //[nb_front_end][nb_context][nb_branch_speculated]                                   X
+  private   : bool                         ** reg_SAVE_RAT;                 //[nb_front_end][nb_context]                                                         X
 
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   private   : Tcontrol_t                    * internal_RENAME_ACK;          //[nb_inst_insert]
-  private   : Tcontrol_t                    * internal_RENAME_SAVE;         //[nb_inst_insert]
   private   : Tcontrol_t                    * internal_INSERT_ACK;          //[nb_inst_insert]
   private   : Tcontrol_t                    * internal_RETIRE_ACK;          //[nb_inst_retire]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Parameters.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Parameters.cpp	(revision 145)
@@ -41,5 +41,6 @@
     _nb_branch_speculated   = nb_branch_speculated;
 
-    _max_nb_context         = max<uint32_t>(_nb_context, _nb_front_end);
+    _max_nb_context          = max<uint32_t>(_nb_context, _nb_front_end);
+    _max_nb_branch_speculated= max<uint32_t>(_nb_branch_speculated, _nb_front_end, _nb_context);
 
     test();
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp	(revision 145)
@@ -160,6 +160,12 @@
         for (uint32_t i=0; i<_param->_nb_front_end; ++i)
           for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
-            sensitive << (*(in_RETIRE_EVENT_VAL   [i][j]))
-                      << (*(in_RETIRE_EVENT_STATE [i][j]));
+            {
+              sensitive << (*(in_RETIRE_EVENT_VAL   [i][j]))
+                        << (*(in_RETIRE_EVENT_STATE [i][j]))
+                        << (*(in_DEPTH_FULL         [i][j]));
+              if (_param->_have_port_depth)
+              sensitive << (*(in_DEPTH_MIN          [i][j]))
+                        << (*(in_DEPTH_MAX          [i][j]));
+            }
 
 # ifdef SYSTEMCASS_SPECIFIC
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp	(revision 145)
@@ -131,14 +131,24 @@
     }
 
+    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);
+
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN                    ,"MIN"               ,Tdepth_t         ,_param->_size_depth       ,_param->_nb_front_end,_param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX                    ,"MAX"               ,Tdepth_t         ,_param->_size_depth       ,_param->_nb_front_end,_param->_nb_context[it1]); 
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL                   ,"FULL"              ,Tcontrol_t       ,1                         ,_param->_nb_front_end,_param->_nb_context[it1]); 
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]);
+    }
+
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
     ALLOC1(internal_RENAME_ACK       ,Tcontrol_t,_param->_nb_inst_insert);
-    ALLOC1(internal_RENAME_SAVE      ,Tcontrol_t,_param->_nb_inst_insert);
     ALLOC1(internal_INSERT_ACK       ,Tcontrol_t,_param->_nb_inst_insert);
     ALLOC1(internal_RETIRE_ACK       ,Tcontrol_t,_param->_nb_inst_retire);
     ALLOC2(internal_RETIRE_EVENT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]);
 
-    ALLOC3(rat_gpr_speculative      ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-    ALLOC3(rat_spr_speculative      ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+    ALLOC3(RAT_GPR_NOT_SPECULATIVE  ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
+    ALLOC3(RAT_SPR_NOT_SPECULATIVE  ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
 
     switch(_param->_rat_scheme)
@@ -150,9 +160,9 @@
       case RAT_ONE_SAVE   :
         {
-          ALLOC3(rat_gpr_not_speculative  ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-          ALLOC3(rat_gpr_speculative_valid,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-
-          ALLOC3(rat_spr_not_speculative  ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
-          ALLOC3(rat_spr_speculative_valid,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+          ALLOC4(RAT_GPR_SPECULATIVE      ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic);
+          ALLOC4(RAT_SPR_SPECULATIVE      ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic);
+
+          ALLOC4(RAT_GPR_SPECULATIVE_VALID,bool              ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic);
+          ALLOC4(RAT_SPR_SPECULATIVE_VALID,bool              ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic);
           
           break;
@@ -160,8 +170,13 @@
       case RAT_DEPTH_SAVE :
         {
-          ALLOC4(rat_gpr_save             ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
-          ALLOC4(rat_spr_save             ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
-          ALLOC2(rat_depth                ,Tdepth_t          ,_param->_nb_front_end,_param->_nb_context[it1]);
-    
+          ALLOC4(RAT_GPR_SPECULATIVE      ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
+          ALLOC4(RAT_SPR_SPECULATIVE      ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
+
+          ALLOC4(RAT_GPR_SPECULATIVE_VALID,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
+          ALLOC4(RAT_SPR_SPECULATIVE_VALID,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
+    
+          ALLOC3(reg_RAT_USE              ,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2]);
+          ALLOC2(reg_SAVE_RAT             ,bool              ,_param->_nb_front_end,_param->_nb_context[it1]);
+
           break;
         }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp	(revision 145)
@@ -76,13 +76,15 @@
         DELETE2_SIGNAL_COND( in_RETIRE_EVENT_DEPTH          ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth     ,_param->_rat_scheme == RAT_DEPTH_SAVE);
 
+        DELETE2_SIGNAL     ( in_DEPTH_MIN                   ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth);
+        DELETE2_SIGNAL     ( in_DEPTH_MAX                   ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth);
+        DELETE2_SIGNAL     ( in_DEPTH_FULL                  ,_param->_nb_front_end,_param->_nb_context[it1],1                  );
+
         DELETE1(internal_RENAME_ACK                    ,_param->_nb_inst_insert);
-        DELETE1(internal_RENAME_SAVE                   ,_param->_nb_inst_insert);
-        DELETE1(internal_INSERT_ACK                    ,_param->_nb_inst_insert);
         DELETE1(internal_RETIRE_ACK                    ,_param->_nb_inst_retire);
         DELETE2(internal_RETIRE_EVENT_ACK              ,_param->_nb_front_end,_param->_nb_context[it1]);
 
-        DELETE3(rat_gpr_speculative          ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-        DELETE3(rat_spr_speculative          ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
-
+        DELETE3(RAT_GPR_NOT_SPECULATIVE      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
+        DELETE3(RAT_SPR_NOT_SPECULATIVE      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+        
         switch(_param->_rat_scheme)
           {
@@ -93,9 +95,9 @@
           case RAT_ONE_SAVE   :
             {
-              DELETE3(rat_gpr_not_speculative      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-              DELETE3(rat_gpr_speculative_valid    ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-              
-              DELETE3(rat_spr_not_speculative      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
-              DELETE3(rat_spr_speculative_valid    ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+              DELETE4(RAT_GPR_SPECULATIVE          ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic);
+              DELETE4(RAT_SPR_SPECULATIVE          ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic);
+
+              DELETE4(RAT_GPR_SPECULATIVE_VALID    ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic);
+              DELETE4(RAT_SPR_SPECULATIVE_VALID    ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic);
               
               break;
@@ -103,7 +105,12 @@
           case RAT_DEPTH_SAVE :
             {
-              DELETE4(rat_gpr_save                 ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
-              DELETE4(rat_spr_save                 ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
-              DELETE2(rat_depth                    ,_param->_nb_front_end,_param->_nb_context[it1]);
+              DELETE4(RAT_GPR_SPECULATIVE          ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
+              DELETE4(RAT_SPR_SPECULATIVE          ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
+
+              DELETE4(RAT_GPR_SPECULATIVE_VALID    ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
+              DELETE4(RAT_SPR_SPECULATIVE_VALID    ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
+
+              DELETE3(reg_RAT_USE                  ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2]);
+              DELETE2(reg_SAVE_RAT                 ,_param->_nb_front_end,_param->_nb_context[it1]);
 
               break;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_constant.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_constant.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_constant.cpp	(revision 145)
@@ -30,6 +30,8 @@
       {
         internal_INSERT_ACK [i] = 1;
+        internal_RENAME_ACK [i] = 1;
         
         PORT_WRITE(out_INSERT_ACK[i],internal_INSERT_ACK [i]);
+        PORT_WRITE(out_RENAME_ACK[i],internal_RENAME_ACK [i]);
       }
     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp	(revision 145)
@@ -28,66 +28,140 @@
     if (PORT_READ(in_NRESET) != 0)
       {
-        bool     have_branch_previous = false;
-        bool     can_continue [_param->_nb_front_end][_param->_max_nb_context];
+        bool rat_gpr_speculative_valid [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated][_param->_nb_general_register_logic];
+        bool rat_spr_speculative_valid [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated][_param->_nb_special_register_logic];
+        // bool reg_save_rat              [_param->_nb_front_end][_param->_max_nb_context];
 
         for (uint32_t i=0; i<_param->_nb_front_end; ++i)
           for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
-            can_continue [i][j] = true;
+            {
+              // reg_save_rat [i][j] = reg_SAVE_RAT [i][j];
+              for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+                {
+                  for (uint32_t l=0; l<_param->_nb_general_register_logic; ++l)
+                    rat_gpr_speculative_valid [i][j][k][l] = RAT_GPR_SPECULATIVE_VALID [i][j][k][l];
+                  for (uint32_t l=0; l<_param->_nb_special_register_logic; ++l)
+                    rat_spr_speculative_valid [i][j][k][l] = RAT_SPR_SPECULATIVE_VALID [i][j][k][l];
+                }
+            }
 
         for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
-          if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access
-            {
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RENAME [%d]",i);
-              
-              Tcontext_t front_end_id        = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
-              Tcontext_t context_id          = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
-              // bool       have_event          = (PORT_READ(in_RETIRE_EVENT_VAL [front_end_id][context_id]) and // always ack
-              //                                   (PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) == EVENT_STATE_EVENT));
-              
-              bool       have_branch_current = PORT_READ(in_RENAME_SAVE_RAT [i]);
+          {
+            if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access
+              {
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RENAME [%d]",i);
+                
+                Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
+                Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
+                
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id       : %d",front_end_id);
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id         : %d",context_id);
 
-              // one branch per cycle
-              can_continue[front_end_id][context_id] &= not (have_branch_current and have_branch_previous);
+                Tdepth_t   depth_min    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0;
+                Tdepth_t   depth_max    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;
+                Tcontrol_t depth_full   = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);
 
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id         : %d",front_end_id);
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id           : %d",context_id);
-           // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * have_event           : %d",have_event);
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * have_branch_previous : %d",have_branch_previous);
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * have_branch_current  : %d",have_branch_current );
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * can_continue         : %d",can_continue[front_end_id][context_id]);
-              
-              Tgeneral_address_t num_reg_ra_log    = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register;
-              Tgeneral_address_t num_reg_rb_log    = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register;
-              Tspecial_address_t num_reg_rc_log    = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register;
-              Tgeneral_address_t num_reg_rd_log    = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register;
-              Tspecial_address_t num_reg_re_log    = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register;
-              
-              Tgeneral_address_t num_reg_ra_phy    = rat_gpr_speculative[front_end_id][context_id][num_reg_ra_log];
-              Tgeneral_address_t num_reg_rb_phy    = rat_gpr_speculative[front_end_id][context_id][num_reg_rb_log];
-              Tspecial_address_t num_reg_rc_phy    = rat_spr_speculative[front_end_id][context_id][num_reg_rc_log];
-              Tgeneral_address_t num_reg_rd_phy_old= rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log];
-              Tspecial_address_t num_reg_re_phy_old= rat_spr_speculative[front_end_id][context_id][num_reg_re_log];
-              
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_ra           : %d -> %d",num_reg_ra_log,num_reg_ra_phy    );
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rb           : %d -> %d",num_reg_rb_log,num_reg_rb_phy    );
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rc           : %d -> %d",num_reg_rc_log,num_reg_rc_phy    );
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd           : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old);
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re           : %d -> %d",num_reg_re_log,num_reg_re_phy_old);
-              
-              internal_RENAME_ACK [i] = can_continue[front_end_id][context_id];
-              PORT_WRITE(out_RENAME_ACK                [i],internal_RENAME_ACK [i]);
-              PORT_WRITE(out_RENAME_NUM_REG_RA_PHY     [i], num_reg_ra_phy    );
-              PORT_WRITE(out_RENAME_NUM_REG_RB_PHY     [i], num_reg_rb_phy    );
-              PORT_WRITE(out_RENAME_NUM_REG_RC_PHY     [i], num_reg_rc_phy    );
-              PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old);
-              PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old);
+                Tdepth_t   depth        = (_param->_have_port_depth       )?PORT_READ(in_RENAME_DEPTH        [i]):0;
+                // Tcontrol_t save_rat     = PORT_READ(in_RENAME_SAVE_RAT [i]);
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * depth/min/max/full : %d - [%d:%d] - %d",depth,depth_min,depth_max,depth_full);
+                // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * save_rat (new)     : %d",save_rat);
+                // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * save_rat (old)     : %d",reg_save_rat [front_end_id][context_id]);
+                
+                // if (reg_save_rat [front_end_id][context_id])
+                //   {
+                //     for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_general_register_logic; num_reg_log++)
+                //       rat_gpr_speculative_valid [front_end_id][context_id][depth][num_reg_log] = false;
+                //     for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_special_register_logic; num_reg_log++)
+                //       rat_spr_speculative_valid [front_end_id][context_id][depth][num_reg_log] = false;
+                //   }
+                
+                // reg_save_rat[front_end_id][context_id] = save_rat;
+                
+                Tgeneral_address_t num_reg_ra_log    = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register;
+                Tgeneral_address_t num_reg_rb_log    = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register;
+                Tspecial_address_t num_reg_rc_log    = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register;
+                Tgeneral_address_t num_reg_rd_log    = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register;
+                Tspecial_address_t num_reg_re_log    = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register;
+                
+                Tgeneral_address_t num_reg_ra_phy    ;
+                Tgeneral_address_t num_reg_rb_phy    ;
+                Tspecial_address_t num_reg_rc_phy    ;
+                Tgeneral_address_t num_reg_rd_phy_old;
+                Tspecial_address_t num_reg_re_phy_old;
+                        
+                bool find_ra = false;
+                bool find_rb = false;
+                bool find_rc = false;
+                bool find_rd = false;
+                bool find_re = false;
+                
+                for (uint32_t num_branch=0; num_branch<_param->_nb_branch_speculated[front_end_id][context_id]; ++num_branch)
+                  {
+                    uint32_t index = (depth-num_branch)%_param->_nb_branch_speculated[front_end_id][context_id];
 
-              internal_RENAME_SAVE [i] = have_branch_current;
+                    if (not find_ra and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_ra_log])
+                      {
+                        find_ra            = true;
+                        num_reg_ra_phy     = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_ra_log];
+                      }
+                    
+                    if (not find_rb and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_rb_log])
+                      {
+                        find_rb            = true;
+                        num_reg_rb_phy     = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rb_log];
+                      }
+                    
+                    if (not find_rc and rat_spr_speculative_valid [front_end_id][context_id][index][num_reg_rc_log])
+                      {
+                        find_rc            = true;
+                        num_reg_rc_phy     = RAT_SPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rc_log];
+                      }
+                    
+                    if (not find_rd and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_rd_log])
+                      {
+                        find_rd            = true;
+                        num_reg_rd_phy_old = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rd_log];
+                      }
+                    
+                    if (not find_re and rat_spr_speculative_valid [front_end_id][context_id][index][num_reg_re_log])
+                      {
+                        find_re            = true;
+                        num_reg_re_phy_old = RAT_SPR_SPECULATIVE[front_end_id][context_id][index][num_reg_re_log];
+                      }
 
-              // save info to the next instruction
-              have_branch_previous |= have_branch_current;
-            }
+                    // if index == depth_min, stop because depth_min is the not speculative.
+                    // if (index == depth_min)
+                    //   break;
+                  }
+                
+                if (not find_ra)
+                  num_reg_ra_phy     = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_ra_log];
+                if (not find_rb)
+                  num_reg_rb_phy     = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rb_log];
+                if (not find_rc)
+                  num_reg_rc_phy     = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rc_log];
+                if (not find_rd)
+                  num_reg_rd_phy_old = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rd_log];
+                if (not find_re)
+                  num_reg_re_phy_old = RAT_SPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_re_log];
+                
+                // if rat_SPECULATIVE is valid, 
+                // then read rat_SPECULATIVE have the most valid alias register
+                // else, they have an previous event, the rat_NOT_SPECULATIVE have the valid register
+                
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_ra         : %d -> %d",num_reg_ra_log,num_reg_ra_phy    );
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rb         : %d -> %d",num_reg_rb_log,num_reg_rb_phy    );
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rc         : %d -> %d",num_reg_rc_log,num_reg_rc_phy    );
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd         : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old);
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re         : %d -> %d",num_reg_re_log,num_reg_re_phy_old);
+                
+                PORT_WRITE(out_RENAME_NUM_REG_RA_PHY     [i], num_reg_ra_phy    );
+                PORT_WRITE(out_RENAME_NUM_REG_RB_PHY     [i], num_reg_rb_phy    );
+                PORT_WRITE(out_RENAME_NUM_REG_RC_PHY     [i], num_reg_rc_phy    );
+                PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old);
+                PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old);
+              }
+          }
       }
-    
+
     log_end(Register_Address_Translation_unit,FUNCTION);
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_transition.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_transition.cpp	(revision 145)
@@ -34,11 +34,30 @@
 	  for (uint32_t j=0; j<_param->_nb_context[i]; j++)
 	    {
-              rat_depth                 [i][j]    = 0;
-              rat_gpr_speculative       [i][j][0] = 0;
+	      RAT_GPR_NOT_SPECULATIVE   [i][j][0]    = 0;
+              RAT_GPR_SPECULATIVE_VALID [i][j][0][0] = false;
+              RAT_GPR_SPECULATIVE       [i][j][0][0] = 0    ; // not necessary
 
 	      for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
-                rat_gpr_speculative        [i][j][k] = gpr++;
+                {
+                  RAT_GPR_NOT_SPECULATIVE    [i][j][k]    = gpr++;
+                  for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
+                    {
+                      RAT_GPR_SPECULATIVE_VALID  [i][j][l][k] = false;
+                      RAT_GPR_SPECULATIVE        [i][j][l][k] = 0    ; // not necessary
+                    }
+                }
 	      for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
-                rat_spr_speculative        [i][j][k] = spr++; // not necessary
+                {
+                  RAT_SPR_NOT_SPECULATIVE    [i][j][k]    = spr++;
+                  for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
+                    {
+                      RAT_SPR_SPECULATIVE_VALID  [i][j][l][k] = false;
+                      RAT_SPR_SPECULATIVE        [i][j][l][k] = 0    ; // not necessary
+                    }
+                }
+
+              for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+                reg_RAT_USE [i][j][k] = false;
+              reg_SAVE_RAT [i][j] = false;
 	    }
       }
@@ -46,4 +65,9 @@
       {
 	// Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0)
+        bool free_rat [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated];
+	for (uint32_t i=0; i<_param->_nb_front_end; i++)
+	  for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+            for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+              free_rat [i][j][k] = false;
 
 	// =====================================================
@@ -55,48 +79,60 @@
               {
                 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RETIRE_EVENT [%d][%d]",i,j);
+
+                // Test if event have just occure
+                //   * if exception -> reset valid table (rat_NOT_SPECULATIVE have the good value)
                 
-                // Test if event have just occure
                 if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)
-                  {
-                    switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j]))
+                  switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j]))
+                    {
+                    case EVENT_TYPE_BRANCH_MISS_SPECULATION :
                       {
-                      case EVENT_TYPE_BRANCH_MISS_SPECULATION :
-                      case EVENT_TYPE_LOAD_MISS_SPECULATION   :
-                        {
-                          // Miss speculation (branch or load)
-                          // Restore contexte and update depth
-
-                          log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * MISS_SPECULATION : Restore RAT");
-
-                          Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH [i][j]):0;
-
-                          log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth : %d",depth);
-                          
-                          // restore GPR
-                          for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++)
-                            rat_gpr_speculative [i][j][num_gpr] = rat_gpr_save [i][j][depth][num_gpr];
-                          
-                          // restore SPR
-                          for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++)
-                            rat_spr_speculative [i][j][num_spr] = rat_spr_save [i][j][depth][num_spr];
-                          
-                          // update rat_depth
-                          rat_depth[i][j] = depth;
-                          
-                          break;
-                        }
-                        // case EVENT_TYPE_EXCEPTION               :
-                        // case EVENT_TYPE_SPR_ACCESS              :
-                        // case EVENT_TYPE_MSYNC                   :
-                        // case EVENT_TYPE_PSYNC                   :
-                        // case EVENT_TYPE_CSYNC                   :
-                      default :
-                        {
-                          // nothing
-                          break;
-                        }
+                        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * BRANCH_MISS_SPECULATION - Reset Update Table");
+
+                        reg_SAVE_RAT [i][j] = true;
+                        
+                        Tdepth_t   depth      = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH[i][j]):0;
+                        Tdepth_t   depth_min  = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0;
+                        Tdepth_t   depth_max  = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0;
+                        Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]);
+                        
+                        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth      : %d",depth);
+                        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth_min  : %d",depth_min);
+                        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth_max  : %d",depth_max);
+                        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth_full : %d",depth_full);
+
+                        Tdepth_t   it        = depth_min;
+                        
+                        for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+                          {
+                            it = (it-1)%_param->_nb_branch_speculated[i][j];
+
+                            if (it == depth)
+                              break;
+                            
+                            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"        * flush    : %d",it);
+                            
+                            free_rat[i][j][it] = true;
+                          }
+                        
+                        break;
                       }
-                  
-                  }
+                    case EVENT_TYPE_EXCEPTION :
+                      {
+                        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * EXCEPTION - Reset Update Table");
+                        
+                        reg_SAVE_RAT [i][j] = true;
+
+                        // Reset validity table
+                        for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+                          free_rat [i][j][k] = true;
+                        
+                        break;
+                      }
+                    default :
+                      {
+                        break;
+                      }
+                    }
               }
 
@@ -114,15 +150,36 @@
 	      Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
 	      Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
-              Tcontrol_t save         = internal_RENAME_SAVE [i];
+              Tcontrol_t write_rd     = PORT_READ(in_INSERT_WRITE_RD [i]);
+              Tcontrol_t write_re     = PORT_READ(in_INSERT_WRITE_RE [i]);
+              Tdepth_t   depth        = (_param->_have_port_depth       )?PORT_READ(in_RENAME_DEPTH        [i]):0;
+              Tcontrol_t save_rat     = reg_SAVE_RAT[front_end_id][context_id];
+              // TODO SAVE_RAT
 
               log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end          : %d",front_end_id);
               log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context            : %d",context_id);
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * save               : %d",save);
-
-	      // Test if write and modifie RAT (RD and RE)
-
-              Tcontrol_t write_rd     = PORT_READ(in_INSERT_WRITE_RD [i]);
-              Tcontrol_t write_re     = PORT_READ(in_INSERT_WRITE_RE [i]);
-
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * depth              : %d",depth);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * save_rat (old)     : %d",save_rat);
+
+              if (save_rat)
+                {
+// #ifdef DEBUG_TEST
+//                   if (reg_RAT_USE[front_end_id][context_id][depth])
+//                     throw ERRORMORPHEO(FUNCTION,toString(_("Invalid RAT and need save_rat (%d).\n"),depth));
+// #endif
+                  reg_RAT_USE[front_end_id][context_id][depth] = true;
+                  
+                  // new branch, new RAT
+                  for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_general_register_logic; num_reg_log++)
+                    RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false;
+                  for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_special_register_logic; num_reg_log++)
+                    RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false;
+                }
+
+              save_rat = PORT_READ(in_RENAME_SAVE_RAT [i]);
+              reg_SAVE_RAT[front_end_id][context_id] = save_rat;
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * save_rat (new)     : %d",save_rat);
+	      
+	      // Test if write and modifie RAT
               log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_rd           : %d",write_rd);
 	      if (write_rd == 1)
@@ -134,5 +191,6 @@
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy     : %d",num_reg_rd_phy);
 
-                  rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy;
+                  RAT_GPR_SPECULATIVE       [front_end_id][context_id][depth][num_reg_rd_log] = num_reg_rd_phy;
+                  RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_rd_log] = true;
                 }
 
@@ -146,30 +204,6 @@
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy     : %d",num_reg_re_phy);
 
-                  rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy;
-                }
-
-              if (save)
-                {
-                  // Need save RAT
-
-                  Tdepth_t depth = (_param->_have_port_depth       )?PORT_READ(in_RENAME_DEPTH        [i]):0;
-
-                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth old - new  : %d",depth);
-
-// #ifdef DEBUG_TEST
-//                   if (depth != ((depth_old+1)%_param->_nb_branch_speculated[front_end_id][context_id]))
-//                     throw ERRORMORPHEO(FUNCTION,toString(_("Rename : Invalid depth (old : %d, new : %d).\n"),depth_old,depth));
-// #endif
-
-                  // save GPR
-                  for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++)
-                    rat_gpr_save [front_end_id][context_id][depth][num_gpr] = rat_gpr_speculative [front_end_id][context_id][num_gpr];
-
-                  // save SPR
-                  for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++)
-                    rat_spr_save [front_end_id][context_id][depth][num_spr] = rat_spr_speculative [front_end_id][context_id][num_spr];
-
-                  // update rat_depth with new depth
-                  rat_depth[front_end_id][context_id] = depth;
+                  RAT_SPR_SPECULATIVE       [front_end_id][context_id][depth][num_reg_re_log] = num_reg_re_phy;
+                  RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_re_log] = true;
                 }
 	    }
@@ -179,19 +213,13 @@
 	// =====================================================
 	// Second : interface retire
-	//  (because if an event on the same thread : the instruction is already renamed)
-	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
-	  if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i])
-	    {
+	// if event AND event is exception, restore rat_NOT_SPECULATIVE
+
+        for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+          if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i])
+            {
               log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RETIRE [%d]",i);
 
-	      // if no event : no effect, because the RAT content the most recently register
-	      // but if they have a event (exception or miss speculation), the rat must restore the oldest value
-	      // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register
-	      // the retire interface became of the Re Order Buffer, also is in program sequence !
-
-#ifdef DEBUG
               Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
               Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RETIRE_CONTEXT_ID   [i]):0;
-#endif
               Tcontrol_t write_rd     = PORT_READ(in_RETIRE_WRITE_RD [i]);
               Tcontrol_t write_re     = PORT_READ(in_RETIRE_WRITE_RE [i]);
@@ -206,7 +234,5 @@
               if (write_rd == 1)
                 {
-#ifdef DEBUG
                   Tgeneral_address_t num_reg_rd_log     = PORT_READ(in_RETIRE_NUM_REG_RD_LOG     [i]);
-#endif
 
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_log     : %d",num_reg_rd_log    );
@@ -214,10 +240,9 @@
                   if (not restore)
                     {
-#ifdef DEBUG
                   Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]);
-#endif
+
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy_new : %d",num_reg_rd_phy_new);
 
-                  // rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
+                  RAT_GPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
                     }
                 }
@@ -226,23 +251,81 @@
               if (write_re == 1)
                 {
-#ifdef DEBUG
                   Tspecial_address_t num_reg_re_log     = PORT_READ(in_RETIRE_NUM_REG_RE_LOG     [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_log     : %d",num_reg_re_log    );
+
+                  if (not restore)
+                    {
+                  Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy_new : %d",num_reg_re_phy_new);
+
+                  RAT_SPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
+                    }
+                }
+            }
+
+	// =====================================================
+	// ====[ DEPTH ]========================================
+	// =====================================================
+#if 1
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            {
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * DEPTH[%d][%d]",i,j);
+
+              Tdepth_t   depth_min  = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0;
+              Tdepth_t   depth_max  = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0;
+              Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]);
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * depth_min  : %d",depth_min);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * depth_max  : %d",depth_max);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * depth_full : %d",depth_full);
+              
+              if (not depth_full)
+                {
+                  Tdepth_t depth     = depth_max;
+
+                  for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+                    {
+                      if (depth == depth_min)
+                        break;
+
+                      if (reg_RAT_USE[i][j][depth])
+                        {
+                          log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * flush    : %d",depth);
+                  
+                          free_rat [i][j][depth] = true;
+                          // reg_RAT_USE[i][j][depth] = false;
+
+                          // for (uint32_t l=0; l<_param->_nb_general_register_logic; l++)
+                          //   RAT_GPR_SPECULATIVE_VALID  [i][j][depth][l] = false;
+                          // for (uint32_t l=0; l<_param->_nb_special_register_logic; l++)
+                          //   RAT_SPR_SPECULATIVE_VALID  [i][j][depth][l] = false;
+                        }
+
+                      depth = (depth+1)%_param->_nb_branch_speculated[i][j];
+                    }
+                }
+            }
 #endif
-
-                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_log     : %d",num_reg_re_log    );
-
-                  if (not restore)
-                    {
-#ifdef DEBUG
-                  Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);
-#endif
-
-                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy_new : %d",num_reg_re_phy_new);
-
-                  // rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
-                    }
-                }
-
-	    }
+	// =====================================================
+	// ====[ FREE RAT ]=====================================
+	// =====================================================
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+              if (free_rat[i][j][k])
+                {
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * Free RAT : [%d][%d][%d]",i,j,k);
+                  
+                  reg_RAT_USE[i][j][k] = false;
+                  
+                  for (uint32_t l=0; l<_param->_nb_general_register_logic; l++)
+                    RAT_GPR_SPECULATIVE_VALID  [i][j][k][l] = false;
+                  for (uint32_t l=0; l<_param->_nb_special_register_logic; l++)
+                    RAT_SPR_SPECULATIVE_VALID  [i][j][k][l] = false;
+                }
+
       }
 
@@ -255,36 +338,40 @@
         for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
           {
-            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end[%d].context[%d] - rat_depth : %d",i,j,rat_depth[i][j]);
-          
-            for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
+            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end[%d].context[%d] - SAVE_RAT : %d",i,j,reg_SAVE_RAT[i][j]);
+              
+            for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit)
               {
                 std::string str = "";
                 for (uint32_t x=0; x<limit; x++)
                   {
-                    uint32_t index = k+x;
+                    uint32_t index = l+x;
                     if (index >= _param->_nb_general_register_logic)
                       break;
                     else
-                      str+=toString("GPR[%.4d] - %.5d | ",index,rat_gpr_speculative [i][j][index]);
+                      str+=toString("GPR[%.4d]       -   %.5d | ",index,RAT_GPR_NOT_SPECULATIVE [i][j][index]);
                   }
                 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
               }
 
-            for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
-              for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
-                {
-                  std::string str = "";
-                  for (uint32_t x=0; x<limit; x++)
-                    {
-                      uint32_t index = k+x;
-                      if (index >= _param->_nb_general_register_logic)
-                        break;
-                      else
-                        str+=toString("GPR_%d[%.4d] - %.5d | ",l,index,rat_gpr_save [i][j][l][index]);
-                    }
-                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
-                }
-            
-            for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
+            for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+              {
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * GPR      [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]);
+
+                for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit)
+                  {
+                    std::string str = "";
+                    for (uint32_t x=0; x<limit; x++)
+                      {
+                        uint32_t index = l+x;
+                        if (index >= _param->_nb_general_register_logic)
+                          break;
+                        else
+                          str+=toString("GPR[%.4d][%.4d] - %.1d %.5d | ",index,k,RAT_GPR_SPECULATIVE_VALID [i][j][k][index],RAT_GPR_SPECULATIVE [i][j][k][index]);
+                      }
+                    log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
+                  }
+              }
+
+            for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit)
               {
                 std::string str = "";
@@ -292,28 +379,33 @@
                 for (uint32_t x=0; x<limit; x++)
                   {
-                    uint32_t index = k+x;
+                    uint32_t index = l+x;
                     if (index >= _param->_nb_special_register_logic)
                       break;
                     else
-                      str+=toString("SPR[%.4d] - %.5d | ",index,rat_spr_speculative [i][j][index]);
+                      str+=toString("SPR[%.4d]       -   %.5d | ",index,RAT_SPR_NOT_SPECULATIVE [i][j][index]);
                   }
                 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
               }
 
-            for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
-              for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
-                {
-                  std::string str = "";
-                  for (uint32_t x=0; x<limit; x++)
-                    {
-                      uint32_t index = k+x;
-                      if (index >= _param->_nb_special_register_logic)
-                        break;
-                      else
-                        str+=toString("SPR_%d[%.4d] - %.5d | ",l,index,rat_spr_save [i][j][l][index]);
-                    }
-                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
-                }
-
+      
+            for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+              {
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * SPR      [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]);
+                
+                for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit)
+                  {
+                    std::string str = "";
+                    
+                    for (uint32_t x=0; x<limit; x++)
+                      {
+                        uint32_t index = l+x;
+                        if (index >= _param->_nb_special_register_logic)
+                          break;
+                        else
+                          str+=toString("SPR[%.4d][%.4d] - %.1d %.5d | ",index,k,RAT_SPR_SPECULATIVE_VALID [i][j][k][index],RAT_SPR_SPECULATIVE [i][j][k][index]);
+                      }
+                    log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
+                  }
+              }
           }
     }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_genMealy_rename.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_genMealy_rename.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_genMealy_rename.cpp	(revision 145)
@@ -52,9 +52,9 @@
         // else, they have an previous event, the rat_not_speculative have the valid register
 
-        Tgeneral_address_t num_reg_ra_phy    = (rat_gpr_speculative_valid[front_end_id][context_id][num_reg_ra_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_ra_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_ra_log];
-        Tgeneral_address_t num_reg_rb_phy    = (rat_gpr_speculative_valid[front_end_id][context_id][num_reg_rb_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_rb_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_rb_log];
-        Tspecial_address_t num_reg_rc_phy    = (rat_spr_speculative_valid[front_end_id][context_id][num_reg_rc_log] and not have_event)?rat_spr_speculative[front_end_id][context_id][num_reg_rc_log]:rat_spr_not_speculative[front_end_id][context_id][num_reg_rc_log];
-        Tgeneral_address_t num_reg_rd_phy_old= (rat_gpr_speculative_valid[front_end_id][context_id][num_reg_rd_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_rd_log];
-        Tspecial_address_t num_reg_re_phy_old= (rat_spr_speculative_valid[front_end_id][context_id][num_reg_re_log] and not have_event)?rat_spr_speculative[front_end_id][context_id][num_reg_re_log]:rat_spr_not_speculative[front_end_id][context_id][num_reg_re_log];
+        Tgeneral_address_t num_reg_ra_phy    = (RAT_GPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_ra_log] and not have_event)?RAT_GPR_SPECULATIVE[front_end_id][context_id][0][num_reg_ra_log]:RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_ra_log];
+        Tgeneral_address_t num_reg_rb_phy    = (RAT_GPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_rb_log] and not have_event)?RAT_GPR_SPECULATIVE[front_end_id][context_id][0][num_reg_rb_log]:RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rb_log];
+        Tspecial_address_t num_reg_rc_phy    = (RAT_SPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_rc_log] and not have_event)?RAT_SPR_SPECULATIVE[front_end_id][context_id][0][num_reg_rc_log]:RAT_SPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rc_log];
+        Tgeneral_address_t num_reg_rd_phy_old= (RAT_GPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_rd_log] and not have_event)?RAT_GPR_SPECULATIVE[front_end_id][context_id][0][num_reg_rd_log]:RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rd_log];
+        Tspecial_address_t num_reg_re_phy_old= (RAT_SPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_re_log] and not have_event)?RAT_SPR_SPECULATIVE[front_end_id][context_id][0][num_reg_re_log]:RAT_SPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_re_log];
 
         log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_ra         : %d -> %d",num_reg_ra_log,num_reg_ra_phy    );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_transition.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_transition.cpp	(revision 145)
@@ -34,19 +34,19 @@
 	  for (uint32_t j=0; j<_param->_nb_context[i]; j++)
 	    {
-	      rat_gpr_not_speculative   [i][j][0] = 0;
-              rat_gpr_speculative_valid [i][j][0] = false;
-              rat_gpr_speculative       [i][j][0] = 0    ; // not necessary
+	      RAT_GPR_NOT_SPECULATIVE   [i][j][0]    = 0;
+              RAT_GPR_SPECULATIVE_VALID [i][j][0][0] = false;
+              RAT_GPR_SPECULATIVE       [i][j][0][0] = 0    ; // not necessary
 
 	      for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
                 {
-                  rat_gpr_not_speculative    [i][j][k] = gpr++;
-                  rat_gpr_speculative_valid  [i][j][k] = false;
-                  rat_gpr_speculative        [i][j][k] = 0    ; // not necessary
+                  RAT_GPR_NOT_SPECULATIVE    [i][j][k]    = gpr++;
+                  RAT_GPR_SPECULATIVE_VALID  [i][j][0][k] = false;
+                  RAT_GPR_SPECULATIVE        [i][j][0][k] = 0    ; // not necessary
                 }
 	      for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
                 {
-                  rat_spr_not_speculative    [i][j][k] = spr++;
-                  rat_spr_speculative_valid  [i][j][k] = false;
-                  rat_spr_speculative        [i][j][k] = 0    ; // not necessary
+                  RAT_SPR_NOT_SPECULATIVE    [i][j][k]    = spr++;
+                  RAT_SPR_SPECULATIVE_VALID  [i][j][0][k] = false;
+                  RAT_SPR_SPECULATIVE        [i][j][0][k] = 0    ; // not necessary
                 }
 	    }
@@ -69,7 +69,7 @@
                   // Reset validity table
                   for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
-                    rat_gpr_speculative_valid [i][j][k] = false;
+                    RAT_GPR_SPECULATIVE_VALID [i][j][0][k] = false;
                   for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
-                    rat_spr_speculative_valid [i][j][k] = false;
+                    RAT_SPR_SPECULATIVE_VALID [i][j][0][k] = false;
                 }
 
@@ -103,6 +103,6 @@
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy     : %d",num_reg_rd_phy);
 
-                  rat_gpr_speculative       [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy;
-                  rat_gpr_speculative_valid [front_end_id][context_id][num_reg_rd_log] = true;
+                  RAT_GPR_SPECULATIVE       [front_end_id][context_id][0][num_reg_rd_log] = num_reg_rd_phy;
+                  RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][0][num_reg_rd_log] = true;
                 }
 
@@ -116,6 +116,6 @@
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy     : %d",num_reg_re_phy);
 
-                  rat_spr_speculative       [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy;
-                  rat_spr_speculative_valid [front_end_id][context_id][num_reg_re_log] = true;
+                  RAT_SPR_SPECULATIVE       [front_end_id][context_id][0][num_reg_re_log] = num_reg_re_phy;
+                  RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][0][num_reg_re_log] = true;
                 }
 	    }
@@ -160,5 +160,5 @@
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy_new : %d",num_reg_rd_phy_new);
 
-                  rat_gpr_not_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
+                  RAT_GPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
                     }
                 }
@@ -177,5 +177,5 @@
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy_new : %d",num_reg_re_phy_new);
 
-                  rat_spr_not_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
+                  RAT_SPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
                     }
                 }
@@ -203,5 +203,5 @@
                       break;
                     else
-                      str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) | ",index,rat_gpr_speculative_valid [i][j][index],rat_gpr_speculative [i][j][index],rat_gpr_not_speculative [i][j][index]);
+                      str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) | ",index,RAT_GPR_SPECULATIVE_VALID [i][j][0][index],RAT_GPR_SPECULATIVE [i][j][0][index],RAT_GPR_NOT_SPECULATIVE [i][j][index]);
                   }
                 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
@@ -218,5 +218,5 @@
                       break;
                     else
-                      str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) | ",index,rat_spr_speculative_valid [i][j][index],rat_spr_speculative [i][j][index],rat_spr_not_speculative [i][j][index]);
+                      str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) | ",index,RAT_SPR_SPECULATIVE_VALID [i][j][0][index],RAT_SPR_SPECULATIVE [i][j][0][index],RAT_SPR_NOT_SPECULATIVE [i][j][index]);
                   }
                 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
@@ -235,10 +235,10 @@
               for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y)
                 {
-                  if (rat_gpr_speculative_valid [i][j][x] and
-                      rat_gpr_speculative_valid [i][j][y] and
-                      (rat_gpr_speculative[i][j][x] == rat_gpr_speculative[i][j][y]))
-                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_speculative[%d][%d][%d] == rat_gpr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_speculative[i][j][x]));
-                  if (rat_gpr_not_speculative[i][j][x] == rat_gpr_not_speculative[i][j][y])
-                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_not_speculative[%d][%d][%d] == rat_gpr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_not_speculative[i][j][x]));
+                  if (RAT_GPR_SPECULATIVE_VALID [i][j][0][x] and
+                      RAT_GPR_SPECULATIVE_VALID [i][j][0][y] and
+                      (RAT_GPR_SPECULATIVE[i][j][0][x] == RAT_GPR_SPECULATIVE[i][j][0][y]))
+                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_GPR_SPECULATIVE[%d][%d][0][%d] == RAT_GPR_SPECULATIVE[%d][%d][0][%d] == %d"),i,j,x,i,j,y,RAT_GPR_SPECULATIVE[i][j][0][x]));
+                  if (RAT_GPR_NOT_SPECULATIVE[i][j][x] == RAT_GPR_NOT_SPECULATIVE[i][j][y])
+                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_GPR_NOT_SPECULATIVE[%d][%d][%d] == RAT_GPR_NOT_SPECULATIVE[%d][%d][%d] == %d"),i,j,x,i,j,y,RAT_GPR_NOT_SPECULATIVE[i][j][x]));
                   
                 }
@@ -246,10 +246,10 @@
               for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y)
                 {
-                  if(rat_spr_speculative_valid [i][j][x] and
-                     rat_spr_speculative_valid [i][j][y] and
-                     (rat_spr_speculative[i][j][x] == rat_spr_speculative[i][j][y]))
-                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_speculative[%d][%d][%d] == rat_spr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_speculative[i][j][x]));
-                  if (rat_spr_not_speculative[i][j][x] == rat_spr_not_speculative[i][j][y])
-                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_not_speculative[%d][%d][%d] == rat_spr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_not_speculative[i][j][x]));
+                  if(RAT_SPR_SPECULATIVE_VALID [i][j][0][x] and
+                     RAT_SPR_SPECULATIVE_VALID [i][j][0][y] and
+                     (RAT_SPR_SPECULATIVE[i][j][0][x] == RAT_SPR_SPECULATIVE[i][j][0][y]))
+                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_SPR_SPECULATIVE[%d][%d][0][%d] == RAT_SPR_SPECULATIVE[%d][%d][0][%d] == %d"),i,j,x,i,j,y,RAT_SPR_SPECULATIVE[i][j][0][x]));
+                  if (RAT_SPR_NOT_SPECULATIVE[i][j][x] == RAT_SPR_NOT_SPECULATIVE[i][j][y])
+                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_SPR_NOT_SPECULATIVE[%d][%d][%d] == RAT_SPR_NOT_SPECULATIVE[%d][%d][%d] == %d"),i,j,x,i,j,y,RAT_SPR_NOT_SPECULATIVE[i][j][x]));
                   
                 }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_constant.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_constant.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_constant.cpp	(revision 145)
@@ -0,0 +1,63 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_ooo_engine {
+namespace ooo_engine {
+namespace rename_unit {
+namespace register_translation_unit {
+namespace register_address_translation_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Register_Address_Translation_unit::function_depth_save_constant"
+  void Register_Address_Translation_unit::function_depth_save_constant (void)
+  {
+    log_begin(Register_Address_Translation_unit,FUNCTION);
+    log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
+
+    // Constant : accepted already transaction
+    for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+      {
+        internal_INSERT_ACK [i] = 1;
+        
+        PORT_WRITE(out_INSERT_ACK[i],internal_INSERT_ACK [i]);
+      }
+    
+    for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+      {
+        internal_RETIRE_ACK [i] = 1;
+        
+        PORT_WRITE(out_RETIRE_ACK[i],internal_RETIRE_ACK [i]);
+      }
+    
+    for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+      for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+        {
+          internal_RETIRE_EVENT_ACK [i][j] = 1;
+          
+          PORT_WRITE(out_RETIRE_EVENT_ACK[i][j],internal_RETIRE_EVENT_ACK [i][j]);
+        }
+    
+    log_end(Register_Address_Translation_unit,FUNCTION);
+  };
+
+}; // end namespace register_address_translation_unit
+}; // end namespace register_translation_unit
+}; // end namespace rename_unit
+}; // end namespace ooo_engine
+}; // end namespace multi_ooo_engine
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp	(revision 145)
@@ -0,0 +1,104 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_ooo_engine {
+namespace ooo_engine {
+namespace rename_unit {
+namespace register_translation_unit {
+namespace register_address_translation_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Register_Address_Translation_unit::function_depth_save_genMealy_rename"
+  void Register_Address_Translation_unit::function_depth_save_genMealy_rename (void)
+  {
+    log_begin(Register_Address_Translation_unit,FUNCTION);
+    log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET) != 0)
+      {
+        bool     have_branch_previous = false;
+        bool     can_continue [_param->_nb_front_end][_param->_max_nb_context];
+
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            can_continue [i][j] = true;
+
+        for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+          if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access
+            {
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RENAME [%d]",i);
+              
+              Tcontext_t front_end_id        = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
+              Tcontext_t context_id          = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
+              // bool       have_event          = (PORT_READ(in_RETIRE_EVENT_VAL [front_end_id][context_id]) and // always ack
+              //                                   (PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) == EVENT_STATE_EVENT));
+              
+              bool       have_branch_current = PORT_READ(in_RENAME_SAVE_RAT [i]);
+
+              // one branch per cycle
+              can_continue[front_end_id][context_id] &= not (have_branch_current and have_branch_previous);
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id         : %d",front_end_id);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id           : %d",context_id);
+           // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * have_event           : %d",have_event);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * have_branch_previous : %d",have_branch_previous);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * have_branch_current  : %d",have_branch_current );
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * can_continue         : %d",can_continue[front_end_id][context_id]);
+              
+              Tgeneral_address_t num_reg_ra_log    = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register;
+              Tgeneral_address_t num_reg_rb_log    = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register;
+              Tspecial_address_t num_reg_rc_log    = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register;
+              Tgeneral_address_t num_reg_rd_log    = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register;
+              Tspecial_address_t num_reg_re_log    = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register;
+              
+              Tgeneral_address_t num_reg_ra_phy    = rat_gpr_speculative[front_end_id][context_id][num_reg_ra_log];
+              Tgeneral_address_t num_reg_rb_phy    = rat_gpr_speculative[front_end_id][context_id][num_reg_rb_log];
+              Tspecial_address_t num_reg_rc_phy    = rat_spr_speculative[front_end_id][context_id][num_reg_rc_log];
+              Tgeneral_address_t num_reg_rd_phy_old= rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log];
+              Tspecial_address_t num_reg_re_phy_old= rat_spr_speculative[front_end_id][context_id][num_reg_re_log];
+              
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_ra           : %d -> %d",num_reg_ra_log,num_reg_ra_phy    );
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rb           : %d -> %d",num_reg_rb_log,num_reg_rb_phy    );
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rc           : %d -> %d",num_reg_rc_log,num_reg_rc_phy    );
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd           : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re           : %d -> %d",num_reg_re_log,num_reg_re_phy_old);
+              
+              internal_RENAME_ACK [i] = can_continue[front_end_id][context_id];
+              PORT_WRITE(out_RENAME_ACK                [i],internal_RENAME_ACK [i]);
+              PORT_WRITE(out_RENAME_NUM_REG_RA_PHY     [i], num_reg_ra_phy    );
+              PORT_WRITE(out_RENAME_NUM_REG_RB_PHY     [i], num_reg_rb_phy    );
+              PORT_WRITE(out_RENAME_NUM_REG_RC_PHY     [i], num_reg_rc_phy    );
+              PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old);
+              PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old);
+
+              internal_RENAME_SAVE [i] = have_branch_current;
+
+              // save info to the next instruction
+              have_branch_previous |= have_branch_current;
+            }
+      }
+    
+    log_end(Register_Address_Translation_unit,FUNCTION);
+  };
+
+}; // end namespace register_address_translation_unit
+}; // end namespace register_translation_unit
+}; // end namespace rename_unit
+}; // end namespace ooo_engine
+}; // end namespace multi_ooo_engine
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_transition.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_transition.cpp	(revision 145)
@@ -0,0 +1,334 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_ooo_engine {
+namespace ooo_engine {
+namespace rename_unit {
+namespace register_translation_unit {
+namespace register_address_translation_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Register_Address_Translation_unit::function_depth_save_transition"
+  void Register_Address_Translation_unit::function_depth_save_transition (void)
+  {
+    log_begin(Register_Address_Translation_unit,FUNCTION);
+    log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET) == 0)
+      {
+	uint32_t gpr = 1;
+	uint32_t spr = 0;
+
+	for (uint32_t i=0; i<_param->_nb_front_end; i++)
+	  for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+	    {
+              rat_depth                 [i][j]    = 0;
+              rat_gpr_speculative       [i][j][0] = 0;
+
+	      for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
+                rat_gpr_speculative        [i][j][k] = gpr++;
+	      for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
+                rat_spr_speculative        [i][j][k] = spr++; // not necessary
+	    }
+      }
+    else
+      {
+	// Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0)
+
+	// =====================================================
+	// ====[ RETIRE_EVENT ]=================================
+	// =====================================================
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j])
+              {
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RETIRE_EVENT [%d][%d]",i,j);
+                
+                // Test if event have just occure
+                if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)
+                  {
+                    switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j]))
+                      {
+                      case EVENT_TYPE_BRANCH_MISS_SPECULATION :
+                      case EVENT_TYPE_LOAD_MISS_SPECULATION   :
+                        {
+                          // Miss speculation (branch or load)
+                          // Restore contexte and update depth
+
+                          log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * MISS_SPECULATION : Restore RAT");
+
+                          Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH [i][j]):0;
+
+                          log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth : %d",depth);
+                          
+                          // restore GPR
+                          for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++)
+                            rat_gpr_speculative [i][j][num_gpr] = rat_gpr_save [i][j][depth][num_gpr];
+                          
+                          // restore SPR
+                          for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++)
+                            rat_spr_speculative [i][j][num_spr] = rat_spr_save [i][j][depth][num_spr];
+                          
+                          // update rat_depth
+                          rat_depth[i][j] = depth;
+                          
+                          break;
+                        }
+                        // case EVENT_TYPE_EXCEPTION               :
+                        // case EVENT_TYPE_SPR_ACCESS              :
+                        // case EVENT_TYPE_MSYNC                   :
+                        // case EVENT_TYPE_PSYNC                   :
+                        // case EVENT_TYPE_CSYNC                   :
+                      default :
+                        {
+                          // nothing
+                          break;
+                        }
+                      }
+                  
+                  }
+              }
+
+	// =====================================================
+	// ====[ INSERT ]=======================================
+	// =====================================================
+	// First : interface insert
+        // this instruction is speculative !!!
+	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+	  // Test transaction
+	  if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK  [i])
+	    {
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * INSERT [%d]",i);
+
+	      Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
+	      Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
+              Tcontrol_t save         = internal_RENAME_SAVE [i];
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end          : %d",front_end_id);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context            : %d",context_id);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * save               : %d",save);
+
+	      // Test if write and modifie RAT (RD and RE)
+
+              Tcontrol_t write_rd     = PORT_READ(in_INSERT_WRITE_RD [i]);
+              Tcontrol_t write_re     = PORT_READ(in_INSERT_WRITE_RE [i]);
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_rd           : %d",write_rd);
+	      if (write_rd == 1)
+                {
+                  Tgeneral_address_t num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [i]);
+                  Tgeneral_address_t num_reg_rd_phy = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_log     : %d",num_reg_rd_log);
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy     : %d",num_reg_rd_phy);
+
+                  rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy;
+                }
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_re           : %d",write_re);
+	      if (write_re == 1)
+                {
+                  Tspecial_address_t num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [i]);
+                  Tspecial_address_t num_reg_re_phy = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_log     : %d",num_reg_re_log);
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy     : %d",num_reg_re_phy);
+
+                  rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy;
+                }
+
+              if (save)
+                {
+                  // Need save RAT
+
+                  Tdepth_t depth = (_param->_have_port_depth       )?PORT_READ(in_RENAME_DEPTH        [i]):0;
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth old - new  : %d",depth);
+
+// #ifdef DEBUG_TEST
+//                   if (depth != ((depth_old+1)%_param->_nb_branch_speculated[front_end_id][context_id]))
+//                     throw ERRORMORPHEO(FUNCTION,toString(_("Rename : Invalid depth (old : %d, new : %d).\n"),depth_old,depth));
+// #endif
+
+                  // save GPR
+                  for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++)
+                    rat_gpr_save [front_end_id][context_id][depth][num_gpr] = rat_gpr_speculative [front_end_id][context_id][num_gpr];
+
+                  // save SPR
+                  for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++)
+                    rat_spr_save [front_end_id][context_id][depth][num_spr] = rat_spr_speculative [front_end_id][context_id][num_spr];
+
+                  // update rat_depth with new depth
+                  rat_depth[front_end_id][context_id] = depth;
+                }
+	    }
+
+	// =====================================================
+	// ====[ RETIRE ]=======================================
+	// =====================================================
+	// Second : interface retire
+	//  (because if an event on the same thread : the instruction is already renamed)
+	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+	  if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i])
+	    {
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RETIRE [%d]",i);
+
+	      // if no event : no effect, because the RAT content the most recently register
+	      // but if they have a event (exception or miss speculation), the rat must restore the oldest value
+	      // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register
+	      // the retire interface became of the Re Order Buffer, also is in program sequence !
+
+#ifdef DEBUG
+              Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
+              Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RETIRE_CONTEXT_ID   [i]):0;
+#endif
+              Tcontrol_t write_rd     = PORT_READ(in_RETIRE_WRITE_RD [i]);
+              Tcontrol_t write_re     = PORT_READ(in_RETIRE_WRITE_RE [i]);
+              Tcontrol_t restore      = PORT_READ(in_RETIRE_RESTORE  [i]);
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id       : %d",front_end_id);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id         : %d",context_id  );
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * restore            : %d",restore     );
+
+              // Test if write and have not a previous update
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_rd           : %d",write_rd);
+              if (write_rd == 1)
+                {
+#ifdef DEBUG
+                  Tgeneral_address_t num_reg_rd_log     = PORT_READ(in_RETIRE_NUM_REG_RD_LOG     [i]);
+#endif
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_log     : %d",num_reg_rd_log    );
+
+                  if (not restore)
+                    {
+#ifdef DEBUG
+                  Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]);
+#endif
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy_new : %d",num_reg_rd_phy_new);
+
+                  // rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
+                    }
+                }
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_re           : %d",write_re);
+              if (write_re == 1)
+                {
+#ifdef DEBUG
+                  Tspecial_address_t num_reg_re_log     = PORT_READ(in_RETIRE_NUM_REG_RE_LOG     [i]);
+#endif
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_log     : %d",num_reg_re_log    );
+
+                  if (not restore)
+                    {
+#ifdef DEBUG
+                  Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);
+#endif
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy_new : %d",num_reg_re_phy_new);
+
+                  // rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
+                    }
+                }
+
+	    }
+      }
+
+#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true)
+    {
+      uint32_t limit = 4;
+      
+      log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * Dump RAT (Register_Address_Translation_unit)");
+      for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+        for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+          {
+            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end[%d].context[%d] - rat_depth : %d",i,j,rat_depth[i][j]);
+          
+            for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
+              {
+                std::string str = "";
+                for (uint32_t x=0; x<limit; x++)
+                  {
+                    uint32_t index = k+x;
+                    if (index >= _param->_nb_general_register_logic)
+                      break;
+                    else
+                      str+=toString("GPR[%.4d] - %.5d | ",index,rat_gpr_speculative [i][j][index]);
+                  }
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
+              }
+
+            for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
+              for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
+                {
+                  std::string str = "";
+                  for (uint32_t x=0; x<limit; x++)
+                    {
+                      uint32_t index = k+x;
+                      if (index >= _param->_nb_general_register_logic)
+                        break;
+                      else
+                        str+=toString("GPR_%d[%.4d] - %.5d | ",l,index,rat_gpr_save [i][j][l][index]);
+                    }
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
+                }
+            
+            for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
+              {
+                std::string str = "";
+                
+                for (uint32_t x=0; x<limit; x++)
+                  {
+                    uint32_t index = k+x;
+                    if (index >= _param->_nb_special_register_logic)
+                      break;
+                    else
+                      str+=toString("SPR[%.4d] - %.5d | ",index,rat_spr_speculative [i][j][index]);
+                  }
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
+              }
+
+            for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
+              for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
+                {
+                  std::string str = "";
+                  for (uint32_t x=0; x<limit; x++)
+                    {
+                      uint32_t index = k+x;
+                      if (index >= _param->_nb_special_register_logic)
+                        break;
+                      else
+                        str+=toString("SPR_%d[%.4d] - %.5d | ",l,index,rat_spr_save [i][j][l][index]);
+                    }
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
+                }
+
+          }
+    }
+#endif
+
+    log_end(Register_Address_Translation_unit,FUNCTION);
+  };
+
+}; // end namespace register_address_translation_unit
+}; // end namespace register_translation_unit
+}; // end namespace rename_unit
+}; // end namespace ooo_engine
+}; // end namespace multi_ooo_engine
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,5 +1,0 @@
-Register_translation_unit_Glue
-1	4	*2	# nb_inst_insert
-1	4	*2	# nb_inst_retire
-5  	5  	*2	# size_general_register
-2 	2 	*2	# size_special_register
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,5 @@
+Register_translation_unit_Glue
+1	4	*2	# nb_inst_insert
+1	4	*2	# nb_inst_retire
+5  	5  	*2	# size_general_register
+2 	2 	*2	# size_special_register
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Register_translation_unit
-1	1	*2	#nb_front_end       
-1	1	*2	#nb_context          [nb_front_end]
-64	64	*2	#nb_general_register
-4	4	*2	#nb_special_register
-1	1	*4	#nb_inst_insert     
-1	1	*4	#nb_inst_retire     
-1	1	*4	#nb_reg_free        
-1	1	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Register_translation_unit
-1	1	*2	#nb_front_end       
-1	1	*2	#nb_context          [nb_front_end]
-64	64	*2	#nb_general_register
-16	16	*2	#nb_special_register
-1	4	*4	#nb_inst_insert     
-1	4	*4	#nb_inst_retire     
-1	4	*4	#nb_reg_free        
-8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1a.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Register_translation_unit
-1	1	*2	#nb_front_end       
-1	1	*2	#nb_context          [nb_front_end]
-64	64	*2	#nb_general_register
-16	16	*2	#nb_special_register
-1	4	*4	#nb_inst_insert     
-1	4	*4	#nb_inst_retire     
-1	4	*4	#nb_reg_free        
-8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4a.cfg	(revision 144)
+++ 	(revision )
@@ -1,12 +1,0 @@
-Register_translation_unit
-4	4	*2	#nb_front_end       
-1	1	*2	#nb_context          [0] [nb_front_end]
-1	1	*2	#nb_context          [1] [nb_front_end]
-1	1	*2	#nb_context          [2] [nb_front_end]
-1	1	*2	#nb_context          [3] [nb_front_end]
-256	256	*2	#nb_general_register
-32	32	*2	#nb_special_register
-4	4	*4	#nb_inst_insert     
-4	4	*4	#nb_inst_retire     
-4	4	*4	#nb_reg_free        
-8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4b.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4b.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Register_translation_unit
-1	1	*2	#nb_front_end       
-4	4	*2	#nb_context          [0] [nb_front_end]
-256	256	*2	#nb_general_register
-32	32	*2	#nb_special_register
-4	4	*4	#nb_inst_insert     
-4	4	*4	#nb_inst_retire     
-4	4	*4	#nb_reg_free        
-8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4c.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4c.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Register_translation_unit
-2	2	*2	#nb_front_end       
-2	2	*2	#nb_context          [0] [nb_front_end]
-2	2	*2	#nb_context          [1] [nb_front_end]
-256	256	*2	#nb_general_register
-32	32	*2	#nb_special_register
-4	4	*4	#nb_inst_insert     
-4	4	*4	#nb_inst_retire     
-4	4	*4	#nb_reg_free        
-8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4d.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4d.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Register_translation_unit
-2	2	*2	#nb_front_end       
-1	1	*2	#nb_context          [0] [nb_front_end]
-3	3	*2	#nb_context          [1] [nb_front_end]
-256	256	*2	#nb_general_register
-32	32	*2	#nb_special_register
-4	4	*4	#nb_inst_insert     
-4	4	*4	#nb_inst_retire     
-4	4	*4	#nb_reg_free        
-8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,9 @@
+Register_translation_unit
+1	1	*2	#nb_front_end       
+1	1	*2	#nb_context          [nb_front_end]
+64	64	*2	#nb_general_register
+4	4	*2	#nb_special_register
+1	1	*4	#nb_inst_insert     
+1	1	*4	#nb_inst_retire     
+1	1	*4	#nb_reg_free        
+1	1	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_1.gen	(revision 145)
@@ -0,0 +1,9 @@
+Register_translation_unit
+1	1	*2	#nb_front_end       
+1	1	*2	#nb_context          [nb_front_end]
+64	64	*2	#nb_general_register
+16	16	*2	#nb_special_register
+1	4	*4	#nb_inst_insert     
+1	4	*4	#nb_inst_retire     
+1	4	*4	#nb_reg_free        
+8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_1a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_1a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_1a.gen	(revision 145)
@@ -0,0 +1,9 @@
+Register_translation_unit
+1	1	*2	#nb_front_end       
+1	1	*2	#nb_context          [nb_front_end]
+64	64	*2	#nb_general_register
+16	16	*2	#nb_special_register
+1	4	*4	#nb_inst_insert     
+1	4	*4	#nb_inst_retire     
+1	4	*4	#nb_reg_free        
+8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4a.gen	(revision 145)
@@ -0,0 +1,12 @@
+Register_translation_unit
+4	4	*2	#nb_front_end       
+1	1	*2	#nb_context          [0] [nb_front_end]
+1	1	*2	#nb_context          [1] [nb_front_end]
+1	1	*2	#nb_context          [2] [nb_front_end]
+1	1	*2	#nb_context          [3] [nb_front_end]
+256	256	*2	#nb_general_register
+32	32	*2	#nb_special_register
+4	4	*4	#nb_inst_insert     
+4	4	*4	#nb_inst_retire     
+4	4	*4	#nb_reg_free        
+8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4b.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4b.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4b.gen	(revision 145)
@@ -0,0 +1,9 @@
+Register_translation_unit
+1	1	*2	#nb_front_end       
+4	4	*2	#nb_context          [0] [nb_front_end]
+256	256	*2	#nb_general_register
+32	32	*2	#nb_special_register
+4	4	*4	#nb_inst_insert     
+4	4	*4	#nb_inst_retire     
+4	4	*4	#nb_reg_free        
+8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4c.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4c.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4c.gen	(revision 145)
@@ -0,0 +1,10 @@
+Register_translation_unit
+2	2	*2	#nb_front_end       
+2	2	*2	#nb_context          [0] [nb_front_end]
+2	2	*2	#nb_context          [1] [nb_front_end]
+256	256	*2	#nb_general_register
+32	32	*2	#nb_special_register
+4	4	*4	#nb_inst_insert     
+4	4	*4	#nb_inst_retire     
+4	4	*4	#nb_reg_free        
+8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4d.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4d.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4d.gen	(revision 145)
@@ -0,0 +1,10 @@
+Register_translation_unit
+2	2	*2	#nb_front_end       
+1	1	*2	#nb_context          [0] [nb_front_end]
+3	3	*2	#nb_context          [1] [nb_front_end]
+256	256	*2	#nb_general_register
+32	32	*2	#nb_special_register
+4	4	*4	#nb_inst_insert     
+4	4	*4	#nb_inst_retire     
+4	4	*4	#nb_reg_free        
+8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_mono_thread.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_mono_thread.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Stat_List_unit
-1	1	*2	#_nb_front_end          
-1	1	*2	#_nb_context            
-64	64	*2	#_nb_general_register   
-16	16	*2	#_nb_special_register   
-1	4	*2	#_nb_inst_insert        
-1	4	*2	#_nb_inst_retire        
-1	4	*2	#_nb_reg_free           
-4	4	*2	#_nb_bank               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_multi_thread.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_multi_thread.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Stat_List_unit
-2	2	*2	#_nb_front_end          
-1	3	+1	#_nb_context            [0]
-2	2	*2	#_nb_context            [1]
-256	256	*2	#_nb_general_register   
-64	64	*2	#_nb_special_register   
-4	4	*2	#_nb_inst_insert        
-4	4	*2	#_nb_inst_retire        
-4	4	*2	#_nb_reg_free           
-4	8	*2	#_nb_bank               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/configuration/config_mono_thread.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/configuration/config_mono_thread.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/configuration/config_mono_thread.gen	(revision 145)
@@ -0,0 +1,9 @@
+Stat_List_unit
+1	1	*2	#_nb_front_end          
+1	1	*2	#_nb_context            
+64	64	*2	#_nb_general_register   
+16	16	*2	#_nb_special_register   
+1	4	*2	#_nb_inst_insert        
+1	4	*2	#_nb_inst_retire        
+1	4	*2	#_nb_reg_free           
+4	4	*2	#_nb_bank               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/configuration/config_multi_thread.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/configuration/config_multi_thread.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/configuration/config_multi_thread.gen	(revision 145)
@@ -0,0 +1,10 @@
+Stat_List_unit
+2	2	*2	#_nb_front_end          
+1	3	+1	#_nb_context            [0]
+2	2	*2	#_nb_context            [1]
+256	256	*2	#_nb_general_register   
+64	64	*2	#_nb_special_register   
+4	4	*2	#_nb_inst_insert        
+4	4	*2	#_nb_inst_retire        
+4	4	*2	#_nb_reg_free           
+4	8	*2	#_nb_bank               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp	(revision 145)
@@ -17,4 +17,39 @@
 namespace register_translation_unit {
 namespace stat_list_unit {
+
+  
+#if (DEBUG >= DEBUG_TRACE)
+# define dump_stat_list                                                 \
+  do                                                                    \
+    {                                                                   \
+      log_printf(TRACE,Stat_List_unit,FUNCTION,"  * Dump Stat List");   \
+      log_printf(TRACE,Stat_List_unit,FUNCTION,"    * reg_GPR_PTR_FREE : %d",reg_GPR_PTR_FREE); \
+      log_printf(TRACE,Stat_List_unit,FUNCTION,"    * reg_SPR_PTR_FREE : %d",reg_SPR_PTR_FREE); \
+                                                                        \
+      for (uint32_t i=0; i<_param->_nb_bank; i++)                       \
+        for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) \
+          log_printf(TRACE,Stat_List_unit,FUNCTION,"    * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d", \
+                     i,                                                 \
+                     j,                                                 \
+                     (i<<_param->_shift_gpr)|j,                         \
+                     gpr_stat_list[i][j]._is_free,                      \
+                     gpr_stat_list[i][j]._is_link,                      \
+                     gpr_stat_list[i][j]._is_use                        \
+                     );                                                 \
+      for (uint32_t i=0; i<_param->_nb_bank; i++)                       \
+        for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) \
+          log_printf(TRACE,Stat_List_unit,FUNCTION,"    * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d", \
+                     i,                                                 \
+                     j,                                                 \
+                     (i<<_param->_shift_spr)|j,                         \
+                     spr_stat_list[i][j]._is_free,                      \
+                     spr_stat_list[i][j]._is_link,                      \
+                     spr_stat_list[i][j]._is_use                        \
+                     );                                                 \
+    }                                                                   \
+  while (0)
+#else
+# define dump_stat_list
+#endif
 
 
@@ -107,5 +142,5 @@
             for (uint32_t i=0; i<_param->_nb_bank; i++)
               for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++)
-                if (not gpr_stat_list [i][j]._is_free)
+                if (not (gpr_stat_list [i][j]._is_free or gpr_stat_list [i][j].can_free()))
                   list_gpr_not_free+=toString((i<<_param->_shift_gpr)|j)+" ";   
 
@@ -114,6 +149,12 @@
             for (uint32_t i=0; i<_param->_nb_bank; i++)
               for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++)
-                if (not spr_stat_list [i][j]._is_free)
+                if (not (spr_stat_list [i][j]._is_free or spr_stat_list [i][j].can_free()))
                   list_spr_not_free+=toString((i<<_param->_shift_spr)|j)+" ";   
+
+          if (error_nb_gpr_free     or
+              error_nb_spr_free     or
+              error_rob_nb_gpr_free or
+              error_rob_nb_spr_free)
+            dump_stat_list;
 
           if (error_nb_gpr_free)
@@ -334,36 +375,6 @@
 
 
-#if (DEBUG >= DEBUG_TRACE)
-    {
-      log_printf(TRACE,Stat_List_unit,FUNCTION,"  * Dump Stat List");
-      log_printf(TRACE,Stat_List_unit,FUNCTION,"    * reg_GPR_PTR_FREE : %d",reg_GPR_PTR_FREE);
-      log_printf(TRACE,Stat_List_unit,FUNCTION,"    * reg_SPR_PTR_FREE : %d",reg_SPR_PTR_FREE);
-      
-      for (uint32_t i=0; i<_param->_nb_bank; i++)
-        for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++)
-          log_printf(TRACE,Stat_List_unit,FUNCTION,"    * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d",
-                     i,
-                     j,
-                     (i<<_param->_shift_gpr)|j,
-                     gpr_stat_list[i][j]._is_free,
-                     gpr_stat_list[i][j]._is_link,
-                     gpr_stat_list[i][j]._is_use// ,
-//                      gpr_stat_list[i][j]._is_valid,
-//                      gpr_stat_list[i][j]._counter
-                     );
-      for (uint32_t i=0; i<_param->_nb_bank; i++)
-        for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++)
-          log_printf(TRACE,Stat_List_unit,FUNCTION,"    * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d",
-                     i,
-                     j,
-                     (i<<_param->_shift_spr)|j,
-                     spr_stat_list[i][j]._is_free,
-                     spr_stat_list[i][j]._is_link,
-                     spr_stat_list[i][j]._is_use// ,
-//                      spr_stat_list[i][j]._is_valid,
-//                      spr_stat_list[i][j]._counter
-                     );
-    }
-#endif
+    dump_stat_list;
+
 
 #ifdef DEBUG_TEST
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Register_translation_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Register_translation_unit.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Register_translation_unit.h	(revision 145)
@@ -144,4 +144,9 @@
   public    : SC_IN (Tdepth_t          )  ***  in_RETIRE_EVENT_DEPTH       ;//[nb_front_end][nb_context]
 
+    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MIN                ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MAX                ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_DEPTH_FULL               ;//[nb_front_end][nb_context]
+
     // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 #ifdef DEBUG_TEST
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp	(revision 145)
@@ -123,10 +123,10 @@
       ALLOC1_SIGNAL_IN ( in_RETIRE_FRONT_END_ID      ,"front_end_id"      ,Tcontext_t        ,_param->_size_front_end_id          );
       ALLOC1_SIGNAL_IN ( in_RETIRE_CONTEXT_ID        ,"context_id"        ,Tcontext_t        ,_param->_size_context_id            );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RA           ,"read_ra"           ,Tcontrol_t        ,1                                   );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RA_PHY    ,"num_reg_ra_phy"    ,Tgeneral_address_t,_param->_size_general_register      );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RB           ,"read_rb"           ,Tcontrol_t        ,1                                   );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RB_PHY    ,"num_reg_rb_phy"    ,Tgeneral_address_t,_param->_size_general_register      );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RC           ,"read_rc"           ,Tcontrol_t        ,1                                   );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RC_PHY    ,"num_reg_rc_phy"    ,Tspecial_address_t,_param->_size_special_register      );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RA           ,"read_ra"           ,Tcontrol_t        ,1                                   );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RA_PHY    ,"num_reg_ra_phy"    ,Tgeneral_address_t,_param->_size_general_register      );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RB           ,"read_rb"           ,Tcontrol_t        ,1                                   );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RB_PHY    ,"num_reg_rb_phy"    ,Tgeneral_address_t,_param->_size_general_register      );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RC           ,"read_rc"           ,Tcontrol_t        ,1                                   );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RC_PHY    ,"num_reg_rc_phy"    ,Tspecial_address_t,_param->_size_special_register      );
       ALLOC1_SIGNAL_IN ( in_RETIRE_WRITE_RD          ,"write_rd"          ,Tcontrol_t        ,1                                   );
       ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RD_LOG    ,"num_reg_rd_log"    ,Tgeneral_address_t,_param->_size_general_register_logic);
@@ -155,4 +155,15 @@
 
       ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
+    }
+
+    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);
+
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN                        ,"MIN"                        ,Tdepth_t         ,_param->_size_depth                  ,_param->_nb_front_end, _param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX                        ,"MAX"                        ,Tdepth_t         ,_param->_size_depth                  ,_param->_nb_front_end, _param->_nb_context[it1]); 
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL                       ,"FULL"                       ,Tcontrol_t       ,1                                    ,_param->_nb_front_end, _param->_nb_context[it1]); 
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]);
     }
 
@@ -429,4 +440,24 @@
                                 dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_DEPTH");
               }
+          }
+
+      for (uint32_t i=0; i<_param->_nb_front_end; i++)
+        for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+          {
+            dest = _name;
+            
+#ifdef POSITION
+            _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j),
+                                       dest,"depth_"+toString(i)+"_"+toString(j));
+#endif     
+            if (_param->_have_port_depth)
+              {
+	    PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" ,
+                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" );
+	    PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" ,
+                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" );
+              }
+	    PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL",
+                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL");
           }
     }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp	(revision 145)
@@ -102,4 +102,8 @@
         DELETE2_SIGNAL_COND( in_RETIRE_EVENT_DEPTH          ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth     ,_param->_rat_scheme == RAT_DEPTH_SAVE);
 
+        DELETE2_SIGNAL     ( in_DEPTH_MIN                   ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth);
+        DELETE2_SIGNAL     ( in_DEPTH_MAX                   ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth);
+        DELETE2_SIGNAL     ( in_DEPTH_FULL                  ,_param->_nb_front_end,_param->_nb_context[it1],1                  );
+
 #ifdef DEBUG_TEST
         DELETE0_SIGNAL     ( in_INFO_ROB_EMPTY  ,1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/config_mono_front_end.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/config_mono_front_end.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Rename_select
-1	1	+1	# nb_front_end             
-1	1	+1	# nb_context            [0] [nb_front_end]
-1	1	+1	# max_branch_speculated    
-32	32	*2	# size_general_data        
-1	4	*4	# nb_inst_rename           
-1	4	*4	# nb_inst_decod         [0] [nb_front_end]
-1	1	*4	# nb_front_end_select      
-0	1	+1	# priority                 
-0	1	+1	# load_balancing           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/config_multi_front_end.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/config_multi_front_end.cfg	(revision 144)
+++ 	(revision )
@@ -1,16 +1,0 @@
-Rename_select
-4	4	+1	# nb_front_end             
-2	2	+1	# nb_context            [0] [nb_front_end]
-4	4	+1	# nb_context            [1] [nb_front_end]
-3	3	+1	# nb_context            [2] [nb_front_end]
-1	1	+1	# nb_context            [3] [nb_front_end]
-1	1	+1	# max_branch_speculated    
-32	32	*2	# size_general_data        
-4	4	*4	# nb_inst_rename           
-3	3	*4	# nb_inst_decod         [0] [nb_front_end]
-1	1	*4	# nb_inst_decod         [1] [nb_front_end]
-2	2	*4	# nb_inst_decod         [2] [nb_front_end]
-4	4	*4	# nb_inst_decod         [3] [nb_front_end]
-1	4	+1	# nb_front_end_select      
-0	1	+1	# priority                 
-0	1	+1	# load_balancing           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/configuration/config_mono_front_end.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/configuration/config_mono_front_end.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/configuration/config_mono_front_end.gen	(revision 145)
@@ -0,0 +1,10 @@
+Rename_select
+1	1	+1	# nb_front_end             
+1	1	+1	# nb_context            [0] [nb_front_end]
+1	1	+1	# max_branch_speculated    
+32	32	*2	# size_general_data        
+1	4	*4	# nb_inst_rename           
+1	4	*4	# nb_inst_decod         [0] [nb_front_end]
+1	1	*4	# nb_front_end_select      
+0	1	+1	# priority                 
+0	1	+1	# load_balancing           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/configuration/config_multi_front_end.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/configuration/config_multi_front_end.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/configuration/config_multi_front_end.gen	(revision 145)
@@ -0,0 +1,16 @@
+Rename_select
+4	4	+1	# nb_front_end             
+2	2	+1	# nb_context            [0] [nb_front_end]
+4	4	+1	# nb_context            [1] [nb_front_end]
+3	3	+1	# nb_context            [2] [nb_front_end]
+1	1	+1	# nb_context            [3] [nb_front_end]
+1	1	+1	# max_branch_speculated    
+32	32	*2	# size_general_data        
+4	4	*4	# nb_inst_rename           
+3	3	*4	# nb_inst_decod         [0] [nb_front_end]
+1	1	*4	# nb_inst_decod         [1] [nb_front_end]
+2	2	*4	# nb_inst_decod         [2] [nb_front_end]
+4	4	*4	# nb_inst_decod         [3] [nb_front_end]
+1	4	+1	# nb_front_end_select      
+0	1	+1	# priority                 
+0	1	+1	# load_balancing           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,7 +1,0 @@
-Rename_unit_Glue
-1	1	+1	# nb_front_end          
-1	1	+1	# nb_context     [0] [nb_front_end]
-1	1	+1	# nb_inst_insert        
-1	1	+1	# nb_inst_retire        
-32	32	+1	# size_general_data
-2	2	+1	# size_special_register
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,7 @@
+Rename_unit_Glue
+1	1	+1	# nb_front_end          
+1	1	+1	# nb_context     [0] [nb_front_end]
+1	1	+1	# nb_inst_insert        
+1	1	+1	# nb_inst_retire        
+32	32	+1	# size_general_data
+2	2	+1	# size_special_register
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h	(revision 145)
@@ -69,4 +69,5 @@
   public    : SC_OUT(Tcontext_t        )   ** out_INSERT_CONTEXT_ID                             ;//[nb_inst_insert]
   public    : SC_OUT(Tdepth_t          )   ** out_INSERT_DEPTH                                  ;//[nb_inst_insert]
+  public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_SAVE_RAT                               ;//[nb_inst_insert]
   public    : SC_OUT(Ttype_t           )   ** out_INSERT_TYPE                                   ;//[nb_inst_insert]
   public    : SC_OUT(Toperation_t      )   ** out_INSERT_OPERATION                              ;//[nb_inst_insert]
@@ -82,4 +83,5 @@
   public    : SC_IN (Tcontext_t        )   **  in_INSERT_RENAME_SELECT_CONTEXT_ID               ;//[nb_inst_insert]
   public    : SC_IN (Tdepth_t          )   **  in_INSERT_RENAME_SELECT_DEPTH                    ;//[nb_inst_insert]
+  public    : SC_IN (Tcontrol_t        )   **  in_INSERT_RENAME_SELECT_SAVE_RAT                 ;//[nb_inst_insert]
   public    : SC_IN (Ttype_t           )   **  in_INSERT_RENAME_SELECT_TYPE                     ;//[nb_inst_insert]
   public    : SC_IN (Toperation_t      )   **  in_INSERT_RENAME_SELECT_OPERATION                ;//[nb_inst_insert]
@@ -94,4 +96,5 @@
   public    : SC_OUT(Tcontext_t        )   ** out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID        ;//[nb_inst_insert]
   public    : SC_OUT(Tdepth_t          )   ** out_INSERT_REGISTER_TRANSLATION_DEPTH             ;//[nb_inst_insert]
+  public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_REGISTER_TRANSLATION_SAVE_RAT          ;//[nb_inst_insert]
   public    : SC_IN (Tspecial_address_t)   **  in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW;//[nb_inst_insert]
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp	(revision 145)
@@ -163,6 +163,10 @@
 	    if (_param->_have_port_context_id)
 	    sensitive << (*(in_INSERT_RENAME_SELECT_CONTEXT_ID                [i]));
-            if (_param->_have_port_depth and (_param->_rat_scheme == RAT_DEPTH_SAVE))
+            if (_param->_rat_scheme == RAT_DEPTH_SAVE)
+              {
+            if (_param->_have_port_depth)
 	    sensitive << (*(in_INSERT_RENAME_SELECT_DEPTH                     [i]));
+	    sensitive << (*(in_INSERT_RENAME_SELECT_SAVE_RAT                  [i]));
+              }
 	    sensitive << (*(in_INSERT_RENAME_SELECT_TYPE                      [i]))
 		      << (*(in_INSERT_RENAME_SELECT_OPERATION                 [i]))
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp	(revision 145)
@@ -66,4 +66,5 @@
       ALLOC1_SIGNAL_OUT     (out_INSERT_CONTEXT_ID                             ,"CONTEXT_ID"                             ,Tcontext_t        ,_param->_size_context_id);
       ALLOC1_SIGNAL_OUT_COND(out_INSERT_DEPTH                                  ,"DEPTH"                                  ,Tdepth_t          ,_param->_size_depth,_param->_rat_scheme == RAT_DEPTH_SAVE);
+      ALLOC1_SIGNAL_OUT_COND(out_INSERT_SAVE_RAT                               ,"SAVE_RAT"                               ,Tcontrol_t        ,1,_param->_rat_scheme == RAT_DEPTH_SAVE);
       ALLOC1_SIGNAL_OUT     (out_INSERT_TYPE                                   ,"TYPE"                                   ,Ttype_t           ,_param->_size_type);
       ALLOC1_SIGNAL_OUT     (out_INSERT_OPERATION                              ,"OPERATION"                              ,Toperation_t      ,_param->_size_operation);
@@ -79,4 +80,5 @@
       ALLOC1_SIGNAL_IN      ( in_INSERT_RENAME_SELECT_CONTEXT_ID               ,"RENAME_SELECT_CONTEXT_ID"               ,Tcontext_t        ,_param->_size_context_id);
       ALLOC1_SIGNAL_IN_COND ( in_INSERT_RENAME_SELECT_DEPTH                    ,"RENAME_SELECT_DEPTH"                    ,Tdepth_t          ,_param->_size_depth,_param->_rat_scheme == RAT_DEPTH_SAVE);
+      ALLOC1_SIGNAL_IN_COND ( in_INSERT_RENAME_SELECT_SAVE_RAT                 ,"RENAME_SELECT_SAVE_RAT"                 ,Tcontrol_t        ,1,_param->_rat_scheme == RAT_DEPTH_SAVE);
       ALLOC1_SIGNAL_IN      ( in_INSERT_RENAME_SELECT_TYPE                     ,"RENAME_SELECT_TYPE"                     ,Ttype_t           ,_param->_size_type);
       ALLOC1_SIGNAL_IN      ( in_INSERT_RENAME_SELECT_OPERATION                ,"RENAME_SELECT_OPERATION"                ,Toperation_t      ,_param->_size_operation);
@@ -91,4 +93,5 @@
       ALLOC1_SIGNAL_OUT     (out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID        ,"REGISTER_TRANSLATION_CONTEXT_ID"        ,Tcontext_t        ,_param->_size_context_id);
       ALLOC1_SIGNAL_OUT_COND(out_INSERT_REGISTER_TRANSLATION_DEPTH             ,"REGISTER_TRANSLATION_DEPTH"             ,Tdepth_t          ,_param->_size_depth,_param->_rat_scheme == RAT_DEPTH_SAVE);
+      ALLOC1_SIGNAL_OUT_COND(out_INSERT_REGISTER_TRANSLATION_SAVE_RAT          ,"REGISTER_TRANSLATION_SAVE_RAT"          ,Tcontrol_t        ,1,_param->_rat_scheme == RAT_DEPTH_SAVE);
       ALLOC1_SIGNAL_IN      ( in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW,"REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_size_special_register);
       ALLOC1_SIGNAL_OUT     (out_INSERT_LOAD_STORE_QUEUE_POINTER_VAL           ,"LOAD_STORE_QUEUE_POINTER_VAL"           ,Tcontrol_t        ,1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert.cpp	(revision 145)
@@ -32,5 +32,6 @@
 	Tcontext_t         FRONT_END_ID       = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_RENAME_SELECT_FRONT_END_ID [i]):0;
 	Tcontext_t         CONTEXT_ID         = (_param->_have_port_context_id  )?PORT_READ(in_INSERT_RENAME_SELECT_CONTEXT_ID   [i]):0;
-	Tdepth_t           DEPTH              = ((_param->_rat_scheme == RAT_DEPTH_SAVE) and _param->_have_port_depth)?PORT_READ(in_INSERT_RENAME_SELECT_DEPTH [i]):0;
+	Tdepth_t           DEPTH              = ((_param->_rat_scheme == RAT_DEPTH_SAVE) and _param->_have_port_depth)?PORT_READ(in_INSERT_RENAME_SELECT_DEPTH    [i]):0;
+	Tcontrol_t         SAVE_RAT           = ( _param->_rat_scheme == RAT_DEPTH_SAVE                              )?PORT_READ(in_INSERT_RENAME_SELECT_SAVE_RAT [i]):0;
 	Ttype_t            TYPE               = PORT_READ(in_INSERT_RENAME_SELECT_TYPE                      [i]);
 	Toperation_t       OPERATION          = PORT_READ(in_INSERT_RENAME_SELECT_OPERATION                 [i]);
@@ -97,9 +98,14 @@
 	PORT_WRITE(out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID       [i],CONTEXT_ID        );
 	PORT_WRITE(out_INSERT_LOAD_STORE_QUEUE_POINTER_CONTEXT_ID   [i],CONTEXT_ID        );
-	  }
-        if (_param->_have_port_depth and (_param->_rat_scheme == RAT_DEPTH_SAVE))
-	  {
+	  }	
+        if (_param->_rat_scheme == RAT_DEPTH_SAVE)
+          {
+        if (_param->_have_port_depth)
+          {
 	PORT_WRITE(out_INSERT_DEPTH                                 [i],DEPTH             );
 	PORT_WRITE(out_INSERT_REGISTER_TRANSLATION_DEPTH            [i],DEPTH             );
+          }
+	PORT_WRITE(out_INSERT_SAVE_RAT                              [i],SAVE_RAT          );
+	PORT_WRITE(out_INSERT_REGISTER_TRANSLATION_SAVE_RAT         [i],SAVE_RAT          );
           }
 	PORT_WRITE(out_INSERT_TYPE                                  [i],TYPE              );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,20 +1,0 @@
-Rename_unit
-1	1	+1	# nb_front_end                     
-1	1	+1	# nb_context                       [0]    [nb_front_end]
-1	1	+1	# nb_inst_decod                    [0]    [nb_front_end]
-1	1	+1	# nb_inst_insert                   
-1	1	+1	# nb_inst_retire                   
-1	1	+1	# nb_load_store_queue              
-2	2	+1	# size_store_queue                 [0]    [nb_load_store_queue]
-1	1	+1	# size_load_queue                  [0]    [nb_load_store_queue]
-1	1	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
-1	1	+1	# rename_select_priority           
-1	1	+1	# rename_select_load_balancing     
-1	1	+1	# rename_select_nb_front_end_select
-1 	1	+1	# max_branch_speculated            
-32	32	+1	# size_general_data                
-64	64	+1	# nb_general_register              
-4	4	+1	# nb_special_register              
-1	1	+1	# nb_reg_free                      
-1	1	+1	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_1a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_1a.cfg	(revision 144)
+++ 	(revision )
@@ -1,20 +1,0 @@
-Rename_unit
-1	1	+1	# nb_front_end                     
-1	1	+1	# nb_context                       [0]    [nb_front_end]
-4	4	+1	# nb_inst_decod                    [0]    [nb_front_end]
-4	4	+1	# nb_inst_insert                   
-4	4	+1	# nb_inst_retire                   
-1	1	+1	# nb_load_store_queue              
-8	8	+1	# size_store_queue                 [0]    [nb_load_store_queue]
-8	8	+1	# size_load_queue                  [0]    [nb_load_store_queue]
-8	8	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
-1	1	+1	# rename_select_priority           
-1	1	+1	# rename_select_load_balancing     
-1	1	+1	# rename_select_nb_front_end_select
-4 	4	+1	# max_branch_speculated            
-32	32	+1	# size_general_data                
-64	64	+1	# nb_general_register              
-8	8	+1	# nb_special_register              
-2	2	+1	# nb_reg_free                      
-4	8	*2	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4a.cfg	(revision 144)
+++ 	(revision )
@@ -1,23 +1,0 @@
-Rename_unit
-1	1	+1	# nb_front_end                     
-4	4	+1	# nb_context                       [0]    [nb_front_end]
-4	4	+1	# nb_inst_decod                    [0]    [nb_front_end]
-4	4	+1	# nb_inst_insert                   
-4	4	+1	# nb_inst_retire                   
-1	1	+1	# nb_load_store_queue              
-8	8	+1	# size_store_queue                 [0]    [nb_load_store_queue]
-8	8	+1	# size_load_queue                  [0]    [nb_load_store_queue]
-4	4	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
-0	0	+1	# link_load_store_unit_with_thread [0][1] [nb_front_end][nb_context]
-0	0	+1	# link_load_store_unit_with_thread [0][2] [nb_front_end][nb_context]
-0	0	+1	# link_load_store_unit_with_thread [0][3] [nb_front_end][nb_context]
-1	1	+1	# rename_select_priority           
-1	1	+1	# rename_select_load_balancing     
-1	1	+1	# rename_select_nb_front_end_select
-4 	4	+1	# max_branch_speculated            
-32	32      +1	# size_general_data                
-256	256     +1	# nb_general_register              
-16	16	+1	# nb_special_register              
-2	2	+1	# nb_reg_free                      
-8	8	*2	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4b.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4b.cfg	(revision 144)
+++ 	(revision )
@@ -1,26 +1,0 @@
-Rename_unit
-1	1	+1	# nb_front_end                     
-4	4	+1	# nb_context                       [0]    [nb_front_end]
-4	4	+1	# nb_inst_decod                    [0]    [nb_front_end]
-4	4	+1	# nb_inst_insert                   
-4	4	+1	# nb_inst_retire                   
-2	2	+1	# nb_load_store_queue              
-8	8	+1	# size_store_queue                 [0]    [nb_load_store_queue]
-4	4	+1	# size_store_queue                 [1]    [nb_load_store_queue]
-8	8	+1	# size_load_queue                  [0]    [nb_load_store_queue]
-4	4	+1	# size_load_queue                  [1]    [nb_load_store_queue]
-4	4	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
-2	2	+1	# nb_inst_memory                   [1]    [nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
-1	1	+1	# link_load_store_unit_with_thread [0][1] [nb_front_end][nb_context]
-1	1	+1	# link_load_store_unit_with_thread [0][2] [nb_front_end][nb_context]
-0	0	+1	# link_load_store_unit_with_thread [0][3] [nb_front_end][nb_context]
-1	1	+1	# rename_select_priority           
-1	1	+1	# rename_select_load_balancing     
-1	1	+1	# rename_select_nb_front_end_select
-4 	4	+1	# max_branch_speculated            
-32	32      +1	# size_general_data                
-256	256     +1	# nb_general_register              
-16	16	+1	# nb_special_register              
-2	2	+1	# nb_reg_free                      
-8	8	*2	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,20 @@
+Rename_unit
+1	1	+1	# nb_front_end                     
+1	1	+1	# nb_context                       [0]    [nb_front_end]
+1	1	+1	# nb_inst_decod                    [0]    [nb_front_end]
+1	1	+1	# nb_inst_insert                   
+1	1	+1	# nb_inst_retire                   
+1	1	+1	# nb_load_store_queue              
+2	2	+1	# size_store_queue                 [0]    [nb_load_store_queue]
+1	1	+1	# size_load_queue                  [0]    [nb_load_store_queue]
+1	1	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
+1	1	+1	# rename_select_priority           
+1	1	+1	# rename_select_load_balancing     
+1	1	+1	# rename_select_nb_front_end_select
+1 	1	+1	# max_branch_speculated            
+32	32	+1	# size_general_data                
+64	64	+1	# nb_general_register              
+4	4	+1	# nb_special_register              
+1	1	+1	# nb_reg_free                      
+1	1	+1	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_1a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_1a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_1a.gen	(revision 145)
@@ -0,0 +1,20 @@
+Rename_unit
+1	1	+1	# nb_front_end                     
+1	1	+1	# nb_context                       [0]    [nb_front_end]
+4	4	+1	# nb_inst_decod                    [0]    [nb_front_end]
+4	4	+1	# nb_inst_insert                   
+4	4	+1	# nb_inst_retire                   
+1	1	+1	# nb_load_store_queue              
+8	8	+1	# size_store_queue                 [0]    [nb_load_store_queue]
+8	8	+1	# size_load_queue                  [0]    [nb_load_store_queue]
+8	8	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
+1	1	+1	# rename_select_priority           
+1	1	+1	# rename_select_load_balancing     
+1	1	+1	# rename_select_nb_front_end_select
+4 	4	+1	# max_branch_speculated            
+32	32	+1	# size_general_data                
+64	64	+1	# nb_general_register              
+8	8	+1	# nb_special_register              
+2	2	+1	# nb_reg_free                      
+4	8	*2	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_4a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_4a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_4a.gen	(revision 145)
@@ -0,0 +1,23 @@
+Rename_unit
+1	1	+1	# nb_front_end                     
+4	4	+1	# nb_context                       [0]    [nb_front_end]
+4	4	+1	# nb_inst_decod                    [0]    [nb_front_end]
+4	4	+1	# nb_inst_insert                   
+4	4	+1	# nb_inst_retire                   
+1	1	+1	# nb_load_store_queue              
+8	8	+1	# size_store_queue                 [0]    [nb_load_store_queue]
+8	8	+1	# size_load_queue                  [0]    [nb_load_store_queue]
+4	4	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
+0	0	+1	# link_load_store_unit_with_thread [0][1] [nb_front_end][nb_context]
+0	0	+1	# link_load_store_unit_with_thread [0][2] [nb_front_end][nb_context]
+0	0	+1	# link_load_store_unit_with_thread [0][3] [nb_front_end][nb_context]
+1	1	+1	# rename_select_priority           
+1	1	+1	# rename_select_load_balancing     
+1	1	+1	# rename_select_nb_front_end_select
+4 	4	+1	# max_branch_speculated            
+32	32      +1	# size_general_data                
+256	256     +1	# nb_general_register              
+16	16	+1	# nb_special_register              
+2	2	+1	# nb_reg_free                      
+8	8	*2	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_4b.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_4b.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_4b.gen	(revision 145)
@@ -0,0 +1,26 @@
+Rename_unit
+1	1	+1	# nb_front_end                     
+4	4	+1	# nb_context                       [0]    [nb_front_end]
+4	4	+1	# nb_inst_decod                    [0]    [nb_front_end]
+4	4	+1	# nb_inst_insert                   
+4	4	+1	# nb_inst_retire                   
+2	2	+1	# nb_load_store_queue              
+8	8	+1	# size_store_queue                 [0]    [nb_load_store_queue]
+4	4	+1	# size_store_queue                 [1]    [nb_load_store_queue]
+8	8	+1	# size_load_queue                  [0]    [nb_load_store_queue]
+4	4	+1	# size_load_queue                  [1]    [nb_load_store_queue]
+4	4	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
+2	2	+1	# nb_inst_memory                   [1]    [nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
+1	1	+1	# link_load_store_unit_with_thread [0][1] [nb_front_end][nb_context]
+1	1	+1	# link_load_store_unit_with_thread [0][2] [nb_front_end][nb_context]
+0	0	+1	# link_load_store_unit_with_thread [0][3] [nb_front_end][nb_context]
+1	1	+1	# rename_select_priority           
+1	1	+1	# rename_select_load_balancing     
+1	1	+1	# rename_select_nb_front_end_select
+4 	4	+1	# max_branch_speculated            
+32	32      +1	# size_general_data                
+256	256     +1	# nb_general_register              
+16	16	+1	# nb_special_register              
+2	2	+1	# nb_reg_free                      
+8	8	*2	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h	(revision 145)
@@ -117,4 +117,5 @@
   public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_LAST_EVENT           ;//[nb_inst_insert]
   public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_IS_DELAY_SLOT        ;//[nb_inst_insert]
+  public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_SAVE_RAT             ;//[nb_inst_insert]
 #ifdef DEBUG
   public    : SC_OUT(Taddress_t        )   ** out_INSERT_ADDRESS              ;//[nb_inst_insert]
@@ -194,4 +195,9 @@
   public    : SC_IN (Tspr_t            )  ***  in_SPR_READ_SR                 ;//[nb_front_end][nb_context]
 
+    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MIN                   ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MAX                   ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_DEPTH_FULL                  ;//[nb_front_end][nb_context]
+
     // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 #ifdef DEBUG_TEST
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp	(revision 145)
@@ -15,6 +15,4 @@
 namespace ooo_engine {
 namespace rename_unit {
-
-
 
 #undef  FUNCTION
@@ -101,52 +99,53 @@
       ALLOC1_INTERFACE_BEGIN("insert",OUT,WEST , _("Instruction with physical register"), _param->_nb_inst_insert);
       
-      ALLOC1_VALACK_OUT(out_INSERT_VAL                  ,VAL);
-      ALLOC1_VALACK_IN ( in_INSERT_ACK                  ,ACK);
-      ALLOC1_SIGNAL_OUT(out_INSERT_FRONT_END_ID         ,"front_end_id"         ,Tcontext_t        ,_param->_size_front_end_id          );
-      ALLOC1_SIGNAL_OUT(out_INSERT_CONTEXT_ID           ,"context_id"           ,Tcontext_t        ,_param->_size_context_id            );
-      ALLOC1_SIGNAL_OUT(out_INSERT_DEPTH                ,"depth"                ,Tdepth_t          ,_param->_size_depth                 );
-#ifdef STATISTICS
-      ALLOC1_SIGNAL_OUT(out_INSERT_INSTRUCTION          ,"instruction"          ,uint32_t          ,32);
-#endif
-      ALLOC1_SIGNAL_OUT(out_INSERT_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type                  );
-      ALLOC1_SIGNAL_OUT(out_INSERT_OPERATION            ,"operation"            ,Toperation_t      ,_param->_size_operation             );
-      ALLOC1_SIGNAL_OUT(out_INSERT_NO_EXECUTE           ,"no_execute"           ,Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_LAST_EVENT           ,"last_event"           ,Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_IS_DELAY_SLOT        ,"is_delay_slot"        ,Tcontrol_t        ,1                                   );
+      ALLOC1_VALACK_OUT     (out_INSERT_VAL                  ,VAL);
+      ALLOC1_VALACK_IN      ( in_INSERT_ACK                  ,ACK);
+      ALLOC1_SIGNAL_OUT     (out_INSERT_FRONT_END_ID         ,"front_end_id"         ,Tcontext_t        ,_param->_size_front_end_id          );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_CONTEXT_ID           ,"context_id"           ,Tcontext_t        ,_param->_size_context_id            );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_DEPTH                ,"depth"                ,Tdepth_t          ,_param->_size_depth                 );
+#ifdef STATISTICS           
+      ALLOC1_SIGNAL_OUT     (out_INSERT_INSTRUCTION          ,"instruction"          ,uint32_t          ,32);
+#endif                      
+      ALLOC1_SIGNAL_OUT     (out_INSERT_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type                  );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_OPERATION            ,"operation"            ,Toperation_t      ,_param->_size_operation             );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NO_EXECUTE           ,"no_execute"           ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_LAST_EVENT           ,"last_event"           ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_IS_DELAY_SLOT        ,"is_delay_slot"        ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT_COND(out_INSERT_SAVE_RAT             ,"save_rat"             ,Tcontrol_t        ,1                                   ,_param->_rat_scheme == RAT_DEPTH_SAVE);
 #ifdef DEBUG
-      ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS              ,"address"              ,Taddress_t        ,_param->_size_instruction_address   );
-#endif
-      ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS_NEXT         ,"address_next"         ,Taddress_t        ,_param->_size_instruction_address   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_IMMEDIAT             ,"immediat"             ,Tgeneral_data_t   ,_param->_size_general_data          );
-      ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr       );
-      ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr       );
-      ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr        );
-      ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION_USE        ,"exception_use"        ,Texception_t      ,_param->_size_exception_use         );
-      ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION            ,"exception"            ,Texception_t      ,_param->_size_exception             );
-      ALLOC1_SIGNAL_OUT(out_INSERT_READ_RA              ,"read_ra"              ,Tcontrol_t        ,1                                   );
-#ifdef DEBUG
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RA_LOG       ,"num_reg_ra_log"       ,Tgeneral_address_t,_param->_size_general_register_logic);
-#endif
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RA_PHY       ,"num_reg_ra_phy"       ,Tgeneral_address_t,_param->_size_general_register      );
-      ALLOC1_SIGNAL_OUT(out_INSERT_READ_RB              ,"read_rb"              ,Tcontrol_t        ,1                                   );
-#ifdef DEBUG
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RB_LOG       ,"num_reg_rb_log"       ,Tgeneral_address_t,_param->_size_general_register_logic);
-#endif
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RB_PHY       ,"num_reg_rb_phy"       ,Tgeneral_address_t,_param->_size_general_register      );
-      ALLOC1_SIGNAL_OUT(out_INSERT_READ_RC              ,"read_rc"              ,Tcontrol_t        ,1                                   );
-#ifdef DEBUG
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RC_LOG       ,"num_reg_rc_log"       ,Tspecial_address_t,_param->_size_special_register_logic);
-#endif
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RC_PHY       ,"num_reg_rc_phy"       ,Tspecial_address_t,_param->_size_special_register      );
-      ALLOC1_SIGNAL_OUT(out_INSERT_WRITE_RD             ,"write_rd"             ,Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RD_LOG       ,"num_reg_rd_log"       ,Tgeneral_address_t,_param->_size_general_register_logic);
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RD_PHY_OLD   ,"num_reg_rd_phy_old"   ,Tgeneral_address_t,_param->_size_general_register      );
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RD_PHY_NEW   ,"num_reg_rd_phy_new"   ,Tgeneral_address_t,_param->_size_general_register      );
-      ALLOC1_SIGNAL_OUT(out_INSERT_WRITE_RE             ,"write_re"             ,Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_LOG       ,"num_reg_re_log"       ,Tspecial_address_t,_param->_size_special_register_logic);
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_OLD   ,"num_reg_re_phy_old"   ,Tspecial_address_t,_param->_size_special_register      );
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_NEW   ,"num_reg_re_phy_new"   ,Tspecial_address_t,_param->_size_special_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_ADDRESS              ,"address"              ,Taddress_t        ,_param->_size_instruction_address   );
+#endif                      
+      ALLOC1_SIGNAL_OUT     (out_INSERT_ADDRESS_NEXT         ,"address_next"         ,Taddress_t        ,_param->_size_instruction_address   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_IMMEDIAT             ,"immediat"             ,Tgeneral_data_t   ,_param->_size_general_data          );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr       );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr       );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr        );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_EXCEPTION_USE        ,"exception_use"        ,Texception_t      ,_param->_size_exception_use         );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_EXCEPTION            ,"exception"            ,Texception_t      ,_param->_size_exception             );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_READ_RA              ,"read_ra"              ,Tcontrol_t        ,1                                   );
+#ifdef DEBUG                
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RA_LOG       ,"num_reg_ra_log"       ,Tgeneral_address_t,_param->_size_general_register_logic);
+#endif                      
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RA_PHY       ,"num_reg_ra_phy"       ,Tgeneral_address_t,_param->_size_general_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_READ_RB              ,"read_rb"              ,Tcontrol_t        ,1                                   );
+#ifdef DEBUG                
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RB_LOG       ,"num_reg_rb_log"       ,Tgeneral_address_t,_param->_size_general_register_logic);
+#endif                      
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RB_PHY       ,"num_reg_rb_phy"       ,Tgeneral_address_t,_param->_size_general_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_READ_RC              ,"read_rc"              ,Tcontrol_t        ,1                                   );
+#ifdef DEBUG                
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RC_LOG       ,"num_reg_rc_log"       ,Tspecial_address_t,_param->_size_special_register_logic);
+#endif                      
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RC_PHY       ,"num_reg_rc_phy"       ,Tspecial_address_t,_param->_size_special_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_WRITE_RD             ,"write_rd"             ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RD_LOG       ,"num_reg_rd_log"       ,Tgeneral_address_t,_param->_size_general_register_logic);
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RD_PHY_OLD   ,"num_reg_rd_phy_old"   ,Tgeneral_address_t,_param->_size_general_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RD_PHY_NEW   ,"num_reg_rd_phy_new"   ,Tgeneral_address_t,_param->_size_general_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_WRITE_RE             ,"write_re"             ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RE_LOG       ,"num_reg_re_log"       ,Tspecial_address_t,_param->_size_special_register_logic);
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RE_PHY_OLD   ,"num_reg_re_phy_old"   ,Tspecial_address_t,_param->_size_special_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RE_PHY_NEW   ,"num_reg_re_phy_new"   ,Tspecial_address_t,_param->_size_special_register      );
 
       ALLOC1_INTERFACE_END(_param->_nb_inst_insert);
@@ -210,4 +209,15 @@
 
       ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
+    }
+
+    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);
+
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN                        ,"MIN"                        ,Tdepth_t         ,_param->_size_depth                  ,_param->_nb_front_end, _param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX                        ,"MAX"                        ,Tdepth_t         ,_param->_size_depth                  ,_param->_nb_front_end, _param->_nb_context[it1]); 
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL                       ,"FULL"                       ,Tcontrol_t       ,1                                    ,_param->_nb_front_end, _param->_nb_context[it1]); 
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]);
     }
 
@@ -440,4 +450,5 @@
 #endif
 
+          if (_param->_rat_scheme != RAT_DEPTH_SAVE)
 	  COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_SAVE_RAT"  ,
 		                   dest, "in_RENAME_"    +toString(i)+"_SAVE_RAT"  );
@@ -483,4 +494,7 @@
 	  COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+              "_DEPTH"        ,
 		                   dest, "in_INSERT_"    +toString(i)+"_RENAME_SELECT_DEPTH"        );
+          if (_param->_rat_scheme == RAT_DEPTH_SAVE)
+	  COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+              "_SAVE_RAT"     ,
+		                   dest, "in_INSERT_"    +toString(i)+"_RENAME_SELECT_SAVE_RAT"     );
 	  COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+              "_TYPE"         ,
 			           dest, "in_INSERT_"    +toString(i)+"_RENAME_SELECT_TYPE"         );
@@ -559,4 +573,7 @@
 	  COMPONENT_MAP(_component,src , "in_RENAME_"+toString(i)+                     "_DEPTH"        ,
 			           dest,"out_INSERT_"+toString(i)+"_REGISTER_TRANSLATION_DEPTH"        );
+          if (_param->_rat_scheme == RAT_DEPTH_SAVE)
+	  COMPONENT_MAP(_component,src , "in_RENAME_"+toString(i)+                     "_SAVE_RAT"     ,
+			           dest,"out_INSERT_"+toString(i)+"_REGISTER_TRANSLATION_SAVE_RAT"     );
 
 	  //  in_RENAME_SAVE_RAS          - rename_select
@@ -733,4 +750,23 @@
           }
 
+      for (uint32_t i=0; i<_param->_nb_front_end; i++)
+        for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+          {
+            dest = _name;
+            
+#ifdef POSITION
+            _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j),
+                                       dest,"depth_"+toString(i)+"_"+toString(j));
+#endif     
+            if (_param->_have_port_depth)
+              {
+	    PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" ,
+                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" );
+	    PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" ,
+                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" );
+              }
+	    PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL",
+                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL");
+          }
 
 #ifdef DEBUG_TEST
@@ -909,4 +945,7 @@
 	  PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_DEPTH"        ,
 		              dest,"out_INSERT_"+toString(i)+"_DEPTH"        );
+          if (_param->_rat_scheme == RAT_DEPTH_SAVE)
+	  PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_SAVE_RAT"     ,
+		              dest,"out_INSERT_"+toString(i)+"_SAVE_RAT"     );
 	  PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_TYPE"         ,
 		              dest,"out_INSERT_"+toString(i)+"_TYPE"         );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp	(revision 145)
@@ -75,4 +75,5 @@
         DELETE1_SIGNAL     (out_INSERT_LAST_EVENT           ,_param->_nb_inst_insert,1                                   );
         DELETE1_SIGNAL     (out_INSERT_IS_DELAY_SLOT        ,_param->_nb_inst_insert,1                                   );
+        DELETE1_SIGNAL_COND(out_INSERT_SAVE_RAT             ,_param->_nb_inst_insert,1                                   ,_param->_rat_scheme == RAT_DEPTH_SAVE);
 #ifdef DEBUG               
         DELETE1_SIGNAL     (out_INSERT_ADDRESS              ,_param->_nb_inst_insert,_param->_size_instruction_address   );
@@ -147,5 +148,9 @@
         DELETE2_SIGNAL_COND( in_RETIRE_EVENT_DEPTH          ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth     ,_param->_rat_scheme == RAT_DEPTH_SAVE);
         
-        DELETE2_SIGNAL     (in_SPR_READ_SR                  ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr);
+        DELETE2_SIGNAL     ( in_SPR_READ_SR                 ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr);
+
+        DELETE2_SIGNAL     ( in_DEPTH_MIN                   ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth);
+        DELETE2_SIGNAL     ( in_DEPTH_MAX                   ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth);
+        DELETE2_SIGNAL     ( in_DEPTH_FULL                  ,_param->_nb_front_end,_param->_nb_context[it1],1                  );
 
 #ifdef DEBUG_TEST
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,43 +1,0 @@
-OOO_Engine
-1	1	+1	# nb_front_end                                        
-1	1	+1	# nb_context                        [0]               [nb_front_end]
-1	1	+1	# nb_rename_unit                                      
-1	1	+1	# nb_execute_loop                                     
-1	1	+1	# nb_inst_decod                     [0]               [nb_front_end]
-1	1	+1	# nb_inst_insert                    [0]               [nb_rename_unit]
-1	1	+1	# nb_inst_retire                    [0]               [nb_rename_unit]
-1	1	+1	# nb_inst_execute                   [0]               [nb_execute_loop]
-1	1	+1	# nb_inst_reexecute                                   
-1	1	+1	# nb_inst_commit                                      
-1	1	+1	# nb_inst_branch_complete                             
-1	1	+1	# nb_branch_speculated              [0][0]            [nb_front_end][nb_context]
-1	1	+1	# size_nb_inst_decod  
-1	1	+1	# nb_rename_unit_select                    
-1	1	+1	# nb_execute_loop_select                   
-32	32	*2	# size_general_data                        
-2	2	*2	# size_special_data                        
-0	0	+1	# link_rename_unit_with_front_end   [0]               [nb_front_end]
-1	1	+1	# size_re_order_buffer                     
-1	1	+1	# nb_re_order_buffer_bank                  
-1	1	+1	# commit_priority                          
-1	1	+1	# commit_load_balancing                    
-1	1	+1	# size_issue_queue
-0	1	+1	# issue_queue_scheme
-1	1	+1	# nb_issue_queue_bank                      
-1	1	+1	# issue_priority                           
-1	1	+1	# issue_load_balancing                     
-1	1	+1	# size_reexecute_queue                     
-1	1	+1	# reexecute_priority                       
-1	1	+1	# reexecute_load_balancing                 
-1	1	+1	# rename_select_priority            [0]               [nb_rename_unit]
-1	1	+1	# rename_select_load_balancing      [0]               [nb_rename_unit]
-1	1	+1	# rename_select_nb_front_end_select [0]               [nb_rename_unit]
-64	64	+1	# nb_general_register               [0]               [nb_rename_unit]
-4	4	+1	# nb_special_register               [0]               [nb_rename_unit]
-1	1	+1	# nb_reg_free                       [0]               [nb_rename_unit]
-1	1	+1	# nb_rename_unit_bank               [0]               [nb_rename_unit]
-1	1	+1	# nb_load_store_queue               [0]               [nb_rename_unit]
-2	2	+1	# size_store_queue                  [0][0]            [nb_rename_unit][nb_load_store_queue]
-1	1	+1	# size_load_queue                   [0][0]            [nb_rename_unit][nb_load_store_queue]
-1	1	+1	# nb_inst_memory                    [0][0]            [nb_rename_unit][nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread  [0][0]            [nb_front_end][nb_context]           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,43 @@
+OOO_Engine
+1	1	+1	# nb_front_end                                        
+1	1	+1	# nb_context                        [0]               [nb_front_end]
+1	1	+1	# nb_rename_unit                                      
+1	1	+1	# nb_execute_loop                                     
+1	1	+1	# nb_inst_decod                     [0]               [nb_front_end]
+1	1	+1	# nb_inst_insert                    [0]               [nb_rename_unit]
+1	1	+1	# nb_inst_retire                    [0]               [nb_rename_unit]
+1	1	+1	# nb_inst_execute                   [0]               [nb_execute_loop]
+1	1	+1	# nb_inst_reexecute                                   
+1	1	+1	# nb_inst_commit                                      
+1	1	+1	# nb_inst_branch_complete                             
+1	1	+1	# nb_branch_speculated              [0][0]            [nb_front_end][nb_context]
+1	1	+1	# size_nb_inst_decod  
+1	1	+1	# nb_rename_unit_select                    
+1	1	+1	# nb_execute_loop_select                   
+32	32	*2	# size_general_data                        
+2	2	*2	# size_special_data                        
+0	0	+1	# link_rename_unit_with_front_end   [0]               [nb_front_end]
+1	1	+1	# size_re_order_buffer                     
+1	1	+1	# nb_re_order_buffer_bank                  
+1	1	+1	# commit_priority                          
+1	1	+1	# commit_load_balancing                    
+1	1	+1	# size_issue_queue
+0	1	+1	# issue_queue_scheme
+1	1	+1	# nb_issue_queue_bank                      
+1	1	+1	# issue_priority                           
+1	1	+1	# issue_load_balancing                     
+1	1	+1	# size_reexecute_queue                     
+1	1	+1	# reexecute_priority                       
+1	1	+1	# reexecute_load_balancing                 
+1	1	+1	# rename_select_priority            [0]               [nb_rename_unit]
+1	1	+1	# rename_select_load_balancing      [0]               [nb_rename_unit]
+1	1	+1	# rename_select_nb_front_end_select [0]               [nb_rename_unit]
+64	64	+1	# nb_general_register               [0]               [nb_rename_unit]
+4	4	+1	# nb_special_register               [0]               [nb_rename_unit]
+1	1	+1	# nb_reg_free                       [0]               [nb_rename_unit]
+1	1	+1	# nb_rename_unit_bank               [0]               [nb_rename_unit]
+1	1	+1	# nb_load_store_queue               [0]               [nb_rename_unit]
+2	2	+1	# size_store_queue                  [0][0]            [nb_rename_unit][nb_load_store_queue]
+1	1	+1	# size_load_queue                   [0][0]            [nb_rename_unit][nb_load_store_queue]
+1	1	+1	# nb_inst_memory                    [0][0]            [nb_rename_unit][nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread  [0][0]            [nb_front_end][nb_context]           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration/debug.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration/debug.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration/debug.gen	(revision 145)
@@ -0,0 +1,43 @@
+OOO_Engine
+1	1	+1	# nb_front_end                                        
+1	1	+1	# nb_context                        [0]               [nb_front_end]
+1	1	+1	# nb_rename_unit                                      
+1	1	+1	# nb_execute_loop                                     
+1	1	+1	# nb_inst_decod                     [0]               [nb_front_end]
+1	1	+1	# nb_inst_insert                    [0]               [nb_rename_unit]
+1	1	+1	# nb_inst_retire                    [0]               [nb_rename_unit]
+1	1	+1	# nb_inst_execute                   [0]               [nb_execute_loop]
+1	1	+1	# nb_inst_reexecute                                   
+1	1	+1	# nb_inst_commit                                      
+1	1	+1	# nb_inst_branch_complete                             
+1	1	+1	# nb_branch_speculated              [0][0]            [nb_front_end][nb_context]
+1	1	+1	# size_nb_inst_decod  
+1	1	+1	# nb_rename_unit_select                    
+1	1	+1	# nb_execute_loop_select                   
+32	32	*2	# size_general_data                        
+2	2	*2	# size_special_data                        
+0	0	+1	# link_rename_unit_with_front_end   [0]               [nb_front_end]
+1	1	+1	# size_re_order_buffer                     
+1	1	+1	# nb_re_order_buffer_bank                  
+1	1	+1	# commit_priority                          
+1	1	+1	# commit_load_balancing                    
+1	1	+1	# size_issue_queue
+1	1	+1	# issue_queue_scheme
+1	1	+1	# nb_issue_queue_bank                      
+1	1	+1	# issue_priority                           
+1	1	+1	# issue_load_balancing                     
+1	1	+1	# size_reexecute_queue                     
+1	1	+1	# reexecute_priority                       
+1	1	+1	# reexecute_load_balancing                 
+1	1	+1	# rename_select_priority            [0]               [nb_rename_unit]
+1	1	+1	# rename_select_load_balancing      [0]               [nb_rename_unit]
+1	1	+1	# rename_select_nb_front_end_select [0]               [nb_rename_unit]
+64	64	+1	# nb_general_register               [0]               [nb_rename_unit]
+4	4	+1	# nb_special_register               [0]               [nb_rename_unit]
+1	1	+1	# nb_reg_free                       [0]               [nb_rename_unit]
+1	1	+1	# nb_rename_unit_bank               [0]               [nb_rename_unit]
+1	1	+1	# nb_load_store_queue               [0]               [nb_rename_unit]
+2	2	+1	# size_store_queue                  [0][0]            [nb_rename_unit][nb_load_store_queue]
+1	1	+1	# size_load_queue                   [0][0]            [nb_rename_unit][nb_load_store_queue]
+1	1	+1	# nb_inst_memory                    [0][0]            [nb_rename_unit][nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread  [0][0]            [nb_front_end][nb_context]           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/debug.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/debug.cfg	(revision 144)
+++ 	(revision )
@@ -1,43 +1,0 @@
-OOO_Engine
-1	1	+1	# nb_front_end                                        
-1	1	+1	# nb_context                        [0]               [nb_front_end]
-1	1	+1	# nb_rename_unit                                      
-1	1	+1	# nb_execute_loop                                     
-1	1	+1	# nb_inst_decod                     [0]               [nb_front_end]
-1	1	+1	# nb_inst_insert                    [0]               [nb_rename_unit]
-1	1	+1	# nb_inst_retire                    [0]               [nb_rename_unit]
-1	1	+1	# nb_inst_execute                   [0]               [nb_execute_loop]
-1	1	+1	# nb_inst_reexecute                                   
-1	1	+1	# nb_inst_commit                                      
-1	1	+1	# nb_inst_branch_complete                             
-1	1	+1	# nb_branch_speculated              [0][0]            [nb_front_end][nb_context]
-1	1	+1	# size_nb_inst_decod  
-1	1	+1	# nb_rename_unit_select                    
-1	1	+1	# nb_execute_loop_select                   
-32	32	*2	# size_general_data                        
-2	2	*2	# size_special_data                        
-0	0	+1	# link_rename_unit_with_front_end   [0]               [nb_front_end]
-1	1	+1	# size_re_order_buffer                     
-1	1	+1	# nb_re_order_buffer_bank                  
-1	1	+1	# commit_priority                          
-1	1	+1	# commit_load_balancing                    
-1	1	+1	# size_issue_queue
-1	1	+1	# issue_queue_scheme
-1	1	+1	# nb_issue_queue_bank                      
-1	1	+1	# issue_priority                           
-1	1	+1	# issue_load_balancing                     
-1	1	+1	# size_reexecute_queue                     
-1	1	+1	# reexecute_priority                       
-1	1	+1	# reexecute_load_balancing                 
-1	1	+1	# rename_select_priority            [0]               [nb_rename_unit]
-1	1	+1	# rename_select_load_balancing      [0]               [nb_rename_unit]
-1	1	+1	# rename_select_nb_front_end_select [0]               [nb_rename_unit]
-64	64	+1	# nb_general_register               [0]               [nb_rename_unit]
-4	4	+1	# nb_special_register               [0]               [nb_rename_unit]
-1	1	+1	# nb_reg_free                       [0]               [nb_rename_unit]
-1	1	+1	# nb_rename_unit_bank               [0]               [nb_rename_unit]
-1	1	+1	# nb_load_store_queue               [0]               [nb_rename_unit]
-2	2	+1	# size_store_queue                  [0][0]            [nb_rename_unit][nb_load_store_queue]
-1	1	+1	# size_load_queue                   [0][0]            [nb_rename_unit][nb_load_store_queue]
-1	1	+1	# nb_inst_memory                    [0][0]            [nb_rename_unit][nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread  [0][0]            [nb_front_end][nb_context]           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,4 +1,0 @@
-Special_Register_unit
-1	1	+1 # nb_front_end         
-1	1	+1 # nb_context        [0] [nb_front_end]
-1	1	+1 # nb_inst_reexecute    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,4 @@
+Special_Register_unit
+1	1	+1 # nb_front_end         
+1	1	+1 # nb_context        [0] [nb_front_end]
+1	1	+1 # nb_inst_reexecute    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h	(revision 145)
@@ -208,5 +208,5 @@
   public    : SC_OUT(Tcounter_t        )  *** out_NB_INST_COMMIT_MEM               ;//[nb_front_end][nb_context]
   public    : SC_IN (Tcounter_t        )  ***  in_NB_INST_DECOD_ALL                ;//[nb_front_end][nb_context]
-                                                                                   
+
     // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~         
   public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MIN                        ;//[nb_front_end][nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h	(revision 145)
@@ -98,5 +98,4 @@
   public : uint32_t            * _rename_unit_size_front_end_id                ;//[nb_rename_unit]
   public : uint32_t            * _rename_unit_size_context_id                  ;//[nb_rename_unit]
-  public : Trat_scheme_t       * _commit_unit_rat_scheme                       ;//[nb_front_end]
   public : uint32_t              _max_nb_context                               ;
   public : uint32_t              _max_branch_speculated                        ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp	(revision 145)
@@ -534,4 +534,7 @@
             COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)                +"_IS_DELAY_SLOT" ,
                                      dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT" );
+            if (_param->_rat_scheme[i] == RAT_DEPTH_SAVE)
+            COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)                +"_SAVE_RAT"      ,
+                                     dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_SAVE_RAT"      );
 //          COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)                +"_HAVE_EVENT"    ,
 //                                   dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_HAVE_EVENT"    );
@@ -633,6 +636,4 @@
 #endif
 
-
-
             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_VAL"               ,
                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_VAL"               );
@@ -670,16 +671,16 @@
             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_LOAD_QUEUE_PTR_WRITE" ,
                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_LOAD_QUEUE_PTR_WRITE" );
-//             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_READ_RA"              ,
-//                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RA"              );
-//             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RA_PHY"       ,
-//                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RA_PHY"       );
-//             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_READ_RB"              ,
-//                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RB"              );
-//             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RB_PHY"       ,
-//                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RB_PHY"       );
-//             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_READ_RC"              ,
-//                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RC"              );
-//             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RC_PHY"       ,
-//                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RC_PHY"       );
+//          COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_READ_RA"              ,
+//                                   dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RA"              );
+//          COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RA_PHY"       ,
+//                                   dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RA_PHY"       );
+//          COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_READ_RB"              ,
+//                                   dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RB"              );
+//          COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RB_PHY"       ,
+//                                   dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RB_PHY"       );
+//          COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_READ_RC"              ,
+//                                   dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RC"              );
+//          COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RC_PHY"       ,
+//                                   dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RC_PHY"       );
             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RD_LOG"       ,
                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RD_LOG"       );
@@ -755,4 +756,36 @@
               }
         }
+
+        // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+        {
+          std::vector<uint32_t>::iterator it = _param->_link_front_end_with_rename_unit[i].begin();
+          uint32_t x = 0;
+          for (uint32_t j=0; j<_param->_nb_front_end; j++)
+            if (j == *it)
+              {
+                for (uint32_t k=0; k<_param->_nb_context[j]; k++)
+                  {
+                    dest = _name;
+                    
+#ifdef POSITION
+                    _component->interface_map (src ,"spr_read_"+toString(x)+"_"+toString(k),
+                                               dest,"spr_"     +toString(j)+"_"+toString(k));
+#endif
+
+                    if (_param->_have_port_depth)
+                      {
+                    PORT_MAP(_component,src , "in_DEPTH_"+toString(x)+"_"+toString(k)+"_MIN" ,
+                                        dest, "in_DEPTH_"+toString(j)+"_"+toString(k)+"_MIN" );
+                    PORT_MAP(_component,src , "in_DEPTH_"+toString(x)+"_"+toString(k)+"_MAX" ,
+                                        dest, "in_DEPTH_"+toString(j)+"_"+toString(k)+"_MAX" );
+                      }
+                    PORT_MAP(_component,src , "in_DEPTH_"+toString(x)+"_"+toString(k)+"_FULL",
+                                        dest, "in_DEPTH_"+toString(j)+"_"+toString(k)+"_FULL");
+                  }
+                x++;
+                ++it;
+              }
+        }
+
 
         // ~~~~~[ Interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -919,4 +952,5 @@
             //  out_RETIRE_CONTEXT_ID                - component_rename_unit
             ////out_RETIRE_RENAME_UNIT_ID            - component_rename_unit
+            //  out_RETIRE_DEPTH                     - component_rename_unit
             //  out_RETIRE_USE_STORE_QUEUE           - component_rename_unit
             //  out_RETIRE_USE_LOAD_QUEUE            - component_rename_unit
@@ -981,5 +1015,4 @@
           COMPONENT_MAP(_component,src ,"out_COMMIT_"+toString(i)+"_NUM_REG_RD" ,
                                    dest, "in_COMMIT_"+toString(i)+"_NUM_REG_RD" );
-          //@@@@@@@@@@
 	}
       
@@ -1111,24 +1144,24 @@
           }
 
-      // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
-      for (uint32_t i=0; i<_param->_nb_front_end; i++)
-        for (uint32_t j=0; j<_param->_nb_context[i]; j++)
-          {
-            dest = _name;
-#ifdef POSITION
-            _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j),
-                                       dest,"depth_"+toString(i)+"_"+toString(j));
-#endif
-
-            if (_param->_have_port_depth)
-              {
-            PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN",
-                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN");
-            PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX",
-                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX");
-              }
-            PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL",
-                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL");
-          }
+//      // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
+//      for (uint32_t i=0; i<_param->_nb_front_end; i++)
+//        for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+//          {
+//            dest = _name;
+//#ifdef POSITION
+//            _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j),
+//                                       dest,"depth_"+toString(i)+"_"+toString(j));
+//#endif
+//
+//            if (_param->_have_port_depth)
+//              {
+//            PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN",
+//                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN");
+//            PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX",
+//                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX");
+//              }
+//            PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL",
+//                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL");
+//          }
 
       // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp	(revision 145)
@@ -82,51 +82,50 @@
     log_begin(OOO_Engine,FUNCTION);
 
-    _nb_front_end                      = nb_front_end                     ;
-    _nb_context                        = nb_context                       ;
-    _nb_rename_unit                    = nb_rename_unit                   ;
-    _nb_execute_loop                   = nb_execute_loop                  ;
-    _nb_inst_decod                     = nb_inst_decod                    ;
-    _nb_inst_insert                    = nb_inst_insert                   ;
-    _nb_inst_retire                    = nb_inst_retire                   ;
-//  _nb_inst_issue                     = nb_inst_issue                    ;
-    _nb_inst_execute                   = nb_inst_execute                  ;
-    _nb_inst_reexecute                 = nb_inst_reexecute                ;
-    _nb_inst_commit                    = nb_inst_commit                   ;
-    _nb_inst_branch_complete           = nb_inst_branch_complete          ;
-    _nb_branch_speculated              = nb_branch_speculated             ;
-    _nb_rename_unit_select             = nb_rename_unit_select            ;
-    _nb_execute_loop_select            = nb_execute_loop_select           ;
-//  _size_general_data                 = size_general_data                ;
-//  _size_special_data                 = size_special_data                ;
-    _link_rename_unit_with_front_end   = link_rename_unit_with_front_end  ;
-    _size_re_order_buffer              = size_re_order_buffer             ;
-    _nb_re_order_buffer_bank           = nb_re_order_buffer_bank          ;
-    _retire_ooo_scheme                 = retire_ooo_scheme                ;
-    _commit_priority                   = commit_priority                  ;
-    _commit_load_balancing             = commit_load_balancing            ;
-    _size_issue_queue                  = size_issue_queue                 ;
-    _issue_queue_scheme                = issue_queue_scheme               ;
-    _nb_issue_queue_bank               = nb_issue_queue_bank              ;
-    _issue_priority                    = issue_priority                   ;
-    _issue_load_balancing              = issue_load_balancing             ;
-//  _table_routing                     = table_routing                    ;
-//  _table_issue_type                  = table_issue_type                 ;
-    _size_reexecute_queue              = size_reexecute_queue             ;
-    _rename_select_priority            = rename_select_priority           ;
-    _rename_select_load_balancing      = rename_select_load_balancing     ;
-    _rename_select_nb_front_end_select = rename_select_nb_front_end_select;
-    _nb_general_register               = nb_general_register              ;
-    _nb_special_register               = nb_special_register              ;
-    _rat_scheme                        = rat_scheme                       ;
-    _nb_reg_free                       = nb_reg_free                      ;
-    _nb_rename_unit_bank               = nb_rename_unit_bank              ;
-//  _size_read_counter                 = size_read_counter                ;
-    _nb_load_store_queue               = nb_load_store_queue              ;
-    _size_store_queue                  = size_store_queue                 ;
-    _size_load_queue                   = size_load_queue                  ;
-    _nb_inst_memory                    = nb_inst_memory                   ;
-    _link_load_store_unit_with_thread  = link_load_store_unit_with_thread ;
-    _implement_group                   = implement_group                  ;
-
+    _nb_front_end                        = nb_front_end                     ;
+    _nb_context                          = nb_context                       ;
+    _nb_rename_unit                      = nb_rename_unit                   ;
+    _nb_execute_loop                     = nb_execute_loop                  ;
+    _nb_inst_decod                       = nb_inst_decod                    ;
+    _nb_inst_insert                      = nb_inst_insert                   ;
+    _nb_inst_retire                      = nb_inst_retire                   ;
+//  _nb_inst_issue                       = nb_inst_issue                    ;
+    _nb_inst_execute                     = nb_inst_execute                  ;
+    _nb_inst_reexecute                   = nb_inst_reexecute                ;
+    _nb_inst_commit                      = nb_inst_commit                   ;
+    _nb_inst_branch_complete             = nb_inst_branch_complete          ;
+    _nb_branch_speculated                = nb_branch_speculated             ;
+    _nb_rename_unit_select               = nb_rename_unit_select            ;
+    _nb_execute_loop_select              = nb_execute_loop_select           ;
+//  _size_general_data                   = size_general_data                ;
+//  _size_special_data                   = size_special_data                ;
+    _link_rename_unit_with_front_end     = link_rename_unit_with_front_end  ;
+    _size_re_order_buffer                = size_re_order_buffer             ;
+    _nb_re_order_buffer_bank             = nb_re_order_buffer_bank          ;
+    _retire_ooo_scheme                   = retire_ooo_scheme                ;
+    _commit_priority                     = commit_priority                  ;
+    _commit_load_balancing               = commit_load_balancing            ;
+    _size_issue_queue                    = size_issue_queue                 ;
+    _issue_queue_scheme                  = issue_queue_scheme               ;
+    _nb_issue_queue_bank                 = nb_issue_queue_bank              ;
+    _issue_priority                      = issue_priority                   ;
+    _issue_load_balancing                = issue_load_balancing             ;
+//  _table_routing                       = table_routing                    ;
+//  _table_issue_type                    = table_issue_type                 ;
+    _size_reexecute_queue                = size_reexecute_queue             ;
+    _rename_select_priority              = rename_select_priority           ;
+    _rename_select_load_balancing        = rename_select_load_balancing     ;
+    _rename_select_nb_front_end_select   = rename_select_nb_front_end_select;
+    _nb_general_register                 = nb_general_register              ;
+    _nb_special_register                 = nb_special_register              ;
+    _rat_scheme                          = rat_scheme                       ;
+    _nb_reg_free                         = nb_reg_free                      ;
+    _nb_rename_unit_bank                 = nb_rename_unit_bank              ;
+//  _size_read_counter                   = size_read_counter                ;
+    _nb_load_store_queue                 = nb_load_store_queue              ;
+    _size_store_queue                    = size_store_queue                 ;
+    _size_load_queue                     = size_load_queue                  ;
+    _nb_inst_memory                      = nb_inst_memory                   ;
+    _link_load_store_unit_with_thread    = link_load_store_unit_with_thread ;
+    _implement_group                     = implement_group                  ;
     _nb_thread                           = nb_thread                          ;
     _translate_num_context_to_num_thread = translate_num_context_to_num_thread;
@@ -144,4 +143,5 @@
         _link_front_end_with_rename_unit[num_rename_unit].push_back(i);
       }
+
     _rename_unit_size_front_end_id                = new uint32_t    [_nb_rename_unit];
     _rename_unit_size_context_id                  = new uint32_t    [_nb_rename_unit];
@@ -197,9 +197,4 @@
           }
       }
-
-    ALLOC1(_commit_unit_rat_scheme,Trat_scheme_t,_nb_front_end);
-
-    for (uint32_t num_front_end=0; num_front_end<_nb_front_end; ++num_front_end)
-      _commit_unit_rat_scheme [num_front_end] = rat_scheme [_link_rename_unit_with_front_end [num_front_end]];
 
     _max_nb_context                = max<uint32_t>(_nb_context,_nb_front_end);
@@ -265,27 +260,28 @@
     _param_commit_unit           = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Parameters  
       (
-       _nb_front_end            ,
-       _nb_context              ,
-       _nb_rename_unit          ,
-       _size_re_order_buffer    ,
-       _nb_re_order_buffer_bank ,
-       _retire_ooo_scheme       ,
-       _nb_inst_insert          ,
-       _nb_inst_retire          ,
-       _nb_inst_commit          ,
-       _nb_inst_reexecute       ,
-       _nb_inst_branch_complete ,
-       _nb_branch_speculated    ,
-        size_nb_inst_decod      ,
-        size_general_data       ,
-        size_store_queue_ptr    ,
-        size_load_queue_ptr     ,
-        size_general_register   ,
-        size_special_register   ,
-       _commit_unit_rat_scheme  ,
-       _issue_priority          ,
-       _issue_load_balancing    ,
-       _nb_rename_unit_select   ,
-       _nb_thread               ,
+       _nb_front_end                   ,
+       _nb_context                     ,
+       _nb_rename_unit                 ,
+       _size_re_order_buffer           ,
+       _nb_re_order_buffer_bank        ,
+       _retire_ooo_scheme              ,
+       _nb_inst_insert                 ,
+       _nb_inst_retire                 ,
+       _nb_inst_commit                 ,
+       _nb_inst_reexecute              ,
+       _nb_inst_branch_complete        ,
+       _nb_branch_speculated           ,
+        size_nb_inst_decod             ,
+        size_general_data              ,
+        size_store_queue_ptr           ,
+        size_load_queue_ptr            ,
+        size_general_register          ,
+        size_special_register          ,
+       _rat_scheme                     ,
+       _link_front_end_with_rename_unit,
+       _issue_priority                 ,
+       _issue_load_balancing           ,
+       _nb_rename_unit_select          ,
+       _nb_thread                      ,
        _translate_num_context_to_num_thread
        );
@@ -430,6 +426,4 @@
     delete [] _link_front_end_with_rename_unit             ;
 
-    DELETE1(_commit_unit_rat_scheme,_nb_front_end);
-
     for (uint32_t i=0; i<_nb_rename_unit; i++)
     delete    _param_rename_unit [i]      ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_msg_error.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_msg_error.cpp	(revision 145)
@@ -36,5 +36,10 @@
           test.error(toString(_("Front_end [%d] is linked with invalid rename_unit.\n"),i));
         else
-          _is_link [x] = true;
+          {
+            if (_is_link [x])
+              test.error(toString(_("Front_end [%d] can't be connected with multiple rename_unit.\n"),i));
+            else
+              _is_link [x] = true;
+          }
       }
 
