Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-1_front_end-1_ooo_engine-1_execute_loop.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-1_front_end-1_ooo_engine-1_execute_loop.cfg	(revision 144)
+++ 	(revision )
@@ -1,46 +1,0 @@
-Core_Glue
-1	1	+1	# nb_front_end                                                                                     
-1	4	*4	# nb_context                            [0]          [nb_front_end]
-1	1	+1	# nb_ooo_engine                                                                                    
-1	1	+1	# nb_execute_loop                                                                                  
-1	1	+1	# ooo_engine_nb_front_end               [0]          [nb_ooo_engine]
-1	1	+1	# ooo_engine_nb_execute_loop            [0]          [nb_ooo_engine]
-1	1	+1	# execute_loop_nb_ooo_engine            [0]          [nb_execute_loop]
-4	4	+1	# nb_inst_decod                         [0]          [nb_front_end]   
-4	4 	+1	# front_end_nb_inst_branch_complete     [0]          [nb_front_end] 
-4	4	+1	# ooo_engine_nb_inst_branch_complete    [0]          [nb_ooo_engine]
-4	4	+1	# nb_inst_insert                        [0]          [nb_ooo_engine]  
-4	4	+1	# nb_inst_reexecute                     [0]          [nb_ooo_engine]  
-4	4	+1	# nb_inst_issue                         [0]          [nb_ooo_engine]  
-4	4	+1	# nb_inst_execute                       [0]          [nb_ooo_engine]  
-4	4	+1	# nb_read_unit                          [0]          [nb_execute_loop]
-4	4	+1	# nb_write_unit                         [0]          [nb_execute_loop]
-3	3	+1	# size_depth                                                                                       
-5	5	+1	# size_rob_ptr                                                                                     
-8	8	+1	# size_load_queue_ptr                                                                              
-8	8	+1	# size_store_queue_ptr                                                                             
-32	32	+1	# size_general_data                                                                                
-2	2	+1	# size_special_data                                                                                
-6	6	+1	# size_general_register                                                                            
-2	2	+1	# size_special_register                                                                            
-1	1	+1	# dispatch_priority                                                                                
-1	1	+1	# dispatch_load_balancing                                                                          
-1	1	+1	# table_dispatch                        [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][0][0][3] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [1][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [1][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [1][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [1][0][0][3] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][0][0][3] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [3][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [3][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [3][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [3][0][0][3] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-0	0	+1	# translate_ooo_engine_num_front_end    [0][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
-0	0	+1	# translate_ooo_engine_num_execute_loop [0][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-0	0	+1	# translate_execute_loop_num_ooo_engine [0][0]       [nb_execute_loop][execute_loop_nb_ooo_engine]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-1_ooo_engine-1_execute_loop.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-1_ooo_engine-1_execute_loop.cfg	(revision 144)
+++ 	(revision )
@@ -1,51 +1,0 @@
-Core_Glue
-4	4	+1	# nb_front_end                                                                                     
-1	1	+1	# nb_context                            [0]          [nb_front_end]
-2	2	+1	# nb_context                            [1]          [nb_front_end]
-4	4	+1	# nb_context                            [2]          [nb_front_end]
-3	3	+1	# nb_context                            [3]          [nb_front_end]
-1	1	+1	# nb_ooo_engine                                                                                    
-1	1	+1	# nb_execute_loop                                                                                  
-4	4	+1	# ooo_engine_nb_front_end               [0]          [nb_ooo_engine]
-1	1	+1	# ooo_engine_nb_execute_loop            [0]          [nb_ooo_engine]
-1	1	+1	# execute_loop_nb_ooo_engine            [0]          [nb_execute_loop]
-4	4	+1	# nb_inst_decod                         [0]          [nb_front_end]   
-2	2	+1	# nb_inst_decod                         [1]          [nb_front_end]   
-1	1	+1	# nb_inst_decod                         [2]          [nb_front_end]   
-3	3	+1	# nb_inst_decod                         [3]          [nb_front_end]   
-4	4 	+1	# front_end_nb_inst_branch_complete     [0]          [nb_front_end] 
-4	4 	+1	# front_end_nb_inst_branch_complete     [1]          [nb_front_end] 
-4	4 	+1	# front_end_nb_inst_branch_complete     [2]          [nb_front_end] 
-4	4 	+1	# front_end_nb_inst_branch_complete     [3]          [nb_front_end] 
-4	4	+1	# ooo_engine_nb_inst_branch_complete    [0]          [nb_ooo_engine]
-3	3	+1	# nb_inst_insert                        [0]          [nb_ooo_engine]  
-3	3	+1	# nb_inst_reexecute                     [0]          [nb_ooo_engine]  
-3	3	+1	# nb_inst_issue                         [0]          [nb_ooo_engine]  
-4	4	+1	# nb_inst_execute                       [0]          [nb_ooo_engine]  
-3	3	+1	# nb_read_unit                          [0]          [nb_execute_loop]
-4	4	+1	# nb_write_unit                         [0]          [nb_execute_loop]
-3	3	+1	# size_depth                                                                                       
-5	5	+1	# size_rob_ptr                                                                                     
-8	8	+1	# size_load_queue_ptr                                                                              
-8	8	+1	# size_store_queue_ptr                                                                             
-32	32	+1	# size_general_data                                                                                
-2	2	+1	# size_special_data                                                                                
-6	6	+1	# size_general_register                                                                            
-2	2	+1	# size_special_register                                                                            
-1	1	+1	# dispatch_priority                                                                                
-1	1	+1	# dispatch_load_balancing                                                                          
-1	1	+1	# table_dispatch                        [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][2][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][2][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][2][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-0	0	+1	# translate_ooo_engine_num_front_end    [0][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
-1	1	+1	# translate_ooo_engine_num_front_end    [0][1]       [nb_ooo_engine][ooo_engine_nb_front_end]
-2	2	+1	# translate_ooo_engine_num_front_end    [0][2]       [nb_ooo_engine][ooo_engine_nb_front_end]
-3	3	+1	# translate_ooo_engine_num_front_end    [0][3]       [nb_ooo_engine][ooo_engine_nb_front_end]
-0	0	+1	# translate_ooo_engine_num_execute_loop [0][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-0	0	+1	# translate_execute_loop_num_ooo_engine [0][0]       [nb_execute_loop][execute_loop_nb_ooo_engine]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-1_execute_loop.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-1_execute_loop.cfg	(revision 144)
+++ 	(revision )
@@ -1,78 +1,0 @@
-Core_Glue
-4	4	+1	# nb_front_end                                                                                     
-1	1	+1	# nb_context                            [0]          [nb_front_end]
-2	2	+1	# nb_context                            [1]          [nb_front_end]
-4	4	+1	# nb_context                            [2]          [nb_front_end]
-3	3	+1	# nb_context                            [3]          [nb_front_end]
-3	3	+1	# nb_ooo_engine                                                                                    
-1	1	+1	# nb_execute_loop                                                                                  
-1	1	+1	# ooo_engine_nb_front_end               [0]          [nb_ooo_engine]
-2	2	+1	# ooo_engine_nb_front_end               [1]          [nb_ooo_engine]
-1	1	+1	# ooo_engine_nb_front_end               [2]          [nb_ooo_engine]
-1	1	+1	# ooo_engine_nb_execute_loop            [0]          [nb_ooo_engine]
-1	1	+1	# ooo_engine_nb_execute_loop            [1]          [nb_ooo_engine]
-1	1	+1	# ooo_engine_nb_execute_loop            [2]          [nb_ooo_engine]
-3	3	+1	# execute_loop_nb_ooo_engine            [0]          [nb_execute_loop]
-4	4	+1	# nb_inst_decod                         [0]          [nb_front_end]   
-2	2	+1	# nb_inst_decod                         [1]          [nb_front_end]   
-1	1	+1	# nb_inst_decod                         [2]          [nb_front_end]   
-3	3	+1	# nb_inst_decod                         [3]          [nb_front_end]   
-4	4 	+1	# front_end_nb_inst_branch_complete     [0]          [nb_front_end] 
-2	2 	+1	# front_end_nb_inst_branch_complete     [1]          [nb_front_end] 
-2	2 	+1	# front_end_nb_inst_branch_complete     [2]          [nb_front_end] 
-3	3 	+1	# front_end_nb_inst_branch_complete     [3]          [nb_front_end] 
-4	4	+1	# ooo_engine_nb_inst_branch_complete    [0]          [nb_ooo_engine]
-2	2	+1	# ooo_engine_nb_inst_branch_complete    [1]          [nb_ooo_engine]
-3	3	+1	# ooo_engine_nb_inst_branch_complete    [2]          [nb_ooo_engine]
-3	3	+1	# nb_inst_insert                        [0]          [nb_ooo_engine]  
-1	1	+1	# nb_inst_insert                        [1]          [nb_ooo_engine]  
-2	2	+1	# nb_inst_insert                        [2]          [nb_ooo_engine]  
-3	3	+1	# nb_inst_reexecute                     [0]          [nb_ooo_engine]  
-1	1	+1	# nb_inst_reexecute                     [1]          [nb_ooo_engine]  
-2	2	+1	# nb_inst_reexecute                     [2]          [nb_ooo_engine]  
-3	3	+1	# nb_inst_issue                         [0]          [nb_ooo_engine]  
-1	1	+1	# nb_inst_issue                         [1]          [nb_ooo_engine]  
-2	2	+1	# nb_inst_issue                         [2]          [nb_ooo_engine]  
-4	4	+1	# nb_inst_execute                       [0][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-4	4	+1	# nb_inst_execute                       [1][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-4	4	+1	# nb_inst_execute                       [2][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-3	3	+1	# nb_read_unit                          [0]          [nb_execute_loop]
-4	4	+1	# nb_write_unit                         [0]          [nb_execute_loop]
-3	3	+1	# size_depth                                                                                       
-5	5	+1	# size_rob_ptr                                                                                     
-8	8	+1	# size_load_queue_ptr                                                                              
-8	8	+1	# size_store_queue_ptr                                                                             
-32	32	+1	# size_general_data                                                                                
-2	2	+1	# size_special_data                                                                                
-6	6	+1	# size_general_register                                                                            
-2	2	+1	# size_special_register                                                                            
-1	1	+1	# dispatch_priority                                                                                
-1	1	+1	# dispatch_load_balancing                                                                          
-1	1	+1	# table_dispatch                        [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][2][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][2][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][2][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [1][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [1][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [1][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-0	0	+1	# translate_ooo_engine_num_front_end    [0][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
-1	1	+1	# translate_ooo_engine_num_front_end    [1][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
-2	2	+1	# translate_ooo_engine_num_front_end    [1][1]       [nb_ooo_engine][ooo_engine_nb_front_end]
-3	3	+1	# translate_ooo_engine_num_front_end    [2][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
-0	0	+1	# translate_ooo_engine_num_execute_loop [0][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-0	0	+1	# translate_ooo_engine_num_execute_loop [1][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-0	0	+1	# translate_ooo_engine_num_execute_loop [2][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-0	0	+1	# translate_execute_loop_num_ooo_engine [0][0]       [nb_execute_loop][execute_loop_nb_ooo_engine]
-1	1	+1	# translate_execute_loop_num_ooo_engine [0][1]       [nb_execute_loop][execute_loop_nb_ooo_engine]
-2	2	+1	# translate_execute_loop_num_ooo_engine [0][2]       [nb_execute_loop][execute_loop_nb_ooo_engine]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-2_execute_loop.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-2_execute_loop.cfg	(revision 144)
+++ 	(revision )
@@ -1,101 +1,0 @@
-Core_Glue
-4	4	+1	# nb_front_end                                                                                     
-1	1	+1	# nb_context                            [0]          [nb_front_end]
-2	2	+1	# nb_context                            [1]          [nb_front_end]
-4	4	+1	# nb_context                            [2]          [nb_front_end]
-3	3	+1	# nb_context                            [3]          [nb_front_end]
-3	3	+1	# nb_ooo_engine                                                                                    
-2	2	+1	# nb_execute_loop                                                                                  
-1	1	+1	# ooo_engine_nb_front_end               [0]          [nb_ooo_engine]
-2	2	+1	# ooo_engine_nb_front_end               [1]          [nb_ooo_engine]
-1	1	+1	# ooo_engine_nb_front_end               [2]          [nb_ooo_engine]
-1	1	+1	# ooo_engine_nb_execute_loop            [0]          [nb_ooo_engine]
-2	2	+1	# ooo_engine_nb_execute_loop            [1]          [nb_ooo_engine]
-1	1	+1	# ooo_engine_nb_execute_loop            [2]          [nb_ooo_engine]
-2	2	+1	# execute_loop_nb_ooo_engine            [0]          [nb_execute_loop]
-1	1	+1	# execute_loop_nb_ooo_engine            [1]          [nb_execute_loop]
-4	4	+1	# nb_inst_decod                         [0]          [nb_front_end]   
-2	2	+1	# nb_inst_decod                         [1]          [nb_front_end]   
-1	1	+1	# nb_inst_decod                         [2]          [nb_front_end]   
-3	3	+1	# nb_inst_decod                         [3]          [nb_front_end]   
-4	4 	+1	# front_end_nb_inst_branch_complete     [0]          [nb_front_end] 
-2	2 	+1	# front_end_nb_inst_branch_complete     [1]          [nb_front_end] 
-2	2 	+1	# front_end_nb_inst_branch_complete     [2]          [nb_front_end] 
-3	3 	+1	# front_end_nb_inst_branch_complete     [3]          [nb_front_end] 
-4	4	+1	# ooo_engine_nb_inst_branch_complete    [0]          [nb_ooo_engine]
-2	2	+1	# ooo_engine_nb_inst_branch_complete    [1]          [nb_ooo_engine]
-3	3	+1	# ooo_engine_nb_inst_branch_complete    [2]          [nb_ooo_engine]
-3	3	+1	# nb_inst_insert                        [0]          [nb_ooo_engine]  
-1	1	+1	# nb_inst_insert                        [1]          [nb_ooo_engine]  
-2	2	+1	# nb_inst_insert                        [2]          [nb_ooo_engine]  
-3	3	+1	# nb_inst_reexecute                     [0]          [nb_ooo_engine]  
-1	1	+1	# nb_inst_reexecute                     [1]          [nb_ooo_engine]  
-2	2	+1	# nb_inst_reexecute                     [2]          [nb_ooo_engine]  
-3	3	+1	# nb_inst_issue                         [0]          [nb_ooo_engine]  
-1	1	+1	# nb_inst_issue                         [1]          [nb_ooo_engine]  
-2	2	+1	# nb_inst_issue                         [2]          [nb_ooo_engine]  
-4	4	+1	# nb_inst_execute                       [0][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-3	3	+1	# nb_inst_execute                       [1][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-4	4	+1	# nb_inst_execute                       [1][1]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-4	4	+1	# nb_inst_execute                       [2][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-3	3	+1	# nb_read_unit                          [0]          [nb_execute_loop]
-3	3	+1	# nb_read_unit                          [1]          [nb_execute_loop]
-4	4	+1	# nb_write_unit                         [0]          [nb_execute_loop]
-3	3	+1	# nb_write_unit                         [1]          [nb_execute_loop]
-3	3	+1	# size_depth                                                                                       
-5	5	+1	# size_rob_ptr                                                                                     
-8	8	+1	# size_load_queue_ptr                                                                              
-8	8	+1	# size_store_queue_ptr                                                                             
-32	32	+1	# size_general_data                                                                                
-2	2	+1	# size_special_data                                                                                
-6	6	+1	# size_general_register                                                                            
-2	2	+1	# size_special_register                                                                            
-1	1	+1	# dispatch_priority                                                                                
-1	1	+1	# dispatch_load_balancing                                                                          
-1	1	+1	# table_dispatch                        [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][0][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][0][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][0][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][1][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][1][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][1][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][2][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][2][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][2][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][2][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][2][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [0][2][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [1][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [1][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [1][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [1][0][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [1][0][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [1][0][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][0][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][0][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][0][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][1][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
-1	1	+1	# table_dispatch                        [2][1][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit]
-1	1	+1	# table_dispatch                        [2][1][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit]
-0	0	+1	# translate_ooo_engine_num_front_end    [0][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
-1	1	+1	# translate_ooo_engine_num_front_end    [1][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
-2	2	+1	# translate_ooo_engine_num_front_end    [1][1]       [nb_ooo_engine][ooo_engine_nb_front_end]
-3	3	+1	# translate_ooo_engine_num_front_end    [2][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
-0	0	+1	# translate_ooo_engine_num_execute_loop [0][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-1	1	+1	# translate_ooo_engine_num_execute_loop [1][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-0	0	+1	# translate_ooo_engine_num_execute_loop [1][1]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-0	0	+1	# translate_ooo_engine_num_execute_loop [2][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
-0	0	+1	# translate_execute_loop_num_ooo_engine [0][0]       [nb_execute_loop][execute_loop_nb_ooo_engine]
-2	2	+1	# translate_execute_loop_num_ooo_engine [0][1]       [nb_execute_loop][execute_loop_nb_ooo_engine]
-1	1	+1	# translate_execute_loop_num_ooo_engine [1][0]       [nb_execute_loop][execute_loop_nb_ooo_engine]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,31 +1,0 @@
-Core_Glue
-1	1	+1	# nb_front_end                                                                                     
-1	1	+1	# nb_context                            [0]                  [nb_front_end]
-1	1	+1	# nb_ooo_engine                                                                                            
-1	1	+1	# nb_execute_loop                                                                                          
-1	1	+1	# ooo_engine_nb_front_end               [0]                  [nb_ooo_engine]
-1	1	+1	# ooo_engine_nb_execute_loop            [0]                  [nb_ooo_engine]
-1	1	+1	# execute_loop_nb_ooo_engine            [0]                  [nb_execute_loop]
-1	1	+1	# nb_inst_decod                         [0]                  [nb_front_end]   
-1	1	+1	# front_end_nb_inst_branch_complete     [0]                  [nb_front_end]   
-1	1	+1	# ooo_engine_nb_inst_branch_complete    [0]                  [nb_ooo_engine]
-1	1	+1	# nb_inst_insert                        [0]                  [nb_ooo_engine]  
-1	1	+1	# nb_inst_reexecute                     [0]                  [nb_ooo_engine]  
-1	1	+1	# nb_inst_issue                         [0]                  [nb_ooo_engine]  
-1	1	+1	# nb_inst_execute                       [0][0]               [nb_ooo_engine][ooo_engine_nb_execute_loop]
-1	1	+1	# nb_read_unit                          [0]                  [nb_execute_loop]
-1	1	+1	# nb_write_unit                         [0]                  [nb_execute_loop]
-1	1	+1	# size_depth                                                                                       
-1	1	+1	# size_rob_ptr                                                                                     
-1	1	+1	# size_load_queue_ptr                                                                              
-2	2	+1	# size_store_queue_ptr                                                                             
-32	32	+1	# size_general_data                                                                                
-2	2	+1	# size_special_data                                                                                
-6	6	+1	# size_general_register                                                                            
-2	2	+1	# size_special_register                                                                            
-1	1	+1	# dispatch_priority                                                                                
-1	1	+1	# dispatch_load_balancing                                                                          
-1	1	+1	# table_dispatch                        [0][0][0][0]         [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit]
-0	0	+1	# translate_ooo_engine_num_front_end    [0][0]               [nb_ooo_engine][ooo_engine_nb_front_end]
-0	0	+1	# translate_ooo_engine_num_execute_loop [0][0]               [nb_ooo_engine][ooo_engine_nb_execute_loop]
-0	0	+1	# translate_execute_loop_num_ooo_engine [0][0]               [nb_execute_loop][execute_loop_nb_ooo_engine]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-1_front_end-1_ooo_engine-1_execute_loop.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-1_front_end-1_ooo_engine-1_execute_loop.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-1_front_end-1_ooo_engine-1_execute_loop.gen	(revision 145)
@@ -0,0 +1,46 @@
+Core_Glue
+1	1	+1	# nb_front_end                                                                                     
+1	4	*4	# nb_context                            [0]          [nb_front_end]
+1	1	+1	# nb_ooo_engine                                                                                    
+1	1	+1	# nb_execute_loop                                                                                  
+1	1	+1	# ooo_engine_nb_front_end               [0]          [nb_ooo_engine]
+1	1	+1	# ooo_engine_nb_execute_loop            [0]          [nb_ooo_engine]
+1	1	+1	# execute_loop_nb_ooo_engine            [0]          [nb_execute_loop]
+4	4	+1	# nb_inst_decod                         [0]          [nb_front_end]   
+4	4 	+1	# front_end_nb_inst_branch_complete     [0]          [nb_front_end] 
+4	4	+1	# ooo_engine_nb_inst_branch_complete    [0]          [nb_ooo_engine]
+4	4	+1	# nb_inst_insert                        [0]          [nb_ooo_engine]  
+4	4	+1	# nb_inst_reexecute                     [0]          [nb_ooo_engine]  
+4	4	+1	# nb_inst_issue                         [0]          [nb_ooo_engine]  
+4	4	+1	# nb_inst_execute                       [0]          [nb_ooo_engine]  
+4	4	+1	# nb_read_unit                          [0]          [nb_execute_loop]
+4	4	+1	# nb_write_unit                         [0]          [nb_execute_loop]
+3	3	+1	# size_depth                                                                                       
+5	5	+1	# size_rob_ptr                                                                                     
+8	8	+1	# size_load_queue_ptr                                                                              
+8	8	+1	# size_store_queue_ptr                                                                             
+32	32	+1	# size_general_data                                                                                
+2	2	+1	# size_special_data                                                                                
+6	6	+1	# size_general_register                                                                            
+2	2	+1	# size_special_register                                                                            
+1	1	+1	# dispatch_priority                                                                                
+1	1	+1	# dispatch_load_balancing                                                                          
+1	1	+1	# table_dispatch                        [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][0][0][3] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [1][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [1][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [1][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [1][0][0][3] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][0][0][3] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [3][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [3][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [3][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [3][0][0][3] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+0	0	+1	# translate_ooo_engine_num_front_end    [0][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
+0	0	+1	# translate_ooo_engine_num_execute_loop [0][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+0	0	+1	# translate_execute_loop_num_ooo_engine [0][0]       [nb_execute_loop][execute_loop_nb_ooo_engine]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-4_front_end-1_ooo_engine-1_execute_loop.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-4_front_end-1_ooo_engine-1_execute_loop.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-4_front_end-1_ooo_engine-1_execute_loop.gen	(revision 145)
@@ -0,0 +1,51 @@
+Core_Glue
+4	4	+1	# nb_front_end                                                                                     
+1	1	+1	# nb_context                            [0]          [nb_front_end]
+2	2	+1	# nb_context                            [1]          [nb_front_end]
+4	4	+1	# nb_context                            [2]          [nb_front_end]
+3	3	+1	# nb_context                            [3]          [nb_front_end]
+1	1	+1	# nb_ooo_engine                                                                                    
+1	1	+1	# nb_execute_loop                                                                                  
+4	4	+1	# ooo_engine_nb_front_end               [0]          [nb_ooo_engine]
+1	1	+1	# ooo_engine_nb_execute_loop            [0]          [nb_ooo_engine]
+1	1	+1	# execute_loop_nb_ooo_engine            [0]          [nb_execute_loop]
+4	4	+1	# nb_inst_decod                         [0]          [nb_front_end]   
+2	2	+1	# nb_inst_decod                         [1]          [nb_front_end]   
+1	1	+1	# nb_inst_decod                         [2]          [nb_front_end]   
+3	3	+1	# nb_inst_decod                         [3]          [nb_front_end]   
+4	4 	+1	# front_end_nb_inst_branch_complete     [0]          [nb_front_end] 
+4	4 	+1	# front_end_nb_inst_branch_complete     [1]          [nb_front_end] 
+4	4 	+1	# front_end_nb_inst_branch_complete     [2]          [nb_front_end] 
+4	4 	+1	# front_end_nb_inst_branch_complete     [3]          [nb_front_end] 
+4	4	+1	# ooo_engine_nb_inst_branch_complete    [0]          [nb_ooo_engine]
+3	3	+1	# nb_inst_insert                        [0]          [nb_ooo_engine]  
+3	3	+1	# nb_inst_reexecute                     [0]          [nb_ooo_engine]  
+3	3	+1	# nb_inst_issue                         [0]          [nb_ooo_engine]  
+4	4	+1	# nb_inst_execute                       [0]          [nb_ooo_engine]  
+3	3	+1	# nb_read_unit                          [0]          [nb_execute_loop]
+4	4	+1	# nb_write_unit                         [0]          [nb_execute_loop]
+3	3	+1	# size_depth                                                                                       
+5	5	+1	# size_rob_ptr                                                                                     
+8	8	+1	# size_load_queue_ptr                                                                              
+8	8	+1	# size_store_queue_ptr                                                                             
+32	32	+1	# size_general_data                                                                                
+2	2	+1	# size_special_data                                                                                
+6	6	+1	# size_general_register                                                                            
+2	2	+1	# size_special_register                                                                            
+1	1	+1	# dispatch_priority                                                                                
+1	1	+1	# dispatch_load_balancing                                                                          
+1	1	+1	# table_dispatch                        [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][2][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][2][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][2][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+0	0	+1	# translate_ooo_engine_num_front_end    [0][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
+1	1	+1	# translate_ooo_engine_num_front_end    [0][1]       [nb_ooo_engine][ooo_engine_nb_front_end]
+2	2	+1	# translate_ooo_engine_num_front_end    [0][2]       [nb_ooo_engine][ooo_engine_nb_front_end]
+3	3	+1	# translate_ooo_engine_num_front_end    [0][3]       [nb_ooo_engine][ooo_engine_nb_front_end]
+0	0	+1	# translate_ooo_engine_num_execute_loop [0][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+0	0	+1	# translate_execute_loop_num_ooo_engine [0][0]       [nb_execute_loop][execute_loop_nb_ooo_engine]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-4_front_end-3_ooo_engine-1_execute_loop.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-4_front_end-3_ooo_engine-1_execute_loop.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-4_front_end-3_ooo_engine-1_execute_loop.gen	(revision 145)
@@ -0,0 +1,78 @@
+Core_Glue
+4	4	+1	# nb_front_end                                                                                     
+1	1	+1	# nb_context                            [0]          [nb_front_end]
+2	2	+1	# nb_context                            [1]          [nb_front_end]
+4	4	+1	# nb_context                            [2]          [nb_front_end]
+3	3	+1	# nb_context                            [3]          [nb_front_end]
+3	3	+1	# nb_ooo_engine                                                                                    
+1	1	+1	# nb_execute_loop                                                                                  
+1	1	+1	# ooo_engine_nb_front_end               [0]          [nb_ooo_engine]
+2	2	+1	# ooo_engine_nb_front_end               [1]          [nb_ooo_engine]
+1	1	+1	# ooo_engine_nb_front_end               [2]          [nb_ooo_engine]
+1	1	+1	# ooo_engine_nb_execute_loop            [0]          [nb_ooo_engine]
+1	1	+1	# ooo_engine_nb_execute_loop            [1]          [nb_ooo_engine]
+1	1	+1	# ooo_engine_nb_execute_loop            [2]          [nb_ooo_engine]
+3	3	+1	# execute_loop_nb_ooo_engine            [0]          [nb_execute_loop]
+4	4	+1	# nb_inst_decod                         [0]          [nb_front_end]   
+2	2	+1	# nb_inst_decod                         [1]          [nb_front_end]   
+1	1	+1	# nb_inst_decod                         [2]          [nb_front_end]   
+3	3	+1	# nb_inst_decod                         [3]          [nb_front_end]   
+4	4 	+1	# front_end_nb_inst_branch_complete     [0]          [nb_front_end] 
+2	2 	+1	# front_end_nb_inst_branch_complete     [1]          [nb_front_end] 
+2	2 	+1	# front_end_nb_inst_branch_complete     [2]          [nb_front_end] 
+3	3 	+1	# front_end_nb_inst_branch_complete     [3]          [nb_front_end] 
+4	4	+1	# ooo_engine_nb_inst_branch_complete    [0]          [nb_ooo_engine]
+2	2	+1	# ooo_engine_nb_inst_branch_complete    [1]          [nb_ooo_engine]
+3	3	+1	# ooo_engine_nb_inst_branch_complete    [2]          [nb_ooo_engine]
+3	3	+1	# nb_inst_insert                        [0]          [nb_ooo_engine]  
+1	1	+1	# nb_inst_insert                        [1]          [nb_ooo_engine]  
+2	2	+1	# nb_inst_insert                        [2]          [nb_ooo_engine]  
+3	3	+1	# nb_inst_reexecute                     [0]          [nb_ooo_engine]  
+1	1	+1	# nb_inst_reexecute                     [1]          [nb_ooo_engine]  
+2	2	+1	# nb_inst_reexecute                     [2]          [nb_ooo_engine]  
+3	3	+1	# nb_inst_issue                         [0]          [nb_ooo_engine]  
+1	1	+1	# nb_inst_issue                         [1]          [nb_ooo_engine]  
+2	2	+1	# nb_inst_issue                         [2]          [nb_ooo_engine]  
+4	4	+1	# nb_inst_execute                       [0][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+4	4	+1	# nb_inst_execute                       [1][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+4	4	+1	# nb_inst_execute                       [2][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+3	3	+1	# nb_read_unit                          [0]          [nb_execute_loop]
+4	4	+1	# nb_write_unit                         [0]          [nb_execute_loop]
+3	3	+1	# size_depth                                                                                       
+5	5	+1	# size_rob_ptr                                                                                     
+8	8	+1	# size_load_queue_ptr                                                                              
+8	8	+1	# size_store_queue_ptr                                                                             
+32	32	+1	# size_general_data                                                                                
+2	2	+1	# size_special_data                                                                                
+6	6	+1	# size_general_register                                                                            
+2	2	+1	# size_special_register                                                                            
+1	1	+1	# dispatch_priority                                                                                
+1	1	+1	# dispatch_load_balancing                                                                          
+1	1	+1	# table_dispatch                        [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][2][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][2][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][2][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [1][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [1][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [1][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+0	0	+1	# translate_ooo_engine_num_front_end    [0][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
+1	1	+1	# translate_ooo_engine_num_front_end    [1][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
+2	2	+1	# translate_ooo_engine_num_front_end    [1][1]       [nb_ooo_engine][ooo_engine_nb_front_end]
+3	3	+1	# translate_ooo_engine_num_front_end    [2][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
+0	0	+1	# translate_ooo_engine_num_execute_loop [0][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+0	0	+1	# translate_ooo_engine_num_execute_loop [1][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+0	0	+1	# translate_ooo_engine_num_execute_loop [2][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+0	0	+1	# translate_execute_loop_num_ooo_engine [0][0]       [nb_execute_loop][execute_loop_nb_ooo_engine]
+1	1	+1	# translate_execute_loop_num_ooo_engine [0][1]       [nb_execute_loop][execute_loop_nb_ooo_engine]
+2	2	+1	# translate_execute_loop_num_ooo_engine [0][2]       [nb_execute_loop][execute_loop_nb_ooo_engine]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-4_front_end-3_ooo_engine-2_execute_loop.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-4_front_end-3_ooo_engine-2_execute_loop.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-4_front_end-3_ooo_engine-2_execute_loop.gen	(revision 145)
@@ -0,0 +1,101 @@
+Core_Glue
+4	4	+1	# nb_front_end                                                                                     
+1	1	+1	# nb_context                            [0]          [nb_front_end]
+2	2	+1	# nb_context                            [1]          [nb_front_end]
+4	4	+1	# nb_context                            [2]          [nb_front_end]
+3	3	+1	# nb_context                            [3]          [nb_front_end]
+3	3	+1	# nb_ooo_engine                                                                                    
+2	2	+1	# nb_execute_loop                                                                                  
+1	1	+1	# ooo_engine_nb_front_end               [0]          [nb_ooo_engine]
+2	2	+1	# ooo_engine_nb_front_end               [1]          [nb_ooo_engine]
+1	1	+1	# ooo_engine_nb_front_end               [2]          [nb_ooo_engine]
+1	1	+1	# ooo_engine_nb_execute_loop            [0]          [nb_ooo_engine]
+2	2	+1	# ooo_engine_nb_execute_loop            [1]          [nb_ooo_engine]
+1	1	+1	# ooo_engine_nb_execute_loop            [2]          [nb_ooo_engine]
+2	2	+1	# execute_loop_nb_ooo_engine            [0]          [nb_execute_loop]
+1	1	+1	# execute_loop_nb_ooo_engine            [1]          [nb_execute_loop]
+4	4	+1	# nb_inst_decod                         [0]          [nb_front_end]   
+2	2	+1	# nb_inst_decod                         [1]          [nb_front_end]   
+1	1	+1	# nb_inst_decod                         [2]          [nb_front_end]   
+3	3	+1	# nb_inst_decod                         [3]          [nb_front_end]   
+4	4 	+1	# front_end_nb_inst_branch_complete     [0]          [nb_front_end] 
+2	2 	+1	# front_end_nb_inst_branch_complete     [1]          [nb_front_end] 
+2	2 	+1	# front_end_nb_inst_branch_complete     [2]          [nb_front_end] 
+3	3 	+1	# front_end_nb_inst_branch_complete     [3]          [nb_front_end] 
+4	4	+1	# ooo_engine_nb_inst_branch_complete    [0]          [nb_ooo_engine]
+2	2	+1	# ooo_engine_nb_inst_branch_complete    [1]          [nb_ooo_engine]
+3	3	+1	# ooo_engine_nb_inst_branch_complete    [2]          [nb_ooo_engine]
+3	3	+1	# nb_inst_insert                        [0]          [nb_ooo_engine]  
+1	1	+1	# nb_inst_insert                        [1]          [nb_ooo_engine]  
+2	2	+1	# nb_inst_insert                        [2]          [nb_ooo_engine]  
+3	3	+1	# nb_inst_reexecute                     [0]          [nb_ooo_engine]  
+1	1	+1	# nb_inst_reexecute                     [1]          [nb_ooo_engine]  
+2	2	+1	# nb_inst_reexecute                     [2]          [nb_ooo_engine]  
+3	3	+1	# nb_inst_issue                         [0]          [nb_ooo_engine]  
+1	1	+1	# nb_inst_issue                         [1]          [nb_ooo_engine]  
+2	2	+1	# nb_inst_issue                         [2]          [nb_ooo_engine]  
+4	4	+1	# nb_inst_execute                       [0][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+3	3	+1	# nb_inst_execute                       [1][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+4	4	+1	# nb_inst_execute                       [1][1]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+4	4	+1	# nb_inst_execute                       [2][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+3	3	+1	# nb_read_unit                          [0]          [nb_execute_loop]
+3	3	+1	# nb_read_unit                          [1]          [nb_execute_loop]
+4	4	+1	# nb_write_unit                         [0]          [nb_execute_loop]
+3	3	+1	# nb_write_unit                         [1]          [nb_execute_loop]
+3	3	+1	# size_depth                                                                                       
+5	5	+1	# size_rob_ptr                                                                                     
+8	8	+1	# size_load_queue_ptr                                                                              
+8	8	+1	# size_store_queue_ptr                                                                             
+32	32	+1	# size_general_data                                                                                
+2	2	+1	# size_special_data                                                                                
+6	6	+1	# size_general_register                                                                            
+2	2	+1	# size_special_register                                                                            
+1	1	+1	# dispatch_priority                                                                                
+1	1	+1	# dispatch_load_balancing                                                                          
+1	1	+1	# table_dispatch                        [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][0][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][0][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][0][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][1][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][1][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][1][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][2][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][2][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][2][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][2][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][2][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [0][2][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [1][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [1][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [1][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [1][0][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [1][0][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [1][0][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][0][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][0][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][0][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][1][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 
+1	1	+1	# table_dispatch                        [2][1][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit]
+1	1	+1	# table_dispatch                        [2][1][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit]
+0	0	+1	# translate_ooo_engine_num_front_end    [0][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
+1	1	+1	# translate_ooo_engine_num_front_end    [1][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
+2	2	+1	# translate_ooo_engine_num_front_end    [1][1]       [nb_ooo_engine][ooo_engine_nb_front_end]
+3	3	+1	# translate_ooo_engine_num_front_end    [2][0]       [nb_ooo_engine][ooo_engine_nb_front_end]
+0	0	+1	# translate_ooo_engine_num_execute_loop [0][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+1	1	+1	# translate_ooo_engine_num_execute_loop [1][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+0	0	+1	# translate_ooo_engine_num_execute_loop [1][1]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+0	0	+1	# translate_ooo_engine_num_execute_loop [2][0]       [nb_ooo_engine][ooo_engine_nb_execute_loop]
+0	0	+1	# translate_execute_loop_num_ooo_engine [0][0]       [nb_execute_loop][execute_loop_nb_ooo_engine]
+2	2	+1	# translate_execute_loop_num_ooo_engine [0][1]       [nb_execute_loop][execute_loop_nb_ooo_engine]
+1	1	+1	# translate_execute_loop_num_ooo_engine [1][0]       [nb_execute_loop][execute_loop_nb_ooo_engine]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,31 @@
+Core_Glue
+1	1	+1	# nb_front_end                                                                                     
+1	1	+1	# nb_context                            [0]                  [nb_front_end]
+1	1	+1	# nb_ooo_engine                                                                                            
+1	1	+1	# nb_execute_loop                                                                                          
+1	1	+1	# ooo_engine_nb_front_end               [0]                  [nb_ooo_engine]
+1	1	+1	# ooo_engine_nb_execute_loop            [0]                  [nb_ooo_engine]
+1	1	+1	# execute_loop_nb_ooo_engine            [0]                  [nb_execute_loop]
+1	1	+1	# nb_inst_decod                         [0]                  [nb_front_end]   
+1	1	+1	# front_end_nb_inst_branch_complete     [0]                  [nb_front_end]   
+1	1	+1	# ooo_engine_nb_inst_branch_complete    [0]                  [nb_ooo_engine]
+1	1	+1	# nb_inst_insert                        [0]                  [nb_ooo_engine]  
+1	1	+1	# nb_inst_reexecute                     [0]                  [nb_ooo_engine]  
+1	1	+1	# nb_inst_issue                         [0]                  [nb_ooo_engine]  
+1	1	+1	# nb_inst_execute                       [0][0]               [nb_ooo_engine][ooo_engine_nb_execute_loop]
+1	1	+1	# nb_read_unit                          [0]                  [nb_execute_loop]
+1	1	+1	# nb_write_unit                         [0]                  [nb_execute_loop]
+1	1	+1	# size_depth                                                                                       
+1	1	+1	# size_rob_ptr                                                                                     
+1	1	+1	# size_load_queue_ptr                                                                              
+2	2	+1	# size_store_queue_ptr                                                                             
+32	32	+1	# size_general_data                                                                                
+2	2	+1	# size_special_data                                                                                
+6	6	+1	# size_general_register                                                                            
+2	2	+1	# size_special_register                                                                            
+1	1	+1	# dispatch_priority                                                                                
+1	1	+1	# dispatch_load_balancing                                                                          
+1	1	+1	# table_dispatch                        [0][0][0][0]         [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit]
+0	0	+1	# translate_ooo_engine_num_front_end    [0][0]               [nb_ooo_engine][ooo_engine_nb_front_end]
+0	0	+1	# translate_ooo_engine_num_execute_loop [0][0]               [nb_ooo_engine][ooo_engine_nb_execute_loop]
+0	0	+1	# translate_execute_loop_num_ooo_engine [0][0]               [nb_execute_loop][execute_loop_nb_ooo_engine]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,12 +1,0 @@
-Dcache_Access
-1	1	+1	# nb_execute_loop        
-1	1	+1	# nb_load_store_unit [0]       [nb_execute_loop]
-1	1	+1	# nb_cache_access    [0][0]    [nb_execute_loop][nb_load_store_unit]
-1	1	+1	# nb_dcache_port         
-32	32	+1	# size_address           
-32	32	+1	# size_data              
-0	0	+1	# size_thread_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# table_routing      [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-0	1	+1	# priority               
-0	1	+1	# load_balancing         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_mono_execute_loop1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_mono_execute_loop1.cfg	(revision 144)
+++ 	(revision )
@@ -1,24 +1,0 @@
-Dcache_Access
-1	1	+1	# nb_execute_loop        
-4	4	+1	# nb_load_store_unit [0]       [nb_execute_loop]
-1	1	+1	# nb_cache_access    [0][0]    [nb_execute_loop][nb_load_store_unit]
-1	1	+1	# nb_cache_access    [0][1]    [nb_execute_loop][nb_load_store_unit]
-1	1	+1	# nb_cache_access    [0][2]    [nb_execute_loop][nb_load_store_unit]
-1	1	+1	# nb_cache_access    [0][3]    [nb_execute_loop][nb_load_store_unit]
-1	1	+1	# nb_dcache_port         
-32	32	+1	# size_address           
-32	32	+1	# size_data              
-0	0	+1	# size_thread_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [0][1]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [0][2]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [0][3]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [0][1]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [0][2]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [0][3]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# table_routing      [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-0	0	+1	# table_routing      [0][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-0	0	+1	# table_routing      [0][2][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-0	0	+1	# table_routing      [0][3][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-0	1	+1	# priority               
-0	1	+1	# load_balancing         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_mono_execute_loop2.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_mono_execute_loop2.cfg	(revision 144)
+++ 	(revision )
@@ -1,27 +1,0 @@
-Dcache_Access
-1	1	+1	# nb_execute_loop        
-4	4	+1	# nb_load_store_unit [0]       [nb_execute_loop]
-1	1	+1	# nb_cache_access    [0][0]    [nb_execute_loop][nb_load_store_unit]
-2	2	+1	# nb_cache_access    [0][1]    [nb_execute_loop][nb_load_store_unit]
-3	3	+1	# nb_cache_access    [0][2]    [nb_execute_loop][nb_load_store_unit]
-1	1	+1	# nb_cache_access    [0][3]    [nb_execute_loop][nb_load_store_unit]
-4	4	+1	# nb_dcache_port         
-32	32	+1	# size_address           
-32	32	+1	# size_data              
-0	0	+1	# size_thread_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [0][1]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [0][2]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [0][3]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [0][1]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [0][2]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [0][3]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# table_routing      [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-1	1	+1	# table_routing      [0][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-2	2	+1	# table_routing      [0][1][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-2	2	+1	# table_routing      [0][2][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-1	1	+1	# table_routing      [0][2][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-0	0	+1	# table_routing      [0][2][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-3	3	+1	# table_routing      [0][3][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-0	1	+1	# priority               
-0	1	+1	# load_balancing         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_multi_execute_loop1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_multi_execute_loop1.cfg	(revision 144)
+++ 	(revision )
@@ -1,40 +1,0 @@
-Dcache_Access
-3	3	+1	# nb_execute_loop        
-1	1	+1	# nb_load_store_unit [0]       [nb_execute_loop]
-2	2	+1	# nb_load_store_unit [1]       [nb_execute_loop]
-3	3	+1	# nb_load_store_unit [2]       [nb_execute_loop]
-1	1	+1	# nb_cache_access    [0][0]    [nb_execute_loop][nb_load_store_unit]
-2	2	+1	# nb_cache_access    [1][0]    [nb_execute_loop][nb_load_store_unit]
-1	1	+1	# nb_cache_access    [1][1]    [nb_execute_loop][nb_load_store_unit]
-3	3	+1	# nb_cache_access    [2][0]    [nb_execute_loop][nb_load_store_unit]
-1	1	+1	# nb_cache_access    [2][1]    [nb_execute_loop][nb_load_store_unit]
-4	4	+1	# nb_cache_access    [2][2]    [nb_execute_loop][nb_load_store_unit]
-4	4	+1	# nb_dcache_port         
-32	32	+1	# size_address           
-32	32	+1	# size_data              
-0	0	+1	# size_thread_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [1][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [1][1]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [2][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [2][1]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [2][2]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [1][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [1][1]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [2][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [2][1]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [2][2]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# table_routing      [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-1	1	+1	# table_routing      [1][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-1	1	+1	# table_routing      [1][0][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-2	2	+1	# table_routing      [1][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-3	3	+1	# table_routing      [2][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-3	3	+1	# table_routing      [2][0][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-3	3	+1	# table_routing      [2][0][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-0	0	+1	# table_routing      [2][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-1	1	+1	# table_routing      [2][2][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-1	1	+1	# table_routing      [2][2][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-3	3	+1	# table_routing      [2][2][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-1	1	+1	# table_routing      [2][2][3] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-0	1	+1	# priority               
-0	1	+1	# load_balancing         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_multi_execute_loop2.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_multi_execute_loop2.cfg	(revision 144)
+++ 	(revision )
@@ -1,40 +1,0 @@
-Dcache_Access
-3	3	+1	# nb_execute_loop        
-1	1	+1	# nb_load_store_unit [0]       [nb_execute_loop]
-2	2	+1	# nb_load_store_unit [1]       [nb_execute_loop]
-3	3	+1	# nb_load_store_unit [2]       [nb_execute_loop]
-1	1	+1	# nb_cache_access    [0][0]    [nb_execute_loop][nb_load_store_unit]
-2	2	+1	# nb_cache_access    [1][0]    [nb_execute_loop][nb_load_store_unit]
-1	1	+1	# nb_cache_access    [1][1]    [nb_execute_loop][nb_load_store_unit]
-3	3	+1	# nb_cache_access    [2][0]    [nb_execute_loop][nb_load_store_unit]
-1	1	+1	# nb_cache_access    [2][1]    [nb_execute_loop][nb_load_store_unit]
-4	4	+1	# nb_cache_access    [2][2]    [nb_execute_loop][nb_load_store_unit]
-8	8	+1	# nb_dcache_port         
-32	32	+1	# size_address           
-32	32	+1	# size_data              
-0	0	+1	# size_thread_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [1][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [1][1]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [2][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [2][1]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_thread_id     [2][2]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [1][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [1][1]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [2][0]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [2][1]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# size_packet_id     [2][2]    [nb_execute_loop][nb_load_store_unit]
-0	0	+1	# table_routing      [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-1	1	+1	# table_routing      [1][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-2	2	+1	# table_routing      [1][0][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-3	3	+1	# table_routing      [1][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-4	4	+1	# table_routing      [2][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-5	5	+1	# table_routing      [2][0][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-6	6	+1	# table_routing      [2][0][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-7	7	+1	# table_routing      [2][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-0	0	+1	# table_routing      [2][2][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-1	1	+1	# table_routing      [2][2][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-2	2	+1	# table_routing      [2][2][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-3	3	+1	# table_routing      [2][2][3] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
-0	1	+1	# priority               
-0	1	+1	# load_balancing         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,12 @@
+Dcache_Access
+1	1	+1	# nb_execute_loop        
+1	1	+1	# nb_load_store_unit [0]       [nb_execute_loop]
+1	1	+1	# nb_cache_access    [0][0]    [nb_execute_loop][nb_load_store_unit]
+1	1	+1	# nb_dcache_port         
+32	32	+1	# size_address           
+32	32	+1	# size_data              
+0	0	+1	# size_thread_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# table_routing      [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+0	1	+1	# priority               
+0	1	+1	# load_balancing         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_mono_execute_loop1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_mono_execute_loop1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_mono_execute_loop1.gen	(revision 145)
@@ -0,0 +1,24 @@
+Dcache_Access
+1	1	+1	# nb_execute_loop        
+4	4	+1	# nb_load_store_unit [0]       [nb_execute_loop]
+1	1	+1	# nb_cache_access    [0][0]    [nb_execute_loop][nb_load_store_unit]
+1	1	+1	# nb_cache_access    [0][1]    [nb_execute_loop][nb_load_store_unit]
+1	1	+1	# nb_cache_access    [0][2]    [nb_execute_loop][nb_load_store_unit]
+1	1	+1	# nb_cache_access    [0][3]    [nb_execute_loop][nb_load_store_unit]
+1	1	+1	# nb_dcache_port         
+32	32	+1	# size_address           
+32	32	+1	# size_data              
+0	0	+1	# size_thread_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [0][1]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [0][2]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [0][3]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [0][1]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [0][2]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [0][3]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# table_routing      [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+0	0	+1	# table_routing      [0][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+0	0	+1	# table_routing      [0][2][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+0	0	+1	# table_routing      [0][3][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+0	1	+1	# priority               
+0	1	+1	# load_balancing         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_mono_execute_loop2.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_mono_execute_loop2.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_mono_execute_loop2.gen	(revision 145)
@@ -0,0 +1,27 @@
+Dcache_Access
+1	1	+1	# nb_execute_loop        
+4	4	+1	# nb_load_store_unit [0]       [nb_execute_loop]
+1	1	+1	# nb_cache_access    [0][0]    [nb_execute_loop][nb_load_store_unit]
+2	2	+1	# nb_cache_access    [0][1]    [nb_execute_loop][nb_load_store_unit]
+3	3	+1	# nb_cache_access    [0][2]    [nb_execute_loop][nb_load_store_unit]
+1	1	+1	# nb_cache_access    [0][3]    [nb_execute_loop][nb_load_store_unit]
+4	4	+1	# nb_dcache_port         
+32	32	+1	# size_address           
+32	32	+1	# size_data              
+0	0	+1	# size_thread_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [0][1]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [0][2]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [0][3]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [0][1]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [0][2]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [0][3]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# table_routing      [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+1	1	+1	# table_routing      [0][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+2	2	+1	# table_routing      [0][1][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+2	2	+1	# table_routing      [0][2][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+1	1	+1	# table_routing      [0][2][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+0	0	+1	# table_routing      [0][2][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+3	3	+1	# table_routing      [0][3][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+0	1	+1	# priority               
+0	1	+1	# load_balancing         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_multi_execute_loop1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_multi_execute_loop1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_multi_execute_loop1.gen	(revision 145)
@@ -0,0 +1,40 @@
+Dcache_Access
+3	3	+1	# nb_execute_loop        
+1	1	+1	# nb_load_store_unit [0]       [nb_execute_loop]
+2	2	+1	# nb_load_store_unit [1]       [nb_execute_loop]
+3	3	+1	# nb_load_store_unit [2]       [nb_execute_loop]
+1	1	+1	# nb_cache_access    [0][0]    [nb_execute_loop][nb_load_store_unit]
+2	2	+1	# nb_cache_access    [1][0]    [nb_execute_loop][nb_load_store_unit]
+1	1	+1	# nb_cache_access    [1][1]    [nb_execute_loop][nb_load_store_unit]
+3	3	+1	# nb_cache_access    [2][0]    [nb_execute_loop][nb_load_store_unit]
+1	1	+1	# nb_cache_access    [2][1]    [nb_execute_loop][nb_load_store_unit]
+4	4	+1	# nb_cache_access    [2][2]    [nb_execute_loop][nb_load_store_unit]
+4	4	+1	# nb_dcache_port         
+32	32	+1	# size_address           
+32	32	+1	# size_data              
+0	0	+1	# size_thread_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [1][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [1][1]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [2][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [2][1]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [2][2]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [1][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [1][1]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [2][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [2][1]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [2][2]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# table_routing      [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+1	1	+1	# table_routing      [1][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+1	1	+1	# table_routing      [1][0][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+2	2	+1	# table_routing      [1][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+3	3	+1	# table_routing      [2][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+3	3	+1	# table_routing      [2][0][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+3	3	+1	# table_routing      [2][0][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+0	0	+1	# table_routing      [2][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+1	1	+1	# table_routing      [2][2][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+1	1	+1	# table_routing      [2][2][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+3	3	+1	# table_routing      [2][2][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+1	1	+1	# table_routing      [2][2][3] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+0	1	+1	# priority               
+0	1	+1	# load_balancing         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_multi_execute_loop2.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_multi_execute_loop2.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/configuration/config_multi_execute_loop2.gen	(revision 145)
@@ -0,0 +1,40 @@
+Dcache_Access
+3	3	+1	# nb_execute_loop        
+1	1	+1	# nb_load_store_unit [0]       [nb_execute_loop]
+2	2	+1	# nb_load_store_unit [1]       [nb_execute_loop]
+3	3	+1	# nb_load_store_unit [2]       [nb_execute_loop]
+1	1	+1	# nb_cache_access    [0][0]    [nb_execute_loop][nb_load_store_unit]
+2	2	+1	# nb_cache_access    [1][0]    [nb_execute_loop][nb_load_store_unit]
+1	1	+1	# nb_cache_access    [1][1]    [nb_execute_loop][nb_load_store_unit]
+3	3	+1	# nb_cache_access    [2][0]    [nb_execute_loop][nb_load_store_unit]
+1	1	+1	# nb_cache_access    [2][1]    [nb_execute_loop][nb_load_store_unit]
+4	4	+1	# nb_cache_access    [2][2]    [nb_execute_loop][nb_load_store_unit]
+8	8	+1	# nb_dcache_port         
+32	32	+1	# size_address           
+32	32	+1	# size_data              
+0	0	+1	# size_thread_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [1][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [1][1]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [2][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [2][1]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_thread_id     [2][2]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [0][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [1][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [1][1]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [2][0]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [2][1]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# size_packet_id     [2][2]    [nb_execute_loop][nb_load_store_unit]
+0	0	+1	# table_routing      [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+1	1	+1	# table_routing      [1][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+2	2	+1	# table_routing      [1][0][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+3	3	+1	# table_routing      [1][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+4	4	+1	# table_routing      [2][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+5	5	+1	# table_routing      [2][0][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+6	6	+1	# table_routing      [2][0][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+7	7	+1	# table_routing      [2][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+0	0	+1	# table_routing      [2][2][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+1	1	+1	# table_routing      [2][2][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+2	2	+1	# table_routing      [2][2][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+3	3	+1	# table_routing      [2][2][3] [nb_execute_loop][nb_load_store_unit][nb_cache_access]
+0	1	+1	# priority               
+0	1	+1	# load_balancing         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Icache_Access
-1	1	+1	# nb_front_end       
-1	1	+1	# nb_context     [0]    [nb_front_end]
-1	1	+1	# nb_icache_port
-30	30	+1	# size_address   
-1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
-0	0	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [0][0] [nb_front_end][nb_context]
-0	1	+1	# priority           
-0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_mono_front_end1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_mono_front_end1.cfg	(revision 144)
+++ 	(revision )
@@ -1,19 +1,0 @@
-Icache_Access
-1	1	+1	# nb_front_end       
-4	4	+1	# nb_context     [0]    [nb_front_end]
-1	1	+1	# nb_icache_port
-30	30	+1	# size_address   
-1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
-2	2	+1	# nb_instruction [0][1] [nb_front_end][nb_context]
-4	4	+1	# nb_instruction [0][2] [nb_front_end][nb_context]
-8	8	+1	# nb_instruction [0][3] [nb_front_end][nb_context]
-2	2	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
-3	3	+1	# size_packet_id [0][1] [nb_front_end][nb_context]
-0	0	+1	# size_packet_id [0][2] [nb_front_end][nb_context]
-1	1	+1	# size_packet_id [0][3] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [0][0] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [0][1] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [0][2] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [0][3] [nb_front_end][nb_context]
-0	1	+1	# priority           
-0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_mono_front_end2.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_mono_front_end2.cfg	(revision 144)
+++ 	(revision )
@@ -1,19 +1,0 @@
-Icache_Access
-1	1	+1	# nb_front_end       
-4	4	+1	# nb_context     [0]    [nb_front_end]
-2	2	+1	# nb_icache_port
-30	30	+1	# size_address   
-1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
-2	2	+1	# nb_instruction [0][1] [nb_front_end][nb_context]
-4	4	+1	# nb_instruction [0][2] [nb_front_end][nb_context]
-8	8	+1	# nb_instruction [0][3] [nb_front_end][nb_context]
-2	2	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
-3	3	+1	# size_packet_id [0][1] [nb_front_end][nb_context]
-0	0	+1	# size_packet_id [0][2] [nb_front_end][nb_context]
-1	1	+1	# size_packet_id [0][3] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [0][0] [nb_front_end][nb_context]
-1	1	+1	# table_routing  [0][1] [nb_front_end][nb_context]
-1	1	+1	# table_routing  [0][2] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [0][3] [nb_front_end][nb_context]
-0	1	+1	# priority           
-0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end1.cfg	(revision 144)
+++ 	(revision )
@@ -1,27 +1,0 @@
-Icache_Access
-3	3	+1	# nb_front_end       
-1	1	+1	# nb_context     [0]    [nb_front_end]
-3	3	+1	# nb_context     [1]    [nb_front_end]
-2	2	+1	# nb_context     [2]    [nb_front_end]
-1	1	+1	# nb_icache_port
-30	30	+1	# size_address   
-1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
-2	2	+1	# nb_instruction [1][0] [nb_front_end][nb_context]
-3	3	+1	# nb_instruction [1][1] [nb_front_end][nb_context]
-2	2	+1	# nb_instruction [1][2] [nb_front_end][nb_context]
-4	4	+1	# nb_instruction [2][0] [nb_front_end][nb_context]
-4	4	+1	# nb_instruction [2][1] [nb_front_end][nb_context]
-2	2	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
-3	3	+1	# size_packet_id [1][0] [nb_front_end][nb_context]
-3	3	+1	# size_packet_id [1][1] [nb_front_end][nb_context]
-0	0	+1	# size_packet_id [1][2] [nb_front_end][nb_context]
-1	1	+1	# size_packet_id [2][0] [nb_front_end][nb_context]
-1	1	+1	# size_packet_id [2][1] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [0][0] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [1][0] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [1][1] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [1][2] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [2][0] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [2][1] [nb_front_end][nb_context]
-0	1	+1	# priority           
-0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end2.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end2.cfg	(revision 144)
+++ 	(revision )
@@ -1,27 +1,0 @@
-Icache_Access
-3	3	+1	# nb_front_end       
-1	1	+1	# nb_context     [0]    [nb_front_end]
-3	3	+1	# nb_context     [1]    [nb_front_end]
-2	2	+1	# nb_context     [2]    [nb_front_end]
-2	2	+1	# nb_icache_port
-30	30	+1	# size_address   
-1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
-2	2	+1	# nb_instruction [1][0] [nb_front_end][nb_context]
-3	3	+1	# nb_instruction [1][1] [nb_front_end][nb_context]
-2	2	+1	# nb_instruction [1][2] [nb_front_end][nb_context]
-4	4	+1	# nb_instruction [2][0] [nb_front_end][nb_context]
-4	4	+1	# nb_instruction [2][1] [nb_front_end][nb_context]
-2	2	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
-3	3	+1	# size_packet_id [1][0] [nb_front_end][nb_context]
-3	3	+1	# size_packet_id [1][1] [nb_front_end][nb_context]
-0	0	+1	# size_packet_id [1][2] [nb_front_end][nb_context]
-1	1	+1	# size_packet_id [2][0] [nb_front_end][nb_context]
-1	1	+1	# size_packet_id [2][1] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [0][0] [nb_front_end][nb_context]
-1	1	+1	# table_routing  [1][0] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [1][1] [nb_front_end][nb_context]
-1	1	+1	# table_routing  [1][2] [nb_front_end][nb_context]
-1	1	+1	# table_routing  [2][0] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [2][1] [nb_front_end][nb_context]
-0	1	+1	# priority           
-0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end3.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end3.cfg	(revision 144)
+++ 	(revision )
@@ -1,27 +1,0 @@
-Icache_Access
-3	3	+1	# nb_front_end       
-1	1	+1	# nb_context     [0]    [nb_front_end]
-3	3	+1	# nb_context     [1]    [nb_front_end]
-2	2	+1	# nb_context     [2]    [nb_front_end]
-3	3	+1	# nb_icache_port
-30	30	+1	# size_address   
-1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
-2	2	+1	# nb_instruction [1][0] [nb_front_end][nb_context]
-3	3	+1	# nb_instruction [1][1] [nb_front_end][nb_context]
-2	2	+1	# nb_instruction [1][2] [nb_front_end][nb_context]
-4	4	+1	# nb_instruction [2][0] [nb_front_end][nb_context]
-4	4	+1	# nb_instruction [2][1] [nb_front_end][nb_context]
-2	2	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
-3	3	+1	# size_packet_id [1][0] [nb_front_end][nb_context]
-3	3	+1	# size_packet_id [1][1] [nb_front_end][nb_context]
-0	0	+1	# size_packet_id [1][2] [nb_front_end][nb_context]
-1	1	+1	# size_packet_id [2][0] [nb_front_end][nb_context]
-1	1	+1	# size_packet_id [2][1] [nb_front_end][nb_context]
-2	2	+1	# table_routing  [0][0] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [1][0] [nb_front_end][nb_context]
-1	1	+1	# table_routing  [1][1] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [1][2] [nb_front_end][nb_context]
-1	1	+1	# table_routing  [2][0] [nb_front_end][nb_context]
-2	2	+1	# table_routing  [2][1] [nb_front_end][nb_context]
-0	1	+1	# priority           
-0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end4.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end4.cfg	(revision 144)
+++ 	(revision )
@@ -1,27 +1,0 @@
-Icache_Access
-3	3	+1	# nb_front_end       
-1	1	+1	# nb_context     [0]    [nb_front_end]
-3	3	+1	# nb_context     [1]    [nb_front_end]
-2	2	+1	# nb_context     [2]    [nb_front_end]
-4	4	+1	# nb_icache_port
-30	30	+1	# size_address   
-1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
-2	2	+1	# nb_instruction [1][0] [nb_front_end][nb_context]
-3	3	+1	# nb_instruction [1][1] [nb_front_end][nb_context]
-2	2	+1	# nb_instruction [1][2] [nb_front_end][nb_context]
-4	4	+1	# nb_instruction [2][0] [nb_front_end][nb_context]
-4	4	+1	# nb_instruction [2][1] [nb_front_end][nb_context]
-2	2	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
-3	3	+1	# size_packet_id [1][0] [nb_front_end][nb_context]
-3	3	+1	# size_packet_id [1][1] [nb_front_end][nb_context]
-0	0	+1	# size_packet_id [1][2] [nb_front_end][nb_context]
-1	1	+1	# size_packet_id [2][0] [nb_front_end][nb_context]
-1	1	+1	# size_packet_id [2][1] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [0][0] [nb_front_end][nb_context]
-1	1	+1	# table_routing  [1][0] [nb_front_end][nb_context]
-2	2	+1	# table_routing  [1][1] [nb_front_end][nb_context]
-3	3	+1	# table_routing  [1][2] [nb_front_end][nb_context]
-1	1	+1	# table_routing  [2][0] [nb_front_end][nb_context]
-0	0	+1	# table_routing  [2][1] [nb_front_end][nb_context]
-0	1	+1	# priority           
-0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,10 @@
+Icache_Access
+1	1	+1	# nb_front_end       
+1	1	+1	# nb_context     [0]    [nb_front_end]
+1	1	+1	# nb_icache_port
+30	30	+1	# size_address   
+1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
+0	0	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [0][0] [nb_front_end][nb_context]
+0	1	+1	# priority           
+0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_mono_front_end1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_mono_front_end1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_mono_front_end1.gen	(revision 145)
@@ -0,0 +1,19 @@
+Icache_Access
+1	1	+1	# nb_front_end       
+4	4	+1	# nb_context     [0]    [nb_front_end]
+1	1	+1	# nb_icache_port
+30	30	+1	# size_address   
+1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
+2	2	+1	# nb_instruction [0][1] [nb_front_end][nb_context]
+4	4	+1	# nb_instruction [0][2] [nb_front_end][nb_context]
+8	8	+1	# nb_instruction [0][3] [nb_front_end][nb_context]
+2	2	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
+3	3	+1	# size_packet_id [0][1] [nb_front_end][nb_context]
+0	0	+1	# size_packet_id [0][2] [nb_front_end][nb_context]
+1	1	+1	# size_packet_id [0][3] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [0][0] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [0][1] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [0][2] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [0][3] [nb_front_end][nb_context]
+0	1	+1	# priority           
+0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_mono_front_end2.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_mono_front_end2.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_mono_front_end2.gen	(revision 145)
@@ -0,0 +1,19 @@
+Icache_Access
+1	1	+1	# nb_front_end       
+4	4	+1	# nb_context     [0]    [nb_front_end]
+2	2	+1	# nb_icache_port
+30	30	+1	# size_address   
+1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
+2	2	+1	# nb_instruction [0][1] [nb_front_end][nb_context]
+4	4	+1	# nb_instruction [0][2] [nb_front_end][nb_context]
+8	8	+1	# nb_instruction [0][3] [nb_front_end][nb_context]
+2	2	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
+3	3	+1	# size_packet_id [0][1] [nb_front_end][nb_context]
+0	0	+1	# size_packet_id [0][2] [nb_front_end][nb_context]
+1	1	+1	# size_packet_id [0][3] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [0][0] [nb_front_end][nb_context]
+1	1	+1	# table_routing  [0][1] [nb_front_end][nb_context]
+1	1	+1	# table_routing  [0][2] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [0][3] [nb_front_end][nb_context]
+0	1	+1	# priority           
+0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_multi_front_end1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_multi_front_end1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_multi_front_end1.gen	(revision 145)
@@ -0,0 +1,27 @@
+Icache_Access
+3	3	+1	# nb_front_end       
+1	1	+1	# nb_context     [0]    [nb_front_end]
+3	3	+1	# nb_context     [1]    [nb_front_end]
+2	2	+1	# nb_context     [2]    [nb_front_end]
+1	1	+1	# nb_icache_port
+30	30	+1	# size_address   
+1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
+2	2	+1	# nb_instruction [1][0] [nb_front_end][nb_context]
+3	3	+1	# nb_instruction [1][1] [nb_front_end][nb_context]
+2	2	+1	# nb_instruction [1][2] [nb_front_end][nb_context]
+4	4	+1	# nb_instruction [2][0] [nb_front_end][nb_context]
+4	4	+1	# nb_instruction [2][1] [nb_front_end][nb_context]
+2	2	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
+3	3	+1	# size_packet_id [1][0] [nb_front_end][nb_context]
+3	3	+1	# size_packet_id [1][1] [nb_front_end][nb_context]
+0	0	+1	# size_packet_id [1][2] [nb_front_end][nb_context]
+1	1	+1	# size_packet_id [2][0] [nb_front_end][nb_context]
+1	1	+1	# size_packet_id [2][1] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [0][0] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [1][0] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [1][1] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [1][2] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [2][0] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [2][1] [nb_front_end][nb_context]
+0	1	+1	# priority           
+0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_multi_front_end2.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_multi_front_end2.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_multi_front_end2.gen	(revision 145)
@@ -0,0 +1,27 @@
+Icache_Access
+3	3	+1	# nb_front_end       
+1	1	+1	# nb_context     [0]    [nb_front_end]
+3	3	+1	# nb_context     [1]    [nb_front_end]
+2	2	+1	# nb_context     [2]    [nb_front_end]
+2	2	+1	# nb_icache_port
+30	30	+1	# size_address   
+1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
+2	2	+1	# nb_instruction [1][0] [nb_front_end][nb_context]
+3	3	+1	# nb_instruction [1][1] [nb_front_end][nb_context]
+2	2	+1	# nb_instruction [1][2] [nb_front_end][nb_context]
+4	4	+1	# nb_instruction [2][0] [nb_front_end][nb_context]
+4	4	+1	# nb_instruction [2][1] [nb_front_end][nb_context]
+2	2	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
+3	3	+1	# size_packet_id [1][0] [nb_front_end][nb_context]
+3	3	+1	# size_packet_id [1][1] [nb_front_end][nb_context]
+0	0	+1	# size_packet_id [1][2] [nb_front_end][nb_context]
+1	1	+1	# size_packet_id [2][0] [nb_front_end][nb_context]
+1	1	+1	# size_packet_id [2][1] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [0][0] [nb_front_end][nb_context]
+1	1	+1	# table_routing  [1][0] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [1][1] [nb_front_end][nb_context]
+1	1	+1	# table_routing  [1][2] [nb_front_end][nb_context]
+1	1	+1	# table_routing  [2][0] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [2][1] [nb_front_end][nb_context]
+0	1	+1	# priority           
+0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_multi_front_end3.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_multi_front_end3.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_multi_front_end3.gen	(revision 145)
@@ -0,0 +1,27 @@
+Icache_Access
+3	3	+1	# nb_front_end       
+1	1	+1	# nb_context     [0]    [nb_front_end]
+3	3	+1	# nb_context     [1]    [nb_front_end]
+2	2	+1	# nb_context     [2]    [nb_front_end]
+3	3	+1	# nb_icache_port
+30	30	+1	# size_address   
+1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
+2	2	+1	# nb_instruction [1][0] [nb_front_end][nb_context]
+3	3	+1	# nb_instruction [1][1] [nb_front_end][nb_context]
+2	2	+1	# nb_instruction [1][2] [nb_front_end][nb_context]
+4	4	+1	# nb_instruction [2][0] [nb_front_end][nb_context]
+4	4	+1	# nb_instruction [2][1] [nb_front_end][nb_context]
+2	2	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
+3	3	+1	# size_packet_id [1][0] [nb_front_end][nb_context]
+3	3	+1	# size_packet_id [1][1] [nb_front_end][nb_context]
+0	0	+1	# size_packet_id [1][2] [nb_front_end][nb_context]
+1	1	+1	# size_packet_id [2][0] [nb_front_end][nb_context]
+1	1	+1	# size_packet_id [2][1] [nb_front_end][nb_context]
+2	2	+1	# table_routing  [0][0] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [1][0] [nb_front_end][nb_context]
+1	1	+1	# table_routing  [1][1] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [1][2] [nb_front_end][nb_context]
+1	1	+1	# table_routing  [2][0] [nb_front_end][nb_context]
+2	2	+1	# table_routing  [2][1] [nb_front_end][nb_context]
+0	1	+1	# priority           
+0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_multi_front_end4.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_multi_front_end4.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/configuration/config_multi_front_end4.gen	(revision 145)
@@ -0,0 +1,27 @@
+Icache_Access
+3	3	+1	# nb_front_end       
+1	1	+1	# nb_context     [0]    [nb_front_end]
+3	3	+1	# nb_context     [1]    [nb_front_end]
+2	2	+1	# nb_context     [2]    [nb_front_end]
+4	4	+1	# nb_icache_port
+30	30	+1	# size_address   
+1	1	+1	# nb_instruction [0][0] [nb_front_end][nb_context]
+2	2	+1	# nb_instruction [1][0] [nb_front_end][nb_context]
+3	3	+1	# nb_instruction [1][1] [nb_front_end][nb_context]
+2	2	+1	# nb_instruction [1][2] [nb_front_end][nb_context]
+4	4	+1	# nb_instruction [2][0] [nb_front_end][nb_context]
+4	4	+1	# nb_instruction [2][1] [nb_front_end][nb_context]
+2	2	+1	# size_packet_id [0][0] [nb_front_end][nb_context]
+3	3	+1	# size_packet_id [1][0] [nb_front_end][nb_context]
+3	3	+1	# size_packet_id [1][1] [nb_front_end][nb_context]
+0	0	+1	# size_packet_id [1][2] [nb_front_end][nb_context]
+1	1	+1	# size_packet_id [2][0] [nb_front_end][nb_context]
+1	1	+1	# size_packet_id [2][1] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [0][0] [nb_front_end][nb_context]
+1	1	+1	# table_routing  [1][0] [nb_front_end][nb_context]
+2	2	+1	# table_routing  [1][1] [nb_front_end][nb_context]
+3	3	+1	# table_routing  [1][2] [nb_front_end][nb_context]
+1	1	+1	# table_routing  [2][0] [nb_front_end][nb_context]
+0	0	+1	# table_routing  [2][1] [nb_front_end][nb_context]
+0	1	+1	# priority           
+0	1	+1	# load_balancing     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,8 +1,0 @@
-Execute_loop_Glue
-1	4	*4	# nb_gpr_write         
-1	4	*4	# nb_spr_write         
-0	2	+1	# size_ooo_engine_id   
-6	6	*2	# size_general_register
-4	4	*2	# size_special_register
-32	32	*2	# size_general_data    
-2	2	*2	# size_special_data    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,8 @@
+Execute_loop_Glue
+1	4	*4	# nb_gpr_write         
+1	4	*4	# nb_spr_write         
+0	2	+1	# size_ooo_engine_id   
+6	6	*2	# size_general_register
+4	4	*2	# size_special_register
+32	32	*2	# size_general_data    
+2	2	*2	# size_special_data    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,11 +1,0 @@
-Functionnal_unit
-1	1	+1	# nb_context         
-1	1	+1	# nb_front_end       
-2	2	+1	# nb_ooo_engine      
-256 	256 	+1	# nb_packet          
-32	32	+1	# size_general_data  
-32	32	+1	# nb_general_register
-2 	2 	+1	# size_special_data  
-16	16	+1	# nb_special_register
-4 	4 	*2	# size_store_queue
-1 	4 	*4	# size_load_queue
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,11 @@
+Functionnal_unit
+1	1	+1	# nb_context         
+1	1	+1	# nb_front_end       
+2	2	+1	# nb_ooo_engine      
+256 	256 	+1	# nb_packet          
+32	32	+1	# size_general_data  
+32	32	+1	# nb_general_register
+2 	2 	+1	# size_special_data  
+16	16	+1	# nb_special_register
+4 	4 	*2	# size_store_queue
+1 	4 	*4	# size_load_queue
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,17 +1,0 @@
-Load_store_unit
-3	3	*2	# store_size_queue       
-2	2	*2	# load_size_queue        
-2	2	*2	# size_speculative_access_queue
-2	2	+1	# nb_port_check
-2	2	+1	# speculative_load       {none,access,commit,bypass}
-0	0	+1	# bypass_memory
-1	1	+1	# nb_cache_port 
-1	1	+1	# nb_inst_memory
-2	2	*2	# nb_context             1	1	*2	
-2	2	*2	# nb_front_end		 1	1	*2	
-2	2	*2	# nb_ooo_engine          1	1	*2	
-64	64	*2	# nb_packet              
-32	32	*2	# size_general_data      
-2	2	*2	# size_special_data      
-32	32	*2	# nb_general_register    
-16	16	*2	# nb_special_register    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,17 @@
+Load_store_unit
+3	3	*2	# store_size_queue       
+2	2	*2	# load_size_queue        
+2	2	*2	# size_speculative_access_queue
+2	2	+1	# nb_port_check
+2	2	+1	# speculative_load       {none,access,commit,bypass}
+0	0	+1	# bypass_memory
+1	1	+1	# nb_cache_port 
+1	1	+1	# nb_inst_memory
+2	2	*2	# nb_context             1	1	*2	
+2	2	*2	# nb_front_end		 1	1	*2	
+2	2	*2	# nb_ooo_engine          1	1	*2	
+64	64	*2	# nb_packet              
+32	32	*2	# size_general_data      
+2	2	*2	# size_special_data      
+32	32	*2	# nb_general_register    
+16	16	*2	# nb_special_register    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 145)
@@ -237,9 +237,9 @@
   public  : void     genMealy_retire           (void);
    
-  public  : void     function_speculative_load_access_transition      (void);
-  public  : void     function_speculative_load_access_genMoore        (void);
-  public  : void     function_speculative_load_access_genMealy_dcache (void);
-  public  : void     function_speculative_load_access_genMealy_insert (void);
-  public  : void     function_speculative_load_access_genMealy_retire (void);
+  public  : void     function_speculative_load_commit_transition      (void);
+  public  : void     function_speculative_load_commit_genMoore        (void);
+  public  : void     function_speculative_load_commit_genMealy_dcache (void);
+  public  : void     function_speculative_load_commit_genMealy_insert (void);
+  public  : void     function_speculative_load_commit_genMealy_retire (void);
 #endif					       
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h	(revision 145)
@@ -34,7 +34,7 @@
     {
        NO_SPECULATIVE_LOAD     //each load wait all previous store before the data cache access
-      ,SPECULATIVE_LOAD_ACCESS //each load wait all previous store before the commiting
-    //,SPECULATIVE_LOAD_COMMIT //each load commit the result before the end of dependence's check
-    //,SPECULATIVE_LOAD_BYPASS //each load bypass the result before the end of dependence's check
+   // ,SPECULATIVE_LOAD_ACCESS //each load wait all previous store before the commiting
+   // ,SPECULATIVE_LOAD_ACCESS == (SPECULATIVE_LOAD_COMMIT and speculative_commit_predictor_scheme == PREDICTOR_NEVER_TAKE)
+      ,SPECULATIVE_LOAD_COMMIT //each load commit the result before the end of dependence's check
     } Tspeculative_load_t; 
   
@@ -218,6 +218,6 @@
       {
       case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD     : return "no_speculative_load"    ; break;
-      case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS : return "speculative_load_access"; break;
-//    case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT : return "speculative_load_commit"; break;
+//    case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS : return "speculative_load_access"; break;
+      case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT : return "speculative_load_commit"; break;
 //    case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS : return "speculative_load_bypass"; break;
       default    : return ""      ; break;
@@ -230,10 +230,10 @@
         (x.compare(toString(                      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD     )) == 0))
       return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD;
-    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS))) == 0) or
-        (x.compare(toString(                      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS )) == 0))
-      return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS;
-//  if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT))) == 0) or
-//      (x.compare(toString(                      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT )) == 0))
-//    return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT;
+//  if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS))) == 0) or
+//      (x.compare(toString(                      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS )) == 0))
+//    return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS;
+    if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT))) == 0) or
+        (x.compare(toString(                      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT )) == 0))
+      return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT;
 //  if ((x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS))) == 0) or
 //      (x.compare(toString(                      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS )) == 0))
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp	(revision 145)
@@ -77,16 +77,15 @@
     switch (_param->_speculative_load)
       {
-      case SPECULATIVE_LOAD_ACCESS :
+      case SPECULATIVE_LOAD_COMMIT :
 	{
-	  function_transition      = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_transition     ;
-	  function_genMoore        = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_genMoore       ;
-	  function_genMealy_dcache = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_genMealy_dcache;
-	  function_genMealy_insert = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_genMealy_insert;
-	  function_genMealy_retire = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_access_genMealy_retire;
+	  function_transition      = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_transition     ;
+	  function_genMoore        = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_genMoore       ;
+	  function_genMealy_dcache = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_genMealy_dcache;
+	  function_genMealy_insert = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_genMealy_insert;
+	  function_genMealy_retire = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_genMealy_retire;
 	  break;
 	}
       case NO_SPECULATIVE_LOAD     :
-      // case SPECULATIVE_LOAD_COMMIT :
-      //case SPECULATIVE_LOAD_BYPASS :
+      // case SPECULATIVE_LOAD_ACCESS :
       default                      :
 	{
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_dcache.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_dcache.cpp	(revision 144)
+++ 	(revision )
@@ -1,40 +1,0 @@
-#ifdef SYSTEMC
-//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
-/*
- * $Id$
- *
- * [ Description ]
- * 
- */
-
-#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
-
-namespace morpheo                    {
-namespace behavioural {
-namespace core {
-namespace multi_execute_loop {
-namespace execute_loop {
-namespace multi_execute_unit {
-namespace execute_unit {
-namespace load_store_unit {
-
-
-#undef  FUNCTION
-#define FUNCTION "Load_store_unit::function_speculative_load_access_genMealy_dcache"
-  void Load_store_unit::function_speculative_load_access_genMealy_dcache (void)
-  {
-    log_begin(Load_store_unit,FUNCTION);
-    log_end  (Load_store_unit,FUNCTION);
-  };
-
-}; // end namespace load_store_unit
-}; // end namespace execute_unit
-}; // end namespace multi_execute_unit
-}; // end namespace execute_loop
-}; // end namespace multi_execute_loop
-}; // end namespace core
-
-}; // end namespace behavioural
-}; // end namespace morpheo              
-#endif
-//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_insert.cpp	(revision 144)
+++ 	(revision )
@@ -1,76 +1,0 @@
-#ifdef SYSTEMC
-//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
-/*
- * $Id$
- *
- * [ Description ]
- * 
- */
-
-#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
-
-namespace morpheo                    {
-namespace behavioural {
-namespace core {
-namespace multi_execute_loop {
-namespace execute_loop {
-namespace multi_execute_unit {
-namespace execute_unit {
-namespace load_store_unit {
-
-
-#undef  FUNCTION
-#define FUNCTION "Load_store_unit::function_speculative_load_access_genMealy_insert"
-  void Load_store_unit::function_speculative_load_access_genMealy_insert (void)
-  {
-    log_begin(Load_store_unit,FUNCTION);
-    log_function(Load_store_unit,FUNCTION,_name.c_str());
-
-    // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-    
-    // Initialisation
-    internal_MEMORY_IN_PORT = 0;
-    Tcontrol_t ack [_param->_nb_inst_memory];
-    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
-      ack [i] = 0;
-
-    if (PORT_READ(in_NRESET))
-      {
-    // find first valid entry
-    // store queue is never full (pointer is manage by rename stage)
-    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
-      if (PORT_READ(in_MEMORY_IN_VAL [i]))
-	{
-	  internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION [i])) or not _speculative_access_queue_control->full();
-
-	  if (internal_MEMORY_IN_ACK)
-	    {
-	      ack [i] = 1;
-	      internal_MEMORY_IN_PORT = i;
-	      break; // end
-	    }
-	}
-      }
-    else
-      {
-        internal_MEMORY_IN_ACK = 0;
-//         internal_MEMORY_IN_PORT = i;
-      }
-
-    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
-      PORT_WRITE(out_MEMORY_IN_ACK [i], ack [i]);
-
-    log_end(Load_store_unit,FUNCTION);
-  };
-
-}; // end namespace load_store_unit
-}; // end namespace execute_unit
-}; // end namespace multi_execute_unit
-}; // end namespace execute_loop
-}; // end namespace multi_execute_loop
-}; // end namespace core
-
-}; // end namespace behavioural
-}; // end namespace morpheo              
-#endif
-//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMealy_retire.cpp	(revision 144)
+++ 	(revision )
@@ -1,40 +1,0 @@
-#ifdef SYSTEMC
-//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
-/*
- * $Id$
- *
- * [ Description ]
- * 
- */
-
-#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
-
-namespace morpheo                    {
-namespace behavioural {
-namespace core {
-namespace multi_execute_loop {
-namespace execute_loop {
-namespace multi_execute_unit {
-namespace execute_unit {
-namespace load_store_unit {
-
-
-#undef  FUNCTION
-#define FUNCTION "Load_store_unit::function_speculative_load_access_genMealy_retire"
-  void Load_store_unit::function_speculative_load_access_genMealy_retire (void)
-  {
-    log_begin(Load_store_unit,FUNCTION);
-    log_end  (Load_store_unit,FUNCTION);
-  };
-
-}; // end namespace load_store_unit
-}; // end namespace execute_unit
-}; // end namespace multi_execute_unit
-}; // end namespace execute_loop
-}; // end namespace multi_execute_loop
-}; // end namespace core
-
-}; // end namespace behavioural
-}; // end namespace morpheo              
-#endif
-//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_genMoore.cpp	(revision 144)
+++ 	(revision )
@@ -1,284 +1,0 @@
-#ifdef SYSTEMC
-//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
-/*
- * $Id$
- *
- * [ Description ]
- * 
- */
-
-#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
-
-namespace morpheo                    {
-namespace behavioural {
-namespace core {
-namespace multi_execute_loop {
-namespace execute_loop {
-namespace multi_execute_unit {
-namespace execute_unit {
-namespace load_store_unit {
-
-
-#undef  FUNCTION
-#define FUNCTION "Load_store_unit::function_speculative_load_access_genMoore"
-  void Load_store_unit::function_speculative_load_access_genMoore (void)
-  {
-    log_begin(Load_store_unit,FUNCTION);
-    log_function(Load_store_unit,FUNCTION,_name.c_str());
-
-    if (PORT_READ(in_NRESET))
-      {
-    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-    Tcontext_t         memory_out_context_id    = 0;
-    Tcontext_t         memory_out_front_end_id  = 0;
-    Tcontext_t         memory_out_ooo_engine_id = 0;
-    Tpacket_t          memory_out_packet_id     = 0;
-    Tcontrol_t         memory_out_cancel        = 0;
-    Tcontrol_t         memory_out_write_rd      = 0;
-    Tgeneral_address_t memory_out_num_reg_rd    = 0;
-    Tgeneral_data_t    memory_out_data_rd       = 0;
-//  Tcontrol_t         memory_out_write_re      = 0;
-//  Tspecial_address_t memory_out_num_reg_re    = 0;
-//  Tspecial_data_t    memory_out_data_re       = 0;
-    Tcontrol_t         memory_out_no_sequence   = 0;
-    Texception_t       memory_out_exception     = 0;
-
-    internal_MEMORY_OUT_VAL = 0;
-
-    // Test store and load queue
-
-    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test MEMORY_OUT");
-
-    log_printf(TRACE,Load_store_unit,FUNCTION,"    * Load  queue");
-    for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++)
-//     for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++)
-      {
-// 	internal_MEMORY_OUT_PTR = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
-	internal_MEMORY_OUT_VAL = ((_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK) or
-				   (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT));
-	
-	if (internal_MEMORY_OUT_VAL)
-	  {
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
-	    internal_MEMORY_OUT_SELECT_QUEUE = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?SELECT_LOAD_QUEUE_SPECULATIVE:SELECT_LOAD_QUEUE;
-	    
-	    memory_out_context_id    = _load_queue [internal_MEMORY_OUT_PTR]._context_id;
-	    memory_out_front_end_id  = _load_queue [internal_MEMORY_OUT_PTR]._front_end_id;
-	    memory_out_ooo_engine_id = _load_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
-	    memory_out_packet_id     = _load_queue [internal_MEMORY_OUT_PTR]._packet_id ;
-	    memory_out_cancel        = _load_queue [internal_MEMORY_OUT_PTR]._cancel    ;
-	    memory_out_write_rd      = _load_queue [internal_MEMORY_OUT_PTR]._write_rd  ;
-	    memory_out_num_reg_rd    = _load_queue [internal_MEMORY_OUT_PTR]._num_reg_rd;
-
-	    Tdcache_data_t data_old = _load_queue [internal_MEMORY_OUT_PTR]._rdata;
-	    Tdcache_data_t data_new = extend<Tdcache_data_t>(_param->_size_general_data,
-							     data_old >> _load_queue [internal_MEMORY_OUT_PTR]._shift,
-							     _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed,
-							     _load_queue [internal_MEMORY_OUT_PTR]._access_size);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (old) : %.8x",data_old);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (new) : %.8x",data_new);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * address      : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._address);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * rdata        : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * shift        : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * signed?      : %d",_load_queue [internal_MEMORY_OUT_PTR]._is_load_signed);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * access_size  : %d",_load_queue [internal_MEMORY_OUT_PTR]._access_size);
-
-	    Texception_t exception      = _load_queue [internal_MEMORY_OUT_PTR]._exception;
-	    bool         have_exception = ((exception != EXCEPTION_MEMORY_NONE) and
-					   (exception != EXCEPTION_MEMORY_MISS_SPECULATION));
-
-	    // if exception, rdata content the address of load, else content read data.
-	    memory_out_data_rd       = (have_exception)?data_old:data_new;
-	    memory_out_exception     = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?EXCEPTION_MEMORY_LOAD_SPECULATIVE:exception;
-
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",exception);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",memory_out_exception);
-
-	    break; // we have find a entry !!! stop the search
-	  }
-      }
-
-    if (not internal_MEMORY_OUT_VAL)
-      {
-	log_printf(TRACE,Load_store_unit,FUNCTION,"    * Store queue");
-
-	for (uint32_t i=0; i<_param->_size_store_queue; ++i)
-	  {
-	    internal_MEMORY_OUT_PTR = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
-	    // Can retire an store instruction if :
-	    //  * state is commit
-	    //  * none load must check this store
-
-
-	    bool val_head = ((i==0) and
-			     (_store_queue [internal_MEMORY_OUT_PTR]._state       == STORE_QUEUE_COMMIT) and
-			     (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == true) and
-			     (reg_STORE_QUEUE_NB_CHECK [internal_MEMORY_OUT_PTR] == 0)
-			     );
-
-	    bool val_commit = ((_store_queue [internal_MEMORY_OUT_PTR]._state       != STORE_QUEUE_EMPTY) and
-			       (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == false));
-
-	    if (val_head or val_commit)
-	      {
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
-		
-		internal_MEMORY_OUT_VAL          = 1;
-		internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
-		
-		memory_out_context_id    = _store_queue [internal_MEMORY_OUT_PTR]._context_id;
-		memory_out_front_end_id  = _store_queue [internal_MEMORY_OUT_PTR]._front_end_id;
-		memory_out_ooo_engine_id = _store_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
-		memory_out_packet_id     = _store_queue [internal_MEMORY_OUT_PTR]._packet_id ;
-		memory_out_cancel        = _store_queue [internal_MEMORY_OUT_PTR]._cancel;
-//              memory_out_write_rd  	 
-//              memory_out_num_reg_rd	 
-		memory_out_data_rd       = _store_queue [internal_MEMORY_OUT_PTR]._address; // to the exception
-		memory_out_exception     = _store_queue [internal_MEMORY_OUT_PTR]._exception;
-		memory_out_no_sequence   = val_commit;
-		break; // find an entry
-	      }
-
-	  }
-      }
-
-    // write output
-    if (_param->_have_port_context_id)
-    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   [0], memory_out_context_id   );
-    if (_param->_have_port_front_end_id)
-    PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id );
-    if (_param->_have_port_ooo_engine_id)
-    PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id);
-    if (_param->_have_port_rob_ptr)
-    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    [0], memory_out_packet_id    );
-//  PORT_WRITE(out_MEMORY_OUT_OPERATION    [0], memory_out_operation    );
-//  PORT_WRITE(out_MEMORY_OUT_TYPE         [0], TYPE_MEMORY             );
-    PORT_WRITE(out_MEMORY_OUT_CANCEL       [0], memory_out_cancel       );
-    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     [0], memory_out_write_rd     );
-    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   [0], memory_out_num_reg_rd   );
-    PORT_WRITE(out_MEMORY_OUT_DATA_RD      [0], memory_out_data_rd      );
-//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], memory_out_write_re     );
-//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], memory_out_num_reg_re   );
-//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], memory_out_data_re      );
-    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], 0);
-    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], 0);
-    PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], 0);
-    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    [0], memory_out_exception    );
-    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  [0], memory_out_no_sequence  );// hack
-#ifdef DEBUG
-    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], memory_out_data_rd);
-#else
-    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], 0);
-#endif
-
-    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-    Tcontext_t        dcache_req_context_id = 0;
-    Tpacket_t         dcache_req_packet_id  = 0;
-    Tdcache_address_t dcache_req_address    = 0;
-    Tdcache_type_t    dcache_req_type       = 0;
-    Tdcache_data_t    dcache_req_wdata      = 0;
-
-    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test DCACHE_REQ");
-
-    internal_DCACHE_REQ_VAL = 0;
-
-    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = (*_speculative_access_queue_control)[0];
-
-    // Test store and load queue
-    if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE)
-      {
-	log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);
-
-	internal_DCACHE_REQ_VAL          = 1;
-	internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
-
-	if (_param->_have_port_dcache_context_id)
-	  {
-	    Tcontext_t context_id    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
-	    Tcontext_t front_end_id  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
-	    Tcontext_t ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
-	    
-	    dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
-				     (front_end_id <<(_param->_size_context_id)) |
-				     (context_id));
-	  }
-
-	dcache_req_packet_id  = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write);
-	dcache_req_address    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb;
-	dcache_req_type       = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation);
-
-// 	log_printf(TRACE,Load_store_unit,FUNCTION,"      * address            : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address);
-//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * mask               : %.8x",_param->_mask_address_msb);
-        log_printf(TRACE,Load_store_unit,FUNCTION,"      * dcache_req_address : %.8x",dcache_req_address);
-
-#ifdef SYSTEMC_VHDL_COMPATIBILITY
-	dcache_req_wdata      = 0;
-#endif
-      }
-    else
-      {
-	// Test an store must be commited.
-	if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE)
-	  {
-	    internal_DCACHE_REQ_VAL          = 1;
-	    internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE;
-	    
-	    if (_param->_have_port_dcache_context_id)
-	      {
-		Tcontext_t context_id    = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id;
-		Tcontext_t front_end_id  = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id;
-		Tcontext_t ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id;
-		
-		dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
-					 (front_end_id <<(_param->_size_context_id)) |
-					 (context_id));
-	      }
-
-	    // FIXME : il peut avoir plusieurs store avec le même paquet_id ... pour l'instant pas très grave car pas de retour (enfin seul les bus error sont des retours)
-	    dcache_req_packet_id  = DCACHE_REQ_IS_STORE(reg_STORE_QUEUE_PTR_READ);
-	    dcache_req_address    = _store_queue [reg_STORE_QUEUE_PTR_READ]._address;
-	    dcache_req_type       = operation_to_dcache_type(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation);
-	    dcache_req_wdata      = _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata;
-	  }
-      }
-
-    if (_param->_have_port_dcache_context_id)
-    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id);
-    PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id );
-    PORT_WRITE(out_DCACHE_REQ_ADDRESS   [0], dcache_req_address   );
-    PORT_WRITE(out_DCACHE_REQ_TYPE      [0], dcache_req_type      );
-    PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
-      }
-    else
-      {
-        // Reset
-    internal_MEMORY_OUT_VAL = 0;
-//  internal_MEMORY_OUT_PTR =0
-//  internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
-
-    internal_DCACHE_REQ_VAL = 0;
-    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = 0;
-//  internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
-      }
-
-    // Write output
-    PORT_WRITE(out_MEMORY_OUT_VAL [0], internal_MEMORY_OUT_VAL);
-    PORT_WRITE(out_DCACHE_REQ_VAL [0], internal_DCACHE_REQ_VAL);
-
-
-    log_end(Load_store_unit,FUNCTION);
-  };
-
-}; // end namespace load_store_unit
-}; // end namespace execute_unit
-}; // end namespace multi_execute_unit
-}; // end namespace execute_loop
-}; // end namespace multi_execute_loop
-}; // end namespace core
-
-}; // end namespace behavioural
-}; // end namespace morpheo              
-#endif
-//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_access_transition.cpp	(revision 144)
+++ 	(revision )
@@ -1,1424 +1,0 @@
-#ifdef SYSTEMC
-/*
- * $Id$
- *
- * [ Description ]
- * 
- */
-
-#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
-#include "Behavioural/include/Identification.h"
-
-namespace morpheo                    {
-namespace behavioural {
-namespace core {
-namespace multi_execute_loop {
-namespace execute_loop {
-namespace multi_execute_unit {
-namespace execute_unit {
-namespace load_store_unit {
-
-template <typename T>
-T swapBytes (T data, uint32_t size_data, uint32_t size_access)
-{
-  uint64_t x = static_cast<uint64_t>(data);
-
-//   switch (size_data)
-//     {
-//     case 2 : // 16 bits
-//       {
-//         switch (size_access)
-//           {
-//           case 2 : 
-//             {
-//               x = ((((x>> 8)&0xff) <<  0) |
-//                    (((x>> 0)&0xff) <<  8) );
-//               break;
-//             }
-//           default :
-//             {
-//               break;
-//             }
-//           }
-//         break;
-//       }
-//     case 4 : // 32 bits
-//       {
-//         switch (size_access)
-//           {
-//           case 2 : 
-//             {
-//               x = ((((x>> 8)&0xff) <<  0) |
-//                    (((x>> 0)&0xff) <<  8) |
-//                    (((x>>24)&0xff) << 16) |
-//                    (((x>>16)&0xff) << 24) );
-//               break;
-//             }
-//           case 4 : 
-//             {
-//               x = ((((x>>24)&0xff) <<  0) |
-//                    (((x>>16)&0xff) <<  8) |
-//                    (((x>> 8)&0xff) << 16) |
-//                    (((x>> 0)&0xff) << 24) );
-//               break;
-//             }
-//           default :
-//             {
-//               break;
-//             }
-//           }
-//         break;
-//       }
-//     case 8 : // 64 bits
-//       {
-//         switch (size_access)
-//           {
-//           case 2 : 
-//             {
-//               x = ((((x>> 8)&0xff) <<  0) |
-//                    (((x>> 0)&0xff) <<  8) |
-//                    (((x>>24)&0xff) << 16) |
-//                    (((x>>16)&0xff) << 24) |
-//                    (((x>>40)&0xff) << 32) |
-//                    (((x>>32)&0xff) << 40) |
-//                    (((x>>56)&0xff) << 48) |
-//                    (((x>>48)&0xff) << 56) );
-//               break;
-//             }
-//           case 4 : 
-//             {
-//               x = ((((x>>24)&0xff) <<  0) |
-//                    (((x>>16)&0xff) <<  8) |
-//                    (((x>> 8)&0xff) << 16) |
-//                    (((x>> 0)&0xff) << 24) |
-//                    (((x>>56)&0xff) << 32) |
-//                    (((x>>48)&0xff) << 40) |
-//                    (((x>>40)&0xff) << 48) |
-//                    (((x>>32)&0xff) << 56) );
-//               break;
-//             }
-//           case 8 : 
-//             {
-//               x = ((((x>>56)&0xff) <<  0) |
-//                    (((x>>48)&0xff) <<  8) |
-//                    (((x>>40)&0xff) << 16) |
-//                    (((x>>32)&0xff) << 24) |
-//                    (((x>>24)&0xff) << 32) |
-//                    (((x>>16)&0xff) << 40) |
-//                    (((x>> 8)&0xff) << 48) |
-//                    (((x>> 0)&0xff) << 56) );
-//               break;
-//             }
-//           default :
-//             {
-//               break;
-//             }
-//           }
-//         break;
-//       }
-//     default :
-//       {
-//         break;
-//       }
-//     }
-
-
-  uint64_t y=0;
-
-  for (uint32_t i=0; i<size_data; i+=size_access)
-    {
-      uint32_t offset = i<<3;
-
-      switch (size_access)
-        {
-        case 1 :
-          {
-            y = x;
-            break;
-          }
-        case 2 : 
-          {
-            y |= ((((x>>( 8+offset))&0xff) << ( 0+offset)) |
-                  (((x>>( 0+offset))&0xff) << ( 8+offset)) );
-            break;
-          }
-        case 4 : 
-          {
-            y |= ((((x>>(24+offset))&0xff) << ( 0+offset)) |
-                  (((x>>(16+offset))&0xff) << ( 8+offset)) |
-                  (((x>>( 8+offset))&0xff) << (16+offset)) |
-                  (((x>>( 0+offset))&0xff) << (24+offset)) );
-            break;
-          }
-        case 8 : 
-          {
-            y |= ((((x>>(56+offset))&0xff) << ( 0+offset)) |
-                  (((x>>(48+offset))&0xff) << ( 8+offset)) |
-                  (((x>>(40+offset))&0xff) << (16+offset)) |
-                  (((x>>(32+offset))&0xff) << (24+offset)) |
-                  (((x>>(24+offset))&0xff) << (32+offset)) |
-                  (((x>>(16+offset))&0xff) << (40+offset)) |
-                  (((x>>( 8+offset))&0xff) << (48+offset)) |
-                  (((x>>( 0+offset))&0xff) << (56+offset)) );
-            break;
-          }
-        default :
-            {
-              break;
-            }
-        }
-    }
-
-  return static_cast<T>(y);
-}
-
-template <typename T>
-T swapBits (T data, uint32_t size_data, uint32_t size_access)
-{
-  uint8_t x = static_cast<uint8_t>(data);
-
-  uint8_t y=0;
-
-  for (uint32_t i=0; i<size_data; i+=size_access)
-    {
-      uint32_t offset = i;
-
-      switch (size_access)
-        {
-        case 1 :
-          {
-            y = x;
-            break;
-          }
-        case 2 : 
-          {
-            y |= ((((x>>( 1+offset))&0x1) << ( 0+offset)) |
-                  (((x>>( 0+offset))&0x1) << ( 1+offset)) );
-            break;
-          }
-        case 4 : 
-          {
-            y |= ((((x>>( 3+offset))&0x1) << ( 0+offset)) |
-                  (((x>>( 2+offset))&0x1) << ( 1+offset)) |
-                  (((x>>( 1+offset))&0x1) << ( 2+offset)) |
-                  (((x>>( 0+offset))&0x1) << ( 3+offset)) );
-            break;
-          }
-        case 8 : 
-          {
-            y |= ((((x>>( 7+offset))&0x1) << ( 0+offset)) |
-                  (((x>>( 6+offset))&0x1) << ( 1+offset)) |
-                  (((x>>( 5+offset))&0x1) << ( 2+offset)) |
-                  (((x>>( 4+offset))&0x1) << ( 3+offset)) |
-                  (((x>>( 3+offset))&0x1) << ( 4+offset)) |
-                  (((x>>( 2+offset))&0x1) << ( 5+offset)) |
-                  (((x>>( 1+offset))&0x1) << ( 6+offset)) |
-                  (((x>>( 0+offset))&0x1) << ( 7+offset)) );
-            break;
-          }
-        default :
-            {
-              break;
-            }
-        }
-    }
-
-  return static_cast<T>(y);
-}
-
-#undef  FUNCTION
-#define FUNCTION "Load_store_unit::function_speculative_load_access_transition"
-  void Load_store_unit::function_speculative_load_access_transition (void)
-  {
-    log_begin(Load_store_unit,FUNCTION);
-    log_function(Load_store_unit,FUNCTION,_name.c_str());
-
-    if (PORT_READ(in_NRESET) == 0)
-      {
-	// Reset : clear all queue
-	_speculative_access_queue_control->clear();
-
-	reg_STORE_QUEUE_PTR_READ       = 0;
-	reg_LOAD_QUEUE_CHECK_PRIORITY  = 0;
-
-	for (uint32_t i=0; i< _param->_size_store_queue             ; i++)
-          {
-            reg_STORE_QUEUE_NB_CHECK  [i] = 0;
-//          reg_STORE_QUEUE_INVALID   [i] = 0;
-  	    _store_queue              [i]._state                 = STORE_QUEUE_EMPTY;
-  	    _store_queue              [i]._context_id            = 0; // not necessary
-  	    _store_queue              [i]._front_end_id          = 0; // not necessary
-  	    _store_queue              [i]._ooo_engine_id         = 0; // not necessary
-  	    _store_queue              [i]._packet_id             = 0; // not necessary
-  	    _store_queue              [i]._operation             = 0; // not necessary
-  	    _store_queue              [i]._cancel                = 0; // not necessary
-  	    _store_queue              [i]._load_queue_ptr_write  = 0; // not necessary
-  	    _store_queue              [i]._address               = 0; // not necessary
-  	    _store_queue              [i]._wdata                 = 0; // not necessary
-//	    _store_queue              [i]._write_rd              = 0; // not necessary
-//	    _store_queue              [i]._num_reg_rd            = 0; // not necessary
-  	    _store_queue              [i]._exception             = 0; // not necessary
-  	    _store_queue              [i]._send_commit           = 0; // not necessary
-          }
-
-	for (uint32_t i=0; i< _param->_size_load_queue              ; i++)
-          {
-            _load_queue               [i]._state                 = LOAD_QUEUE_EMPTY;
-            _load_queue               [i]._context_id            = 0; // not necessary
-            _load_queue               [i]._front_end_id          = 0; // not necessary
-            _load_queue               [i]._ooo_engine_id         = 0; // not necessary
-            _load_queue               [i]._packet_id             = 0; // not necessary
-            _load_queue               [i]._operation             = 0; // not necessary
-            _load_queue               [i]._cancel                = 0; // not necessary
-            _load_queue               [i]._store_queue_ptr_write = 0; // not necessary
-            _load_queue               [i]._store_queue_ptr_read  = 0; // not necessary
-            _load_queue               [i]._store_queue_empty     = 0; // not necessary
-            _load_queue               [i]._address               = 0; // not necessary
-            _load_queue               [i]._check_hit_byte        = 0; // not necessary 
-            _load_queue               [i]._check_hit             = 0; // not necessary
-            _load_queue               [i]._shift                 = 0; // not necessary
-            _load_queue               [i]._is_load_signed        = 0; // not necessary
-            _load_queue               [i]._access_size           = 0; // not necessary
-            _load_queue               [i]._rdata                 = 0; // not necessary
-            _load_queue               [i]._write_rd              = 0; // not necessary
-            _load_queue               [i]._num_reg_rd            = 0; // not necessary
-            _load_queue               [i]._exception             = 0; // not necessary
-            _load_queue               [i]._can_speculative_commit= 0; // not necessary
-          }
-
-	for (uint32_t i=0; i< _param->_size_speculative_access_queue; i++)
-          {
-            _speculative_access_queue [i]._state                 = SPECULATIVE_ACCESS_QUEUE_EMPTY;
-            _speculative_access_queue [i]._context_id            = 0; // not necessary
-            _speculative_access_queue [i]._front_end_id          = 0; // not necessary
-            _speculative_access_queue [i]._ooo_engine_id         = 0; // not necessary
-            _speculative_access_queue [i]._packet_id             = 0; // not necessary
-            _speculative_access_queue [i]._operation             = 0; // not necessary
-            _speculative_access_queue [i]._cancel                = 0; // not necessary
-            _speculative_access_queue [i]._load_queue_ptr_write  = 0; // not necessary
-            _speculative_access_queue [i]._store_queue_ptr_write = 0; // not necessary
-            _speculative_access_queue [i]._store_queue_ptr_read  = 0; // not necessary
-            _speculative_access_queue [i]._store_queue_empty     = 0; // not necessary
-            _speculative_access_queue [i]._address               = 0; // not necessary
-            _speculative_access_queue [i]._write_rd              = 0; // not necessary
-            _speculative_access_queue [i]._num_reg_rd            = 0; // not necessary
-            _speculative_access_queue [i]._exception             = 0; // not necessary
-          }
-      }
-    else
-      {
-        // load_queue_push if speculative_access_queue have access at the dcache, or they have an event
-	bool load_queue_push = (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE);
-
-	//================================================================
-	// Interface "MEMORY_OUT"
-	//================================================================
-
-        if ((    internal_MEMORY_OUT_VAL  == 1) and
-            (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1))
-          {
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_OUT[0] transaction");
-
-	    switch (internal_MEMORY_OUT_SELECT_QUEUE)
-	      {
-	      case SELECT_STORE_QUEUE :
-		{
-		  // =======================
-		  // ===== STORE_QUEUE =====
-		  // =======================
-		  
-		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue [%d]",internal_MEMORY_OUT_PTR);
-	    
-		  // Entry flush and increase the read pointer
-		  if (_store_queue [internal_MEMORY_OUT_PTR]._send_commit)
-		    {
-		      _store_queue [internal_MEMORY_OUT_PTR]._state = STORE_QUEUE_EMPTY;
-		      reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue;
-		    }
-		  else
-		    _store_queue [internal_MEMORY_OUT_PTR]._send_commit = true;
-
-		  break;
-		}
-	      case SELECT_LOAD_QUEUE :
-		{
-		  // ======================
-		  // ===== LOAD_QUEUE =====
-		  // ======================
-		  
-		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * load_queue  [%d]",internal_MEMORY_OUT_PTR);
-		  
-		  // Entry flush and increase the read pointer
-		  
-		  _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY;
-		  
-		  // reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
-
-		  break;
-		}
-	      case SELECT_LOAD_QUEUE_SPECULATIVE :
-		{
-		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * load_queue  [%d] (speculative)",internal_MEMORY_OUT_PTR);
-		  
-                  // !!! WARNING !!!
-                  // !!! Test special case :
-                  // !!! in a cycle an instruction can check the last store AND commit instruction
-                  // !!! also the memory_out is before the port_check
-
-		  _load_queue [internal_MEMORY_OUT_PTR]._state    = LOAD_QUEUE_CHECK;
-		  // NOTE : a speculative load write in the register file.
-		  // if the speculation is a miss, write_rd is re set at 1.
-		  _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0;
-
-#ifdef STATISTICS
-                  if (usage_is_set(_usage,USE_STATISTICS))
-                    (*_stat_nb_inst_load_commit_speculative) ++;
-#endif
-
-		  break;
-		}
-
-		break;
-	      }
-	  }
-
-	//================================================================
-	// Interface "PORT_CHECK"
-	//================================================================
-	
-	// Plusieurs moyens de faire la verification de dépendance entre les loads et les stores.
-	//  1) un load ne peut vérifier qu'un store par cycle. Dans ce cas port_check <= size_load_queue
-	//  2) un load tente de vérifier le maximum de store par cycle. Dans ce cas ce n'est pas du pointeur d'écriture qu'il lui faut mais un vecteur de bit indiquant quel store à déjà été testé. De plus il faut un bit indiquant qu'il y a un match mais que ce n'est pas forcément le premier.
-
-	// solution 1)
- 	log_printf(TRACE,Load_store_unit,FUNCTION,"  * CHECK");
-	for (uint32_t i=0, nb_check=0; (nb_check<_param->_nb_port_check) and (i<_param->_size_load_queue); i++)
-	  {
-            // Get an index from load queue
-	    uint32_t index_load_queue = (i + reg_LOAD_QUEUE_CHECK_PRIORITY)%_param->_size_load_queue;
-
-            // Test if this load must ckecked store queue
-	    if (((_load_queue[index_load_queue]._state == LOAD_QUEUE_WAIT_CHECK) or
-		 (_load_queue[index_load_queue]._state == LOAD_QUEUE_COMMIT_CHECK) or
-		 (_load_queue[index_load_queue]._state == LOAD_QUEUE_CHECK)) and
-		is_operation_memory_load(_load_queue[index_load_queue]._operation))
-	      {
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * Find a load : %d",index_load_queue);
-
-		nb_check++; // use one port
-
-		// find a entry that it need a check
-		Tlsq_ptr_t store_queue_ptr_write     = _load_queue[index_load_queue]._store_queue_ptr_write;
-		Tlsq_ptr_t store_queue_ptr_read      = _load_queue[index_load_queue]._store_queue_ptr_read ;
- 		Tlsq_ptr_t store_queue_empty         = _load_queue[index_load_queue]._store_queue_empty    ;
-// 		Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write;
-
-                // Init variable
-		bool       end_check    = false;
-		bool       change_state = false;
-		bool       next         = false;
-
-		// At the first store queue empty, stop check.
-		// Explication :
-		//  * rename logic keep a empty case in the store queue (also size_store_queue > 1)
-		//  * when a store is out of store queue, also it was in head of re order buffer. Also, they are none previous load.
-
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_ptr_write    : %d",store_queue_ptr_write);
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_ptr_read     : %d",store_queue_ptr_read );
-// 		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_empty        : %d",store_queue_empty );
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * reg_STORE_QUEUE_PTR_READ : %d",reg_STORE_QUEUE_PTR_READ);
-
- 		if ((store_queue_ptr_write ==     store_queue_ptr_read) or
-		    (store_queue_ptr_write == reg_STORE_QUEUE_PTR_READ))
-// 		if (store_queue_empty)
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write == store_queue_ptr_read");
-		    end_check    = true;
-		    change_state = true;
-		  }
-		else
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write != store_queue_ptr_read");
-
-		    store_queue_ptr_write = (store_queue_ptr_write-1)%(_param->_size_store_queue); // store_queue_ptr_write target the next slot to write, also the slot is not significatif when the load is renaming
-
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write : %d",store_queue_ptr_write);
-
-                    bool test_thread_id = true;
-                    
-                    // Test thread id
-                    if (_param->_have_port_context_id)
-                      test_thread_id &= (_load_queue[index_load_queue]._context_id    == _store_queue[store_queue_ptr_write]._context_id);
-                    if (_param->_have_port_front_end_id)
-                      test_thread_id &= (_load_queue[index_load_queue]._front_end_id  == _store_queue[store_queue_ptr_write]._front_end_id);
-                    if (_param->_have_port_ooo_engine_id)
-                      test_thread_id &= (_load_queue[index_load_queue]._ooo_engine_id == _store_queue[store_queue_ptr_write]._ooo_engine_id);
-		    
-                    // switch on store_queue state
-		    switch (_store_queue[store_queue_ptr_write]._state)
-		      {
-		      case STORE_QUEUE_VALID_NO_SPECULATIVE : 
-		      case STORE_QUEUE_COMMIT :
-		      case STORE_QUEUE_VALID_SPECULATIVE :
-			{
-                          log_printf(TRACE,Load_store_unit,FUNCTION,"      * store have a valid entry");
-			  
-			  // TODO : MMU - nous considérons que les adresses sont physique
-			  if (test_thread_id)
-			    {
-			      // the load and store are in the same thread. Now, we must test address.
-
-			      log_printf(TRACE,Load_store_unit,FUNCTION,"        * load and store is the same thread.");
-			      Tdcache_address_t load_addr  = _load_queue [index_load_queue ]._address;
-			      Tdcache_address_t store_addr = _store_queue[store_queue_ptr_write]._address;
-			      
-			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * load_addr                     : %.8x.",load_addr );
-			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * store_addr                    : %.8x.",store_addr);
-			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * load_addr  & mask_address_msb : %.8x.",load_addr  & _param->_mask_address_msb);
-			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * store_addr & mask_address_msb : %.8x.",store_addr & _param->_mask_address_msb);
-			      // Test if the both address target the same "word"
-			      if ((load_addr  & _param->_mask_address_msb) == 
-				  (store_addr & _param->_mask_address_msb))
-				{
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * address_msb is the same.");
-
-				  // all case - [] : store, () : load
-				  // (1) store_max >= load_max and store_min <= load_min  ...[...(...)...]... Ok - inclusion in store
-				  // (2) store_min >  load_max                            ...[...]...(...)... Ok - no conflit
-				  // (3) store_max <  load_min                            ...(...)...[...]... Ok - no conflit
-				  // (4) store_max <  load_max and store_min >  load_min  ...(...[...]...)... Ko - inclusion in load
-				  // (5) store_max >= load_max and store_min >  load_min  ...[...(...]...)... Ko - conflit
-				  // (6) store_max <  load_max and store_min <= load_min  ...(...[...)...]... Ko - conflit
-				  // but :
-				  // load in the cache is a word !
-				  // the mask can be make when the load is commited. Also, the rdata content a full word.
-				  // the only case is (4)
-				  
-                                  // Read data
-                                  bool is_big_endian = true;
-
-				  Tgeneral_data_t   load_data      = _load_queue [index_load_queue ]._rdata  ;
-				  Tgeneral_data_t   store_data     = _store_queue[store_queue_ptr_write]._wdata  ;
-                                  Tdcache_address_t check_hit_byte = _load_queue [index_load_queue ]._check_hit_byte;
-                                  Tcontrol_t        check_hit      = _load_queue [index_load_queue ]._check_hit;
-                                  uint32_t          load_size_access  = memory_size(_load_queue [index_load_queue ]._operation)>>3;
-                                  uint32_t          store_size_access = memory_size(_store_queue[store_queue_ptr_write]._operation)>>3;
-
-                                  log_printf(TRACE,Load_store_unit,FUNCTION,"            * is_big_endian           : %d",is_big_endian);
-                                  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data               : 0x%.8x",load_data);
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_data              : 0x%.8x",store_data);
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte          : %x",check_hit_byte);
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit               : %d",check_hit);
-
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_size_access        : %d",load_size_access );
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_size_access       : %d",store_size_access);
-
-                                  if (is_big_endian)
-                                    {
-                                      // swap in little endian
-                                      load_data      = swapBytes<Tgeneral_data_t  >(load_data     , _param->_size_general_data>>3,load_size_access);
-                                      store_data     = swapBytes<Tgeneral_data_t  >(store_data    , _param->_size_general_data>>3,store_size_access);
-                                      check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access);
-                                      
-                                      
-                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data      (swap 1) : 0x%.8x",load_data);
-                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_data     (swap 1) : 0x%.8x",store_data);
-                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte (swap 1) : %x",check_hit_byte);
-                                    }
-
-                                  uint32_t store_nb_byte     = (1<<memory_access(_store_queue[store_queue_ptr_write]._operation));
-
-                                  // Take interval to the store
-				  uint32_t store_num_byte_min = (store_addr & _param->_mask_address_lsb);
-				  uint32_t store_num_byte_max = store_num_byte_min+store_nb_byte;
-
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_num_byte_min      : %d",store_num_byte_min);
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_num_byte_max      : %d",store_num_byte_max);
-
-
-				  // The bypass is checked byte per byte
-                                  // Is same endianness : because to change endianness, we must write in special register. Also the pipeline is flushed.
-				  for (uint32_t num_store_byte=store_num_byte_min; num_store_byte<store_num_byte_max; num_store_byte ++)
-				    {
-                                      // Make a mask
-                                      uint32_t num_load_byte = num_store_byte;
-
-//                                       if (is_big_endian)
-//                                         {
-//                                           // sd 0 : 0 1 2 3 4 5 6 7
-//                                           // ld 0 : 0 1 2 3 4 5 6 7 >>  0 
-//                                           // lw 0 :         0 1 2 3 >>  0 -4
-//                                           // lw 4 : 4 5 6 7         >> 32 +4
-//                                           // lh 0 :             0 1 >>  0 -6
-//                                           // lh 2 :         2 3     >> 16 -2
-//                                           // lh 4 :     4 5         >> 32 +2
-//                                           // lh 6 : 6 7             >> 48 +6
-//                                           // lb 0 :               0 >>  0 -7
-//                                           // lb 1 :             1   >>  8 -5
-//                                           // lb 2 :           2     >> 16 -3
-//                                           // lb 3 :         3       >> 24 -1
-//                                           // lb 4 :       4         >> 32 +1
-//                                           // lb 5 :     5           >> 40 +3
-//                                           // lb 6 :   6             >> 48 +5
-//                                           // lb 7 : 7               >> 56 +7
-
-//                                           // diff : (store_nb_byte + load_nb_byte) - 2*nb_load_byte*((num_store_byte+1)
-
-//                                           // store duplicate = all store access can be see as full size_data store
-// //                                           uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load_queue ]._operation));
-
-// //                                           int32_t diff = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1));
-
-// //                                           num_load_byte =num_store_byte+diff;
-
-// //                                           log_printf(TRACE,Load_store_unit,FUNCTION,"              * load_nb_byte   : %d",load_nb_byte);
-// //                                           log_printf(TRACE,Load_store_unit,FUNCTION,"              * diff           : %d",diff);
-
-
-//                                           num_load_byte = num_store_byte;
-//                                         }
-//                                       else
-//                                         {
-//                                           // sd 0 : 0 1 2 3 4 5 6 7
-//                                           // ld 0 : 0 1 2 3 4 5 6 7 >>  0
-//                                           // lw 0 :         4 5 6 7 >>  0
-//                                           // lw 4 : 0 1 2 3         >> 32
-//                                           // lh 0 :             6 7 >>  0
-//                                           // lh 2 :         4 5     >> 16
-//                                           // lh 4 :     2 3         >> 32
-//                                           // lh 6 : 0 1             >> 48
-//                                           // lb 0 :               7 >>  0
-//                                           // lb 1 :             6   >>  8
-//                                           // lb 2 :           5     >> 16
-//                                           // lb 3 :         4       >> 24
-//                                           // lb 4 :       3         >> 32
-//                                           // lb 5 :     2           >> 40
-//                                           // lb 6 :   1             >> 48
-//                                           // lb 7 : 0               >> 56
-                                          
-//                                           num_load_byte = num_store_byte;
-//                                         }
-
-				      uint32_t mask  = 1<<num_load_byte;
-
-				      log_printf(TRACE,Load_store_unit,FUNCTION,"              * num_store_byte : %d",num_store_byte);
-				      log_printf(TRACE,Load_store_unit,FUNCTION,"              * num_load_byte  : %d",num_load_byte);
-				      log_printf(TRACE,Load_store_unit,FUNCTION,"              * mask           : %d",mask);
-
-				      // Accept the bypass if :
-                                      //   * they have not a previous bypass with an another store
-                                      //   * it's a valid request of load
-				      if ((check_hit_byte&mask)==0)
-					{
-                                          // Note : Store is duplicate = all store access can be see as full size_data store
-
-                                          uint32_t num_store_bit_min = num_store_byte<<3; //*8
-//                                        uint32_t num_store_bit_max = num_store_bit_min+8-1;
-                                          uint32_t num_load_bit_min  = num_load_byte <<3; //*8
-                                          uint32_t num_load_bit_max  = num_load_bit_min+8-1;
-
-					  log_printf(TRACE,Load_store_unit,FUNCTION,"              * bypass !!!");
-//                                        log_printf(TRACE,Load_store_unit,FUNCTION,"              * interval store : [%d:%d]",num_store_bit_max,num_store_bit_min);
-                                          log_printf(TRACE,Load_store_unit,FUNCTION,"              * interval store : [..:%d]",num_store_bit_min);
-                                          log_printf(TRACE,Load_store_unit,FUNCTION,"              * interval load  : [%d:%d]",num_load_bit_max,num_load_bit_min);
-					  log_printf(TRACE,Load_store_unit,FUNCTION,"                * rdata_old : 0x%.8x", load_data);
-
-					  load_data = ((((store_data>>num_store_bit_min) & 0xff) << num_load_bit_min) |
-                                                       mask_not<Tdcache_data_t>(load_data,num_load_bit_max,num_load_bit_min));
-
-					  check_hit_byte |= mask;
-					  check_hit       = 1;
-					  change_state = true;
-
-					  log_printf(TRACE,Load_store_unit,FUNCTION,"                * rdata_new : 0x%.8x", load_data);
-					}
-				    }
-
-                                  if (is_big_endian)
-                                    {
-                                      // swap in little endian
-                                      load_data      = swapBytes<Tgeneral_data_t  >(load_data     , _param->_size_general_data>>3,load_size_access);
-                                      check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access);
-                                      
-                                      
-                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data      (swap 2) : 0x%.8x",load_data);
-                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte (swap 2) : %x",check_hit_byte);
-                                    }
-
-				  _load_queue[index_load_queue]._rdata          = load_data;
-                                  _load_queue[index_load_queue]._check_hit_byte = check_hit_byte;
-                                  _load_queue[index_load_queue]._check_hit      = check_hit;
-
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data  (after) : 0x%.8x",load_data);
-
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit          : %x",check_hit);
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte     : %x",check_hit_byte);
-
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * mask_end_check     : %x",(-1& _param->_mask_address_lsb));
-				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * mask_check_hit_byte: %x",_param->_mask_check_hit_byte);
-				  // The check is finish if all bit is set
-				  end_check = (_load_queue[index_load_queue]._check_hit_byte == _param->_mask_check_hit_byte);
-				}
-			    }
-			  
-			  next = true;
-			  break;
-			}
-		      case STORE_QUEUE_EMPTY :
-			{
-			  log_printf(TRACE,Load_store_unit,FUNCTION,"      * store is empty ... wait.");
-			  break;
-			}
-
-		      case STORE_QUEUE_NO_VALID_NO_SPECULATIVE :
-			{
-                          log_printf(TRACE,Load_store_unit,FUNCTION,"      * store have an invalid entry");
-
-			  if (test_thread_id)
-                            {
-                              end_check    = true; // previous store is invalid -> exception
-                              change_state = true;
-                            }
-                          else
-                            next = true;
-                            
-			  break;
-			}
-		      }
-		  }
-
-		if (next)
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * next");
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * new store_queue_ptr_write : %d",store_queue_ptr_write);
-
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * update reg_STORE_QUEUE_NB_CHECK");
-#ifdef DEBUG
-                    if (reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write] == 0)
-                      throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
-#endif
-
-                    reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write] --;
-
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 1 [%d] <- %d", store_queue_ptr_write,reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write]);
-
-		    if ((store_queue_ptr_write ==     store_queue_ptr_read) or
-			(store_queue_ptr_write == reg_STORE_QUEUE_PTR_READ))
-		      {
-// 			store_queue_empty = true;
-			end_check         = true;
-			change_state      = true;
-		      }
-
-// 		    if (_load_queue[index_load_queue]._store_queue_ptr_write == 0)
-// 		      _load_queue[index_load_queue]._store_queue_ptr_write = _param->_size_store_queue-1;
-// 		    else
-// 		      _load_queue[index_load_queue]._store_queue_ptr_write --;
-		    _load_queue[index_load_queue]._store_queue_ptr_write = store_queue_ptr_write; // because the index store have be decrease
- 		    _load_queue[index_load_queue]._store_queue_empty     = store_queue_empty; // because the index store have be decrease
-
-		    // FIXME : peut n'est pas obliger de faire cette comparaison. Au prochain cycle on le détectera que les pointeur sont égaux. Ceci évitera d'avoir deux comparateurs avec le registre "store_queue_ptr_read"
-		  }
-
-		if (change_state)
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * change_state");
-                    log_printf(TRACE,Load_store_unit,FUNCTION,"              * end_check : %d",end_check);
-
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * state old : %s",toString(_load_queue[index_load_queue]._state).c_str());
-
-		    switch (_load_queue[index_load_queue]._state)
-		      {
-		      case LOAD_QUEUE_WAIT_CHECK   : 
-                        {
-			  if (end_check)
-                            _load_queue[index_load_queue]._state = LOAD_QUEUE_WAIT  ; 
-                          break;
-                        }
-		      case LOAD_QUEUE_COMMIT_CHECK : 
-			{
-			  if (end_check)
-			    _load_queue[index_load_queue]._state = LOAD_QUEUE_COMMIT; 
-			  else
-			    _load_queue[index_load_queue]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end
-			  break;
-			}
-		      case LOAD_QUEUE_CHECK        : 
-			{
-			  if (end_check)
-			    _load_queue[index_load_queue]._state     = LOAD_QUEUE_COMMIT;
-
-			  // check find a bypass. A speculative load have been committed : report a speculation miss.
-			  if ((_load_queue[index_load_queue]._check_hit != 0) and 
-                              (_load_queue[index_load_queue]._write_rd  == 0) // is commit
-                              )
-			    {
-			      _load_queue[index_load_queue]._exception = EXCEPTION_MEMORY_MISS_SPECULATION;
-			      _load_queue[index_load_queue]._write_rd  = 1; // write the good result
-
-#ifdef STATISTICS
-                              if (usage_is_set(_usage,USE_STATISTICS))
-                                (*_stat_nb_inst_load_commit_miss) ++;
-#endif
-			    }
-			  
-			  break;
-			}
-		      default : break;
-		      }
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * state new : %s",toString(_load_queue[index_load_queue]._state).c_str());
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * exception : %d",_load_queue[index_load_queue]._exception);
-
-                    if (end_check//  and not store_queue_empty
-			)
-                      {
-                        log_printf(TRACE,Load_store_unit,FUNCTION,"                * end check, decrease all nb_check");
-                        
-                        uint32_t i=store_queue_ptr_write;
-                        while (i!=store_queue_ptr_read)
-                          {
-                            i=((i==0)?_param->_size_store_queue:i)-1;
-                            
-#ifdef DEBUG
-                            if (reg_STORE_QUEUE_NB_CHECK [i] == 0)
-                              throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
-#endif
-			    
-                            reg_STORE_QUEUE_NB_CHECK [i] --;
-
-			    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 2 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
-
-                            //i=(i+1)%_param->_size_store_queue;
-                          }
-			
-			_load_queue[index_load_queue]._store_queue_empty = true; // end of check
-                      }
-		  }
-	      }
-	    // else : don't use a port
-	  }
-	
-	//================================================================
-	// Interface "MEMORY_IN"
-	//================================================================
-	
-        if ((PORT_READ(in_MEMORY_IN_VAL [internal_MEMORY_IN_PORT]) == 1) and
-            (    internal_MEMORY_IN_ACK  == 1))
-          {
-            log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_IN [%d]",internal_MEMORY_IN_PORT);
-
-	    // Test operation :
-	    //~~~~~~~~~~~~~~~~~
-	    //  store  in store_queue
-	    //  load   in speculation_access_queue
-	    //  others in speculation_access_queue
-
-#ifdef DEBUG_TEST
-	    if (PORT_READ(in_MEMORY_IN_TYPE [internal_MEMORY_IN_PORT]) != TYPE_MEMORY)
-	      throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'");
-#endif
-	    Toperation_t    operation            = PORT_READ(in_MEMORY_IN_OPERATION[internal_MEMORY_IN_PORT]);
-	    Tcontrol_t      cancel               = PORT_READ(in_MEMORY_IN_CANCEL   [internal_MEMORY_IN_PORT]);
-	    Tgeneral_data_t address              = (PORT_READ(in_MEMORY_IN_IMMEDIAT[internal_MEMORY_IN_PORT]) +
-						    PORT_READ(in_MEMORY_IN_DATA_RA [internal_MEMORY_IN_PORT]));
-	    bool            exception_alignement = (mask_memory_access(operation) & address) != 0;
-						    
-	    if (is_operation_memory_store(operation) == true)
-	      {
-		// =======================
-		// ===== STORE_QUEUE =====
-		// =======================
-		// There a two store request type :
-		//   - first is operation with address and data
-		//   - second is the information of re order buffer : the store become not speculative and can access at the data cache
-
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue");
-		log_printf(TRACE,Load_store_unit,FUNCTION,"      * PUSH");
-		
-		// Write pointer is define in rename stage :
-		Tlsq_ptr_t           index         = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
-		log_printf(TRACE,Load_store_unit,FUNCTION,"      * index         : %d",index);
-		
-		// Need read : state and exception.
-		Tstore_queue_state_t old_state     = _store_queue [index]._state;
-		Tstore_queue_state_t new_state     = old_state;
-		bool                 update_info   = false;
-
-		Texception_t         old_exception = _store_queue [index]._exception;
-		Texception_t         new_exception = old_exception;
-
-		// Compute next state
-		switch (old_state)
-		  {
-		  case STORE_QUEUE_EMPTY                   :
-		    {
-//                    reg_STORE_QUEUE_INVALID [index] = false; // new first store instruction
-
-		      if (is_operation_memory_store_head(operation) == true)
-			{
-			  new_state = STORE_QUEUE_NO_VALID_NO_SPECULATIVE;
-
-			  // test if is a speculation
-			  if (operation == OPERATION_MEMORY_STORE_HEAD_KO)
-                            {
-                              new_exception = EXCEPTION_MEMORY_MISS_SPECULATION;
-//                            reg_STORE_QUEUE_INVALID [index] = true;
-                            }
-			  else
-			    new_exception = EXCEPTION_MEMORY_NONE;
-			}
-		      else
-			{
-			  new_state = STORE_QUEUE_VALID_SPECULATIVE;
-
-			  // Test if have an exception
-			  if (exception_alignement == true)
-			    new_exception = EXCEPTION_MEMORY_ALIGNMENT;
-			  else
-			    new_exception = EXCEPTION_MEMORY_NONE;
-
-			  update_info = true;
-			}
-		      break;
-		    }
-		  case STORE_QUEUE_NO_VALID_NO_SPECULATIVE :
-		    {
-#ifdef DEBUG_TEST
-		      if (is_operation_memory_store_head(operation) == true)
-			throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_NO_VALID_NO_SPECULATIVE\", also a previous store_head have been receiveid. But this operation is a store_head."));
-#endif
-		      // Test if have a new exception (priority : miss_speculation)
-		      if ((exception_alignement == true) and (old_exception == EXCEPTION_MEMORY_NONE))
-			new_exception = EXCEPTION_MEMORY_ALIGNMENT;
-		      
-		      if (new_exception != EXCEPTION_MEMORY_NONE)
-			new_state = STORE_QUEUE_COMMIT;
-		      else
-			new_state = STORE_QUEUE_VALID_NO_SPECULATIVE;
-		      
-		      update_info = true;
-		      break;
-		    }
-		  case STORE_QUEUE_VALID_SPECULATIVE       :
-		    {
-#ifdef DEBUG_TEST
-		      if (is_operation_memory_store_head(operation) == false)
-			throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_VALID_SPECULATIVE\", also a previous access with register and address have been receiveid. But this operation is a not store_head."));
-#endif
-		      if (operation == OPERATION_MEMORY_STORE_HEAD_KO)
-                        {
-                          new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; // great prioritary
-//                        reg_STORE_QUEUE_INVALID [index] = true;
-                        }
-
-		      if (new_exception != EXCEPTION_MEMORY_NONE)
-			new_state = STORE_QUEUE_COMMIT;
-		      else
-			new_state = STORE_QUEUE_VALID_NO_SPECULATIVE;
-		      
-		      break;
-		    }
-		  case STORE_QUEUE_VALID_NO_SPECULATIVE    :
-		  case STORE_QUEUE_COMMIT                  :
-		    {
-		      throw ERRORMORPHEO(FUNCTION,"<Load_store_unit::function_speculative_load_access_transition> Invalid state and operation");
-		    }
-		  }
-
-		_store_queue [index]._state     = new_state;
-		_store_queue [index]._exception = new_exception;
-		
-		if (update_info == true)
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * Update information");
-
-		    _store_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID   [internal_MEMORY_IN_PORT]);
-		    _store_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
-		    _store_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
-		    _store_queue [index]._packet_id            = (not _param->_have_port_rob_ptr      )?0:PORT_READ(in_MEMORY_IN_PACKET_ID    [internal_MEMORY_IN_PORT]);
-		    _store_queue [index]._operation            = operation;
-		    _store_queue [index]._cancel               = cancel   ;
-		    _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
-		    _store_queue [index]._address              = address;
-		    _store_queue [index]._send_commit          = false;
-
-		    // reordering data
-		    _store_queue [index]._wdata                = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0); 
-//                  _store_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  [internal_MEMORY_IN_PORT]);
-		  }
-	      }
-	    else
-	      {
-		// ====================================
-		// ===== SPECULATIVE_ACCESS_QUEUE =====
-		// ====================================
-
-		// In speculative access queue, they are many type's request
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue");
-		log_printf(TRACE,Load_store_unit,FUNCTION,"      * PUSH");
-		
-		// Write in reservation station
-		uint32_t     index = _speculative_access_queue_control->push();
-
-		log_printf(TRACE,Load_store_unit,FUNCTION,"      * index : %d", index);
-
-		Texception_t exception;
-
-		if (exception_alignement == true)
-		  exception = EXCEPTION_MEMORY_ALIGNMENT;
-		else
-		  exception = EXCEPTION_MEMORY_NONE;
-				
-		// if exception, don't access at the cache
-		// NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits)
-		_speculative_access_queue [index]._state                = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE;
-		_speculative_access_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID   [internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._packet_id            = (not _param->_have_port_rob_ptr      )?0:PORT_READ(in_MEMORY_IN_PACKET_ID    [internal_MEMORY_IN_PORT]);
-
-		_speculative_access_queue [index]._operation            = operation;
-		_speculative_access_queue [index]._cancel               = cancel   ;
-		_speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._store_queue_ptr_read = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_READ [internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._store_queue_empty    = PORT_READ(in_MEMORY_IN_STORE_QUEUE_EMPTY    [internal_MEMORY_IN_PORT]);
-		_speculative_access_queue [index]._address              = address;
-		// NOTE : is operation is a load, then they are a result and must write in the register file
-		_speculative_access_queue [index]._write_rd             = is_operation_memory_load(operation);
-		_speculative_access_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  [internal_MEMORY_IN_PORT]);
-
-		_speculative_access_queue [index]._exception            = exception;
-	      }
-	  }
-
-	//================================================================
-	// Interface "DCACHE_REQ"
-	//================================================================
-        if ((    internal_DCACHE_REQ_VAL  == 1) and
-            (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1))
-          {
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_REQ [0]");
-
-	    switch (internal_DCACHE_REQ_SELECT_QUEUE)
-	      {
-	      case SELECT_STORE_QUEUE :
-		{
-		  // =======================
-		  // ===== STORE_QUEUE =====
-		  // =======================
-		  
-		  // Entry flush and increase the read pointer
-		  
-		  _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_COMMIT;
-
-#if defined(DEBUG) and defined(DEBUG_Load_store_unit) and (DEBUG_Load_store_unit == true)
-		  if (log_file_generate)
-	            {
-	              // log file
-                      Tcontext_t num_thread    = get_num_thread(_store_queue [reg_STORE_QUEUE_PTR_READ]._context_id   , _param->_size_context_id   ,
-                                                                _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id , _param->_size_front_end_id ,
-                                                                _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id, _param->_size_ooo_engine_id);
-
-	              memory_log_file [num_thread] 
-	            	<< "[" << simulation_cycle() << "] "
-	            	<< std::hex
-                        << "@ 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _store_queue [reg_STORE_QUEUE_PTR_READ]._address << " -[ Write ]-> 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata << " "
-	            	<< std::dec
-	            	<< "{" << toString(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation) << "}";
-	              
-	              memory_log_file [num_thread] << std::endl;
-	            }
-#endif	    
-
-
-		  break;
-		}
-	      case SELECT_LOAD_QUEUE_SPECULATIVE :
-		{
-		  // =========================================
-		  // ===== SELECT_LOAD_QUEUE_SPECULATIVE =====
-		  // =========================================
-
-		  load_queue_push = true;
-		  break;
-		}
-	      case SELECT_LOAD_QUEUE :
-		{
-		  throw ERRORMORPHEO(FUNCTION,_("Invalid selection"));
-		  break;
-		}
-
-		break;
-	      }
-	  }
-
-	if (load_queue_push)
-	  {
-            log_printf(TRACE,Load_store_unit,FUNCTION,"  * load_queue_push");
-
-	    Tlsq_ptr_t   ptr_write = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write;
-	    Toperation_t operation = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation;
-	    Texception_t exception = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._exception;
-	    bool         have_exception = (exception != EXCEPTION_MEMORY_NONE);
-            bool         need_check= false;
-            Tlsq_ptr_t   store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;
-            Tlsq_ptr_t   store_queue_ptr_read  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_read ;
-            Tcontrol_t   store_queue_empty     = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_empty    ;
-	    
-	    if (have_exception)
-	      _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT;
-	    else
-	      {
-		if (have_dcache_rsp(operation))
-		  {
-		    // load and synchronisation
-		    if (must_check(operation) and not store_queue_empty)
-		      {
-			// load
-                        need_check = true;
-			
-			_load_queue [ptr_write]._state = LOAD_QUEUE_WAIT_CHECK;
-		      }
-		    else
-		      {
-			// synchronisation
-			_load_queue [ptr_write]._state = LOAD_QUEUE_WAIT;
-		      }
-		  }
-		else
-		  {
-		    // lock, prefecth, flush and invalidate
-		    _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT;
-		  }
-	      }
-
-	    Tdcache_address_t address        = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;
-	    Tdcache_address_t address_lsb    = (address & _param->_mask_address_lsb);
-	    Tdcache_address_t check_hit_byte = gen_mask_not<Tdcache_address_t>(address_lsb+(memory_size(operation)>>3)-1,address_lsb) & _param->_mask_check_hit_byte;
-
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * address                 : 0x%.8x", address);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * address_lsb             : 0x%.8x", address_lsb);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * operation               : %d", operation);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * memory_size             : %d", memory_size(operation));
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * check_hit_byte          : 0x%x", check_hit_byte);
-
-	    _load_queue [ptr_write]._context_id            = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
-	    _load_queue [ptr_write]._front_end_id          = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
-	    _load_queue [ptr_write]._ooo_engine_id         = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
-	    _load_queue [ptr_write]._packet_id             = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._packet_id;
-	    _load_queue [ptr_write]._operation             = operation;
-	    _load_queue [ptr_write]._cancel                = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._cancel;
-	    _load_queue [ptr_write]._store_queue_ptr_write = store_queue_ptr_write;
-	    _load_queue [ptr_write]._store_queue_ptr_read  = store_queue_ptr_read ;
- 	    _load_queue [ptr_write]._store_queue_empty     = store_queue_empty    ;
-	    _load_queue [ptr_write]._address               = address;
-	    _load_queue [ptr_write]._check_hit_byte        = check_hit_byte;
-	    _load_queue [ptr_write]._check_hit             = 0;
-	    _load_queue [ptr_write]._shift                 = address_lsb<<3;// *8
-	    _load_queue [ptr_write]._is_load_signed        = is_operation_memory_load_signed(operation);
-	    _load_queue [ptr_write]._access_size           = memory_size(operation);
-	    // NOTE : if have an exception, must write in register, because a depend instruction wait the load data.
-	    _load_queue [ptr_write]._write_rd              = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._write_rd             ;
-	    _load_queue [ptr_write]._num_reg_rd            = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._num_reg_rd           ;
-	    _load_queue [ptr_write]._exception             = exception;
-	    _load_queue [ptr_write]._rdata                 = address; // to the exception
-
-            switch (_param->_speculative_commit_predictor_scheme)
-              {
-
-              case PREDICTOR_NEVER_TAKE  : {_load_queue [ptr_write]._can_speculative_commit = false; break;}
-              case PREDICTOR_ALWAYS_TAKE : {_load_queue [ptr_write]._can_speculative_commit = true ; break;}
-              case PREDICTOR_COUNTER     : {_load_queue [ptr_write]._can_speculative_commit = false; break;} // TODO
-              default :
-                {
-                  // throw ERRORMORPHEO(FUNCTION,_("Invalid predictor scheme.\n"));
-                  _load_queue [ptr_write]._can_speculative_commit = false;
-                  break;
-                }
-              }
-	    
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue");
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * POP[%d]",(*_speculative_access_queue_control)[0]);
-	    
-	    _speculative_access_queue [(*_speculative_access_queue_control)[0]]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY;
-	    
-	    _speculative_access_queue_control->pop();
-
-#ifdef STATISTICS
-            if (usage_is_set(_usage,USE_STATISTICS))
-              (*_stat_nb_inst_load) ++;
-#endif
-
-            // Only load need check
-            if (need_check//  and not store_queue_empty
-		)
-//             if (is_operation_memory_load(_load_queue [ptr_write]._operation))
-              {
-                log_printf(TRACE,Load_store_unit,FUNCTION,"    * update nb_check");
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_ptr_write : %d",store_queue_ptr_write);
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_ptr_read  : %d",store_queue_ptr_read );
-		log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_empty     : %d",store_queue_empty    );
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      * reg_STORE_QUEUE_PTR_READ  : %d",reg_STORE_QUEUE_PTR_READ);
-                
-                uint32_t i=store_queue_ptr_write;
-                while (i!=store_queue_ptr_read)
-                  {
-                    i=((i==0)?_param->_size_store_queue:i)-1;
-                    
-                    log_printf(TRACE,Load_store_unit,FUNCTION,"      * i                         : %d",i);
-                    
-                    reg_STORE_QUEUE_NB_CHECK [i] ++;
-
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 3 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
-                  }
-              }
-          }
-
-	//================================================================
-	// Interface "DCACHE_RSP"
-	//================================================================
-        if ((PORT_READ(in_DCACHE_RSP_VAL[0])== 1) and
-            (    internal_DCACHE_RSP_ACK == 1))
-          {
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_RSP [0]");
-
-	    // don't use context_id : because there are one queue for all thread
-	    //Tcontext_t      context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID[0]); 
-	    Tpacket_t       packet_id  = PORT_READ(in_DCACHE_RSP_PACKET_ID [0]);
-	    Tdcache_data_t  rdata      = PORT_READ(in_DCACHE_RSP_RDATA     [0]);
-	    Tdcache_error_t error      = PORT_READ(in_DCACHE_RSP_ERROR     [0]);
-
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * original packet_id : %d"  , packet_id);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * packet_id          : %d"  , packet_id>>1);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * rdata              : %.8x", rdata);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * error              : %d"  , error);
-	    
-	    if (DCACHE_RSP_IS_LOAD(packet_id) == 1)
-	      {
-		packet_id >>= 1;
-
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * packet is a LOAD");
- 
-#ifdef DEBUG_TEST
-		if (not have_dcache_rsp(_load_queue [packet_id]._operation))
-		  throw ERRORMORPHEO(FUNCTION,_("Receive of respons, but the corresponding operation don't wait a respons."));
-#endif
-
-                Tdcache_data_t data = _load_queue [packet_id]._rdata;
-
-                log_printf(TRACE,Load_store_unit,FUNCTION,"    * data construction");
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      * data from cache     : 0x%.8x",rdata);
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      * data (before)       : 0x%.8x", data);
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      * check_hit_byte      : 0x%x"  ,_load_queue [packet_id]._check_hit_byte);
-                for (uint32_t i=0;i<(_param->_size_general_data>>3)/*8*/; ++i)
-                  // Test if this byte has been checked
-                  if ((_load_queue [packet_id]._check_hit_byte & (1<<i)) == 0)
-                    {
-                      log_printf(TRACE,Load_store_unit,FUNCTION,"      * no previous check ]%d:%d]",(i+1)<<3,i<<3);
-                      data = insert<Tdcache_data_t>(data,rdata,((i+1)<<3)-1,i<<3);
-                    }
-                log_printf(TRACE,Load_store_unit,FUNCTION,"      * data (after)        : 0x%.8x", data);
-                
-                _load_queue [packet_id]._rdata = data;
-		
-#if defined(DEBUG) and defined(DEBUG_Load_store_unit) and (DEBUG_Load_store_unit == true)
-		if (log_file_generate)
-		  {
-		    // log file
-		    Tcontext_t num_thread    = get_num_thread(_load_queue [packet_id]._context_id   , _param->_size_context_id   ,
-							      _load_queue [packet_id]._front_end_id , _param->_size_front_end_id ,
-							      _load_queue [packet_id]._ooo_engine_id, _param->_size_ooo_engine_id);
-		    
-		    memory_log_file [num_thread] 
-		      << "[" << simulation_cycle() << "] "
-		      << std::hex
-		      << "@ 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _load_queue [packet_id]._address << " -[ Read  ]-> 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _load_queue [packet_id]._rdata << " "
-		      << std::dec
-		      << "{" << toString(_load_queue [packet_id]._operation) << "}";
-		    
-		    memory_log_file [num_thread] << std::endl;
-		  }
-#endif	    
-
-		if (error != DCACHE_ERROR_NONE)
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"    * have a bus error !!!");
-
-		    _load_queue [packet_id]._exception = EXCEPTION_MEMORY_BUS_ERROR;
-		    _load_queue [packet_id]._state     = LOAD_QUEUE_COMMIT;
-
-                    
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write : %d", _load_queue[packet_id]._store_queue_ptr_write);
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_read  : %d", _load_queue[packet_id]._store_queue_ptr_read );
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_empty     : %d", _load_queue[packet_id]._store_queue_empty    );
-
- 		    if (not _load_queue[packet_id]._store_queue_empty)
-		      {
-			uint32_t i=_load_queue[packet_id]._store_queue_ptr_write;
-			
-			while (i!=_load_queue[packet_id]._store_queue_ptr_read)
-			  {
-			    i=((i==0)?_param->_size_store_queue:i)-1;
-			    
-#ifdef DEBUG
-			    if (reg_STORE_QUEUE_NB_CHECK [i] == 0)
-			      throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
-#endif
-			    
-			    reg_STORE_QUEUE_NB_CHECK [i] --;
-
-			    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 4 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
-
-			    //i=(i+1)%_param->_size_store_queue;
-			  }
-			_load_queue[packet_id]._store_queue_empty = true; // end of check
-
-		      }
-		  }
-		else
-		  {
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"    * have no bus error.");
-		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * previous state : %s",toString(_load_queue [packet_id]._state).c_str());
-
-		    // FIXME : convention : if bus error, the cache return the fautive address !
-		    // But, the load's address is aligned !
-
-		    switch (_load_queue [packet_id]._state)
-		      {
-		      case LOAD_QUEUE_WAIT_CHECK : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT_CHECK; break;
-		      case LOAD_QUEUE_WAIT       : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT      ; break;
-		      default : throw ERRORMORPHEO(FUNCTION,_("Illegal state (dcache_rsp).")); break;
-		      }
-		  }
-	      }
-	    else
-	      {
-		log_printf(TRACE,Load_store_unit,FUNCTION,"    * packet is a STORE");
-		
-		// TODO : les stores ne génére pas de réponse sauf quand c'est un bus error !!!
-		throw ERRORMORPHEO(FUNCTION,_("dcache_rsp : no respons to a write. (TODO : manage bus error to the store operation.)"));
-	      }
-	    
-	  }
-	
-	// this register is to manage the priority of check -> Round robin
-	reg_LOAD_QUEUE_CHECK_PRIORITY = (reg_LOAD_QUEUE_CHECK_PRIORITY+1)%_param->_size_load_queue;
-	
-	
-#if defined(DEBUG) and (DEBUG>=DEBUG_TRACE)
-	// ***** dump store queue
-        log_printf(TRACE,Load_store_unit,FUNCTION,"  * Dump STORE_QUEUE");
-        log_printf(TRACE,Load_store_unit,FUNCTION,"    * ptr_read : %d",reg_STORE_QUEUE_PTR_READ);
-	
-	for (uint32_t i=0; i<_param->_size_store_queue; i++)
-	  {
-	    uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
-
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d %.1d, %.4d, %.8x %.8x, %.2d %.1d, %.2d %s",
-                       j,
-                       _store_queue[j]._context_id          ,
-                       _store_queue[j]._front_end_id        ,
-                       _store_queue[j]._ooo_engine_id       ,
-                       _store_queue[j]._packet_id           ,
-                       _store_queue[j]._operation           ,
-                       _store_queue[j]._cancel              ,
-                       _store_queue[j]._load_queue_ptr_write,
-                       _store_queue[j]._address             ,
-                       _store_queue[j]._wdata               ,
-                     //_store_queue[j]._write_rd            ,
-                     //_store_queue[j]._num_reg_rd          ,
-                       _store_queue[j]._exception           ,
-                       _store_queue[j]._send_commit         ,
-                       reg_STORE_QUEUE_NB_CHECK  [j]        ,
-                       toString(_store_queue[j]._state).c_str());
-	  }
-
-	// ***** dump speculative_access queue
-	log_printf(TRACE,Load_store_unit,FUNCTION,"  * Dump SPECULATIVE_ACCESS_QUEUE");
-	
-	for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
-	  {
-	    uint32_t j = (*_speculative_access_queue_control)[i];
-
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d %.1d, %.4d %.4d %.4d %.1d, %.8x, %.1d %.4d, %.2d, %s",
-                       j,
-                       _speculative_access_queue[j]._context_id          ,
-                       _speculative_access_queue[j]._front_end_id        ,
-                       _speculative_access_queue[j]._ooo_engine_id       ,
-                       _speculative_access_queue[j]._packet_id           ,
-                       _speculative_access_queue[j]._operation           ,
-                       _speculative_access_queue[j]._cancel              ,
-                       _speculative_access_queue[j]._load_queue_ptr_write,
-                       _speculative_access_queue[j]._store_queue_ptr_write,
-                       _speculative_access_queue[j]._store_queue_ptr_read ,
-                       _speculative_access_queue[j]._store_queue_empty    ,
-                       _speculative_access_queue[j]._address             ,
-                       _speculative_access_queue[j]._write_rd            ,
-                       _speculative_access_queue[j]._num_reg_rd          ,
-                       _speculative_access_queue[j]._exception           ,
-                       toString(_speculative_access_queue[j]._state).c_str());
-	  }
-
-	// ***** dump load queue
-	log_printf(TRACE,Load_store_unit,FUNCTION,"  * Dump LOAD_QUEUE");
-        log_printf(TRACE,Load_store_unit,FUNCTION,"    * ptr_read_check_priority : %d",reg_LOAD_QUEUE_CHECK_PRIORITY);
-	
-	for (uint32_t i=0; i<_param->_size_load_queue; i++)
-	  {
-	    uint32_t j = i;
-
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d %.1d, %.4d %.4d %.1d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s",
-                       j,
-                       _load_queue[j]._context_id          ,
-                       _load_queue[j]._front_end_id        ,
-                       _load_queue[j]._ooo_engine_id       ,
-                       _load_queue[j]._packet_id           ,
-                       _load_queue[j]._operation           ,
-                       _load_queue[j]._cancel              ,
-                       _load_queue[j]._store_queue_ptr_write,
-                       _load_queue[j]._store_queue_ptr_read ,
-		       _load_queue[j]._store_queue_empty    ,
-                       _load_queue[j]._address             ,
-                       _load_queue[j]._check_hit_byte      , 
-                       _load_queue[j]._check_hit           ,
-                       _load_queue[j]._shift               ,
-                       _load_queue[j]._is_load_signed      ,
-                       _load_queue[j]._access_size         ,
-                       _load_queue[j]._rdata               ,
-                       _load_queue[j]._write_rd            ,
-                       _load_queue[j]._num_reg_rd          ,
-                       _load_queue[j]._exception           ,
-                       toString(_load_queue[j]._state).c_str());
-	  }
-#endif
-	
-#ifdef STATISTICS
-        if (usage_is_set(_usage,USE_STATISTICS))
-          {
-            for (uint32_t i=0; i<_param->_size_store_queue; i++)
-              if (_store_queue[i]._state != STORE_QUEUE_EMPTY)
-                (*_stat_use_store_queue) ++;
-            for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
-              if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY)
-                (*_stat_use_speculative_access_queue) ++;
-            for (uint32_t i=0; i<_param->_size_load_queue; i++)
-              if (_load_queue[i]._state != LOAD_QUEUE_EMPTY)
-                (*_stat_use_load_queue) ++;
-          }
-#endif
-      }
-
-    log_end(Load_store_unit,FUNCTION);
-  };
-
-}; // end namespace load_store_unit
-}; // end namespace execute_unit
-}; // end namespace multi_execute_unit
-}; // end namespace execute_loop
-}; // end namespace multi_execute_loop
-}; // end namespace core
-
-}; // end namespace behavioural
-}; // end namespace morpheo              
-#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp	(revision 145)
@@ -0,0 +1,40 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMealy_dcache"
+  void Load_store_unit::function_speculative_load_commit_genMealy_dcache (void)
+  {
+    log_begin(Load_store_unit,FUNCTION);
+    log_end  (Load_store_unit,FUNCTION);
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp	(revision 145)
@@ -0,0 +1,76 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMealy_insert"
+  void Load_store_unit::function_speculative_load_commit_genMealy_insert (void)
+  {
+    log_begin(Load_store_unit,FUNCTION);
+    log_function(Load_store_unit,FUNCTION,_name.c_str());
+
+    // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    
+    // Initialisation
+    internal_MEMORY_IN_PORT = 0;
+    Tcontrol_t ack [_param->_nb_inst_memory];
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      ack [i] = 0;
+
+    if (PORT_READ(in_NRESET))
+      {
+    // find first valid entry
+    // store queue is never full (pointer is manage by rename stage)
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      if (PORT_READ(in_MEMORY_IN_VAL [i]))
+	{
+	  internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION [i])) or not _speculative_access_queue_control->full();
+
+	  if (internal_MEMORY_IN_ACK)
+	    {
+	      ack [i] = 1;
+	      internal_MEMORY_IN_PORT = i;
+	      break; // end
+	    }
+	}
+      }
+    else
+      {
+        internal_MEMORY_IN_ACK = 0;
+//         internal_MEMORY_IN_PORT = i;
+      }
+
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      PORT_WRITE(out_MEMORY_IN_ACK [i], ack [i]);
+
+    log_end(Load_store_unit,FUNCTION);
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp	(revision 145)
@@ -0,0 +1,40 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMealy_retire"
+  void Load_store_unit::function_speculative_load_commit_genMealy_retire (void)
+  {
+    log_begin(Load_store_unit,FUNCTION);
+    log_end  (Load_store_unit,FUNCTION);
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 145)
@@ -0,0 +1,289 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMoore"
+  void Load_store_unit::function_speculative_load_commit_genMoore (void)
+  {
+    log_begin(Load_store_unit,FUNCTION);
+    log_function(Load_store_unit,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET))
+      {
+    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+    Tcontext_t         memory_out_context_id    = 0;
+    Tcontext_t         memory_out_front_end_id  = 0;
+    Tcontext_t         memory_out_ooo_engine_id = 0;
+    Tpacket_t          memory_out_packet_id     = 0;
+    Tcontrol_t         memory_out_cancel        = 0;
+    Tcontrol_t         memory_out_write_rd      = 0;
+    Tgeneral_address_t memory_out_num_reg_rd    = 0;
+    Tgeneral_data_t    memory_out_data_rd       = 0;
+//  Tcontrol_t         memory_out_write_re      = 0;
+//  Tspecial_address_t memory_out_num_reg_re    = 0;
+//  Tspecial_data_t    memory_out_data_re       = 0;
+    Tcontrol_t         memory_out_no_sequence   = 0;
+    Texception_t       memory_out_exception     = 0;
+
+    internal_MEMORY_OUT_VAL = 0;
+
+    // Test store and load queue
+
+    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test MEMORY_OUT");
+
+    log_printf(TRACE,Load_store_unit,FUNCTION,"    * Load  queue");
+    for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++)
+//     for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++)
+      {
+// 	internal_MEMORY_OUT_PTR = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
+
+        // have valid entry if :
+        //  * load_queue entry need commit
+        //  * load_queue entry have rsp and can make a speculative commit
+	internal_MEMORY_OUT_VAL = ((_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT) or
+                                   (_load_queue[internal_MEMORY_OUT_PTR]._can_speculative_commit and (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK))
+				   );
+	
+	if (internal_MEMORY_OUT_VAL)
+	  {
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
+	    internal_MEMORY_OUT_SELECT_QUEUE = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?SELECT_LOAD_QUEUE_SPECULATIVE:SELECT_LOAD_QUEUE;
+	    
+	    memory_out_context_id    = _load_queue [internal_MEMORY_OUT_PTR]._context_id;
+	    memory_out_front_end_id  = _load_queue [internal_MEMORY_OUT_PTR]._front_end_id;
+	    memory_out_ooo_engine_id = _load_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
+	    memory_out_packet_id     = _load_queue [internal_MEMORY_OUT_PTR]._packet_id ;
+	    memory_out_cancel        = _load_queue [internal_MEMORY_OUT_PTR]._cancel    ;
+	    memory_out_write_rd      = _load_queue [internal_MEMORY_OUT_PTR]._write_rd  ;
+	    memory_out_num_reg_rd    = _load_queue [internal_MEMORY_OUT_PTR]._num_reg_rd;
+
+	    Tdcache_data_t data_old = _load_queue [internal_MEMORY_OUT_PTR]._rdata;
+	    Tdcache_data_t data_new = extend<Tdcache_data_t>(_param->_size_general_data,
+							     data_old >> _load_queue [internal_MEMORY_OUT_PTR]._shift,
+							     _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed,
+							     _load_queue [internal_MEMORY_OUT_PTR]._access_size);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (old) : %.8x",data_old);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (new) : %.8x",data_new);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * address      : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._address);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * rdata        : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * shift        : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * signed?      : %d",_load_queue [internal_MEMORY_OUT_PTR]._is_load_signed);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * access_size  : %d",_load_queue [internal_MEMORY_OUT_PTR]._access_size);
+
+	    Texception_t exception      = _load_queue [internal_MEMORY_OUT_PTR]._exception;
+	    bool         have_exception = ((exception != EXCEPTION_MEMORY_NONE) and
+					   (exception != EXCEPTION_MEMORY_MISS_SPECULATION));
+
+	    // if exception, rdata content the address of load, else content read data.
+	    memory_out_data_rd       = (have_exception)?data_old:data_new;
+	    memory_out_exception     = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?EXCEPTION_MEMORY_LOAD_SPECULATIVE:exception;
+
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",exception);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",memory_out_exception);
+
+	    break; // we have find a entry !!! stop the search
+	  }
+      }
+
+    if (not internal_MEMORY_OUT_VAL)
+      {
+	log_printf(TRACE,Load_store_unit,FUNCTION,"    * Store queue");
+
+	for (uint32_t i=0; i<_param->_size_store_queue; ++i)
+	  {
+	    internal_MEMORY_OUT_PTR = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
+	    // Can retire an store instruction if :
+	    //  * state is commit
+	    //  * none load must check this store
+
+
+	    bool val_head = ((i==0) and
+			     (_store_queue [internal_MEMORY_OUT_PTR]._state       == STORE_QUEUE_COMMIT) and
+			     (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == true) and
+			     (reg_STORE_QUEUE_NB_CHECK [internal_MEMORY_OUT_PTR] == 0)
+			     );
+
+	    bool val_commit = ((_store_queue [internal_MEMORY_OUT_PTR]._state       != STORE_QUEUE_EMPTY) and
+			       (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == false));
+
+	    if (val_head or val_commit)
+	      {
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
+		
+		internal_MEMORY_OUT_VAL          = 1;
+		internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
+		
+		memory_out_context_id    = _store_queue [internal_MEMORY_OUT_PTR]._context_id;
+		memory_out_front_end_id  = _store_queue [internal_MEMORY_OUT_PTR]._front_end_id;
+		memory_out_ooo_engine_id = _store_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
+		memory_out_packet_id     = _store_queue [internal_MEMORY_OUT_PTR]._packet_id ;
+		memory_out_cancel        = _store_queue [internal_MEMORY_OUT_PTR]._cancel;
+//              memory_out_write_rd  	 
+//              memory_out_num_reg_rd	 
+		memory_out_data_rd       = _store_queue [internal_MEMORY_OUT_PTR]._address; // to the exception
+		memory_out_exception     = _store_queue [internal_MEMORY_OUT_PTR]._exception;
+		memory_out_no_sequence   = val_commit;
+		break; // find an entry
+	      }
+
+	  }
+      }
+
+    // write output
+    if (_param->_have_port_context_id)
+    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   [0], memory_out_context_id   );
+    if (_param->_have_port_front_end_id)
+    PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id );
+    if (_param->_have_port_ooo_engine_id)
+    PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id);
+    if (_param->_have_port_rob_ptr)
+    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    [0], memory_out_packet_id    );
+//  PORT_WRITE(out_MEMORY_OUT_OPERATION    [0], memory_out_operation    );
+//  PORT_WRITE(out_MEMORY_OUT_TYPE         [0], TYPE_MEMORY             );
+    PORT_WRITE(out_MEMORY_OUT_CANCEL       [0], memory_out_cancel       );
+    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     [0], memory_out_write_rd     );
+    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   [0], memory_out_num_reg_rd   );
+    PORT_WRITE(out_MEMORY_OUT_DATA_RD      [0], memory_out_data_rd      );
+//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], memory_out_write_re     );
+//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], memory_out_num_reg_re   );
+//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], memory_out_data_re      );
+    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    [0], memory_out_exception    );
+    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  [0], memory_out_no_sequence  );// hack
+#ifdef DEBUG
+    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], memory_out_data_rd);
+#else
+    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], 0);
+#endif
+
+    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+    Tcontext_t        dcache_req_context_id = 0;
+    Tpacket_t         dcache_req_packet_id  = 0;
+    Tdcache_address_t dcache_req_address    = 0;
+    Tdcache_type_t    dcache_req_type       = 0;
+    Tdcache_data_t    dcache_req_wdata      = 0;
+
+    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test DCACHE_REQ");
+
+    internal_DCACHE_REQ_VAL = 0;
+
+    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = (*_speculative_access_queue_control)[0];
+
+    // Test store and load queue
+    if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE)
+      {
+	log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);
+
+	internal_DCACHE_REQ_VAL          = 1;
+	internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
+
+	if (_param->_have_port_dcache_context_id)
+	  {
+	    Tcontext_t context_id    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
+	    Tcontext_t front_end_id  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
+	    Tcontext_t ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
+	    
+	    dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
+				     (front_end_id <<(_param->_size_context_id)) |
+				     (context_id));
+	  }
+
+	dcache_req_packet_id  = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write);
+	dcache_req_address    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb;
+	dcache_req_type       = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation);
+
+// 	log_printf(TRACE,Load_store_unit,FUNCTION,"      * address            : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address);
+//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * mask               : %.8x",_param->_mask_address_msb);
+        log_printf(TRACE,Load_store_unit,FUNCTION,"      * dcache_req_address : %.8x",dcache_req_address);
+
+#ifdef SYSTEMC_VHDL_COMPATIBILITY
+	dcache_req_wdata      = 0;
+#endif
+      }
+    else
+      {
+	// Test an store must be commited.
+	if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE)
+	  {
+	    internal_DCACHE_REQ_VAL          = 1;
+	    internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE;
+	    
+	    if (_param->_have_port_dcache_context_id)
+	      {
+		Tcontext_t context_id    = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id;
+		Tcontext_t front_end_id  = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id;
+		Tcontext_t ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id;
+		
+		dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
+					 (front_end_id <<(_param->_size_context_id)) |
+					 (context_id));
+	      }
+
+	    // FIXME : il peut avoir plusieurs store avec le même paquet_id ... pour l'instant pas très grave car pas de retour (enfin seul les bus error sont des retours)
+	    dcache_req_packet_id  = DCACHE_REQ_IS_STORE(reg_STORE_QUEUE_PTR_READ);
+	    dcache_req_address    = _store_queue [reg_STORE_QUEUE_PTR_READ]._address;
+	    dcache_req_type       = operation_to_dcache_type(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation);
+	    dcache_req_wdata      = _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata;
+	  }
+      }
+
+    if (_param->_have_port_dcache_context_id)
+    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id);
+    PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id );
+    PORT_WRITE(out_DCACHE_REQ_ADDRESS   [0], dcache_req_address   );
+    PORT_WRITE(out_DCACHE_REQ_TYPE      [0], dcache_req_type      );
+    PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
+      }
+    else
+      {
+        // Reset
+    internal_MEMORY_OUT_VAL = 0;
+//  internal_MEMORY_OUT_PTR =0
+//  internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
+
+    internal_DCACHE_REQ_VAL = 0;
+    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = 0;
+//  internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
+      }
+
+    // Write output
+    PORT_WRITE(out_MEMORY_OUT_VAL [0], internal_MEMORY_OUT_VAL);
+    PORT_WRITE(out_DCACHE_REQ_VAL [0], internal_DCACHE_REQ_VAL);
+
+
+    log_end(Load_store_unit,FUNCTION);
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 145)
@@ -0,0 +1,1426 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+#include "Behavioural/include/Identification.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+template <typename T>
+T swapBytes (T data, uint32_t size_data, uint32_t size_access)
+{
+  uint64_t x = static_cast<uint64_t>(data);
+
+//   switch (size_data)
+//     {
+//     case 2 : // 16 bits
+//       {
+//         switch (size_access)
+//           {
+//           case 2 : 
+//             {
+//               x = ((((x>> 8)&0xff) <<  0) |
+//                    (((x>> 0)&0xff) <<  8) );
+//               break;
+//             }
+//           default :
+//             {
+//               break;
+//             }
+//           }
+//         break;
+//       }
+//     case 4 : // 32 bits
+//       {
+//         switch (size_access)
+//           {
+//           case 2 : 
+//             {
+//               x = ((((x>> 8)&0xff) <<  0) |
+//                    (((x>> 0)&0xff) <<  8) |
+//                    (((x>>24)&0xff) << 16) |
+//                    (((x>>16)&0xff) << 24) );
+//               break;
+//             }
+//           case 4 : 
+//             {
+//               x = ((((x>>24)&0xff) <<  0) |
+//                    (((x>>16)&0xff) <<  8) |
+//                    (((x>> 8)&0xff) << 16) |
+//                    (((x>> 0)&0xff) << 24) );
+//               break;
+//             }
+//           default :
+//             {
+//               break;
+//             }
+//           }
+//         break;
+//       }
+//     case 8 : // 64 bits
+//       {
+//         switch (size_access)
+//           {
+//           case 2 : 
+//             {
+//               x = ((((x>> 8)&0xff) <<  0) |
+//                    (((x>> 0)&0xff) <<  8) |
+//                    (((x>>24)&0xff) << 16) |
+//                    (((x>>16)&0xff) << 24) |
+//                    (((x>>40)&0xff) << 32) |
+//                    (((x>>32)&0xff) << 40) |
+//                    (((x>>56)&0xff) << 48) |
+//                    (((x>>48)&0xff) << 56) );
+//               break;
+//             }
+//           case 4 : 
+//             {
+//               x = ((((x>>24)&0xff) <<  0) |
+//                    (((x>>16)&0xff) <<  8) |
+//                    (((x>> 8)&0xff) << 16) |
+//                    (((x>> 0)&0xff) << 24) |
+//                    (((x>>56)&0xff) << 32) |
+//                    (((x>>48)&0xff) << 40) |
+//                    (((x>>40)&0xff) << 48) |
+//                    (((x>>32)&0xff) << 56) );
+//               break;
+//             }
+//           case 8 : 
+//             {
+//               x = ((((x>>56)&0xff) <<  0) |
+//                    (((x>>48)&0xff) <<  8) |
+//                    (((x>>40)&0xff) << 16) |
+//                    (((x>>32)&0xff) << 24) |
+//                    (((x>>24)&0xff) << 32) |
+//                    (((x>>16)&0xff) << 40) |
+//                    (((x>> 8)&0xff) << 48) |
+//                    (((x>> 0)&0xff) << 56) );
+//               break;
+//             }
+//           default :
+//             {
+//               break;
+//             }
+//           }
+//         break;
+//       }
+//     default :
+//       {
+//         break;
+//       }
+//     }
+
+
+  uint64_t y=0;
+
+  for (uint32_t i=0; i<size_data; i+=size_access)
+    {
+      uint32_t offset = i<<3;
+
+      switch (size_access)
+        {
+        case 1 :
+          {
+            y = x;
+            break;
+          }
+        case 2 : 
+          {
+            y |= ((((x>>( 8+offset))&0xff) << ( 0+offset)) |
+                  (((x>>( 0+offset))&0xff) << ( 8+offset)) );
+            break;
+          }
+        case 4 : 
+          {
+            y |= ((((x>>(24+offset))&0xff) << ( 0+offset)) |
+                  (((x>>(16+offset))&0xff) << ( 8+offset)) |
+                  (((x>>( 8+offset))&0xff) << (16+offset)) |
+                  (((x>>( 0+offset))&0xff) << (24+offset)) );
+            break;
+          }
+        case 8 : 
+          {
+            y |= ((((x>>(56+offset))&0xff) << ( 0+offset)) |
+                  (((x>>(48+offset))&0xff) << ( 8+offset)) |
+                  (((x>>(40+offset))&0xff) << (16+offset)) |
+                  (((x>>(32+offset))&0xff) << (24+offset)) |
+                  (((x>>(24+offset))&0xff) << (32+offset)) |
+                  (((x>>(16+offset))&0xff) << (40+offset)) |
+                  (((x>>( 8+offset))&0xff) << (48+offset)) |
+                  (((x>>( 0+offset))&0xff) << (56+offset)) );
+            break;
+          }
+        default :
+            {
+              break;
+            }
+        }
+    }
+
+  return static_cast<T>(y);
+}
+
+template <typename T>
+T swapBits (T data, uint32_t size_data, uint32_t size_access)
+{
+  uint8_t x = static_cast<uint8_t>(data);
+
+  uint8_t y=0;
+
+  for (uint32_t i=0; i<size_data; i+=size_access)
+    {
+      uint32_t offset = i;
+
+      switch (size_access)
+        {
+        case 1 :
+          {
+            y = x;
+            break;
+          }
+        case 2 : 
+          {
+            y |= ((((x>>( 1+offset))&0x1) << ( 0+offset)) |
+                  (((x>>( 0+offset))&0x1) << ( 1+offset)) );
+            break;
+          }
+        case 4 : 
+          {
+            y |= ((((x>>( 3+offset))&0x1) << ( 0+offset)) |
+                  (((x>>( 2+offset))&0x1) << ( 1+offset)) |
+                  (((x>>( 1+offset))&0x1) << ( 2+offset)) |
+                  (((x>>( 0+offset))&0x1) << ( 3+offset)) );
+            break;
+          }
+        case 8 : 
+          {
+            y |= ((((x>>( 7+offset))&0x1) << ( 0+offset)) |
+                  (((x>>( 6+offset))&0x1) << ( 1+offset)) |
+                  (((x>>( 5+offset))&0x1) << ( 2+offset)) |
+                  (((x>>( 4+offset))&0x1) << ( 3+offset)) |
+                  (((x>>( 3+offset))&0x1) << ( 4+offset)) |
+                  (((x>>( 2+offset))&0x1) << ( 5+offset)) |
+                  (((x>>( 1+offset))&0x1) << ( 6+offset)) |
+                  (((x>>( 0+offset))&0x1) << ( 7+offset)) );
+            break;
+          }
+        default :
+            {
+              break;
+            }
+        }
+    }
+
+  return static_cast<T>(y);
+}
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_commit_transition"
+  void Load_store_unit::function_speculative_load_commit_transition (void)
+  {
+    log_begin(Load_store_unit,FUNCTION);
+    log_function(Load_store_unit,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET) == 0)
+      {
+	// Reset : clear all queue
+	_speculative_access_queue_control->clear();
+
+	reg_STORE_QUEUE_PTR_READ       = 0;
+	reg_LOAD_QUEUE_CHECK_PRIORITY  = 0;
+
+	for (uint32_t i=0; i< _param->_size_store_queue             ; i++)
+          {
+            reg_STORE_QUEUE_NB_CHECK  [i] = 0;
+//          reg_STORE_QUEUE_INVALID   [i] = 0;
+  	    _store_queue              [i]._state                 = STORE_QUEUE_EMPTY;
+  	    _store_queue              [i]._context_id            = 0; // not necessary
+  	    _store_queue              [i]._front_end_id          = 0; // not necessary
+  	    _store_queue              [i]._ooo_engine_id         = 0; // not necessary
+  	    _store_queue              [i]._packet_id             = 0; // not necessary
+  	    _store_queue              [i]._operation             = 0; // not necessary
+  	    _store_queue              [i]._cancel                = 0; // not necessary
+  	    _store_queue              [i]._load_queue_ptr_write  = 0; // not necessary
+  	    _store_queue              [i]._address               = 0; // not necessary
+  	    _store_queue              [i]._wdata                 = 0; // not necessary
+//	    _store_queue              [i]._write_rd              = 0; // not necessary
+//	    _store_queue              [i]._num_reg_rd            = 0; // not necessary
+  	    _store_queue              [i]._exception             = 0; // not necessary
+  	    _store_queue              [i]._send_commit           = 0; // not necessary
+          }
+
+	for (uint32_t i=0; i< _param->_size_load_queue              ; i++)
+          {
+            _load_queue               [i]._state                 = LOAD_QUEUE_EMPTY;
+            _load_queue               [i]._context_id            = 0; // not necessary
+            _load_queue               [i]._front_end_id          = 0; // not necessary
+            _load_queue               [i]._ooo_engine_id         = 0; // not necessary
+            _load_queue               [i]._packet_id             = 0; // not necessary
+            _load_queue               [i]._operation             = 0; // not necessary
+            _load_queue               [i]._cancel                = 0; // not necessary
+            _load_queue               [i]._store_queue_ptr_write = 0; // not necessary
+            _load_queue               [i]._store_queue_ptr_read  = 0; // not necessary
+            _load_queue               [i]._store_queue_empty     = 0; // not necessary
+            _load_queue               [i]._address               = 0; // not necessary
+            _load_queue               [i]._check_hit_byte        = 0; // not necessary 
+            _load_queue               [i]._check_hit             = 0; // not necessary
+            _load_queue               [i]._shift                 = 0; // not necessary
+            _load_queue               [i]._is_load_signed        = 0; // not necessary
+            _load_queue               [i]._access_size           = 0; // not necessary
+            _load_queue               [i]._rdata                 = 0; // not necessary
+            _load_queue               [i]._write_rd              = 0; // not necessary
+            _load_queue               [i]._num_reg_rd            = 0; // not necessary
+            _load_queue               [i]._exception             = 0; // not necessary
+            _load_queue               [i]._can_speculative_commit= 0; // not necessary
+          }
+
+	for (uint32_t i=0; i< _param->_size_speculative_access_queue; i++)
+          {
+            _speculative_access_queue [i]._state                 = SPECULATIVE_ACCESS_QUEUE_EMPTY;
+            _speculative_access_queue [i]._context_id            = 0; // not necessary
+            _speculative_access_queue [i]._front_end_id          = 0; // not necessary
+            _speculative_access_queue [i]._ooo_engine_id         = 0; // not necessary
+            _speculative_access_queue [i]._packet_id             = 0; // not necessary
+            _speculative_access_queue [i]._operation             = 0; // not necessary
+            _speculative_access_queue [i]._cancel                = 0; // not necessary
+            _speculative_access_queue [i]._load_queue_ptr_write  = 0; // not necessary
+            _speculative_access_queue [i]._store_queue_ptr_write = 0; // not necessary
+            _speculative_access_queue [i]._store_queue_ptr_read  = 0; // not necessary
+            _speculative_access_queue [i]._store_queue_empty     = 0; // not necessary
+            _speculative_access_queue [i]._address               = 0; // not necessary
+            _speculative_access_queue [i]._write_rd              = 0; // not necessary
+            _speculative_access_queue [i]._num_reg_rd            = 0; // not necessary
+            _speculative_access_queue [i]._exception             = 0; // not necessary
+          }
+      }
+    else
+      {
+        // load_queue_push if speculative_access_queue have access at the dcache, or they have an event
+	bool load_queue_push = (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE);
+
+	//================================================================
+	// Interface "MEMORY_OUT"
+	//================================================================
+
+        if ((    internal_MEMORY_OUT_VAL  == 1) and
+            (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1))
+          {
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_OUT[0] transaction");
+
+	    switch (internal_MEMORY_OUT_SELECT_QUEUE)
+	      {
+	      case SELECT_STORE_QUEUE :
+		{
+		  // =======================
+		  // ===== STORE_QUEUE =====
+		  // =======================
+		  
+		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue [%d]",internal_MEMORY_OUT_PTR);
+	    
+		  // Entry flush and increase the read pointer
+		  if (_store_queue [internal_MEMORY_OUT_PTR]._send_commit)
+		    {
+		      _store_queue [internal_MEMORY_OUT_PTR]._state = STORE_QUEUE_EMPTY;
+		      reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue;
+		    }
+		  else
+		    _store_queue [internal_MEMORY_OUT_PTR]._send_commit = true;
+
+		  break;
+		}
+	      case SELECT_LOAD_QUEUE :
+		{
+		  // ======================
+		  // ===== LOAD_QUEUE =====
+		  // ======================
+		  
+		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * load_queue  [%d]",internal_MEMORY_OUT_PTR);
+		  
+		  // Entry flush and increase the read pointer
+		  
+		  _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY;
+		  
+		  // reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
+
+		  break;
+		}
+	      case SELECT_LOAD_QUEUE_SPECULATIVE :
+		{
+		  log_printf(TRACE,Load_store_unit,FUNCTION,"    * load_queue  [%d] (speculative)",internal_MEMORY_OUT_PTR);
+		  
+                  // !!! WARNING !!!
+                  // !!! Test special case :
+                  // !!! in a cycle an instruction can check the last store AND commit instruction
+                  // !!! also the memory_out is before the port_check
+
+		  _load_queue [internal_MEMORY_OUT_PTR]._state    = LOAD_QUEUE_CHECK;
+		  // NOTE : a speculative load write in the register file.
+		  // if the speculation is a miss, write_rd is re set at 1.
+		  _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0;
+
+#ifdef STATISTICS
+                  if (usage_is_set(_usage,USE_STATISTICS))
+                    (*_stat_nb_inst_load_commit_speculative) ++;
+#endif
+
+		  break;
+		}
+
+		break;
+	      }
+	  }
+
+	//================================================================
+	// Interface "PORT_CHECK"
+	//================================================================
+	
+	// Plusieurs moyens de faire la verification de dépendance entre les loads et les stores.
+	//  1) un load ne peut vérifier qu'un store par cycle. Dans ce cas port_check <= size_load_queue
+	//  2) un load tente de vérifier le maximum de store par cycle. Dans ce cas ce n'est pas du pointeur d'écriture qu'il lui faut mais un vecteur de bit indiquant quel store à déjà été testé. De plus il faut un bit indiquant qu'il y a un match mais que ce n'est pas forcément le premier.
+
+	// solution 1)
+ 	log_printf(TRACE,Load_store_unit,FUNCTION,"  * CHECK");
+	for (uint32_t i=0, nb_check=0; (nb_check<_param->_nb_port_check) and (i<_param->_size_load_queue); i++)
+	  {
+            // Get an index from load queue
+	    uint32_t index_load_queue = (i + reg_LOAD_QUEUE_CHECK_PRIORITY)%_param->_size_load_queue;
+
+            // Test if this load must ckecked store queue
+	    if (((_load_queue[index_load_queue]._state == LOAD_QUEUE_WAIT_CHECK) or
+		 (_load_queue[index_load_queue]._state == LOAD_QUEUE_COMMIT_CHECK) or
+		 (_load_queue[index_load_queue]._state == LOAD_QUEUE_CHECK)) and
+		is_operation_memory_load(_load_queue[index_load_queue]._operation))
+	      {
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * Find a load : %d",index_load_queue);
+
+		nb_check++; // use one port
+
+		// find a entry that it need a check
+		Tlsq_ptr_t store_queue_ptr_write     = _load_queue[index_load_queue]._store_queue_ptr_write;
+		Tlsq_ptr_t store_queue_ptr_read      = _load_queue[index_load_queue]._store_queue_ptr_read ;
+ 		Tlsq_ptr_t store_queue_empty         = _load_queue[index_load_queue]._store_queue_empty    ;
+// 		Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write;
+
+                // Init variable
+		bool       end_check    = false;
+		bool       change_state = false;
+		bool       next         = false;
+
+		// At the first store queue empty, stop check.
+		// Explication :
+		//  * rename logic keep a empty case in the store queue (also size_store_queue > 1)
+		//  * when a store is out of store queue, also it was in head of re order buffer. Also, they are none previous load.
+
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_ptr_write    : %d",store_queue_ptr_write);
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_ptr_read     : %d",store_queue_ptr_read );
+// 		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue_empty        : %d",store_queue_empty );
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * reg_STORE_QUEUE_PTR_READ : %d",reg_STORE_QUEUE_PTR_READ);
+
+ 		if ((store_queue_ptr_write ==     store_queue_ptr_read) or
+		    (store_queue_ptr_write == reg_STORE_QUEUE_PTR_READ))
+// 		if (store_queue_empty)
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write == store_queue_ptr_read");
+		    end_check    = true;
+		    change_state = true;
+		  }
+		else
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write != store_queue_ptr_read");
+
+		    store_queue_ptr_write = (store_queue_ptr_write-1)%(_param->_size_store_queue); // store_queue_ptr_write target the next slot to write, also the slot is not significatif when the load is renaming
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write : %d",store_queue_ptr_write);
+
+                    bool test_thread_id = true;
+                    
+                    // Test thread id
+                    if (_param->_have_port_context_id)
+                      test_thread_id &= (_load_queue[index_load_queue]._context_id    == _store_queue[store_queue_ptr_write]._context_id);
+                    if (_param->_have_port_front_end_id)
+                      test_thread_id &= (_load_queue[index_load_queue]._front_end_id  == _store_queue[store_queue_ptr_write]._front_end_id);
+                    if (_param->_have_port_ooo_engine_id)
+                      test_thread_id &= (_load_queue[index_load_queue]._ooo_engine_id == _store_queue[store_queue_ptr_write]._ooo_engine_id);
+		    
+                    // switch on store_queue state
+		    switch (_store_queue[store_queue_ptr_write]._state)
+		      {
+		      case STORE_QUEUE_VALID_NO_SPECULATIVE : 
+		      case STORE_QUEUE_COMMIT :
+		      case STORE_QUEUE_VALID_SPECULATIVE :
+			{
+                          log_printf(TRACE,Load_store_unit,FUNCTION,"      * store have a valid entry");
+			  
+			  // TODO : MMU - nous considérons que les adresses sont physique
+			  if (test_thread_id)
+			    {
+			      // the load and store are in the same thread. Now, we must test address.
+
+			      log_printf(TRACE,Load_store_unit,FUNCTION,"        * load and store is the same thread.");
+			      Tdcache_address_t load_addr  = _load_queue [index_load_queue ]._address;
+			      Tdcache_address_t store_addr = _store_queue[store_queue_ptr_write]._address;
+			      
+			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * load_addr                     : %.8x.",load_addr );
+			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * store_addr                    : %.8x.",store_addr);
+			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * load_addr  & mask_address_msb : %.8x.",load_addr  & _param->_mask_address_msb);
+			      log_printf(TRACE,Load_store_unit,FUNCTION,"          * store_addr & mask_address_msb : %.8x.",store_addr & _param->_mask_address_msb);
+			      // Test if the both address target the same "word"
+			      if ((load_addr  & _param->_mask_address_msb) == 
+				  (store_addr & _param->_mask_address_msb))
+				{
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * address_msb is the same.");
+
+				  // all case - [] : store, () : load
+				  // (1) store_max >= load_max and store_min <= load_min  ...[...(...)...]... Ok - inclusion in store
+				  // (2) store_min >  load_max                            ...[...]...(...)... Ok - no conflit
+				  // (3) store_max <  load_min                            ...(...)...[...]... Ok - no conflit
+				  // (4) store_max <  load_max and store_min >  load_min  ...(...[...]...)... Ko - inclusion in load
+				  // (5) store_max >= load_max and store_min >  load_min  ...[...(...]...)... Ko - conflit
+				  // (6) store_max <  load_max and store_min <= load_min  ...(...[...)...]... Ko - conflit
+				  // but :
+				  // load in the cache is a word !
+				  // the mask can be make when the load is commited. Also, the rdata content a full word.
+				  // the only case is (4)
+				  
+                                  // Read data
+                                  bool is_big_endian = true;
+
+				  Tgeneral_data_t   load_data      = _load_queue [index_load_queue ]._rdata  ;
+				  Tgeneral_data_t   store_data     = _store_queue[store_queue_ptr_write]._wdata  ;
+                                  Tdcache_address_t check_hit_byte = _load_queue [index_load_queue ]._check_hit_byte;
+                                  Tcontrol_t        check_hit      = _load_queue [index_load_queue ]._check_hit;
+                                  uint32_t          load_size_access  = memory_size(_load_queue [index_load_queue ]._operation)>>3;
+                                  uint32_t          store_size_access = memory_size(_store_queue[store_queue_ptr_write]._operation)>>3;
+
+                                  log_printf(TRACE,Load_store_unit,FUNCTION,"            * is_big_endian           : %d",is_big_endian);
+                                  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data               : 0x%.8x",load_data);
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_data              : 0x%.8x",store_data);
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte          : %x",check_hit_byte);
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit               : %d",check_hit);
+
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_size_access        : %d",load_size_access );
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_size_access       : %d",store_size_access);
+
+                                  if (is_big_endian)
+                                    {
+                                      // swap in little endian
+                                      load_data      = swapBytes<Tgeneral_data_t  >(load_data     , _param->_size_general_data>>3,load_size_access);
+                                      store_data     = swapBytes<Tgeneral_data_t  >(store_data    , _param->_size_general_data>>3,store_size_access);
+                                      check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access);
+                                      
+                                      
+                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data      (swap 1) : 0x%.8x",load_data);
+                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_data     (swap 1) : 0x%.8x",store_data);
+                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte (swap 1) : %x",check_hit_byte);
+                                    }
+
+                                  uint32_t store_nb_byte     = (1<<memory_access(_store_queue[store_queue_ptr_write]._operation));
+
+                                  // Take interval to the store
+				  uint32_t store_num_byte_min = (store_addr & _param->_mask_address_lsb);
+				  uint32_t store_num_byte_max = store_num_byte_min+store_nb_byte;
+
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_num_byte_min      : %d",store_num_byte_min);
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * store_num_byte_max      : %d",store_num_byte_max);
+
+
+				  // The bypass is checked byte per byte
+                                  // Is same endianness : because to change endianness, we must write in special register. Also the pipeline is flushed.
+				  for (uint32_t num_store_byte=store_num_byte_min; num_store_byte<store_num_byte_max; num_store_byte ++)
+				    {
+                                      // Make a mask
+                                      uint32_t num_load_byte = num_store_byte;
+
+//                                       if (is_big_endian)
+//                                         {
+//                                           // sd 0 : 0 1 2 3 4 5 6 7
+//                                           // ld 0 : 0 1 2 3 4 5 6 7 >>  0 
+//                                           // lw 0 :         0 1 2 3 >>  0 -4
+//                                           // lw 4 : 4 5 6 7         >> 32 +4
+//                                           // lh 0 :             0 1 >>  0 -6
+//                                           // lh 2 :         2 3     >> 16 -2
+//                                           // lh 4 :     4 5         >> 32 +2
+//                                           // lh 6 : 6 7             >> 48 +6
+//                                           // lb 0 :               0 >>  0 -7
+//                                           // lb 1 :             1   >>  8 -5
+//                                           // lb 2 :           2     >> 16 -3
+//                                           // lb 3 :         3       >> 24 -1
+//                                           // lb 4 :       4         >> 32 +1
+//                                           // lb 5 :     5           >> 40 +3
+//                                           // lb 6 :   6             >> 48 +5
+//                                           // lb 7 : 7               >> 56 +7
+
+//                                           // diff : (store_nb_byte + load_nb_byte) - 2*nb_load_byte*((num_store_byte+1)
+
+//                                           // store duplicate = all store access can be see as full size_data store
+// //                                           uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load_queue ]._operation));
+
+// //                                           int32_t diff = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1));
+
+// //                                           num_load_byte =num_store_byte+diff;
+
+// //                                           log_printf(TRACE,Load_store_unit,FUNCTION,"              * load_nb_byte   : %d",load_nb_byte);
+// //                                           log_printf(TRACE,Load_store_unit,FUNCTION,"              * diff           : %d",diff);
+
+
+//                                           num_load_byte = num_store_byte;
+//                                         }
+//                                       else
+//                                         {
+//                                           // sd 0 : 0 1 2 3 4 5 6 7
+//                                           // ld 0 : 0 1 2 3 4 5 6 7 >>  0
+//                                           // lw 0 :         4 5 6 7 >>  0
+//                                           // lw 4 : 0 1 2 3         >> 32
+//                                           // lh 0 :             6 7 >>  0
+//                                           // lh 2 :         4 5     >> 16
+//                                           // lh 4 :     2 3         >> 32
+//                                           // lh 6 : 0 1             >> 48
+//                                           // lb 0 :               7 >>  0
+//                                           // lb 1 :             6   >>  8
+//                                           // lb 2 :           5     >> 16
+//                                           // lb 3 :         4       >> 24
+//                                           // lb 4 :       3         >> 32
+//                                           // lb 5 :     2           >> 40
+//                                           // lb 6 :   1             >> 48
+//                                           // lb 7 : 0               >> 56
+                                          
+//                                           num_load_byte = num_store_byte;
+//                                         }
+
+				      uint32_t mask  = 1<<num_load_byte;
+
+				      log_printf(TRACE,Load_store_unit,FUNCTION,"              * num_store_byte : %d",num_store_byte);
+				      log_printf(TRACE,Load_store_unit,FUNCTION,"              * num_load_byte  : %d",num_load_byte);
+				      log_printf(TRACE,Load_store_unit,FUNCTION,"              * mask           : %d",mask);
+
+				      // Accept the bypass if :
+                                      //   * they have not a previous bypass with an another store
+                                      //   * it's a valid request of load
+				      if ((check_hit_byte&mask)==0)
+					{
+                                          // Note : Store is duplicate = all store access can be see as full size_data store
+
+                                          uint32_t num_store_bit_min = num_store_byte<<3; //*8
+//                                        uint32_t num_store_bit_max = num_store_bit_min+8-1;
+                                          uint32_t num_load_bit_min  = num_load_byte <<3; //*8
+                                          uint32_t num_load_bit_max  = num_load_bit_min+8-1;
+
+					  log_printf(TRACE,Load_store_unit,FUNCTION,"              * bypass !!!");
+//                                        log_printf(TRACE,Load_store_unit,FUNCTION,"              * interval store : [%d:%d]",num_store_bit_max,num_store_bit_min);
+                                          log_printf(TRACE,Load_store_unit,FUNCTION,"              * interval store : [..:%d]",num_store_bit_min);
+                                          log_printf(TRACE,Load_store_unit,FUNCTION,"              * interval load  : [%d:%d]",num_load_bit_max,num_load_bit_min);
+					  log_printf(TRACE,Load_store_unit,FUNCTION,"                * rdata_old : 0x%.8x", load_data);
+
+					  load_data = ((((store_data>>num_store_bit_min) & 0xff) << num_load_bit_min) |
+                                                       mask_not<Tdcache_data_t>(load_data,num_load_bit_max,num_load_bit_min));
+
+					  check_hit_byte |= mask;
+					  check_hit       = 1;
+					  change_state = true;
+
+					  log_printf(TRACE,Load_store_unit,FUNCTION,"                * rdata_new : 0x%.8x", load_data);
+					}
+				    }
+
+                                  if (is_big_endian)
+                                    {
+                                      // swap in little endian
+                                      load_data      = swapBytes<Tgeneral_data_t  >(load_data     , _param->_size_general_data>>3,load_size_access);
+                                      check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access);
+                                      
+                                      
+                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data      (swap 2) : 0x%.8x",load_data);
+                                      log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte (swap 2) : %x",check_hit_byte);
+                                    }
+
+				  _load_queue[index_load_queue]._rdata          = load_data;
+                                  _load_queue[index_load_queue]._check_hit_byte = check_hit_byte;
+                                  _load_queue[index_load_queue]._check_hit      = check_hit;
+
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * load_data  (after) : 0x%.8x",load_data);
+
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit          : %x",check_hit);
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * check_hit_byte     : %x",check_hit_byte);
+
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * mask_end_check     : %x",(-1& _param->_mask_address_lsb));
+				  log_printf(TRACE,Load_store_unit,FUNCTION,"            * mask_check_hit_byte: %x",_param->_mask_check_hit_byte);
+				  // The check is finish if all bit is set
+				  end_check = (_load_queue[index_load_queue]._check_hit_byte == _param->_mask_check_hit_byte);
+
+                                  // TODO : autoriser l'envoie de la donnée !
+				}
+			    }
+			  
+			  next = true;
+			  break;
+			}
+		      case STORE_QUEUE_EMPTY :
+			{
+			  log_printf(TRACE,Load_store_unit,FUNCTION,"      * store is empty ... wait.");
+			  break;
+			}
+
+		      case STORE_QUEUE_NO_VALID_NO_SPECULATIVE :
+			{
+                          log_printf(TRACE,Load_store_unit,FUNCTION,"      * store have an invalid entry");
+
+			  if (test_thread_id)
+                            {
+                              end_check    = true; // previous store is invalid -> exception
+                              change_state = true;
+                            }
+                          else
+                            next = true;
+                            
+			  break;
+			}
+		      }
+		  }
+
+		if (next)
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * next");
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * new store_queue_ptr_write : %d",store_queue_ptr_write);
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * update reg_STORE_QUEUE_NB_CHECK");
+#ifdef DEBUG
+                    if (reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write] == 0)
+                      throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
+#endif
+
+                    reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write] --;
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 1 [%d] <- %d", store_queue_ptr_write,reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write]);
+
+		    if ((store_queue_ptr_write ==     store_queue_ptr_read) or
+			(store_queue_ptr_write == reg_STORE_QUEUE_PTR_READ))
+		      {
+// 			store_queue_empty = true;
+			end_check         = true;
+			change_state      = true;
+		      }
+
+// 		    if (_load_queue[index_load_queue]._store_queue_ptr_write == 0)
+// 		      _load_queue[index_load_queue]._store_queue_ptr_write = _param->_size_store_queue-1;
+// 		    else
+// 		      _load_queue[index_load_queue]._store_queue_ptr_write --;
+		    _load_queue[index_load_queue]._store_queue_ptr_write = store_queue_ptr_write; // because the index store have be decrease
+ 		    _load_queue[index_load_queue]._store_queue_empty     = store_queue_empty; // because the index store have be decrease
+
+		    // FIXME : peut n'est pas obliger de faire cette comparaison. Au prochain cycle on le détectera que les pointeur sont égaux. Ceci évitera d'avoir deux comparateurs avec le registre "store_queue_ptr_read"
+		  }
+
+		if (change_state)
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * change_state");
+                    log_printf(TRACE,Load_store_unit,FUNCTION,"              * end_check : %d",end_check);
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * state old : %s",toString(_load_queue[index_load_queue]._state).c_str());
+
+		    switch (_load_queue[index_load_queue]._state)
+		      {
+		      case LOAD_QUEUE_WAIT_CHECK   : 
+                        {
+			  if (end_check)
+                            _load_queue[index_load_queue]._state = LOAD_QUEUE_WAIT  ; 
+                          break;
+                        }
+		      case LOAD_QUEUE_COMMIT_CHECK : 
+			{
+			  if (end_check)
+			    _load_queue[index_load_queue]._state = LOAD_QUEUE_COMMIT; 
+			  else
+			    _load_queue[index_load_queue]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end
+			  break;
+			}
+		      case LOAD_QUEUE_CHECK        : 
+			{
+			  if (end_check)
+			    _load_queue[index_load_queue]._state     = LOAD_QUEUE_COMMIT;
+
+			  // check find a bypass. A speculative load have been committed : report a speculation miss.
+			  if ((_load_queue[index_load_queue]._check_hit != 0) and 
+                              (_load_queue[index_load_queue]._write_rd  == 0) // is commit
+                              )
+			    {
+			      _load_queue[index_load_queue]._exception = EXCEPTION_MEMORY_MISS_SPECULATION;
+			      _load_queue[index_load_queue]._write_rd  = 1; // write the good result
+
+#ifdef STATISTICS
+                              if (usage_is_set(_usage,USE_STATISTICS))
+                                (*_stat_nb_inst_load_commit_miss) ++;
+#endif
+			    }
+			  
+			  break;
+			}
+		      default : break;
+		      }
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * state new : %s",toString(_load_queue[index_load_queue]._state).c_str());
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"                * exception : %d",_load_queue[index_load_queue]._exception);
+
+                    if (end_check//  and not store_queue_empty
+			)
+                      {
+                        log_printf(TRACE,Load_store_unit,FUNCTION,"                * end check, decrease all nb_check");
+                        
+                        uint32_t i=store_queue_ptr_write;
+                        while (i!=store_queue_ptr_read)
+                          {
+                            i=((i==0)?_param->_size_store_queue:i)-1;
+                            
+#ifdef DEBUG
+                            if (reg_STORE_QUEUE_NB_CHECK [i] == 0)
+                              throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
+#endif
+			    
+                            reg_STORE_QUEUE_NB_CHECK [i] --;
+
+			    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 2 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
+
+                            //i=(i+1)%_param->_size_store_queue;
+                          }
+			
+			_load_queue[index_load_queue]._store_queue_empty = true; // end of check
+                      }
+		  }
+	      }
+	    // else : don't use a port
+	  }
+	
+	//================================================================
+	// Interface "MEMORY_IN"
+	//================================================================
+	
+        if ((PORT_READ(in_MEMORY_IN_VAL [internal_MEMORY_IN_PORT]) == 1) and
+            (    internal_MEMORY_IN_ACK  == 1))
+          {
+            log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_IN [%d]",internal_MEMORY_IN_PORT);
+
+	    // Test operation :
+	    //~~~~~~~~~~~~~~~~~
+	    //  store  in store_queue
+	    //  load   in speculation_access_queue
+	    //  others in speculation_access_queue
+
+#ifdef DEBUG_TEST
+	    if (PORT_READ(in_MEMORY_IN_TYPE [internal_MEMORY_IN_PORT]) != TYPE_MEMORY)
+	      throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'");
+#endif
+	    Toperation_t    operation            = PORT_READ(in_MEMORY_IN_OPERATION[internal_MEMORY_IN_PORT]);
+	    Tcontrol_t      cancel               = PORT_READ(in_MEMORY_IN_CANCEL   [internal_MEMORY_IN_PORT]);
+	    Tgeneral_data_t address              = (PORT_READ(in_MEMORY_IN_IMMEDIAT[internal_MEMORY_IN_PORT]) +
+						    PORT_READ(in_MEMORY_IN_DATA_RA [internal_MEMORY_IN_PORT]));
+	    bool            exception_alignement = (mask_memory_access(operation) & address) != 0;
+						    
+	    if (is_operation_memory_store(operation) == true)
+	      {
+		// =======================
+		// ===== STORE_QUEUE =====
+		// =======================
+		// There a two store request type :
+		//   - first is operation with address and data
+		//   - second is the information of re order buffer : the store become not speculative and can access at the data cache
+
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * store_queue");
+		log_printf(TRACE,Load_store_unit,FUNCTION,"      * PUSH");
+		
+		// Write pointer is define in rename stage :
+		Tlsq_ptr_t           index         = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
+		log_printf(TRACE,Load_store_unit,FUNCTION,"      * index         : %d",index);
+		
+		// Need read : state and exception.
+		Tstore_queue_state_t old_state     = _store_queue [index]._state;
+		Tstore_queue_state_t new_state     = old_state;
+		bool                 update_info   = false;
+
+		Texception_t         old_exception = _store_queue [index]._exception;
+		Texception_t         new_exception = old_exception;
+
+		// Compute next state
+		switch (old_state)
+		  {
+		  case STORE_QUEUE_EMPTY                   :
+		    {
+//                    reg_STORE_QUEUE_INVALID [index] = false; // new first store instruction
+
+		      if (is_operation_memory_store_head(operation) == true)
+			{
+			  new_state = STORE_QUEUE_NO_VALID_NO_SPECULATIVE;
+
+			  // test if is a speculation
+			  if (operation == OPERATION_MEMORY_STORE_HEAD_KO)
+                            {
+                              new_exception = EXCEPTION_MEMORY_MISS_SPECULATION;
+//                            reg_STORE_QUEUE_INVALID [index] = true;
+                            }
+			  else
+			    new_exception = EXCEPTION_MEMORY_NONE;
+			}
+		      else
+			{
+			  new_state = STORE_QUEUE_VALID_SPECULATIVE;
+
+			  // Test if have an exception
+			  if (exception_alignement == true)
+			    new_exception = EXCEPTION_MEMORY_ALIGNMENT;
+			  else
+			    new_exception = EXCEPTION_MEMORY_NONE;
+
+			  update_info = true;
+			}
+		      break;
+		    }
+		  case STORE_QUEUE_NO_VALID_NO_SPECULATIVE :
+		    {
+#ifdef DEBUG_TEST
+		      if (is_operation_memory_store_head(operation) == true)
+			throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_NO_VALID_NO_SPECULATIVE\", also a previous store_head have been receiveid. But this operation is a store_head."));
+#endif
+		      // Test if have a new exception (priority : miss_speculation)
+		      if ((exception_alignement == true) and (old_exception == EXCEPTION_MEMORY_NONE))
+			new_exception = EXCEPTION_MEMORY_ALIGNMENT;
+		      
+		      if (new_exception != EXCEPTION_MEMORY_NONE)
+			new_state = STORE_QUEUE_COMMIT;
+		      else
+			new_state = STORE_QUEUE_VALID_NO_SPECULATIVE;
+		      
+		      update_info = true;
+		      break;
+		    }
+		  case STORE_QUEUE_VALID_SPECULATIVE       :
+		    {
+#ifdef DEBUG_TEST
+		      if (is_operation_memory_store_head(operation) == false)
+			throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_VALID_SPECULATIVE\", also a previous access with register and address have been receiveid. But this operation is a not store_head."));
+#endif
+		      if (operation == OPERATION_MEMORY_STORE_HEAD_KO)
+                        {
+                          new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; // great prioritary
+//                        reg_STORE_QUEUE_INVALID [index] = true;
+                        }
+
+		      if (new_exception != EXCEPTION_MEMORY_NONE)
+			new_state = STORE_QUEUE_COMMIT;
+		      else
+			new_state = STORE_QUEUE_VALID_NO_SPECULATIVE;
+		      
+		      break;
+		    }
+		  case STORE_QUEUE_VALID_NO_SPECULATIVE    :
+		  case STORE_QUEUE_COMMIT                  :
+		    {
+		      throw ERRORMORPHEO(FUNCTION,"Invalid state and operation");
+		    }
+		  }
+
+		_store_queue [index]._state     = new_state;
+		_store_queue [index]._exception = new_exception;
+		
+		if (update_info == true)
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * Update information");
+
+		    _store_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID   [internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._packet_id            = (not _param->_have_port_rob_ptr      )?0:PORT_READ(in_MEMORY_IN_PACKET_ID    [internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._operation            = operation;
+		    _store_queue [index]._cancel               = cancel   ;
+		    _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._address              = address;
+		    _store_queue [index]._send_commit          = false;
+
+		    // reordering data
+		    _store_queue [index]._wdata                = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0); 
+//                  _store_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  [internal_MEMORY_IN_PORT]);
+		  }
+	      }
+	    else
+	      {
+		// ====================================
+		// ===== SPECULATIVE_ACCESS_QUEUE =====
+		// ====================================
+
+		// In speculative access queue, they are many type's request
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue");
+		log_printf(TRACE,Load_store_unit,FUNCTION,"      * PUSH");
+		
+		// Write in reservation station
+		uint32_t     index = _speculative_access_queue_control->push();
+
+		log_printf(TRACE,Load_store_unit,FUNCTION,"      * index : %d", index);
+
+		Texception_t exception;
+
+		if (exception_alignement == true)
+		  exception = EXCEPTION_MEMORY_ALIGNMENT;
+		else
+		  exception = EXCEPTION_MEMORY_NONE;
+				
+		// if exception, don't access at the cache
+		// NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits)
+		_speculative_access_queue [index]._state                = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE;
+		_speculative_access_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID   [internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._packet_id            = (not _param->_have_port_rob_ptr      )?0:PORT_READ(in_MEMORY_IN_PACKET_ID    [internal_MEMORY_IN_PORT]);
+
+		_speculative_access_queue [index]._operation            = operation;
+		_speculative_access_queue [index]._cancel               = cancel   ;
+		_speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._store_queue_ptr_read = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_READ [internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._store_queue_empty    = PORT_READ(in_MEMORY_IN_STORE_QUEUE_EMPTY    [internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._address              = address;
+		// NOTE : is operation is a load, then they are a result and must write in the register file
+		_speculative_access_queue [index]._write_rd             = is_operation_memory_load(operation);
+		_speculative_access_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  [internal_MEMORY_IN_PORT]);
+
+		_speculative_access_queue [index]._exception            = exception;
+	      }
+	  }
+
+	//================================================================
+	// Interface "DCACHE_REQ"
+	//================================================================
+        if ((    internal_DCACHE_REQ_VAL  == 1) and
+            (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1))
+          {
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_REQ [0]");
+
+	    switch (internal_DCACHE_REQ_SELECT_QUEUE)
+	      {
+	      case SELECT_STORE_QUEUE :
+		{
+		  // =======================
+		  // ===== STORE_QUEUE =====
+		  // =======================
+		  
+		  // Entry flush and increase the read pointer
+		  
+		  _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_COMMIT;
+
+#if defined(DEBUG) and defined(DEBUG_Load_store_unit) and (DEBUG_Load_store_unit == true)
+		  if (log_file_generate)
+	            {
+	              // log file
+                      Tcontext_t num_thread    = get_num_thread(_store_queue [reg_STORE_QUEUE_PTR_READ]._context_id   , _param->_size_context_id   ,
+                                                                _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id , _param->_size_front_end_id ,
+                                                                _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id, _param->_size_ooo_engine_id);
+
+	              memory_log_file [num_thread] 
+	            	<< "[" << simulation_cycle() << "] "
+	            	<< std::hex
+                        << "@ 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _store_queue [reg_STORE_QUEUE_PTR_READ]._address << " -[ Write ]-> 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata << " "
+	            	<< std::dec
+	            	<< "{" << toString(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation) << "}";
+	              
+	              memory_log_file [num_thread] << std::endl;
+	            }
+#endif	    
+
+
+		  break;
+		}
+	      case SELECT_LOAD_QUEUE_SPECULATIVE :
+		{
+		  // =========================================
+		  // ===== SELECT_LOAD_QUEUE_SPECULATIVE =====
+		  // =========================================
+
+		  load_queue_push = true;
+		  break;
+		}
+	      case SELECT_LOAD_QUEUE :
+		{
+		  throw ERRORMORPHEO(FUNCTION,_("Invalid selection"));
+		  break;
+		}
+
+		break;
+	      }
+	  }
+
+	if (load_queue_push)
+	  {
+            log_printf(TRACE,Load_store_unit,FUNCTION,"  * load_queue_push");
+
+	    Tlsq_ptr_t   ptr_write = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write;
+	    Toperation_t operation = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation;
+	    Texception_t exception = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._exception;
+	    bool         have_exception = (exception != EXCEPTION_MEMORY_NONE);
+            bool         need_check= false;
+            Tlsq_ptr_t   store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;
+            Tlsq_ptr_t   store_queue_ptr_read  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_read ;
+            Tcontrol_t   store_queue_empty     = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_empty    ;
+	    
+	    if (have_exception)
+	      _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT;
+	    else
+	      {
+		if (have_dcache_rsp(operation))
+		  {
+		    // load and synchronisation
+		    if (must_check(operation) and not store_queue_empty)
+		      {
+			// load
+                        need_check = true;
+			
+			_load_queue [ptr_write]._state = LOAD_QUEUE_WAIT_CHECK;
+		      }
+		    else
+		      {
+			// synchronisation
+			_load_queue [ptr_write]._state = LOAD_QUEUE_WAIT;
+		      }
+		  }
+		else
+		  {
+		    // lock, prefecth, flush and invalidate
+		    _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT;
+		  }
+	      }
+
+	    Tdcache_address_t address        = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;
+	    Tdcache_address_t address_lsb    = (address & _param->_mask_address_lsb);
+	    Tdcache_address_t check_hit_byte = gen_mask_not<Tdcache_address_t>(address_lsb+(memory_size(operation)>>3)-1,address_lsb) & _param->_mask_check_hit_byte;
+
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * address                 : 0x%.8x", address);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * address_lsb             : 0x%.8x", address_lsb);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * operation               : %d", operation);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * memory_size             : %d", memory_size(operation));
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * check_hit_byte          : 0x%x", check_hit_byte);
+
+	    _load_queue [ptr_write]._context_id            = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
+	    _load_queue [ptr_write]._front_end_id          = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
+	    _load_queue [ptr_write]._ooo_engine_id         = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
+	    _load_queue [ptr_write]._packet_id             = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._packet_id;
+	    _load_queue [ptr_write]._operation             = operation;
+	    _load_queue [ptr_write]._cancel                = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._cancel;
+	    _load_queue [ptr_write]._store_queue_ptr_write = store_queue_ptr_write;
+	    _load_queue [ptr_write]._store_queue_ptr_read  = store_queue_ptr_read ;
+ 	    _load_queue [ptr_write]._store_queue_empty     = store_queue_empty    ;
+	    _load_queue [ptr_write]._address               = address;
+	    _load_queue [ptr_write]._check_hit_byte        = check_hit_byte;
+	    _load_queue [ptr_write]._check_hit             = 0;
+	    _load_queue [ptr_write]._shift                 = address_lsb<<3;// *8
+	    _load_queue [ptr_write]._is_load_signed        = is_operation_memory_load_signed(operation);
+	    _load_queue [ptr_write]._access_size           = memory_size(operation);
+	    // NOTE : if have an exception, must write in register, because a depend instruction wait the load data.
+	    _load_queue [ptr_write]._write_rd              = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._write_rd             ;
+	    _load_queue [ptr_write]._num_reg_rd            = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._num_reg_rd           ;
+	    _load_queue [ptr_write]._exception             = exception;
+	    _load_queue [ptr_write]._rdata                 = address; // to the exception
+
+            switch (_param->_speculative_commit_predictor_scheme)
+              {
+
+              case PREDICTOR_NEVER_TAKE  : {_load_queue [ptr_write]._can_speculative_commit = false; break;}
+              case PREDICTOR_ALWAYS_TAKE : {_load_queue [ptr_write]._can_speculative_commit = true ; break;}
+              case PREDICTOR_COUNTER     : {_load_queue [ptr_write]._can_speculative_commit = false; break;} // TODO
+              default :
+                {
+                  // throw ERRORMORPHEO(FUNCTION,_("Invalid predictor scheme.\n"));
+                  _load_queue [ptr_write]._can_speculative_commit = false;
+                  break;
+                }
+              }
+	    
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue");
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * POP[%d]",(*_speculative_access_queue_control)[0]);
+	    
+	    _speculative_access_queue [(*_speculative_access_queue_control)[0]]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY;
+	    
+	    _speculative_access_queue_control->pop();
+
+#ifdef STATISTICS
+            if (usage_is_set(_usage,USE_STATISTICS))
+              (*_stat_nb_inst_load) ++;
+#endif
+
+            // Only load need check
+            if (need_check//  and not store_queue_empty
+		)
+//             if (is_operation_memory_load(_load_queue [ptr_write]._operation))
+              {
+                log_printf(TRACE,Load_store_unit,FUNCTION,"    * update nb_check");
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_ptr_write : %d",store_queue_ptr_write);
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_ptr_read  : %d",store_queue_ptr_read );
+		log_printf(TRACE,Load_store_unit,FUNCTION,"      *     store_queue_empty     : %d",store_queue_empty    );
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      * reg_STORE_QUEUE_PTR_READ  : %d",reg_STORE_QUEUE_PTR_READ);
+                
+                uint32_t i=store_queue_ptr_write;
+                while (i!=store_queue_ptr_read)
+                  {
+                    i=((i==0)?_param->_size_store_queue:i)-1;
+                    
+                    log_printf(TRACE,Load_store_unit,FUNCTION,"      * i                         : %d",i);
+                    
+                    reg_STORE_QUEUE_NB_CHECK [i] ++;
+
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 3 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
+                  }
+              }
+          }
+
+	//================================================================
+	// Interface "DCACHE_RSP"
+	//================================================================
+        if ((PORT_READ(in_DCACHE_RSP_VAL[0])== 1) and
+            (    internal_DCACHE_RSP_ACK == 1))
+          {
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_RSP [0]");
+
+	    // don't use context_id : because there are one queue for all thread
+	    //Tcontext_t      context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID[0]); 
+	    Tpacket_t       packet_id  = PORT_READ(in_DCACHE_RSP_PACKET_ID [0]);
+	    Tdcache_data_t  rdata      = PORT_READ(in_DCACHE_RSP_RDATA     [0]);
+	    Tdcache_error_t error      = PORT_READ(in_DCACHE_RSP_ERROR     [0]);
+
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * original packet_id : %d"  , packet_id);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * packet_id          : %d"  , packet_id>>1);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * rdata              : %.8x", rdata);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * error              : %d"  , error);
+	    
+	    if (DCACHE_RSP_IS_LOAD(packet_id) == 1)
+	      {
+		packet_id >>= 1;
+
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * packet is a LOAD");
+ 
+#ifdef DEBUG_TEST
+		if (not have_dcache_rsp(_load_queue [packet_id]._operation))
+		  throw ERRORMORPHEO(FUNCTION,_("Receive of respons, but the corresponding operation don't wait a respons."));
+#endif
+
+                Tdcache_data_t data = _load_queue [packet_id]._rdata;
+
+                log_printf(TRACE,Load_store_unit,FUNCTION,"    * data construction");
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      * data from cache     : 0x%.8x",rdata);
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      * data (before)       : 0x%.8x", data);
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      * check_hit_byte      : 0x%x"  ,_load_queue [packet_id]._check_hit_byte);
+                for (uint32_t i=0;i<(_param->_size_general_data>>3)/*8*/; ++i)
+                  // Test if this byte has been checked
+                  if ((_load_queue [packet_id]._check_hit_byte & (1<<i)) == 0)
+                    {
+                      log_printf(TRACE,Load_store_unit,FUNCTION,"      * no previous check ]%d:%d]",(i+1)<<3,i<<3);
+                      data = insert<Tdcache_data_t>(data,rdata,((i+1)<<3)-1,i<<3);
+                    }
+                log_printf(TRACE,Load_store_unit,FUNCTION,"      * data (after)        : 0x%.8x", data);
+                
+                _load_queue [packet_id]._rdata = data;
+		
+#if defined(DEBUG) and defined(DEBUG_Load_store_unit) and (DEBUG_Load_store_unit == true)
+		if (log_file_generate)
+		  {
+		    // log file
+		    Tcontext_t num_thread    = get_num_thread(_load_queue [packet_id]._context_id   , _param->_size_context_id   ,
+							      _load_queue [packet_id]._front_end_id , _param->_size_front_end_id ,
+							      _load_queue [packet_id]._ooo_engine_id, _param->_size_ooo_engine_id);
+		    
+		    memory_log_file [num_thread] 
+		      << "[" << simulation_cycle() << "] "
+		      << std::hex
+		      << "@ 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _load_queue [packet_id]._address << " -[ Read  ]-> 0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << _load_queue [packet_id]._rdata << " "
+		      << std::dec
+		      << "{" << toString(_load_queue [packet_id]._operation) << "}";
+		    
+		    memory_log_file [num_thread] << std::endl;
+		  }
+#endif	    
+
+		if (error != DCACHE_ERROR_NONE)
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"    * have a bus error !!!");
+
+		    _load_queue [packet_id]._exception = EXCEPTION_MEMORY_BUS_ERROR;
+		    _load_queue [packet_id]._state     = LOAD_QUEUE_COMMIT;
+
+                    
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_write : %d", _load_queue[packet_id]._store_queue_ptr_write);
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_ptr_read  : %d", _load_queue[packet_id]._store_queue_ptr_read );
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * store_queue_empty     : %d", _load_queue[packet_id]._store_queue_empty    );
+
+ 		    if (not _load_queue[packet_id]._store_queue_empty)
+		      {
+			uint32_t i=_load_queue[packet_id]._store_queue_ptr_write;
+			
+			while (i!=_load_queue[packet_id]._store_queue_ptr_read)
+			  {
+			    i=((i==0)?_param->_size_store_queue:i)-1;
+			    
+#ifdef DEBUG
+			    if (reg_STORE_QUEUE_NB_CHECK [i] == 0)
+			      throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
+#endif
+			    
+			    reg_STORE_QUEUE_NB_CHECK [i] --;
+
+			    log_printf(TRACE,Load_store_unit,FUNCTION,"              * reg_STORE_QUEUE_NB_CHECK 4 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]);
+
+			    //i=(i+1)%_param->_size_store_queue;
+			  }
+			_load_queue[packet_id]._store_queue_empty = true; // end of check
+
+		      }
+		  }
+		else
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"    * have no bus error.");
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"      * previous state : %s",toString(_load_queue [packet_id]._state).c_str());
+
+		    // FIXME : convention : if bus error, the cache return the fautive address !
+		    // But, the load's address is aligned !
+
+		    switch (_load_queue [packet_id]._state)
+		      {
+		      case LOAD_QUEUE_WAIT_CHECK : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT_CHECK; break;
+		      case LOAD_QUEUE_WAIT       : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT      ; break;
+		      default : throw ERRORMORPHEO(FUNCTION,_("Illegal state (dcache_rsp).")); break;
+		      }
+		  }
+	      }
+	    else
+	      {
+		log_printf(TRACE,Load_store_unit,FUNCTION,"    * packet is a STORE");
+		
+		// TODO : les stores ne génére pas de réponse sauf quand c'est un bus error !!!
+		throw ERRORMORPHEO(FUNCTION,_("dcache_rsp : no respons to a write. (TODO : manage bus error to the store operation.)"));
+	      }
+	    
+	  }
+	
+	// this register is to manage the priority of check -> Round robin
+	reg_LOAD_QUEUE_CHECK_PRIORITY = (reg_LOAD_QUEUE_CHECK_PRIORITY+1)%_param->_size_load_queue;
+	
+	
+#if defined(DEBUG) and (DEBUG>=DEBUG_TRACE)
+	// ***** dump store queue
+        log_printf(TRACE,Load_store_unit,FUNCTION,"  * Dump STORE_QUEUE");
+        log_printf(TRACE,Load_store_unit,FUNCTION,"    * ptr_read : %d",reg_STORE_QUEUE_PTR_READ);
+	
+	for (uint32_t i=0; i<_param->_size_store_queue; i++)
+	  {
+	    uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
+
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d %.1d, %.4d, %.8x %.8x, %.2d %.1d, %.2d %s",
+                       j,
+                       _store_queue[j]._context_id          ,
+                       _store_queue[j]._front_end_id        ,
+                       _store_queue[j]._ooo_engine_id       ,
+                       _store_queue[j]._packet_id           ,
+                       _store_queue[j]._operation           ,
+                       _store_queue[j]._cancel              ,
+                       _store_queue[j]._load_queue_ptr_write,
+                       _store_queue[j]._address             ,
+                       _store_queue[j]._wdata               ,
+                     //_store_queue[j]._write_rd            ,
+                     //_store_queue[j]._num_reg_rd          ,
+                       _store_queue[j]._exception           ,
+                       _store_queue[j]._send_commit         ,
+                       reg_STORE_QUEUE_NB_CHECK  [j]        ,
+                       toString(_store_queue[j]._state).c_str());
+	  }
+
+	// ***** dump speculative_access queue
+	log_printf(TRACE,Load_store_unit,FUNCTION,"  * Dump SPECULATIVE_ACCESS_QUEUE");
+	
+	for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
+	  {
+	    uint32_t j = (*_speculative_access_queue_control)[i];
+
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d %.1d, %.4d %.4d %.4d %.1d, %.8x, %.1d %.4d, %.2d, %s",
+                       j,
+                       _speculative_access_queue[j]._context_id          ,
+                       _speculative_access_queue[j]._front_end_id        ,
+                       _speculative_access_queue[j]._ooo_engine_id       ,
+                       _speculative_access_queue[j]._packet_id           ,
+                       _speculative_access_queue[j]._operation           ,
+                       _speculative_access_queue[j]._cancel              ,
+                       _speculative_access_queue[j]._load_queue_ptr_write,
+                       _speculative_access_queue[j]._store_queue_ptr_write,
+                       _speculative_access_queue[j]._store_queue_ptr_read ,
+                       _speculative_access_queue[j]._store_queue_empty    ,
+                       _speculative_access_queue[j]._address             ,
+                       _speculative_access_queue[j]._write_rd            ,
+                       _speculative_access_queue[j]._num_reg_rd          ,
+                       _speculative_access_queue[j]._exception           ,
+                       toString(_speculative_access_queue[j]._state).c_str());
+	  }
+
+	// ***** dump load queue
+	log_printf(TRACE,Load_store_unit,FUNCTION,"  * Dump LOAD_QUEUE");
+        log_printf(TRACE,Load_store_unit,FUNCTION,"    * ptr_read_check_priority : %d",reg_LOAD_QUEUE_CHECK_PRIORITY);
+	
+	for (uint32_t i=0; i<_param->_size_load_queue; i++)
+	  {
+	    uint32_t j = i;
+
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d %.1d, %.4d %.4d %.1d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s",
+                       j,
+                       _load_queue[j]._context_id          ,
+                       _load_queue[j]._front_end_id        ,
+                       _load_queue[j]._ooo_engine_id       ,
+                       _load_queue[j]._packet_id           ,
+                       _load_queue[j]._operation           ,
+                       _load_queue[j]._cancel              ,
+                       _load_queue[j]._store_queue_ptr_write,
+                       _load_queue[j]._store_queue_ptr_read ,
+		       _load_queue[j]._store_queue_empty    ,
+                       _load_queue[j]._address             ,
+                       _load_queue[j]._check_hit_byte      , 
+                       _load_queue[j]._check_hit           ,
+                       _load_queue[j]._shift               ,
+                       _load_queue[j]._is_load_signed      ,
+                       _load_queue[j]._access_size         ,
+                       _load_queue[j]._rdata               ,
+                       _load_queue[j]._write_rd            ,
+                       _load_queue[j]._num_reg_rd          ,
+                       _load_queue[j]._exception           ,
+                       toString(_load_queue[j]._state).c_str());
+	  }
+#endif
+	
+#ifdef STATISTICS
+        if (usage_is_set(_usage,USE_STATISTICS))
+          {
+            for (uint32_t i=0; i<_param->_size_store_queue; i++)
+              if (_store_queue[i]._state != STORE_QUEUE_EMPTY)
+                (*_stat_use_store_queue) ++;
+            for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
+              if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY)
+                (*_stat_use_speculative_access_queue) ++;
+            for (uint32_t i=0; i<_param->_size_load_queue; i++)
+              if (_load_queue[i]._state != LOAD_QUEUE_EMPTY)
+                (*_stat_use_load_queue) ++;
+          }
+#endif
+      }
+
+    log_end(Load_store_unit,FUNCTION);
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp	(revision 145)
@@ -30,24 +30,33 @@
     switch (_speculative_load)
       {
-      case SPECULATIVE_LOAD_ACCESS :
+      case SPECULATIVE_LOAD_COMMIT :
+      // case SPECULATIVE_LOAD_ACCESS :
 	{
-	  if (not (_nb_bypass_memory == 0))
-	    test.error(_("Bypass memory is not supported. Please wait a next revision.\n"));
- 
 	  break;
 	}
       case NO_SPECULATIVE_LOAD     :
-      // case SPECULATIVE_LOAD_BYPASS :
-      // case SPECULATIVE_LOAD_COMMIT :
       default                      :
 	{
-	  if (not (_nb_bypass_memory == 0))
-	    test.error(toString(_("In the load scheme '%s', they have none bypass.\n"),toString(_speculative_load).c_str()));
-
-	  test.error(toString(_("Speculative load scheme '%s' is not supported. Please wait a next revision.\n"),toString(_speculative_load).c_str()));
+	  test.error(toString(_("Speculative load scheme '%s' is not yet supported.\n"),toString(_speculative_load).c_str()));
 	  break;
 	}
       }
 
+    if (_nb_bypass_memory > 0)
+      switch (_speculative_load)
+        {
+        case SPECULATIVE_LOAD_COMMIT :
+          {
+            break;
+          }
+        case NO_SPECULATIVE_LOAD     :
+        // case SPECULATIVE_LOAD_ACCESS :
+        default                      :
+          {
+            test.error(toString(_("In the load scheme '%s', they have none bypass.\n"),toString(_speculative_load).c_str()));
+            break;
+          }
+        }
+      
     if (not (_size_store_queue >= 2))
       test.error(_("Store queue must have at less two slot.\n"));
@@ -66,6 +75,11 @@
       case PREDICTOR_NEVER_TAKE  :
       case PREDICTOR_ALWAYS_TAKE :
+        {
+          break;
+        }
       case PREDICTOR_COUNTER     :
         {
+          test.error(toString(_("Predictor scheme \"%s\" is not yet supported.\n"),toString(_speculative_commit_predictor_scheme).c_str()));
+
           break;
         }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/config0.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/config0.cfg	(revision 144)
+++ 	(revision )
@@ -1,14 +1,0 @@
-Read_queue
-2	8	*2	# size_queue    
-1	1	*2	# nb_context         
-1	1	*2	# nb_front_end       
-4	4	*2	# nb_ooo_engine      
-32	32	*2	# nb_packet          
-16	16	+1	# size_general_data  
-8	8	+1	# size_special_data  
-16	16	*2	# nb_general_register
-2 	2 	+1	# nb_special_register
-4	4	*2	# nb_gpr_write
-2	2	*2	# nb_spr_write
-4	4	*2	# size_store_queue
-1	4	*4	# size_load_queue    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/config1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/config1.cfg	(revision 144)
+++ 	(revision )
@@ -1,14 +1,0 @@
-Read_queue
-4	4	*2	# size_queue    
-1	1	*2	# nb_context         
-1	1	*2	# nb_front_end 
-1	1	*2	# nb_ooo_engine
-32	32	*2	# nb_packet          
-16	16	+1	# size_general_data  
-16	16	+1	# size_special_data  
-4 	4 	*2	# nb_general_register
-4 	4 	+1	# nb_special_register
-2	4	*2	# nb_gpr_write
-2	4	*2	# nb_spr_write
-4	4	*2	# size_store_queue
-4	4	*2	# size_load_queue    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/config2.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/config2.cfg	(revision 144)
+++ 	(revision )
@@ -1,14 +1,0 @@
-Read_queue
-4	4	*2	# size_queue    
-2	4	*2	# nb_context         
-2	4	*2	# nb_front_end 
-1	4	*2	# nb_ooo_engine
-32	32	*2	# nb_packet          
-16	16	+1	# size_general_data  
-16	16	+1	# size_special_data  
-4 	4 	*2	# nb_general_register
-4 	4 	+1	# nb_special_register
-1	1	*2	# nb_gpr_write
-1	1	*2	# nb_spr_write
-4	4	*2	# size_store_queue
-4	4	*2	# size_load_queue    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,14 +1,0 @@
-Read_queue
-1	4	*2	# size_queue    
-1	1	*2	# nb_context         
-1	1	*2	# nb_front_end       
-1	1	*2	# nb_ooo_engine      
-32	32	*2	# nb_packet          
-16	16	+1	# size_general_data  
-2	2	+1	# size_special_data  
-32	32	*2	# nb_general_register
-32	32	+1	# nb_special_register
-1 	1 	*2	# nb_gpr_write
-1 	1 	*2	# nb_spr_write
-4	4	*2	# size_store_queue
-4	4	*2	# size_load_queue    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/configuration/config0.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/configuration/config0.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/configuration/config0.gen	(revision 145)
@@ -0,0 +1,14 @@
+Read_queue
+2	8	*2	# size_queue    
+1	1	*2	# nb_context         
+1	1	*2	# nb_front_end       
+4	4	*2	# nb_ooo_engine      
+32	32	*2	# nb_packet          
+16	16	+1	# size_general_data  
+8	8	+1	# size_special_data  
+16	16	*2	# nb_general_register
+2 	2 	+1	# nb_special_register
+4	4	*2	# nb_gpr_write
+2	2	*2	# nb_spr_write
+4	4	*2	# size_store_queue
+1	4	*4	# size_load_queue    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/configuration/config1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/configuration/config1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/configuration/config1.gen	(revision 145)
@@ -0,0 +1,14 @@
+Read_queue
+4	4	*2	# size_queue    
+1	1	*2	# nb_context         
+1	1	*2	# nb_front_end 
+1	1	*2	# nb_ooo_engine
+32	32	*2	# nb_packet          
+16	16	+1	# size_general_data  
+16	16	+1	# size_special_data  
+4 	4 	*2	# nb_general_register
+4 	4 	+1	# nb_special_register
+2	4	*2	# nb_gpr_write
+2	4	*2	# nb_spr_write
+4	4	*2	# size_store_queue
+4	4	*2	# size_load_queue    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/configuration/config2.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/configuration/config2.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/configuration/config2.gen	(revision 145)
@@ -0,0 +1,14 @@
+Read_queue
+4	4	*2	# size_queue    
+2	4	*2	# nb_context         
+2	4	*2	# nb_front_end 
+1	4	*2	# nb_ooo_engine
+32	32	*2	# nb_packet          
+16	16	+1	# size_general_data  
+16	16	+1	# size_special_data  
+4 	4 	*2	# nb_general_register
+4 	4 	+1	# nb_special_register
+1	1	*2	# nb_gpr_write
+1	1	*2	# nb_spr_write
+4	4	*2	# size_store_queue
+4	4	*2	# size_load_queue    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,14 @@
+Read_queue
+1	4	*2	# size_queue    
+1	1	*2	# nb_context         
+1	1	*2	# nb_front_end       
+1	1	*2	# nb_ooo_engine      
+32	32	*2	# nb_packet          
+16	16	+1	# size_general_data  
+2	2	+1	# size_special_data  
+32	32	*2	# nb_general_register
+32	32	+1	# nb_special_register
+1 	1 	*2	# nb_gpr_write
+1 	1 	*2	# nb_spr_write
+4	4	*2	# size_store_queue
+4	4	*2	# size_load_queue    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_bypass_memory.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_bypass_memory.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_bypass_memory.gen	(revision 145)
@@ -0,0 +1,17 @@
+Reservation_station
+1 	16 	*2	# size_queue    
+1	1	*4	# nb_inst_retire
+1	1	*4	# nb_context         
+1	1	*4	# nb_front_end       
+4	4	*4	# nb_ooo_engine
+64 	64 	*2	# nb_packet          
+32	32	+1	# size_general_data  
+2 	2 	+1	# size_special_data  
+16 	16 	*2	# nb_general_register
+8 	8 	+1	# nb_special_register
+1	1	*2	# nb_gpr_write
+1	1	*2	# nb_spr_write
+0	0	*2	# nb_bypass_write 
+1	4	*2	# nb_bypass_memory
+4	4	*2	# size_store_queue
+4	4	*2	# size_load_queue 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_bypass_write.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_bypass_write.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_bypass_write.gen	(revision 145)
@@ -0,0 +1,17 @@
+Reservation_station
+1 	16 	*2	# size_queue    
+1	1	*4	# nb_inst_retire
+1	1	*4	# nb_context         
+1	1	*4	# nb_front_end       
+4	4	*4	# nb_ooo_engine
+64 	64 	*2	# nb_packet          
+32	32	+1	# size_general_data  
+2 	2 	+1	# size_special_data  
+16 	16     	*2	# nb_general_register
+8 	8 	+1	# nb_special_register
+1	1	*2	# nb_gpr_write
+1	1	*2	# nb_spr_write
+1	4	*2	# nb_bypass_write 
+0	0	*2	# nb_bypass_memory
+4	4	*2	# size_store_queue
+4	4	*2	# size_load_queue 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_retire2.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_retire2.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_retire2.gen	(revision 145)
@@ -0,0 +1,17 @@
+Reservation_station
+2 	16 	*2	# size_queue    
+2	2	*4	# nb_inst_retire
+1	1	*4	# nb_context         
+1	1	*4	# nb_front_end       
+4	4	*4	# nb_ooo_engine
+64 	64 	*2	# nb_packet          
+32	32	+1	# size_general_data  
+2 	2 	+1	# size_special_data  
+18   	16 	*2	# nb_general_register
+8 	8 	+1	# nb_special_register
+1	1	*2	# nb_gpr_write
+1	1	*2	# nb_spr_write
+0	0	*2	# nb_bypass_write 
+0	0	*2	# nb_bypass_memory
+4	4	*2	# size_store_queue
+4	4	*2	# size_load_queue 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_retire4.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_retire4.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_retire4.gen	(revision 145)
@@ -0,0 +1,17 @@
+Reservation_station
+4 	16 	*2	# size_queue    
+4	4	*4	# nb_inst_retire
+1	1	*4	# nb_context         
+1	1	*4	# nb_front_end       
+4	4	*4	# nb_ooo_engine
+64 	64 	*2	# nb_packet          
+32	32	+1	# size_general_data  
+2 	2 	+1	# size_special_data  
+16	16	*2	# nb_general_register
+8 	8	+1	# nb_special_register
+1 	1	*2	# nb_gpr_write
+1	1	*2	# nb_spr_write
+0	0	*2	# nb_bypass_write 
+0	0	*2	# nb_bypass_memory
+4	4	*2	# size_store_queue
+4	4	*2	# size_load_queue 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_write.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_write.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration/configuration_multi_port_write.gen	(revision 145)
@@ -0,0 +1,17 @@
+Reservation_station
+1 	16 	*2	# size_queue    
+1	1	*4	# nb_inst_retire
+1	1	*4	# nb_context         
+1	1	*4	# nb_front_end       
+4	4	*4	# nb_ooo_engine
+64 	64 	*2	# nb_packet          
+32	32	+1	# size_general_data  
+2 	2 	+1	# size_special_data  
+16 	16 	*2	# nb_general_register
+8 	8 	+1	# nb_special_register
+2	4	*2	# nb_gpr_write
+2	4	*2	# nb_spr_write
+0	0	*2	# nb_bypass_write 
+0	0	*2	# nb_bypass_memory
+4	4	*2	# size_store_queue
+1	4	*4	# size_load_queue 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration_multi_port_bypass_memory.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration_multi_port_bypass_memory.cfg	(revision 144)
+++ 	(revision )
@@ -1,17 +1,0 @@
-Reservation_station
-1 	16 	*2	# size_queue    
-1	1	*4	# nb_inst_retire
-1	1	*4	# nb_context         
-1	1	*4	# nb_front_end       
-4	4	*4	# nb_ooo_engine
-64 	64 	*2	# nb_packet          
-32	32	+1	# size_general_data  
-2 	2 	+1	# size_special_data  
-16 	16 	*2	# nb_general_register
-8 	8 	+1	# nb_special_register
-1	1	*2	# nb_gpr_write
-1	1	*2	# nb_spr_write
-0	0	*2	# nb_bypass_write 
-1	4	*2	# nb_bypass_memory
-4	4	*2	# size_store_queue
-4	4	*2	# size_load_queue 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration_multi_port_bypass_write.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration_multi_port_bypass_write.cfg	(revision 144)
+++ 	(revision )
@@ -1,17 +1,0 @@
-Reservation_station
-1 	16 	*2	# size_queue    
-1	1	*4	# nb_inst_retire
-1	1	*4	# nb_context         
-1	1	*4	# nb_front_end       
-4	4	*4	# nb_ooo_engine
-64 	64 	*2	# nb_packet          
-32	32	+1	# size_general_data  
-2 	2 	+1	# size_special_data  
-16 	16     	*2	# nb_general_register
-8 	8 	+1	# nb_special_register
-1	1	*2	# nb_gpr_write
-1	1	*2	# nb_spr_write
-1	4	*2	# nb_bypass_write 
-0	0	*2	# nb_bypass_memory
-4	4	*2	# size_store_queue
-4	4	*2	# size_load_queue 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration_multi_port_retire2.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration_multi_port_retire2.cfg	(revision 144)
+++ 	(revision )
@@ -1,17 +1,0 @@
-Reservation_station
-2 	16 	*2	# size_queue    
-2	2	*4	# nb_inst_retire
-1	1	*4	# nb_context         
-1	1	*4	# nb_front_end       
-4	4	*4	# nb_ooo_engine
-64 	64 	*2	# nb_packet          
-32	32	+1	# size_general_data  
-2 	2 	+1	# size_special_data  
-18   	16 	*2	# nb_general_register
-8 	8 	+1	# nb_special_register
-1	1	*2	# nb_gpr_write
-1	1	*2	# nb_spr_write
-0	0	*2	# nb_bypass_write 
-0	0	*2	# nb_bypass_memory
-4	4	*2	# size_store_queue
-4	4	*2	# size_load_queue 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration_multi_port_retire4.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration_multi_port_retire4.cfg	(revision 144)
+++ 	(revision )
@@ -1,17 +1,0 @@
-Reservation_station
-4 	16 	*2	# size_queue    
-4	4	*4	# nb_inst_retire
-1	1	*4	# nb_context         
-1	1	*4	# nb_front_end       
-4	4	*4	# nb_ooo_engine
-64 	64 	*2	# nb_packet          
-32	32	+1	# size_general_data  
-2 	2 	+1	# size_special_data  
-16	16	*2	# nb_general_register
-8 	8	+1	# nb_special_register
-1 	1	*2	# nb_gpr_write
-1	1	*2	# nb_spr_write
-0	0	*2	# nb_bypass_write 
-0	0	*2	# nb_bypass_memory
-4	4	*2	# size_store_queue
-4	4	*2	# size_load_queue 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration_multi_port_write.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/configuration_multi_port_write.cfg	(revision 144)
+++ 	(revision )
@@ -1,17 +1,0 @@
-Reservation_station
-1 	16 	*2	# size_queue    
-1	1	*4	# nb_inst_retire
-1	1	*4	# nb_context         
-1	1	*4	# nb_front_end       
-4	4	*4	# nb_ooo_engine
-64 	64 	*2	# nb_packet          
-32	32	+1	# size_general_data  
-2 	2 	+1	# size_special_data  
-16 	16 	*2	# nb_general_register
-8 	8 	+1	# nb_special_register
-2	4	*2	# nb_gpr_write
-2	4	*2	# nb_spr_write
-0	0	*2	# nb_bypass_write 
-0	0	*2	# nb_bypass_memory
-4	4	*2	# size_store_queue
-1	4	*4	# size_load_queue 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,18 +1,0 @@
-Read_unit
-4	8	*2	# size_read_queue         
-4	8	*2	# size_reservation_station
-1	1	*2	# nb_context              
-1	1	*2	# nb_front_end            
-1	4	*4	# nb_ooo_engine           
-64	64	*2 	# nb_packet               
-32	32	*2	# size_general_data       
-2	2	*2	# size_special_data       
-64	64	*2	# nb_general_register     
-16	16	*2	# nb_special_register     
-4	4	*4	# nb_gpr_write            
-4	4	*4	# nb_spr_write            
-4	4	*2	# size_store_queue
-4	4	*4	# size_load_queue         
-4	4	*4	# nb_inst_retire          
-4	4	*4	# nb_bypass_write         
-4	4	*4	# nb_bypass_memory        
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,18 @@
+Read_unit
+4	8	*2	# size_read_queue         
+4	8	*2	# size_reservation_station
+1	1	*2	# nb_context              
+1	1	*2	# nb_front_end            
+1	4	*4	# nb_ooo_engine           
+64	64	*2 	# nb_packet               
+32	32	*2	# size_general_data       
+2	2	*2	# size_special_data       
+64	64	*2	# nb_general_register     
+16	16	*2	# nb_special_register     
+4	4	*4	# nb_gpr_write            
+4	4	*4	# nb_spr_write            
+4	4	*2	# size_store_queue
+4	4	*4	# size_load_queue         
+4	4	*4	# nb_inst_retire          
+4	4	*4	# nb_bypass_write         
+4	4	*4	# nb_bypass_memory        
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,8 +1,0 @@
-Execute_queue
-8	16	*2 # uint32_t size_queue         
-1	1	*2 # uint32_t nb_context         
-1	1	*2 # uint32_t nb_front_end       
-1	4	*2 # uint32_t nb_ooo_engine      
-64	64	*2 # uint32_t nb_packet          
-32	32	*2 # uint32_t size_general_data  
-2	2	*2 # uint32_t size_special_data  
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,8 @@
+Execute_queue
+8	16	*2 # uint32_t size_queue         
+1	1	*2 # uint32_t nb_context         
+1	1	*2 # uint32_t nb_front_end       
+1	4	*2 # uint32_t nb_ooo_engine      
+64	64	*2 # uint32_t nb_packet          
+32	32	*2 # uint32_t size_general_data  
+2	2	*2 # uint32_t size_special_data  
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,13 +1,0 @@
-Write_unit
-8	8	*2 # uint32_t size_write_queue         
-4	4	*2 # uint32_t size_execute_queue         
-1	1	*2 # uint32_t nb_context         
-1	1	*2 # uint32_t nb_front_end       
-1	4	*4 # uint32_t nb_ooo_engine      
-32	32	*2 # uint32_t nb_packet          
-32	32	*2 # uint32_t size_general_data  
-64	64	*2 # uint32_t nb_general_register
-2	2	*2 # uint32_t size_special_data  
-16	16	*2 # uint32_t nb_special_register
-1	8	*2 # uint32_t nb_bypass_write  
-0	1	+1 #          write_queue_scheme
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,13 @@
+Write_unit
+8	8	*2 # uint32_t size_write_queue         
+4	4	*2 # uint32_t size_execute_queue         
+1	1	*2 # uint32_t nb_context         
+1	1	*2 # uint32_t nb_front_end       
+1	4	*4 # uint32_t nb_ooo_engine      
+32	32	*2 # uint32_t nb_packet          
+32	32	*2 # uint32_t size_general_data  
+64	64	*2 # uint32_t nb_general_register
+2	2	*2 # uint32_t size_special_data  
+16	16	*2 # uint32_t nb_special_register
+1	8	*2 # uint32_t nb_bypass_write  
+0	1	+1 #          write_queue_scheme
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/configuration/configuration_execute_queue_null.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/configuration/configuration_execute_queue_null.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/configuration/configuration_execute_queue_null.gen	(revision 145)
@@ -0,0 +1,13 @@
+Write_unit
+8	8	*2 # uint32_t size_write_queue         
+0	0	*2 # uint32_t size_execute_queue         
+1	1	*2 # uint32_t nb_context         
+1	1	*2 # uint32_t nb_front_end       
+1	4	*4 # uint32_t nb_ooo_engine      
+32	32	*2 # uint32_t nb_packet          
+32	32	*2 # uint32_t size_general_data  
+64	64	*2 # uint32_t nb_general_register
+2	2	*2 # uint32_t size_special_data  
+16	16	*2 # uint32_t nb_special_register
+8	8	*2 # uint32_t nb_bypass_write  
+0	1	+1 #          write_queue_scheme
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/configuration_execute_queue_null.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/configuration_execute_queue_null.cfg	(revision 144)
+++ 	(revision )
@@ -1,13 +1,0 @@
-Write_unit
-8	8	*2 # uint32_t size_write_queue         
-0	0	*2 # uint32_t size_execute_queue         
-1	1	*2 # uint32_t nb_context         
-1	1	*2 # uint32_t nb_front_end       
-1	4	*4 # uint32_t nb_ooo_engine      
-32	32	*2 # uint32_t nb_packet          
-32	32	*2 # uint32_t size_general_data  
-64	64	*2 # uint32_t nb_general_register
-2	2	*2 # uint32_t size_special_data  
-16	16	*2 # uint32_t nb_special_register
-8	8	*2 # uint32_t nb_bypass_write  
-0	1	+1 #          write_queue_scheme
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,12 +1,0 @@
-Write_queue
-8	8	*2 # uint32_t              size_queue         
-1	1	*2 # uint32_t              nb_context         
-1	1	*2 # uint32_t              nb_front_end       
-1	4	*2 # uint32_t              nb_ooo_engine      
-32	32	*2 # uint32_t              nb_packet          
-32	32	*2 # uint32_t              size_general_data  
-64	64	*2 # uint32_t              nb_general_register
-2	2	*2 # uint32_t              size_special_data  
-16	16	*2 # uint32_t              nb_special_register
-1	8	*4 # uint32_t              nb_bypass_write  
-0	1	+1 # Twrite_queue_scheme_t queue_scheme
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,12 @@
+Write_queue
+8	8	*2 # uint32_t              size_queue         
+1	1	*2 # uint32_t              nb_context         
+1	1	*2 # uint32_t              nb_front_end       
+1	4	*2 # uint32_t              nb_ooo_engine      
+32	32	*2 # uint32_t              nb_packet          
+32	32	*2 # uint32_t              size_general_data  
+64	64	*2 # uint32_t              nb_general_register
+2	2	*2 # uint32_t              size_special_data  
+16	16	*2 # uint32_t              nb_special_register
+1	8	*4 # uint32_t              nb_bypass_write  
+0	1	+1 # Twrite_queue_scheme_t queue_scheme
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,17 +1,0 @@
-Execution_unit_to_Write_unit
-2	2 	*2	# nb_execute_unit        
-1	1 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
-1	1 	*2	# nb_write_unit           
-1	1	*2	# nb_context             
-1	1	*2	# nb_front_end           
-1	1	*2	# nb_ooo_engine          
-64	64	*2	# nb_packet              
-32	32	*2	# size_general_data      
-2	2	*2	# size_special_data      
-64	64	*2	# nb_general_register    
-16	16	*2	# nb_special_register    
-0	1	+1	# priority
-1	1	+1	# table_routing        [0][0][0]
-1	1	+1	# table_routing        [1][0][0]
-1	1	+1	# table_execute_thread [0][0]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-mono_thread.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-mono_thread.cfg	(revision 144)
+++ 	(revision )
@@ -1,31 +1,0 @@
-Execution_unit_to_Write_unit
-4	4 	*2	# nb_execute_unit        
-1	1 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [2] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [3] [nb_execute_unit]
-3	3 	*2	# nb_write_unit           
-1	1	*2	# nb_context             
-1	1	*2	# nb_front_end           
-1	1	*2	# nb_ooo_engine          
-64	64	*2	# nb_packet              
-32	32	*2	# size_general_data      
-2	2	*2	# size_special_data      
-64	64	*2	# nb_general_register    
-16	16	*2	# nb_special_register    
-0	1	+1	# priority
-1	1	+1	# table_routing [0][0][0]
-0 	0	+1	# table_routing [0][1][0]
-0	0	+1	# table_routing [0][2][0]
-0	0	+1	# table_routing [1][0][0]
-1	1	+1	# table_routing [1][1][0]
-1	1	+1	# table_routing [1][2][0]
-0	0	+1	# table_routing [2][0][0]
-0	0	+1	# table_routing [2][1][0]
-1	1	+1	# table_routing [2][2][0]
-1	1	+1	# table_routing [3][0][0]
-1	1	+1	# table_routing [3][1][0]
-1	1	+1	# table_routing [3][2][0]
-1	1	+1	# table_thread  [0][0]
-1	1	+1	# table_thread  [1][0]
-1	1	+1	# table_thread  [2][0]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-multi_thread-multi_port.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-multi_thread-multi_port.cfg	(revision 144)
+++ 	(revision )
@@ -1,52 +1,0 @@
-Execution_unit_to_Write_unit
-4	4 	*2	# nb_execute_unit        
-2	2 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
-3	3 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [2] [nb_execute_unit]
-2	2 	+1	# nb_execute_unit_port [3] [nb_execute_unit]
-3	3 	*2	# nb_write_unit           
-2	2	*2	# nb_context             
-2	2	*2	# nb_front_end           
-1	1	*2	# nb_ooo_engine          
-64	64	*2	# nb_packet              
-32	32	*2	# size_general_data      
-2	2	*2	# size_special_data      
-64	64	*2	# nb_general_register    
-16	16	*2	# nb_special_register    
-0	1	+1	# priority
-1	1	+1	# table_routing [0][0][0]
-1	1	+1	# table_routing [0][0][1]
-0 	0	+1	# table_routing [0][0][2]
-0 	0	+1	# table_routing [0][1][0]
-1	1	+1	# table_routing [0][1][1]
-0	0	+1	# table_routing [0][1][2]
-0	0	+1	# table_routing [1][0][0]
-1	1	+1	# table_routing [1][0][1]
-0	0	+1	# table_routing [1][0][2]
-1	1	+1	# table_routing [1][1][0]
-1	1	+1	# table_routing [1][1][1]
-1	1	+1	# table_routing [1][1][2]
-1	1	+1	# table_routing [1][2][0]
-1	1	+1	# table_routing [1][2][1]
-1	1	+1	# table_routing [1][2][2]
-0	0	+1	# table_routing [2][0][0]
-0	0	+1	# table_routing [2][0][1]
-1	1	+1	# table_routing [2][0][2]
-1	1	+1	# table_routing [3][0][0]
-1	1	+1	# table_routing [3][0][1]
-1	1	+1	# table_routing [3][0][2]
-1	1	+1	# table_routing [3][1][0]
-1	1	+1	# table_routing [3][1][1]
-1	1	+1	# table_routing [3][1][2]
-1	1	+1	# table_thread  [0][0]
-0	0	+1	# table_thread  [0][1]
-0	0	+1	# table_thread  [0][2]
-0	0	+1	# table_thread  [0][3]
-0	0	+1	# table_thread  [1][0]
-1	1	+1	# table_thread  [1][1]
-1	1	+1	# table_thread  [1][2]
-0	0	+1	# table_thread  [1][3]
-0	0	+1	# table_thread  [2][0]
-0	0	+1	# table_thread  [2][1]
-0	0	+1	# table_thread  [2][2]
-1	1	+1	# table_thread  [2][3]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-multi_thread.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-multi_thread.cfg	(revision 144)
+++ 	(revision )
@@ -1,40 +1,0 @@
-Execution_unit_to_Write_unit
-4	4 	*2	# nb_execute_unit        
-1	1 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [2] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [3] [nb_execute_unit]
-3	3 	*2	# nb_write_unit           
-2	2	*2	# nb_context             
-2	2	*2	# nb_front_end           
-1	1	*2	# nb_ooo_engine          
-64	64	*2	# nb_packet              
-32	32	*2	# size_general_data      
-2	2	*2	# size_special_data      
-64	64	*2	# nb_general_register    
-16	16	*2	# nb_special_register    
-0	1	+1	# priority
-1	1	+1	# table_routing [0][0][0]
-0 	0	+1	# table_routing [0][1][0]
-0	0	+1	# table_routing [0][2][0]
-0	0	+1	# table_routing [1][0][0]
-1	1	+1	# table_routing [1][1][0]
-1	1	+1	# table_routing [1][2][0]
-0	0	+1	# table_routing [2][0][0]
-0	0	+1	# table_routing [2][1][0]
-1	1	+1	# table_routing [2][2][0]
-1	1	+1	# table_routing [3][0][0]
-1	1	+1	# table_routing [3][1][0]
-1	1	+1	# table_routing [3][2][0]
-1	1	+1	# table_thread  [0][0]
-0	0	+1	# table_thread  [0][1]
-0	0	+1	# table_thread  [0][2]
-0	0	+1	# table_thread  [0][3]
-0	0	+1	# table_thread  [1][0]
-1	1	+1	# table_thread  [1][1]
-1	1	+1	# table_thread  [1][2]
-0	0	+1	# table_thread  [1][3]
-0	0	+1	# table_thread  [2][0]
-0	0	+1	# table_thread  [2][1]
-0	0	+1	# table_thread  [2][2]
-1	1	+1	# table_thread  [2][3]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,17 @@
+Execution_unit_to_Write_unit
+2	2 	*2	# nb_execute_unit        
+1	1 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
+1	1 	*2	# nb_write_unit           
+1	1	*2	# nb_context             
+1	1	*2	# nb_front_end           
+1	1	*2	# nb_ooo_engine          
+64	64	*2	# nb_packet              
+32	32	*2	# size_general_data      
+2	2	*2	# size_special_data      
+64	64	*2	# nb_general_register    
+16	16	*2	# nb_special_register    
+0	1	+1	# priority
+1	1	+1	# table_routing        [0][0][0]
+1	1	+1	# table_routing        [1][0][0]
+1	1	+1	# table_execute_thread [0][0]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/configuration/config_multi_execute-mono_thread.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/configuration/config_multi_execute-mono_thread.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/configuration/config_multi_execute-mono_thread.gen	(revision 145)
@@ -0,0 +1,31 @@
+Execution_unit_to_Write_unit
+4	4 	*2	# nb_execute_unit        
+1	1 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [2] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [3] [nb_execute_unit]
+3	3 	*2	# nb_write_unit           
+1	1	*2	# nb_context             
+1	1	*2	# nb_front_end           
+1	1	*2	# nb_ooo_engine          
+64	64	*2	# nb_packet              
+32	32	*2	# size_general_data      
+2	2	*2	# size_special_data      
+64	64	*2	# nb_general_register    
+16	16	*2	# nb_special_register    
+0	1	+1	# priority
+1	1	+1	# table_routing [0][0][0]
+0 	0	+1	# table_routing [0][1][0]
+0	0	+1	# table_routing [0][2][0]
+0	0	+1	# table_routing [1][0][0]
+1	1	+1	# table_routing [1][1][0]
+1	1	+1	# table_routing [1][2][0]
+0	0	+1	# table_routing [2][0][0]
+0	0	+1	# table_routing [2][1][0]
+1	1	+1	# table_routing [2][2][0]
+1	1	+1	# table_routing [3][0][0]
+1	1	+1	# table_routing [3][1][0]
+1	1	+1	# table_routing [3][2][0]
+1	1	+1	# table_thread  [0][0]
+1	1	+1	# table_thread  [1][0]
+1	1	+1	# table_thread  [2][0]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/configuration/config_multi_execute-multi_thread-multi_port.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/configuration/config_multi_execute-multi_thread-multi_port.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/configuration/config_multi_execute-multi_thread-multi_port.gen	(revision 145)
@@ -0,0 +1,52 @@
+Execution_unit_to_Write_unit
+4	4 	*2	# nb_execute_unit        
+2	2 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
+3	3 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [2] [nb_execute_unit]
+2	2 	+1	# nb_execute_unit_port [3] [nb_execute_unit]
+3	3 	*2	# nb_write_unit           
+2	2	*2	# nb_context             
+2	2	*2	# nb_front_end           
+1	1	*2	# nb_ooo_engine          
+64	64	*2	# nb_packet              
+32	32	*2	# size_general_data      
+2	2	*2	# size_special_data      
+64	64	*2	# nb_general_register    
+16	16	*2	# nb_special_register    
+0	1	+1	# priority
+1	1	+1	# table_routing [0][0][0]
+1	1	+1	# table_routing [0][0][1]
+0 	0	+1	# table_routing [0][0][2]
+0 	0	+1	# table_routing [0][1][0]
+1	1	+1	# table_routing [0][1][1]
+0	0	+1	# table_routing [0][1][2]
+0	0	+1	# table_routing [1][0][0]
+1	1	+1	# table_routing [1][0][1]
+0	0	+1	# table_routing [1][0][2]
+1	1	+1	# table_routing [1][1][0]
+1	1	+1	# table_routing [1][1][1]
+1	1	+1	# table_routing [1][1][2]
+1	1	+1	# table_routing [1][2][0]
+1	1	+1	# table_routing [1][2][1]
+1	1	+1	# table_routing [1][2][2]
+0	0	+1	# table_routing [2][0][0]
+0	0	+1	# table_routing [2][0][1]
+1	1	+1	# table_routing [2][0][2]
+1	1	+1	# table_routing [3][0][0]
+1	1	+1	# table_routing [3][0][1]
+1	1	+1	# table_routing [3][0][2]
+1	1	+1	# table_routing [3][1][0]
+1	1	+1	# table_routing [3][1][1]
+1	1	+1	# table_routing [3][1][2]
+1	1	+1	# table_thread  [0][0]
+0	0	+1	# table_thread  [0][1]
+0	0	+1	# table_thread  [0][2]
+0	0	+1	# table_thread  [0][3]
+0	0	+1	# table_thread  [1][0]
+1	1	+1	# table_thread  [1][1]
+1	1	+1	# table_thread  [1][2]
+0	0	+1	# table_thread  [1][3]
+0	0	+1	# table_thread  [2][0]
+0	0	+1	# table_thread  [2][1]
+0	0	+1	# table_thread  [2][2]
+1	1	+1	# table_thread  [2][3]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/configuration/config_multi_execute-multi_thread.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/configuration/config_multi_execute-multi_thread.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/configuration/config_multi_execute-multi_thread.gen	(revision 145)
@@ -0,0 +1,40 @@
+Execution_unit_to_Write_unit
+4	4 	*2	# nb_execute_unit        
+1	1 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [2] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [3] [nb_execute_unit]
+3	3 	*2	# nb_write_unit           
+2	2	*2	# nb_context             
+2	2	*2	# nb_front_end           
+1	1	*2	# nb_ooo_engine          
+64	64	*2	# nb_packet              
+32	32	*2	# size_general_data      
+2	2	*2	# size_special_data      
+64	64	*2	# nb_general_register    
+16	16	*2	# nb_special_register    
+0	1	+1	# priority
+1	1	+1	# table_routing [0][0][0]
+0 	0	+1	# table_routing [0][1][0]
+0	0	+1	# table_routing [0][2][0]
+0	0	+1	# table_routing [1][0][0]
+1	1	+1	# table_routing [1][1][0]
+1	1	+1	# table_routing [1][2][0]
+0	0	+1	# table_routing [2][0][0]
+0	0	+1	# table_routing [2][1][0]
+1	1	+1	# table_routing [2][2][0]
+1	1	+1	# table_routing [3][0][0]
+1	1	+1	# table_routing [3][1][0]
+1	1	+1	# table_routing [3][2][0]
+1	1	+1	# table_thread  [0][0]
+0	0	+1	# table_thread  [0][1]
+0	0	+1	# table_thread  [0][2]
+0	0	+1	# table_thread  [0][3]
+0	0	+1	# table_thread  [1][0]
+1	1	+1	# table_thread  [1][1]
+1	1	+1	# table_thread  [1][2]
+0	0	+1	# table_thread  [1][3]
+0	0	+1	# table_thread  [2][0]
+0	0	+1	# table_thread  [2][1]
+0	0	+1	# table_thread  [2][2]
+1	1	+1	# table_thread  [2][3]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,45 +1,0 @@
-Read_unit_to_Execution_unit
-1	1 	*2	# nb_read_unit           
-1	1 	+1	# nb_read_unit_port    [0] [nb_read_unit]
-2	2 	*2	# nb_execute_unit
-1	1 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
-1	1	*2	# nb_context             
-1	1	*2	# nb_front_end           
-1	1	*2	# nb_ooo_engine          
-64	64	*2	# nb_packet              
-32	32	*2	# size_general_data      
-2	2	*2	# size_special_data      
-64	64	*2	# nb_general_register    
-16	16	*2	# nb_special_register    
-4	4	*2	# size_store_queue       
-4	4	*2	# size_load_queue        
-0	1	+1	# priority
-1	1	+1	# table_routing        [0][0][0]
-1	1	+1	# table_routing        [0][1][0]
-0	0	+1	# table_execute_type   [0][TYPE_ALU    ]
-0	0	+1	# table_execute_type   [0][TYPE_SHIFT  ]
-0	0	+1	# table_execute_type   [0][TYPE_MOVE   ]
-0	0	+1	# table_execute_type   [0][TYPE_TEST   ]
-0	0	+1	# table_execute_type   [0][TYPE_MUL    ]
-0	0	+1	# table_execute_type   [0][TYPE_DIV    ]
-0	0	+1	# table_execute_type   [0][TYPE_EXTEND ]
-0	0	+1	# table_execute_type   [0][TYPE_FIND   ]
-0	0	+1	# table_execute_type   [0][TYPE_SPECIAL]
-0	0	+1	# table_execute_type   [0][TYPE_CUSTOM ]
-0	0	+1	# table_execute_type   [0][TYPE_BRANCH ]
-1	1	+1	# table_execute_type   [0][TYPE_MEMORY ]
-1	1	+1	# table_execute_type   [1][TYPE_ALU    ]
-1	1	+1	# table_execute_type   [1][TYPE_SHIFT  ]
-1	1	+1	# table_execute_type   [1][TYPE_MOVE   ]
-1	1	+1	# table_execute_type   [1][TYPE_TEST   ]
-1	1	+1	# table_execute_type   [1][TYPE_MUL    ]
-1	1	+1	# table_execute_type   [1][TYPE_DIV    ]
-1	1	+1	# table_execute_type   [1][TYPE_EXTEND ]
-1	1	+1	# table_execute_type   [1][TYPE_FIND   ]
-1	1	+1	# table_execute_type   [1][TYPE_SPECIAL]
-1	1	+1	# table_execute_type   [1][TYPE_CUSTOM ]
-1	1	+1	# table_execute_type   [1][TYPE_BRANCH ]
-0	0	+1	# table_execute_type   [1][TYPE_MEMORY ]
-1	1	+1	# table_execute_thread [0][0]
-1	1	+1	# table_execute_thread [1][0]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-mono_thread-multi_lsq.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-mono_thread-multi_lsq.cfg	(revision 144)
+++ 	(revision )
@@ -1,105 +1,0 @@
-Read_unit_to_Execution_unit
-3	3 	*2	# nb_read_unit           
-2	2 	+1	# nb_read_unit_port    [0] [nb_read_unit]
-3	3 	+1	# nb_read_unit_port    [1] [nb_read_unit]
-1	1 	+1	# nb_read_unit_port    [2] [nb_read_unit]
-5	5 	*2	# nb_execute_unit
-2	2 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [2] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [3] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [4] [nb_execute_unit]
-1	1	*2	# nb_context             
-1	1	*2	# nb_front_end           
-1	1	*2	# nb_ooo_engine          
-64	64	*2	# nb_packet              
-32	32	*2	# size_general_data      
-2	2	*2	# size_special_data      
-64	64	*2	# nb_general_register    
-16	16	*2	# nb_special_register    
-4	4	*2	# size_store_queue       
-1	4	*4	# size_load_queue        
-0	1	+1	# priority
-1	1	+1	# table_routing        [0][0][0]
-1	1	+1	# table_routing        [0][0][0]
-0	0	+1	# table_routing        [0][1][0]
-0	0	+1	# table_routing        [0][2][0]
-0	0	+1	# table_routing        [0][3][0]
-0	0	+1	# table_routing        [0][4][0]
-0 	0	+1	# table_routing        [1][0][0]
-0 	0	+1	# table_routing        [1][0][1]
-1	1	+1	# table_routing        [1][1][0]
-1	1	+1	# table_routing        [1][2][0]
-0	0	+1	# table_routing        [1][3][0]
-0	0	+1	# table_routing        [1][4][0]
-0	0	+1	# table_routing        [2][0][0]
-1	1	+1	# table_routing        [2][0][1]
-0	0	+1	# table_routing        [2][1][0]
-1	1	+1	# table_routing        [2][2][0]
-1	1	+1	# table_routing        [2][3][0]
-1	1	+1	# table_routing        [2][4][0]
-0	0	+1	# table_execute_type   [0][TYPE_ALU    ]
-0	0	+1	# table_execute_type   [0][TYPE_SHIFT  ]
-0	0	+1	# table_execute_type   [0][TYPE_MOVE   ]
-0	0	+1	# table_execute_type   [0][TYPE_TEST   ]
-0	0	+1	# table_execute_type   [0][TYPE_MUL    ]
-0	0	+1	# table_execute_type   [0][TYPE_DIV    ]
-0	0	+1	# table_execute_type   [0][TYPE_EXTEND ]
-0	0	+1	# table_execute_type   [0][TYPE_FIND   ]
-0	0	+1	# table_execute_type   [0][TYPE_SPECIAL]
-0	0	+1	# table_execute_type   [0][TYPE_CUSTOM ]
-0	0	+1	# table_execute_type   [0][TYPE_BRANCH ]
-1	1	+1	# table_execute_type   [0][TYPE_MEMORY ]
-1	1	+1	# table_execute_type   [1][TYPE_ALU    ]
-1	1	+1	# table_execute_type   [1][TYPE_SHIFT  ]
-1	1	+1	# table_execute_type   [1][TYPE_MOVE   ]
-1	1	+1	# table_execute_type   [1][TYPE_TEST   ]
-1	1	+1	# table_execute_type   [1][TYPE_MUL    ]
-1	1	+1	# table_execute_type   [1][TYPE_DIV    ]
-1	1	+1	# table_execute_type   [1][TYPE_EXTEND ]
-1	1	+1	# table_execute_type   [1][TYPE_FIND   ]
-1	1	+1	# table_execute_type   [1][TYPE_SPECIAL]
-1	1	+1	# table_execute_type   [1][TYPE_CUSTOM ]
-1	1	+1	# table_execute_type   [1][TYPE_BRANCH ]
-0	0	+1	# table_execute_type   [1][TYPE_MEMORY ]
-1	1	+1	# table_execute_type   [2][TYPE_ALU    ]
-0	0	+1	# table_execute_type   [2][TYPE_SHIFT  ]
-0	0	+1	# table_execute_type   [2][TYPE_MOVE   ]
-0	0	+1	# table_execute_type   [2][TYPE_TEST   ]
-0	0	+1	# table_execute_type   [2][TYPE_MUL    ]
-0	0	+1	# table_execute_type   [2][TYPE_DIV    ]
-0	0	+1	# table_execute_type   [2][TYPE_EXTEND ]
-0	0	+1	# table_execute_type   [2][TYPE_FIND   ]
-0	0	+1	# table_execute_type   [2][TYPE_SPECIAL]
-0	0	+1	# table_execute_type   [2][TYPE_CUSTOM ]
-1	1	+1	# table_execute_type   [2][TYPE_BRANCH ]
-0	0	+1	# table_execute_type   [2][TYPE_MEMORY ]
-1	1	+1	# table_execute_type   [3][TYPE_ALU    ]
-1	1	+1	# table_execute_type   [3][TYPE_SHIFT  ]
-1	1	+1	# table_execute_type   [3][TYPE_MOVE   ]
-1	1	+1	# table_execute_type   [3][TYPE_TEST   ]
-0	0	+1	# table_execute_type   [3][TYPE_MUL    ]
-0	0	+1	# table_execute_type   [3][TYPE_DIV    ]
-1	1	+1	# table_execute_type   [3][TYPE_EXTEND ]
-1	1	+1	# table_execute_type   [3][TYPE_FIND   ]
-0	0	+1	# table_execute_type   [3][TYPE_SPECIAL]
-0	0	+1	# table_execute_type   [3][TYPE_CUSTOM ]
-1	1	+1	# table_execute_type   [3][TYPE_BRANCH ]
-0	0	+1	# table_execute_type   [3][TYPE_MEMORY ]
-0	0	+1	# table_execute_type   [4][TYPE_ALU    ]
-1	1	+1	# table_execute_type   [4][TYPE_SHIFT  ]
-1	1	+1	# table_execute_type   [4][TYPE_MOVE   ]
-0	0	+1	# table_execute_type   [4][TYPE_TEST   ]
-1	1	+1	# table_execute_type   [4][TYPE_MUL    ]
-1	1	+1	# table_execute_type   [4][TYPE_DIV    ]
-0	0	+1	# table_execute_type   [4][TYPE_EXTEND ]
-0	0	+1	# table_execute_type   [4][TYPE_FIND   ]
-0	0	+1	# table_execute_type   [4][TYPE_SPECIAL]
-0	0	+1	# table_execute_type   [4][TYPE_CUSTOM ]
-0	0	+1	# table_execute_type   [4][TYPE_BRANCH ]
-0	0	+1	# table_execute_type   [4][TYPE_MEMORY ]
-1	1	+1	# table_execute_thread [0][0]
-1	1	+1	# table_execute_thread [1][0]
-1	1	+1	# table_execute_thread [2][0]
-1	1	+1	# table_execute_thread [3][0]
-1	1	+1	# table_execute_thread [4][0]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-mono_thread.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-mono_thread.cfg	(revision 144)
+++ 	(revision )
@@ -1,85 +1,0 @@
-Read_unit_to_Execution_unit
-3	3 	*2	# nb_read_unit           
-1	1 	+1	# nb_read_unit_port    [0] [nb_read_unit]
-2	2 	+1	# nb_read_unit_port    [1] [nb_read_unit]
-4	4 	+1	# nb_read_unit_port    [2] [nb_read_unit]
-4	4 	*2	# nb_execute_unit        
-1	1 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [2] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [3] [nb_execute_unit]
-1	1	*2	# nb_context             
-1	1	*2	# nb_front_end           
-1	1	*2	# nb_ooo_engine          
-64	64	*2	# nb_packet              
-32	32	*2	# size_general_data      
-2	2	*2	# size_special_data      
-64	64	*2	# nb_general_register    
-16	16	*2	# nb_special_register    
-4	4	*2	# size_store_queue       
-1	4	*4	# size_load_queue        
-0	1	+1	# priority
-1	1	+1	# table_routing        [0][0][0]
-0	0	+1	# table_routing        [0][1][0]
-0	0	+1	# table_routing        [0][2][0]
-0	0	+1	# table_routing        [0][3][0]
-0 	0	+1	# table_routing        [1][0][0]
-1	1	+1	# table_routing        [1][1][0]
-1	1	+1	# table_routing        [1][2][0]
-0	0	+1	# table_routing        [1][3][0]
-0	0	+1	# table_routing        [2][0][0]
-0	0	+1	# table_routing        [2][1][0]
-1	1	+1	# table_routing        [2][2][0]
-1	1	+1	# table_routing        [2][3][0]
-0	0	+1	# table_execute_type   [0][TYPE_ALU    ]
-0	0	+1	# table_execute_type   [0][TYPE_SHIFT  ]
-0	0	+1	# table_execute_type   [0][TYPE_MOVE   ]
-0	0	+1	# table_execute_type   [0][TYPE_TEST   ]
-0	0	+1	# table_execute_type   [0][TYPE_MUL    ]
-0	0	+1	# table_execute_type   [0][TYPE_DIV    ]
-0	0	+1	# table_execute_type   [0][TYPE_EXTEND ]
-0	0	+1	# table_execute_type   [0][TYPE_FIND   ]
-0	0	+1	# table_execute_type   [0][TYPE_SPECIAL]
-0	0	+1	# table_execute_type   [0][TYPE_CUSTOM ]
-0	0	+1	# table_execute_type   [0][TYPE_BRANCH ]
-1	1	+1	# table_execute_type   [0][TYPE_MEMORY ]
-1	1	+1	# table_execute_type   [1][TYPE_ALU    ]
-1	1	+1	# table_execute_type   [1][TYPE_SHIFT  ]
-1	1	+1	# table_execute_type   [1][TYPE_MOVE   ]
-1	1	+1	# table_execute_type   [1][TYPE_TEST   ]
-1	1	+1	# table_execute_type   [1][TYPE_MUL    ]
-1	1	+1	# table_execute_type   [1][TYPE_DIV    ]
-1	1	+1	# table_execute_type   [1][TYPE_EXTEND ]
-1	1	+1	# table_execute_type   [1][TYPE_FIND   ]
-1	1	+1	# table_execute_type   [1][TYPE_SPECIAL]
-1	1	+1	# table_execute_type   [1][TYPE_CUSTOM ]
-1	1	+1	# table_execute_type   [1][TYPE_BRANCH ]
-0	0	+1	# table_execute_type   [1][TYPE_MEMORY ]
-1	1	+1	# table_execute_type   [2][TYPE_ALU    ]
-0	0	+1	# table_execute_type   [2][TYPE_SHIFT  ]
-0	0	+1	# table_execute_type   [2][TYPE_MOVE   ]
-0	0	+1	# table_execute_type   [2][TYPE_TEST   ]
-0	0	+1	# table_execute_type   [2][TYPE_MUL    ]
-0	0	+1	# table_execute_type   [2][TYPE_DIV    ]
-0	0	+1	# table_execute_type   [2][TYPE_EXTEND ]
-0	0	+1	# table_execute_type   [2][TYPE_FIND   ]
-0	0	+1	# table_execute_type   [2][TYPE_SPECIAL]
-0	0	+1	# table_execute_type   [2][TYPE_CUSTOM ]
-1	1	+1	# table_execute_type   [2][TYPE_BRANCH ]
-0	0	+1	# table_execute_type   [2][TYPE_MEMORY ]
-1	1	+1	# table_execute_type   [3][TYPE_ALU    ]
-1	1	+1	# table_execute_type   [3][TYPE_SHIFT  ]
-1	1	+1	# table_execute_type   [3][TYPE_MOVE   ]
-1	1	+1	# table_execute_type   [3][TYPE_TEST   ]
-0	0	+1	# table_execute_type   [3][TYPE_MUL    ]
-0	0	+1	# table_execute_type   [3][TYPE_DIV    ]
-1	1	+1	# table_execute_type   [3][TYPE_EXTEND ]
-1	1	+1	# table_execute_type   [3][TYPE_FIND   ]
-0	0	+1	# table_execute_type   [3][TYPE_SPECIAL]
-0	0	+1	# table_execute_type   [3][TYPE_CUSTOM ]
-1	1	+1	# table_execute_type   [3][TYPE_BRANCH ]
-0	0	+1	# table_execute_type   [3][TYPE_MEMORY ]
-1	1	+1	# table_execute_thread [0][0]
-1	1	+1	# table_execute_thread [1][0]
-1	1	+1	# table_execute_thread [2][0]
-1	1	+1	# table_execute_thread [3][0]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-multi_thread.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-multi_thread.cfg	(revision 144)
+++ 	(revision )
@@ -1,97 +1,0 @@
-Read_unit_to_Execution_unit
-3	3 	*2	# nb_read_unit           
-1	1 	+1	# nb_read_unit_port    [0] [nb_read_unit]
-1	1 	+1	# nb_read_unit_port    [1] [nb_read_unit]
-1	1 	+1	# nb_read_unit_port    [2] [nb_read_unit]
-4	4 	*2	# nb_execute_unit        
-1	1 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [2] [nb_execute_unit]
-1	1 	+1	# nb_execute_unit_port [3] [nb_execute_unit]
-4	4	*2	# nb_context             
-1	1	*2	# nb_front_end           
-1	1	*2	# nb_ooo_engine          
-64	64	*2	# nb_packet              
-32	32	*2	# size_general_data      
-2	2	*2	# size_special_data      
-64	64	*2	# nb_general_register    
-16	16	*2	# nb_special_register    
-4	4	*2	# size_store_queue       
-4	4	*2	# size_load_queue        
-0	1	+1	# priority
-1	1	+1	# table_routing        [0][0][0]
-0	0	+1	# table_routing        [0][1][0]
-0	0	+1	# table_routing        [0][2][0]
-0	0	+1	# table_routing        [0][3][0]
-0 	0	+1	# table_routing        [1][0][0]
-1	1	+1	# table_routing        [1][1][0]
-1	1	+1	# table_routing        [1][2][0]
-0	0	+1	# table_routing        [1][3][0]
-0	0	+1	# table_routing        [2][0][0]
-0	0	+1	# table_routing        [2][1][0]
-1	1	+1	# table_routing        [2][2][0]
-1	1	+1	# table_routing        [2][3][0]
-0	0	+1	# table_execute_type   [0][TYPE_ALU    ]
-0	0	+1	# table_execute_type   [0][TYPE_SHIFT  ]
-0	0	+1	# table_execute_type   [0][TYPE_MOVE   ]
-0	0	+1	# table_execute_type   [0][TYPE_TEST   ]
-0	0	+1	# table_execute_type   [0][TYPE_MUL    ]
-0	0	+1	# table_execute_type   [0][TYPE_DIV    ]
-0	0	+1	# table_execute_type   [0][TYPE_EXTEND ]
-0	0	+1	# table_execute_type   [0][TYPE_FIND   ]
-0	0	+1	# table_execute_type   [0][TYPE_SPECIAL]
-0	0	+1	# table_execute_type   [0][TYPE_CUSTOM ]
-0	0	+1	# table_execute_type   [0][TYPE_BRANCH ]
-1	1	+1	# table_execute_type   [0][TYPE_MEMORY ]
-1	1	+1	# table_execute_type   [1][TYPE_ALU    ]
-1	1	+1	# table_execute_type   [1][TYPE_SHIFT  ]
-1	1	+1	# table_execute_type   [1][TYPE_MOVE   ]
-1	1	+1	# table_execute_type   [1][TYPE_TEST   ]
-1	1	+1	# table_execute_type   [1][TYPE_MUL    ]
-1	1	+1	# table_execute_type   [1][TYPE_DIV    ]
-1	1	+1	# table_execute_type   [1][TYPE_EXTEND ]
-1	1	+1	# table_execute_type   [1][TYPE_FIND   ]
-1	1	+1	# table_execute_type   [1][TYPE_SPECIAL]
-1	1	+1	# table_execute_type   [1][TYPE_CUSTOM ]
-1	1	+1	# table_execute_type   [1][TYPE_BRANCH ]
-0	0	+1	# table_execute_type   [1][TYPE_MEMORY ]
-1	1	+1	# table_execute_type   [2][TYPE_ALU    ]
-0	0	+1	# table_execute_type   [2][TYPE_SHIFT  ]
-0	0	+1	# table_execute_type   [2][TYPE_MOVE   ]
-0	0	+1	# table_execute_type   [2][TYPE_TEST   ]
-0	0	+1	# table_execute_type   [2][TYPE_MUL    ]
-0	0	+1	# table_execute_type   [2][TYPE_DIV    ]
-0	0	+1	# table_execute_type   [2][TYPE_EXTEND ]
-0	0	+1	# table_execute_type   [2][TYPE_FIND   ]
-0	0	+1	# table_execute_type   [2][TYPE_SPECIAL]
-0	0	+1	# table_execute_type   [2][TYPE_CUSTOM ]
-1	1	+1	# table_execute_type   [2][TYPE_BRANCH ]
-0	0	+1	# table_execute_type   [2][TYPE_MEMORY ]
-1	1	+1	# table_execute_type   [3][TYPE_ALU    ]
-1	1	+1	# table_execute_type   [3][TYPE_SHIFT  ]
-1	1	+1	# table_execute_type   [3][TYPE_MOVE   ]
-1	1	+1	# table_execute_type   [3][TYPE_TEST   ]
-1	1	+1	# table_execute_type   [3][TYPE_MUL    ]
-1	1	+1	# table_execute_type   [3][TYPE_DIV    ]
-0	0	+1	# table_execute_type   [3][TYPE_EXTEND ]
-0	0	+1	# table_execute_type   [3][TYPE_FIND   ]
-1	1	+1	# table_execute_type   [3][TYPE_SPECIAL]
-0	0	+1	# table_execute_type   [3][TYPE_CUSTOM ]
-1	1	+1	# table_execute_type   [3][TYPE_BRANCH ]
-0	0	+1	# table_execute_type   [3][TYPE_MEMORY ]
-1	1	+1	# table_execute_thread [0][0]
-1	1	+1	# table_execute_thread [0][1]
-1	1	+1	# table_execute_thread [0][2]
-1	1	+1	# table_execute_thread [0][3]
-1	1	+1	# table_execute_thread [1][0]
-1	1	+1	# table_execute_thread [1][1]
-1	1	+1	# table_execute_thread [1][2]
-0	0	+1	# table_execute_thread [1][3]
-0	0	+1	# table_execute_thread [2][0]
-1	1	+1	# table_execute_thread [2][1]
-1	1	+1	# table_execute_thread [2][2]
-0	0	+1	# table_execute_thread [2][3]
-0	0	+1	# table_execute_thread [3][0]
-0	0	+1	# table_execute_thread [3][1]
-0	0	+1	# table_execute_thread [3][2]
-1	1	+1	# table_execute_thread [3][3]	
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,45 @@
+Read_unit_to_Execution_unit
+1	1 	*2	# nb_read_unit           
+1	1 	+1	# nb_read_unit_port    [0] [nb_read_unit]
+2	2 	*2	# nb_execute_unit
+1	1 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
+1	1	*2	# nb_context             
+1	1	*2	# nb_front_end           
+1	1	*2	# nb_ooo_engine          
+64	64	*2	# nb_packet              
+32	32	*2	# size_general_data      
+2	2	*2	# size_special_data      
+64	64	*2	# nb_general_register    
+16	16	*2	# nb_special_register    
+4	4	*2	# size_store_queue       
+4	4	*2	# size_load_queue        
+0	1	+1	# priority
+1	1	+1	# table_routing        [0][0][0]
+1	1	+1	# table_routing        [0][1][0]
+0	0	+1	# table_execute_type   [0][TYPE_ALU    ]
+0	0	+1	# table_execute_type   [0][TYPE_SHIFT  ]
+0	0	+1	# table_execute_type   [0][TYPE_MOVE   ]
+0	0	+1	# table_execute_type   [0][TYPE_TEST   ]
+0	0	+1	# table_execute_type   [0][TYPE_MUL    ]
+0	0	+1	# table_execute_type   [0][TYPE_DIV    ]
+0	0	+1	# table_execute_type   [0][TYPE_EXTEND ]
+0	0	+1	# table_execute_type   [0][TYPE_FIND   ]
+0	0	+1	# table_execute_type   [0][TYPE_SPECIAL]
+0	0	+1	# table_execute_type   [0][TYPE_CUSTOM ]
+0	0	+1	# table_execute_type   [0][TYPE_BRANCH ]
+1	1	+1	# table_execute_type   [0][TYPE_MEMORY ]
+1	1	+1	# table_execute_type   [1][TYPE_ALU    ]
+1	1	+1	# table_execute_type   [1][TYPE_SHIFT  ]
+1	1	+1	# table_execute_type   [1][TYPE_MOVE   ]
+1	1	+1	# table_execute_type   [1][TYPE_TEST   ]
+1	1	+1	# table_execute_type   [1][TYPE_MUL    ]
+1	1	+1	# table_execute_type   [1][TYPE_DIV    ]
+1	1	+1	# table_execute_type   [1][TYPE_EXTEND ]
+1	1	+1	# table_execute_type   [1][TYPE_FIND   ]
+1	1	+1	# table_execute_type   [1][TYPE_SPECIAL]
+1	1	+1	# table_execute_type   [1][TYPE_CUSTOM ]
+1	1	+1	# table_execute_type   [1][TYPE_BRANCH ]
+0	0	+1	# table_execute_type   [1][TYPE_MEMORY ]
+1	1	+1	# table_execute_thread [0][0]
+1	1	+1	# table_execute_thread [1][0]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/configuration/config_multi_execute-mono_thread-multi_lsq.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/configuration/config_multi_execute-mono_thread-multi_lsq.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/configuration/config_multi_execute-mono_thread-multi_lsq.gen	(revision 145)
@@ -0,0 +1,105 @@
+Read_unit_to_Execution_unit
+3	3 	*2	# nb_read_unit           
+2	2 	+1	# nb_read_unit_port    [0] [nb_read_unit]
+3	3 	+1	# nb_read_unit_port    [1] [nb_read_unit]
+1	1 	+1	# nb_read_unit_port    [2] [nb_read_unit]
+5	5 	*2	# nb_execute_unit
+2	2 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [2] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [3] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [4] [nb_execute_unit]
+1	1	*2	# nb_context             
+1	1	*2	# nb_front_end           
+1	1	*2	# nb_ooo_engine          
+64	64	*2	# nb_packet              
+32	32	*2	# size_general_data      
+2	2	*2	# size_special_data      
+64	64	*2	# nb_general_register    
+16	16	*2	# nb_special_register    
+4	4	*2	# size_store_queue       
+1	4	*4	# size_load_queue        
+0	1	+1	# priority
+1	1	+1	# table_routing        [0][0][0]
+1	1	+1	# table_routing        [0][0][0]
+0	0	+1	# table_routing        [0][1][0]
+0	0	+1	# table_routing        [0][2][0]
+0	0	+1	# table_routing        [0][3][0]
+0	0	+1	# table_routing        [0][4][0]
+0 	0	+1	# table_routing        [1][0][0]
+0 	0	+1	# table_routing        [1][0][1]
+1	1	+1	# table_routing        [1][1][0]
+1	1	+1	# table_routing        [1][2][0]
+0	0	+1	# table_routing        [1][3][0]
+0	0	+1	# table_routing        [1][4][0]
+0	0	+1	# table_routing        [2][0][0]
+1	1	+1	# table_routing        [2][0][1]
+0	0	+1	# table_routing        [2][1][0]
+1	1	+1	# table_routing        [2][2][0]
+1	1	+1	# table_routing        [2][3][0]
+1	1	+1	# table_routing        [2][4][0]
+0	0	+1	# table_execute_type   [0][TYPE_ALU    ]
+0	0	+1	# table_execute_type   [0][TYPE_SHIFT  ]
+0	0	+1	# table_execute_type   [0][TYPE_MOVE   ]
+0	0	+1	# table_execute_type   [0][TYPE_TEST   ]
+0	0	+1	# table_execute_type   [0][TYPE_MUL    ]
+0	0	+1	# table_execute_type   [0][TYPE_DIV    ]
+0	0	+1	# table_execute_type   [0][TYPE_EXTEND ]
+0	0	+1	# table_execute_type   [0][TYPE_FIND   ]
+0	0	+1	# table_execute_type   [0][TYPE_SPECIAL]
+0	0	+1	# table_execute_type   [0][TYPE_CUSTOM ]
+0	0	+1	# table_execute_type   [0][TYPE_BRANCH ]
+1	1	+1	# table_execute_type   [0][TYPE_MEMORY ]
+1	1	+1	# table_execute_type   [1][TYPE_ALU    ]
+1	1	+1	# table_execute_type   [1][TYPE_SHIFT  ]
+1	1	+1	# table_execute_type   [1][TYPE_MOVE   ]
+1	1	+1	# table_execute_type   [1][TYPE_TEST   ]
+1	1	+1	# table_execute_type   [1][TYPE_MUL    ]
+1	1	+1	# table_execute_type   [1][TYPE_DIV    ]
+1	1	+1	# table_execute_type   [1][TYPE_EXTEND ]
+1	1	+1	# table_execute_type   [1][TYPE_FIND   ]
+1	1	+1	# table_execute_type   [1][TYPE_SPECIAL]
+1	1	+1	# table_execute_type   [1][TYPE_CUSTOM ]
+1	1	+1	# table_execute_type   [1][TYPE_BRANCH ]
+0	0	+1	# table_execute_type   [1][TYPE_MEMORY ]
+1	1	+1	# table_execute_type   [2][TYPE_ALU    ]
+0	0	+1	# table_execute_type   [2][TYPE_SHIFT  ]
+0	0	+1	# table_execute_type   [2][TYPE_MOVE   ]
+0	0	+1	# table_execute_type   [2][TYPE_TEST   ]
+0	0	+1	# table_execute_type   [2][TYPE_MUL    ]
+0	0	+1	# table_execute_type   [2][TYPE_DIV    ]
+0	0	+1	# table_execute_type   [2][TYPE_EXTEND ]
+0	0	+1	# table_execute_type   [2][TYPE_FIND   ]
+0	0	+1	# table_execute_type   [2][TYPE_SPECIAL]
+0	0	+1	# table_execute_type   [2][TYPE_CUSTOM ]
+1	1	+1	# table_execute_type   [2][TYPE_BRANCH ]
+0	0	+1	# table_execute_type   [2][TYPE_MEMORY ]
+1	1	+1	# table_execute_type   [3][TYPE_ALU    ]
+1	1	+1	# table_execute_type   [3][TYPE_SHIFT  ]
+1	1	+1	# table_execute_type   [3][TYPE_MOVE   ]
+1	1	+1	# table_execute_type   [3][TYPE_TEST   ]
+0	0	+1	# table_execute_type   [3][TYPE_MUL    ]
+0	0	+1	# table_execute_type   [3][TYPE_DIV    ]
+1	1	+1	# table_execute_type   [3][TYPE_EXTEND ]
+1	1	+1	# table_execute_type   [3][TYPE_FIND   ]
+0	0	+1	# table_execute_type   [3][TYPE_SPECIAL]
+0	0	+1	# table_execute_type   [3][TYPE_CUSTOM ]
+1	1	+1	# table_execute_type   [3][TYPE_BRANCH ]
+0	0	+1	# table_execute_type   [3][TYPE_MEMORY ]
+0	0	+1	# table_execute_type   [4][TYPE_ALU    ]
+1	1	+1	# table_execute_type   [4][TYPE_SHIFT  ]
+1	1	+1	# table_execute_type   [4][TYPE_MOVE   ]
+0	0	+1	# table_execute_type   [4][TYPE_TEST   ]
+1	1	+1	# table_execute_type   [4][TYPE_MUL    ]
+1	1	+1	# table_execute_type   [4][TYPE_DIV    ]
+0	0	+1	# table_execute_type   [4][TYPE_EXTEND ]
+0	0	+1	# table_execute_type   [4][TYPE_FIND   ]
+0	0	+1	# table_execute_type   [4][TYPE_SPECIAL]
+0	0	+1	# table_execute_type   [4][TYPE_CUSTOM ]
+0	0	+1	# table_execute_type   [4][TYPE_BRANCH ]
+0	0	+1	# table_execute_type   [4][TYPE_MEMORY ]
+1	1	+1	# table_execute_thread [0][0]
+1	1	+1	# table_execute_thread [1][0]
+1	1	+1	# table_execute_thread [2][0]
+1	1	+1	# table_execute_thread [3][0]
+1	1	+1	# table_execute_thread [4][0]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/configuration/config_multi_execute-mono_thread.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/configuration/config_multi_execute-mono_thread.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/configuration/config_multi_execute-mono_thread.gen	(revision 145)
@@ -0,0 +1,85 @@
+Read_unit_to_Execution_unit
+3	3 	*2	# nb_read_unit           
+1	1 	+1	# nb_read_unit_port    [0] [nb_read_unit]
+2	2 	+1	# nb_read_unit_port    [1] [nb_read_unit]
+4	4 	+1	# nb_read_unit_port    [2] [nb_read_unit]
+4	4 	*2	# nb_execute_unit        
+1	1 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [2] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [3] [nb_execute_unit]
+1	1	*2	# nb_context             
+1	1	*2	# nb_front_end           
+1	1	*2	# nb_ooo_engine          
+64	64	*2	# nb_packet              
+32	32	*2	# size_general_data      
+2	2	*2	# size_special_data      
+64	64	*2	# nb_general_register    
+16	16	*2	# nb_special_register    
+4	4	*2	# size_store_queue       
+1	4	*4	# size_load_queue        
+0	1	+1	# priority
+1	1	+1	# table_routing        [0][0][0]
+0	0	+1	# table_routing        [0][1][0]
+0	0	+1	# table_routing        [0][2][0]
+0	0	+1	# table_routing        [0][3][0]
+0 	0	+1	# table_routing        [1][0][0]
+1	1	+1	# table_routing        [1][1][0]
+1	1	+1	# table_routing        [1][2][0]
+0	0	+1	# table_routing        [1][3][0]
+0	0	+1	# table_routing        [2][0][0]
+0	0	+1	# table_routing        [2][1][0]
+1	1	+1	# table_routing        [2][2][0]
+1	1	+1	# table_routing        [2][3][0]
+0	0	+1	# table_execute_type   [0][TYPE_ALU    ]
+0	0	+1	# table_execute_type   [0][TYPE_SHIFT  ]
+0	0	+1	# table_execute_type   [0][TYPE_MOVE   ]
+0	0	+1	# table_execute_type   [0][TYPE_TEST   ]
+0	0	+1	# table_execute_type   [0][TYPE_MUL    ]
+0	0	+1	# table_execute_type   [0][TYPE_DIV    ]
+0	0	+1	# table_execute_type   [0][TYPE_EXTEND ]
+0	0	+1	# table_execute_type   [0][TYPE_FIND   ]
+0	0	+1	# table_execute_type   [0][TYPE_SPECIAL]
+0	0	+1	# table_execute_type   [0][TYPE_CUSTOM ]
+0	0	+1	# table_execute_type   [0][TYPE_BRANCH ]
+1	1	+1	# table_execute_type   [0][TYPE_MEMORY ]
+1	1	+1	# table_execute_type   [1][TYPE_ALU    ]
+1	1	+1	# table_execute_type   [1][TYPE_SHIFT  ]
+1	1	+1	# table_execute_type   [1][TYPE_MOVE   ]
+1	1	+1	# table_execute_type   [1][TYPE_TEST   ]
+1	1	+1	# table_execute_type   [1][TYPE_MUL    ]
+1	1	+1	# table_execute_type   [1][TYPE_DIV    ]
+1	1	+1	# table_execute_type   [1][TYPE_EXTEND ]
+1	1	+1	# table_execute_type   [1][TYPE_FIND   ]
+1	1	+1	# table_execute_type   [1][TYPE_SPECIAL]
+1	1	+1	# table_execute_type   [1][TYPE_CUSTOM ]
+1	1	+1	# table_execute_type   [1][TYPE_BRANCH ]
+0	0	+1	# table_execute_type   [1][TYPE_MEMORY ]
+1	1	+1	# table_execute_type   [2][TYPE_ALU    ]
+0	0	+1	# table_execute_type   [2][TYPE_SHIFT  ]
+0	0	+1	# table_execute_type   [2][TYPE_MOVE   ]
+0	0	+1	# table_execute_type   [2][TYPE_TEST   ]
+0	0	+1	# table_execute_type   [2][TYPE_MUL    ]
+0	0	+1	# table_execute_type   [2][TYPE_DIV    ]
+0	0	+1	# table_execute_type   [2][TYPE_EXTEND ]
+0	0	+1	# table_execute_type   [2][TYPE_FIND   ]
+0	0	+1	# table_execute_type   [2][TYPE_SPECIAL]
+0	0	+1	# table_execute_type   [2][TYPE_CUSTOM ]
+1	1	+1	# table_execute_type   [2][TYPE_BRANCH ]
+0	0	+1	# table_execute_type   [2][TYPE_MEMORY ]
+1	1	+1	# table_execute_type   [3][TYPE_ALU    ]
+1	1	+1	# table_execute_type   [3][TYPE_SHIFT  ]
+1	1	+1	# table_execute_type   [3][TYPE_MOVE   ]
+1	1	+1	# table_execute_type   [3][TYPE_TEST   ]
+0	0	+1	# table_execute_type   [3][TYPE_MUL    ]
+0	0	+1	# table_execute_type   [3][TYPE_DIV    ]
+1	1	+1	# table_execute_type   [3][TYPE_EXTEND ]
+1	1	+1	# table_execute_type   [3][TYPE_FIND   ]
+0	0	+1	# table_execute_type   [3][TYPE_SPECIAL]
+0	0	+1	# table_execute_type   [3][TYPE_CUSTOM ]
+1	1	+1	# table_execute_type   [3][TYPE_BRANCH ]
+0	0	+1	# table_execute_type   [3][TYPE_MEMORY ]
+1	1	+1	# table_execute_thread [0][0]
+1	1	+1	# table_execute_thread [1][0]
+1	1	+1	# table_execute_thread [2][0]
+1	1	+1	# table_execute_thread [3][0]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/configuration/config_multi_execute-multi_thread.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/configuration/config_multi_execute-multi_thread.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/configuration/config_multi_execute-multi_thread.gen	(revision 145)
@@ -0,0 +1,97 @@
+Read_unit_to_Execution_unit
+3	3 	*2	# nb_read_unit           
+1	1 	+1	# nb_read_unit_port    [0] [nb_read_unit]
+1	1 	+1	# nb_read_unit_port    [1] [nb_read_unit]
+1	1 	+1	# nb_read_unit_port    [2] [nb_read_unit]
+4	4 	*2	# nb_execute_unit        
+1	1 	+1	# nb_execute_unit_port [0] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [1] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [2] [nb_execute_unit]
+1	1 	+1	# nb_execute_unit_port [3] [nb_execute_unit]
+4	4	*2	# nb_context             
+1	1	*2	# nb_front_end           
+1	1	*2	# nb_ooo_engine          
+64	64	*2	# nb_packet              
+32	32	*2	# size_general_data      
+2	2	*2	# size_special_data      
+64	64	*2	# nb_general_register    
+16	16	*2	# nb_special_register    
+4	4	*2	# size_store_queue       
+4	4	*2	# size_load_queue        
+0	1	+1	# priority
+1	1	+1	# table_routing        [0][0][0]
+0	0	+1	# table_routing        [0][1][0]
+0	0	+1	# table_routing        [0][2][0]
+0	0	+1	# table_routing        [0][3][0]
+0 	0	+1	# table_routing        [1][0][0]
+1	1	+1	# table_routing        [1][1][0]
+1	1	+1	# table_routing        [1][2][0]
+0	0	+1	# table_routing        [1][3][0]
+0	0	+1	# table_routing        [2][0][0]
+0	0	+1	# table_routing        [2][1][0]
+1	1	+1	# table_routing        [2][2][0]
+1	1	+1	# table_routing        [2][3][0]
+0	0	+1	# table_execute_type   [0][TYPE_ALU    ]
+0	0	+1	# table_execute_type   [0][TYPE_SHIFT  ]
+0	0	+1	# table_execute_type   [0][TYPE_MOVE   ]
+0	0	+1	# table_execute_type   [0][TYPE_TEST   ]
+0	0	+1	# table_execute_type   [0][TYPE_MUL    ]
+0	0	+1	# table_execute_type   [0][TYPE_DIV    ]
+0	0	+1	# table_execute_type   [0][TYPE_EXTEND ]
+0	0	+1	# table_execute_type   [0][TYPE_FIND   ]
+0	0	+1	# table_execute_type   [0][TYPE_SPECIAL]
+0	0	+1	# table_execute_type   [0][TYPE_CUSTOM ]
+0	0	+1	# table_execute_type   [0][TYPE_BRANCH ]
+1	1	+1	# table_execute_type   [0][TYPE_MEMORY ]
+1	1	+1	# table_execute_type   [1][TYPE_ALU    ]
+1	1	+1	# table_execute_type   [1][TYPE_SHIFT  ]
+1	1	+1	# table_execute_type   [1][TYPE_MOVE   ]
+1	1	+1	# table_execute_type   [1][TYPE_TEST   ]
+1	1	+1	# table_execute_type   [1][TYPE_MUL    ]
+1	1	+1	# table_execute_type   [1][TYPE_DIV    ]
+1	1	+1	# table_execute_type   [1][TYPE_EXTEND ]
+1	1	+1	# table_execute_type   [1][TYPE_FIND   ]
+1	1	+1	# table_execute_type   [1][TYPE_SPECIAL]
+1	1	+1	# table_execute_type   [1][TYPE_CUSTOM ]
+1	1	+1	# table_execute_type   [1][TYPE_BRANCH ]
+0	0	+1	# table_execute_type   [1][TYPE_MEMORY ]
+1	1	+1	# table_execute_type   [2][TYPE_ALU    ]
+0	0	+1	# table_execute_type   [2][TYPE_SHIFT  ]
+0	0	+1	# table_execute_type   [2][TYPE_MOVE   ]
+0	0	+1	# table_execute_type   [2][TYPE_TEST   ]
+0	0	+1	# table_execute_type   [2][TYPE_MUL    ]
+0	0	+1	# table_execute_type   [2][TYPE_DIV    ]
+0	0	+1	# table_execute_type   [2][TYPE_EXTEND ]
+0	0	+1	# table_execute_type   [2][TYPE_FIND   ]
+0	0	+1	# table_execute_type   [2][TYPE_SPECIAL]
+0	0	+1	# table_execute_type   [2][TYPE_CUSTOM ]
+1	1	+1	# table_execute_type   [2][TYPE_BRANCH ]
+0	0	+1	# table_execute_type   [2][TYPE_MEMORY ]
+1	1	+1	# table_execute_type   [3][TYPE_ALU    ]
+1	1	+1	# table_execute_type   [3][TYPE_SHIFT  ]
+1	1	+1	# table_execute_type   [3][TYPE_MOVE   ]
+1	1	+1	# table_execute_type   [3][TYPE_TEST   ]
+1	1	+1	# table_execute_type   [3][TYPE_MUL    ]
+1	1	+1	# table_execute_type   [3][TYPE_DIV    ]
+0	0	+1	# table_execute_type   [3][TYPE_EXTEND ]
+0	0	+1	# table_execute_type   [3][TYPE_FIND   ]
+1	1	+1	# table_execute_type   [3][TYPE_SPECIAL]
+0	0	+1	# table_execute_type   [3][TYPE_CUSTOM ]
+1	1	+1	# table_execute_type   [3][TYPE_BRANCH ]
+0	0	+1	# table_execute_type   [3][TYPE_MEMORY ]
+1	1	+1	# table_execute_thread [0][0]
+1	1	+1	# table_execute_thread [0][1]
+1	1	+1	# table_execute_thread [0][2]
+1	1	+1	# table_execute_thread [0][3]
+1	1	+1	# table_execute_thread [1][0]
+1	1	+1	# table_execute_thread [1][1]
+1	1	+1	# table_execute_thread [1][2]
+0	0	+1	# table_execute_thread [1][3]
+0	0	+1	# table_execute_thread [2][0]
+1	1	+1	# table_execute_thread [2][1]
+1	1	+1	# table_execute_thread [2][2]
+0	0	+1	# table_execute_thread [2][3]
+0	0	+1	# table_execute_thread [3][0]
+0	0	+1	# table_execute_thread [3][1]
+0	0	+1	# table_execute_thread [3][2]
+1	1	+1	# table_execute_thread [3][3]	
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,16 +1,0 @@
-Register_unit_Glue
-4	4	*4	#nb_ooo_engine    
-32	32	*2	#size_general_data
-2	2	+1	#size_special_data
-2	8	*4	#nb_gpr_read      
-2	8	*4	#nb_spr_read          
-1	4	*4	#nb_gpr_write     
-1	4	*4	#nb_spr_write     
-1	1	*2	#_nb_inst_insert_rob  [0]     
-2	2	*2	#_nb_inst_insert_rob  [1]     
-4	4	*2	#_nb_inst_insert_rob  [2]     
-8	8	*2	#_nb_inst_insert_rob  [3]     
-1	1	*2	#_nb_inst_retire_rob  [0]     
-2	2	*2	#_nb_inst_retire_rob  [1]     
-4	4	*2	#_nb_inst_retire_rob  [2]     
-8	8	*2	#_nb_inst_retire_rob  [3]     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,16 @@
+Register_unit_Glue
+4	4	*4	#nb_ooo_engine    
+32	32	*2	#size_general_data
+2	2	+1	#size_special_data
+2	8	*4	#nb_gpr_read      
+2	8	*4	#nb_spr_read          
+1	4	*4	#nb_gpr_write     
+1	4	*4	#nb_spr_write     
+1	1	*2	#_nb_inst_insert_rob  [0]     
+2	2	*2	#_nb_inst_insert_rob  [1]     
+4	4	*2	#_nb_inst_insert_rob  [2]     
+8	8	*2	#_nb_inst_insert_rob  [3]     
+1	1	*2	#_nb_inst_retire_rob  [0]     
+2	2	*2	#_nb_inst_retire_rob  [1]     
+4	4	*2	#_nb_inst_retire_rob  [2]     
+8	8	*2	#_nb_inst_retire_rob  [3]     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration/configuration_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration/configuration_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration/configuration_min.gen	(revision 145)
@@ -0,0 +1,18 @@
+Register_unit
+1	1	*4	#_nb_ooo_engine            
+32	32	*4	#_size_general_data        
+2	2	*4	#_size_special_data        
+1	1	*4	#_nb_gpr_read              
+1	1	*4	#_nb_gpr_write             
+1	1	*4	#_nb_gpr_bank              
+1	1	*4	#_nb_gpr_port_read_by_bank 
+1	1	*4	#_nb_gpr_port_write_by_bank
+1	1	*4	#_nb_spr_read              
+1	1	*4	#_nb_spr_write             
+1	1	*4	#_nb_spr_bank              
+1	1	*4	#_nb_spr_port_read_by_bank 
+1	1	*4	#_nb_spr_port_write_by_bank
+32 	32 	*4	#_nb_general_register [0]     
+32 	32  	*4	#_nb_special_register [0]     
+1	1	*4	#_nb_inst_insert_rob  [0]     
+1	1	*4	#_nb_inst_retire_rob  [0]     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration/configuration_mono_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration/configuration_mono_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration/configuration_mono_context.gen	(revision 145)
@@ -0,0 +1,18 @@
+Register_unit
+1	1	*4	#_nb_ooo_engine            
+32	32	*4	#_size_general_data        
+32	32	*4	#_size_special_data        
+4	8	*4	#_nb_gpr_read              
+4	8	*4	#_nb_gpr_write             
+2	8	*4	#_nb_gpr_bank              
+1	4	*4	#_nb_gpr_port_read_by_bank 
+1	4	*4	#_nb_gpr_port_write_by_bank
+4	4	*4	#_nb_spr_read              
+4	4	*4	#_nb_spr_write             
+1	1	*4	#_nb_spr_bank              
+1	4	*4	#_nb_spr_port_read_by_bank 
+1	1	*4	#_nb_spr_port_write_by_bank
+32 	32 	*4	#_nb_general_register [0]     
+32 	32  	*4	#_nb_special_register [0]     
+1	4	*4	#_nb_inst_insert_rob  [0]     
+1	4	*4	#_nb_inst_retire_rob  [0]     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration/configuration_multi_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration/configuration_multi_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration/configuration_multi_context.gen	(revision 145)
@@ -0,0 +1,30 @@
+Register_unit
+4	4	*4	#_nb_ooo_engine            
+32	32	*4	#_size_general_data        
+32	32	*4	#_size_special_data        
+4	8	*4	#_nb_gpr_read              
+4	8	*4	#_nb_gpr_write             
+1	4	*4	#_nb_gpr_bank              
+1	4	*4	#_nb_gpr_port_read_by_bank 
+1	4	*4	#_nb_gpr_port_write_by_bank
+4	4	*4	#_nb_spr_read              
+4	4	*4	#_nb_spr_write             
+1	1	*4	#_nb_spr_bank              
+2	2	*4	#_nb_spr_port_read_by_bank 
+2	2	*4	#_nb_spr_port_write_by_bank
+64 	64 	*2	#_nb_general_register [0]     
+32 	32 	*2	#_nb_general_register [1]     
+32 	32 	*2	#_nb_general_register [2]     
+16 	16 	*2	#_nb_general_register [3]     
+8  	8    	*2	#_nb_special_register [0]     
+32 	32   	*2	#_nb_special_register [1]     
+64 	64   	*2	#_nb_special_register [2]     
+128	128  	*2	#_nb_special_register [3]     
+8	8	*4	#_nb_inst_insert_rob  [0]     
+4	4	*4	#_nb_inst_insert_rob  [1]     
+2	2	*4	#_nb_inst_insert_rob  [2]     
+1	1	*4	#_nb_inst_insert_rob  [3]     
+1	1	*4	#_nb_inst_retire_rob  [0]     
+2	2	*4	#_nb_inst_retire_rob  [1]     
+4	4	*4	#_nb_inst_retire_rob  [2]     
+8	8	*4	#_nb_inst_retire_rob  [3]     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,18 +1,0 @@
-Register_unit
-1	1	*4	#_nb_ooo_engine            
-32	32	*4	#_size_general_data        
-2	2	*4	#_size_special_data        
-1	1	*4	#_nb_gpr_read              
-1	1	*4	#_nb_gpr_write             
-1	1	*4	#_nb_gpr_bank              
-1	1	*4	#_nb_gpr_port_read_by_bank 
-1	1	*4	#_nb_gpr_port_write_by_bank
-1	1	*4	#_nb_spr_read              
-1	1	*4	#_nb_spr_write             
-1	1	*4	#_nb_spr_bank              
-1	1	*4	#_nb_spr_port_read_by_bank 
-1	1	*4	#_nb_spr_port_write_by_bank
-32 	32 	*4	#_nb_general_register [0]     
-32 	32  	*4	#_nb_special_register [0]     
-1	1	*4	#_nb_inst_insert_rob  [0]     
-1	1	*4	#_nb_inst_retire_rob  [0]     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration_mono_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,18 +1,0 @@
-Register_unit
-1	1	*4	#_nb_ooo_engine            
-32	32	*4	#_size_general_data        
-32	32	*4	#_size_special_data        
-4	8	*4	#_nb_gpr_read              
-4	8	*4	#_nb_gpr_write             
-2	8	*4	#_nb_gpr_bank              
-1	4	*4	#_nb_gpr_port_read_by_bank 
-1	4	*4	#_nb_gpr_port_write_by_bank
-4	4	*4	#_nb_spr_read              
-4	4	*4	#_nb_spr_write             
-1	1	*4	#_nb_spr_bank              
-1	4	*4	#_nb_spr_port_read_by_bank 
-1	1	*4	#_nb_spr_port_write_by_bank
-32 	32 	*4	#_nb_general_register [0]     
-32 	32  	*4	#_nb_special_register [0]     
-1	4	*4	#_nb_inst_insert_rob  [0]     
-1	4	*4	#_nb_inst_retire_rob  [0]     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration_multi_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,30 +1,0 @@
-Register_unit
-4	4	*4	#_nb_ooo_engine            
-32	32	*4	#_size_general_data        
-32	32	*4	#_size_special_data        
-4	8	*4	#_nb_gpr_read              
-4	8	*4	#_nb_gpr_write             
-1	4	*4	#_nb_gpr_bank              
-1	4	*4	#_nb_gpr_port_read_by_bank 
-1	4	*4	#_nb_gpr_port_write_by_bank
-4	4	*4	#_nb_spr_read              
-4	4	*4	#_nb_spr_write             
-1	1	*4	#_nb_spr_bank              
-2	2	*4	#_nb_spr_port_read_by_bank 
-2	2	*4	#_nb_spr_port_write_by_bank
-64 	64 	*2	#_nb_general_register [0]     
-32 	32 	*2	#_nb_general_register [1]     
-32 	32 	*2	#_nb_general_register [2]     
-16 	16 	*2	#_nb_general_register [3]     
-8  	8    	*2	#_nb_special_register [0]     
-32 	32   	*2	#_nb_special_register [1]     
-64 	64   	*2	#_nb_special_register [2]     
-128	128  	*2	#_nb_special_register [3]     
-8	8	*4	#_nb_inst_insert_rob  [0]     
-4	4	*4	#_nb_inst_insert_rob  [1]     
-2	2	*4	#_nb_inst_insert_rob  [2]     
-1	1	*4	#_nb_inst_insert_rob  [3]     
-1	1	*4	#_nb_inst_retire_rob  [0]     
-2	2	*4	#_nb_inst_retire_rob  [1]     
-4	4	*4	#_nb_inst_retire_rob  [2]     
-8	8	*4	#_nb_inst_retire_rob  [3]     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,50 +1,0 @@
-Execute_loop
-1	1	+1	# nb_read_unit                              
-1	1	+1	# nb_functionnal_unit                       
-1	1	+1	# nb_load_store_unit                        
-1	1	+1	# nb_write_unit                             
-1	1	+1	# nb_context                                
-1	1	+1	# nb_front_end                              
-1	1	+1	# nb_ooo_engine                             
-32	32	+1	# nb_packet                                 
-32	32	+1	# size_general_data                         
-2	2	+1	# size_special_data                         
-1	1	+1	# size_read_queue                            [0]       [nb_read_unit]
-1	1	+1	# size_reservation_station                   [0]       [nb_read_unit]
-1	1	+1	# nb_inst_retire                             [0]       [nb_read_unit]
-1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
-2	2	+1	# size_store_queue                           [0]       [nb_load_store_unit]
-1	1	+1	# size_load_queue                            [0]       [nb_load_store_unit]
-1	1	+1	# size_speculative_access_queue              [0]       [nb_load_store_unit]
-1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
-2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
-0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
-1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
-1	1	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
-1	1	+1	# size_write_queue                           [0]       [nb_write_unit]
-1	1	+1	# size_execute_queue                         [0]       [nb_write_unit]
-1	1	+1	# nb_bypass_write                            [0]       [nb_write_unit]
-0	1	+1	# write_queue_scheme                         [0]       [nb_write_unit]
-1	1	+1	# nb_gpr_bank                                	       
-1	1	+1	# nb_gpr_port_read_by_bank                   	       
-1	1	+1	# nb_gpr_port_write_by_bank                  	       
-1	1	+1	# nb_spr_bank                                	       
-1	1	+1	# nb_spr_port_read_by_bank                   	       
-1	1	+1	# nb_spr_port_write_by_bank                  	       
-64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# execution_unit_to_write_unit_priority                                         
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# read_unit_to_execution_unit_priority                                          
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
-0	0	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
-1	1	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_2a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_2a.cfg	(revision 144)
+++ 	(revision )
@@ -1,50 +1,0 @@
-Execute_loop
-1	1	+1	# nb_read_unit                              
-1	1	+1	# nb_functionnal_unit                       
-1	1	+1	# nb_load_store_unit                        
-1	1	+1	# nb_write_unit                             
-1	1	+1	# nb_context                                
-1	1	+1	# nb_front_end                              
-1	1	+1	# nb_ooo_engine                             
-32	32	+1	# nb_packet                                 
-32	32	+1	# size_general_data                         
-2	2	+1	# size_special_data                         
-4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
-4	4	*4	# size_reservation_station                   [0]       [nb_read_unit]
-2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
-1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
-4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
-4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
-4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
-1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
-2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
-0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
-1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
-1	1	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
-4	4	*4	# size_write_queue                           [0]       [nb_write_unit]
-4	4	*4	# size_execute_queue                         [0]       [nb_write_unit]
-2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
-0	1	+1	# write_queue_scheme                         [0]       [nb_write_unit]
-4	4	+1	# nb_gpr_bank                                	       
-1	1	+1	# nb_gpr_port_read_by_bank                   	       
-1	1	+1	# nb_gpr_port_write_by_bank                  	       
-4	4	+1	# nb_spr_bank                                	       
-1	1	+1	# nb_spr_port_read_by_bank                   	       
-1	1	+1	# nb_spr_port_write_by_bank                  	       
-64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# execution_unit_to_write_unit_priority                                         
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# read_unit_to_execution_unit_priority                                          
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
-0	0	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
-1	1	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_2b.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_2b.cfg	(revision 144)
+++ 	(revision )
@@ -1,94 +1,0 @@
-Execute_loop
-4	4	+1	# nb_read_unit                              
-1	1	+1	# nb_functionnal_unit                       
-1	1	+1	# nb_load_store_unit                        
-4	4	+1	# nb_write_unit                             
-1	1	+1	# nb_context                                
-1	1	+1	# nb_front_end                              
-1	1	+1	# nb_ooo_engine                             
-32	32	+1	# nb_packet                                 
-32	32	+1	# size_general_data                         
-2	2	+1	# size_special_data                         
-4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
-8	8	*4	# size_read_queue                            [1]       [nb_read_unit]
-1	1	*4	# size_read_queue                            [2]       [nb_read_unit]
-8	8	*4	# size_read_queue                            [3]       [nb_read_unit]
-8	8	*4	# size_reservation_station                   [0]       [nb_read_unit]
-1	1	*4	# size_reservation_station                   [1]       [nb_read_unit]
-4	4	*4	# size_reservation_station                   [2]       [nb_read_unit]
-2	2	*4	# size_reservation_station                   [3]       [nb_read_unit]
-2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
-1	1	+1	# nb_inst_retire                             [1]       [nb_read_unit]
-4	4	+1	# nb_inst_retire                             [2]       [nb_read_unit]
-2	2	+1	# nb_inst_retire                             [3]       [nb_read_unit]
-1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
-4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
-4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
-4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
-1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
-2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
-0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
-1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
-2	2	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
-2	2	*4	# size_write_queue                           [0]       [nb_write_unit]
-4	4	*4	# size_write_queue                           [1]       [nb_write_unit]
-1	1	*4	# size_write_queue                           [2]       [nb_write_unit]
-8	8	*4	# size_write_queue                           [3]       [nb_write_unit]
-0	0	*4	# size_execute_queue                         [0]       [nb_write_unit]
-4	4	*4	# size_execute_queue                         [1]       [nb_write_unit]
-2	2	*4	# size_execute_queue                         [2]       [nb_write_unit]
-1	1	*4	# size_execute_queue                         [3]       [nb_write_unit]
-2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
-2	2	+1	# nb_bypass_write                            [1]       [nb_write_unit]
-1	1	+1	# nb_bypass_write                            [2]       [nb_write_unit]
-4	4	+1	# nb_bypass_write                            [3]       [nb_write_unit]
-0	0	+1	# write_queue_scheme                         [0]       [nb_write_unit]
-0	1	+1	# write_queue_scheme                         [1]       [nb_write_unit]
-0	0	+1	# write_queue_scheme                         [2]       [nb_write_unit]
-0	1	+1	# write_queue_scheme                         [3]       [nb_write_unit]
-4	4	+1	# nb_gpr_bank                                	       
-2	2	+1	# nb_gpr_port_read_by_bank                   	       
-2	2	+1	# nb_gpr_port_write_by_bank                  	       
-4	4	+1	# nb_spr_bank                                	       
-1	1	+1	# nb_spr_port_read_by_bank                   	       
-1	1	+1	# nb_spr_port_write_by_bank                  	       
-64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# execution_unit_to_write_unit_priority                                         
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-0	0	+1	# execution_unit_to_write_unit_table_routing [0][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-0	0	+1	# execution_unit_to_write_unit_table_routing [0][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][1][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][1][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-0	0	+1	# execution_unit_to_write_unit_table_routing [0][1][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-0	0	+1	# execution_unit_to_write_unit_table_routing [0][1][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [1][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [2][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [3][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# read_unit_to_execution_unit_priority                                          
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [2][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [2][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [2][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [3][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [3][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [3][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
-1	1	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
-0	0	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_3a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_3a.cfg	(revision 144)
+++ 	(revision )
@@ -1,106 +1,0 @@
-Execute_loop
-4	4	+1	# nb_read_unit                              
-2	2	+1	# nb_functionnal_unit                       
-1	1	+1	# nb_load_store_unit                        
-4	4	+1	# nb_write_unit                             
-1	1	+1	# nb_context                                
-1	1	+1	# nb_front_end                              
-1	1	+1	# nb_ooo_engine                             
-32	32	+1	# nb_packet                                 
-32	32	+1	# size_general_data                         
-2	2	+1	# size_special_data                         
-4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
-8	8	*4	# size_read_queue                            [1]       [nb_read_unit]
-1	1	*4	# size_read_queue                            [2]       [nb_read_unit]
-8	8	*4	# size_read_queue                            [3]       [nb_read_unit]
-8	8	*4	# size_reservation_station                   [0]       [nb_read_unit]
-1	1	*4	# size_reservation_station                   [1]       [nb_read_unit]
-4	4	*4	# size_reservation_station                   [2]       [nb_read_unit]
-2	2	*4	# size_reservation_station                   [3]       [nb_read_unit]
-2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
-1	1	+1	# nb_inst_retire                             [1]       [nb_read_unit]
-4	4	+1	# nb_inst_retire                             [2]       [nb_read_unit]
-2	2	+1	# nb_inst_retire                             [3]       [nb_read_unit]
-1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
-1	1	+1	# nb_inst_functionnal_unit		     [1]       [nb_inst_functionnal]
-4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
-4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
-4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
-1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
-2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
-0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
-1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
-2	2	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
-2	2	*4	# size_write_queue                           [0]       [nb_write_unit]
-4	4	*4	# size_write_queue                           [1]       [nb_write_unit]
-1	1	*4	# size_write_queue                           [2]       [nb_write_unit]
-8	8	*4	# size_write_queue                           [3]       [nb_write_unit]
-0	0	*4	# size_execute_queue                         [0]       [nb_write_unit]
-4	4	*4	# size_execute_queue                         [1]       [nb_write_unit]
-2	2	*4	# size_execute_queue                         [2]       [nb_write_unit]
-1	1	*4	# size_execute_queue                         [3]       [nb_write_unit]
-2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
-2	2	+1	# nb_bypass_write                            [1]       [nb_write_unit]
-1	1	+1	# nb_bypass_write                            [2]       [nb_write_unit]
-4	4	+1	# nb_bypass_write                            [3]       [nb_write_unit]
-0	0	+1	# write_queue_scheme                         [0]       [nb_write_unit]
-0	1	+1	# write_queue_scheme                         [1]       [nb_write_unit]
-0	0	+1	# write_queue_scheme                         [2]       [nb_write_unit]
-0	1	+1	# write_queue_scheme                         [3]       [nb_write_unit]
-4	4	+1	# nb_gpr_bank                                	       
-2	2	+1	# nb_gpr_port_read_by_bank                   	       
-2	2	+1	# nb_gpr_port_write_by_bank                  	       
-4	4	+1	# nb_spr_bank                                	       
-1	1	+1	# nb_spr_port_read_by_bank                   	       
-1	1	+1	# nb_spr_port_write_by_bank                  	       
-64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# execution_unit_to_write_unit_priority                                         
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-0	0	+1	# execution_unit_to_write_unit_table_routing [0][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-0	0	+1	# execution_unit_to_write_unit_table_routing [0][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][1][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][1][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-0	0	+1	# execution_unit_to_write_unit_table_routing [0][1][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-0	0	+1	# execution_unit_to_write_unit_table_routing [0][1][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [1][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [2][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [3][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# read_unit_to_execution_unit_priority                                          
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [0][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [2][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [2][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [2][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [2][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [3][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [3][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [3][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [3][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [2][0]    [nb_execute_unit][nb_thread]    
-1	1	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
-0	0	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
-0	0	+1      # is_load_store_unit                         [2]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
-1       1       +1      # translate_num_execute_unit                 [2]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_6a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_6a.cfg	(revision 144)
+++ 	(revision )
@@ -1,142 +1,0 @@
-Execute_loop
-4	4	+1	# nb_read_unit                              
-5	5	+1	# nb_functionnal_unit                       
-1	1	+1	# nb_load_store_unit                        
-4	4	+1	# nb_write_unit                             
-1	1	+1	# nb_context                                
-1	1	+1	# nb_front_end                              
-1	1	+1	# nb_ooo_engine                             
-32	32	+1	# nb_packet                                 
-32	32	+1	# size_general_data                         
-2	2	+1	# size_special_data                         
-4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
-8	8	*4	# size_read_queue                            [1]       [nb_read_unit]
-1	1	*4	# size_read_queue                            [2]       [nb_read_unit]
-8	8	*4	# size_read_queue                            [3]       [nb_read_unit]
-8	8	*4	# size_reservation_station                   [0]       [nb_read_unit]
-1	1	*4	# size_reservation_station                   [1]       [nb_read_unit]
-4	4	*4	# size_reservation_station                   [2]       [nb_read_unit]
-2	2	*4	# size_reservation_station                   [3]       [nb_read_unit]
-2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
-1	1	+1	# nb_inst_retire                             [1]       [nb_read_unit]
-4	4	+1	# nb_inst_retire                             [2]       [nb_read_unit]
-2	2	+1	# nb_inst_retire                             [3]       [nb_read_unit]
-1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_functionnal_unit]
-1	1	+1	# nb_inst_functionnal_unit		     [1]       [nb_functionnal_unit]
-1	1	+1	# nb_inst_functionnal_unit		     [2]       [nb_functionnal_unit]
-1	1	+1	# nb_inst_functionnal_unit		     [3]       [nb_functionnal_unit]
-1	1	+1	# nb_inst_functionnal_unit		     [4]       [nb_functionnal_unit]
-4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
-4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
-4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
-1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
-2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
-0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
-1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
-2	2	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
-2	2	*4	# size_write_queue                           [0]       [nb_write_unit]
-4	4	*4	# size_write_queue                           [1]       [nb_write_unit]
-1	1	*4	# size_write_queue                           [2]       [nb_write_unit]
-8	8	*4	# size_write_queue                           [3]       [nb_write_unit]
-0	0	*4	# size_execute_queue                         [0]       [nb_write_unit]
-4	4	*4	# size_execute_queue                         [1]       [nb_write_unit]
-2	2	*4	# size_execute_queue                         [2]       [nb_write_unit]
-1	1	*4	# size_execute_queue                         [3]       [nb_write_unit]
-2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
-2	2	+1	# nb_bypass_write                            [1]       [nb_write_unit]
-1	1	+1	# nb_bypass_write                            [2]       [nb_write_unit]
-4	4	+1	# nb_bypass_write                            [3]       [nb_write_unit]
-0	0	+1	# write_queue_scheme                         [0]       [nb_write_unit]
-0	1	+1	# write_queue_scheme                         [1]       [nb_write_unit]
-0	0	+1	# write_queue_scheme                         [2]       [nb_write_unit]
-0	1	+1	# write_queue_scheme                         [3]       [nb_write_unit]
-4	4	+1	# nb_gpr_bank                                	       
-2	2	+1	# nb_gpr_port_read_by_bank                   	       
-2	2	+1	# nb_gpr_port_write_by_bank                  	       
-4	4	+1	# nb_spr_bank                                	       
-1	1	+1	# nb_spr_port_read_by_bank                   	       
-1	1	+1	# nb_spr_port_write_by_bank                  	       
-64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# execution_unit_to_write_unit_priority                                         
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-0	0	+1	# execution_unit_to_write_unit_table_routing [0][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-0	0	+1	# execution_unit_to_write_unit_table_routing [0][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][1][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][1][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-0	0	+1	# execution_unit_to_write_unit_table_routing [0][1][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-0	0	+1	# execution_unit_to_write_unit_table_routing [0][1][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [3][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [3][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [3][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [3][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [4][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [4][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [4][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [4][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [5][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [5][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [5][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [5][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [1][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [2][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [3][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# read_unit_to_execution_unit_priority                                          
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [0][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [0][3][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [0][4][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [0][5][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][3][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][4][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [1][5][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [2][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [2][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [2][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [2][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [2][3][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [2][4][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [2][5][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [3][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-0	0	+1	# read_unit_to_execution_unit_table_routing  [3][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [3][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [3][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [3][3][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [3][4][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [3][5][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [2][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [3][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [4][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [5][0]    [nb_execute_unit][nb_thread]    
-1	1	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
-0	0	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
-0	0	+1      # is_load_store_unit                         [2]       [nb_execute_unit]
-0	0	+1      # is_load_store_unit                         [3]       [nb_execute_unit]
-0	0	+1      # is_load_store_unit                         [4]       [nb_execute_unit]
-0	0	+1      # is_load_store_unit                         [5]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
-1       1       +1      # translate_num_execute_unit                 [2]       [nb_execute_unit]
-4       4       +1      # translate_num_execute_unit                 [3]       [nb_execute_unit]
-3       3       +1      # translate_num_execute_unit                 [4]       [nb_execute_unit]
-2       2       +1      # translate_num_execute_unit                 [5]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2a.cfg	(revision 144)
+++ 	(revision )
@@ -1,75 +1,0 @@
-Execute_loop
-1	1	+1	# nb_read_unit                              
-1	1	+1	# nb_functionnal_unit                       
-1	1	+1	# nb_load_store_unit                        
-1	1	+1	# nb_write_unit                             
-2	2	+1	# nb_context                                
-2	2	+1	# nb_front_end                              
-2	2	+1	# nb_ooo_engine                             
-32	32	+1	# nb_packet                                 
-32	32	+1	# size_general_data                         
-2	2	+1	# size_special_data                         
-4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
-4	4	*4	# size_reservation_station                   [0]       [nb_read_unit]
-2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
-1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
-4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
-4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
-4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
-1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
-2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
-0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
-1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
-1	1	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
-4	4	*4	# size_write_queue                           [0]       [nb_write_unit]
-4	4	*4	# size_execute_queue                         [0]       [nb_write_unit]
-2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
-0	0	+1	# write_queue_scheme                         [0]       [nb_write_unit]
-4	4	+1	# nb_gpr_bank                                	       
-1	1	+1	# nb_gpr_port_read_by_bank                   	       
-1	1	+1	# nb_gpr_port_write_by_bank                  	       
-4	4	+1	# nb_spr_bank                                	       
-1	1	+1	# nb_spr_port_read_by_bank                   	       
-1	1	+1	# nb_spr_port_write_by_bank                  	       
-64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
-128	128	+1	# nb_general_register                        [1]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
-8	8	+1	# nb_special_register                        [1]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
-2	2	+1	# nb_inst_insert_rob                         [1]       [nb_ooo_engine]		  
-2	2	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [1]       [nb_ooo_engine]		  
-1	1	+1	# execution_unit_to_write_unit_priority                                         
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][1]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][2]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][3]    [nb_write_unit][nb_thread]	  
-0	0	+1	# execution_unit_to_write_unit_table_thread  [0][4]    [nb_write_unit][nb_thread]	  
-0	0	+1	# execution_unit_to_write_unit_table_thread  [0][5]    [nb_write_unit][nb_thread]	  
-0	0	+1	# execution_unit_to_write_unit_table_thread  [0][6]    [nb_write_unit][nb_thread]	  
-0	0	+1	# execution_unit_to_write_unit_table_thread  [0][7]    [nb_write_unit][nb_thread]	  
-1	1	+1	# read_unit_to_execution_unit_priority                                          
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][1]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][2]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][3]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][4]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][5]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][6]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][7]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][1]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][2]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][3]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][4]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][5]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][6]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][7]    [nb_execute_unit][nb_thread]    
-0	0	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
-1	1	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2b.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2b.cfg	(revision 144)
+++ 	(revision )
@@ -1,83 +1,0 @@
-Execute_loop
-1	1	+1	# nb_read_unit                              
-1	1	+1	# nb_functionnal_unit                       
-1	1	+1	# nb_load_store_unit                        
-1	1	+1	# nb_write_unit                             
-2	2	+1	# nb_context                                
-1	1	+1	# nb_front_end                              
-4	4	+1	# nb_ooo_engine                             
-32	32	+1	# nb_packet                                 
-32	32	+1	# size_general_data                         
-2	2	+1	# size_special_data                         
-4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
-4	4	*4	# size_reservation_station                   [0]       [nb_read_unit]
-2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
-1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
-4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
-4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
-4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
-1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
-2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
-0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
-1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
-1	1	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
-4	4	*4	# size_write_queue                           [0]       [nb_write_unit]
-4	4	*4	# size_execute_queue                         [0]       [nb_write_unit]
-2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
-0	1	+1	# write_queue_scheme                         [0]       [nb_write_unit]
-4	4	+1	# nb_gpr_bank                                	       
-1	1	+1	# nb_gpr_port_read_by_bank                   	       
-1	1	+1	# nb_gpr_port_write_by_bank                  	       
-4	4	+1	# nb_spr_bank                                	       
-1	1	+1	# nb_spr_port_read_by_bank                   	       
-1	1	+1	# nb_spr_port_write_by_bank                  	       
-64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
-64	64	+1	# nb_general_register                        [1]       [nb_ooo_engine]		  
-64	64	+1	# nb_general_register                        [2]       [nb_ooo_engine]		  
-64	64	+1	# nb_general_register                        [3]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [1]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [2]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [3]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [1]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [2]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [3]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [1]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [2]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [3]       [nb_ooo_engine]		  
-1	1	+1	# execution_unit_to_write_unit_priority                                         
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][1]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][2]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][3]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][4]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][5]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][6]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][7]    [nb_write_unit][nb_thread]	  
-1	1	+1	# read_unit_to_execution_unit_priority                                          
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][1]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][2]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][3]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][4]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][5]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][6]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][7]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][1]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][2]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][3]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][4]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][5]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][6]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][7]    [nb_execute_unit][nb_thread]    
-0	0	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
-1	1	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2c.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2c.cfg	(revision 144)
+++ 	(revision )
@@ -1,99 +1,0 @@
-Execute_loop
-1	1	+1	# nb_read_unit                              
-1	1	+1	# nb_functionnal_unit                       
-1	1	+1	# nb_load_store_unit                        
-1	1	+1	# nb_write_unit                             
-1	1	+1	# nb_context                                
-1	1	+1	# nb_front_end                              
-8	8	+1	# nb_ooo_engine                             
-32	32	+1	# nb_packet                                 
-32	32	+1	# size_general_data                         
-2	2	+1	# size_special_data                         
-4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
-4	4	*4	# size_reservation_station                   [0]       [nb_read_unit]
-2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
-1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
-4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
-4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
-4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
-1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
-2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
-0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
-1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
-1	1	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
-4	4	*4	# size_write_queue                           [0]       [nb_write_unit]
-4	4	*4	# size_execute_queue                         [0]       [nb_write_unit]
-2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
-0	0	+1	# write_queue_scheme                         [0]       [nb_write_unit]
-4	4	+1	# nb_gpr_bank                                	       
-1	1	+1	# nb_gpr_port_read_by_bank                   	       
-1	1	+1	# nb_gpr_port_write_by_bank                  	       
-4	4	+1	# nb_spr_bank                                	       
-1	1	+1	# nb_spr_port_read_by_bank                   	       
-1	1	+1	# nb_spr_port_write_by_bank                  	       
-64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
-64	64	+1	# nb_general_register                        [1]       [nb_ooo_engine]		  
-64	64	+1	# nb_general_register                        [2]       [nb_ooo_engine]		  
-64	64	+1	# nb_general_register                        [3]       [nb_ooo_engine]		  
-64	64	+1	# nb_general_register                        [4]       [nb_ooo_engine]		  
-64	64	+1	# nb_general_register                        [5]       [nb_ooo_engine]		  
-64	64	+1	# nb_general_register                        [6]       [nb_ooo_engine]		  
-64	64	+1	# nb_general_register                        [7]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [1]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [2]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [3]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [4]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [5]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [6]       [nb_ooo_engine]		  
-16	16	+1	# nb_special_register                        [7]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [1]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [2]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [3]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [4]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [5]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [6]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_insert_rob                         [7]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [1]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [2]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [3]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [4]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [5]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [6]       [nb_ooo_engine]		  
-1	1	+1	# nb_inst_retire_rob                         [7]       [nb_ooo_engine]		  
-1	1	+1	# execution_unit_to_write_unit_priority                                         
-1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][1]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][2]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][3]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][4]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][5]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][6]    [nb_write_unit][nb_thread]	  
-1	1	+1	# execution_unit_to_write_unit_table_thread  [0][7]    [nb_write_unit][nb_thread]	  
-1	1	+1	# read_unit_to_execution_unit_priority                                          
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][1]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][2]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][3]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][4]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][5]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][6]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [0][7]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][1]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][2]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][3]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][4]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][5]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][6]    [nb_execute_unit][nb_thread]    
-1	1	+1	# read_unit_to_execution_unit_table_thread   [1][7]    [nb_execute_unit][nb_thread]    
-0	0	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
-1	1	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
-0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,50 @@
+Execute_loop
+1	1	+1	# nb_read_unit                              
+1	1	+1	# nb_functionnal_unit                       
+1	1	+1	# nb_load_store_unit                        
+1	1	+1	# nb_write_unit                             
+1	1	+1	# nb_context                                
+1	1	+1	# nb_front_end                              
+1	1	+1	# nb_ooo_engine                             
+32	32	+1	# nb_packet                                 
+32	32	+1	# size_general_data                         
+2	2	+1	# size_special_data                         
+1	1	+1	# size_read_queue                            [0]       [nb_read_unit]
+1	1	+1	# size_reservation_station                   [0]       [nb_read_unit]
+1	1	+1	# nb_inst_retire                             [0]       [nb_read_unit]
+1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
+2	2	+1	# size_store_queue                           [0]       [nb_load_store_unit]
+1	1	+1	# size_load_queue                            [0]       [nb_load_store_unit]
+1	1	+1	# size_speculative_access_queue              [0]       [nb_load_store_unit]
+1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
+2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
+0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
+1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
+1	1	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
+1	1	+1	# size_write_queue                           [0]       [nb_write_unit]
+1	1	+1	# size_execute_queue                         [0]       [nb_write_unit]
+1	1	+1	# nb_bypass_write                            [0]       [nb_write_unit]
+0	1	+1	# write_queue_scheme                         [0]       [nb_write_unit]
+1	1	+1	# nb_gpr_bank                                	       
+1	1	+1	# nb_gpr_port_read_by_bank                   	       
+1	1	+1	# nb_gpr_port_write_by_bank                  	       
+1	1	+1	# nb_spr_bank                                	       
+1	1	+1	# nb_spr_port_read_by_bank                   	       
+1	1	+1	# nb_spr_port_write_by_bank                  	       
+64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# execution_unit_to_write_unit_priority                                         
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# read_unit_to_execution_unit_priority                                          
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
+0	0	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
+1	1	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_1_execute_2a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_1_execute_2a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_1_execute_2a.gen	(revision 145)
@@ -0,0 +1,50 @@
+Execute_loop
+1	1	+1	# nb_read_unit                              
+1	1	+1	# nb_functionnal_unit                       
+1	1	+1	# nb_load_store_unit                        
+1	1	+1	# nb_write_unit                             
+1	1	+1	# nb_context                                
+1	1	+1	# nb_front_end                              
+1	1	+1	# nb_ooo_engine                             
+32	32	+1	# nb_packet                                 
+32	32	+1	# size_general_data                         
+2	2	+1	# size_special_data                         
+4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
+4	4	*4	# size_reservation_station                   [0]       [nb_read_unit]
+2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
+1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
+4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
+4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
+4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
+1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
+2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
+0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
+1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
+1	1	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
+4	4	*4	# size_write_queue                           [0]       [nb_write_unit]
+4	4	*4	# size_execute_queue                         [0]       [nb_write_unit]
+2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
+0	1	+1	# write_queue_scheme                         [0]       [nb_write_unit]
+4	4	+1	# nb_gpr_bank                                	       
+1	1	+1	# nb_gpr_port_read_by_bank                   	       
+1	1	+1	# nb_gpr_port_write_by_bank                  	       
+4	4	+1	# nb_spr_bank                                	       
+1	1	+1	# nb_spr_port_read_by_bank                   	       
+1	1	+1	# nb_spr_port_write_by_bank                  	       
+64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# execution_unit_to_write_unit_priority                                         
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# read_unit_to_execution_unit_priority                                          
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
+0	0	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
+1	1	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_1_execute_2b.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_1_execute_2b.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_1_execute_2b.gen	(revision 145)
@@ -0,0 +1,94 @@
+Execute_loop
+4	4	+1	# nb_read_unit                              
+1	1	+1	# nb_functionnal_unit                       
+1	1	+1	# nb_load_store_unit                        
+4	4	+1	# nb_write_unit                             
+1	1	+1	# nb_context                                
+1	1	+1	# nb_front_end                              
+1	1	+1	# nb_ooo_engine                             
+32	32	+1	# nb_packet                                 
+32	32	+1	# size_general_data                         
+2	2	+1	# size_special_data                         
+4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
+8	8	*4	# size_read_queue                            [1]       [nb_read_unit]
+1	1	*4	# size_read_queue                            [2]       [nb_read_unit]
+8	8	*4	# size_read_queue                            [3]       [nb_read_unit]
+8	8	*4	# size_reservation_station                   [0]       [nb_read_unit]
+1	1	*4	# size_reservation_station                   [1]       [nb_read_unit]
+4	4	*4	# size_reservation_station                   [2]       [nb_read_unit]
+2	2	*4	# size_reservation_station                   [3]       [nb_read_unit]
+2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
+1	1	+1	# nb_inst_retire                             [1]       [nb_read_unit]
+4	4	+1	# nb_inst_retire                             [2]       [nb_read_unit]
+2	2	+1	# nb_inst_retire                             [3]       [nb_read_unit]
+1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
+4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
+4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
+4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
+1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
+2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
+0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
+1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
+2	2	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
+2	2	*4	# size_write_queue                           [0]       [nb_write_unit]
+4	4	*4	# size_write_queue                           [1]       [nb_write_unit]
+1	1	*4	# size_write_queue                           [2]       [nb_write_unit]
+8	8	*4	# size_write_queue                           [3]       [nb_write_unit]
+0	0	*4	# size_execute_queue                         [0]       [nb_write_unit]
+4	4	*4	# size_execute_queue                         [1]       [nb_write_unit]
+2	2	*4	# size_execute_queue                         [2]       [nb_write_unit]
+1	1	*4	# size_execute_queue                         [3]       [nb_write_unit]
+2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
+2	2	+1	# nb_bypass_write                            [1]       [nb_write_unit]
+1	1	+1	# nb_bypass_write                            [2]       [nb_write_unit]
+4	4	+1	# nb_bypass_write                            [3]       [nb_write_unit]
+0	0	+1	# write_queue_scheme                         [0]       [nb_write_unit]
+0	1	+1	# write_queue_scheme                         [1]       [nb_write_unit]
+0	0	+1	# write_queue_scheme                         [2]       [nb_write_unit]
+0	1	+1	# write_queue_scheme                         [3]       [nb_write_unit]
+4	4	+1	# nb_gpr_bank                                	       
+2	2	+1	# nb_gpr_port_read_by_bank                   	       
+2	2	+1	# nb_gpr_port_write_by_bank                  	       
+4	4	+1	# nb_spr_bank                                	       
+1	1	+1	# nb_spr_port_read_by_bank                   	       
+1	1	+1	# nb_spr_port_write_by_bank                  	       
+64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# execution_unit_to_write_unit_priority                                         
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+0	0	+1	# execution_unit_to_write_unit_table_routing [0][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+0	0	+1	# execution_unit_to_write_unit_table_routing [0][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][1][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][1][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+0	0	+1	# execution_unit_to_write_unit_table_routing [0][1][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+0	0	+1	# execution_unit_to_write_unit_table_routing [0][1][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [1][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [2][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [3][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# read_unit_to_execution_unit_priority                                          
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [2][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [2][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [2][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [3][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [3][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [3][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
+1	1	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
+0	0	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_1_execute_3a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_1_execute_3a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_1_execute_3a.gen	(revision 145)
@@ -0,0 +1,106 @@
+Execute_loop
+4	4	+1	# nb_read_unit                              
+2	2	+1	# nb_functionnal_unit                       
+1	1	+1	# nb_load_store_unit                        
+4	4	+1	# nb_write_unit                             
+1	1	+1	# nb_context                                
+1	1	+1	# nb_front_end                              
+1	1	+1	# nb_ooo_engine                             
+32	32	+1	# nb_packet                                 
+32	32	+1	# size_general_data                         
+2	2	+1	# size_special_data                         
+4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
+8	8	*4	# size_read_queue                            [1]       [nb_read_unit]
+1	1	*4	# size_read_queue                            [2]       [nb_read_unit]
+8	8	*4	# size_read_queue                            [3]       [nb_read_unit]
+8	8	*4	# size_reservation_station                   [0]       [nb_read_unit]
+1	1	*4	# size_reservation_station                   [1]       [nb_read_unit]
+4	4	*4	# size_reservation_station                   [2]       [nb_read_unit]
+2	2	*4	# size_reservation_station                   [3]       [nb_read_unit]
+2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
+1	1	+1	# nb_inst_retire                             [1]       [nb_read_unit]
+4	4	+1	# nb_inst_retire                             [2]       [nb_read_unit]
+2	2	+1	# nb_inst_retire                             [3]       [nb_read_unit]
+1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
+1	1	+1	# nb_inst_functionnal_unit		     [1]       [nb_inst_functionnal]
+4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
+4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
+4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
+1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
+2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
+0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
+1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
+2	2	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
+2	2	*4	# size_write_queue                           [0]       [nb_write_unit]
+4	4	*4	# size_write_queue                           [1]       [nb_write_unit]
+1	1	*4	# size_write_queue                           [2]       [nb_write_unit]
+8	8	*4	# size_write_queue                           [3]       [nb_write_unit]
+0	0	*4	# size_execute_queue                         [0]       [nb_write_unit]
+4	4	*4	# size_execute_queue                         [1]       [nb_write_unit]
+2	2	*4	# size_execute_queue                         [2]       [nb_write_unit]
+1	1	*4	# size_execute_queue                         [3]       [nb_write_unit]
+2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
+2	2	+1	# nb_bypass_write                            [1]       [nb_write_unit]
+1	1	+1	# nb_bypass_write                            [2]       [nb_write_unit]
+4	4	+1	# nb_bypass_write                            [3]       [nb_write_unit]
+0	0	+1	# write_queue_scheme                         [0]       [nb_write_unit]
+0	1	+1	# write_queue_scheme                         [1]       [nb_write_unit]
+0	0	+1	# write_queue_scheme                         [2]       [nb_write_unit]
+0	1	+1	# write_queue_scheme                         [3]       [nb_write_unit]
+4	4	+1	# nb_gpr_bank                                	       
+2	2	+1	# nb_gpr_port_read_by_bank                   	       
+2	2	+1	# nb_gpr_port_write_by_bank                  	       
+4	4	+1	# nb_spr_bank                                	       
+1	1	+1	# nb_spr_port_read_by_bank                   	       
+1	1	+1	# nb_spr_port_write_by_bank                  	       
+64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# execution_unit_to_write_unit_priority                                         
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+0	0	+1	# execution_unit_to_write_unit_table_routing [0][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+0	0	+1	# execution_unit_to_write_unit_table_routing [0][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][1][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][1][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+0	0	+1	# execution_unit_to_write_unit_table_routing [0][1][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+0	0	+1	# execution_unit_to_write_unit_table_routing [0][1][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [1][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [2][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [3][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# read_unit_to_execution_unit_priority                                          
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [0][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [2][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [2][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [2][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [2][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [3][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [3][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [3][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [3][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [2][0]    [nb_execute_unit][nb_thread]    
+1	1	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
+0	0	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
+0	0	+1      # is_load_store_unit                         [2]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
+1       1       +1      # translate_num_execute_unit                 [2]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_1_execute_6a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_1_execute_6a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_1_execute_6a.gen	(revision 145)
@@ -0,0 +1,142 @@
+Execute_loop
+4	4	+1	# nb_read_unit                              
+5	5	+1	# nb_functionnal_unit                       
+1	1	+1	# nb_load_store_unit                        
+4	4	+1	# nb_write_unit                             
+1	1	+1	# nb_context                                
+1	1	+1	# nb_front_end                              
+1	1	+1	# nb_ooo_engine                             
+32	32	+1	# nb_packet                                 
+32	32	+1	# size_general_data                         
+2	2	+1	# size_special_data                         
+4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
+8	8	*4	# size_read_queue                            [1]       [nb_read_unit]
+1	1	*4	# size_read_queue                            [2]       [nb_read_unit]
+8	8	*4	# size_read_queue                            [3]       [nb_read_unit]
+8	8	*4	# size_reservation_station                   [0]       [nb_read_unit]
+1	1	*4	# size_reservation_station                   [1]       [nb_read_unit]
+4	4	*4	# size_reservation_station                   [2]       [nb_read_unit]
+2	2	*4	# size_reservation_station                   [3]       [nb_read_unit]
+2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
+1	1	+1	# nb_inst_retire                             [1]       [nb_read_unit]
+4	4	+1	# nb_inst_retire                             [2]       [nb_read_unit]
+2	2	+1	# nb_inst_retire                             [3]       [nb_read_unit]
+1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_functionnal_unit]
+1	1	+1	# nb_inst_functionnal_unit		     [1]       [nb_functionnal_unit]
+1	1	+1	# nb_inst_functionnal_unit		     [2]       [nb_functionnal_unit]
+1	1	+1	# nb_inst_functionnal_unit		     [3]       [nb_functionnal_unit]
+1	1	+1	# nb_inst_functionnal_unit		     [4]       [nb_functionnal_unit]
+4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
+4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
+4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
+1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
+2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
+0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
+1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
+2	2	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
+2	2	*4	# size_write_queue                           [0]       [nb_write_unit]
+4	4	*4	# size_write_queue                           [1]       [nb_write_unit]
+1	1	*4	# size_write_queue                           [2]       [nb_write_unit]
+8	8	*4	# size_write_queue                           [3]       [nb_write_unit]
+0	0	*4	# size_execute_queue                         [0]       [nb_write_unit]
+4	4	*4	# size_execute_queue                         [1]       [nb_write_unit]
+2	2	*4	# size_execute_queue                         [2]       [nb_write_unit]
+1	1	*4	# size_execute_queue                         [3]       [nb_write_unit]
+2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
+2	2	+1	# nb_bypass_write                            [1]       [nb_write_unit]
+1	1	+1	# nb_bypass_write                            [2]       [nb_write_unit]
+4	4	+1	# nb_bypass_write                            [3]       [nb_write_unit]
+0	0	+1	# write_queue_scheme                         [0]       [nb_write_unit]
+0	1	+1	# write_queue_scheme                         [1]       [nb_write_unit]
+0	0	+1	# write_queue_scheme                         [2]       [nb_write_unit]
+0	1	+1	# write_queue_scheme                         [3]       [nb_write_unit]
+4	4	+1	# nb_gpr_bank                                	       
+2	2	+1	# nb_gpr_port_read_by_bank                   	       
+2	2	+1	# nb_gpr_port_write_by_bank                  	       
+4	4	+1	# nb_spr_bank                                	       
+1	1	+1	# nb_spr_port_read_by_bank                   	       
+1	1	+1	# nb_spr_port_write_by_bank                  	       
+64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# execution_unit_to_write_unit_priority                                         
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+0	0	+1	# execution_unit_to_write_unit_table_routing [0][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+0	0	+1	# execution_unit_to_write_unit_table_routing [0][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][1][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][1][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+0	0	+1	# execution_unit_to_write_unit_table_routing [0][1][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+0	0	+1	# execution_unit_to_write_unit_table_routing [0][1][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [2][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [3][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [3][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [3][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [3][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [4][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [4][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [4][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [4][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [5][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [5][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [5][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [5][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [1][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [2][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [3][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# read_unit_to_execution_unit_priority                                          
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [0][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [0][3][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [0][4][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [0][5][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][3][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][4][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [1][5][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [2][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [2][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [2][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [2][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [2][3][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [2][4][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [2][5][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [3][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+0	0	+1	# read_unit_to_execution_unit_table_routing  [3][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [3][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [3][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [3][3][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [3][4][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [3][5][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [2][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [3][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [4][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [5][0]    [nb_execute_unit][nb_thread]    
+1	1	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
+0	0	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
+0	0	+1      # is_load_store_unit                         [2]       [nb_execute_unit]
+0	0	+1      # is_load_store_unit                         [3]       [nb_execute_unit]
+0	0	+1      # is_load_store_unit                         [4]       [nb_execute_unit]
+0	0	+1      # is_load_store_unit                         [5]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
+1       1       +1      # translate_num_execute_unit                 [2]       [nb_execute_unit]
+4       4       +1      # translate_num_execute_unit                 [3]       [nb_execute_unit]
+3       3       +1      # translate_num_execute_unit                 [4]       [nb_execute_unit]
+2       2       +1      # translate_num_execute_unit                 [5]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_8_execute_2a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_8_execute_2a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_8_execute_2a.gen	(revision 145)
@@ -0,0 +1,75 @@
+Execute_loop
+1	1	+1	# nb_read_unit                              
+1	1	+1	# nb_functionnal_unit                       
+1	1	+1	# nb_load_store_unit                        
+1	1	+1	# nb_write_unit                             
+2	2	+1	# nb_context                                
+2	2	+1	# nb_front_end                              
+2	2	+1	# nb_ooo_engine                             
+32	32	+1	# nb_packet                                 
+32	32	+1	# size_general_data                         
+2	2	+1	# size_special_data                         
+4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
+4	4	*4	# size_reservation_station                   [0]       [nb_read_unit]
+2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
+1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
+4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
+4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
+4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
+1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
+2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
+0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
+1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
+1	1	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
+4	4	*4	# size_write_queue                           [0]       [nb_write_unit]
+4	4	*4	# size_execute_queue                         [0]       [nb_write_unit]
+2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
+0	0	+1	# write_queue_scheme                         [0]       [nb_write_unit]
+4	4	+1	# nb_gpr_bank                                	       
+1	1	+1	# nb_gpr_port_read_by_bank                   	       
+1	1	+1	# nb_gpr_port_write_by_bank                  	       
+4	4	+1	# nb_spr_bank                                	       
+1	1	+1	# nb_spr_port_read_by_bank                   	       
+1	1	+1	# nb_spr_port_write_by_bank                  	       
+64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
+128	128	+1	# nb_general_register                        [1]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
+8	8	+1	# nb_special_register                        [1]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
+2	2	+1	# nb_inst_insert_rob                         [1]       [nb_ooo_engine]		  
+2	2	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [1]       [nb_ooo_engine]		  
+1	1	+1	# execution_unit_to_write_unit_priority                                         
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][1]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][2]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][3]    [nb_write_unit][nb_thread]	  
+0	0	+1	# execution_unit_to_write_unit_table_thread  [0][4]    [nb_write_unit][nb_thread]	  
+0	0	+1	# execution_unit_to_write_unit_table_thread  [0][5]    [nb_write_unit][nb_thread]	  
+0	0	+1	# execution_unit_to_write_unit_table_thread  [0][6]    [nb_write_unit][nb_thread]	  
+0	0	+1	# execution_unit_to_write_unit_table_thread  [0][7]    [nb_write_unit][nb_thread]	  
+1	1	+1	# read_unit_to_execution_unit_priority                                          
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][1]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][2]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][3]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][4]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][5]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][6]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][7]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][1]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][2]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][3]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][4]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][5]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][6]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][7]    [nb_execute_unit][nb_thread]    
+0	0	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
+1	1	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_8_execute_2b.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_8_execute_2b.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_8_execute_2b.gen	(revision 145)
@@ -0,0 +1,83 @@
+Execute_loop
+1	1	+1	# nb_read_unit                              
+1	1	+1	# nb_functionnal_unit                       
+1	1	+1	# nb_load_store_unit                        
+1	1	+1	# nb_write_unit                             
+2	2	+1	# nb_context                                
+1	1	+1	# nb_front_end                              
+4	4	+1	# nb_ooo_engine                             
+32	32	+1	# nb_packet                                 
+32	32	+1	# size_general_data                         
+2	2	+1	# size_special_data                         
+4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
+4	4	*4	# size_reservation_station                   [0]       [nb_read_unit]
+2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
+1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
+4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
+4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
+4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
+1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
+2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
+0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
+1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
+1	1	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
+4	4	*4	# size_write_queue                           [0]       [nb_write_unit]
+4	4	*4	# size_execute_queue                         [0]       [nb_write_unit]
+2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
+0	1	+1	# write_queue_scheme                         [0]       [nb_write_unit]
+4	4	+1	# nb_gpr_bank                                	       
+1	1	+1	# nb_gpr_port_read_by_bank                   	       
+1	1	+1	# nb_gpr_port_write_by_bank                  	       
+4	4	+1	# nb_spr_bank                                	       
+1	1	+1	# nb_spr_port_read_by_bank                   	       
+1	1	+1	# nb_spr_port_write_by_bank                  	       
+64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
+64	64	+1	# nb_general_register                        [1]       [nb_ooo_engine]		  
+64	64	+1	# nb_general_register                        [2]       [nb_ooo_engine]		  
+64	64	+1	# nb_general_register                        [3]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [1]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [2]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [3]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [1]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [2]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [3]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [1]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [2]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [3]       [nb_ooo_engine]		  
+1	1	+1	# execution_unit_to_write_unit_priority                                         
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][1]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][2]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][3]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][4]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][5]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][6]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][7]    [nb_write_unit][nb_thread]	  
+1	1	+1	# read_unit_to_execution_unit_priority                                          
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][1]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][2]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][3]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][4]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][5]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][6]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][7]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][1]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][2]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][3]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][4]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][5]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][6]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][7]    [nb_execute_unit][nb_thread]    
+0	0	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
+1	1	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_8_execute_2c.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_8_execute_2c.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration/config_thread_8_execute_2c.gen	(revision 145)
@@ -0,0 +1,99 @@
+Execute_loop
+1	1	+1	# nb_read_unit                              
+1	1	+1	# nb_functionnal_unit                       
+1	1	+1	# nb_load_store_unit                        
+1	1	+1	# nb_write_unit                             
+1	1	+1	# nb_context                                
+1	1	+1	# nb_front_end                              
+8	8	+1	# nb_ooo_engine                             
+32	32	+1	# nb_packet                                 
+32	32	+1	# size_general_data                         
+2	2	+1	# size_special_data                         
+4	4	*4	# size_read_queue                            [0]       [nb_read_unit]
+4	4	*4	# size_reservation_station                   [0]       [nb_read_unit]
+2	2	+1	# nb_inst_retire                             [0]       [nb_read_unit]
+1	1	+1	# nb_inst_functionnal_unit		     [0]       [nb_inst_functionnal]
+4	4	*2	# size_store_queue                           [0]       [nb_load_store_unit]
+4	4	*2	# size_load_queue                            [0]       [nb_load_store_unit]
+4	4	*2	# size_speculative_access_queue              [0]       [nb_load_store_unit]
+1	1	+1	# nb_port_check                              [0]       [nb_load_store_unit]
+2	2	+1	# speculative_load                           [0]       [nb_load_store_unit]
+0	0	+1	# nb_bypass_memory                           [0]       [nb_load_store_unit]
+1	1	+1	# nb_cache_port                              [0]       [nb_load_store_unit]
+1	1	+1	# nb_inst_memory                             [0]       [nb_load_store_unit]
+4	4	*4	# size_write_queue                           [0]       [nb_write_unit]
+4	4	*4	# size_execute_queue                         [0]       [nb_write_unit]
+2	2	+1	# nb_bypass_write                            [0]       [nb_write_unit]
+0	0	+1	# write_queue_scheme                         [0]       [nb_write_unit]
+4	4	+1	# nb_gpr_bank                                	       
+1	1	+1	# nb_gpr_port_read_by_bank                   	       
+1	1	+1	# nb_gpr_port_write_by_bank                  	       
+4	4	+1	# nb_spr_bank                                	       
+1	1	+1	# nb_spr_port_read_by_bank                   	       
+1	1	+1	# nb_spr_port_write_by_bank                  	       
+64	64	+1	# nb_general_register                        [0]       [nb_ooo_engine]		  
+64	64	+1	# nb_general_register                        [1]       [nb_ooo_engine]		  
+64	64	+1	# nb_general_register                        [2]       [nb_ooo_engine]		  
+64	64	+1	# nb_general_register                        [3]       [nb_ooo_engine]		  
+64	64	+1	# nb_general_register                        [4]       [nb_ooo_engine]		  
+64	64	+1	# nb_general_register                        [5]       [nb_ooo_engine]		  
+64	64	+1	# nb_general_register                        [6]       [nb_ooo_engine]		  
+64	64	+1	# nb_general_register                        [7]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [0]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [1]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [2]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [3]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [4]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [5]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [6]       [nb_ooo_engine]		  
+16	16	+1	# nb_special_register                        [7]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [1]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [2]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [3]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [4]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [5]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [6]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_insert_rob                         [7]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [0]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [1]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [2]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [3]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [4]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [5]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [6]       [nb_ooo_engine]		  
+1	1	+1	# nb_inst_retire_rob                         [7]       [nb_ooo_engine]		  
+1	1	+1	# execution_unit_to_write_unit_priority                                         
+1	1	+1	# execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit]
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][0]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][1]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][2]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][3]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][4]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][5]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][6]    [nb_write_unit][nb_thread]	  
+1	1	+1	# execution_unit_to_write_unit_table_thread  [0][7]    [nb_write_unit][nb_thread]	  
+1	1	+1	# read_unit_to_execution_unit_priority                                          
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_routing  [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port]
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][1]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][2]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][3]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][4]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][5]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][6]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [0][7]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][0]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][1]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][2]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][3]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][4]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][5]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][6]    [nb_execute_unit][nb_thread]    
+1	1	+1	# read_unit_to_execution_unit_table_thread   [1][7]    [nb_execute_unit][nb_thread]    
+0	0	+1      # is_load_store_unit                         [0]       [nb_execute_unit]
+1	1	+1      # is_load_store_unit                         [1]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [0]       [nb_execute_unit]
+0       0       +1      # translate_num_execute_unit                 [1]       [nb_execute_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp	(revision 145)
@@ -8,4 +8,5 @@
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Parameters.h"
 #include "Behavioural/include/Allocation.h"
+#include "Behavioural/include/Types.h"
 #include "Common/include/Max.h"
 
@@ -373,5 +374,15 @@
     uint32_t size_general_register   = log2(_max_nb_general_register);
     uint32_t size_special_register   = log2(_max_nb_special_register);
-    
+
+    bool speculative_commit = false;
+    for (uint32_t i=0; i<_nb_execute_unit; i++)
+      if (_is_load_store_unit [i])
+        {
+          uint32_t x = _translate_num_execute_unit [i];
+      
+          speculative_commit |=  ((_speculative_load[x] == multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD) and (_speculative_commit_predictor_scheme[x] != PREDICTOR_NEVER_TAKE));
+        }
+    log_printf(TRACE,Execute_loop,FUNCTION," * speculative_commit : %d",speculative_commit);
+
     test();
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Context_State
-1	1	+1	# nb_context
-1	1	+1	# nb_decod_unit
-1	1	+1	# nb_inst_branch_complete
-1	1	+1	# nb_inst_branch_speculated     [0] [nb_context]
-32	32	+1	# size_general_data		
-1	1	+1	# size_inst_decod               [0] [nb_decod_unit]
-1	1	+1	# size_inst_commit
-0	0	+1	# link_context_to_decod_unit    [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_mono_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Context_State
-1	1	+1	# nb_context
-1	1	*4	# nb_decod_unit
-1	4	*4	# nb_inst_branch_complete
-1	4	*2	# nb_inst_branch_speculated     [0] [nb_context]
-32	32	+1	# size_general_data		
-1	4	*4	# size_inst_decod               [0] [nb_decod_unit]
-1	4	*4	# size_inst_commit
-0	0	+1	# link_context_to_decod_unit    [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_multi_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,26 +1,0 @@
-Context_State
-8	8	+1	# nb_context
-4	4	*4	# nb_decod_unit
-2	2	*4	# nb_inst_branch_complete
-6	6	+1	# nb_inst_branch_speculated     [0] [nb_context]
-3	3	+1	# nb_inst_branch_speculated     [1] [nb_context]
-2	2	+1	# nb_inst_branch_speculated     [2] [nb_context]
-1	1	+1	# nb_inst_branch_speculated     [3] [nb_context]
-8	8	+1	# nb_inst_branch_speculated     [4] [nb_context]
-4	4	+1	# nb_inst_branch_speculated     [5] [nb_context]
-2	2	+1	# nb_inst_branch_speculated     [6] [nb_context]
-1	1	+1	# nb_inst_branch_speculated     [7] [nb_context]
-32	32	+1	# size_general_data		
-4	4	*4	# size_inst_decod               [0] [nb_decod_unit]
-1	1	*4	# size_inst_decod               [1] [nb_decod_unit]
-2	2	*4	# size_inst_decod               [2] [nb_decod_unit]
-4	4	*4	# size_inst_decod               [3] [nb_decod_unit]
-8	8	*4	# size_inst_commit
-0	0	+1	# link_context_to_decod_unit    [0] [nb_context]
-1	1	+1	# link_context_to_decod_unit    [1] [nb_context]
-2	2	+1	# link_context_to_decod_unit    [2] [nb_context]
-3	3	+1	# link_context_to_decod_unit    [3] [nb_context]
-0	0	+1	# link_context_to_decod_unit    [4] [nb_context]
-1	1	+1	# link_context_to_decod_unit    [5] [nb_context]
-2	2	+1	# link_context_to_decod_unit    [6] [nb_context]
-3	3	+1	# link_context_to_decod_unit    [7] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,9 @@
+Context_State
+1	1	+1	# nb_context
+1	1	+1	# nb_decod_unit
+1	1	+1	# nb_inst_branch_complete
+1	1	+1	# nb_inst_branch_speculated     [0] [nb_context]
+32	32	+1	# size_general_data		
+1	1	+1	# size_inst_decod               [0] [nb_decod_unit]
+1	1	+1	# size_inst_commit
+0	0	+1	# link_context_to_decod_unit    [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/configuration/config_mono_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/configuration/config_mono_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/configuration/config_mono_context.gen	(revision 145)
@@ -0,0 +1,9 @@
+Context_State
+1	1	+1	# nb_context
+1	1	*4	# nb_decod_unit
+1	4	*4	# nb_inst_branch_complete
+1	4	*2	# nb_inst_branch_speculated     [0] [nb_context]
+32	32	+1	# size_general_data		
+1	4	*4	# size_inst_decod               [0] [nb_decod_unit]
+1	4	*4	# size_inst_commit
+0	0	+1	# link_context_to_decod_unit    [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/configuration/config_multi_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/configuration/config_multi_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/configuration/config_multi_context.gen	(revision 145)
@@ -0,0 +1,26 @@
+Context_State
+8	8	+1	# nb_context
+4	4	*4	# nb_decod_unit
+2	2	*4	# nb_inst_branch_complete
+6	6	+1	# nb_inst_branch_speculated     [0] [nb_context]
+3	3	+1	# nb_inst_branch_speculated     [1] [nb_context]
+2	2	+1	# nb_inst_branch_speculated     [2] [nb_context]
+1	1	+1	# nb_inst_branch_speculated     [3] [nb_context]
+8	8	+1	# nb_inst_branch_speculated     [4] [nb_context]
+4	4	+1	# nb_inst_branch_speculated     [5] [nb_context]
+2	2	+1	# nb_inst_branch_speculated     [6] [nb_context]
+1	1	+1	# nb_inst_branch_speculated     [7] [nb_context]
+32	32	+1	# size_general_data		
+4	4	*4	# size_inst_decod               [0] [nb_decod_unit]
+1	1	*4	# size_inst_decod               [1] [nb_decod_unit]
+2	2	*4	# size_inst_decod               [2] [nb_decod_unit]
+4	4	*4	# size_inst_decod               [3] [nb_decod_unit]
+8	8	*4	# size_inst_commit
+0	0	+1	# link_context_to_decod_unit    [0] [nb_context]
+1	1	+1	# link_context_to_decod_unit    [1] [nb_context]
+2	2	+1	# link_context_to_decod_unit    [2] [nb_context]
+3	3	+1	# link_context_to_decod_unit    [3] [nb_context]
+0	0	+1	# link_context_to_decod_unit    [4] [nb_context]
+1	1	+1	# link_context_to_decod_unit    [5] [nb_context]
+2	2	+1	# link_context_to_decod_unit    [6] [nb_context]
+3	3	+1	# link_context_to_decod_unit    [7] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h	(revision 145)
@@ -32,4 +32,5 @@
       CONTEXT_STATE_KO_MISS_BRANCH_ADDR                , // update address manager
       CONTEXT_STATE_KO_MISS_BRANCH_WAITEND             , // wait end of event (miss branch)
+      CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE          , // wait end of event (miss branch)
       CONTEXT_STATE_KO_MISS_LOAD_ADDR                  , // update address manager
       CONTEXT_STATE_KO_MISS_LOAD_WAITEND               , // wait end of event (miss load))
@@ -69,4 +70,5 @@
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_ADDR                 : return "context_state_ko_miss_branch_addr"                ; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_WAITEND              : return "context_state_ko_miss_branch_waitend"             ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE           : return "context_state_ko_miss_branch_inaccurate"          ; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE : return "context_state_ko_miss_load_and_branch_wait_update"; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR        : return "context_state_ko_miss_load_and_branch_addr"       ; break;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_statistics_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_statistics_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_statistics_allocation.cpp	(revision 145)
@@ -40,14 +40,13 @@
     for (uint32_t i=0; i<_param->_nb_context; ++i)
       {
-        _stat_nb_cycle_state_ok                      [i] = _stat->create_counter("nb_cycle_state_ok_"                     +toString(i),"",toString(_("Number of cycle in state ok                      (context %d)"),i));
-        _stat_nb_cycle_state_ko_excep                [i] = _stat->create_counter("nb_cycle_state_ko_excep_"               +toString(i),"",toString(_("Number of cycle in state ko_excep                (context %d)"),i));
-        _stat_nb_cycle_state_ko_miss_branch          [i] = _stat->create_counter("nb_cycle_state_ko_miss_branch_"         +toString(i),"",toString(_("Number of cycle in state ko_miss_branch          (context %d)"),i));
-        _stat_nb_cycle_state_ko_miss_load            [i] = _stat->create_counter("nb_cycle_state_ko_miss_load_"           +toString(i),"",toString(_("Number of cycle in state ko_miss_load            (context %d)"),i));
-        _stat_nb_cycle_state_ko_miss_load_and_branch [i] = _stat->create_counter("nb_cycle_state_ko_miss_load_and_branch_"+toString(i),"",toString(_("Number of cycle in state ko_miss_load_and_branch (context %d)"),i));
-        _stat_nb_cycle_state_ko_msync                [i] = _stat->create_counter("nb_cycle_state_ko_msync_"               +toString(i),"",toString(_("Number of cycle in state ko_msync                (context %d)"),i));
-        _stat_nb_cycle_state_ko_psync                [i] = _stat->create_counter("nb_cycle_state_ko_psync_"               +toString(i),"",toString(_("Number of cycle in state ko_psync                (context %d)"),i));
-        _stat_nb_cycle_state_ko_csync                [i] = _stat->create_counter("nb_cycle_state_ko_csync_"               +toString(i),"",toString(_("Number of cycle in state ko_csync                (context %d)"),i));
-        _stat_nb_cycle_state_ko_spr                  [i] = _stat->create_counter("nb_cycle_state_ko_spr_"                 +toString(i),"",toString(_("Number of cycle in state ko_spr                  (context %d)"),i));
-
+        _stat_nb_cycle_state_ok                      [i] = _stat->create_variable("nb_cycle_state_ok_"                     +toString(i));
+        _stat_nb_cycle_state_ko_excep                [i] = _stat->create_variable("nb_cycle_state_ko_excep_"               +toString(i));
+        _stat_nb_cycle_state_ko_miss_branch          [i] = _stat->create_variable("nb_cycle_state_ko_miss_branch_"         +toString(i));
+        _stat_nb_cycle_state_ko_miss_load            [i] = _stat->create_variable("nb_cycle_state_ko_miss_load_"           +toString(i));
+        _stat_nb_cycle_state_ko_miss_load_and_branch [i] = _stat->create_variable("nb_cycle_state_ko_miss_load_and_branch_"+toString(i));
+        _stat_nb_cycle_state_ko_msync                [i] = _stat->create_variable("nb_cycle_state_ko_msync_"               +toString(i));
+        _stat_nb_cycle_state_ko_psync                [i] = _stat->create_variable("nb_cycle_state_ko_psync_"               +toString(i));
+        _stat_nb_cycle_state_ko_csync                [i] = _stat->create_variable("nb_cycle_state_ko_csync_"               +toString(i));
+        _stat_nb_cycle_state_ko_spr                  [i] = _stat->create_variable("nb_cycle_state_ko_spr_"                 +toString(i));
 
         _stat->create_expr_percent("percent_state_ok_"                     +toString(i),"nb_cycle_state_ok_"                     +toString(i),"cycle",toString(_("Percent of cycle in state ok                      (context %d)"),i));
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 145)
@@ -33,4 +33,5 @@
   (((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR                ) or  \
     (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND             ) or  \
+    (state == CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE          ) or  \
     (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE         ))?PRIORITY_MISS_BRANCH: \
    ((state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION:                           \
@@ -112,4 +113,11 @@
 //                  state = CONTEXT_STATE_OK;
                     state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE :
+                {
+                  if (inst_all == 0)
+//                  state = CONTEXT_STATE_OK;
+                    state = CONTEXT_STATE_OK;
                   break;
                 }
@@ -321,12 +329,8 @@
                       if (can_continue)
                         reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
-                      else
-                        {
-// #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)
-//                           reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
-// #else
-                          reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_WAITEND;
-// #endif
-                        }
+                      else 
+                        // cf UPT : dest_val = direction, accurate depend of jump type (e.g. jr is inacurate)
+                        // reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_WAITEND;
+                        reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE;
 
                       reg_EVENT_ADDRESS          [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC  [i])+1; // address delay slot
@@ -647,4 +651,5 @@
                         case CONTEXT_STATE_KO_MISS_BRANCH_ADDR             :
                         case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND          :
+                        case CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE       :
                         case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR    :
                         case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND :
@@ -752,4 +757,5 @@
           case CONTEXT_STATE_KO_EXCEP_SPR                       : (*_stat_nb_cycle_state_ko_excep                [i])++; break;
 
+          case CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE          : 
           case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE         : 
           case CONTEXT_STATE_KO_MISS_BRANCH_ADDR                : 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Decod
-1	1	*4	# nb_context           
-1	1	*4	# nb_inst_fetch                 [0] [nb_context]
-1	1	*4	# nb_inst_decod        
-1	1	*2	# nb_branch_speculated          [0] [nb_context]
-1	1	*2	# nb_context_select    
-32	32	*2	# size_general_data    
-1	1	+1	# priority             
-1	1	+1	# load_balancing       
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_mono_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Decod
-1	1	*4	# nb_context           
-4	16	*4	# nb_inst_fetch                 [0] [nb_context]
-1	4 	*4	# nb_inst_decod         
-1	1	*2	# nb_branch_speculated          [0] [nb_context]
-1	1	*2	# nb_context_select    
-32	32	*2	# size_general_data    
-1	1	+1	# priority             
-1	1	+1	# load_balancing       
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_multi_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,15 +1,0 @@
-Decod
-4	4	*4	# nb_context           
-1	1	*4	# nb_inst_fetch                 [0] [nb_context]
-2	2	*4	# nb_inst_fetch                 [1] [nb_context]
-4	4	*4	# nb_inst_fetch                 [2] [nb_context]
-8	8	*4	# nb_inst_fetch                 [3] [nb_context]
-1	8	*2	# nb_inst_decod        
-1	1	*2	# nb_branch_speculated          [0] [nb_context]
-0	0	*2	# nb_branch_speculated          [1] [nb_context]
-1	1	*2	# nb_branch_speculated          [2] [nb_context]
-2	2	*2	# nb_branch_speculated          [3] [nb_context]
-1	4	*2	# nb_context_select    
-32	32	*2	# size_general_data    
-1	1	+1	# priority             
-1	1	+1	# load_balancing       
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,9 @@
+Decod
+1	1	*4	# nb_context           
+1	1	*4	# nb_inst_fetch                 [0] [nb_context]
+1	1	*4	# nb_inst_decod        
+1	1	*2	# nb_branch_speculated          [0] [nb_context]
+1	1	*2	# nb_context_select    
+32	32	*2	# size_general_data    
+1	1	+1	# priority             
+1	1	+1	# load_balancing       
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/configuration/config_mono_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/configuration/config_mono_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/configuration/config_mono_context.gen	(revision 145)
@@ -0,0 +1,9 @@
+Decod
+1	1	*4	# nb_context           
+4	16	*4	# nb_inst_fetch                 [0] [nb_context]
+1	4 	*4	# nb_inst_decod         
+1	1	*2	# nb_branch_speculated          [0] [nb_context]
+1	1	*2	# nb_context_select    
+32	32	*2	# size_general_data    
+1	1	+1	# priority             
+1	1	+1	# load_balancing       
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/configuration/config_multi_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/configuration/config_multi_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/configuration/config_multi_context.gen	(revision 145)
@@ -0,0 +1,15 @@
+Decod
+4	4	*4	# nb_context           
+1	1	*4	# nb_inst_fetch                 [0] [nb_context]
+2	2	*4	# nb_inst_fetch                 [1] [nb_context]
+4	4	*4	# nb_inst_fetch                 [2] [nb_context]
+8	8	*4	# nb_inst_fetch                 [3] [nb_context]
+1	8	*2	# nb_inst_decod        
+1	1	*2	# nb_branch_speculated          [0] [nb_context]
+0	0	*2	# nb_branch_speculated          [1] [nb_context]
+1	1	*2	# nb_branch_speculated          [2] [nb_context]
+2	2	*2	# nb_branch_speculated          [3] [nb_context]
+1	4	*2	# nb_context_select    
+32	32	*2	# size_general_data    
+1	1	+1	# priority             
+1	1	+1	# load_balancing       
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp	(revision 145)
@@ -71,4 +71,5 @@
     std::list<generic::priority::select_t> * select = _priority->select();
     std::list<generic::priority::select_t>::iterator it=select->begin();
+
     for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
       {
@@ -76,13 +77,14 @@
 
         bool ifetch_val = false;
-	while ((it != select->end())    and  // have a no scanned "slot_in" ?
+
+	while ((it != select->end())    and  // have a no scanned instruction from ifetch_unit ?
 // 	       (decod_val [i] == false) and  // have not a previous selected entry?
                (ifetch_val    == false) and  // not find ifetch instruction valid
-	       (context_event_val == false)) // Have not a context_event (spr_access, exception, ...)
+	       (context_event_val == false)) // Have not a context_event (spr_access, exception, ...) (ONCE CONTEXT PER CYCLE (context state moore easy))
 	  {
 // 	    predict_val [i] = false;
 
-	    Tcontext_t x = it->grp;
-	    uint32_t   y = it->elt;
+	    Tcontext_t x = it->grp; // num_front_end
+	    uint32_t   y = it->elt; // num_instruction
 
             log_printf(TRACE,Decod,FUNCTION,"    * IFETCH [%d][%d]",x,y);    
@@ -102,4 +104,5 @@
 		Tgeneral_data_t addr = PORT_READ(in_IFETCH_ADDRESS [x][y]);
 
+                // Read instruction and set default value
 		_decod_instruction->_instruction        = PORT_READ(in_IFETCH_INSTRUCTION [x][y]);
 		_decod_instruction->_context_id         = x;
@@ -132,13 +135,11 @@
 		_decod_instruction->_branch_direction   = 0; // not necessary
 		_decod_instruction->_event_type         = EVENT_TYPE_NONE; // not necessary
-		
-
-
-                // Test IFetch exception
+
+                // Test if ifetch_unit have an exception (per example : IBERR)
                 Texception_t ifetch_exception = PORT_READ(in_IFETCH_EXCEPTION [x][y]);
 
                 if (ifetch_exception == EXCEPTION_IFETCH_NONE)
                   {
-                    // Decod !
+                    // No exception, can Decod !
                     log_printf(TRACE,Decod,FUNCTION,"      * address                : %.8x (%.8x)",addr,(addr<<2));
                     log_printf(TRACE,Decod,FUNCTION,"      * is_delay_slot          : %d",internal_CONTEXT_IS_DELAY_SLOT [x]);
@@ -150,5 +151,11 @@
                 else
                   {
-                    // No decod : nop
+                    // Exception : transform this instruction in a nop
+                    //  * INSTRUCTION_TLB  
+                    //  * INSTRUCTION_PAGE 
+                    //  * BUS_ERROR        
+
+                    log_printf(TRACE,Decod,FUNCTION,"      * exception -> change instruction in a l.nop");
+                    
                     instruction_l_nop (_decod_instruction, _decod_param[x]);
 
@@ -156,7 +163,4 @@
                     _decod_instruction->_exception     = exception_ifetch_to_exception_decod(ifetch_exception);
                     
-                    // INSTRUCTION_TLB  
-                    // INSTRUCTION_PAGE 
-                    // BUS_ERROR        
                     if (_decod_instruction->_is_delay_slot)
                       _decod_instruction->_address_next       = _decod_instruction->_address_previous;
@@ -167,13 +171,23 @@
                   }
 
-		Ttype_t      type      = _decod_instruction->_type;
-                // Depth current. If have decod a branch and i can continue : depth = depth_next
-                Tdepth_t     depth     = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0;
-                // Tcontrol_t   save_rat  = internal_CONTEXT_SAVE_RAT [x];
-                Tcontrol_t   no_execute = _decod_instruction->_no_execute;
-
+		Ttype_t             type             = _decod_instruction->_type;
+                Tdepth_t            depth            = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0;
+                Tbranch_condition_t branch_condition = _decod_instruction->_branch_condition;
+                
+                // Save RAT if instruction is a branch and is conditionnal (not l.j and not l.jal)
+
+              //Tcontrol_t          save_rat         = internal_CONTEXT_SAVE_RAT [x];
+                // Tcontrol_t          save_rat         = ((type == TYPE_BRANCH) and 
+                //                                         not ((branch_condition==BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK) or
+                //                                              (branch_condition==BRANCH_CONDITION_NONE_WITH_WRITE_STACK)));
+
+                Tcontrol_t          save_rat         = ((type == TYPE_BRANCH) and 
+                                                        not (branch_condition==BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK));
+
+                // FIXME : depth+1 valid ???????
                 if ((_param->_nb_branch_speculated[x] > 0) and have_decod_branch [x])
                   depth = (depth+1)%_param->_nb_branch_speculated[x];
-                
+
+                // Write output
 		if (_param->_have_port_context_id)
 		PORT_WRITE(out_DECOD_CONTEXT_ID    [i], x);
@@ -185,16 +199,10 @@
 		PORT_WRITE(out_DECOD_TYPE          [i], type);
 		PORT_WRITE(out_DECOD_OPERATION     [i], _decod_instruction->_operation     );
- 		PORT_WRITE(out_DECOD_NO_EXECUTE    [i], no_execute);
+ 		PORT_WRITE(out_DECOD_NO_EXECUTE    [i], _decod_instruction->_no_execute    );
 		PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot );
-		// PORT_WRITE(out_DECOD_SAVE_RAT      [i], save_rat);
-                PORT_WRITE(out_DECOD_SAVE_RAT      [i], ((type == TYPE_BRANCH) and not no_execute));
+                PORT_WRITE(out_DECOD_SAVE_RAT      [i], save_rat);
 #ifdef DEBUG
  		PORT_WRITE(out_DECOD_ADDRESS       [i], addr);
 #endif
-//                 if ((type == TYPE_BRANCH) and
-//                     ((_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_SET) or
-//                      (_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_UNSET)))
-//                 PORT_WRITE(out_DECOD_ADDRESS_NEXT  [i], _decod_instruction->_address+2);
-//                 else
                 PORT_WRITE(out_DECOD_ADDRESS_NEXT  [i], _decod_instruction->_address_next  );
 		PORT_WRITE(out_DECOD_HAS_IMMEDIAT  [i], _decod_instruction->_has_immediat  );
@@ -206,5 +214,5 @@
 		PORT_WRITE(out_DECOD_READ_RC       [i], _decod_instruction->_read_rc       );
 		PORT_WRITE(out_DECOD_NUM_REG_RC    [i], _decod_instruction->_num_reg_rc    );
-		PORT_WRITE(out_DECOD_WRITE_RD      [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0);
+		PORT_WRITE(out_DECOD_WRITE_RD      [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0); // don't write in RD if RD=0
 		PORT_WRITE(out_DECOD_NUM_REG_RD    [i], _decod_instruction->_num_reg_rd    );
 		PORT_WRITE(out_DECOD_WRITE_RE      [i], _decod_instruction->_write_re      );
@@ -224,11 +232,9 @@
                     log_printf(TRACE,Decod,FUNCTION,"        * predict_val       : %d",ifetch_ack [x][y]);
                     log_printf(TRACE,Decod,FUNCTION,"        * predict_ack       : %d",PORT_READ(in_PREDICT_ACK [i]));
-                                                         
 		    log_printf(TRACE,Decod,FUNCTION,"        * address src       : %.8x (%.8x)",_decod_instruction->_address     ,_decod_instruction->_address     <<2);
 		    log_printf(TRACE,Decod,FUNCTION,"        * address dest      : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2);
                     
-                    // test if have already decod an branch : one branch per context
-		    predict_val [i]     = not have_decod_branch [x] and ifetch_ack  [x][y] // and decod_val [i]
-		      ;
+                    // test if have already decod an branch : ONCE BRANCH PER CONTEXT
+		    predict_val [i]     = not have_decod_branch [x] and ifetch_ack  [x][y]; // and decod_val [i]
                     decod_val   [i]    &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable 		    
                     ifetch_ack  [x][y] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack
@@ -252,5 +258,5 @@
 		if (_param->_have_port_depth)
                 PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x][y]));
-		PORT_WRITE(out_PREDICT_BRANCH_CONDITION            [i],_decod_instruction->_branch_condition  );
+		PORT_WRITE(out_PREDICT_BRANCH_CONDITION            [i],branch_condition);
 // 		PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE          [i],_decod_instruction->_branch_stack_write);
 		PORT_WRITE(out_PREDICT_BRANCH_DIRECTION            [i],_decod_instruction->_branch_direction  );
@@ -266,6 +272,5 @@
 		    // speculative jump at the exception handler
 		    // if type = TYPE_BRANCH, also event_type == EVENT_TYPE_NONE
-		    context_event_val   = ifetch_ack  [x][y] // and decod_val [i]
-		      ;
+		    context_event_val   = ifetch_ack  [x][y]; // and decod_val [i]
 		    decod_val   [i]    &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable 		  
 		    ifetch_ack  [x][y] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable and decod_ack
@@ -277,5 +282,4 @@
                     CONTEXT_EVENT_ADDRESS       = _decod_instruction->_address;
                     CONTEXT_EVENT_ADDRESS_EPCR  = _decod_instruction->_address_next ;
-                
 		  }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,7 +1,0 @@
-Decod_queue
-1	1	+1	# nb_context       
-1	1	*4	# nb_inst_decod    
-1	1	*4	# size_queue       
-0       1       +1      # queue_scheme
-32	32	+1	# size_general_data
-1	1	+1	# nb_branch_speculated [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/config_mono_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,7 +1,0 @@
-Decod_queue
-1	1	+1	# nb_context       
-1	8	*2	# nb_inst_decod    
-8	16	*2	# size_queue       
-0       1       +1      # queue_scheme
-32	32	+1	# size_general_data
-1	2	+1	# nb_branch_speculated [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/config_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/config_multi_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Decod_queue
-4	4	+1	# nb_context       
-4	4	*4	# nb_inst_decod    
-16	16	*4	# size_queue       
-0       1       +1      # queue_scheme
-32	32	+1	# size_general_data
-2	2	+1	# nb_branch_speculated [0] [nb_context]
-4	4	+1	# nb_branch_speculated [1] [nb_context]
-1	1	+1	# nb_branch_speculated [2] [nb_context]
-8	8	+1	# nb_branch_speculated [3] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,7 @@
+Decod_queue
+1	1	+1	# nb_context       
+1	1	*4	# nb_inst_decod    
+1	1	*4	# size_queue       
+0       1       +1      # queue_scheme
+32	32	+1	# size_general_data
+1	1	+1	# nb_branch_speculated [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/configuration/config_mono_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/configuration/config_mono_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/configuration/config_mono_context.gen	(revision 145)
@@ -0,0 +1,7 @@
+Decod_queue
+1	1	+1	# nb_context       
+1	8	*2	# nb_inst_decod    
+8	16	*2	# size_queue       
+0       1       +1      # queue_scheme
+32	32	+1	# size_general_data
+1	2	+1	# nb_branch_speculated [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/configuration/config_multi_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/configuration/config_multi_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/configuration/config_multi_context.gen	(revision 145)
@@ -0,0 +1,10 @@
+Decod_queue
+4	4	+1	# nb_context       
+4	4	*4	# nb_inst_decod    
+16	16	*4	# size_queue       
+0       1       +1      # queue_scheme
+32	32	+1	# size_general_data
+2	2	+1	# nb_branch_speculated [0] [nb_context]
+4	4	+1	# nb_branch_speculated [1] [nb_context]
+1	1	+1	# nb_branch_speculated [2] [nb_context]
+8	8	+1	# nb_branch_speculated [3] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,11 +1,0 @@
-Decod_unit
-1	1	+1	# nb_context                   
-1	1	+1	# nb_inst_fetch                [0][nb_context]
-1	1	+1	# nb_inst_decod                
-1	1	+1	# size_queue                   
-0	1	+1	# queue_scheme
-32	32	+1	# size_general_data            
-1	1	+1	# nb_branch_speculated         [0][nb_context]
-1	1	+1	# nb_context_select            
-1	1	+1	# select_priority              
-1	1	+1	# select_load_balancing        
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_mono_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,11 +1,0 @@
-Decod_unit
-1	1	+1	# nb_context                   
-4	8	*2 	# nb_inst_fetch                [0][nb_context]
-1	4	*4	# nb_inst_decod                
-4	16	*4	# size_queue                   
-0	1	+1	# queue_scheme
-32	32	+1	# size_general_data            
-1	1	*4	# nb_branch_speculated         [0][nb_context]
-1	1	+1	# nb_context_select            
-1	1	+1	# select_priority              
-1	1	+1	# select_load_balancing        
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_multi_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,17 +1,0 @@
-Decod_unit
-4	4	+1	# nb_context                   
-4	4	*4	# nb_inst_fetch                [0][nb_context]
-2	2	*4	# nb_inst_fetch                 [1][nb_context]
-1	1	*4	# nb_inst_fetch                 [2][nb_context]
-8	8	*4	# nb_inst_fetch                 [3][nb_context]
-1	8 	*4	# nb_inst_decod                 
-16	16	*4	# size_queue                    
-0	1	+1	# queue_scheme
-32	32	+1	# size_general_data             
-1	1	*4	# nb_branch_speculated          [0][nb_context]
-2	2	*4	# nb_branch_speculated          [1][nb_context]
-1	1	*4	# nb_branch_speculated          [2][nb_context]
-4	4	*4	# nb_branch_speculated          [3][nb_context]
-1	4	*4	# nb_context_select            
-1	1	+1	# select_priority              
-1	1	+1	# select_load_balancing        
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,11 @@
+Decod_unit
+1	1	+1	# nb_context                   
+1	1	+1	# nb_inst_fetch                [0][nb_context]
+1	1	+1	# nb_inst_decod                
+1	1	+1	# size_queue                   
+0	1	+1	# queue_scheme
+32	32	+1	# size_general_data            
+1	1	+1	# nb_branch_speculated         [0][nb_context]
+1	1	+1	# nb_context_select            
+1	1	+1	# select_priority              
+1	1	+1	# select_load_balancing        
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/configuration/config_mono_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/configuration/config_mono_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/configuration/config_mono_context.gen	(revision 145)
@@ -0,0 +1,11 @@
+Decod_unit
+1	1	+1	# nb_context                   
+4	8	*2 	# nb_inst_fetch                [0][nb_context]
+1	4	*4	# nb_inst_decod                
+4	16	*4	# size_queue                   
+0	1	+1	# queue_scheme
+32	32	+1	# size_general_data            
+1	1	*4	# nb_branch_speculated         [0][nb_context]
+1	1	+1	# nb_context_select            
+1	1	+1	# select_priority              
+1	1	+1	# select_load_balancing        
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/configuration/config_multi_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/configuration/config_multi_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/configuration/config_multi_context.gen	(revision 145)
@@ -0,0 +1,17 @@
+Decod_unit
+4	4	+1	# nb_context                   
+4	4	*4	# nb_inst_fetch                [0][nb_context]
+2	2	*4	# nb_inst_fetch                 [1][nb_context]
+1	1	*4	# nb_inst_fetch                 [2][nb_context]
+8	8	*4	# nb_inst_fetch                 [3][nb_context]
+1	8 	*4	# nb_inst_decod                 
+16	16	*4	# size_queue                    
+0	1	+1	# queue_scheme
+32	32	+1	# size_general_data             
+1	1	*4	# nb_branch_speculated          [0][nb_context]
+2	2	*4	# nb_branch_speculated          [1][nb_context]
+1	1	*4	# nb_branch_speculated          [2][nb_context]
+4	4	*4	# nb_branch_speculated          [3][nb_context]
+1	4	*4	# nb_context_select            
+1	1	+1	# select_priority              
+1	1	+1	# select_load_balancing        
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_1-decod_unit_1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_1-decod_unit_1.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Front_end_Glue
-1	1	+1	# nb_context                     
-1	1	+1	# nb_decod_unit                  
-1	1	+1	# nb_inst_decod              [0] [nb_decod_unit]
-1	1	+1	# nb_inst_branch_complete        
-0	0	+1	# link_context_to_decod_unit [0] [nb_context]
-30	30	+1	# size_address                   
-2	2	+1	# size_depth                 [0] [nb_context]
-4	4	+1	# nb_branch_speculated       [0] [nb_context]
-4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_1.cfg	(revision 144)
+++ 	(revision )
@@ -1,19 +1,0 @@
-Front_end_Glue
-4	4	+1	# nb_context                     
-1	1	+1	# nb_decod_unit                  
-1	1	+1	# nb_inst_decod              [0] [nb_decod_unit]
-1	1	+1	# nb_inst_branch_complete        
-0	0	+1	# link_context_to_decod_unit [0] [nb_context]
-0	0	+1	# link_context_to_decod_unit [1] [nb_context]
-0	0	+1	# link_context_to_decod_unit [2] [nb_context]
-0	0	+1	# link_context_to_decod_unit [3] [nb_context]
-30	30	+1	# size_address                   
-2	2	+1	# size_depth                 [0] [nb_context]
-0	0	+1	# size_depth                 [1] [nb_context]
-1	1	+1	# size_depth                 [2] [nb_context]
-3	3	+1	# size_depth                 [3] [nb_context]
-4	4	+1	# nb_branch_speculated       [0] [nb_context]
-1	1	+1	# nb_branch_speculated       [1] [nb_context]
-2	2	+1	# nb_branch_speculated       [2] [nb_context]
-8	8	+1	# nb_branch_speculated       [3] [nb_context]
-4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-a.cfg	(revision 144)
+++ 	(revision )
@@ -1,20 +1,0 @@
-Front_end_Glue
-4	4	+1	# nb_context                     
-2	2	+1	# nb_decod_unit                  
-4	4	+1	# nb_inst_decod              [0] [nb_decod_unit]
-1	1	+1	# nb_inst_decod              [1] [nb_decod_unit]
-1	1	+1	# nb_inst_branch_complete        
-0	0	+1	# link_context_to_decod_unit [0] [nb_context]
-1	1	+1	# link_context_to_decod_unit [1] [nb_context]
-0	0	+1	# link_context_to_decod_unit [2] [nb_context]
-1	1	+1	# link_context_to_decod_unit [3] [nb_context]
-30	30	+1	# size_address                   
-2	2	+1	# size_depth                 [0] [nb_context]
-0	0	+1	# size_depth                 [1] [nb_context]
-1	1	+1	# size_depth                 [2] [nb_context]
-3	3	+1	# size_depth                 [3] [nb_context]
-4	4	+1	# nb_branch_speculated       [0] [nb_context]
-1	1	+1	# nb_branch_speculated       [1] [nb_context]
-2	2	+1	# nb_branch_speculated       [2] [nb_context]
-8	8	+1	# nb_branch_speculated       [3] [nb_context]
-4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-b.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-b.cfg	(revision 144)
+++ 	(revision )
@@ -1,20 +1,0 @@
-Front_end_Glue
-4	4	+1	# nb_context                     
-2	2	+1	# nb_decod_unit                  
-4	4	+1	# nb_inst_decod              [0] [nb_decod_unit]
-1	1	+1	# nb_inst_decod              [1] [nb_decod_unit]
-1	1	+1	# nb_inst_branch_complete        
-0	0	+1	# link_context_to_decod_unit [0] [nb_context]
-1	1	+1	# link_context_to_decod_unit [1] [nb_context]
-1	1	+1	# link_context_to_decod_unit [2] [nb_context]
-1	1	+1	# link_context_to_decod_unit [3] [nb_context]
-30	30	+1	# size_address                   
-2	2	+1	# size_depth                 [0] [nb_context]
-0	0	+1	# size_depth                 [1] [nb_context]
-1	1	+1	# size_depth                 [2] [nb_context]
-3	3	+1	# size_depth                 [3] [nb_context]
-4	4	+1	# nb_branch_speculated       [0] [nb_context]
-1	1	+1	# nb_branch_speculated       [1] [nb_context]
-2	2	+1	# nb_branch_speculated       [2] [nb_context]
-8	8	+1	# nb_branch_speculated       [3] [nb_context]
-4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_4.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_4.cfg	(revision 144)
+++ 	(revision )
@@ -1,22 +1,0 @@
-Front_end_Glue
-4	4	+1	# nb_context                     
-4	4	+1	# nb_decod_unit                  
-2	2	+1	# nb_inst_decod              [0] [nb_decod_unit]
-4	4	+1	# nb_inst_decod              [1] [nb_decod_unit]
-1	1	+1	# nb_inst_decod              [2] [nb_decod_unit]
-8	8	+1	# nb_inst_decod              [3] [nb_decod_unit]
-1	1	+1	# nb_inst_branch_complete        
-1	1	+1	# link_context_to_decod_unit [0] [nb_context]
-0	0	+1	# link_context_to_decod_unit [1] [nb_context]
-3	3	+1	# link_context_to_decod_unit [2] [nb_context]
-2	2	+1	# link_context_to_decod_unit [3] [nb_context]
-30	30	+1	# size_address                   
-2	2	+1	# size_depth                 [0] [nb_context]
-0	0	+1	# size_depth                 [1] [nb_context]
-1	1	+1	# size_depth                 [2] [nb_context]
-3	3	+1	# size_depth                 [3] [nb_context]
-4	4	+1	# nb_branch_speculated       [0] [nb_context]
-1	1	+1	# nb_branch_speculated       [1] [nb_context]
-2	2	+1	# nb_branch_speculated       [2] [nb_context]
-8	8	+1	# nb_branch_speculated       [3] [nb_context]
-4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Front_end_Glue
-1	1	+1	# nb_context                     
-1	1	+1	# nb_decod_unit                  
-1	1	+1	# nb_inst_decod              [0] [nb_decod_unit]
-1	1	+1	# nb_inst_branch_complete        
-0	0	+1	# link_context_to_decod_unit [0] [nb_context]
-30	30	+1	# size_address                   
-0	0	+1	# size_depth                 [0] [nb_context]
-1	1	+1	# nb_branch_speculated       [0] [nb_context]
-1       1       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_1-decod_unit_1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_1-decod_unit_1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_1-decod_unit_1.gen	(revision 145)
@@ -0,0 +1,10 @@
+Front_end_Glue
+1	1	+1	# nb_context                     
+1	1	+1	# nb_decod_unit                  
+1	1	+1	# nb_inst_decod              [0] [nb_decod_unit]
+1	1	+1	# nb_inst_branch_complete        
+0	0	+1	# link_context_to_decod_unit [0] [nb_context]
+30	30	+1	# size_address                   
+2	2	+1	# size_depth                 [0] [nb_context]
+4	4	+1	# nb_branch_speculated       [0] [nb_context]
+4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_4-decod_unit_1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_4-decod_unit_1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_4-decod_unit_1.gen	(revision 145)
@@ -0,0 +1,19 @@
+Front_end_Glue
+4	4	+1	# nb_context                     
+1	1	+1	# nb_decod_unit                  
+1	1	+1	# nb_inst_decod              [0] [nb_decod_unit]
+1	1	+1	# nb_inst_branch_complete        
+0	0	+1	# link_context_to_decod_unit [0] [nb_context]
+0	0	+1	# link_context_to_decod_unit [1] [nb_context]
+0	0	+1	# link_context_to_decod_unit [2] [nb_context]
+0	0	+1	# link_context_to_decod_unit [3] [nb_context]
+30	30	+1	# size_address                   
+2	2	+1	# size_depth                 [0] [nb_context]
+0	0	+1	# size_depth                 [1] [nb_context]
+1	1	+1	# size_depth                 [2] [nb_context]
+3	3	+1	# size_depth                 [3] [nb_context]
+4	4	+1	# nb_branch_speculated       [0] [nb_context]
+1	1	+1	# nb_branch_speculated       [1] [nb_context]
+2	2	+1	# nb_branch_speculated       [2] [nb_context]
+8	8	+1	# nb_branch_speculated       [3] [nb_context]
+4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_4-decod_unit_2-a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_4-decod_unit_2-a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_4-decod_unit_2-a.gen	(revision 145)
@@ -0,0 +1,20 @@
+Front_end_Glue
+4	4	+1	# nb_context                     
+2	2	+1	# nb_decod_unit                  
+4	4	+1	# nb_inst_decod              [0] [nb_decod_unit]
+1	1	+1	# nb_inst_decod              [1] [nb_decod_unit]
+1	1	+1	# nb_inst_branch_complete        
+0	0	+1	# link_context_to_decod_unit [0] [nb_context]
+1	1	+1	# link_context_to_decod_unit [1] [nb_context]
+0	0	+1	# link_context_to_decod_unit [2] [nb_context]
+1	1	+1	# link_context_to_decod_unit [3] [nb_context]
+30	30	+1	# size_address                   
+2	2	+1	# size_depth                 [0] [nb_context]
+0	0	+1	# size_depth                 [1] [nb_context]
+1	1	+1	# size_depth                 [2] [nb_context]
+3	3	+1	# size_depth                 [3] [nb_context]
+4	4	+1	# nb_branch_speculated       [0] [nb_context]
+1	1	+1	# nb_branch_speculated       [1] [nb_context]
+2	2	+1	# nb_branch_speculated       [2] [nb_context]
+8	8	+1	# nb_branch_speculated       [3] [nb_context]
+4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_4-decod_unit_2-b.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_4-decod_unit_2-b.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_4-decod_unit_2-b.gen	(revision 145)
@@ -0,0 +1,20 @@
+Front_end_Glue
+4	4	+1	# nb_context                     
+2	2	+1	# nb_decod_unit                  
+4	4	+1	# nb_inst_decod              [0] [nb_decod_unit]
+1	1	+1	# nb_inst_decod              [1] [nb_decod_unit]
+1	1	+1	# nb_inst_branch_complete        
+0	0	+1	# link_context_to_decod_unit [0] [nb_context]
+1	1	+1	# link_context_to_decod_unit [1] [nb_context]
+1	1	+1	# link_context_to_decod_unit [2] [nb_context]
+1	1	+1	# link_context_to_decod_unit [3] [nb_context]
+30	30	+1	# size_address                   
+2	2	+1	# size_depth                 [0] [nb_context]
+0	0	+1	# size_depth                 [1] [nb_context]
+1	1	+1	# size_depth                 [2] [nb_context]
+3	3	+1	# size_depth                 [3] [nb_context]
+4	4	+1	# nb_branch_speculated       [0] [nb_context]
+1	1	+1	# nb_branch_speculated       [1] [nb_context]
+2	2	+1	# nb_branch_speculated       [2] [nb_context]
+8	8	+1	# nb_branch_speculated       [3] [nb_context]
+4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_4-decod_unit_4.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_4-decod_unit_4.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-context_4-decod_unit_4.gen	(revision 145)
@@ -0,0 +1,22 @@
+Front_end_Glue
+4	4	+1	# nb_context                     
+4	4	+1	# nb_decod_unit                  
+2	2	+1	# nb_inst_decod              [0] [nb_decod_unit]
+4	4	+1	# nb_inst_decod              [1] [nb_decod_unit]
+1	1	+1	# nb_inst_decod              [2] [nb_decod_unit]
+8	8	+1	# nb_inst_decod              [3] [nb_decod_unit]
+1	1	+1	# nb_inst_branch_complete        
+1	1	+1	# link_context_to_decod_unit [0] [nb_context]
+0	0	+1	# link_context_to_decod_unit [1] [nb_context]
+3	3	+1	# link_context_to_decod_unit [2] [nb_context]
+2	2	+1	# link_context_to_decod_unit [3] [nb_context]
+30	30	+1	# size_address                   
+2	2	+1	# size_depth                 [0] [nb_context]
+0	0	+1	# size_depth                 [1] [nb_context]
+1	1	+1	# size_depth                 [2] [nb_context]
+3	3	+1	# size_depth                 [3] [nb_context]
+4	4	+1	# nb_branch_speculated       [0] [nb_context]
+1	1	+1	# nb_branch_speculated       [1] [nb_context]
+2	2	+1	# nb_branch_speculated       [2] [nb_context]
+8	8	+1	# nb_branch_speculated       [3] [nb_context]
+4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,10 @@
+Front_end_Glue
+1	1	+1	# nb_context                     
+1	1	+1	# nb_decod_unit                  
+1	1	+1	# nb_inst_decod              [0] [nb_decod_unit]
+1	1	+1	# nb_inst_branch_complete        
+0	0	+1	# link_context_to_decod_unit [0] [nb_context]
+30	30	+1	# size_address                   
+0	0	+1	# size_depth                 [0] [nb_context]
+1	1	+1	# nb_branch_speculated       [0] [nb_context]
+1       1       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,4 +1,0 @@
-Address_management
-1	8	*2	# nb_instruction               
-30	30 	*2	# size_address                 
-1	4	*4	# size_branch_update_prediction
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,4 @@
+Address_management
+1	8	*2	# nb_instruction               
+30	30 	*2	# size_address                 
+1	4	*4	# size_branch_update_prediction
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,5 +1,0 @@
-Ifetch_queue
-1	1 	*2	# _size_queue                   
-1	1	*2	# _nb_instruction               
-1	1	*2	# _size_branch_update_prediction
-32	32	*2	# _size_general_data            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,5 +1,0 @@
-Ifetch_queue
-8	16	*2	# _size_queue                   
-1	8	*2	# _nb_instruction               
-1	1	*2	# _size_branch_update_prediction
-32	32	*2	# _size_general_data            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,5 @@
+Ifetch_queue
+1	1 	*2	# _size_queue                   
+1	1	*2	# _nb_instruction               
+1	1	*2	# _size_branch_update_prediction
+32	32	*2	# _size_general_data            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,5 @@
+Ifetch_queue
+8	16	*2	# _size_queue                   
+1	8	*2	# _nb_instruction               
+1	1	*2	# _size_branch_update_prediction
+32	32	*2	# _size_general_data            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_full_assoc_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_full_assoc_transition.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_full_assoc_transition.cpp	(revision 145)
@@ -205,17 +205,20 @@
 	for (uint32_t i=0; i<_param->_size_queue; i++)
 	  {
+            uint32_t index=(i+reg_PTR_READ)%_param->_size_queue;
+
             log_printf(TRACE,Ifetch_queue,FUNCTION,"    * [%d] 0x%.8x (0x%.8x) %d - %d %d %d - %s",
-                       i, 
-                       _queue [i]->_address,
-                       _queue [i]->_address<<2,
-                       _queue [i]->_inst_ifetch_ptr,
-                       _queue [i]->_branch_state,
-                       _queue [i]->_branch_update_prediction_id,
-                       _queue [i]->_exception,
-                       toString(_queue [i]->_state).c_str()
+                       index, 
+                       _queue [index]->_address,
+                       _queue [index]->_address<<2,
+                       _queue [index]->_inst_ifetch_ptr,
+                       _queue [index]->_branch_state,
+                       _queue [index]->_branch_update_prediction_id,
+                       _queue [index]->_exception,
+                       toString(_queue [index]->_state).c_str()
                        );
 	    
-	    for (uint32_t j=0; j<_param->_nb_instruction; j++)
-	      log_printf(TRACE,Ifetch_queue,FUNCTION,"      * %d 0x%.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]);
+            if (_queue [index]->_state != IFETCH_QUEUE_STATE_EMPTY)
+              for (uint32_t j=0; j<_param->_nb_instruction; j++)
+                log_printf(TRACE,Ifetch_queue,FUNCTION,"      * %d 0x%.8x (0x%.8x)", _queue [index]->_instruction_enable[j], _queue [index]->_instruction[j],(_queue [index]->_address+j)<<2);
 	  }
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_no_assoc_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_no_assoc_transition.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_no_assoc_transition.cpp	(revision 145)
@@ -173,17 +173,19 @@
 	for (uint32_t i=0; i<_param->_size_queue; i++)
 	  {
+            uint32_t index=(i+reg_PTR_READ)%_param->_size_queue;
             log_printf(TRACE,Ifetch_queue,FUNCTION,"    * [%d] 0x%.8x (0x%.8x) %d - %d %d %d - %s",
-                       i, 
-                       _queue [i]->_address,
-                       _queue [i]->_address<<2,
-                       _queue [i]->_inst_ifetch_ptr,
-                       _queue [i]->_branch_state,
-                       _queue [i]->_branch_update_prediction_id,
-                       _queue [i]->_exception,
-                       toString(_queue [i]->_state).c_str()
+                       index, 
+                       _queue [index]->_address,
+                       _queue [index]->_address<<2,
+                       _queue [index]->_inst_ifetch_ptr,
+                       _queue [index]->_branch_state,
+                       _queue [index]->_branch_update_prediction_id,
+                       _queue [index]->_exception,
+                       toString(_queue [index]->_state).c_str()
                        );
 	    
-	    for (uint32_t j=0; j<_param->_nb_instruction; j++)
-	      log_printf(TRACE,Ifetch_queue,FUNCTION,"      * %d 0x%.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]);
+            if (_queue [index]->_state != IFETCH_QUEUE_STATE_EMPTY)
+              for (uint32_t j=0; j<_param->_nb_instruction; j++)
+                log_printf(TRACE,Ifetch_queue,FUNCTION,"      * %d 0x%.8x (0x%.8x)", _queue [index]->_instruction_enable[j], _queue [index]->_instruction[j],(_queue [index]->_address+j)<<2);
 	  }
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,2 +1,0 @@
-Ifetch_unit_Glue
-30	30	+32	# size_address
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,2 @@
+Ifetch_unit_Glue
+30	30	+32	# size_address
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config.cfg	(revision 144)
+++ 	(revision )
@@ -1,5 +1,0 @@
-Ifetch_unit
-8	16	*2	# _size_queue                   
-1	8	*2	# _nb_instruction               
-1	1	*2	# _size_branch_update_prediction
-30	30	*2	# _size_general_data            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,5 +1,0 @@
-Ifetch_unit
-1	1	*2	# size_queue                   
-1	1	*2	# nb_instruction               
-1	1	*2	# size_branch_update_prediction
-30	30	*2	# size_general_data            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/configuration/config.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/configuration/config.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/configuration/config.gen	(revision 145)
@@ -0,0 +1,5 @@
+Ifetch_unit
+8	16	*2	# _size_queue                   
+1	8	*2	# _nb_instruction               
+1	1	*2	# _size_branch_update_prediction
+30	30	*2	# _size_general_data            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,5 @@
+Ifetch_unit
+1	1	*2	# size_queue                   
+1	1	*2	# nb_instruction               
+1	1	*2	# size_branch_update_prediction
+30	30	*2	# size_general_data            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/config.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/config.cfg	(revision 144)
+++ 	(revision )
@@ -1,8 +1,0 @@
-Branch_Target_Buffer_Glue
-1	4	*4	# max_nb_instruction
-4	16	*4	# size_buffer       
-1	4	*4	# associativity     
-32	32	*4	# size_address      
-1	4	*4	# nb_inst_predict   
-1	4	*4	# nb_inst_decod     
-1	4	*4	# nb_inst_update    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,8 +1,0 @@
-Branch_Target_Buffer_Glue
-1	1	*4	# max_nb_instruction
-1	1 	*4	# size_buffer       
-1	1	*4	# associativity     
-32	32	*4	# size_address      
-1	1	*4	# nb_inst_predict   
-1	1	*4	# nb_inst_decod     
-1	1	*4	# nb_inst_update    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/configuration/config.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/configuration/config.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/configuration/config.gen	(revision 145)
@@ -0,0 +1,8 @@
+Branch_Target_Buffer_Glue
+1	4	*4	# max_nb_instruction
+4	16	*4	# size_buffer       
+1	4	*4	# associativity     
+32	32	*4	# size_address      
+1	4	*4	# nb_inst_predict   
+1	4	*4	# nb_inst_decod     
+1	4	*4	# nb_inst_update    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,8 @@
+Branch_Target_Buffer_Glue
+1	1	*4	# max_nb_instruction
+1	1 	*4	# size_buffer       
+1	1	*4	# associativity     
+32	32	*4	# size_address      
+1	1	*4	# nb_inst_predict   
+1	1	*4	# nb_inst_decod     
+1	1	*4	# nb_inst_update    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Branch_Target_Buffer_Register
-1	1	+1	# nb_context     
-1 	1  	*2	# nb_instruction [0] [nb_context]
-1 	1	*4	# size_buffer    
-1 	1	*4	# associativity  
-30	30	*2	# size_address   
-2	2	+1	# size_counter   
-1	1	*4	# nb_inst_predict
-1	1	*4	# nb_inst_decod  
-1	1  	*4	# nb_inst_commit 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_mono_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Branch_Target_Buffer_Register
-1	1	+1	# nb_context     
-1 	4   	*2	# nb_instruction [0] [nb_context]
-16	16	*4	# size_buffer    
-2 	16	*4	# associativity  
-30	30	*2	# size_address   
-2	2	+1	# size_counter   
-1	4	*4	# nb_inst_predict
-1	4	*4	# nb_inst_decod  
-1	4  	*4	# nb_inst_commit 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_multi_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,13 +1,0 @@
-Branch_Target_Buffer_Register
-4	4	+1	# nb_context     
-1	1	+1	# nb_instruction [0] [nb_context]
-2	2	+1	# nb_instruction [1] [nb_context]
-4	4	+1	# nb_instruction [2] [nb_context]
-8	8	+1	# nb_instruction [3] [nb_context]
-8 	64	*4	# size_buffer    
-4	8	*2	# associativity  
-30	30	*2	# size_address   
-2	2	+1	# size_counter   
-1	4	*4	# nb_inst_predict
-1	4	*4	# nb_inst_decod  
-1	4	*4	# nb_inst_commit 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,10 @@
+Branch_Target_Buffer_Register
+1	1	+1	# nb_context     
+1 	1  	*2	# nb_instruction [0] [nb_context]
+1 	1	*4	# size_buffer    
+1 	1	*4	# associativity  
+30	30	*2	# size_address   
+2	2	+1	# size_counter   
+1	1	*4	# nb_inst_predict
+1	1	*4	# nb_inst_decod  
+1	1  	*4	# nb_inst_commit 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/configuration/config_mono_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/configuration/config_mono_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/configuration/config_mono_context.gen	(revision 145)
@@ -0,0 +1,10 @@
+Branch_Target_Buffer_Register
+1	1	+1	# nb_context     
+1 	4   	*2	# nb_instruction [0] [nb_context]
+16	16	*4	# size_buffer    
+2 	16	*4	# associativity  
+30	30	*2	# size_address   
+2	2	+1	# size_counter   
+1	4	*4	# nb_inst_predict
+1	4	*4	# nb_inst_decod  
+1	4  	*4	# nb_inst_commit 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/configuration/config_multi_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/configuration/config_multi_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/configuration/config_multi_context.gen	(revision 145)
@@ -0,0 +1,13 @@
+Branch_Target_Buffer_Register
+4	4	+1	# nb_context     
+1	1	+1	# nb_instruction [0] [nb_context]
+2	2	+1	# nb_instruction [1] [nb_context]
+4	4	+1	# nb_instruction [2] [nb_context]
+8	8	+1	# nb_instruction [3] [nb_context]
+8 	64	*4	# size_buffer    
+4	8	*2	# associativity  
+30	30	*2	# size_address   
+2	2	+1	# size_counter   
+1	4	*4	# nb_inst_predict
+1	4	*4	# nb_inst_decod  
+1	4	*4	# nb_inst_commit 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,11 +1,0 @@
-Branch_Target_Buffer
-1	1	+1	# nb_context     
-1 	1   	*2	# nb_instruction [0] [nb_context]
-1 	1 	*4	# size_buffer    
-1 	1 	*4	# associativity  
-30	30	*2	# size_address   
-2	2	+1	# size_counter   
-1	1	*4	# nb_inst_predict
-1	1	*4	# nb_inst_decod  
-1	1  	*4	# nb_inst_commit 
-3	3	+1	# victim_scheme
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_mono_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,11 +1,0 @@
-Branch_Target_Buffer
-1	1	+1	# nb_context     
-1 	4   	*2	# nb_instruction [0] [nb_context]
-16	16	*4	# size_buffer    
-2 	16	*4	# associativity  
-30	30	*2	# size_address   
-2	2	+1	# size_counter   
-1	4	*4	# nb_inst_predict
-1	4	*4	# nb_inst_decod  
-1	4  	*4	# nb_inst_commit 
-3	3	+1	# victim_scheme
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_multi_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,14 +1,0 @@
-Branch_Target_Buffer
-4	4	+1	# nb_context     
-1	1	+1	# nb_instruction [0] [nb_context]
-2	2	+1	# nb_instruction [1] [nb_context]
-4	4	+1	# nb_instruction [2] [nb_context]
-8	8	+1	# nb_instruction [3] [nb_context]
-8 	64	*4	# size_buffer    
-4	8	*2	# associativity  
-30	30	*2	# size_address   
-2	2	+1	# size_counter   
-1	4	*4	# nb_inst_predict
-1	4	*4	# nb_inst_decod  
-1	4	*4	# nb_inst_commit 
-3	3	+1	# victim_scheme
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,11 @@
+Branch_Target_Buffer
+1	1	+1	# nb_context     
+1 	1   	*2	# nb_instruction [0] [nb_context]
+1 	1 	*4	# size_buffer    
+1 	1 	*4	# associativity  
+30	30	*2	# size_address   
+2	2	+1	# size_counter   
+1	1	*4	# nb_inst_predict
+1	1	*4	# nb_inst_decod  
+1	1  	*4	# nb_inst_commit 
+3	3	+1	# victim_scheme
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/configuration/config_mono_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/configuration/config_mono_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/configuration/config_mono_context.gen	(revision 145)
@@ -0,0 +1,11 @@
+Branch_Target_Buffer
+1	1	+1	# nb_context     
+1 	4   	*2	# nb_instruction [0] [nb_context]
+16	16	*4	# size_buffer    
+2 	16	*4	# associativity  
+30	30	*2	# size_address   
+2	2	+1	# size_counter   
+1	4	*4	# nb_inst_predict
+1	4	*4	# nb_inst_decod  
+1	4  	*4	# nb_inst_commit 
+3	3	+1	# victim_scheme
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/configuration/config_multi_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/configuration/config_multi_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/configuration/config_multi_context.gen	(revision 145)
@@ -0,0 +1,14 @@
+Branch_Target_Buffer
+4	4	+1	# nb_context     
+1	1	+1	# nb_instruction [0] [nb_context]
+2	2	+1	# nb_instruction [1] [nb_context]
+4	4	+1	# nb_instruction [2] [nb_context]
+8	8	+1	# nb_instruction [3] [nb_context]
+8 	64	*4	# size_buffer    
+4	8	*2	# associativity  
+30	30	*2	# size_address   
+2	2	+1	# size_counter   
+1	4	*4	# nb_inst_predict
+1	4	*4	# nb_inst_decod  
+1	4	*4	# nb_inst_commit 
+3	3	+1	# victim_scheme
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-Direction_Glue
-0	8	+1	# predictor_scheme
-1	4	*4	# nb_inst_predict 
-1	4	*4	# nb_inst_update  
-32	32	*4	# size_address    
-1	4	*4	# size_history    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,6 @@
+Direction_Glue
+0	8	+1	# predictor_scheme
+1	4	*4	# nb_inst_predict 
+1	4	*4	# nb_inst_update  
+32	32	*4	# size_address    
+1	4	*4	# size_history    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/config_meta_predictor.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/config_meta_predictor.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Meta_Predictor_Glue
-4       4       +1 # nb_inst_predict
-4       4       +1 # nb_inst_update
-3	3	+1 # nb_predictor                   
-8	8	+1 # predictor_size_history         [0] [nb_predictor]
-17	17	+1 # predictor_size_history         [1] [nb_predictor]
-4	4	+1 # predictor_size_history         [2] [nb_predictor]
-1	1	+1 # predictor_update_on_prediction [0] [nb_predictor]
-1	1	+1 # predictor_update_on_prediction [1] [nb_predictor]
-0	0	+1 # predictor_update_on_prediction [2] [nb_predictor]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/config_two_level.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/config_two_level.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-Meta_Predictor_Glue
-4       4       +1 # nb_inst_predict
-4       4       +1 # nb_inst_update
-1	1	+1 # nb_predictor                   
-16	16	+1 # predictor_size_history         [0] [nb_predictor]
-1	1	+1 # predictor_update_on_prediction [0] [nb_predictor]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/configuration/config_meta_predictor.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/configuration/config_meta_predictor.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/configuration/config_meta_predictor.gen	(revision 145)
@@ -0,0 +1,10 @@
+Meta_Predictor_Glue
+4       4       +1 # nb_inst_predict
+4       4       +1 # nb_inst_update
+3	3	+1 # nb_predictor                   
+8	8	+1 # predictor_size_history         [0] [nb_predictor]
+17	17	+1 # predictor_size_history         [1] [nb_predictor]
+4	4	+1 # predictor_size_history         [2] [nb_predictor]
+1	1	+1 # predictor_update_on_prediction [0] [nb_predictor]
+1	1	+1 # predictor_update_on_prediction [1] [nb_predictor]
+0	0	+1 # predictor_update_on_prediction [2] [nb_predictor]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/configuration/config_two_level.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/configuration/config_two_level.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/configuration/config_two_level.gen	(revision 145)
@@ -0,0 +1,6 @@
+Meta_Predictor_Glue
+4       4       +1 # nb_inst_predict
+4       4       +1 # nb_inst_update
+1	1	+1 # nb_predictor                   
+16	16	+1 # predictor_size_history         [0] [nb_predictor]
+1	1	+1 # predictor_update_on_prediction [0] [nb_predictor]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/SelfTest/config-alpha_21264.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/SelfTest/config-alpha_21264.cfg	(revision 144)
+++ 	(revision )
@@ -1,25 +1,0 @@
-Meta_Predictor
-1       1       +1      # nb_inst_predict
-1       1       +1      # nb_inst_update
-30      30      *2      # size_address
-1       1       +1      # predictor_0_have_bht              
-10      10      +1      # predictor_0_bht_size_shifter      
-1024    1024    *2      # predictor_0_bht_nb_shifter
-1       1       +1      # predictor_0_have_pht              
-3       3       +1      # predictor_0_pht_size_counter      
-1024    1024    *2      # predictor_0_pht_nb_counter
-0       0       +1      # predictor_0_pht_size_address_share
-1       1       +1      # predictor_1_have_bht              
-12      12      +1      # predictor_1_bht_size_shifter      
-2       2       *2      # predictor_1_bht_nb_shifter
-1       1       +1      # predictor_1_have_pht              
-2       2       +1      # predictor_1_pht_size_counter      
-4096    4096    *2      # predictor_1_pht_nb_counter
-0       0       +1      # predictor_1_pht_size_address_share
-0       0       +1      # predictor_2_have_bht              
-4       4       +1      # predictor_2_bht_size_shifter      
-256     256     *2      # predictor_2_bht_nb_shifter
-1       1       +1      # predictor_2_have_pht              
-2       2       +1      # predictor_2_pht_size_counter      
-4096    4096    *2      # predictor_2_pht_nb_counter
-0       0       +1      # predictor_2_pht_size_address_share
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/SelfTest/configuration/config-alpha_21264.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/SelfTest/configuration/config-alpha_21264.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/SelfTest/configuration/config-alpha_21264.gen	(revision 145)
@@ -0,0 +1,25 @@
+Meta_Predictor
+1       1       +1      # nb_inst_predict
+1       1       +1      # nb_inst_update
+30      30      *2      # size_address
+1       1       +1      # predictor_0_have_bht              
+10      10      +1      # predictor_0_bht_size_shifter      
+1024    1024    *2      # predictor_0_bht_nb_shifter
+1       1       +1      # predictor_0_have_pht              
+3       3       +1      # predictor_0_pht_size_counter      
+1024    1024    *2      # predictor_0_pht_nb_counter
+0       0       +1      # predictor_0_pht_size_address_share
+1       1       +1      # predictor_1_have_bht              
+12      12      +1      # predictor_1_bht_size_shifter      
+2       2       *2      # predictor_1_bht_nb_shifter
+1       1       +1      # predictor_1_have_pht              
+2       2       +1      # predictor_1_pht_size_counter      
+4096    4096    *2      # predictor_1_pht_nb_counter
+0       0       +1      # predictor_1_pht_size_address_share
+0       0       +1      # predictor_2_have_bht              
+4       4       +1      # predictor_2_bht_size_shifter      
+256     256     *2      # predictor_2_bht_nb_shifter
+1       1       +1      # predictor_2_have_pht              
+2       2       +1      # predictor_2_pht_size_counter      
+4096    4096    *2      # predictor_2_pht_nb_counter
+0       0       +1      # predictor_2_pht_size_address_share
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/config_bht_and_pht.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/config_bht_and_pht.cfg	(revision 144)
+++ 	(revision )
@@ -1,12 +1,0 @@
-Two_Level_Branch_Predictor
-4       4       *2      # nb_inst_predict       
-4       4       *2      # nb_inst_update        
-30      30      *2      # size_address          
-1       1       +1      # have_bht              
-4       4       *4      # bht_size_shifter      
-16      16      *4      # bht_nb_shifter        
-1	1	+1	# have_pht              
-4	4  	*2	# pht_size_counter      
-32	32	*4	# pht_nb_counter        
-0	2	+1	# pht_size_address_share
-1       1       +1      # update_on_prediction
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/config_bht_only.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/config_bht_only.cfg	(revision 144)
+++ 	(revision )
@@ -1,12 +1,0 @@
-Two_Level_Branch_Predictor
-4       4       *2      # nb_inst_predict       
-4       4       *2      # nb_inst_update        
-30      30      *2      # size_address          
-1       1       +1      # have_bht              
-1       16      *4      # bht_size_shifter      
-1       16      *4      # bht_nb_shifter        
-0	0	+1	# have_pht              
-0	0	+1	# pht_size_counter      
-0	0	*2	# pht_nb_counter        
-0	0	+1	# pht_size_address_share
-1       1       +1      # update_on_prediction
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/config_pht_only.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/config_pht_only.cfg	(revision 144)
+++ 	(revision )
@@ -1,12 +1,0 @@
-Two_Level_Branch_Predictor
-4       4       *2      # nb_inst_predict       
-4       4       *2      # nb_inst_update        
-30      30      *2      # size_address          
-0       0       +1      # have_bht              
-0       0       *4      # bht_size_shifter      
-0       0       *4      # bht_nb_shifter        
-1	1	+1	# have_pht              
-1	4  	*2	# pht_size_counter      
-1	16	*4	# pht_nb_counter        
-0	0	+1	# pht_size_address_share
-1       1       +1      # update_on_prediction
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/configuration/config_bht_and_pht.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/configuration/config_bht_and_pht.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/configuration/config_bht_and_pht.gen	(revision 145)
@@ -0,0 +1,12 @@
+Two_Level_Branch_Predictor
+4       4       *2      # nb_inst_predict       
+4       4       *2      # nb_inst_update        
+30      30      *2      # size_address          
+1       1       +1      # have_bht              
+4       4       *4      # bht_size_shifter      
+16      16      *4      # bht_nb_shifter        
+1	1	+1	# have_pht              
+4	4  	*2	# pht_size_counter      
+32	32	*4	# pht_nb_counter        
+0	2	+1	# pht_size_address_share
+1       1       +1      # update_on_prediction
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/configuration/config_bht_only.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/configuration/config_bht_only.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/configuration/config_bht_only.gen	(revision 145)
@@ -0,0 +1,12 @@
+Two_Level_Branch_Predictor
+4       4       *2      # nb_inst_predict       
+4       4       *2      # nb_inst_update        
+30      30      *2      # size_address          
+1       1       +1      # have_bht              
+1       16      *4      # bht_size_shifter      
+1       16      *4      # bht_nb_shifter        
+0	0	+1	# have_pht              
+0	0	+1	# pht_size_counter      
+0	0	*2	# pht_nb_counter        
+0	0	+1	# pht_size_address_share
+1       1       +1      # update_on_prediction
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/configuration/config_pht_only.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/configuration/config_pht_only.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/configuration/config_pht_only.gen	(revision 145)
@@ -0,0 +1,12 @@
+Two_Level_Branch_Predictor
+4       4       *2      # nb_inst_predict       
+4       4       *2      # nb_inst_update        
+30      30      *2      # size_address          
+0       0       +1      # have_bht              
+0       0       *4      # bht_size_shifter      
+0       0       *4      # bht_nb_shifter        
+1	1	+1	# have_pht              
+1	4  	*2	# pht_size_counter      
+1	16	*4	# pht_nb_counter        
+0	0	+1	# pht_size_address_share
+1       1       +1      # update_on_prediction
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/config-alpha_21264.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/config-alpha_21264.cfg	(revision 144)
+++ 	(revision )
@@ -1,26 +1,0 @@
-Direction
-4	8	+1	# _predictor_scheme      
-1       1       +1      # nb_inst_predict
-1       1       +1      # nb_inst_update
-30      30      *2      # size_address
-1       1       +1      # predictor_0_have_bht              
-10      10      +1      # predictor_0_bht_size_shifter      
-1024    1024    *2      # predictor_0_bht_nb_shifter
-1       1       +1      # predictor_0_have_pht              
-3       3       +1      # predictor_0_pht_size_counter      
-1024    1024    *2      # predictor_0_pht_nb_counter
-0       0       +1      # predictor_0_pht_size_address_share
-1       1       +1      # predictor_1_have_bht              
-12      12      +1      # predictor_1_bht_size_shifter      
-2       2       *2      # predictor_1_bht_nb_shifter
-1       1       +1      # predictor_1_have_pht              
-2       2       +1      # predictor_1_pht_size_counter      
-4096    4096    *2      # predictor_1_pht_nb_counter
-0       0       +1      # predictor_1_pht_size_address_share
-0       0       +1      # predictor_2_have_bht              
-4       4       +1      # predictor_2_bht_size_shifter      
-256     256     *2      # predictor_2_bht_nb_shifter
-1       1       +1      # predictor_2_have_pht              
-2       2       +1      # predictor_2_pht_size_counter      
-4096    4096    *2      # predictor_2_pht_nb_counter
-0       0       +1      # predictor_2_pht_size_address_share
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/config_without_meta_predictor.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/config_without_meta_predictor.cfg	(revision 144)
+++ 	(revision )
@@ -1,26 +1,0 @@
-Direction
-0	3	+1	# _predictor_scheme      
-1	4	*4	# _nb_inst_predict       
-1	4	*4	# _nb_inst_update        
-32	32	*2	# _size_address          
-1	1	+1	# _predictor_0_have_bht              
-1	1	+1	# _predictor_0_bht_size_shifter      
-1	1	+1	# _predictor_0_bht_nb_shifter        
-1	1	+1	# _predictor_0_have_pht              
-1	1	+1	# _predictor_0_pht_size_counter      
-1	1	+1	# _predictor_0_pht_nb_counter        
-1	1	+1	# _predictor_0_pht_size_address_share
-1	1	+1	# _predictor_1_have_bht              
-1	1	+1	# _predictor_1_bht_size_shifter      
-1	1	+1	# _predictor_1_bht_nb_shifter        
-1	1	+1	# _predictor_1_have_pht              
-1	1	+1	# _predictor_1_pht_size_counter      
-1	1	+1	# _predictor_1_pht_nb_counter        
-1	1	+1	# _predictor_1_pht_size_address_share
-1	1	+1	# _predictor_2_have_bht              
-1	1	+1	# _predictor_2_bht_size_shifter      
-1	1	+1	# _predictor_2_bht_nb_shifter        
-1	1	+1	# _predictor_2_have_pht              
-1	1	+1	# _predictor_2_pht_size_counter      
-1	1	+1	# _predictor_2_pht_nb_counter        
-1	1	+1	# _predictor_2_pht_size_address_share
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/configuration/config-alpha_21264.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/configuration/config-alpha_21264.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/configuration/config-alpha_21264.gen	(revision 145)
@@ -0,0 +1,26 @@
+Direction
+4	8	+1	# _predictor_scheme      
+1       1       +1      # nb_inst_predict
+1       1       +1      # nb_inst_update
+30      30      *2      # size_address
+1       1       +1      # predictor_0_have_bht              
+10      10      +1      # predictor_0_bht_size_shifter      
+1024    1024    *2      # predictor_0_bht_nb_shifter
+1       1       +1      # predictor_0_have_pht              
+3       3       +1      # predictor_0_pht_size_counter      
+1024    1024    *2      # predictor_0_pht_nb_counter
+0       0       +1      # predictor_0_pht_size_address_share
+1       1       +1      # predictor_1_have_bht              
+12      12      +1      # predictor_1_bht_size_shifter      
+2       2       *2      # predictor_1_bht_nb_shifter
+1       1       +1      # predictor_1_have_pht              
+2       2       +1      # predictor_1_pht_size_counter      
+4096    4096    *2      # predictor_1_pht_nb_counter
+0       0       +1      # predictor_1_pht_size_address_share
+0       0       +1      # predictor_2_have_bht              
+4       4       +1      # predictor_2_bht_size_shifter      
+256     256     *2      # predictor_2_bht_nb_shifter
+1       1       +1      # predictor_2_have_pht              
+2       2       +1      # predictor_2_pht_size_counter      
+4096    4096    *2      # predictor_2_pht_nb_counter
+0       0       +1      # predictor_2_pht_size_address_share
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/configuration/config_without_meta_predictor.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/configuration/config_without_meta_predictor.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/configuration/config_without_meta_predictor.gen	(revision 145)
@@ -0,0 +1,26 @@
+Direction
+0	3	+1	# _predictor_scheme      
+1	4	*4	# _nb_inst_predict       
+1	4	*4	# _nb_inst_update        
+32	32	*2	# _size_address          
+1	1	+1	# _predictor_0_have_bht              
+1	1	+1	# _predictor_0_bht_size_shifter      
+1	1	+1	# _predictor_0_bht_nb_shifter        
+1	1	+1	# _predictor_0_have_pht              
+1	1	+1	# _predictor_0_pht_size_counter      
+1	1	+1	# _predictor_0_pht_nb_counter        
+1	1	+1	# _predictor_0_pht_size_address_share
+1	1	+1	# _predictor_1_have_bht              
+1	1	+1	# _predictor_1_bht_size_shifter      
+1	1	+1	# _predictor_1_bht_nb_shifter        
+1	1	+1	# _predictor_1_have_pht              
+1	1	+1	# _predictor_1_pht_size_counter      
+1	1	+1	# _predictor_1_pht_nb_counter        
+1	1	+1	# _predictor_1_pht_size_address_share
+1	1	+1	# _predictor_2_have_bht              
+1	1	+1	# _predictor_2_bht_size_shifter      
+1	1	+1	# _predictor_2_bht_nb_shifter        
+1	1	+1	# _predictor_2_have_pht              
+1	1	+1	# _predictor_2_pht_size_counter      
+1	1	+1	# _predictor_2_pht_nb_counter        
+1	1	+1	# _predictor_2_pht_size_address_share
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/config_mono_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Prediction_unit_Glue
-1	1	*4	# nb_context         
-1	1	*4	# nb_decod_unit      
-30	30	+32	# size_address       
-1	4	*2	# nb_instruction  [0] [nb_context]
-1	1	*4	# size_depth      [0] [nb_context]
-4	4	*4	# nb_inst_decod   [0] [nb_decod_unit]
-1	1	*4	# nb_inst_branch_predict     
-4	4	*4	# nb_inst_branch_decod 
-4	4	*4	# nb_inst_branch_update
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/config_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/config_multi_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,16 +1,0 @@
-Prediction_unit_Glue
-4	4	*4	# nb_context         
-1	1	*4	# nb_decod_unit      
-30	30	+32	# size_address       
-1	1	*4	# nb_instruction  [0] [nb_context]
-2	2	*4	# nb_instruction  [1] [nb_context]
-8	8	*4	# nb_instruction  [2] [nb_context]
-4	4	*4	# nb_instruction  [3] [nb_context]
-2	2	*4	# size_depth      [0] [nb_context]
-1	1	*4	# size_depth      [1] [nb_context]
-7	7	*4	# size_depth      [2] [nb_context]
-4	4	*4	# size_depth      [3] [nb_context]
-4	4	*4	# nb_inst_decod   [0] [nb_decod_unit]
-1	4	*4	# nb_inst_branch_predict     
-4	4	*4	# nb_inst_branch_decod 
-4	4	*4	# nb_inst_branch_update
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/configuration/config_mono_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/configuration/config_mono_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/configuration/config_mono_context.gen	(revision 145)
@@ -0,0 +1,10 @@
+Prediction_unit_Glue
+1	1	*4	# nb_context         
+1	1	*4	# nb_decod_unit      
+30	30	+32	# size_address       
+1	4	*2	# nb_instruction  [0] [nb_context]
+1	1	*4	# size_depth      [0] [nb_context]
+4	4	*4	# nb_inst_decod   [0] [nb_decod_unit]
+1	1	*4	# nb_inst_branch_predict     
+4	4	*4	# nb_inst_branch_decod 
+4	4	*4	# nb_inst_branch_update
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/configuration/config_multi_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/configuration/config_multi_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/configuration/config_multi_context.gen	(revision 145)
@@ -0,0 +1,16 @@
+Prediction_unit_Glue
+4	4	*4	# nb_context         
+1	1	*4	# nb_decod_unit      
+30	30	+32	# size_address       
+1	1	*4	# nb_instruction  [0] [nb_context]
+2	2	*4	# nb_instruction  [1] [nb_context]
+8	8	*4	# nb_instruction  [2] [nb_context]
+4	4	*4	# nb_instruction  [3] [nb_context]
+2	2	*4	# size_depth      [0] [nb_context]
+1	1	*4	# size_depth      [1] [nb_context]
+7	7	*4	# size_depth      [2] [nb_context]
+4	4	*4	# size_depth      [3] [nb_context]
+4	4	*4	# nb_inst_decod   [0] [nb_decod_unit]
+1	4	*4	# nb_inst_branch_predict     
+4	4	*4	# nb_inst_branch_decod 
+4	4	*4	# nb_inst_branch_update
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp	(revision 145)
@@ -78,5 +78,5 @@
           //   * branch was not detected
           Tcontrol_t        miss_decod            = (branch_state == BRANCH_STATE_NONE);
-          Tcontrol_t        can_continue          = false;
+          Tcontrol_t        can_continue          = PORT_READ(in_DECOD_UPT_CAN_CONTINUE [port]);
 
 	  log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"  * DECOD [%d][%d]          : valid",decod_unit,i);
@@ -212,5 +212,6 @@
 		}
 
-              can_continue = false; // need update upt
+              // can_continue = false; // need update upt
+              can_continue &= not take;
 	    }
  	  else
@@ -218,12 +219,5 @@
               log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * hit");
 
-              if (branch_state == BRANCH_STATE_SPEC_NTAKE)
-                can_continue = PORT_READ(in_DECOD_UPT_CAN_CONTINUE [port]);
-              else
-                // BRANCH_STATE_NONE       -> miss
-                // BRANCH_STATE_NSPEC_TAKE -> take
-                // BRANCH_STATE_SPEC_TAKE  -> take
-                can_continue = false;
-
+//            can_continue = PORT_READ(in_DECOD_UPT_CAN_CONTINUE [port]);
 // 	      miss_decod = false;
 // 	      // Hit speculation
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/config_mono_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,7 +1,0 @@
-Return_Address_Stack
-1	1	+1	# nb_context     
-2	4	*2	# size_queue     [0]
-32	32	*2	# size_address   
-1	4	*4	# nb_inst_predict
-1	4	*4	# nb_inst_decod  
-1	4	*4	# nb_inst_update 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/config_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/config_multi_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Return_Address_Stack
-4	4	+1	# nb_context     
-2	2	*2	# size_queue     [0]
-4	4	*2	# size_queue     [1]
-8	8	*2	# size_queue     [2]
-8 	8 	*2	# size_queue     [3]
-32	32	*2	# size_address   
-1	4	*4	# nb_inst_predict
-1	4	*4	# nb_inst_decod  
-1	4	*4	# nb_inst_update 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/configuration/config_mono_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/configuration/config_mono_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/configuration/config_mono_context.gen	(revision 145)
@@ -0,0 +1,7 @@
+Return_Address_Stack
+1	1	+1	# nb_context     
+2	4	*2	# size_queue     [0]
+32	32	*2	# size_address   
+1	4	*4	# nb_inst_predict
+1	4	*4	# nb_inst_decod  
+1	4	*4	# nb_inst_update 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/configuration/config_multi_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/configuration/config_multi_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/configuration/config_multi_context.gen	(revision 145)
@@ -0,0 +1,10 @@
+Return_Address_Stack
+4	4	+1	# nb_context     
+2	2	*2	# size_queue     [0]
+4	4	*2	# size_queue     [1]
+8	8	*2	# size_queue     [2]
+8 	8 	*2	# size_queue     [3]
+32	32	*2	# size_address   
+1	4	*4	# nb_inst_predict
+1	4	*4	# nb_inst_decod  
+1	4	*4	# nb_inst_update 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,39 +1,0 @@
-Prediction_unit
-1	1	+1 # nb_context                 
-1	1	+1 # nb_decod_unit              
-30	30	+1 # size_address               
-1	1	+1 # nb_instruction             [0] [nb_context]
-1	1	+1 # nb_inst_decod              [0] [nb_decod_unit]
-1	1	+1 # nb_inst_branch_predict     
-1	1	+1 # nb_inst_branch_decod       
-1	1	+1 # nb_inst_branch_update      
-1	1	+1 # nb_inst_branch_complete    
-1	1	+1 # btb_size_queue             
-1	1	+1 # btb_associativity          
-2	2	+1 # btb_size_counter           
-3	3	+1 # btb_victim_scheme          
-1	1	+1 # dir_predictor_scheme       
-1	1	+1 # dir_have_bht               [0] [3]
-1	1	+1 # dir_have_bht               [1] [3]
-1	1	+1 # dir_have_bht               [2] [3]
-1	1	+1 # dir_bht_size_shifter       [0] [3]
-1	1	+1 # dir_bht_size_shifter       [1] [3]
-1	1	+1 # dir_bht_size_shifter       [2] [3]
-1	1	+1 # dir_bht_nb_shifter         [0] [3]
-1	1	+1 # dir_bht_nb_shifter         [1] [3]
-1	1	+1 # dir_bht_nb_shifter         [2] [3]
-1	1	+1 # dir_have_pht               [0] [3]
-1	1	+1 # dir_have_pht               [1] [3]
-1	1	+1 # dir_have_pht               [2] [3]
-1	1	+1 # dir_pht_size_counter       [0] [3]
-1	1	+1 # dir_pht_size_counter       [1] [3]
-1	1	+1 # dir_pht_size_counter       [2] [3]
-1	1	+1 # dir_pht_nb_counter         [0] [3]
-1	1	+1 # dir_pht_nb_counter         [1] [3]
-1	1	+1 # dir_pht_nb_counter         [2] [3]
-1	1	+1 # dir_pht_size_address_share [0] [3]
-1	1	+1 # dir_pht_size_address_share [1] [3]
-1	1	+1 # dir_pht_size_address_share [2] [3]
-2	2	+1 # ras_size_queue             [0] [nb_context]
-1	1	+1 # upt_size_queue             [0] [nb_context]
-1	1	+1 # ufpt_size_queue            [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,39 +1,0 @@
-Prediction_unit
-1	1	+1 # nb_context                 
-1	1	+1 # nb_decod_unit              
-30	30	+1 # size_address               
-1	4	*4 # nb_instruction             [0] [nb_context]
-1	4	*4 # nb_inst_decod              [0] [nb_decod_unit]
-1	1	+1 # nb_inst_branch_predict     
-2	2	+1 # nb_inst_branch_decod       
-2	2	+1 # nb_inst_branch_update      
-2	2	+1 # nb_inst_branch_complete    
-2	8	*8 # btb_size_queue             
-2	2	+1 # btb_associativity          
-2	2	+1 # btb_size_counter           
-3	3	+1 # btb_victim_scheme          
-1	1	+1 # dir_predictor_scheme       
-1	1	+1 # dir_have_bht               [0] [3]
-1	1	+1 # dir_have_bht               [1] [3]
-1	1	+1 # dir_have_bht               [2] [3]
-1	1	+1 # dir_bht_size_shifter       [0] [3]
-1	1	+1 # dir_bht_size_shifter       [1] [3]
-1	1	+1 # dir_bht_size_shifter       [2] [3]
-1	1	+1 # dir_bht_nb_shifter         [0] [3]
-1	1	+1 # dir_bht_nb_shifter         [1] [3]
-1	1	+1 # dir_bht_nb_shifter         [2] [3]
-1	1	+1 # dir_have_pht               [0] [3]
-1	1	+1 # dir_have_pht               [1] [3]
-1	1	+1 # dir_have_pht               [2] [3]
-1	1	+1 # dir_pht_size_counter       [0] [3]
-1	1	+1 # dir_pht_size_counter       [1] [3]
-1	1	+1 # dir_pht_size_counter       [2] [3]
-1	1	+1 # dir_pht_nb_counter         [0] [3]
-1	1	+1 # dir_pht_nb_counter         [1] [3]
-1	1	+1 # dir_pht_nb_counter         [2] [3]
-1	1	+1 # dir_pht_size_address_share [0] [3]
-1	1	+1 # dir_pht_size_address_share [1] [3]
-1	1	+1 # dir_pht_size_address_share [2] [3]
-4	4	*2 # ras_size_queue             [0] [nb_context]
-4	4	*2 # upt_size_queue             [0] [nb_context]
-2	2	+1 # ufpt_size_queue            [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context_multi_decod.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context_multi_decod.cfg	(revision 144)
+++ 	(revision )
@@ -1,42 +1,0 @@
-Prediction_unit
-1	1	+1 # nb_context                 
-4	4	+1 # nb_decod_unit              
-30	30	+1 # size_address               
-4	4	*4 # nb_instruction             [0] [nb_context]
-4	4	+1 # nb_inst_decod              [0] [nb_decod_unit]
-1	1	+1 # nb_inst_decod              [1] [nb_decod_unit]
-2	2	+1 # nb_inst_decod              [2] [nb_decod_unit]
-8	8	+1 # nb_inst_decod              [3] [nb_decod_unit]
-1	1	+1 # nb_inst_branch_predict     
-1	1	+1 # nb_inst_branch_decod       
-1	1	+1 # nb_inst_branch_update      
-1	1	+1 # nb_inst_branch_complete    
-8	8	*4 # btb_size_queue             
-2	2	+1 # btb_associativity          
-2	2	+1 # btb_size_counter           
-3	3	+1 # btb_victim_scheme          
-1	1	+1 # dir_predictor_scheme       
-1	1	+1 # dir_have_bht               [0] [3]
-1	1	+1 # dir_have_bht               [1] [3]
-1	1	+1 # dir_have_bht               [2] [3]
-1	1	+1 # dir_bht_size_shifter       [0] [3]
-1	1	+1 # dir_bht_size_shifter       [1] [3]
-1	1	+1 # dir_bht_size_shifter       [2] [3]
-1	1	+1 # dir_bht_nb_shifter         [0] [3]
-1	1	+1 # dir_bht_nb_shifter         [1] [3]
-1	1	+1 # dir_bht_nb_shifter         [2] [3]
-1	1	+1 # dir_have_pht               [0] [3]
-1	1	+1 # dir_have_pht               [1] [3]
-1	1	+1 # dir_have_pht               [2] [3]
-1	1	+1 # dir_pht_size_counter       [0] [3]
-1	1	+1 # dir_pht_size_counter       [1] [3]
-1	1	+1 # dir_pht_size_counter       [2] [3]
-1	1	+1 # dir_pht_nb_counter         [0] [3]
-1	1	+1 # dir_pht_nb_counter         [1] [3]
-1	1	+1 # dir_pht_nb_counter         [2] [3]
-1	1	+1 # dir_pht_size_address_share [0] [3]
-1	1	+1 # dir_pht_size_address_share [1] [3]
-1	1	+1 # dir_pht_size_address_share [2] [3]
-4	4	*2 # ras_size_queue             [0] [nb_context]
-4	4	*4 # upt_size_queue             [0] [nb_context]
-2	2	*4 # ufpt_size_queue            [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_multi_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,51 +1,0 @@
-Prediction_unit
-4	4	+1 # nb_context                 
-1	1	+1 # nb_decod_unit              
-30	30	+1 # size_address               
-1	1	*4 # nb_instruction             [0] [nb_context]
-2	2	*4 # nb_instruction             [1] [nb_context]
-4	4	*4 # nb_instruction             [2] [nb_context]
-8	8	*4 # nb_instruction             [3] [nb_context]
-1	1	+1 # nb_inst_decod              [0] [nb_decod_unit]
-1	1	+1 # nb_inst_branch_predict     
-1	1	+1 # nb_inst_branch_decod       
-1	1	+1 # nb_inst_branch_update      
-1	1	+1 # nb_inst_branch_complete    
-16	16	*4 # btb_size_queue             
-8	8	+1 # btb_associativity          
-2	2	+1 # btb_size_counter           
-3	3	+1 # btb_victim_scheme          
-1	1	+1 # dir_predictor_scheme       
-1	1	+1 # dir_have_bht               [0] [3]
-1	1	+1 # dir_have_bht               [1] [3]
-1	1	+1 # dir_have_bht               [2] [3]
-1	1	+1 # dir_bht_size_shifter       [0] [3]
-1	1	+1 # dir_bht_size_shifter       [1] [3]
-1	1	+1 # dir_bht_size_shifter       [2] [3]
-1	1	+1 # dir_bht_nb_shifter         [0] [3]
-1	1	+1 # dir_bht_nb_shifter         [1] [3]
-1	1	+1 # dir_bht_nb_shifter         [2] [3]
-1	1	+1 # dir_have_pht               [0] [3]
-1	1	+1 # dir_have_pht               [1] [3]
-1	1	+1 # dir_have_pht               [2] [3]
-1	1	+1 # dir_pht_size_counter       [0] [3]
-1	1	+1 # dir_pht_size_counter       [1] [3]
-1	1	+1 # dir_pht_size_counter       [2] [3]
-1	1	+1 # dir_pht_nb_counter         [0] [3]
-1	1	+1 # dir_pht_nb_counter         [1] [3]
-1	1	+1 # dir_pht_nb_counter         [2] [3]
-1	1	+1 # dir_pht_size_address_share [0] [3]
-1	1	+1 # dir_pht_size_address_share [1] [3]
-1	1	+1 # dir_pht_size_address_share [2] [3]
-2	2	*2 # ras_size_queue             [0] [nb_context]
-8	8	*2 # ras_size_queue             [1] [nb_context]
-4	4	*2 # ras_size_queue             [2] [nb_context]
-2	2	*2 # ras_size_queue             [3] [nb_context]
-2	2	*4 # upt_size_queue             [0] [nb_context]
-4	4	*4 # upt_size_queue             [1] [nb_context]
-4	4	*4 # upt_size_queue             [2] [nb_context]
-8	8	*4 # upt_size_queue             [3] [nb_context]
-1	1	*4 # ufpt_size_queue            [0] [nb_context]
-4	4	*4 # ufpt_size_queue            [1] [nb_context]
-2	2	*4 # ufpt_size_queue            [2] [nb_context]
-4	4	*4 # ufpt_size_queue            [3] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,39 @@
+Prediction_unit
+1	1	+1 # nb_context                 
+1	1	+1 # nb_decod_unit              
+30	30	+1 # size_address               
+1	1	+1 # nb_instruction             [0] [nb_context]
+1	1	+1 # nb_inst_decod              [0] [nb_decod_unit]
+1	1	+1 # nb_inst_branch_predict     
+1	1	+1 # nb_inst_branch_decod       
+1	1	+1 # nb_inst_branch_update      
+1	1	+1 # nb_inst_branch_complete    
+1	1	+1 # btb_size_queue             
+1	1	+1 # btb_associativity          
+2	2	+1 # btb_size_counter           
+3	3	+1 # btb_victim_scheme          
+1	1	+1 # dir_predictor_scheme       
+1	1	+1 # dir_have_bht               [0] [3]
+1	1	+1 # dir_have_bht               [1] [3]
+1	1	+1 # dir_have_bht               [2] [3]
+1	1	+1 # dir_bht_size_shifter       [0] [3]
+1	1	+1 # dir_bht_size_shifter       [1] [3]
+1	1	+1 # dir_bht_size_shifter       [2] [3]
+1	1	+1 # dir_bht_nb_shifter         [0] [3]
+1	1	+1 # dir_bht_nb_shifter         [1] [3]
+1	1	+1 # dir_bht_nb_shifter         [2] [3]
+1	1	+1 # dir_have_pht               [0] [3]
+1	1	+1 # dir_have_pht               [1] [3]
+1	1	+1 # dir_have_pht               [2] [3]
+1	1	+1 # dir_pht_size_counter       [0] [3]
+1	1	+1 # dir_pht_size_counter       [1] [3]
+1	1	+1 # dir_pht_size_counter       [2] [3]
+1	1	+1 # dir_pht_nb_counter         [0] [3]
+1	1	+1 # dir_pht_nb_counter         [1] [3]
+1	1	+1 # dir_pht_nb_counter         [2] [3]
+1	1	+1 # dir_pht_size_address_share [0] [3]
+1	1	+1 # dir_pht_size_address_share [1] [3]
+1	1	+1 # dir_pht_size_address_share [2] [3]
+2	2	+1 # ras_size_queue             [0] [nb_context]
+1	1	+1 # upt_size_queue             [0] [nb_context]
+1	1	+1 # ufpt_size_queue            [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/configuration/config_mono_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/configuration/config_mono_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/configuration/config_mono_context.gen	(revision 145)
@@ -0,0 +1,39 @@
+Prediction_unit
+1	1	+1 # nb_context                 
+1	1	+1 # nb_decod_unit              
+30	30	+1 # size_address               
+1	4	*4 # nb_instruction             [0] [nb_context]
+1	4	*4 # nb_inst_decod              [0] [nb_decod_unit]
+1	1	+1 # nb_inst_branch_predict     
+2	2	+1 # nb_inst_branch_decod       
+2	2	+1 # nb_inst_branch_update      
+2	2	+1 # nb_inst_branch_complete    
+2	8	*8 # btb_size_queue             
+2	2	+1 # btb_associativity          
+2	2	+1 # btb_size_counter           
+3	3	+1 # btb_victim_scheme          
+1	1	+1 # dir_predictor_scheme       
+1	1	+1 # dir_have_bht               [0] [3]
+1	1	+1 # dir_have_bht               [1] [3]
+1	1	+1 # dir_have_bht               [2] [3]
+1	1	+1 # dir_bht_size_shifter       [0] [3]
+1	1	+1 # dir_bht_size_shifter       [1] [3]
+1	1	+1 # dir_bht_size_shifter       [2] [3]
+1	1	+1 # dir_bht_nb_shifter         [0] [3]
+1	1	+1 # dir_bht_nb_shifter         [1] [3]
+1	1	+1 # dir_bht_nb_shifter         [2] [3]
+1	1	+1 # dir_have_pht               [0] [3]
+1	1	+1 # dir_have_pht               [1] [3]
+1	1	+1 # dir_have_pht               [2] [3]
+1	1	+1 # dir_pht_size_counter       [0] [3]
+1	1	+1 # dir_pht_size_counter       [1] [3]
+1	1	+1 # dir_pht_size_counter       [2] [3]
+1	1	+1 # dir_pht_nb_counter         [0] [3]
+1	1	+1 # dir_pht_nb_counter         [1] [3]
+1	1	+1 # dir_pht_nb_counter         [2] [3]
+1	1	+1 # dir_pht_size_address_share [0] [3]
+1	1	+1 # dir_pht_size_address_share [1] [3]
+1	1	+1 # dir_pht_size_address_share [2] [3]
+4	4	*2 # ras_size_queue             [0] [nb_context]
+4	4	*2 # upt_size_queue             [0] [nb_context]
+2	2	+1 # ufpt_size_queue            [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/configuration/config_mono_context_multi_decod.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/configuration/config_mono_context_multi_decod.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/configuration/config_mono_context_multi_decod.gen	(revision 145)
@@ -0,0 +1,42 @@
+Prediction_unit
+1	1	+1 # nb_context                 
+4	4	+1 # nb_decod_unit              
+30	30	+1 # size_address               
+4	4	*4 # nb_instruction             [0] [nb_context]
+4	4	+1 # nb_inst_decod              [0] [nb_decod_unit]
+1	1	+1 # nb_inst_decod              [1] [nb_decod_unit]
+2	2	+1 # nb_inst_decod              [2] [nb_decod_unit]
+8	8	+1 # nb_inst_decod              [3] [nb_decod_unit]
+1	1	+1 # nb_inst_branch_predict     
+1	1	+1 # nb_inst_branch_decod       
+1	1	+1 # nb_inst_branch_update      
+1	1	+1 # nb_inst_branch_complete    
+8	8	*4 # btb_size_queue             
+2	2	+1 # btb_associativity          
+2	2	+1 # btb_size_counter           
+3	3	+1 # btb_victim_scheme          
+1	1	+1 # dir_predictor_scheme       
+1	1	+1 # dir_have_bht               [0] [3]
+1	1	+1 # dir_have_bht               [1] [3]
+1	1	+1 # dir_have_bht               [2] [3]
+1	1	+1 # dir_bht_size_shifter       [0] [3]
+1	1	+1 # dir_bht_size_shifter       [1] [3]
+1	1	+1 # dir_bht_size_shifter       [2] [3]
+1	1	+1 # dir_bht_nb_shifter         [0] [3]
+1	1	+1 # dir_bht_nb_shifter         [1] [3]
+1	1	+1 # dir_bht_nb_shifter         [2] [3]
+1	1	+1 # dir_have_pht               [0] [3]
+1	1	+1 # dir_have_pht               [1] [3]
+1	1	+1 # dir_have_pht               [2] [3]
+1	1	+1 # dir_pht_size_counter       [0] [3]
+1	1	+1 # dir_pht_size_counter       [1] [3]
+1	1	+1 # dir_pht_size_counter       [2] [3]
+1	1	+1 # dir_pht_nb_counter         [0] [3]
+1	1	+1 # dir_pht_nb_counter         [1] [3]
+1	1	+1 # dir_pht_nb_counter         [2] [3]
+1	1	+1 # dir_pht_size_address_share [0] [3]
+1	1	+1 # dir_pht_size_address_share [1] [3]
+1	1	+1 # dir_pht_size_address_share [2] [3]
+4	4	*2 # ras_size_queue             [0] [nb_context]
+4	4	*4 # upt_size_queue             [0] [nb_context]
+2	2	*4 # ufpt_size_queue            [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/configuration/config_multi_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/configuration/config_multi_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/configuration/config_multi_context.gen	(revision 145)
@@ -0,0 +1,51 @@
+Prediction_unit
+4	4	+1 # nb_context                 
+1	1	+1 # nb_decod_unit              
+30	30	+1 # size_address               
+1	1	*4 # nb_instruction             [0] [nb_context]
+2	2	*4 # nb_instruction             [1] [nb_context]
+4	4	*4 # nb_instruction             [2] [nb_context]
+8	8	*4 # nb_instruction             [3] [nb_context]
+1	1	+1 # nb_inst_decod              [0] [nb_decod_unit]
+1	1	+1 # nb_inst_branch_predict     
+1	1	+1 # nb_inst_branch_decod       
+1	1	+1 # nb_inst_branch_update      
+1	1	+1 # nb_inst_branch_complete    
+16	16	*4 # btb_size_queue             
+8	8	+1 # btb_associativity          
+2	2	+1 # btb_size_counter           
+3	3	+1 # btb_victim_scheme          
+1	1	+1 # dir_predictor_scheme       
+1	1	+1 # dir_have_bht               [0] [3]
+1	1	+1 # dir_have_bht               [1] [3]
+1	1	+1 # dir_have_bht               [2] [3]
+1	1	+1 # dir_bht_size_shifter       [0] [3]
+1	1	+1 # dir_bht_size_shifter       [1] [3]
+1	1	+1 # dir_bht_size_shifter       [2] [3]
+1	1	+1 # dir_bht_nb_shifter         [0] [3]
+1	1	+1 # dir_bht_nb_shifter         [1] [3]
+1	1	+1 # dir_bht_nb_shifter         [2] [3]
+1	1	+1 # dir_have_pht               [0] [3]
+1	1	+1 # dir_have_pht               [1] [3]
+1	1	+1 # dir_have_pht               [2] [3]
+1	1	+1 # dir_pht_size_counter       [0] [3]
+1	1	+1 # dir_pht_size_counter       [1] [3]
+1	1	+1 # dir_pht_size_counter       [2] [3]
+1	1	+1 # dir_pht_nb_counter         [0] [3]
+1	1	+1 # dir_pht_nb_counter         [1] [3]
+1	1	+1 # dir_pht_nb_counter         [2] [3]
+1	1	+1 # dir_pht_size_address_share [0] [3]
+1	1	+1 # dir_pht_size_address_share [1] [3]
+1	1	+1 # dir_pht_size_address_share [2] [3]
+2	2	*2 # ras_size_queue             [0] [nb_context]
+8	8	*2 # ras_size_queue             [1] [nb_context]
+4	4	*2 # ras_size_queue             [2] [nb_context]
+2	2	*2 # ras_size_queue             [3] [nb_context]
+2	2	*4 # upt_size_queue             [0] [nb_context]
+4	4	*4 # upt_size_queue             [1] [nb_context]
+4	4	*4 # upt_size_queue             [2] [nb_context]
+8	8	*4 # upt_size_queue             [3] [nb_context]
+1	1	*4 # ufpt_size_queue            [0] [nb_context]
+4	4	*4 # ufpt_size_queue            [1] [nb_context]
+2	2	*4 # ufpt_size_queue            [2] [nb_context]
+4	4	*4 # ufpt_size_queue            [3] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,11 +1,0 @@
-Update_Prediction_Table
-1	1	+1	# nb_context             
-1	1	*4	# size_upt_queue         [0] [nb_context]
-1	1	*4	# size_ufpt_queue        [0] [nb_context]
-32	32	*2	# size_address           
-1	1	*4	# nb_inst_predict        
-1	1	*4	# nb_inst_decod          
-1	1	*4	# nb_inst_branch_complete
-1	1	*4	# nb_inst_update         
-0	0	+1	# size_history           
-1	1	*2	# size_ras_index         [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_mono_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,11 +1,0 @@
-Update_Prediction_Table
-1	1	+1	# nb_context             
-4	8	+1	# size_upt_queue         [0] [nb_context]
-1	4	+1	# size_ufpt_queue        [0] [nb_context]
-32	32	*2	# size_address           
-4	4	*4	# nb_inst_predict        
-4	4	*4	# nb_inst_decod          
-4	4	*4	# nb_inst_branch_complete
-4	4	*4	# nb_inst_update         
-0	0	+1	# size_history           
-3	3	*2	# size_ras_index         [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_multi_context.cfg	(revision 144)
+++ 	(revision )
@@ -1,20 +1,0 @@
-Update_Prediction_Table
-4	4	+1	# nb_context             
-4	4	*4	# size_upt_queue         [0] [nb_context]
-2	2	*4	# size_upt_queue         [1] [nb_context]
-8	8	*4	# size_upt_queue         [2] [nb_context]
-1 	1 	*4	# size_upt_queue         [3] [nb_context]
-4	4	*4	# size_ufpt_queue        [0] [nb_context]
-1	1	*4	# size_ufpt_queue        [1] [nb_context]
-2	2	*4	# size_ufpt_queue        [2] [nb_context]
-1 	1 	*4	# size_ufpt_queue        [3] [nb_context]
-32	32	*2	# size_address           
-4	4	*4	# nb_inst_predict        
-4	4	*4	# nb_inst_decod          
-4	4	*4	# nb_inst_branch_complete
-4	4	*4	# nb_inst_update         
-0	0	+1	# size_history           
-3	3	*2	# size_ras_index         [0] [nb_context]
-1	1	*2	# size_ras_index         [1] [nb_context]
-2	2	*2	# size_ras_index         [2] [nb_context]
-8	8	*2	# size_ras_index         [3] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,11 @@
+Update_Prediction_Table
+1	1	+1	# nb_context             
+1	1	*4	# size_upt_queue         [0] [nb_context]
+1	1	*4	# size_ufpt_queue        [0] [nb_context]
+32	32	*2	# size_address           
+1	1	*4	# nb_inst_predict        
+1	1	*4	# nb_inst_decod          
+1	1	*4	# nb_inst_branch_complete
+1	1	*4	# nb_inst_update         
+0	0	+1	# size_history           
+1	1	*2	# size_ras_index         [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/configuration/config_mono_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/configuration/config_mono_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/configuration/config_mono_context.gen	(revision 145)
@@ -0,0 +1,11 @@
+Update_Prediction_Table
+1	1	+1	# nb_context             
+4	8	+1	# size_upt_queue         [0] [nb_context]
+1	4	+1	# size_ufpt_queue        [0] [nb_context]
+32	32	*2	# size_address           
+4	4	*4	# nb_inst_predict        
+4	4	*4	# nb_inst_decod          
+4	4	*4	# nb_inst_branch_complete
+4	4	*4	# nb_inst_update         
+0	0	+1	# size_history           
+3	3	*2	# size_ras_index         [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/configuration/config_multi_context.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/configuration/config_multi_context.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/configuration/config_multi_context.gen	(revision 145)
@@ -0,0 +1,20 @@
+Update_Prediction_Table
+4	4	+1	# nb_context             
+4	4	*4	# size_upt_queue         [0] [nb_context]
+2	2	*4	# size_upt_queue         [1] [nb_context]
+8	8	*4	# size_upt_queue         [2] [nb_context]
+1 	1 	*4	# size_upt_queue         [3] [nb_context]
+4	4	*4	# size_ufpt_queue        [0] [nb_context]
+1	1	*4	# size_ufpt_queue        [1] [nb_context]
+2	2	*4	# size_ufpt_queue        [2] [nb_context]
+1 	1 	*4	# size_ufpt_queue        [3] [nb_context]
+32	32	*2	# size_address           
+4	4	*4	# nb_inst_predict        
+4	4	*4	# nb_inst_decod          
+4	4	*4	# nb_inst_branch_complete
+4	4	*4	# nb_inst_update         
+0	0	+1	# size_history           
+3	3	*2	# size_ras_index         [0] [nb_context]
+1	1	*2	# size_ras_index         [1] [nb_context]
+2	2	*2	# size_ras_index         [2] [nb_context]
+8	8	*2	# size_ras_index         [3] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp	(revision 145)
@@ -90,5 +90,4 @@
             reg_EVENT_ADDRESS_DEST     [i] = 0; // not necessary
             reg_EVENT_CAN_CONTINUE     [i] = 0; // not necessary
-
           }
       }
@@ -328,5 +327,5 @@
                 {
                   // Have a miss !!!
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * miss !!!");
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * miss !!!");
 
                   condition   = PORT_READ(in_DECOD_BTB_CONDITION [i]);
@@ -350,8 +349,8 @@
                   bool flush_ufpt = (not (can_continue and not direction and not miss_ifetch));
 
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * can_continue: %d",can_continue);
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * direction   : %d",direction   );
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * miss_ifetch : %d",miss_ifetch );
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * flush_ufpt: %d",flush_ufpt  );
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * can_continue: %d",can_continue);
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * direction   : %d",direction   );
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * miss_ifetch : %d",miss_ifetch );
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"        * flush_ufpt: %d",flush_ufpt  );
 
                   // Test if can continue without flushing the ufpt (and ifetch_queue)
@@ -378,5 +377,5 @@
 
                       reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT;
-                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT_EVENT_STATE [%d] <- %s (decod, miss)",context,toString(reg_UPT_EVENT_STATE [context]).c_str());
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * UPT_EVENT_STATE [%d] <- %s (decod, miss)",context,toString(reg_UPT_EVENT_STATE [context]).c_str());
 
                       // Need Flush UPFT
@@ -820,6 +819,6 @@
                             reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
                             reg_EVENT_ADDRESS_DEST    [context] = good_addr;
-                            reg_EVENT_CAN_CONTINUE    [context] = false;
-                            
+                            reg_EVENT_CAN_CONTINUE    [context] = true;
+                            // reg_EVENT_CAN_CONTINUE    [context] = false;
                           }
                         
@@ -1184,8 +1183,8 @@
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_UFPT_STATE      : %s"  ,toString(reg_UFPT_EVENT_STATE [i]).c_str());
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_UPT_STATE       : %s"  ,toString(reg_UPT_EVENT_STATE [i]).c_str());
-//         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_VAL             : %d"  ,reg_EVENT_VAL             [i]);
+//      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_VAL             : %d"  ,reg_EVENT_VAL             [i]);
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_UPT_PTR         : %d"  ,reg_EVENT_UPT_PTR         [i]);
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_UPT_FULL        : %d"  ,reg_EVENT_UPT_FULL        [i]);
-//         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_IS_BRANCH       : %d"  ,reg_EVENT_IS_BRANCH       [i]);
+//      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_IS_BRANCH       : %d"  ,reg_EVENT_IS_BRANCH       [i]);
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_DEPTH           : %d"  ,reg_EVENT_DEPTH           [i]);
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_ADDRESS_SRC     : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC     [i],reg_EVENT_ADDRESS_SRC     [i]<<2);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_1-decod_unit_1-a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_1-decod_unit_1-a.cfg	(revision 144)
+++ 	(revision )
@@ -1,47 +1,0 @@
-Front_end
-1	1	+1	# nb_context                                                
-1	1	+1	# nb_decod_unit                                             
-32	32	+1	# size_general_data                                         
-4	4	+1	# size_ifetch_queue             [0] [nb_context]                
-4	4	+1	# nb_inst_fetch                 [0] [nb_context]                
-0	0	+1	# link_context_to_decod_unit    [0] [nb_context]                
-4	4	+1	# size_decod_queue              [0] [nb_decod_unit]             
-0	1	+1	# decod_queue_scheme            [0] [nb_decod_unit]             
-4	4	+1	# nb_inst_decod                 [0] [nb_decod_unit]             
-1	1	+1	# nb_context_select             [0] [nb_decod_unit]             
-1	1	+1	# context_select_priority       [0] [nb_decod_unit]             
-1	1	+1	# context_select_load_balancing [0] [nb_decod_unit]             
-1	1	+1	# nb_inst_branch_predict        
-2	2	+1	# nb_inst_branch_decod          
-2	2	+1	# nb_inst_branch_update         
-2	2	+1	# nb_inst_branch_complete       
-32	32	+1	# btb_size_queue                
-4	4	+1	# btb_associativity             
-2	2	+1	# btb_size_counter              
-3	3	+1	# btb_victim_scheme             
-1	1	+1	# dir_predictor_scheme          
-1	1	+1	# dir_have_bht                  [0] [3]                         
-1	1	+1	# dir_have_bht                  [1] [3]                         
-1	1	+1	# dir_have_bht                  [2] [3]                         
-1	1	+1	# dir_bht_size_shifter          [0] [3]                         
-1	1	+1	# dir_bht_size_shifter          [1] [3]                         
-1	1	+1	# dir_bht_size_shifter          [2] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [0] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [1] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [2] [3]                         
-1	1	+1	# dir_have_pht                  [0] [3]                         
-1	1	+1	# dir_have_pht                  [1] [3]                         
-1	1	+1	# dir_have_pht                  [2] [3]                         
-1	1	+1	# dir_pht_size_counter          [0] [3]                         
-1	1	+1	# dir_pht_size_counter          [1] [3]                         
-1	1	+1	# dir_pht_size_counter          [2] [3]                         
-1	1	+1	# dir_pht_nb_counter            [0] [3]                         
-1	1	+1	# dir_pht_nb_counter            [1] [3]                         
-1	1	+1	# dir_pht_nb_counter            [2] [3]                         
-1	1	+1	# dir_pht_size_address_share    [0] [3]                         
-1	1	+1	# dir_pht_size_address_share    [1] [3]                         
-1	1	+1	# dir_pht_size_address_share    [2] [3]                         
-8       8       +1	# ras_size_queue                [0] [nb_context]                
-1	1	+1	# upt_size_queue                [0] [nb_context]                
-1	1	+1	# ufpt_size_queue               [0] [nb_context]                
-1	1	+1	# size_inst_commit
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_1-a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_1-a.cfg	(revision 144)
+++ 	(revision )
@@ -1,65 +1,0 @@
-Front_end
-4	4	+1	# nb_context                                                
-1	1	+1	# nb_decod_unit                                             
-32	32	+1	# size_general_data                                         
-16	16	+1	# size_ifetch_queue             [0] [nb_context]                
-4	4	+1	# size_ifetch_queue             [1] [nb_context]                
-16	16	+1	# size_ifetch_queue             [2] [nb_context]                
-8	8	+1	# size_ifetch_queue             [3] [nb_context]                
-4	4	+1	# nb_inst_fetch                 [0] [nb_context]                
-2	2	+1	# nb_inst_fetch                 [1] [nb_context]                
-16	16	+1	# nb_inst_fetch                 [2] [nb_context]                
-1	1	+1	# nb_inst_fetch                 [3] [nb_context]                
-0	0	+1	# link_context_to_decod_unit    [0] [nb_context]                
-0	0	+1	# link_context_to_decod_unit    [1] [nb_context]                
-0	0	+1	# link_context_to_decod_unit    [2] [nb_context]                
-0	0	+1	# link_context_to_decod_unit    [3] [nb_context]                
-4	4	+1	# size_decod_queue              [0] [nb_decod_unit]             
-0	1	+1	# decod_queue_scheme            [0] [nb_decod_unit]             
-4	4	+1	# nb_inst_decod                 [0] [nb_decod_unit]             
-1	1	+1	# nb_context_select             [0] [nb_decod_unit]             
-1	1	+1	# context_select_priority       [0] [nb_decod_unit]             
-1	1	+1	# context_select_load_balancing [0] [nb_decod_unit]             
-1	1	+1	# nb_inst_branch_predict        
-2	2	+1	# nb_inst_branch_decod          
-2	2	+1	# nb_inst_branch_update         
-2	2	+1	# nb_inst_branch_complete       
-64	64	+1	# btb_size_queue                
-8	8	+1	# btb_associativity             
-2	2	+1	# btb_size_counter              
-3	3	+1	# btb_victim_scheme             
-1	1	+1	# dir_predictor_scheme          
-1	1	+1	# dir_have_bht                  [0] [3]                         
-1	1	+1	# dir_have_bht                  [1] [3]                         
-1	1	+1	# dir_have_bht                  [2] [3]                         
-1	1	+1	# dir_bht_size_shifter          [0] [3]                         
-1	1	+1	# dir_bht_size_shifter          [1] [3]                         
-1	1	+1	# dir_bht_size_shifter          [2] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [0] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [1] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [2] [3]                         
-1	1	+1	# dir_have_pht                  [0] [3]                         
-1	1	+1	# dir_have_pht                  [1] [3]                         
-1	1	+1	# dir_have_pht                  [2] [3]                         
-1	1	+1	# dir_pht_size_counter          [0] [3]                         
-1	1	+1	# dir_pht_size_counter          [1] [3]                         
-1	1	+1	# dir_pht_size_counter          [2] [3]                         
-1	1	+1	# dir_pht_nb_counter            [0] [3]                         
-1	1	+1	# dir_pht_nb_counter            [1] [3]                         
-1	1	+1	# dir_pht_nb_counter            [2] [3]                         
-1	1	+1	# dir_pht_size_address_share    [0] [3]                         
-1	1	+1	# dir_pht_size_address_share    [1] [3]                         
-1	1	+1	# dir_pht_size_address_share    [2] [3]                         
-8       8       +1	# ras_size_queue                [0] [nb_context]                
-2       2       +1	# ras_size_queue                [1] [nb_context]                
-4       4       +1	# ras_size_queue                [2] [nb_context]                
-2       2       +1	# ras_size_queue                [3] [nb_context]                
-16	16	+1	# upt_size_queue                [0] [nb_context]                
-1	1	+1	# upt_size_queue                [1] [nb_context]                
-2	2	+1	# upt_size_queue                [2] [nb_context]                
-8	8	+1	# upt_size_queue                [3] [nb_context]                
-6 	6 	+1	# ufpt_size_queue               [0] [nb_context]                
-1	1	+1	# ufpt_size_queue               [1] [nb_context]                
-1	1	+1	# ufpt_size_queue               [2] [nb_context]                
-4	4	+1	# ufpt_size_queue               [3] [nb_context]                
-1	1	+1	# size_inst_commit
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-a.cfg	(revision 144)
+++ 	(revision )
@@ -1,71 +1,0 @@
-Front_end
-4	4	+1	# nb_context                                                
-2	2	+1	# nb_decod_unit                                             
-32	32	+1	# size_general_data                                         
-8	8	+1	# size_ifetch_queue             [0] [nb_context]                
-4	4	+1	# size_ifetch_queue             [1] [nb_context]                
-16	16	+1	# size_ifetch_queue             [2] [nb_context]                
-8	8	+1	# size_ifetch_queue             [3] [nb_context]                
-4	4	+1	# nb_inst_fetch                 [0] [nb_context]                
-2	2	+1	# nb_inst_fetch                 [1] [nb_context]                
-16	16	+1	# nb_inst_fetch                 [2] [nb_context]                
-1	1	+1	# nb_inst_fetch                 [3] [nb_context]                
-1	1	+1	# link_context_to_decod_unit    [0] [nb_context]                
-0	0	+1	# link_context_to_decod_unit    [1] [nb_context]                
-1	1	+1	# link_context_to_decod_unit    [2] [nb_context]                
-1	1	+1	# link_context_to_decod_unit    [3] [nb_context]                
-4	4	+1	# size_decod_queue              [0] [nb_decod_unit]             
-12	12	+1	# size_decod_queue              [1] [nb_decod_unit]             
-1	1	+1	# decod_queue_scheme            [0] [nb_decod_unit]             
-0	0	+1	# decod_queue_scheme            [1] [nb_decod_unit]             
-2	2	+1	# nb_inst_decod                 [0] [nb_decod_unit]             
-6	6	+1	# nb_inst_decod                 [1] [nb_decod_unit]             
-1	1	+1	# nb_context_select             [0] [nb_decod_unit]             
-1	3	*3	# nb_context_select             [1] [nb_decod_unit]             
-1	1	+1	# context_select_priority       [0] [nb_decod_unit]             
-1	1	+1	# context_select_priority       [1] [nb_decod_unit]             
-1	1	+1	# context_select_load_balancing [0] [nb_decod_unit]             
-1	1	+1	# context_select_load_balancing [1] [nb_decod_unit]             
-1	1	+1	# nb_inst_branch_predict        
-2	2	+1	# nb_inst_branch_decod          
-2	2	+1	# nb_inst_branch_update         
-2	2	+1	# nb_inst_branch_complete       
-64	64	+1	# btb_size_queue                
-8	8	+1	# btb_associativity             
-2	2	+1	# btb_size_counter              
-3	3	+1	# btb_victim_scheme             
-1	1	+1	# dir_predictor_scheme          
-1	1	+1	# dir_have_bht                  [0] [3]                         
-1	1	+1	# dir_have_bht                  [1] [3]                         
-1	1	+1	# dir_have_bht                  [2] [3]                         
-1	1	+1	# dir_bht_size_shifter          [0] [3]                         
-1	1	+1	# dir_bht_size_shifter          [1] [3]                         
-1	1	+1	# dir_bht_size_shifter          [2] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [0] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [1] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [2] [3]                         
-1	1	+1	# dir_have_pht                  [0] [3]                         
-1	1	+1	# dir_have_pht                  [1] [3]                         
-1	1	+1	# dir_have_pht                  [2] [3]                         
-1	1	+1	# dir_pht_size_counter          [0] [3]                         
-1	1	+1	# dir_pht_size_counter          [1] [3]                         
-1	1	+1	# dir_pht_size_counter          [2] [3]                         
-1	1	+1	# dir_pht_nb_counter            [0] [3]                         
-1	1	+1	# dir_pht_nb_counter            [1] [3]                         
-1	1	+1	# dir_pht_nb_counter            [2] [3]                         
-1	1	+1	# dir_pht_size_address_share    [0] [3]                         
-1	1	+1	# dir_pht_size_address_share    [1] [3]                         
-1	1	+1	# dir_pht_size_address_share    [2] [3]                         
-8       8       +1	# ras_size_queue                [0] [nb_context]                
-2       2       +1	# ras_size_queue                [1] [nb_context]                
-4       4       +1	# ras_size_queue                [2] [nb_context]                
-2       2       +1	# ras_size_queue                [3] [nb_context]                
-16	16	+1	# upt_size_queue                [0] [nb_context]                
-1	1	+1	# upt_size_queue                [1] [nb_context]                
-2	2	+1	# upt_size_queue                [2] [nb_context]                
-8	8	+1	# upt_size_queue                [3] [nb_context]                
-6  	6 	+1	# ufpt_size_queue               [0] [nb_context]                
-1	1	+1	# ufpt_size_queue               [1] [nb_context]                
-1	1	+1	# ufpt_size_queue               [2] [nb_context]                
-4	4	+1	# ufpt_size_queue               [3] [nb_context]                
-1	1	+1	# size_inst_commit
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-b.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-b.cfg	(revision 144)
+++ 	(revision )
@@ -1,71 +1,0 @@
-Front_end
-4	4	+1	# nb_context                                                
-2	2	+1	# nb_decod_unit                                             
-32	32	+1	# size_general_data                                         
-4	4	+1	# size_ifetch_queue             [0] [nb_context]                
-8	8	+1	# size_ifetch_queue             [1] [nb_context]                
-32	32	+1	# size_ifetch_queue             [2] [nb_context]                
-8	8	+1	# size_ifetch_queue             [3] [nb_context]                
-4	4	+1	# nb_inst_fetch                 [0] [nb_context]                
-2	2	+1	# nb_inst_fetch                 [1] [nb_context]                
-16	16	+1	# nb_inst_fetch                 [2] [nb_context]                
-1	1	+1	# nb_inst_fetch                 [3] [nb_context]                
-1	1	+1	# link_context_to_decod_unit    [0] [nb_context]                
-0	0	+1	# link_context_to_decod_unit    [1] [nb_context]                
-1	1	+1	# link_context_to_decod_unit    [2] [nb_context]                
-1	1	+1	# link_context_to_decod_unit    [3] [nb_context]                
-4	4	+1	# size_decod_queue              [0] [nb_decod_unit]             
-12	12	+1	# size_decod_queue              [1] [nb_decod_unit]             
-0	0	+1	# decod_queue_scheme            [0] [nb_decod_unit]             
-1	1	+1	# decod_queue_scheme            [1] [nb_decod_unit]             
-2	2	+1	# nb_inst_decod                 [0] [nb_decod_unit]             
-6	6	+1	# nb_inst_decod                 [1] [nb_decod_unit]             
-1	1	+1	# nb_context_select             [0] [nb_decod_unit]             
-3	3	*3	# nb_context_select             [1] [nb_decod_unit]             
-1	1	+1	# context_select_priority       [0] [nb_decod_unit]             
-1	1	+1	# context_select_priority       [1] [nb_decod_unit]             
-1	1	+1	# context_select_load_balancing [0] [nb_decod_unit]             
-1	1	+1	# context_select_load_balancing [1] [nb_decod_unit]             
-1	1	+1	# nb_inst_branch_predict        
-2	2	+1	# nb_inst_branch_decod          
-2	2	+1	# nb_inst_branch_update         
-2	2	+1	# nb_inst_branch_complete       
-64	64	+1	# btb_size_queue                
-8	8	+1	# btb_associativity             
-2	2	+1	# btb_size_counter              
-3	3	+1	# btb_victim_scheme             
-1	1	+1	# dir_predictor_scheme          
-1	1	+1	# dir_have_bht                  [0] [3]                         
-1	1	+1	# dir_have_bht                  [1] [3]                         
-1	1	+1	# dir_have_bht                  [2] [3]                         
-1	1	+1	# dir_bht_size_shifter          [0] [3]                         
-1	1	+1	# dir_bht_size_shifter          [1] [3]                         
-1	1	+1	# dir_bht_size_shifter          [2] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [0] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [1] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [2] [3]                         
-1	1	+1	# dir_have_pht                  [0] [3]                         
-1	1	+1	# dir_have_pht                  [1] [3]                         
-1	1	+1	# dir_have_pht                  [2] [3]                         
-1	1	+1	# dir_pht_size_counter          [0] [3]                         
-1	1	+1	# dir_pht_size_counter          [1] [3]                         
-1	1	+1	# dir_pht_size_counter          [2] [3]                         
-1	1	+1	# dir_pht_nb_counter            [0] [3]                         
-1	1	+1	# dir_pht_nb_counter            [1] [3]                         
-1	1	+1	# dir_pht_nb_counter            [2] [3]                         
-1	1	+1	# dir_pht_size_address_share    [0] [3]                         
-1	1	+1	# dir_pht_size_address_share    [1] [3]                         
-1	1	+1	# dir_pht_size_address_share    [2] [3]                         
-8       8       +1	# ras_size_queue                [0] [nb_context]                
-2       2       +1	# ras_size_queue                [1] [nb_context]                
-4       4       +1	# ras_size_queue                [2] [nb_context]                
-2       2       +1	# ras_size_queue                [3] [nb_context]                
-16	16	+1	# upt_size_queue                [0] [nb_context]                
-1	1	+1	# upt_size_queue                [1] [nb_context]                
-2	2	+1	# upt_size_queue                [2] [nb_context]                
-8	8	+1	# upt_size_queue                [3] [nb_context]                
-6  	6 	+1	# ufpt_size_queue               [0] [nb_context]                
-1	1	+1	# ufpt_size_queue               [1] [nb_context]                
-1	1	+1	# ufpt_size_queue               [2] [nb_context]                
-4	4	+1	# ufpt_size_queue               [3] [nb_context]                
-1	1	+1	# size_inst_commit
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,47 +1,0 @@
-Front_end
-1	1	+1	# nb_context                                                
-1	1	+1	# nb_decod_unit                                             
-32	32	+1	# size_general_data                                         
-1	1	+1	# size_ifetch_queue             [0] [nb_context]                
-1	1	+1	# nb_inst_fetch                 [0] [nb_context]                
-0	0	+1	# link_context_to_decod_unit    [0] [nb_context]                
-1	1	+1	# size_decod_queue              [0] [nb_decod_unit]             
-0	1	+1	# decod_queue_scheme            [0] [nb_decod_unit]             
-1	1	+1	# nb_inst_decod                 [0] [nb_decod_unit]             
-1	1	+1	# nb_context_select             [0] [nb_decod_unit]             
-1	1	+1	# context_select_priority       [0] [nb_decod_unit]             
-1	1	+1	# context_select_load_balancing [0] [nb_decod_unit]             
-1	1	+1	# nb_inst_branch_predict        
-1	1	+1	# nb_inst_branch_decod          
-1	1	+1	# nb_inst_branch_update         
-1	1	+1	# nb_inst_branch_complete       
-1	1	+1	# btb_size_queue                
-1	1	+1	# btb_associativity             
-2	2	+1	# btb_size_counter              
-1	1	+1	# btb_victim_scheme             
-1	1	+1	# dir_predictor_scheme          
-1	1	+1	# dir_have_bht                  [0] [3]                         
-1	1	+1	# dir_have_bht                  [1] [3]                         
-1	1	+1	# dir_have_bht                  [2] [3]                         
-1	1	+1	# dir_bht_size_shifter          [0] [3]                         
-1	1	+1	# dir_bht_size_shifter          [1] [3]                         
-1	1	+1	# dir_bht_size_shifter          [2] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [0] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [1] [3]                         
-1	1	+1	# dir_bht_nb_shifter            [2] [3]                         
-1	1	+1	# dir_have_pht                  [0] [3]                         
-1	1	+1	# dir_have_pht                  [1] [3]                         
-1	1	+1	# dir_have_pht                  [2] [3]                         
-1	1	+1	# dir_pht_size_counter          [0] [3]                         
-1	1	+1	# dir_pht_size_counter          [1] [3]                         
-1	1	+1	# dir_pht_size_counter          [2] [3]                         
-1	1	+1	# dir_pht_nb_counter            [0] [3]                         
-1	1	+1	# dir_pht_nb_counter            [1] [3]                         
-1	1	+1	# dir_pht_nb_counter            [2] [3]                         
-1	1	+1	# dir_pht_size_address_share    [0] [3]                         
-1	1	+1	# dir_pht_size_address_share    [1] [3]                         
-1	1	+1	# dir_pht_size_address_share    [2] [3]                         
-2       2       +1	# ras_size_queue                [0] [nb_context]                
-1	1	+1	# upt_size_queue                [0] [nb_context]                
-1	1	+1	# ufpt_size_queue               [0] [nb_context]                
-1	1	+1	# size_inst_commit 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-context_1-decod_unit_1-a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-context_1-decod_unit_1-a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-context_1-decod_unit_1-a.gen	(revision 145)
@@ -0,0 +1,47 @@
+Front_end
+1	1	+1	# nb_context                                                
+1	1	+1	# nb_decod_unit                                             
+32	32	+1	# size_general_data                                         
+4	4	+1	# size_ifetch_queue             [0] [nb_context]                
+4	4	+1	# nb_inst_fetch                 [0] [nb_context]                
+0	0	+1	# link_context_to_decod_unit    [0] [nb_context]                
+4	4	+1	# size_decod_queue              [0] [nb_decod_unit]             
+0	1	+1	# decod_queue_scheme            [0] [nb_decod_unit]             
+4	4	+1	# nb_inst_decod                 [0] [nb_decod_unit]             
+1	1	+1	# nb_context_select             [0] [nb_decod_unit]             
+1	1	+1	# context_select_priority       [0] [nb_decod_unit]             
+1	1	+1	# context_select_load_balancing [0] [nb_decod_unit]             
+1	1	+1	# nb_inst_branch_predict        
+2	2	+1	# nb_inst_branch_decod          
+2	2	+1	# nb_inst_branch_update         
+2	2	+1	# nb_inst_branch_complete       
+32	32	+1	# btb_size_queue                
+4	4	+1	# btb_associativity             
+2	2	+1	# btb_size_counter              
+3	3	+1	# btb_victim_scheme             
+1	1	+1	# dir_predictor_scheme          
+1	1	+1	# dir_have_bht                  [0] [3]                         
+1	1	+1	# dir_have_bht                  [1] [3]                         
+1	1	+1	# dir_have_bht                  [2] [3]                         
+1	1	+1	# dir_bht_size_shifter          [0] [3]                         
+1	1	+1	# dir_bht_size_shifter          [1] [3]                         
+1	1	+1	# dir_bht_size_shifter          [2] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [0] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [1] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [2] [3]                         
+1	1	+1	# dir_have_pht                  [0] [3]                         
+1	1	+1	# dir_have_pht                  [1] [3]                         
+1	1	+1	# dir_have_pht                  [2] [3]                         
+1	1	+1	# dir_pht_size_counter          [0] [3]                         
+1	1	+1	# dir_pht_size_counter          [1] [3]                         
+1	1	+1	# dir_pht_size_counter          [2] [3]                         
+1	1	+1	# dir_pht_nb_counter            [0] [3]                         
+1	1	+1	# dir_pht_nb_counter            [1] [3]                         
+1	1	+1	# dir_pht_nb_counter            [2] [3]                         
+1	1	+1	# dir_pht_size_address_share    [0] [3]                         
+1	1	+1	# dir_pht_size_address_share    [1] [3]                         
+1	1	+1	# dir_pht_size_address_share    [2] [3]                         
+8       8       +1	# ras_size_queue                [0] [nb_context]                
+1	1	+1	# upt_size_queue                [0] [nb_context]                
+1	1	+1	# ufpt_size_queue               [0] [nb_context]                
+1	1	+1	# size_inst_commit
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-context_4-decod_unit_1-a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-context_4-decod_unit_1-a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-context_4-decod_unit_1-a.gen	(revision 145)
@@ -0,0 +1,65 @@
+Front_end
+4	4	+1	# nb_context                                                
+1	1	+1	# nb_decod_unit                                             
+32	32	+1	# size_general_data                                         
+16	16	+1	# size_ifetch_queue             [0] [nb_context]                
+4	4	+1	# size_ifetch_queue             [1] [nb_context]                
+16	16	+1	# size_ifetch_queue             [2] [nb_context]                
+8	8	+1	# size_ifetch_queue             [3] [nb_context]                
+4	4	+1	# nb_inst_fetch                 [0] [nb_context]                
+2	2	+1	# nb_inst_fetch                 [1] [nb_context]                
+16	16	+1	# nb_inst_fetch                 [2] [nb_context]                
+1	1	+1	# nb_inst_fetch                 [3] [nb_context]                
+0	0	+1	# link_context_to_decod_unit    [0] [nb_context]                
+0	0	+1	# link_context_to_decod_unit    [1] [nb_context]                
+0	0	+1	# link_context_to_decod_unit    [2] [nb_context]                
+0	0	+1	# link_context_to_decod_unit    [3] [nb_context]                
+4	4	+1	# size_decod_queue              [0] [nb_decod_unit]             
+0	1	+1	# decod_queue_scheme            [0] [nb_decod_unit]             
+4	4	+1	# nb_inst_decod                 [0] [nb_decod_unit]             
+1	1	+1	# nb_context_select             [0] [nb_decod_unit]             
+1	1	+1	# context_select_priority       [0] [nb_decod_unit]             
+1	1	+1	# context_select_load_balancing [0] [nb_decod_unit]             
+1	1	+1	# nb_inst_branch_predict        
+2	2	+1	# nb_inst_branch_decod          
+2	2	+1	# nb_inst_branch_update         
+2	2	+1	# nb_inst_branch_complete       
+64	64	+1	# btb_size_queue                
+8	8	+1	# btb_associativity             
+2	2	+1	# btb_size_counter              
+3	3	+1	# btb_victim_scheme             
+1	1	+1	# dir_predictor_scheme          
+1	1	+1	# dir_have_bht                  [0] [3]                         
+1	1	+1	# dir_have_bht                  [1] [3]                         
+1	1	+1	# dir_have_bht                  [2] [3]                         
+1	1	+1	# dir_bht_size_shifter          [0] [3]                         
+1	1	+1	# dir_bht_size_shifter          [1] [3]                         
+1	1	+1	# dir_bht_size_shifter          [2] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [0] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [1] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [2] [3]                         
+1	1	+1	# dir_have_pht                  [0] [3]                         
+1	1	+1	# dir_have_pht                  [1] [3]                         
+1	1	+1	# dir_have_pht                  [2] [3]                         
+1	1	+1	# dir_pht_size_counter          [0] [3]                         
+1	1	+1	# dir_pht_size_counter          [1] [3]                         
+1	1	+1	# dir_pht_size_counter          [2] [3]                         
+1	1	+1	# dir_pht_nb_counter            [0] [3]                         
+1	1	+1	# dir_pht_nb_counter            [1] [3]                         
+1	1	+1	# dir_pht_nb_counter            [2] [3]                         
+1	1	+1	# dir_pht_size_address_share    [0] [3]                         
+1	1	+1	# dir_pht_size_address_share    [1] [3]                         
+1	1	+1	# dir_pht_size_address_share    [2] [3]                         
+8       8       +1	# ras_size_queue                [0] [nb_context]                
+2       2       +1	# ras_size_queue                [1] [nb_context]                
+4       4       +1	# ras_size_queue                [2] [nb_context]                
+2       2       +1	# ras_size_queue                [3] [nb_context]                
+16	16	+1	# upt_size_queue                [0] [nb_context]                
+1	1	+1	# upt_size_queue                [1] [nb_context]                
+2	2	+1	# upt_size_queue                [2] [nb_context]                
+8	8	+1	# upt_size_queue                [3] [nb_context]                
+6 	6 	+1	# ufpt_size_queue               [0] [nb_context]                
+1	1	+1	# ufpt_size_queue               [1] [nb_context]                
+1	1	+1	# ufpt_size_queue               [2] [nb_context]                
+4	4	+1	# ufpt_size_queue               [3] [nb_context]                
+1	1	+1	# size_inst_commit
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-context_4-decod_unit_2-a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-context_4-decod_unit_2-a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-context_4-decod_unit_2-a.gen	(revision 145)
@@ -0,0 +1,71 @@
+Front_end
+4	4	+1	# nb_context                                                
+2	2	+1	# nb_decod_unit                                             
+32	32	+1	# size_general_data                                         
+8	8	+1	# size_ifetch_queue             [0] [nb_context]                
+4	4	+1	# size_ifetch_queue             [1] [nb_context]                
+16	16	+1	# size_ifetch_queue             [2] [nb_context]                
+8	8	+1	# size_ifetch_queue             [3] [nb_context]                
+4	4	+1	# nb_inst_fetch                 [0] [nb_context]                
+2	2	+1	# nb_inst_fetch                 [1] [nb_context]                
+16	16	+1	# nb_inst_fetch                 [2] [nb_context]                
+1	1	+1	# nb_inst_fetch                 [3] [nb_context]                
+1	1	+1	# link_context_to_decod_unit    [0] [nb_context]                
+0	0	+1	# link_context_to_decod_unit    [1] [nb_context]                
+1	1	+1	# link_context_to_decod_unit    [2] [nb_context]                
+1	1	+1	# link_context_to_decod_unit    [3] [nb_context]                
+4	4	+1	# size_decod_queue              [0] [nb_decod_unit]             
+12	12	+1	# size_decod_queue              [1] [nb_decod_unit]             
+1	1	+1	# decod_queue_scheme            [0] [nb_decod_unit]             
+0	0	+1	# decod_queue_scheme            [1] [nb_decod_unit]             
+2	2	+1	# nb_inst_decod                 [0] [nb_decod_unit]             
+6	6	+1	# nb_inst_decod                 [1] [nb_decod_unit]             
+1	1	+1	# nb_context_select             [0] [nb_decod_unit]             
+1	3	*3	# nb_context_select             [1] [nb_decod_unit]             
+1	1	+1	# context_select_priority       [0] [nb_decod_unit]             
+1	1	+1	# context_select_priority       [1] [nb_decod_unit]             
+1	1	+1	# context_select_load_balancing [0] [nb_decod_unit]             
+1	1	+1	# context_select_load_balancing [1] [nb_decod_unit]             
+1	1	+1	# nb_inst_branch_predict        
+2	2	+1	# nb_inst_branch_decod          
+2	2	+1	# nb_inst_branch_update         
+2	2	+1	# nb_inst_branch_complete       
+64	64	+1	# btb_size_queue                
+8	8	+1	# btb_associativity             
+2	2	+1	# btb_size_counter              
+3	3	+1	# btb_victim_scheme             
+1	1	+1	# dir_predictor_scheme          
+1	1	+1	# dir_have_bht                  [0] [3]                         
+1	1	+1	# dir_have_bht                  [1] [3]                         
+1	1	+1	# dir_have_bht                  [2] [3]                         
+1	1	+1	# dir_bht_size_shifter          [0] [3]                         
+1	1	+1	# dir_bht_size_shifter          [1] [3]                         
+1	1	+1	# dir_bht_size_shifter          [2] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [0] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [1] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [2] [3]                         
+1	1	+1	# dir_have_pht                  [0] [3]                         
+1	1	+1	# dir_have_pht                  [1] [3]                         
+1	1	+1	# dir_have_pht                  [2] [3]                         
+1	1	+1	# dir_pht_size_counter          [0] [3]                         
+1	1	+1	# dir_pht_size_counter          [1] [3]                         
+1	1	+1	# dir_pht_size_counter          [2] [3]                         
+1	1	+1	# dir_pht_nb_counter            [0] [3]                         
+1	1	+1	# dir_pht_nb_counter            [1] [3]                         
+1	1	+1	# dir_pht_nb_counter            [2] [3]                         
+1	1	+1	# dir_pht_size_address_share    [0] [3]                         
+1	1	+1	# dir_pht_size_address_share    [1] [3]                         
+1	1	+1	# dir_pht_size_address_share    [2] [3]                         
+8       8       +1	# ras_size_queue                [0] [nb_context]                
+2       2       +1	# ras_size_queue                [1] [nb_context]                
+4       4       +1	# ras_size_queue                [2] [nb_context]                
+2       2       +1	# ras_size_queue                [3] [nb_context]                
+16	16	+1	# upt_size_queue                [0] [nb_context]                
+1	1	+1	# upt_size_queue                [1] [nb_context]                
+2	2	+1	# upt_size_queue                [2] [nb_context]                
+8	8	+1	# upt_size_queue                [3] [nb_context]                
+6  	6 	+1	# ufpt_size_queue               [0] [nb_context]                
+1	1	+1	# ufpt_size_queue               [1] [nb_context]                
+1	1	+1	# ufpt_size_queue               [2] [nb_context]                
+4	4	+1	# ufpt_size_queue               [3] [nb_context]                
+1	1	+1	# size_inst_commit
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-context_4-decod_unit_2-b.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-context_4-decod_unit_2-b.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-context_4-decod_unit_2-b.gen	(revision 145)
@@ -0,0 +1,71 @@
+Front_end
+4	4	+1	# nb_context                                                
+2	2	+1	# nb_decod_unit                                             
+32	32	+1	# size_general_data                                         
+4	4	+1	# size_ifetch_queue             [0] [nb_context]                
+8	8	+1	# size_ifetch_queue             [1] [nb_context]                
+32	32	+1	# size_ifetch_queue             [2] [nb_context]                
+8	8	+1	# size_ifetch_queue             [3] [nb_context]                
+4	4	+1	# nb_inst_fetch                 [0] [nb_context]                
+2	2	+1	# nb_inst_fetch                 [1] [nb_context]                
+16	16	+1	# nb_inst_fetch                 [2] [nb_context]                
+1	1	+1	# nb_inst_fetch                 [3] [nb_context]                
+1	1	+1	# link_context_to_decod_unit    [0] [nb_context]                
+0	0	+1	# link_context_to_decod_unit    [1] [nb_context]                
+1	1	+1	# link_context_to_decod_unit    [2] [nb_context]                
+1	1	+1	# link_context_to_decod_unit    [3] [nb_context]                
+4	4	+1	# size_decod_queue              [0] [nb_decod_unit]             
+12	12	+1	# size_decod_queue              [1] [nb_decod_unit]             
+0	0	+1	# decod_queue_scheme            [0] [nb_decod_unit]             
+1	1	+1	# decod_queue_scheme            [1] [nb_decod_unit]             
+2	2	+1	# nb_inst_decod                 [0] [nb_decod_unit]             
+6	6	+1	# nb_inst_decod                 [1] [nb_decod_unit]             
+1	1	+1	# nb_context_select             [0] [nb_decod_unit]             
+3	3	*3	# nb_context_select             [1] [nb_decod_unit]             
+1	1	+1	# context_select_priority       [0] [nb_decod_unit]             
+1	1	+1	# context_select_priority       [1] [nb_decod_unit]             
+1	1	+1	# context_select_load_balancing [0] [nb_decod_unit]             
+1	1	+1	# context_select_load_balancing [1] [nb_decod_unit]             
+1	1	+1	# nb_inst_branch_predict        
+2	2	+1	# nb_inst_branch_decod          
+2	2	+1	# nb_inst_branch_update         
+2	2	+1	# nb_inst_branch_complete       
+64	64	+1	# btb_size_queue                
+8	8	+1	# btb_associativity             
+2	2	+1	# btb_size_counter              
+3	3	+1	# btb_victim_scheme             
+1	1	+1	# dir_predictor_scheme          
+1	1	+1	# dir_have_bht                  [0] [3]                         
+1	1	+1	# dir_have_bht                  [1] [3]                         
+1	1	+1	# dir_have_bht                  [2] [3]                         
+1	1	+1	# dir_bht_size_shifter          [0] [3]                         
+1	1	+1	# dir_bht_size_shifter          [1] [3]                         
+1	1	+1	# dir_bht_size_shifter          [2] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [0] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [1] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [2] [3]                         
+1	1	+1	# dir_have_pht                  [0] [3]                         
+1	1	+1	# dir_have_pht                  [1] [3]                         
+1	1	+1	# dir_have_pht                  [2] [3]                         
+1	1	+1	# dir_pht_size_counter          [0] [3]                         
+1	1	+1	# dir_pht_size_counter          [1] [3]                         
+1	1	+1	# dir_pht_size_counter          [2] [3]                         
+1	1	+1	# dir_pht_nb_counter            [0] [3]                         
+1	1	+1	# dir_pht_nb_counter            [1] [3]                         
+1	1	+1	# dir_pht_nb_counter            [2] [3]                         
+1	1	+1	# dir_pht_size_address_share    [0] [3]                         
+1	1	+1	# dir_pht_size_address_share    [1] [3]                         
+1	1	+1	# dir_pht_size_address_share    [2] [3]                         
+8       8       +1	# ras_size_queue                [0] [nb_context]                
+2       2       +1	# ras_size_queue                [1] [nb_context]                
+4       4       +1	# ras_size_queue                [2] [nb_context]                
+2       2       +1	# ras_size_queue                [3] [nb_context]                
+16	16	+1	# upt_size_queue                [0] [nb_context]                
+1	1	+1	# upt_size_queue                [1] [nb_context]                
+2	2	+1	# upt_size_queue                [2] [nb_context]                
+8	8	+1	# upt_size_queue                [3] [nb_context]                
+6  	6 	+1	# ufpt_size_queue               [0] [nb_context]                
+1	1	+1	# ufpt_size_queue               [1] [nb_context]                
+1	1	+1	# ufpt_size_queue               [2] [nb_context]                
+4	4	+1	# ufpt_size_queue               [3] [nb_context]                
+1	1	+1	# size_inst_commit
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,47 @@
+Front_end
+1	1	+1	# nb_context                                                
+1	1	+1	# nb_decod_unit                                             
+32	32	+1	# size_general_data                                         
+1	1	+1	# size_ifetch_queue             [0] [nb_context]                
+1	1	+1	# nb_inst_fetch                 [0] [nb_context]                
+0	0	+1	# link_context_to_decod_unit    [0] [nb_context]                
+1	1	+1	# size_decod_queue              [0] [nb_decod_unit]             
+0	1	+1	# decod_queue_scheme            [0] [nb_decod_unit]             
+1	1	+1	# nb_inst_decod                 [0] [nb_decod_unit]             
+1	1	+1	# nb_context_select             [0] [nb_decod_unit]             
+1	1	+1	# context_select_priority       [0] [nb_decod_unit]             
+1	1	+1	# context_select_load_balancing [0] [nb_decod_unit]             
+1	1	+1	# nb_inst_branch_predict        
+1	1	+1	# nb_inst_branch_decod          
+1	1	+1	# nb_inst_branch_update         
+1	1	+1	# nb_inst_branch_complete       
+1	1	+1	# btb_size_queue                
+1	1	+1	# btb_associativity             
+2	2	+1	# btb_size_counter              
+1	1	+1	# btb_victim_scheme             
+1	1	+1	# dir_predictor_scheme          
+1	1	+1	# dir_have_bht                  [0] [3]                         
+1	1	+1	# dir_have_bht                  [1] [3]                         
+1	1	+1	# dir_have_bht                  [2] [3]                         
+1	1	+1	# dir_bht_size_shifter          [0] [3]                         
+1	1	+1	# dir_bht_size_shifter          [1] [3]                         
+1	1	+1	# dir_bht_size_shifter          [2] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [0] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [1] [3]                         
+1	1	+1	# dir_bht_nb_shifter            [2] [3]                         
+1	1	+1	# dir_have_pht                  [0] [3]                         
+1	1	+1	# dir_have_pht                  [1] [3]                         
+1	1	+1	# dir_have_pht                  [2] [3]                         
+1	1	+1	# dir_pht_size_counter          [0] [3]                         
+1	1	+1	# dir_pht_size_counter          [1] [3]                         
+1	1	+1	# dir_pht_size_counter          [2] [3]                         
+1	1	+1	# dir_pht_nb_counter            [0] [3]                         
+1	1	+1	# dir_pht_nb_counter            [1] [3]                         
+1	1	+1	# dir_pht_nb_counter            [2] [3]                         
+1	1	+1	# dir_pht_size_address_share    [0] [3]                         
+1	1	+1	# dir_pht_size_address_share    [1] [3]                         
+1	1	+1	# dir_pht_size_address_share    [2] [3]                         
+2       2       +1	# ras_size_queue                [0] [nb_context]                
+1	1	+1	# upt_size_queue                [0] [nb_context]                
+1	1	+1	# ufpt_size_queue               [0] [nb_context]                
+1	1	+1	# size_inst_commit 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,21 +1,0 @@
-Commit_unit
-1	1	+1	# nb_front_end            
-1	1	+1	# nb_context              [0]    [nb_front_end]
-1	1	+1	# nb_rename_unit          
-1	1	+1	# size_queue              
-1	1	+1	# nb_bank                 
-1	1	+1	# nb_inst_insert          [0]    [nb_rename_unit]
-1	1	+1	# nb_inst_retire	  [0]    [nb_rename_unit]
-1	1	+1	# nb_inst_commit
-1	1	+1	# nb_inst_reexecute	 
-1	1	+1	# nb_inst_branch_complete 
-0	0	+1	# nb_branch_speculated    [0][0] [nb_front_end][nb_context]
-1       1       +1      # size_nb_inst_decod
-32	32	+1	# size_general_data       
-1	1	+1	# size_store_queue_ptr    
-0	0	+1	# size_load_queue_ptr     
-5	5	+1	# size_general_register   
-1	1	+1	# size_special_register   
-1	1	+1	# priority              
-1	1	+1	# load_balancing        
-1	1	+1	# nb_rename_unit_select 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg	(revision 144)
+++ 	(revision )
@@ -1,21 +1,0 @@
-Commit_unit
-1	1	+1	# nb_front_end            
-1	1	+1	# nb_context              [0]    [nb_front_end]
-1	1	+1	# nb_rename_unit          
-64 	64	*2	# size_queue              
-4	8 	*2	# nb_bank                 
-1	4	*4	# nb_inst_insert          [0]    [nb_rename_unit]
-1	4	*4	# nb_inst_retire	  [0]    [nb_rename_unit]
-1	4	*4	# nb_inst_commit
-1	1	+1	# nb_inst_reexecute	 
-1	1	+1	# nb_inst_branch_complete 
-0	0	+1	# nb_branch_speculated    [0][0] [nb_front_end][nb_context]
-1       1       +1      # size_nb_inst_decod
-32	32	+1	# size_general_data       
-1	1	+1	# size_store_queue_ptr    
-0	0	+1	# size_load_queue_ptr     
-5	5	+1	# size_general_register   
-1	1	+1	# size_special_register   
-1	1	+1	# priority              
-1	1	+1	# load_balancing        
-1	1	+1	# nb_rename_unit_select 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,21 @@
+Commit_unit
+1	1	+1	# nb_front_end            
+1	1	+1	# nb_context              [0]    [nb_front_end]
+1	1	+1	# nb_rename_unit          
+1	1	+1	# size_queue              
+1	1	+1	# nb_bank                 
+1	1	+1	# nb_inst_insert          [0]    [nb_rename_unit]
+1	1	+1	# nb_inst_retire	  [0]    [nb_rename_unit]
+1	1	+1	# nb_inst_commit
+1	1	+1	# nb_inst_reexecute	 
+1	1	+1	# nb_inst_branch_complete 
+0	0	+1	# nb_branch_speculated    [0][0] [nb_front_end][nb_context]
+1       1       +1      # size_nb_inst_decod
+32	32	+1	# size_general_data       
+1	1	+1	# size_store_queue_ptr    
+0	0	+1	# size_load_queue_ptr     
+5	5	+1	# size_general_register   
+1	1	+1	# size_special_register   
+1	1	+1	# priority              
+1	1	+1	# load_balancing        
+1	1	+1	# nb_rename_unit_select 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/configuration/config_mono_rename_unit.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/configuration/config_mono_rename_unit.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/configuration/config_mono_rename_unit.gen	(revision 145)
@@ -0,0 +1,21 @@
+Commit_unit
+1	1	+1	# nb_front_end            
+1	1	+1	# nb_context              [0]    [nb_front_end]
+1	1	+1	# nb_rename_unit          
+64 	64	*2	# size_queue              
+4	8 	*2	# nb_bank                 
+1	4	*4	# nb_inst_insert          [0]    [nb_rename_unit]
+1	4	*4	# nb_inst_retire	  [0]    [nb_rename_unit]
+1	4	*4	# nb_inst_commit
+1	1	+1	# nb_inst_reexecute	 
+1	1	+1	# nb_inst_branch_complete 
+0	0	+1	# nb_branch_speculated    [0][0] [nb_front_end][nb_context]
+1       1       +1      # size_nb_inst_decod
+32	32	+1	# size_general_data       
+1	1	+1	# size_store_queue_ptr    
+0	0	+1	# size_load_queue_ptr     
+5	5	+1	# size_general_register   
+1	1	+1	# size_special_register   
+1	1	+1	# priority              
+1	1	+1	# load_balancing        
+1	1	+1	# nb_rename_unit_select 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 145)
@@ -74,5 +74,5 @@
   public    : counter_t                     ** _stat_nb_cycle_state_wait_end      ;//[nb_thread]
 
-// public    : uint32_t                       * _stat_last_inst                    ;//[nb_thread]
+//public    : uint32_t                       * _stat_last_inst                    ;//[nb_thread]
   public    : uint32_t                       * _stat_last_inst_type               ;//[nb_thread]
   public    : uint32_t                       * _stat_last_inst_operation          ;//[nb_thread]
@@ -97,4 +97,5 @@
 //public    : SC_IN (Tcontext_t         ) ***  in_INSERT_RENAME_UNIT_ID            ;//[nb_rename_unit][nb_inst_insert]
   public    : SC_IN (Tdepth_t           ) ***  in_INSERT_DEPTH                     ;//[nb_rename_unit][nb_inst_insert]
+  public    : SC_IN (Tcontrol_t         ) ***  in_INSERT_SAVE_RAT                  ;//[nb_rename_unit][nb_inst_insert]
 #ifdef STATISTICS
   public    : SC_IN (uint32_t           ) ***  in_INSERT_INSTRUCTION               ;//[nb_rename_unit][nb_inst_insert]
@@ -141,4 +142,5 @@
   public    : SC_OUT(Tcontext_t         ) *** out_RETIRE_CONTEXT_ID                ;//[nb_rename_unit][nb_inst_retire]
 //public    : SC_OUT(Tcontext_t         ) *** out_RETIRE_RENAME_UNIT_ID            ;//[nb_rename_unit][nb_inst_retire]
+//public    : SC_OUT(Tdepth_t           ) *** out_RETIRE_DEPTH                     ;//[nb_rename_unit][nb_inst_retire]
   public    : SC_OUT(Tcontrol_t         ) *** out_RETIRE_USE_STORE_QUEUE           ;//[nb_rename_unit][nb_inst_retire]
   public    : SC_OUT(Tcontrol_t         ) *** out_RETIRE_USE_LOAD_QUEUE            ;//[nb_rename_unit][nb_inst_retire]
@@ -234,8 +236,8 @@
   public    : SC_IN (Tcounter_t         ) ***  in_NB_INST_DECOD_ALL                ;//[nb_front_end][nb_context]
 										   
-    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
-  public    : SC_IN (Tdepth_t           ) ***  in_DEPTH_MIN                        ;//[nb_front_end][nb_context]
-  public    : SC_IN (Tdepth_t           ) ***  in_DEPTH_MAX                        ;//[nb_front_end][nb_context]
-  public    : SC_IN (Tcontrol_t         ) ***  in_DEPTH_FULL                       ;//[nb_front_end][nb_context]
+//  // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
+//public    : SC_IN (Tdepth_t           ) ***  in_DEPTH_MIN                        ;//[nb_front_end][nb_context]
+//public    : SC_IN (Tdepth_t           ) ***  in_DEPTH_MAX                        ;//[nb_front_end][nb_context]
+//public    : SC_IN (Tcontrol_t         ) ***  in_DEPTH_FULL                       ;//[nb_front_end][nb_context]
 
     // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -272,4 +274,5 @@
   private   : Tcounter_t                   ** reg_NB_INST_COMMIT_ALL               ;//[nb_front_end][nb_context]
   private   : Tcounter_t                   ** reg_NB_INST_COMMIT_MEM               ;//[nb_front_end][nb_context]
+  private   : Tcounter_t                  *** reg_NB_INST_DEPTH                    ;//[nb_front_end][nb_context][nb_branch_speculated]
 
   private   : Tcommit_event_state_t        ** reg_EVENT_STATE                      ;//[nb_front_end][nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h	(revision 145)
@@ -24,46 +24,49 @@
   {
     //-----[ fields ]------------------------------------------------------------
-  public : uint32_t             _nb_front_end                       ;
-  public : uint32_t           * _nb_context                         ;//[nb_front_end]
-  public : uint32_t             _nb_rename_unit                     ;
-  public : uint32_t             _size_queue                         ;
-  public : uint32_t             _nb_bank                            ;
-  public : Tretire_ooo_scheme_t _retire_ooo_scheme                  ;
-  public : uint32_t           * _nb_inst_insert                     ;//[nb_rename_unit]
-  public : uint32_t           * _nb_inst_retire	                    ;//[nb_rename_unit]
-  public : uint32_t             _nb_inst_commit                     ;
-  public : uint32_t             _nb_inst_reexecute                  ;
-  public : uint32_t             _nb_inst_branch_complete            ;
-  public : uint32_t          ** _nb_branch_speculated               ;//[nb_front_end][nb_context]
-//public : uint32_t             _size_general_data                  ;
-//public : uint32_t             _size_store_queue_ptr               ;
-//public : uint32_t             _size_load_queue_ptr                ;
-//public : uint32_t             _size_general_register              ;
-//public : uint32_t             _size_special_register              ;
-  public : Trat_scheme_t      * _rat_scheme                         ;//[nb_front_end]
-  public : Tpriority_t          _priority                           ;
-  public : Tload_balancing_t    _load_balancing                     ;
-  public : uint32_t             _nb_rename_unit_select              ;
-  public : uint32_t             _nb_thread                          ;
-  public : uint32_t          ** _translate_num_context_to_num_thread;//[nb_front_end][nb_context]
-  public : const uint32_t       _nb_bank_access_commit              ;
+  public : uint32_t               _nb_front_end                       ;
+  public : uint32_t             * _nb_context                         ;//[nb_front_end]
+  public : uint32_t               _nb_rename_unit                     ;
+  public : uint32_t               _size_queue                         ;
+  public : uint32_t               _nb_bank                            ;
+  public : Tretire_ooo_scheme_t   _retire_ooo_scheme                  ;
+  public : uint32_t             * _nb_inst_insert                     ;//[nb_rename_unit]
+  public : uint32_t             * _nb_inst_retire	                    ;//[nb_rename_unit]
+  public : uint32_t               _nb_inst_commit                     ;
+  public : uint32_t               _nb_inst_reexecute                  ;
+  public : uint32_t               _nb_inst_branch_complete            ;
+  public : uint32_t            ** _nb_branch_speculated               ;//[nb_front_end][nb_context]
+//public : uint32_t               _size_general_data                  ;
+//public : uint32_t               _size_store_queue_ptr               ;
+//public : uint32_t               _size_load_queue_ptr                ;
+//public : uint32_t               _size_general_register              ;
+//public : uint32_t               _size_special_register              ;
+  public : Trat_scheme_t        * _rat_scheme                         ;//[nb_rename_unit]
+  public : std::vector<uint32_t>* _link_front_end_with_rename_unit    ;//[nb_rename_unit]
 
-  public : uint32_t             _max_nb_context          ;
-  public : uint32_t             _max_nb_inst_insert      ;
-  public : uint32_t             _max_nb_inst_retire      ;
-//public : uint32_t             _size_address            ;
-//public : uint32_t             _size_front_end_id       ;
-//public : uint32_t             _size_context_id         ;
-  public : uint32_t             _size_rename_unit_id     ;    
-  public : uint32_t             _size_bank               ;
-//public : uint32_t             _size_nb_inst            ;
-//public : uint32_t             _size_packet_id          ;
-  public : uint32_t          ** _array_size_depth        ;//[nb_front_end][nb_context]
-//public : uint32_t             _max_size_depth          ;
-                             
-//public : Tpacket_t            _shift_num_bank          ;
-  public : Tpacket_t            _mask_num_bank           ;
-  public : Tpacket_t            _shift_num_slot          ;
-//public : Tpacket_t            _mask_num_slot           ;
+  public : Tpriority_t            _priority                           ;
+  public : Tload_balancing_t      _load_balancing                     ;
+  public : uint32_t               _nb_rename_unit_select              ;
+  public : uint32_t               _nb_thread                          ;
+  public : uint32_t            ** _translate_num_context_to_num_thread;//[nb_front_end][nb_context]
+  public : Trat_scheme_t        * _front_end_rat_scheme               ;//[nb_front_end]
+  public : const uint32_t         _nb_bank_access_commit              ;
+                               
+  public : uint32_t               _max_nb_context          ;
+  public : uint32_t               _max_nb_inst_insert      ;
+  public : uint32_t               _max_nb_inst_retire      ;
+//public : uint32_t               _size_address            ;
+//public : uint32_t               _size_front_end_id       ;
+//public : uint32_t               _size_context_id         ;
+  public : uint32_t               _size_rename_unit_id     ;    
+  public : uint32_t               _size_bank               ;
+//public : uint32_t               _size_nb_inst            ;
+//public : uint32_t               _size_packet_id          ;
+  public : uint32_t            ** _array_size_depth        ;//[nb_front_end][nb_context]
+//public : uint32_t               _max_size_depth          ;
+                               
+//public : Tpacket_t              _shift_num_bank          ;
+  public : Tpacket_t              _mask_num_bank           ;
+  public : Tpacket_t              _shift_num_slot          ;
+//public : Tpacket_t              _mask_num_slot           ;
                              
                              
@@ -79,29 +82,30 @@
 
     //-----[ methods ]-----------------------------------------------------------
-  public : Parameters  (uint32_t             nb_front_end                       ,
-			uint32_t           * nb_context                         ,//[nb_front_end]
-			uint32_t             nb_rename_unit                     ,
-			uint32_t             size_queue                         ,
-			uint32_t             nb_bank                            ,
-                        Tretire_ooo_scheme_t retire_ooo_scheme                  ,
-			uint32_t           * nb_inst_insert                     ,//[nb_rename_unit]
-			uint32_t           * nb_inst_retire                     ,//[nb_rename_unit]
-			uint32_t             nb_inst_commit                     ,
-			uint32_t             nb_inst_reexecute                  ,
-			uint32_t             nb_inst_branch_complete            ,
-			uint32_t          ** nb_branch_speculated               ,//[nb_front_end][nb_context]
-                        uint32_t             size_nb_inst_decod                 ,
-			uint32_t             size_general_data                  ,
-			uint32_t             size_store_queue_ptr               ,
-			uint32_t             size_load_queue_ptr                ,
-			uint32_t             size_general_register              ,
-			uint32_t             size_special_register              ,
-                        Trat_scheme_t      * rat_scheme                         ,//[nb_front_end]
-			Tpriority_t          priority                           ,
-			Tload_balancing_t    load_balancing                     ,
-			uint32_t             nb_rename_unit_select              ,
-                        uint32_t             nb_thread                          ,
-                        uint32_t          ** translate_num_context_to_num_thread, //[nb_front_end][nb_context]
-                        bool                 is_toplevel=false
+  public : Parameters  (uint32_t               nb_front_end                       ,
+			uint32_t             * nb_context                         ,//[nb_front_end]
+			uint32_t               nb_rename_unit                     ,
+			uint32_t               size_queue                         ,
+			uint32_t               nb_bank                            ,
+                        Tretire_ooo_scheme_t   retire_ooo_scheme                  ,
+			uint32_t             * nb_inst_insert                     ,//[nb_rename_unit]
+			uint32_t             * nb_inst_retire                     ,//[nb_rename_unit]
+			uint32_t               nb_inst_commit                     ,
+			uint32_t               nb_inst_reexecute                  ,
+			uint32_t               nb_inst_branch_complete            ,
+			uint32_t            ** nb_branch_speculated               ,//[nb_front_end][nb_context]
+                        uint32_t               size_nb_inst_decod                 ,
+			uint32_t               size_general_data                  ,
+			uint32_t               size_store_queue_ptr               ,
+			uint32_t               size_load_queue_ptr                ,
+			uint32_t               size_general_register              ,
+			uint32_t               size_special_register              ,
+                        Trat_scheme_t        * rat_scheme                         ,//[nb_rename_unit]
+                        std::vector<uint32_t>* link_front_end_with_rename_unit    ,//[nb_rename_unit]
+                        Tpriority_t            priority                           ,
+			Tload_balancing_t      load_balancing                     ,
+			uint32_t               nb_rename_unit_select              ,
+                        uint32_t               nb_thread                          ,
+                        uint32_t            ** translate_num_context_to_num_thread, //[nb_front_end][nb_context]
+                        bool                   is_toplevel=false
 			);
 //   public : Parameters  (Parameters & param) ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 145)
@@ -81,4 +81,6 @@
   public  : rob_state_t        state                   ;
   public  : rob_state_t        state_old               ;
+//public  : Tcontrol_t         restore                 ;
+
   public  : uint32_t           ptr                     ;
   public  : Tcontext_t         front_end_id            ;
@@ -207,4 +209,20 @@
   };
 
+  template<> inline std::string toString<morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Tcommit_event_state_t>(const morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Tcommit_event_state_t& x)
+  {
+    switch (x)
+      {
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_NO_EVENT      : return "COMMIT_EVENT_STATE_NO_EVENT"     ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_NOT_YET_EVENT : return "COMMIT_EVENT_STATE_NOT_YET_EVENT"; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_EVENT         : return "COMMIT_EVENT_STATE_EVENT"        ; break;
+//    case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_WAIT_DECOD    : return "COMMIT_EVENT_STATE_WAIT_DECOD"   ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_WAIT_END      : return "COMMIT_EVENT_STATE_WAIT_END"     ; break;
+//    case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_END           : return "COMMIT_EVENT_STATE_END"          ; break;
+
+      default    : return ""      ; break;
+      }
+  };
+
+
 }; // end namespace morpheo              
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp	(revision 145)
@@ -115,4 +115,19 @@
 	sensitive << (*(in_CLOCK)).neg() // need internal register
 		  << (*(in_NRESET));
+
+        for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
+          if (_param->_rat_scheme[i] == RAT_DEPTH_SAVE)
+            for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++)
+              {
+                if (_param->_have_port_front_end_id  )
+                sensitive << (*(in_INSERT_FRONT_END_ID [i][j]));
+                if (_param->_have_port_context_id  )
+                sensitive << (*(in_INSERT_CONTEXT_ID   [i][j]));
+                if (_param->_have_port_depth)
+                sensitive << (*(in_INSERT_DEPTH        [i][j]));
+                sensitive << (*(in_INSERT_SAVE_RAT     [i][j]));
+              }
+
+
 // 	for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
 // 	  for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 145)
@@ -59,48 +59,49 @@
       ALLOC2_INTERFACE_BEGIN("insert", IN, SOUTH, _("Interface with rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
 
-      _ALLOC2_VALACK_IN ( in_INSERT_VAL                     ,VAL,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_VALACK_OUT(out_INSERT_ACK                     ,ACK,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_FRONT_END_ID            ,"front_end_id"         ,Tcontext_t        ,_param->_size_front_end_id          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_CONTEXT_ID              ,"context_id"           ,Tcontext_t        ,_param->_size_context_id            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_OUT(out_INSERT_PACKET_ID               ,"packet_id"            ,Tpacket_t         ,_param->_size_rob_ptr               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-//    _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_ID          ,"rename_unit_id"       ,Tcontext_t        ,_param->_size_rename_unit_id        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_DEPTH                   ,"depth"                ,Tdepth_t          ,_param->_size_depth                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#ifdef STATISTICS
-      _ALLOC2_SIGNAL_IN ( in_INSERT_INSTRUCTION             ,"instruction"          ,uint32_t          ,32                                  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#endif
-      _ALLOC2_SIGNAL_IN ( in_INSERT_TYPE                    ,"type"                 ,Ttype_t           ,_param->_size_type                  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_OPERATION               ,"operation"            ,Toperation_t      ,_param->_size_operation             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NO_EXECUTE              ,"no_execute"           ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_LAST_EVENT              ,"last_event"           ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_IS_DELAY_SLOT           ,"is_delay_slot"        ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#ifdef DEBUG
-      _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS                 ,"address"              ,Taddress_t        ,_param->_size_instruction_address   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#endif
-      _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS_NEXT            ,"address_next"         ,Taddress_t        ,_param->_size_instruction_address   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION               ,"exception"            ,Texception_t      ,_param->_size_exception             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION_USE           ,"exception_use"        ,Texception_t      ,_param->_size_exception_use         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_STORE_QUEUE_PTR_WRITE   ,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr       ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_LOAD_QUEUE_PTR_WRITE    ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#ifdef DEBUG
-      _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RA                 ,"read_ra"              ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RA_LOG          ,"num_reg_ra_log"       ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RA_PHY          ,"num_reg_ra_phy"       ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#endif
-      _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RB                 ,"read_rb"              ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#ifdef DEBUG
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RB_LOG          ,"num_reg_rb_log"       ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RB_PHY          ,"num_reg_rb_phy"       ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RC                 ,"read_rc"              ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RC_LOG          ,"num_reg_rc_log"       ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RC_PHY          ,"num_reg_rc_phy"       ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-#endif
-      _ALLOC2_SIGNAL_IN ( in_INSERT_WRITE_RD                ,"write_rd"             ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_LOG          ,"num_reg_rd_log"       ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY_OLD      ,"num_reg_rd_phy_old"   ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY_NEW      ,"num_reg_rd_phy_new"   ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_WRITE_RE                ,"write_re"             ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_LOG          ,"num_reg_re_log"       ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_OLD      ,"num_reg_re_phy_old"   ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
-      _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_NEW      ,"num_reg_re_phy_new"   ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_VALACK_IN      ( in_INSERT_VAL                     ,VAL,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_VALACK_OUT     (out_INSERT_ACK                     ,ACK,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_FRONT_END_ID            ,"front_end_id"         ,Tcontext_t        ,_param->_size_front_end_id          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_CONTEXT_ID              ,"context_id"           ,Tcontext_t        ,_param->_size_context_id            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_OUT     (out_INSERT_PACKET_ID               ,"packet_id"            ,Tpacket_t         ,_param->_size_rob_ptr               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+//    _ALLOC2_SIGNAL_IN      ( in_INSERT_RENAME_UNIT_ID          ,"rename_unit_id"       ,Tcontext_t        ,_param->_size_rename_unit_id        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_DEPTH                   ,"depth"                ,Tdepth_t          ,_param->_size_depth                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN_COND ( in_INSERT_SAVE_RAT                ,"save_rat"             ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
+#ifdef STATISTICS            
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_INSTRUCTION             ,"instruction"          ,uint32_t          ,32                                  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#endif                       
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_TYPE                    ,"type"                 ,Ttype_t           ,_param->_size_type                  ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_OPERATION               ,"operation"            ,Toperation_t      ,_param->_size_operation             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NO_EXECUTE              ,"no_execute"           ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_LAST_EVENT              ,"last_event"           ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_IS_DELAY_SLOT           ,"is_delay_slot"        ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#ifdef DEBUG                 
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_ADDRESS                 ,"address"              ,Taddress_t        ,_param->_size_instruction_address   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#endif                       
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_ADDRESS_NEXT            ,"address_next"         ,Taddress_t        ,_param->_size_instruction_address   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_EXCEPTION               ,"exception"            ,Texception_t      ,_param->_size_exception             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_EXCEPTION_USE           ,"exception_use"        ,Texception_t      ,_param->_size_exception_use         ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_STORE_QUEUE_PTR_WRITE   ,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr       ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_LOAD_QUEUE_PTR_WRITE    ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr        ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#ifdef DEBUG                 
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_READ_RA                 ,"read_ra"              ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RA_LOG          ,"num_reg_ra_log"       ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RA_PHY          ,"num_reg_ra_phy"       ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#endif                       
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_READ_RB                 ,"read_rb"              ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#ifdef DEBUG                 
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RB_LOG          ,"num_reg_rb_log"       ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RB_PHY          ,"num_reg_rb_phy"       ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_READ_RC                 ,"read_rc"              ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RC_LOG          ,"num_reg_rc_log"       ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RC_PHY          ,"num_reg_rc_phy"       ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+#endif                       
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_WRITE_RD                ,"write_rd"             ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RD_LOG          ,"num_reg_rd_log"       ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RD_PHY_OLD      ,"num_reg_rd_phy_old"   ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RD_PHY_NEW      ,"num_reg_rd_phy_new"   ,Tgeneral_address_t,_param->_size_general_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_WRITE_RE                ,"write_re"             ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RE_LOG          ,"num_reg_re_log"       ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RE_PHY_OLD      ,"num_reg_re_phy_old"   ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN      ( in_INSERT_NUM_REG_RE_PHY_NEW      ,"num_reg_re_phy_new"   ,Tspecial_address_t,_param->_size_special_register      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
 
       ALLOC2_INTERFACE_END(_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
@@ -116,4 +117,5 @@
       _ALLOC2_SIGNAL_OUT(out_RETIRE_CONTEXT_ID              ,"context_id"           ,Tcontext_t        ,_param->_size_context_id            ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);    
 //    _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_ID          ,"rename_unit_id"       ,Tcontext_t        ,_param->_size_rename_unit_id        ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
+//    _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_DEPTH              ,"depth"                ,Tdepth_t          ,_param->_size_depth                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
       _ALLOC2_SIGNAL_OUT(out_RETIRE_USE_STORE_QUEUE         ,"use_store_queue"      ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
       _ALLOC2_SIGNAL_OUT(out_RETIRE_USE_LOAD_QUEUE          ,"use_load_queue"       ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);
@@ -150,6 +152,6 @@
 //    _ALLOC2_SIGNAL_OUT     (out_RETIRE_EVENT_FLUSH ,"flush"      ,Tcontrol_t        ,1                        ,_param->_nb_front_end,_param->_nb_context[it1]);
       _ALLOC2_SIGNAL_OUT     (out_RETIRE_EVENT_STOP  ,"stop"       ,Tcontrol_t        ,1                        ,_param->_nb_front_end,_param->_nb_context[it1]);
-      _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_EVENT_TYPE  ,"type"       ,Tevent_type_t     ,_param->_size_event_type ,_param->_nb_front_end,_param->_nb_context[it1],_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
-      _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_EVENT_DEPTH ,"depth"      ,Tdepth_t          ,_param->_size_depth      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
+      _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_EVENT_TYPE  ,"type"       ,Tevent_type_t     ,_param->_size_event_type ,_param->_nb_front_end,_param->_nb_context[it1],_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE);
+      _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_EVENT_DEPTH ,"depth"      ,Tdepth_t          ,_param->_size_depth      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE);
 
       ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]);
@@ -255,14 +257,14 @@
     }
 
-    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-    {
-      ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);
-
-      _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN                     ,"min"      ,Tdepth_t           ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]);
-      _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX                     ,"max"      ,Tdepth_t           ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]);
-      _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL                    ,"full"     ,Tcontrol_t         ,1                  ,_param->_nb_front_end, _param->_nb_context[it1]);
-
-      ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
-    }
+//  // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+//  {
+//    ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);
+//
+//    _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN                     ,"min"      ,Tdepth_t           ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]);
+//    _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX                     ,"max"      ,Tdepth_t           ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]);
+//    _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL                    ,"full"     ,Tcontrol_t         ,1                  ,_param->_nb_front_end, _param->_nb_context[it1]);
+//
+//    ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
+//  }
 
 
@@ -332,37 +334,39 @@
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-    ALLOC2(_nb_cycle_idle           ,double               ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC1(_rob                     ,std::list<entry_t*>  ,_param->_nb_bank);
+    ALLOC2     (_nb_cycle_idle           ,double               ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC1     (_rob                     ,std::list<entry_t*>  ,_param->_nb_bank);
+               
+    ALLOC1     (reg_BANK_PTR             ,uint32_t             ,_param->_nb_bank);
+                                                          
+    ALLOC2     (reg_NB_INST_COMMIT_ALL   ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_NB_INST_COMMIT_MEM   ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC3_COND(reg_NB_INST_DEPTH        ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_branch_speculated[it1][it2],_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE);
+    ALLOC2     (reg_EVENT_STATE          ,Tcommit_event_state_t,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_TYPE           ,Tevent_type_t        ,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2     (reg_EVENT_FLUSH          ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2     (reg_EVENT_STOP           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2     (reg_EVENT_NUM_BANK       ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2     (reg_EVENT_NUM_PTR        ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2     (reg_EVENT_CAN_RESTART    ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_PACKET         ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_DEPTH          ,Tdepth_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_NB_INST        ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_LAST           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_LAST_NUM_BANK  ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_LAST_NUM_PTR   ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+               
+    ALLOC2     (reg_EVENT_NEXT_STOP      ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_EVENT_NEXT_PACKET    ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+                                                               
+//  ALLOC2     (reg_PC_PREVIOUS          ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_PC_CURRENT           ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_PC_CURRENT_IS_DS     ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_PC_CURRENT_IS_DS_TAKE,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2     (reg_PC_NEXT              ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
+               
+    ALLOC3     (rat_gpr_update_table     ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_general_register_logic);
+    ALLOC3     (rat_spr_update_table     ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_special_register_logic);
+
     
-    ALLOC1(reg_BANK_PTR             ,uint32_t             ,_param->_nb_bank);
-                                                          
-    ALLOC2(reg_NB_INST_COMMIT_ALL   ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_NB_INST_COMMIT_MEM   ,Tcounter_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-    
-    ALLOC2(reg_EVENT_STATE          ,Tcommit_event_state_t,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_TYPE           ,Tevent_type_t        ,_param->_nb_front_end,_param->_nb_context [it1]);
-//  ALLOC2(reg_EVENT_FLUSH          ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
-//  ALLOC2(reg_EVENT_STOP           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
-//  ALLOC2(reg_EVENT_NUM_BANK       ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-//  ALLOC2(reg_EVENT_NUM_PTR        ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-//  ALLOC2(reg_EVENT_CAN_RESTART    ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_PACKET         ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_DEPTH          ,Tdepth_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_NB_INST        ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_LAST           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_LAST_NUM_BANK  ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_LAST_NUM_PTR   ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-    ALLOC2(reg_EVENT_NEXT_STOP      ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_EVENT_NEXT_PACKET    ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
-                                                          
-//  ALLOC2(reg_PC_PREVIOUS          ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_CURRENT           ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_CURRENT_IS_DS     ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_CURRENT_IS_DS_TAKE,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-    ALLOC2(reg_PC_NEXT              ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-    ALLOC3(rat_gpr_update_table     ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_general_register_logic);
-    ALLOC3(rat_spr_update_table     ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_special_register_logic);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 145)
@@ -28,48 +28,49 @@
 	delete    in_NRESET;
 
-        DELETE2_SIGNAL( in_INSERT_VAL                     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL(out_INSERT_ACK                     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_FRONT_END_ID            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_front_end_id          );
-        DELETE2_SIGNAL( in_INSERT_CONTEXT_ID              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_context_id            );
-        DELETE2_SIGNAL(out_INSERT_PACKET_ID               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rob_ptr               );
-//      DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_ID          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rename_unit_id        );
-        DELETE2_SIGNAL( in_INSERT_DEPTH                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_depth                 );
-#ifdef STATISTICS
-        DELETE2_SIGNAL( in_INSERT_INSTRUCTION             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],32);
-#endif
-        DELETE2_SIGNAL( in_INSERT_TYPE                    ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type                  );
-        DELETE2_SIGNAL( in_INSERT_OPERATION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_operation             );
-        DELETE2_SIGNAL( in_INSERT_NO_EXECUTE              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_LAST_EVENT              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_IS_DELAY_SLOT           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-#ifdef DEBUG
-        DELETE2_SIGNAL( in_INSERT_ADDRESS                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address               );
-#endif
-        DELETE2_SIGNAL( in_INSERT_ADDRESS_NEXT            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address               );
-        DELETE2_SIGNAL( in_INSERT_EXCEPTION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception             );
-        DELETE2_SIGNAL( in_INSERT_EXCEPTION_USE           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception             );
-        DELETE2_SIGNAL( in_INSERT_STORE_QUEUE_PTR_WRITE   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr       );
-        DELETE2_SIGNAL( in_INSERT_LOAD_QUEUE_PTR_WRITE    ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr        );
-#ifdef DEBUG
-        DELETE2_SIGNAL( in_INSERT_READ_RA                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RA_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic);
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RA_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
-#endif
-        DELETE2_SIGNAL( in_INSERT_READ_RB                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-#ifdef DEBUG
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RB_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic);
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RB_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
-        DELETE2_SIGNAL( in_INSERT_READ_RC                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RC_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic);
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RC_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register      );
-#endif
-        DELETE2_SIGNAL( in_INSERT_WRITE_RD                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RD_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic);
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RD_PHY_OLD      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RD_PHY_NEW      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
-        DELETE2_SIGNAL( in_INSERT_WRITE_RE                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RE_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic);
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RE_PHY_OLD      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register      );
-        DELETE2_SIGNAL( in_INSERT_NUM_REG_RE_PHY_NEW      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register      );
+        DELETE2_SIGNAL     ( in_INSERT_VAL                     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     (out_INSERT_ACK                     ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_FRONT_END_ID            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_front_end_id          );
+        DELETE2_SIGNAL     ( in_INSERT_CONTEXT_ID              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_context_id            );
+        DELETE2_SIGNAL     (out_INSERT_PACKET_ID               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rob_ptr               );
+//      DELETE2_SIGNAL     ( in_INSERT_RENAME_UNIT_ID          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rename_unit_id        );
+        DELETE2_SIGNAL     ( in_INSERT_DEPTH                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_depth                 );
+        DELETE2_SIGNAL_COND( in_INSERT_SAVE_RAT                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   ,_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
+#ifdef STATISTICS          
+        DELETE2_SIGNAL     ( in_INSERT_INSTRUCTION             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],32);
+#endif                     
+        DELETE2_SIGNAL     ( in_INSERT_TYPE                    ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type                  );
+        DELETE2_SIGNAL     ( in_INSERT_OPERATION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_operation             );
+        DELETE2_SIGNAL     ( in_INSERT_NO_EXECUTE              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_LAST_EVENT              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_IS_DELAY_SLOT           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+#ifdef DEBUG               
+        DELETE2_SIGNAL     ( in_INSERT_ADDRESS                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address   );
+#endif                     
+        DELETE2_SIGNAL     ( in_INSERT_ADDRESS_NEXT            ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address   );
+        DELETE2_SIGNAL     ( in_INSERT_EXCEPTION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception             );
+        DELETE2_SIGNAL     ( in_INSERT_EXCEPTION_USE           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception             );
+        DELETE2_SIGNAL     ( in_INSERT_STORE_QUEUE_PTR_WRITE   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr       );
+        DELETE2_SIGNAL     ( in_INSERT_LOAD_QUEUE_PTR_WRITE    ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr        );
+#ifdef DEBUG               
+        DELETE2_SIGNAL     ( in_INSERT_READ_RA                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RA_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic);
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RA_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
+#endif                     
+        DELETE2_SIGNAL     ( in_INSERT_READ_RB                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+#ifdef DEBUG               
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RB_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic);
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RB_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
+        DELETE2_SIGNAL     ( in_INSERT_READ_RC                 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RC_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic);
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RC_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register      );
+#endif                     
+        DELETE2_SIGNAL     ( in_INSERT_WRITE_RD                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RD_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic);
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RD_PHY_OLD      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RD_PHY_NEW      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register      );
+        DELETE2_SIGNAL     ( in_INSERT_WRITE_RE                ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RE_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic);
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RE_PHY_OLD      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register      );
+        DELETE2_SIGNAL     ( in_INSERT_NUM_REG_RE_PHY_NEW      ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register      );
 
         DELETE2_SIGNAL(out_RETIRE_VAL                     ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
@@ -78,14 +79,15 @@
         DELETE2_SIGNAL(out_RETIRE_CONTEXT_ID              ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_context_id            );    
 //      DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_ID          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_rename_unit_id        );
+//      DELETE2_SIGNAL_COND(out_RETIRE_DEPTH              ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_depth                 ,_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
         DELETE2_SIGNAL(out_RETIRE_USE_STORE_QUEUE         ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
         DELETE2_SIGNAL(out_RETIRE_USE_LOAD_QUEUE          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
         DELETE2_SIGNAL(out_RETIRE_STORE_QUEUE_PTR_WRITE   ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_store_queue_ptr       );
         DELETE2_SIGNAL(out_RETIRE_LOAD_QUEUE_PTR_WRITE    ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_load_queue_ptr        );
-//         DELETE2_SIGNAL(out_RETIRE_READ_RA                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
-//         DELETE2_SIGNAL(out_RETIRE_NUM_REG_RA_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register      );
-//         DELETE2_SIGNAL(out_RETIRE_READ_RB                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
-//         DELETE2_SIGNAL(out_RETIRE_NUM_REG_RB_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register      );
-//         DELETE2_SIGNAL(out_RETIRE_READ_RC                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
-//         DELETE2_SIGNAL(out_RETIRE_NUM_REG_RC_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register      );
+//      DELETE2_SIGNAL(out_RETIRE_READ_RA                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
+//      DELETE2_SIGNAL(out_RETIRE_NUM_REG_RA_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register      );
+//      DELETE2_SIGNAL(out_RETIRE_READ_RB                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
+//      DELETE2_SIGNAL(out_RETIRE_NUM_REG_RB_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register      );
+//      DELETE2_SIGNAL(out_RETIRE_READ_RC                 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
+//      DELETE2_SIGNAL(out_RETIRE_NUM_REG_RC_PHY          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register      );
         DELETE2_SIGNAL(out_RETIRE_WRITE_RD                ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1                                   );
         DELETE2_SIGNAL(out_RETIRE_NUM_REG_RD_LOG          ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register_logic);
@@ -105,6 +107,6 @@
 //      DELETE2_SIGNAL     (out_RETIRE_EVENT_FLUSH             ,_param->_nb_front_end,_param->_nb_context[it1],1);
         DELETE2_SIGNAL     (out_RETIRE_EVENT_STOP              ,_param->_nb_front_end,_param->_nb_context[it1],1);
-        DELETE2_SIGNAL_COND(out_RETIRE_EVENT_TYPE              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_event_type,_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
-        DELETE2_SIGNAL_COND(out_RETIRE_EVENT_DEPTH             ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth     ,_param->_rat_scheme[it1] == RAT_DEPTH_SAVE);
+        DELETE2_SIGNAL_COND(out_RETIRE_EVENT_TYPE              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_event_type,_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE);
+        DELETE2_SIGNAL_COND(out_RETIRE_EVENT_DEPTH             ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth     ,_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE);
 
         DELETE1_SIGNAL( in_COMMIT_VAL               ,_param->_nb_inst_commit,1                             );
@@ -164,7 +166,7 @@
         DELETE2_SIGNAL( in_NB_INST_DECOD_ALL              ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_decod);
 
-        DELETE2_SIGNAL( in_DEPTH_MIN                      ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth);
-        DELETE2_SIGNAL( in_DEPTH_MAX                      ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth);
-        DELETE2_SIGNAL( in_DEPTH_FULL                     ,_param->_nb_front_end, _param->_nb_context[it1],1);
+//      DELETE2_SIGNAL( in_DEPTH_MIN                      ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth);
+//      DELETE2_SIGNAL( in_DEPTH_MAX                      ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth);
+//      DELETE2_SIGNAL( in_DEPTH_FULL                     ,_param->_nb_front_end, _param->_nb_context[it1],1);
 
 	DELETE2_SIGNAL( in_SPR_READ_SR_OVE                ,_param->_nb_front_end, _param->_nb_context[it1],1);
@@ -221,35 +223,36 @@
 	    }
 
-        DELETE2(_nb_cycle_idle           ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE1(_rob                     ,_param->_nb_bank);
-        DELETE1(reg_BANK_PTR             ,_param->_nb_bank);
-        DELETE2(reg_NB_INST_COMMIT_ALL   ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_NB_INST_COMMIT_MEM   ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-        DELETE2(reg_EVENT_STATE          ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_TYPE           ,_param->_nb_front_end,_param->_nb_context [it1]);
-//      DELETE2(reg_EVENT_FLUSH          ,_param->_nb_front_end,_param->_nb_context [it1]);
-//      DELETE2(reg_EVENT_STOP           ,_param->_nb_front_end,_param->_nb_context [it1]);
-//      DELETE2(reg_EVENT_NUM_BANK       ,_param->_nb_front_end,_param->_nb_context [it1]);
-//      DELETE2(reg_EVENT_NUM_PTR        ,_param->_nb_front_end,_param->_nb_context [it1]);
-//      DELETE2(reg_EVENT_CAN_RESTART    ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_PACKET         ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_DEPTH          ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_NB_INST        ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_LAST           ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_LAST_NUM_BANK  ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_LAST_NUM_PTR   ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-        DELETE2(reg_EVENT_NEXT_STOP      ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_EVENT_NEXT_PACKET    ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-//      DELETE2(reg_PC_PREVIOUS          ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_PC_CURRENT           ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_PC_CURRENT_IS_DS     ,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_PC_CURRENT_IS_DS_TAKE,_param->_nb_front_end,_param->_nb_context [it1]);
-        DELETE2(reg_PC_NEXT              ,_param->_nb_front_end,_param->_nb_context [it1]);
-
-        DELETE3(rat_gpr_update_table     ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_general_register_logic);
-        DELETE3(rat_spr_update_table     ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_special_register_logic);
+        DELETE2     (_nb_cycle_idle           ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE1     (_rob                     ,_param->_nb_bank);
+        DELETE1     (reg_BANK_PTR             ,_param->_nb_bank);
+        DELETE2     (reg_NB_INST_COMMIT_ALL   ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_NB_INST_COMMIT_MEM   ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE3_COND(reg_NB_INST_DEPTH        ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_branch_speculated[it1][it2],_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE);
+
+        DELETE2     (reg_EVENT_STATE          ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_TYPE           ,_param->_nb_front_end,_param->_nb_context [it1]);
+//      DELETE2     (reg_EVENT_FLUSH          ,_param->_nb_front_end,_param->_nb_context [it1]);
+//      DELETE2     (reg_EVENT_STOP           ,_param->_nb_front_end,_param->_nb_context [it1]);
+//      DELETE2     (reg_EVENT_NUM_BANK       ,_param->_nb_front_end,_param->_nb_context [it1]);
+//      DELETE2     (reg_EVENT_NUM_PTR        ,_param->_nb_front_end,_param->_nb_context [it1]);
+//      DELETE2     (reg_EVENT_CAN_RESTART    ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_PACKET         ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_DEPTH          ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_NB_INST        ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_LAST           ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_LAST_NUM_BANK  ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_LAST_NUM_PTR   ,_param->_nb_front_end,_param->_nb_context [it1]);
+                    
+        DELETE2     (reg_EVENT_NEXT_STOP      ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_EVENT_NEXT_PACKET    ,_param->_nb_front_end,_param->_nb_context [it1]);
+                    
+//      DELETE2     (reg_PC_PREVIOUS          ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_PC_CURRENT           ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_PC_CURRENT_IS_DS     ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_PC_CURRENT_IS_DS_TAKE,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2     (reg_PC_NEXT              ,_param->_nb_front_end,_param->_nb_context [it1]);
+                    
+        DELETE3     (rat_gpr_update_table     ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_general_register_logic);
+        DELETE3     (rat_spr_update_table     ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_special_register_logic);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 145)
@@ -101,20 +101,42 @@
                     if (not bank_full [num_bank])
                       {
-                        // find !!!
-                        insert_ack       [num_rename_unit][num_inst_insert] = true;
+                        bool cond = true;
+
+                        if (_param->_rat_scheme[num_rename_unit] == RAT_DEPTH_SAVE)
+                          {
+                            Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [num_rename_unit][num_inst_insert]):0;
+                            Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_INSERT_CONTEXT_ID   [num_rename_unit][num_inst_insert]):0;
+                            Tdepth_t   depth        = (_param->_have_port_depth       )?PORT_READ(in_INSERT_DEPTH        [num_rename_unit][num_inst_insert]):0;
+                            Tcontrol_t save_rat     =                                   PORT_READ(in_INSERT_SAVE_RAT     [num_rename_unit][num_inst_insert]);
+
+                            cond = not (save_rat and (reg_NB_INST_DEPTH[front_end_id][context_id][depth]>0));
+
+                            log_printf(TRACE,Commit_unit,FUNCTION,"        * front_end_id : %d",front_end_id);
+                            log_printf(TRACE,Commit_unit,FUNCTION,"        * context_id   : %d",context_id  );
+                            log_printf(TRACE,Commit_unit,FUNCTION,"        * depth        : %d",depth       );
+                            log_printf(TRACE,Commit_unit,FUNCTION,"        * save_rat     : %d",save_rat    );
+                            log_printf(TRACE,Commit_unit,FUNCTION,"        * cond         : %d",cond        );
+                            
+                          }
                         
-                        Tpacket_t packet_id = ((reg_BANK_PTR [num_bank] << _param->_shift_num_slot) | num_bank);
-                        
+                        if (cond)
+                          {
+                            // find !!!
+                            insert_ack       [num_rename_unit][num_inst_insert] = true;
+                            
+                            Tpacket_t packet_id = ((reg_BANK_PTR [num_bank] << _param->_shift_num_slot) | num_bank);
+                            
 #ifdef SYSTEMC_VHDL_COMPATIBILITY
-                        insert_packet_id [num_rename_unit][num_inst_insert] = packet_id;
+                            insert_packet_id [num_rename_unit][num_inst_insert] = packet_id;
 #else
-                        if (_param->_have_port_rob_ptr  )
-                        PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id);
+                            if (_param->_have_port_rob_ptr  )
+                              PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id);
 #endif
-                        internal_BANK_INSERT_VAL             [num_bank] = true;
-                        internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit;
-                        internal_BANK_INSERT_NUM_INST        [num_bank] = num_inst_insert;
-                        
-                        break;
+                            internal_BANK_INSERT_VAL             [num_bank] = true;
+                            internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit;
+                            internal_BANK_INSERT_NUM_INST        [num_bank] = num_inst_insert;
+                            
+                            break;
+                          }
                       }
                   }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 145)
@@ -225,4 +225,6 @@
                         PORT_WRITE(out_RETIRE_CONTEXT_ID            [x][y], context_id                  );
 // 		        PORT_WRITE(out_RETIRE_RENAME_UNIT_ID        [x][y], entry->rename_unit_id       );
+//                      if (_param->_have_port_depth and (_param->_rat_scheme[x] == RAT_DEPTH_SAVE))
+//                      PORT_WRITE(out_RETIRE_DEPTH                 [x][y], entry->depth                );
                         PORT_WRITE(out_RETIRE_USE_STORE_QUEUE       [x][y], entry->use_store_queue      );
                         PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE        [x][y], entry->use_load_queue       );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 145)
@@ -331,5 +331,5 @@
           PORT_WRITE(out_RETIRE_EVENT_STOP  [i][j], ((reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_NOT_YET_EVENT) or
                                                      reg_EVENT_NEXT_STOP [i][j]));
-          if (_param->_rat_scheme[i] == RAT_DEPTH_SAVE)
+          if (_param->_front_end_rat_scheme[i] == RAT_DEPTH_SAVE)
             {
           PORT_WRITE(out_RETIRE_EVENT_TYPE  [i][j], reg_EVENT_TYPE  [i][j]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp	(revision 145)
@@ -48,4 +48,6 @@
     uint32_t mask_operation = gen_mask<uint32_t>(SIZE_OPERATION  );
 
+    msgInformation("Number of iteration couple of instructions.\n");
+
     for (uint32_t i=0; i<_param->_nb_thread; ++i)
       for(stat_inst_fusion_t::iterator it = _stat_inst_fusion [i].begin();
@@ -64,15 +66,14 @@
               uint32_t operation_1 =                      inst                               &mask_operation ;
 
-              // log_printf(STAT,Commit_unit,FUNCTION,
               msgInformation(
                            //"  * %s - %s : %d\n"
                            //,toString_instruction((inst>>SIZE_INSTRUCTION)&mask_inst).c_str()
                            //,toString_instruction( inst                   &mask_inst).c_str(),value
-                             "  * %s.%s - %s.%s : %d\n"
+                             "  * (%d) \t%s.%s - %s.%s\n"
+                             ,value
                              ,toString          (type_0            ).c_str()
                              ,toString_operation(type_0,operation_0).c_str()
                              ,toString          (type_1            ).c_str()
                              ,toString_operation(type_1,operation_1).c_str()
-                             ,value
                              );
             }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 145)
@@ -48,7 +48,4 @@
               _nb_cycle_idle            [i][j] = 0;
 
-	      reg_NB_INST_COMMIT_ALL    [i][j] = 0;
-	      reg_NB_INST_COMMIT_MEM    [i][j] = 0;
-                                        
               reg_EVENT_STATE           [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
 //            reg_EVENT_FLUSH           [i][j] = false;
@@ -72,4 +69,11 @@
               reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0;
               reg_PC_NEXT               [i][j] = (0x100+4)>>2;
+
+	      reg_NB_INST_COMMIT_ALL    [i][j] = 0;
+	      reg_NB_INST_COMMIT_MEM    [i][j] = 0;
+                          
+              if (_param->_front_end_rat_scheme[i] == RAT_DEPTH_SAVE)
+                for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+                  reg_NB_INST_DEPTH [i][j][k] = 0;
 	    }
 
@@ -281,4 +285,5 @@
                       uint32_t  ptr   = reg_BANK_PTR [num_bank];
 
+	              // entry->restore                 = false;
 	              entry->ptr                     = ptr;
 	              entry->front_end_id            = front_end_id;
@@ -353,5 +358,5 @@
                               {
                               case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END  ; break;}
-                              case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store  ==1)?ROB_STORE_WAIT_END_OK:ROB_OTHER_WAIT_END); break;}
+                              case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store==1)?ROB_STORE_WAIT_END_OK:ROB_OTHER_WAIT_END); break;}
                               default          : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
                               }
@@ -378,5 +383,7 @@
                       if (type == TYPE_MEMORY)
                         reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++;
-                      
+
+                      if (_param->_front_end_rat_scheme[front_end_id] == RAT_DEPTH_SAVE)
+                      reg_NB_INST_DEPTH [front_end_id][context_id][entry->depth] ++;
 
                       // flush = present event or future event.
@@ -856,5 +863,6 @@
                     if (type == TYPE_MEMORY)
                     reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
-	            
+                    if (_param->_front_end_rat_scheme[front_end_id] == RAT_DEPTH_SAVE)
+	            reg_NB_INST_DEPTH      [front_end_id][context_id][entry->depth] --;
 	            // Update pointer
 	            reg_NUM_BANK_HEAD = (num_bank+1)%_param->_nb_bank;
@@ -1191,22 +1199,22 @@
                           switch (state)
                             {
-                            case ROB_BRANCH_WAIT_END             : {state = ROB_EVENT_WAIT_END; break;}
-                            case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS      ; break;}
+                            case ROB_BRANCH_WAIT_END             : {state = ROB_EVENT_WAIT_END   ; break;}
+                            case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS         ; break;}
                             case ROB_END_BRANCH_MISS             :
-                            case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS         ; break;}
                             case ROB_END_LOAD_MISS               :
                             case ROB_END_LOAD_MISS_UPDATE        :
-                            case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_MISS      ; break;}
-                            case ROB_STORE_OK                    : {state = ROB_STORE_KO      ; break;}
+                            case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_MISS         ; break;}
+                            case ROB_STORE_OK                    : {state = ROB_STORE_KO         ; break;}
                             case ROB_STORE_WAIT_END_OK           : {state = ROB_STORE_WAIT_END_KO; break;}
 			    case ROB_STORE_OK_WAIT_END           : {state = ROB_STORE_KO_WAIT_END; break;}
-                            case ROB_OTHER_WAIT_END              : {state = ROB_EVENT_WAIT_END; break;}
+                            case ROB_OTHER_WAIT_END              : {state = ROB_EVENT_WAIT_END   ; break;}
                             case ROB_END_OK                      :
-                            case ROB_END_OK_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_OK_SPECULATIVE          : {state = ROB_END_MISS         ; break;}
                             case ROB_END_KO                      :
-                            case ROB_END_KO_SPECULATIVE          : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_KO_SPECULATIVE          : {state = ROB_END_MISS         ; break;}
                             case ROB_END_EXCEPTION_UPDATE        :
                             case ROB_END_EXCEPTION               :
-                            case ROB_END_EXCEPTION_WAIT_HEAD     : {state = ROB_END_MISS      ; break;}
+                            case ROB_END_EXCEPTION_WAIT_HEAD     : {state = ROB_END_MISS         ; break;}
                               
                               // don't change state -> wait
@@ -1348,5 +1356,6 @@
 //          log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT             : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]);
 //          log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]);
-            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_DEPTH       : %d - type %s",reg_EVENT_DEPTH [i][j],toString(reg_EVENT_TYPE [i][j]).c_str());
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_DEPTH       : %d",reg_EVENT_DEPTH [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_TYPE        : %s",toString(reg_EVENT_TYPE [i][j]).c_str());
             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_LAST        : %d - packet %d - ptr %d (bank %d, ptr %d)",reg_EVENT_LAST [i][j],reg_EVENT_PACKET[i][j],((reg_EVENT_LAST_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [i][j]), reg_EVENT_LAST_NUM_BANK [i][j],reg_EVENT_LAST_NUM_PTR [i][j]);
             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_NEXT        : stop : %d - packet : %d",reg_EVENT_NEXT_STOP  [i][j],reg_EVENT_NEXT_PACKET[i][j]);
@@ -1436,5 +1445,5 @@
         }
 
-      log_printf(TRACE,Commit_unit,FUNCTION,"  * Dump RAT Update Table");
+      log_printf(TRACE,Commit_unit,FUNCTION,"  * Dump RAT_Update Table");
       for (uint32_t i=0; i<_param->_nb_front_end; ++i)
         for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp	(revision 145)
@@ -21,29 +21,30 @@
 #undef  FUNCTION
 #define FUNCTION "Commit_unit::Parameters"
-  Parameters::Parameters (uint32_t             nb_front_end                       ,
-			  uint32_t           * nb_context                         ,//[nb_front_end]            
-			  uint32_t             nb_rename_unit                     ,                            
-			  uint32_t             size_queue                         ,                            
-			  uint32_t             nb_bank                            ,                            
-                          Tretire_ooo_scheme_t retire_ooo_scheme                  ,                            
-			  uint32_t           * nb_inst_insert                     ,//[nb_rename_unit]          
-			  uint32_t           * nb_inst_retire                     ,//[nb_rename_unit]
-			  uint32_t             nb_inst_commit                     ,                            
-			  uint32_t             nb_inst_reexecute                  ,                            
-			  uint32_t             nb_inst_branch_complete            ,                            
-			  uint32_t          ** nb_branch_speculated               ,//[nb_front_end][nb_context]
-                          uint32_t             size_nb_inst_decod                 ,
-			  uint32_t             size_general_data                  ,
-			  uint32_t             size_store_queue_ptr               ,
-			  uint32_t             size_load_queue_ptr                ,
-			  uint32_t             size_general_register              ,
-			  uint32_t             size_special_register              ,
-			  Trat_scheme_t      * rat_scheme                         ,//[nb_front_end]
-			  Tpriority_t          priority                           ,
-			  Tload_balancing_t    load_balancing                     ,
-			  uint32_t             nb_rename_unit_select              ,
-                          uint32_t             nb_thread                          ,
-                          uint32_t          ** translate_num_context_to_num_thread,//[nb_front_end][nb_context]
-                          bool                 is_toplevel):
+  Parameters::Parameters (uint32_t               nb_front_end                       ,
+			  uint32_t             * nb_context                         ,//[nb_front_end]            
+			  uint32_t               nb_rename_unit                     ,                            
+			  uint32_t               size_queue                         ,                            
+			  uint32_t               nb_bank                            ,                            
+                          Tretire_ooo_scheme_t   retire_ooo_scheme                  ,                            
+			  uint32_t             * nb_inst_insert                     ,//[nb_rename_unit]          
+			  uint32_t             * nb_inst_retire                     ,//[nb_rename_unit]
+			  uint32_t               nb_inst_commit                     ,                            
+			  uint32_t               nb_inst_reexecute                  ,                            
+			  uint32_t               nb_inst_branch_complete            ,                            
+			  uint32_t            ** nb_branch_speculated               ,//[nb_front_end][nb_context]
+                          uint32_t               size_nb_inst_decod                 ,
+			  uint32_t               size_general_data                  ,
+			  uint32_t               size_store_queue_ptr               ,
+			  uint32_t               size_load_queue_ptr                ,
+			  uint32_t               size_general_register              ,
+			  uint32_t               size_special_register              ,
+			  Trat_scheme_t        * rat_scheme                         ,//[nb_rename_unit]
+                          std::vector<uint32_t>* link_front_end_with_rename_unit    ,//[nb_rename_unit]
+			  Tpriority_t            priority                           ,
+			  Tload_balancing_t      load_balancing                     ,
+			  uint32_t               nb_rename_unit_select              ,
+                          uint32_t               nb_thread                          ,
+                          uint32_t            ** translate_num_context_to_num_thread,//[nb_front_end][nb_context]
+                          bool                   is_toplevel):
     _nb_bank_access_commit (1              )
   {
@@ -63,4 +64,5 @@
     _nb_branch_speculated                = nb_branch_speculated               ;
     _rat_scheme                          = rat_scheme                         ;
+    _link_front_end_with_rename_unit     = link_front_end_with_rename_unit    ;
     _priority                            = priority                           ;
     _load_balancing                      = load_balancing                     ;
@@ -81,4 +83,12 @@
 
     _have_port_rename_unit_id = _size_rename_unit_id > 0;
+
+    ALLOC1(_front_end_rat_scheme, Trat_scheme_t,_nb_front_end);
+    // one rename unit per front_end
+    for (uint32_t i=0; i<_nb_rename_unit; ++i)
+      for (std::vector<uint32_t>::iterator it=_link_front_end_with_rename_unit[i].begin();
+           it != _link_front_end_with_rename_unit[i].end();
+           ++it)
+        _front_end_rat_scheme[*it] = _rat_scheme[i];
 
     ALLOC2(_array_size_depth,uint32_t,_nb_front_end,_nb_context [it1]);
@@ -138,6 +148,7 @@
     log_begin(Commit_unit,FUNCTION);
 
-    DELETE1(_have_thread     ,_nb_thread);
-    DELETE2(_array_size_depth,_nb_front_end,_nb_context [it1]);
+    DELETE1(_have_thread         ,_nb_thread);
+    DELETE2(_array_size_depth    ,_nb_front_end,_nb_context [it1]);
+    DELETE1(_front_end_rat_scheme,_nb_front_end);
 
     log_end(Commit_unit,FUNCTION);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,19 +1,0 @@
-Issue_queue
-1	1	*2	# nb_context              
-1	1	*2	# nb_front_end            
-1	1	*2	# nb_rename_unit          
-1	1	*2	# size_queue              
-0       1       +1      # queue_scheme
-1	1	*2	# nb_bank                 
-0	0	*2	# size_packet             
-32	32	*2	# size_general_data       
-2	2	*2	# size_special_data       
-5	5	*2	# size_general_register   
-2	2	*2	# size_special_register   
-1	1	*2	# size_store_queue_ptr    
-0	0	*2	# size_load_queue_ptr     
-1	1	*2	# nb_inst_rename         [0]               [nb_rename_unit]
-1	1	*2	# nb_inst_reexecute       
-1	1	*2	# nb_rename_unit_select   
-1	1	*2	# priority                
-1	1	*2	# load_balancing          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_mono_rename_unit.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_mono_rename_unit.cfg	(revision 144)
+++ 	(revision )
@@ -1,19 +1,0 @@
-Issue_queue
-4	4	*2	# nb_context              
-4	4	*2	# nb_front_end            
-1	1	*2	# nb_rename_unit          
-16	32	*2	# size_queue              
-0       1       +1      # queue_scheme
-4	16	*2	# nb_bank                 
-0	0	*2	# size_packet             
-32	32	*2	# size_general_data       
-2	2	*2	# size_special_data       
-5	5	*2	# size_general_register   
-2	2	*2	# size_special_register   
-1	1	*2	# size_store_queue_ptr    
-0	0	*2	# size_load_queue_ptr     
-1	4	*4	# nb_inst_rename         [0]               [nb_rename_unit]
-1	4	*4	# nb_inst_reexecute       
-1	1	*2	# nb_rename_unit_select   
-1	1	*2	# priority                
-1	1	*2	# load_balancing          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_multi_rename_unit.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_multi_rename_unit.cfg	(revision 144)
+++ 	(revision )
@@ -1,22 +1,0 @@
-Issue_queue
-4	4	*2	# nb_context              
-4	4	*2	# nb_front_end            
-4	4	*2	# nb_rename_unit          
-64	64	*2	# size_queue              
-0       1       +1      # queue_scheme
-4	16	*2	# nb_bank                 
-0	0	*2	# size_packet             
-32	32	*2	# size_general_data       
-2	2	*2	# size_special_data       
-5	5	*2	# size_general_register   
-2	2	*2	# size_special_register   
-1	1	*2	# size_store_queue_ptr    
-0	0	*2	# size_load_queue_ptr     
-4	4	*4	# nb_inst_rename         [0]               [nb_rename_unit]
-1	1	*4	# nb_inst_rename         [1]               [nb_rename_unit]
-2	2	*4	# nb_inst_rename         [2]               [nb_rename_unit]
-8	8	*4	# nb_inst_rename         [3]               [nb_rename_unit]
-4	4	*4	# nb_inst_reexecute       
-1	4	+1	# nb_rename_unit_select   
-1	1	*2	# priority                
-1	1	*2	# load_balancing          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,19 @@
+Issue_queue
+1	1	*2	# nb_context              
+1	1	*2	# nb_front_end            
+1	1	*2	# nb_rename_unit          
+1	1	*2	# size_queue              
+0       1       +1      # queue_scheme
+1	1	*2	# nb_bank                 
+0	0	*2	# size_packet             
+32	32	*2	# size_general_data       
+2	2	*2	# size_special_data       
+5	5	*2	# size_general_register   
+2	2	*2	# size_special_register   
+1	1	*2	# size_store_queue_ptr    
+0	0	*2	# size_load_queue_ptr     
+1	1	*2	# nb_inst_rename         [0]               [nb_rename_unit]
+1	1	*2	# nb_inst_reexecute       
+1	1	*2	# nb_rename_unit_select   
+1	1	*2	# priority                
+1	1	*2	# load_balancing          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_mono_rename_unit.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_mono_rename_unit.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_mono_rename_unit.gen	(revision 145)
@@ -0,0 +1,19 @@
+Issue_queue
+4	4	*2	# nb_context              
+4	4	*2	# nb_front_end            
+1	1	*2	# nb_rename_unit          
+16	32	*2	# size_queue              
+0       1       +1      # queue_scheme
+4	16	*2	# nb_bank                 
+0	0	*2	# size_packet             
+32	32	*2	# size_general_data       
+2	2	*2	# size_special_data       
+5	5	*2	# size_general_register   
+2	2	*2	# size_special_register   
+1	1	*2	# size_store_queue_ptr    
+0	0	*2	# size_load_queue_ptr     
+1	4	*4	# nb_inst_rename         [0]               [nb_rename_unit]
+1	4	*4	# nb_inst_reexecute       
+1	1	*2	# nb_rename_unit_select   
+1	1	*2	# priority                
+1	1	*2	# load_balancing          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_multi_rename_unit.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_multi_rename_unit.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/configuration/config_multi_rename_unit.gen	(revision 145)
@@ -0,0 +1,22 @@
+Issue_queue
+4	4	*2	# nb_context              
+4	4	*2	# nb_front_end            
+4	4	*2	# nb_rename_unit          
+64	64	*2	# size_queue              
+0       1       +1      # queue_scheme
+4	16	*2	# nb_bank                 
+0	0	*2	# size_packet             
+32	32	*2	# size_general_data       
+2	2	*2	# size_special_data       
+5	5	*2	# size_general_register   
+2	2	*2	# size_special_register   
+1	1	*2	# size_store_queue_ptr    
+0	0	*2	# size_load_queue_ptr     
+4	4	*4	# nb_inst_rename         [0]               [nb_rename_unit]
+1	1	*4	# nb_inst_rename         [1]               [nb_rename_unit]
+2	2	*4	# nb_inst_rename         [2]               [nb_rename_unit]
+8	8	*4	# nb_inst_rename         [3]               [nb_rename_unit]
+4	4	*4	# nb_inst_reexecute       
+1	4	+1	# nb_rename_unit_select   
+1	1	*2	# priority                
+1	1	*2	# load_balancing          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_1.cfg	(revision 144)
+++ 	(revision )
@@ -1,15 +1,0 @@
-OOO_Engine_Glue
-1	1	*2	# nb_front_end                    
-1	1	*2	# nb_context                      [0] [nb_front_end]
-1	1	*2	# nb_rename_unit                     
-4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
-4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
-4	4	*2	# nb_inst_retire                  [0] [nb_rename_unit]
-32	32	*2	# size_general_data                  
-2	2	*2	# size_special_data                  
-0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
-2	2	*2	# size_packet_id                    
-8	8	*2	# size_general_register             
-4	4	*2	# size_special_register             
-4	4	*2	# size_store_queue_ptr              
-4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_4.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_4.cfg	(revision 144)
+++ 	(revision )
@@ -1,21 +1,0 @@
-OOO_Engine_Glue
-1	1	*2	# nb_front_end                    
-1	1	*2	# nb_context                      [0] [nb_front_end]
-4	4	*2	# nb_rename_unit                     
-4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
-4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
-2	2	*2	# nb_inst_insert                  [1] [nb_rename_unit]
-1	1	*2	# nb_inst_insert                  [2] [nb_rename_unit]
-4	4	*2	# nb_inst_insert                  [3] [nb_rename_unit]
-1	1	*2	# nb_inst_retire                  [0] [nb_rename_unit]
-8	8	*2	# nb_inst_retire                  [1] [nb_rename_unit]
-2	2	*2	# nb_inst_retire                  [2] [nb_rename_unit]
-4	4	*2	# nb_inst_retire                  [3] [nb_rename_unit]
-32	32	*2	# size_general_data                  
-2	2	*2	# size_special_data                  
-0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
-2	2	*2	# size_packet_id                    
-8	8	*2	# size_general_register             
-4	4	*2	# size_special_register             
-4	4	*2	# size_store_queue_ptr              
-4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_1.cfg	(revision 144)
+++ 	(revision )
@@ -1,24 +1,0 @@
-OOO_Engine_Glue
-4	4	*2	# nb_front_end                    
-4	4	*2	# nb_context                      [0] [nb_front_end]
-1	1	*2	# nb_context                      [1] [nb_front_end]
-2	2	*2	# nb_context                      [2] [nb_front_end]
-8	8	*2	# nb_context                      [3] [nb_front_end]
-1	1	*2	# nb_rename_unit                     
-4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
-2	2	*2	# nb_inst_decod                   [1] [nb_front_end]
-1	1	*2	# nb_inst_decod                   [2] [nb_front_end]
-4	4	*2	# nb_inst_decod                   [3] [nb_front_end]
-4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
-4	4	*2	# nb_inst_retire                  [0] [nb_rename_unit]
-32	32	*2	# size_general_data                  
-2	2	*2	# size_special_data                  
-0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
-0	0	*2	# link_rename_unit_with_front_end [1] [nb_front_end]
-0	0	*2	# link_rename_unit_with_front_end [2] [nb_front_end]
-0	0	*2	# link_rename_unit_with_front_end [3] [nb_front_end]
-2	2	*2	# size_packet_id                    
-8	8	*2	# size_general_register             
-4	4	*2	# size_special_register             
-4	4	*2	# size_store_queue_ptr              
-4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_4.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_4.cfg	(revision 144)
+++ 	(revision )
@@ -1,30 +1,0 @@
-OOO_Engine_Glue
-4	4	*2	# nb_front_end                    
-4	4	*2	# nb_context                      [0] [nb_front_end]
-1	1	*2	# nb_context                      [1] [nb_front_end]
-2	2	*2	# nb_context                      [2] [nb_front_end]
-8	8	*2	# nb_context                      [3] [nb_front_end]
-4	4	*2	# nb_rename_unit                     
-4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
-2	2	*2	# nb_inst_decod                   [1] [nb_front_end]
-1	1	*2	# nb_inst_decod                   [2] [nb_front_end]
-4	4	*2	# nb_inst_decod                   [3] [nb_front_end]
-4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
-2	2	*2	# nb_inst_insert                  [1] [nb_rename_unit]
-1	1	*2	# nb_inst_insert                  [2] [nb_rename_unit]
-4	4	*2	# nb_inst_insert                  [3] [nb_rename_unit]
-1	1	*2	# nb_inst_retire                  [0] [nb_rename_unit]
-8	8	*2	# nb_inst_retire                  [1] [nb_rename_unit]
-2	2	*2	# nb_inst_retire                  [2] [nb_rename_unit]
-4	4	*2	# nb_inst_retire                  [3] [nb_rename_unit]
-32	32	*2	# size_general_data                  
-2	2	*2	# size_special_data                  
-0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
-3	3	*2	# link_rename_unit_with_front_end [1] [nb_front_end]
-1	1	*2	# link_rename_unit_with_front_end [2] [nb_front_end]
-2	2	*2	# link_rename_unit_with_front_end [3] [nb_front_end]
-2	2	*2	# size_packet_id                    
-8	8	*2	# size_general_register             
-4	4	*2	# size_special_register             
-4	4	*2	# size_store_queue_ptr              
-4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,15 +1,0 @@
-OOO_Engine_Glue
-1	1	*2	# nb_front_end                    
-1	1	*2	# nb_context                      [0] [nb_front_end]
-1	1	*2	# nb_rename_unit                     
-1	1	*2	# nb_inst_decod                   [0] [nb_front_end]
-1	1	*2	# nb_inst_insert                  [0] [nb_rename_unit]
-1	1	*2	# nb_inst_retire                  [0] [nb_rename_unit]
-32	32	*2	# size_general_data                  
-2	2	*2	# size_special_data                  
-0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
-0	0	*2	# size_packet_id                    
-6	6	*2	# size_general_register             
-2	2	*2	# size_special_register             
-1	1	*2	# size_store_queue_ptr              
-0	0	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_1-rename_unit_1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_1-rename_unit_1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_1-rename_unit_1.gen	(revision 145)
@@ -0,0 +1,15 @@
+OOO_Engine_Glue
+1	1	*2	# nb_front_end                    
+1	1	*2	# nb_context                      [0] [nb_front_end]
+1	1	*2	# nb_rename_unit                     
+4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
+4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
+4	4	*2	# nb_inst_retire                  [0] [nb_rename_unit]
+32	32	*2	# size_general_data                  
+2	2	*2	# size_special_data                  
+0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
+2	2	*2	# size_packet_id                    
+8	8	*2	# size_general_register             
+4	4	*2	# size_special_register             
+4	4	*2	# size_store_queue_ptr              
+4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_1-rename_unit_4.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_1-rename_unit_4.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_1-rename_unit_4.gen	(revision 145)
@@ -0,0 +1,21 @@
+OOO_Engine_Glue
+1	1	*2	# nb_front_end                    
+1	1	*2	# nb_context                      [0] [nb_front_end]
+4	4	*2	# nb_rename_unit                     
+4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
+4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
+2	2	*2	# nb_inst_insert                  [1] [nb_rename_unit]
+1	1	*2	# nb_inst_insert                  [2] [nb_rename_unit]
+4	4	*2	# nb_inst_insert                  [3] [nb_rename_unit]
+1	1	*2	# nb_inst_retire                  [0] [nb_rename_unit]
+8	8	*2	# nb_inst_retire                  [1] [nb_rename_unit]
+2	2	*2	# nb_inst_retire                  [2] [nb_rename_unit]
+4	4	*2	# nb_inst_retire                  [3] [nb_rename_unit]
+32	32	*2	# size_general_data                  
+2	2	*2	# size_special_data                  
+0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
+2	2	*2	# size_packet_id                    
+8	8	*2	# size_general_register             
+4	4	*2	# size_special_register             
+4	4	*2	# size_store_queue_ptr              
+4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_4-rename_unit_1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_4-rename_unit_1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_4-rename_unit_1.gen	(revision 145)
@@ -0,0 +1,24 @@
+OOO_Engine_Glue
+4	4	*2	# nb_front_end                    
+4	4	*2	# nb_context                      [0] [nb_front_end]
+1	1	*2	# nb_context                      [1] [nb_front_end]
+2	2	*2	# nb_context                      [2] [nb_front_end]
+8	8	*2	# nb_context                      [3] [nb_front_end]
+1	1	*2	# nb_rename_unit                     
+4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
+2	2	*2	# nb_inst_decod                   [1] [nb_front_end]
+1	1	*2	# nb_inst_decod                   [2] [nb_front_end]
+4	4	*2	# nb_inst_decod                   [3] [nb_front_end]
+4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
+4	4	*2	# nb_inst_retire                  [0] [nb_rename_unit]
+32	32	*2	# size_general_data                  
+2	2	*2	# size_special_data                  
+0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
+0	0	*2	# link_rename_unit_with_front_end [1] [nb_front_end]
+0	0	*2	# link_rename_unit_with_front_end [2] [nb_front_end]
+0	0	*2	# link_rename_unit_with_front_end [3] [nb_front_end]
+2	2	*2	# size_packet_id                    
+8	8	*2	# size_general_register             
+4	4	*2	# size_special_register             
+4	4	*2	# size_store_queue_ptr              
+4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_4-rename_unit_4.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_4-rename_unit_4.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-front_end_4-rename_unit_4.gen	(revision 145)
@@ -0,0 +1,30 @@
+OOO_Engine_Glue
+4	4	*2	# nb_front_end                    
+4	4	*2	# nb_context                      [0] [nb_front_end]
+1	1	*2	# nb_context                      [1] [nb_front_end]
+2	2	*2	# nb_context                      [2] [nb_front_end]
+8	8	*2	# nb_context                      [3] [nb_front_end]
+4	4	*2	# nb_rename_unit                     
+4	4	*2	# nb_inst_decod                   [0] [nb_front_end]
+2	2	*2	# nb_inst_decod                   [1] [nb_front_end]
+1	1	*2	# nb_inst_decod                   [2] [nb_front_end]
+4	4	*2	# nb_inst_decod                   [3] [nb_front_end]
+4	4	*2	# nb_inst_insert                  [0] [nb_rename_unit]
+2	2	*2	# nb_inst_insert                  [1] [nb_rename_unit]
+1	1	*2	# nb_inst_insert                  [2] [nb_rename_unit]
+4	4	*2	# nb_inst_insert                  [3] [nb_rename_unit]
+1	1	*2	# nb_inst_retire                  [0] [nb_rename_unit]
+8	8	*2	# nb_inst_retire                  [1] [nb_rename_unit]
+2	2	*2	# nb_inst_retire                  [2] [nb_rename_unit]
+4	4	*2	# nb_inst_retire                  [3] [nb_rename_unit]
+32	32	*2	# size_general_data                  
+2	2	*2	# size_special_data                  
+0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
+3	3	*2	# link_rename_unit_with_front_end [1] [nb_front_end]
+1	1	*2	# link_rename_unit_with_front_end [2] [nb_front_end]
+2	2	*2	# link_rename_unit_with_front_end [3] [nb_front_end]
+2	2	*2	# size_packet_id                    
+8	8	*2	# size_general_register             
+4	4	*2	# size_special_register             
+4	4	*2	# size_store_queue_ptr              
+4	4	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,15 @@
+OOO_Engine_Glue
+1	1	*2	# nb_front_end                    
+1	1	*2	# nb_context                      [0] [nb_front_end]
+1	1	*2	# nb_rename_unit                     
+1	1	*2	# nb_inst_decod                   [0] [nb_front_end]
+1	1	*2	# nb_inst_insert                  [0] [nb_rename_unit]
+1	1	*2	# nb_inst_retire                  [0] [nb_rename_unit]
+32	32	*2	# size_general_data                  
+2	2	*2	# size_special_data                  
+0	0	*2	# link_rename_unit_with_front_end [0] [nb_front_end]
+0	0	*2	# size_packet_id                    
+6	6	*2	# size_general_register             
+2	2	*2	# size_special_register             
+1	1	*2	# size_store_queue_ptr              
+0	0	*2	# size_load_queue_ptr               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_1.cfg	(revision 144)
+++ 	(revision )
@@ -1,18 +1,0 @@
-Reexecute_unit
-0	0	+1	# size_context_id         
-0	0	+1	# size_front_end_id       
-6	6	+1	# size_packet_id          
-4	4	+1	# size_queue              
-1	1	+1	# nb_execute_loop         
-4	4	+1	# nb_inst_execute          [0] [nb_execute_loop]
-2	2	+1	# nb_inst_commit          
-2	2	+1	# nb_inst_reexecute       
-1	1	+1	# nb_execute_loop_select  
-0	1	+1	# priority                
-0	1	+1	# load_balancing          
-5	5	+1	# size_general_register_id
-1	1	+1	# size_special_register_id
-32	32	+1	# size_general_data       
-5	5	+1	# size_special_data       
-2	2	+1	# size_store_queue_ptr    
-2	2	+1	# size_load_queue_ptr     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_4.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_4.cfg	(revision 144)
+++ 	(revision )
@@ -1,21 +1,0 @@
-Reexecute_unit
-0	0	+1	# size_context_id         
-0	0	+1	# size_front_end_id       
-6	6	+1	# size_packet_id          
-8	8	+1	# size_queue              
-4	4	+1	# nb_execute_loop         
-4	4	+1	# nb_inst_execute          [0] [nb_execute_loop]
-1	1	+1	# nb_inst_execute          [1] [nb_execute_loop]
-3	3	+1	# nb_inst_execute          [2] [nb_execute_loop]
-8	8	+1	# nb_inst_execute          [3] [nb_execute_loop]
-4	4	+1	# nb_inst_commit          
-3 	3	+1	# nb_inst_reexecute       
-1	4	+1	# nb_execute_loop_select  
-0	1	+1	# priority                
-0	1	+1	# load_balancing          
-5	5	+1	# size_general_register_id
-1	1	+1	# size_special_register_id
-32	32	+1	# size_general_data       
-5	5	+1	# size_special_data       
-2	2	+1	# size_store_queue_ptr    
-2	2	+1	# size_load_queue_ptr     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,18 +1,0 @@
-Reexecute_unit
-0	0	+1	# size_context_id         
-0	0	+1	# size_front_end_id       
-0	0	+1	# size_packet_id          
-1	1	+1	# size_queue              
-1	1	+1	# nb_execute_loop         
-1	1	+1	# nb_inst_execute          [0] [nb_execute_loop]
-1	1	+1	# nb_inst_commit          
-1	1	+1	# nb_inst_reexecute       
-1	1	+1	# nb_execute_loop_select  
-0	1	+1	# priority                
-0	1	+1	# load_balancing          
-5	5	+1	# size_general_register_id
-1	1	+1	# size_special_register_id
-32	32	+1	# size_general_data       
-5	5	+1	# size_special_data       
-1	1	+1	# size_store_queue_ptr    
-0	0	+1	# size_load_queue_ptr     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-execute_loop_1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-execute_loop_1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-execute_loop_1.gen	(revision 145)
@@ -0,0 +1,18 @@
+Reexecute_unit
+0	0	+1	# size_context_id         
+0	0	+1	# size_front_end_id       
+6	6	+1	# size_packet_id          
+4	4	+1	# size_queue              
+1	1	+1	# nb_execute_loop         
+4	4	+1	# nb_inst_execute          [0] [nb_execute_loop]
+2	2	+1	# nb_inst_commit          
+2	2	+1	# nb_inst_reexecute       
+1	1	+1	# nb_execute_loop_select  
+0	1	+1	# priority                
+0	1	+1	# load_balancing          
+5	5	+1	# size_general_register_id
+1	1	+1	# size_special_register_id
+32	32	+1	# size_general_data       
+5	5	+1	# size_special_data       
+2	2	+1	# size_store_queue_ptr    
+2	2	+1	# size_load_queue_ptr     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-execute_loop_4.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-execute_loop_4.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-execute_loop_4.gen	(revision 145)
@@ -0,0 +1,21 @@
+Reexecute_unit
+0	0	+1	# size_context_id         
+0	0	+1	# size_front_end_id       
+6	6	+1	# size_packet_id          
+8	8	+1	# size_queue              
+4	4	+1	# nb_execute_loop         
+4	4	+1	# nb_inst_execute          [0] [nb_execute_loop]
+1	1	+1	# nb_inst_execute          [1] [nb_execute_loop]
+3	3	+1	# nb_inst_execute          [2] [nb_execute_loop]
+8	8	+1	# nb_inst_execute          [3] [nb_execute_loop]
+4	4	+1	# nb_inst_commit          
+3 	3	+1	# nb_inst_reexecute       
+1	4	+1	# nb_execute_loop_select  
+0	1	+1	# priority                
+0	1	+1	# load_balancing          
+5	5	+1	# size_general_register_id
+1	1	+1	# size_special_register_id
+32	32	+1	# size_general_data       
+5	5	+1	# size_special_data       
+2	2	+1	# size_store_queue_ptr    
+2	2	+1	# size_load_queue_ptr     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,18 @@
+Reexecute_unit
+0	0	+1	# size_context_id         
+0	0	+1	# size_front_end_id       
+0	0	+1	# size_packet_id          
+1	1	+1	# size_queue              
+1	1	+1	# nb_execute_loop         
+1	1	+1	# nb_inst_execute          [0] [nb_execute_loop]
+1	1	+1	# nb_inst_commit          
+1	1	+1	# nb_inst_reexecute       
+1	1	+1	# nb_execute_loop_select  
+0	1	+1	# priority                
+0	1	+1	# load_balancing          
+5	5	+1	# size_general_register_id
+1	1	+1	# size_special_register_id
+32	32	+1	# size_general_data       
+5	5	+1	# size_special_data       
+1	1	+1	# size_store_queue_ptr    
+0	0	+1	# size_load_queue_ptr     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Load_Store_pointer_unit
-1	1	*2	# nb_front_end                            
-1	1	*2	# nb_context                       [0]    [nb_front_end]
-1	1	*2	# nb_load_store_queue              
-2	4	*2	# size_store_queue                 [0]    [nb_load_store_queue]
-1	4	*2	# size_load_queue                  [0]    [nb_load_store_queue]
-1	4	*4	# nb_inst_memory                   [0]    [nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
-1	4	*4	# nb_inst_insert
-1	4	*4	# nb_inst_retire
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,10 @@
+Load_Store_pointer_unit
+1	1	*2	# nb_front_end                            
+1	1	*2	# nb_context                       [0]    [nb_front_end]
+1	1	*2	# nb_load_store_queue              
+2	4	*2	# size_store_queue                 [0]    [nb_load_store_queue]
+1	4	*2	# size_load_queue                  [0]    [nb_load_store_queue]
+1	4	*4	# nb_inst_memory                   [0]    [nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
+1	4	*4	# nb_inst_insert
+1	4	*4	# nb_inst_retire
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h	(revision 145)
@@ -112,5 +112,5 @@
   private   : uint32_t                       * internal_RETIRE_LSQ          ; // [nb_inst_retire]
   private   : Tlsq_ptr_t                     * internal_RETIRE_PTR          ; // [nb_inst_retire]
-  private   : Tcontrol_t                    ** internal_RETIRE_EVENT_ACK    ;//[nb_front_end][nb_context]
+  private   : Tcontrol_t                    ** internal_RETIRE_EVENT_ACK    ; //[nb_front_end][nb_context]
 
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp	(revision 145)
@@ -27,7 +27,6 @@
     if (PORT_READ(in_NRESET))
       {
-    // TODO : limité à nb_inst_memory le nombre d'accès par lsq !!!
-
-    uint32_t   nb_use_lsq            [_param->_nb_load_store_queue];
+    // Limit at nb_inst_memory access per load_store_queue
+    // uint32_t   nb_use_lsq            [_param->_nb_load_store_queue];
     Tlsq_ptr_t STORE_QUEUE_PTR_WRITE [_param->_nb_load_store_queue];
     bool       STORE_QUEUE_USE       [_param->_nb_load_store_queue][_param->_max_size_store_queue];
@@ -38,5 +37,5 @@
     for (uint32_t i=0; i<_param->_nb_load_store_queue; i++)
       {
-        nb_use_lsq            [i] = _param->_nb_inst_memory[i];
+        // nb_use_lsq            [i] = _param->_nb_inst_memory[i];
 
         STORE_QUEUE_PTR_WRITE [i] = reg_STORE_QUEUE_PTR_WRITE [i];
@@ -82,7 +81,7 @@
                 // Test if a previous instruction use the same lsq
                 // Authorize once memory access by load store unit
-                if (nb_use_lsq [lsq] > 0)
+                // if (nb_use_lsq [lsq] > 0)
                   {
-                    nb_use_lsq [lsq] --;
+                    // nb_use_lsq [lsq] --;
                     
                     uint32_t   ptr;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-Dependency_checking_unit
-1	4	*2	# nb_front_end       
-1	4	*2	# max_nb_context     
-64	64	*2	# nb_general_register
-16	16	*2	# nb_special_register
-1	8	*2	# nb_inst_insert     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,6 @@
+Dependency_checking_unit
+1	4	*2	# nb_front_end       
+1	4	*2	# max_nb_context     
+64	64	*2	# nb_general_register
+16	16	*2	# nb_special_register
+1	8	*2	# nb_inst_insert     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/config_mono_pop.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/config_mono_pop.cfg	(revision 144)
+++ 	(revision )
@@ -1,8 +1,0 @@
-Free_List_unit
-1	1	*2	# nb_thread          
-64	64	*2	# nb_general_register
-16	16	*2	# nb_special_register
-1	4	*2	# nb_bank            
-1	1	*2	# nb_pop             
-1	4	*2	# nb_push            
-0	1	+1  	# priority           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/config_multi_pop.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/config_multi_pop.cfg	(revision 144)
+++ 	(revision )
@@ -1,8 +1,0 @@
-Free_List_unit
-1	1	*2	# nb_thread          
-64	64	*2	# nb_general_register
-16	16	*2	# nb_special_register
-4	8	*2	# nb_bank            
-1	4	*2	# nb_pop             
-2	2	*2	# nb_push            
-0	1	+1  	# priority           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/configuration/config_mono_pop.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/configuration/config_mono_pop.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/configuration/config_mono_pop.gen	(revision 145)
@@ -0,0 +1,8 @@
+Free_List_unit
+1	1	*2	# nb_thread          
+64	64	*2	# nb_general_register
+16	16	*2	# nb_special_register
+1	4	*2	# nb_bank            
+1	1	*2	# nb_pop             
+1	4	*2	# nb_push            
+0	1	+1  	# priority           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/configuration/config_multi_pop.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/configuration/config_multi_pop.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/configuration/config_multi_pop.gen	(revision 145)
@@ -0,0 +1,8 @@
+Free_List_unit
+1	1	*2	# nb_thread          
+64	64	*2	# nb_general_register
+16	16	*2	# nb_special_register
+4	8	*2	# nb_bank            
+1	4	*2	# nb_pop             
+2	2	*2	# nb_push            
+0	1	+1  	# priority           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/config_mono_front_end.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/config_mono_front_end.cfg	(revision 144)
+++ 	(revision )
@@ -1,7 +1,0 @@
-Register_Address_Translation_unit
-1	1	+1	# nb_front_end          
-1	1	+1	# nb_context            [0] [nb_front_end]
-4 	4 	*2	# nb_general_register   
-4 	4 	*2	# nb_special_register   
-4	4	+1	# nb_inst_insert
-4	4	+1	# nb_inst_retire
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/config_multi_front_end.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/config_multi_front_end.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Register_Address_Translation_unit
-4	4	+1	# nb_front_end          
-1	1	+1	# nb_context            [0] [nb_front_end]
-2	2	+1	# nb_context            [1] [nb_front_end]
-1	1	+1	# nb_context            [2] [nb_front_end]
-4	4	+1	# nb_context            [3] [nb_front_end]
-64	64	*2	# nb_general_register   
-16	16	*2	# nb_special_register   
-4	4	+1	# nb_inst_insert
-4	4	+1	# nb_inst_retire
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/configuration/config_mono_front_end.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/configuration/config_mono_front_end.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/configuration/config_mono_front_end.gen	(revision 145)
@@ -0,0 +1,7 @@
+Register_Address_Translation_unit
+1	1	+1	# nb_front_end          
+1	1	+1	# nb_context            [0] [nb_front_end]
+4 	4 	*2	# nb_general_register   
+4 	4 	*2	# nb_special_register   
+4	4	+1	# nb_inst_insert
+4	4	+1	# nb_inst_retire
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/configuration/config_multi_front_end.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/configuration/config_multi_front_end.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/configuration/config_multi_front_end.gen	(revision 145)
@@ -0,0 +1,10 @@
+Register_Address_Translation_unit
+4	4	+1	# nb_front_end          
+1	1	+1	# nb_context            [0] [nb_front_end]
+2	2	+1	# nb_context            [1] [nb_front_end]
+1	1	+1	# nb_context            [2] [nb_front_end]
+4	4	+1	# nb_context            [3] [nb_front_end]
+64	64	*2	# nb_general_register   
+16	16	*2	# nb_special_register   
+4	4	+1	# nb_inst_insert
+4	4	+1	# nb_inst_retire
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Parameters.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Parameters.h	(revision 145)
@@ -36,4 +36,5 @@
     
   public : uint32_t         _max_nb_context        ;
+  public : uint32_t         _max_nb_branch_speculated;
 //public : uint32_t         _size_front_end_id     ;
 //public : uint32_t         _size_context_id       ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h	(revision 145)
@@ -107,28 +107,32 @@
 
     // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-  public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_VAL            ;//[nb_front_end][nb_context]
-  public    : SC_OUT(Tcontrol_t        )  *** out_RETIRE_EVENT_ACK            ;//[nb_front_end][nb_context]
-  public    : SC_IN (Tevent_state_t    )  ***  in_RETIRE_EVENT_STATE          ;//[nb_front_end][nb_context]
-  public    : SC_IN (Tevent_type_t     )  ***  in_RETIRE_EVENT_TYPE           ;//[nb_front_end][nb_context]
-  public    : SC_IN (Tdepth_t          )  ***  in_RETIRE_EVENT_DEPTH          ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_VAL         ;//[nb_front_end][nb_context]
+  public    : SC_OUT(Tcontrol_t        )  *** out_RETIRE_EVENT_ACK         ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tevent_state_t    )  ***  in_RETIRE_EVENT_STATE       ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tevent_type_t     )  ***  in_RETIRE_EVENT_TYPE        ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tdepth_t          )  ***  in_RETIRE_EVENT_DEPTH       ;//[nb_front_end][nb_context]
+
+    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MIN                   ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MAX                   ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_DEPTH_FULL                  ;//[nb_front_end][nb_context]
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-  private   : Tgeneral_address_t          *** rat_gpr_not_speculative;      //[nb_front_end][nb_context]                      [nb_general_register_logic]
-  private   : Tgeneral_address_t          *** rat_gpr_speculative;          //[nb_front_end][nb_context]                      [nb_general_register_logic]
-  private   : bool                        *** rat_gpr_speculative_valid;    //[nb_front_end][nb_context]                      [nb_general_register_logic]
-  private   : Tgeneral_address_t         **** rat_gpr_save;                 //[nb_front_end][nb_context][nb_branch_speculated][nb_general_register_logic]
-
-  private   : Tspecial_address_t          *** rat_spr_not_speculative;      //[nb_front_end][nb_context]                      [nb_special_register_logic]
-  private   : Tspecial_address_t          *** rat_spr_speculative;          //[nb_front_end][nb_context]                      [nb_special_register_logic]
-  private   : bool                        *** rat_spr_speculative_valid;    //[nb_front_end][nb_context]                      [nb_special_register_logic]
-  private   : Tspecial_address_t         **** rat_spr_save;                 //[nb_front_end][nb_context][nb_branch_speculated][nb_special_register_logic]
-
-  private   : Tdepth_t                     ** rat_depth;                    //[nb_front_end][nb_context]
+                                                                            //                                                                            NO ONE DEPTH
+  private   : Tgeneral_address_t          *** RAT_GPR_NOT_SPECULATIVE;      //[nb_front_end][nb_context]                      [nb_general_register_logic] X  X   X
+  private   : Tgeneral_address_t         **** RAT_GPR_SPECULATIVE;          //[nb_front_end][nb_context][nb_branch_speculated][nb_general_register_logic]    X   X
+  private   : bool                       **** RAT_GPR_SPECULATIVE_VALID;    //[nb_front_end][nb_context][nb_branch_speculated][nb_general_register_logic]    X   X
+
+  private   : Tspecial_address_t          *** RAT_SPR_NOT_SPECULATIVE;      //[nb_front_end][nb_context]                      [nb_special_register_logic] X  X   X
+  private   : Tspecial_address_t         **** RAT_SPR_SPECULATIVE;          //[nb_front_end][nb_context][nb_branch_speculated][nb_special_register_logic]    X   X
+  private   : bool                       **** RAT_SPR_SPECULATIVE_VALID;    //[nb_front_end][nb_context][nb_branch_speculated][nb_special_register_logic]    X   X
+
+  private   : bool                        *** reg_RAT_USE;                  //[nb_front_end][nb_context][nb_branch_speculated]                                   X
+  private   : bool                         ** reg_SAVE_RAT;                 //[nb_front_end][nb_context]                                                         X
 
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   private   : Tcontrol_t                    * internal_RENAME_ACK;          //[nb_inst_insert]
-  private   : Tcontrol_t                    * internal_RENAME_SAVE;         //[nb_inst_insert]
   private   : Tcontrol_t                    * internal_INSERT_ACK;          //[nb_inst_insert]
   private   : Tcontrol_t                    * internal_RETIRE_ACK;          //[nb_inst_retire]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Parameters.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Parameters.cpp	(revision 145)
@@ -41,5 +41,6 @@
     _nb_branch_speculated   = nb_branch_speculated;
 
-    _max_nb_context         = max<uint32_t>(_nb_context, _nb_front_end);
+    _max_nb_context          = max<uint32_t>(_nb_context, _nb_front_end);
+    _max_nb_branch_speculated= max<uint32_t>(_nb_branch_speculated, _nb_front_end, _nb_context);
 
     test();
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp	(revision 145)
@@ -160,6 +160,12 @@
         for (uint32_t i=0; i<_param->_nb_front_end; ++i)
           for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
-            sensitive << (*(in_RETIRE_EVENT_VAL   [i][j]))
-                      << (*(in_RETIRE_EVENT_STATE [i][j]));
+            {
+              sensitive << (*(in_RETIRE_EVENT_VAL   [i][j]))
+                        << (*(in_RETIRE_EVENT_STATE [i][j]))
+                        << (*(in_DEPTH_FULL         [i][j]));
+              if (_param->_have_port_depth)
+              sensitive << (*(in_DEPTH_MIN          [i][j]))
+                        << (*(in_DEPTH_MAX          [i][j]));
+            }
 
 # ifdef SYSTEMCASS_SPECIFIC
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp	(revision 145)
@@ -131,14 +131,24 @@
     }
 
+    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);
+
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN                    ,"MIN"               ,Tdepth_t         ,_param->_size_depth       ,_param->_nb_front_end,_param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX                    ,"MAX"               ,Tdepth_t         ,_param->_size_depth       ,_param->_nb_front_end,_param->_nb_context[it1]); 
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL                   ,"FULL"              ,Tcontrol_t       ,1                         ,_param->_nb_front_end,_param->_nb_context[it1]); 
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]);
+    }
+
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
     ALLOC1(internal_RENAME_ACK       ,Tcontrol_t,_param->_nb_inst_insert);
-    ALLOC1(internal_RENAME_SAVE      ,Tcontrol_t,_param->_nb_inst_insert);
     ALLOC1(internal_INSERT_ACK       ,Tcontrol_t,_param->_nb_inst_insert);
     ALLOC1(internal_RETIRE_ACK       ,Tcontrol_t,_param->_nb_inst_retire);
     ALLOC2(internal_RETIRE_EVENT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]);
 
-    ALLOC3(rat_gpr_speculative      ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-    ALLOC3(rat_spr_speculative      ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+    ALLOC3(RAT_GPR_NOT_SPECULATIVE  ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
+    ALLOC3(RAT_SPR_NOT_SPECULATIVE  ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
 
     switch(_param->_rat_scheme)
@@ -150,9 +160,9 @@
       case RAT_ONE_SAVE   :
         {
-          ALLOC3(rat_gpr_not_speculative  ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-          ALLOC3(rat_gpr_speculative_valid,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-
-          ALLOC3(rat_spr_not_speculative  ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
-          ALLOC3(rat_spr_speculative_valid,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+          ALLOC4(RAT_GPR_SPECULATIVE      ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic);
+          ALLOC4(RAT_SPR_SPECULATIVE      ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic);
+
+          ALLOC4(RAT_GPR_SPECULATIVE_VALID,bool              ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic);
+          ALLOC4(RAT_SPR_SPECULATIVE_VALID,bool              ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic);
           
           break;
@@ -160,8 +170,13 @@
       case RAT_DEPTH_SAVE :
         {
-          ALLOC4(rat_gpr_save             ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
-          ALLOC4(rat_spr_save             ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
-          ALLOC2(rat_depth                ,Tdepth_t          ,_param->_nb_front_end,_param->_nb_context[it1]);
-    
+          ALLOC4(RAT_GPR_SPECULATIVE      ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
+          ALLOC4(RAT_SPR_SPECULATIVE      ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
+
+          ALLOC4(RAT_GPR_SPECULATIVE_VALID,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
+          ALLOC4(RAT_SPR_SPECULATIVE_VALID,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
+    
+          ALLOC3(reg_RAT_USE              ,bool              ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2]);
+          ALLOC2(reg_SAVE_RAT             ,bool              ,_param->_nb_front_end,_param->_nb_context[it1]);
+
           break;
         }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp	(revision 145)
@@ -76,13 +76,15 @@
         DELETE2_SIGNAL_COND( in_RETIRE_EVENT_DEPTH          ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth     ,_param->_rat_scheme == RAT_DEPTH_SAVE);
 
+        DELETE2_SIGNAL     ( in_DEPTH_MIN                   ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth);
+        DELETE2_SIGNAL     ( in_DEPTH_MAX                   ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth);
+        DELETE2_SIGNAL     ( in_DEPTH_FULL                  ,_param->_nb_front_end,_param->_nb_context[it1],1                  );
+
         DELETE1(internal_RENAME_ACK                    ,_param->_nb_inst_insert);
-        DELETE1(internal_RENAME_SAVE                   ,_param->_nb_inst_insert);
-        DELETE1(internal_INSERT_ACK                    ,_param->_nb_inst_insert);
         DELETE1(internal_RETIRE_ACK                    ,_param->_nb_inst_retire);
         DELETE2(internal_RETIRE_EVENT_ACK              ,_param->_nb_front_end,_param->_nb_context[it1]);
 
-        DELETE3(rat_gpr_speculative          ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-        DELETE3(rat_spr_speculative          ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
-
+        DELETE3(RAT_GPR_NOT_SPECULATIVE      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
+        DELETE3(RAT_SPR_NOT_SPECULATIVE      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+        
         switch(_param->_rat_scheme)
           {
@@ -93,9 +95,9 @@
           case RAT_ONE_SAVE   :
             {
-              DELETE3(rat_gpr_not_speculative      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-              DELETE3(rat_gpr_speculative_valid    ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);
-              
-              DELETE3(rat_spr_not_speculative      ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
-              DELETE3(rat_spr_speculative_valid    ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);
+              DELETE4(RAT_GPR_SPECULATIVE          ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic);
+              DELETE4(RAT_SPR_SPECULATIVE          ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic);
+
+              DELETE4(RAT_GPR_SPECULATIVE_VALID    ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic);
+              DELETE4(RAT_SPR_SPECULATIVE_VALID    ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic);
               
               break;
@@ -103,7 +105,12 @@
           case RAT_DEPTH_SAVE :
             {
-              DELETE4(rat_gpr_save                 ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
-              DELETE4(rat_spr_save                 ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
-              DELETE2(rat_depth                    ,_param->_nb_front_end,_param->_nb_context[it1]);
+              DELETE4(RAT_GPR_SPECULATIVE          ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
+              DELETE4(RAT_SPR_SPECULATIVE          ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
+
+              DELETE4(RAT_GPR_SPECULATIVE_VALID    ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic);
+              DELETE4(RAT_SPR_SPECULATIVE_VALID    ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic);
+
+              DELETE3(reg_RAT_USE                  ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2]);
+              DELETE2(reg_SAVE_RAT                 ,_param->_nb_front_end,_param->_nb_context[it1]);
 
               break;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_constant.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_constant.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_constant.cpp	(revision 145)
@@ -30,6 +30,8 @@
       {
         internal_INSERT_ACK [i] = 1;
+        internal_RENAME_ACK [i] = 1;
         
         PORT_WRITE(out_INSERT_ACK[i],internal_INSERT_ACK [i]);
+        PORT_WRITE(out_RENAME_ACK[i],internal_RENAME_ACK [i]);
       }
     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp	(revision 145)
@@ -28,66 +28,140 @@
     if (PORT_READ(in_NRESET) != 0)
       {
-        bool     have_branch_previous = false;
-        bool     can_continue [_param->_nb_front_end][_param->_max_nb_context];
+        bool rat_gpr_speculative_valid [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated][_param->_nb_general_register_logic];
+        bool rat_spr_speculative_valid [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated][_param->_nb_special_register_logic];
+        // bool reg_save_rat              [_param->_nb_front_end][_param->_max_nb_context];
 
         for (uint32_t i=0; i<_param->_nb_front_end; ++i)
           for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
-            can_continue [i][j] = true;
+            {
+              // reg_save_rat [i][j] = reg_SAVE_RAT [i][j];
+              for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+                {
+                  for (uint32_t l=0; l<_param->_nb_general_register_logic; ++l)
+                    rat_gpr_speculative_valid [i][j][k][l] = RAT_GPR_SPECULATIVE_VALID [i][j][k][l];
+                  for (uint32_t l=0; l<_param->_nb_special_register_logic; ++l)
+                    rat_spr_speculative_valid [i][j][k][l] = RAT_SPR_SPECULATIVE_VALID [i][j][k][l];
+                }
+            }
 
         for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
-          if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access
-            {
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RENAME [%d]",i);
-              
-              Tcontext_t front_end_id        = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
-              Tcontext_t context_id          = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
-              // bool       have_event          = (PORT_READ(in_RETIRE_EVENT_VAL [front_end_id][context_id]) and // always ack
-              //                                   (PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) == EVENT_STATE_EVENT));
-              
-              bool       have_branch_current = PORT_READ(in_RENAME_SAVE_RAT [i]);
+          {
+            if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access
+              {
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RENAME [%d]",i);
+                
+                Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
+                Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
+                
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id       : %d",front_end_id);
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id         : %d",context_id);
 
-              // one branch per cycle
-              can_continue[front_end_id][context_id] &= not (have_branch_current and have_branch_previous);
+                Tdepth_t   depth_min    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0;
+                Tdepth_t   depth_max    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;
+                Tcontrol_t depth_full   = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);
 
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id         : %d",front_end_id);
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id           : %d",context_id);
-           // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * have_event           : %d",have_event);
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * have_branch_previous : %d",have_branch_previous);
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * have_branch_current  : %d",have_branch_current );
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * can_continue         : %d",can_continue[front_end_id][context_id]);
-              
-              Tgeneral_address_t num_reg_ra_log    = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register;
-              Tgeneral_address_t num_reg_rb_log    = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register;
-              Tspecial_address_t num_reg_rc_log    = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register;
-              Tgeneral_address_t num_reg_rd_log    = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register;
-              Tspecial_address_t num_reg_re_log    = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register;
-              
-              Tgeneral_address_t num_reg_ra_phy    = rat_gpr_speculative[front_end_id][context_id][num_reg_ra_log];
-              Tgeneral_address_t num_reg_rb_phy    = rat_gpr_speculative[front_end_id][context_id][num_reg_rb_log];
-              Tspecial_address_t num_reg_rc_phy    = rat_spr_speculative[front_end_id][context_id][num_reg_rc_log];
-              Tgeneral_address_t num_reg_rd_phy_old= rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log];
-              Tspecial_address_t num_reg_re_phy_old= rat_spr_speculative[front_end_id][context_id][num_reg_re_log];
-              
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_ra           : %d -> %d",num_reg_ra_log,num_reg_ra_phy    );
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rb           : %d -> %d",num_reg_rb_log,num_reg_rb_phy    );
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rc           : %d -> %d",num_reg_rc_log,num_reg_rc_phy    );
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd           : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old);
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re           : %d -> %d",num_reg_re_log,num_reg_re_phy_old);
-              
-              internal_RENAME_ACK [i] = can_continue[front_end_id][context_id];
-              PORT_WRITE(out_RENAME_ACK                [i],internal_RENAME_ACK [i]);
-              PORT_WRITE(out_RENAME_NUM_REG_RA_PHY     [i], num_reg_ra_phy    );
-              PORT_WRITE(out_RENAME_NUM_REG_RB_PHY     [i], num_reg_rb_phy    );
-              PORT_WRITE(out_RENAME_NUM_REG_RC_PHY     [i], num_reg_rc_phy    );
-              PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old);
-              PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old);
+                Tdepth_t   depth        = (_param->_have_port_depth       )?PORT_READ(in_RENAME_DEPTH        [i]):0;
+                // Tcontrol_t save_rat     = PORT_READ(in_RENAME_SAVE_RAT [i]);
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * depth/min/max/full : %d - [%d:%d] - %d",depth,depth_min,depth_max,depth_full);
+                // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * save_rat (new)     : %d",save_rat);
+                // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * save_rat (old)     : %d",reg_save_rat [front_end_id][context_id]);
+                
+                // if (reg_save_rat [front_end_id][context_id])
+                //   {
+                //     for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_general_register_logic; num_reg_log++)
+                //       rat_gpr_speculative_valid [front_end_id][context_id][depth][num_reg_log] = false;
+                //     for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_special_register_logic; num_reg_log++)
+                //       rat_spr_speculative_valid [front_end_id][context_id][depth][num_reg_log] = false;
+                //   }
+                
+                // reg_save_rat[front_end_id][context_id] = save_rat;
+                
+                Tgeneral_address_t num_reg_ra_log    = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register;
+                Tgeneral_address_t num_reg_rb_log    = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register;
+                Tspecial_address_t num_reg_rc_log    = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register;
+                Tgeneral_address_t num_reg_rd_log    = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register;
+                Tspecial_address_t num_reg_re_log    = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register;
+                
+                Tgeneral_address_t num_reg_ra_phy    ;
+                Tgeneral_address_t num_reg_rb_phy    ;
+                Tspecial_address_t num_reg_rc_phy    ;
+                Tgeneral_address_t num_reg_rd_phy_old;
+                Tspecial_address_t num_reg_re_phy_old;
+                        
+                bool find_ra = false;
+                bool find_rb = false;
+                bool find_rc = false;
+                bool find_rd = false;
+                bool find_re = false;
+                
+                for (uint32_t num_branch=0; num_branch<_param->_nb_branch_speculated[front_end_id][context_id]; ++num_branch)
+                  {
+                    uint32_t index = (depth-num_branch)%_param->_nb_branch_speculated[front_end_id][context_id];
 
-              internal_RENAME_SAVE [i] = have_branch_current;
+                    if (not find_ra and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_ra_log])
+                      {
+                        find_ra            = true;
+                        num_reg_ra_phy     = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_ra_log];
+                      }
+                    
+                    if (not find_rb and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_rb_log])
+                      {
+                        find_rb            = true;
+                        num_reg_rb_phy     = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rb_log];
+                      }
+                    
+                    if (not find_rc and rat_spr_speculative_valid [front_end_id][context_id][index][num_reg_rc_log])
+                      {
+                        find_rc            = true;
+                        num_reg_rc_phy     = RAT_SPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rc_log];
+                      }
+                    
+                    if (not find_rd and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_rd_log])
+                      {
+                        find_rd            = true;
+                        num_reg_rd_phy_old = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rd_log];
+                      }
+                    
+                    if (not find_re and rat_spr_speculative_valid [front_end_id][context_id][index][num_reg_re_log])
+                      {
+                        find_re            = true;
+                        num_reg_re_phy_old = RAT_SPR_SPECULATIVE[front_end_id][context_id][index][num_reg_re_log];
+                      }
 
-              // save info to the next instruction
-              have_branch_previous |= have_branch_current;
-            }
+                    // if index == depth_min, stop because depth_min is the not speculative.
+                    // if (index == depth_min)
+                    //   break;
+                  }
+                
+                if (not find_ra)
+                  num_reg_ra_phy     = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_ra_log];
+                if (not find_rb)
+                  num_reg_rb_phy     = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rb_log];
+                if (not find_rc)
+                  num_reg_rc_phy     = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rc_log];
+                if (not find_rd)
+                  num_reg_rd_phy_old = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rd_log];
+                if (not find_re)
+                  num_reg_re_phy_old = RAT_SPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_re_log];
+                
+                // if rat_SPECULATIVE is valid, 
+                // then read rat_SPECULATIVE have the most valid alias register
+                // else, they have an previous event, the rat_NOT_SPECULATIVE have the valid register
+                
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_ra         : %d -> %d",num_reg_ra_log,num_reg_ra_phy    );
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rb         : %d -> %d",num_reg_rb_log,num_reg_rb_phy    );
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rc         : %d -> %d",num_reg_rc_log,num_reg_rc_phy    );
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd         : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old);
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re         : %d -> %d",num_reg_re_log,num_reg_re_phy_old);
+                
+                PORT_WRITE(out_RENAME_NUM_REG_RA_PHY     [i], num_reg_ra_phy    );
+                PORT_WRITE(out_RENAME_NUM_REG_RB_PHY     [i], num_reg_rb_phy    );
+                PORT_WRITE(out_RENAME_NUM_REG_RC_PHY     [i], num_reg_rc_phy    );
+                PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old);
+                PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old);
+              }
+          }
       }
-    
+
     log_end(Register_Address_Translation_unit,FUNCTION);
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_transition.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_transition.cpp	(revision 145)
@@ -34,11 +34,30 @@
 	  for (uint32_t j=0; j<_param->_nb_context[i]; j++)
 	    {
-              rat_depth                 [i][j]    = 0;
-              rat_gpr_speculative       [i][j][0] = 0;
+	      RAT_GPR_NOT_SPECULATIVE   [i][j][0]    = 0;
+              RAT_GPR_SPECULATIVE_VALID [i][j][0][0] = false;
+              RAT_GPR_SPECULATIVE       [i][j][0][0] = 0    ; // not necessary
 
 	      for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
-                rat_gpr_speculative        [i][j][k] = gpr++;
+                {
+                  RAT_GPR_NOT_SPECULATIVE    [i][j][k]    = gpr++;
+                  for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
+                    {
+                      RAT_GPR_SPECULATIVE_VALID  [i][j][l][k] = false;
+                      RAT_GPR_SPECULATIVE        [i][j][l][k] = 0    ; // not necessary
+                    }
+                }
 	      for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
-                rat_spr_speculative        [i][j][k] = spr++; // not necessary
+                {
+                  RAT_SPR_NOT_SPECULATIVE    [i][j][k]    = spr++;
+                  for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
+                    {
+                      RAT_SPR_SPECULATIVE_VALID  [i][j][l][k] = false;
+                      RAT_SPR_SPECULATIVE        [i][j][l][k] = 0    ; // not necessary
+                    }
+                }
+
+              for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+                reg_RAT_USE [i][j][k] = false;
+              reg_SAVE_RAT [i][j] = false;
 	    }
       }
@@ -46,4 +65,9 @@
       {
 	// Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0)
+        bool free_rat [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated];
+	for (uint32_t i=0; i<_param->_nb_front_end; i++)
+	  for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+            for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+              free_rat [i][j][k] = false;
 
 	// =====================================================
@@ -55,48 +79,60 @@
               {
                 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RETIRE_EVENT [%d][%d]",i,j);
+
+                // Test if event have just occure
+                //   * if exception -> reset valid table (rat_NOT_SPECULATIVE have the good value)
                 
-                // Test if event have just occure
                 if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)
-                  {
-                    switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j]))
+                  switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j]))
+                    {
+                    case EVENT_TYPE_BRANCH_MISS_SPECULATION :
                       {
-                      case EVENT_TYPE_BRANCH_MISS_SPECULATION :
-                      case EVENT_TYPE_LOAD_MISS_SPECULATION   :
-                        {
-                          // Miss speculation (branch or load)
-                          // Restore contexte and update depth
-
-                          log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * MISS_SPECULATION : Restore RAT");
-
-                          Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH [i][j]):0;
-
-                          log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth : %d",depth);
-                          
-                          // restore GPR
-                          for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++)
-                            rat_gpr_speculative [i][j][num_gpr] = rat_gpr_save [i][j][depth][num_gpr];
-                          
-                          // restore SPR
-                          for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++)
-                            rat_spr_speculative [i][j][num_spr] = rat_spr_save [i][j][depth][num_spr];
-                          
-                          // update rat_depth
-                          rat_depth[i][j] = depth;
-                          
-                          break;
-                        }
-                        // case EVENT_TYPE_EXCEPTION               :
-                        // case EVENT_TYPE_SPR_ACCESS              :
-                        // case EVENT_TYPE_MSYNC                   :
-                        // case EVENT_TYPE_PSYNC                   :
-                        // case EVENT_TYPE_CSYNC                   :
-                      default :
-                        {
-                          // nothing
-                          break;
-                        }
+                        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * BRANCH_MISS_SPECULATION - Reset Update Table");
+
+                        reg_SAVE_RAT [i][j] = true;
+                        
+                        Tdepth_t   depth      = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH[i][j]):0;
+                        Tdepth_t   depth_min  = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0;
+                        Tdepth_t   depth_max  = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0;
+                        Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]);
+                        
+                        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth      : %d",depth);
+                        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth_min  : %d",depth_min);
+                        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth_max  : %d",depth_max);
+                        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth_full : %d",depth_full);
+
+                        Tdepth_t   it        = depth_min;
+                        
+                        for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+                          {
+                            it = (it-1)%_param->_nb_branch_speculated[i][j];
+
+                            if (it == depth)
+                              break;
+                            
+                            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"        * flush    : %d",it);
+                            
+                            free_rat[i][j][it] = true;
+                          }
+                        
+                        break;
                       }
-                  
-                  }
+                    case EVENT_TYPE_EXCEPTION :
+                      {
+                        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * EXCEPTION - Reset Update Table");
+                        
+                        reg_SAVE_RAT [i][j] = true;
+
+                        // Reset validity table
+                        for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+                          free_rat [i][j][k] = true;
+                        
+                        break;
+                      }
+                    default :
+                      {
+                        break;
+                      }
+                    }
               }
 
@@ -114,15 +150,36 @@
 	      Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
 	      Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
-              Tcontrol_t save         = internal_RENAME_SAVE [i];
+              Tcontrol_t write_rd     = PORT_READ(in_INSERT_WRITE_RD [i]);
+              Tcontrol_t write_re     = PORT_READ(in_INSERT_WRITE_RE [i]);
+              Tdepth_t   depth        = (_param->_have_port_depth       )?PORT_READ(in_RENAME_DEPTH        [i]):0;
+              Tcontrol_t save_rat     = reg_SAVE_RAT[front_end_id][context_id];
+              // TODO SAVE_RAT
 
               log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end          : %d",front_end_id);
               log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context            : %d",context_id);
-              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * save               : %d",save);
-
-	      // Test if write and modifie RAT (RD and RE)
-
-              Tcontrol_t write_rd     = PORT_READ(in_INSERT_WRITE_RD [i]);
-              Tcontrol_t write_re     = PORT_READ(in_INSERT_WRITE_RE [i]);
-
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * depth              : %d",depth);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * save_rat (old)     : %d",save_rat);
+
+              if (save_rat)
+                {
+// #ifdef DEBUG_TEST
+//                   if (reg_RAT_USE[front_end_id][context_id][depth])
+//                     throw ERRORMORPHEO(FUNCTION,toString(_("Invalid RAT and need save_rat (%d).\n"),depth));
+// #endif
+                  reg_RAT_USE[front_end_id][context_id][depth] = true;
+                  
+                  // new branch, new RAT
+                  for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_general_register_logic; num_reg_log++)
+                    RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false;
+                  for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_special_register_logic; num_reg_log++)
+                    RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false;
+                }
+
+              save_rat = PORT_READ(in_RENAME_SAVE_RAT [i]);
+              reg_SAVE_RAT[front_end_id][context_id] = save_rat;
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * save_rat (new)     : %d",save_rat);
+	      
+	      // Test if write and modifie RAT
               log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_rd           : %d",write_rd);
 	      if (write_rd == 1)
@@ -134,5 +191,6 @@
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy     : %d",num_reg_rd_phy);
 
-                  rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy;
+                  RAT_GPR_SPECULATIVE       [front_end_id][context_id][depth][num_reg_rd_log] = num_reg_rd_phy;
+                  RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_rd_log] = true;
                 }
 
@@ -146,30 +204,6 @@
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy     : %d",num_reg_re_phy);
 
-                  rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy;
-                }
-
-              if (save)
-                {
-                  // Need save RAT
-
-                  Tdepth_t depth = (_param->_have_port_depth       )?PORT_READ(in_RENAME_DEPTH        [i]):0;
-
-                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth old - new  : %d",depth);
-
-// #ifdef DEBUG_TEST
-//                   if (depth != ((depth_old+1)%_param->_nb_branch_speculated[front_end_id][context_id]))
-//                     throw ERRORMORPHEO(FUNCTION,toString(_("Rename : Invalid depth (old : %d, new : %d).\n"),depth_old,depth));
-// #endif
-
-                  // save GPR
-                  for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++)
-                    rat_gpr_save [front_end_id][context_id][depth][num_gpr] = rat_gpr_speculative [front_end_id][context_id][num_gpr];
-
-                  // save SPR
-                  for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++)
-                    rat_spr_save [front_end_id][context_id][depth][num_spr] = rat_spr_speculative [front_end_id][context_id][num_spr];
-
-                  // update rat_depth with new depth
-                  rat_depth[front_end_id][context_id] = depth;
+                  RAT_SPR_SPECULATIVE       [front_end_id][context_id][depth][num_reg_re_log] = num_reg_re_phy;
+                  RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_re_log] = true;
                 }
 	    }
@@ -179,19 +213,13 @@
 	// =====================================================
 	// Second : interface retire
-	//  (because if an event on the same thread : the instruction is already renamed)
-	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
-	  if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i])
-	    {
+	// if event AND event is exception, restore rat_NOT_SPECULATIVE
+
+        for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+          if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i])
+            {
               log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RETIRE [%d]",i);
 
-	      // if no event : no effect, because the RAT content the most recently register
-	      // but if they have a event (exception or miss speculation), the rat must restore the oldest value
-	      // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register
-	      // the retire interface became of the Re Order Buffer, also is in program sequence !
-
-#ifdef DEBUG
               Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
               Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RETIRE_CONTEXT_ID   [i]):0;
-#endif
               Tcontrol_t write_rd     = PORT_READ(in_RETIRE_WRITE_RD [i]);
               Tcontrol_t write_re     = PORT_READ(in_RETIRE_WRITE_RE [i]);
@@ -206,7 +234,5 @@
               if (write_rd == 1)
                 {
-#ifdef DEBUG
                   Tgeneral_address_t num_reg_rd_log     = PORT_READ(in_RETIRE_NUM_REG_RD_LOG     [i]);
-#endif
 
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_log     : %d",num_reg_rd_log    );
@@ -214,10 +240,9 @@
                   if (not restore)
                     {
-#ifdef DEBUG
                   Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]);
-#endif
+
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy_new : %d",num_reg_rd_phy_new);
 
-                  // rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
+                  RAT_GPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
                     }
                 }
@@ -226,23 +251,81 @@
               if (write_re == 1)
                 {
-#ifdef DEBUG
                   Tspecial_address_t num_reg_re_log     = PORT_READ(in_RETIRE_NUM_REG_RE_LOG     [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_log     : %d",num_reg_re_log    );
+
+                  if (not restore)
+                    {
+                  Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy_new : %d",num_reg_re_phy_new);
+
+                  RAT_SPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
+                    }
+                }
+            }
+
+	// =====================================================
+	// ====[ DEPTH ]========================================
+	// =====================================================
+#if 1
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            {
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * DEPTH[%d][%d]",i,j);
+
+              Tdepth_t   depth_min  = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0;
+              Tdepth_t   depth_max  = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0;
+              Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]);
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * depth_min  : %d",depth_min);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * depth_max  : %d",depth_max);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * depth_full : %d",depth_full);
+              
+              if (not depth_full)
+                {
+                  Tdepth_t depth     = depth_max;
+
+                  for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+                    {
+                      if (depth == depth_min)
+                        break;
+
+                      if (reg_RAT_USE[i][j][depth])
+                        {
+                          log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * flush    : %d",depth);
+                  
+                          free_rat [i][j][depth] = true;
+                          // reg_RAT_USE[i][j][depth] = false;
+
+                          // for (uint32_t l=0; l<_param->_nb_general_register_logic; l++)
+                          //   RAT_GPR_SPECULATIVE_VALID  [i][j][depth][l] = false;
+                          // for (uint32_t l=0; l<_param->_nb_special_register_logic; l++)
+                          //   RAT_SPR_SPECULATIVE_VALID  [i][j][depth][l] = false;
+                        }
+
+                      depth = (depth+1)%_param->_nb_branch_speculated[i][j];
+                    }
+                }
+            }
 #endif
-
-                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_log     : %d",num_reg_re_log    );
-
-                  if (not restore)
-                    {
-#ifdef DEBUG
-                  Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);
-#endif
-
-                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy_new : %d",num_reg_re_phy_new);
-
-                  // rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
-                    }
-                }
-
-	    }
+	// =====================================================
+	// ====[ FREE RAT ]=====================================
+	// =====================================================
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+              if (free_rat[i][j][k])
+                {
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * Free RAT : [%d][%d][%d]",i,j,k);
+                  
+                  reg_RAT_USE[i][j][k] = false;
+                  
+                  for (uint32_t l=0; l<_param->_nb_general_register_logic; l++)
+                    RAT_GPR_SPECULATIVE_VALID  [i][j][k][l] = false;
+                  for (uint32_t l=0; l<_param->_nb_special_register_logic; l++)
+                    RAT_SPR_SPECULATIVE_VALID  [i][j][k][l] = false;
+                }
+
       }
 
@@ -255,36 +338,40 @@
         for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
           {
-            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end[%d].context[%d] - rat_depth : %d",i,j,rat_depth[i][j]);
-          
-            for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
+            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end[%d].context[%d] - SAVE_RAT : %d",i,j,reg_SAVE_RAT[i][j]);
+              
+            for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit)
               {
                 std::string str = "";
                 for (uint32_t x=0; x<limit; x++)
                   {
-                    uint32_t index = k+x;
+                    uint32_t index = l+x;
                     if (index >= _param->_nb_general_register_logic)
                       break;
                     else
-                      str+=toString("GPR[%.4d] - %.5d | ",index,rat_gpr_speculative [i][j][index]);
+                      str+=toString("GPR[%.4d]       -   %.5d | ",index,RAT_GPR_NOT_SPECULATIVE [i][j][index]);
                   }
                 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
               }
 
-            for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
-              for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
-                {
-                  std::string str = "";
-                  for (uint32_t x=0; x<limit; x++)
-                    {
-                      uint32_t index = k+x;
-                      if (index >= _param->_nb_general_register_logic)
-                        break;
-                      else
-                        str+=toString("GPR_%d[%.4d] - %.5d | ",l,index,rat_gpr_save [i][j][l][index]);
-                    }
-                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
-                }
-            
-            for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
+            for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+              {
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * GPR      [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]);
+
+                for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit)
+                  {
+                    std::string str = "";
+                    for (uint32_t x=0; x<limit; x++)
+                      {
+                        uint32_t index = l+x;
+                        if (index >= _param->_nb_general_register_logic)
+                          break;
+                        else
+                          str+=toString("GPR[%.4d][%.4d] - %.1d %.5d | ",index,k,RAT_GPR_SPECULATIVE_VALID [i][j][k][index],RAT_GPR_SPECULATIVE [i][j][k][index]);
+                      }
+                    log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
+                  }
+              }
+
+            for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit)
               {
                 std::string str = "";
@@ -292,28 +379,33 @@
                 for (uint32_t x=0; x<limit; x++)
                   {
-                    uint32_t index = k+x;
+                    uint32_t index = l+x;
                     if (index >= _param->_nb_special_register_logic)
                       break;
                     else
-                      str+=toString("SPR[%.4d] - %.5d | ",index,rat_spr_speculative [i][j][index]);
+                      str+=toString("SPR[%.4d]       -   %.5d | ",index,RAT_SPR_NOT_SPECULATIVE [i][j][index]);
                   }
                 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
               }
 
-            for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
-              for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
-                {
-                  std::string str = "";
-                  for (uint32_t x=0; x<limit; x++)
-                    {
-                      uint32_t index = k+x;
-                      if (index >= _param->_nb_special_register_logic)
-                        break;
-                      else
-                        str+=toString("SPR_%d[%.4d] - %.5d | ",l,index,rat_spr_save [i][j][l][index]);
-                    }
-                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
-                }
-
+      
+            for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
+              {
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * SPR      [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]);
+                
+                for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit)
+                  {
+                    std::string str = "";
+                    
+                    for (uint32_t x=0; x<limit; x++)
+                      {
+                        uint32_t index = l+x;
+                        if (index >= _param->_nb_special_register_logic)
+                          break;
+                        else
+                          str+=toString("SPR[%.4d][%.4d] - %.1d %.5d | ",index,k,RAT_SPR_SPECULATIVE_VALID [i][j][k][index],RAT_SPR_SPECULATIVE [i][j][k][index]);
+                      }
+                    log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
+                  }
+              }
           }
     }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_genMealy_rename.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_genMealy_rename.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_genMealy_rename.cpp	(revision 145)
@@ -52,9 +52,9 @@
         // else, they have an previous event, the rat_not_speculative have the valid register
 
-        Tgeneral_address_t num_reg_ra_phy    = (rat_gpr_speculative_valid[front_end_id][context_id][num_reg_ra_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_ra_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_ra_log];
-        Tgeneral_address_t num_reg_rb_phy    = (rat_gpr_speculative_valid[front_end_id][context_id][num_reg_rb_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_rb_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_rb_log];
-        Tspecial_address_t num_reg_rc_phy    = (rat_spr_speculative_valid[front_end_id][context_id][num_reg_rc_log] and not have_event)?rat_spr_speculative[front_end_id][context_id][num_reg_rc_log]:rat_spr_not_speculative[front_end_id][context_id][num_reg_rc_log];
-        Tgeneral_address_t num_reg_rd_phy_old= (rat_gpr_speculative_valid[front_end_id][context_id][num_reg_rd_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_rd_log];
-        Tspecial_address_t num_reg_re_phy_old= (rat_spr_speculative_valid[front_end_id][context_id][num_reg_re_log] and not have_event)?rat_spr_speculative[front_end_id][context_id][num_reg_re_log]:rat_spr_not_speculative[front_end_id][context_id][num_reg_re_log];
+        Tgeneral_address_t num_reg_ra_phy    = (RAT_GPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_ra_log] and not have_event)?RAT_GPR_SPECULATIVE[front_end_id][context_id][0][num_reg_ra_log]:RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_ra_log];
+        Tgeneral_address_t num_reg_rb_phy    = (RAT_GPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_rb_log] and not have_event)?RAT_GPR_SPECULATIVE[front_end_id][context_id][0][num_reg_rb_log]:RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rb_log];
+        Tspecial_address_t num_reg_rc_phy    = (RAT_SPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_rc_log] and not have_event)?RAT_SPR_SPECULATIVE[front_end_id][context_id][0][num_reg_rc_log]:RAT_SPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rc_log];
+        Tgeneral_address_t num_reg_rd_phy_old= (RAT_GPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_rd_log] and not have_event)?RAT_GPR_SPECULATIVE[front_end_id][context_id][0][num_reg_rd_log]:RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rd_log];
+        Tspecial_address_t num_reg_re_phy_old= (RAT_SPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_re_log] and not have_event)?RAT_SPR_SPECULATIVE[front_end_id][context_id][0][num_reg_re_log]:RAT_SPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_re_log];
 
         log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_ra         : %d -> %d",num_reg_ra_log,num_reg_ra_phy    );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_transition.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_transition.cpp	(revision 145)
@@ -34,19 +34,19 @@
 	  for (uint32_t j=0; j<_param->_nb_context[i]; j++)
 	    {
-	      rat_gpr_not_speculative   [i][j][0] = 0;
-              rat_gpr_speculative_valid [i][j][0] = false;
-              rat_gpr_speculative       [i][j][0] = 0    ; // not necessary
+	      RAT_GPR_NOT_SPECULATIVE   [i][j][0]    = 0;
+              RAT_GPR_SPECULATIVE_VALID [i][j][0][0] = false;
+              RAT_GPR_SPECULATIVE       [i][j][0][0] = 0    ; // not necessary
 
 	      for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
                 {
-                  rat_gpr_not_speculative    [i][j][k] = gpr++;
-                  rat_gpr_speculative_valid  [i][j][k] = false;
-                  rat_gpr_speculative        [i][j][k] = 0    ; // not necessary
+                  RAT_GPR_NOT_SPECULATIVE    [i][j][k]    = gpr++;
+                  RAT_GPR_SPECULATIVE_VALID  [i][j][0][k] = false;
+                  RAT_GPR_SPECULATIVE        [i][j][0][k] = 0    ; // not necessary
                 }
 	      for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
                 {
-                  rat_spr_not_speculative    [i][j][k] = spr++;
-                  rat_spr_speculative_valid  [i][j][k] = false;
-                  rat_spr_speculative        [i][j][k] = 0    ; // not necessary
+                  RAT_SPR_NOT_SPECULATIVE    [i][j][k]    = spr++;
+                  RAT_SPR_SPECULATIVE_VALID  [i][j][0][k] = false;
+                  RAT_SPR_SPECULATIVE        [i][j][0][k] = 0    ; // not necessary
                 }
 	    }
@@ -69,7 +69,7 @@
                   // Reset validity table
                   for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
-                    rat_gpr_speculative_valid [i][j][k] = false;
+                    RAT_GPR_SPECULATIVE_VALID [i][j][0][k] = false;
                   for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
-                    rat_spr_speculative_valid [i][j][k] = false;
+                    RAT_SPR_SPECULATIVE_VALID [i][j][0][k] = false;
                 }
 
@@ -103,6 +103,6 @@
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy     : %d",num_reg_rd_phy);
 
-                  rat_gpr_speculative       [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy;
-                  rat_gpr_speculative_valid [front_end_id][context_id][num_reg_rd_log] = true;
+                  RAT_GPR_SPECULATIVE       [front_end_id][context_id][0][num_reg_rd_log] = num_reg_rd_phy;
+                  RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][0][num_reg_rd_log] = true;
                 }
 
@@ -116,6 +116,6 @@
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy     : %d",num_reg_re_phy);
 
-                  rat_spr_speculative       [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy;
-                  rat_spr_speculative_valid [front_end_id][context_id][num_reg_re_log] = true;
+                  RAT_SPR_SPECULATIVE       [front_end_id][context_id][0][num_reg_re_log] = num_reg_re_phy;
+                  RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][0][num_reg_re_log] = true;
                 }
 	    }
@@ -160,5 +160,5 @@
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy_new : %d",num_reg_rd_phy_new);
 
-                  rat_gpr_not_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
+                  RAT_GPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
                     }
                 }
@@ -177,5 +177,5 @@
                   log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy_new : %d",num_reg_re_phy_new);
 
-                  rat_spr_not_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
+                  RAT_SPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
                     }
                 }
@@ -203,5 +203,5 @@
                       break;
                     else
-                      str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) | ",index,rat_gpr_speculative_valid [i][j][index],rat_gpr_speculative [i][j][index],rat_gpr_not_speculative [i][j][index]);
+                      str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) | ",index,RAT_GPR_SPECULATIVE_VALID [i][j][0][index],RAT_GPR_SPECULATIVE [i][j][0][index],RAT_GPR_NOT_SPECULATIVE [i][j][index]);
                   }
                 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
@@ -218,5 +218,5 @@
                       break;
                     else
-                      str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) | ",index,rat_spr_speculative_valid [i][j][index],rat_spr_speculative [i][j][index],rat_spr_not_speculative [i][j][index]);
+                      str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) | ",index,RAT_SPR_SPECULATIVE_VALID [i][j][0][index],RAT_SPR_SPECULATIVE [i][j][0][index],RAT_SPR_NOT_SPECULATIVE [i][j][index]);
                   }
                 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
@@ -235,10 +235,10 @@
               for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y)
                 {
-                  if (rat_gpr_speculative_valid [i][j][x] and
-                      rat_gpr_speculative_valid [i][j][y] and
-                      (rat_gpr_speculative[i][j][x] == rat_gpr_speculative[i][j][y]))
-                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_speculative[%d][%d][%d] == rat_gpr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_speculative[i][j][x]));
-                  if (rat_gpr_not_speculative[i][j][x] == rat_gpr_not_speculative[i][j][y])
-                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_not_speculative[%d][%d][%d] == rat_gpr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_not_speculative[i][j][x]));
+                  if (RAT_GPR_SPECULATIVE_VALID [i][j][0][x] and
+                      RAT_GPR_SPECULATIVE_VALID [i][j][0][y] and
+                      (RAT_GPR_SPECULATIVE[i][j][0][x] == RAT_GPR_SPECULATIVE[i][j][0][y]))
+                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_GPR_SPECULATIVE[%d][%d][0][%d] == RAT_GPR_SPECULATIVE[%d][%d][0][%d] == %d"),i,j,x,i,j,y,RAT_GPR_SPECULATIVE[i][j][0][x]));
+                  if (RAT_GPR_NOT_SPECULATIVE[i][j][x] == RAT_GPR_NOT_SPECULATIVE[i][j][y])
+                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_GPR_NOT_SPECULATIVE[%d][%d][%d] == RAT_GPR_NOT_SPECULATIVE[%d][%d][%d] == %d"),i,j,x,i,j,y,RAT_GPR_NOT_SPECULATIVE[i][j][x]));
                   
                 }
@@ -246,10 +246,10 @@
               for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y)
                 {
-                  if(rat_spr_speculative_valid [i][j][x] and
-                     rat_spr_speculative_valid [i][j][y] and
-                     (rat_spr_speculative[i][j][x] == rat_spr_speculative[i][j][y]))
-                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_speculative[%d][%d][%d] == rat_spr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_speculative[i][j][x]));
-                  if (rat_spr_not_speculative[i][j][x] == rat_spr_not_speculative[i][j][y])
-                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_not_speculative[%d][%d][%d] == rat_spr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_not_speculative[i][j][x]));
+                  if(RAT_SPR_SPECULATIVE_VALID [i][j][0][x] and
+                     RAT_SPR_SPECULATIVE_VALID [i][j][0][y] and
+                     (RAT_SPR_SPECULATIVE[i][j][0][x] == RAT_SPR_SPECULATIVE[i][j][0][y]))
+                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_SPR_SPECULATIVE[%d][%d][0][%d] == RAT_SPR_SPECULATIVE[%d][%d][0][%d] == %d"),i,j,x,i,j,y,RAT_SPR_SPECULATIVE[i][j][0][x]));
+                  if (RAT_SPR_NOT_SPECULATIVE[i][j][x] == RAT_SPR_NOT_SPECULATIVE[i][j][y])
+                    throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_SPR_NOT_SPECULATIVE[%d][%d][%d] == RAT_SPR_NOT_SPECULATIVE[%d][%d][%d] == %d"),i,j,x,i,j,y,RAT_SPR_NOT_SPECULATIVE[i][j][x]));
                   
                 }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_constant.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_constant.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_constant.cpp	(revision 145)
@@ -0,0 +1,63 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_ooo_engine {
+namespace ooo_engine {
+namespace rename_unit {
+namespace register_translation_unit {
+namespace register_address_translation_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Register_Address_Translation_unit::function_depth_save_constant"
+  void Register_Address_Translation_unit::function_depth_save_constant (void)
+  {
+    log_begin(Register_Address_Translation_unit,FUNCTION);
+    log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
+
+    // Constant : accepted already transaction
+    for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+      {
+        internal_INSERT_ACK [i] = 1;
+        
+        PORT_WRITE(out_INSERT_ACK[i],internal_INSERT_ACK [i]);
+      }
+    
+    for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+      {
+        internal_RETIRE_ACK [i] = 1;
+        
+        PORT_WRITE(out_RETIRE_ACK[i],internal_RETIRE_ACK [i]);
+      }
+    
+    for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+      for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+        {
+          internal_RETIRE_EVENT_ACK [i][j] = 1;
+          
+          PORT_WRITE(out_RETIRE_EVENT_ACK[i][j],internal_RETIRE_EVENT_ACK [i][j]);
+        }
+    
+    log_end(Register_Address_Translation_unit,FUNCTION);
+  };
+
+}; // end namespace register_address_translation_unit
+}; // end namespace register_translation_unit
+}; // end namespace rename_unit
+}; // end namespace ooo_engine
+}; // end namespace multi_ooo_engine
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp	(revision 145)
@@ -0,0 +1,104 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_ooo_engine {
+namespace ooo_engine {
+namespace rename_unit {
+namespace register_translation_unit {
+namespace register_address_translation_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Register_Address_Translation_unit::function_depth_save_genMealy_rename"
+  void Register_Address_Translation_unit::function_depth_save_genMealy_rename (void)
+  {
+    log_begin(Register_Address_Translation_unit,FUNCTION);
+    log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET) != 0)
+      {
+        bool     have_branch_previous = false;
+        bool     can_continue [_param->_nb_front_end][_param->_max_nb_context];
+
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            can_continue [i][j] = true;
+
+        for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+          if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access
+            {
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RENAME [%d]",i);
+              
+              Tcontext_t front_end_id        = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
+              Tcontext_t context_id          = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
+              // bool       have_event          = (PORT_READ(in_RETIRE_EVENT_VAL [front_end_id][context_id]) and // always ack
+              //                                   (PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) == EVENT_STATE_EVENT));
+              
+              bool       have_branch_current = PORT_READ(in_RENAME_SAVE_RAT [i]);
+
+              // one branch per cycle
+              can_continue[front_end_id][context_id] &= not (have_branch_current and have_branch_previous);
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id         : %d",front_end_id);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id           : %d",context_id);
+           // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * have_event           : %d",have_event);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * have_branch_previous : %d",have_branch_previous);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * have_branch_current  : %d",have_branch_current );
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * can_continue         : %d",can_continue[front_end_id][context_id]);
+              
+              Tgeneral_address_t num_reg_ra_log    = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register;
+              Tgeneral_address_t num_reg_rb_log    = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register;
+              Tspecial_address_t num_reg_rc_log    = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register;
+              Tgeneral_address_t num_reg_rd_log    = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register;
+              Tspecial_address_t num_reg_re_log    = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register;
+              
+              Tgeneral_address_t num_reg_ra_phy    = rat_gpr_speculative[front_end_id][context_id][num_reg_ra_log];
+              Tgeneral_address_t num_reg_rb_phy    = rat_gpr_speculative[front_end_id][context_id][num_reg_rb_log];
+              Tspecial_address_t num_reg_rc_phy    = rat_spr_speculative[front_end_id][context_id][num_reg_rc_log];
+              Tgeneral_address_t num_reg_rd_phy_old= rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log];
+              Tspecial_address_t num_reg_re_phy_old= rat_spr_speculative[front_end_id][context_id][num_reg_re_log];
+              
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_ra           : %d -> %d",num_reg_ra_log,num_reg_ra_phy    );
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rb           : %d -> %d",num_reg_rb_log,num_reg_rb_phy    );
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rc           : %d -> %d",num_reg_rc_log,num_reg_rc_phy    );
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd           : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re           : %d -> %d",num_reg_re_log,num_reg_re_phy_old);
+              
+              internal_RENAME_ACK [i] = can_continue[front_end_id][context_id];
+              PORT_WRITE(out_RENAME_ACK                [i],internal_RENAME_ACK [i]);
+              PORT_WRITE(out_RENAME_NUM_REG_RA_PHY     [i], num_reg_ra_phy    );
+              PORT_WRITE(out_RENAME_NUM_REG_RB_PHY     [i], num_reg_rb_phy    );
+              PORT_WRITE(out_RENAME_NUM_REG_RC_PHY     [i], num_reg_rc_phy    );
+              PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old);
+              PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old);
+
+              internal_RENAME_SAVE [i] = have_branch_current;
+
+              // save info to the next instruction
+              have_branch_previous |= have_branch_current;
+            }
+      }
+    
+    log_end(Register_Address_Translation_unit,FUNCTION);
+  };
+
+}; // end namespace register_address_translation_unit
+}; // end namespace register_translation_unit
+}; // end namespace rename_unit
+}; // end namespace ooo_engine
+}; // end namespace multi_ooo_engine
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_transition.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_transition.cpp	(revision 145)
@@ -0,0 +1,334 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_ooo_engine {
+namespace ooo_engine {
+namespace rename_unit {
+namespace register_translation_unit {
+namespace register_address_translation_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Register_Address_Translation_unit::function_depth_save_transition"
+  void Register_Address_Translation_unit::function_depth_save_transition (void)
+  {
+    log_begin(Register_Address_Translation_unit,FUNCTION);
+    log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET) == 0)
+      {
+	uint32_t gpr = 1;
+	uint32_t spr = 0;
+
+	for (uint32_t i=0; i<_param->_nb_front_end; i++)
+	  for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+	    {
+              rat_depth                 [i][j]    = 0;
+              rat_gpr_speculative       [i][j][0] = 0;
+
+	      for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
+                rat_gpr_speculative        [i][j][k] = gpr++;
+	      for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
+                rat_spr_speculative        [i][j][k] = spr++; // not necessary
+	    }
+      }
+    else
+      {
+	// Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0)
+
+	// =====================================================
+	// ====[ RETIRE_EVENT ]=================================
+	// =====================================================
+        for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+          for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+            if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j])
+              {
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RETIRE_EVENT [%d][%d]",i,j);
+                
+                // Test if event have just occure
+                if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)
+                  {
+                    switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j]))
+                      {
+                      case EVENT_TYPE_BRANCH_MISS_SPECULATION :
+                      case EVENT_TYPE_LOAD_MISS_SPECULATION   :
+                        {
+                          // Miss speculation (branch or load)
+                          // Restore contexte and update depth
+
+                          log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * MISS_SPECULATION : Restore RAT");
+
+                          Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH [i][j]):0;
+
+                          log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth : %d",depth);
+                          
+                          // restore GPR
+                          for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++)
+                            rat_gpr_speculative [i][j][num_gpr] = rat_gpr_save [i][j][depth][num_gpr];
+                          
+                          // restore SPR
+                          for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++)
+                            rat_spr_speculative [i][j][num_spr] = rat_spr_save [i][j][depth][num_spr];
+                          
+                          // update rat_depth
+                          rat_depth[i][j] = depth;
+                          
+                          break;
+                        }
+                        // case EVENT_TYPE_EXCEPTION               :
+                        // case EVENT_TYPE_SPR_ACCESS              :
+                        // case EVENT_TYPE_MSYNC                   :
+                        // case EVENT_TYPE_PSYNC                   :
+                        // case EVENT_TYPE_CSYNC                   :
+                      default :
+                        {
+                          // nothing
+                          break;
+                        }
+                      }
+                  
+                  }
+              }
+
+	// =====================================================
+	// ====[ INSERT ]=======================================
+	// =====================================================
+	// First : interface insert
+        // this instruction is speculative !!!
+	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+	  // Test transaction
+	  if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK  [i])
+	    {
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * INSERT [%d]",i);
+
+	      Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
+	      Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
+              Tcontrol_t save         = internal_RENAME_SAVE [i];
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end          : %d",front_end_id);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context            : %d",context_id);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * save               : %d",save);
+
+	      // Test if write and modifie RAT (RD and RE)
+
+              Tcontrol_t write_rd     = PORT_READ(in_INSERT_WRITE_RD [i]);
+              Tcontrol_t write_re     = PORT_READ(in_INSERT_WRITE_RE [i]);
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_rd           : %d",write_rd);
+	      if (write_rd == 1)
+                {
+                  Tgeneral_address_t num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [i]);
+                  Tgeneral_address_t num_reg_rd_phy = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_log     : %d",num_reg_rd_log);
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy     : %d",num_reg_rd_phy);
+
+                  rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy;
+                }
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_re           : %d",write_re);
+	      if (write_re == 1)
+                {
+                  Tspecial_address_t num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [i]);
+                  Tspecial_address_t num_reg_re_phy = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]);
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_log     : %d",num_reg_re_log);
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy     : %d",num_reg_re_phy);
+
+                  rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy;
+                }
+
+              if (save)
+                {
+                  // Need save RAT
+
+                  Tdepth_t depth = (_param->_have_port_depth       )?PORT_READ(in_RENAME_DEPTH        [i]):0;
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * depth old - new  : %d",depth);
+
+// #ifdef DEBUG_TEST
+//                   if (depth != ((depth_old+1)%_param->_nb_branch_speculated[front_end_id][context_id]))
+//                     throw ERRORMORPHEO(FUNCTION,toString(_("Rename : Invalid depth (old : %d, new : %d).\n"),depth_old,depth));
+// #endif
+
+                  // save GPR
+                  for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++)
+                    rat_gpr_save [front_end_id][context_id][depth][num_gpr] = rat_gpr_speculative [front_end_id][context_id][num_gpr];
+
+                  // save SPR
+                  for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++)
+                    rat_spr_save [front_end_id][context_id][depth][num_spr] = rat_spr_speculative [front_end_id][context_id][num_spr];
+
+                  // update rat_depth with new depth
+                  rat_depth[front_end_id][context_id] = depth;
+                }
+	    }
+
+	// =====================================================
+	// ====[ RETIRE ]=======================================
+	// =====================================================
+	// Second : interface retire
+	//  (because if an event on the same thread : the instruction is already renamed)
+	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+	  if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i])
+	    {
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RETIRE [%d]",i);
+
+	      // if no event : no effect, because the RAT content the most recently register
+	      // but if they have a event (exception or miss speculation), the rat must restore the oldest value
+	      // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register
+	      // the retire interface became of the Re Order Buffer, also is in program sequence !
+
+#ifdef DEBUG
+              Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
+              Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RETIRE_CONTEXT_ID   [i]):0;
+#endif
+              Tcontrol_t write_rd     = PORT_READ(in_RETIRE_WRITE_RD [i]);
+              Tcontrol_t write_re     = PORT_READ(in_RETIRE_WRITE_RE [i]);
+              Tcontrol_t restore      = PORT_READ(in_RETIRE_RESTORE  [i]);
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id       : %d",front_end_id);
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id         : %d",context_id  );
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * restore            : %d",restore     );
+
+              // Test if write and have not a previous update
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_rd           : %d",write_rd);
+              if (write_rd == 1)
+                {
+#ifdef DEBUG
+                  Tgeneral_address_t num_reg_rd_log     = PORT_READ(in_RETIRE_NUM_REG_RD_LOG     [i]);
+#endif
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_log     : %d",num_reg_rd_log    );
+
+                  if (not restore)
+                    {
+#ifdef DEBUG
+                  Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]);
+#endif
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd_phy_new : %d",num_reg_rd_phy_new);
+
+                  // rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
+                    }
+                }
+
+              log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * write_re           : %d",write_re);
+              if (write_re == 1)
+                {
+#ifdef DEBUG
+                  Tspecial_address_t num_reg_re_log     = PORT_READ(in_RETIRE_NUM_REG_RE_LOG     [i]);
+#endif
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_log     : %d",num_reg_re_log    );
+
+                  if (not restore)
+                    {
+#ifdef DEBUG
+                  Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);
+#endif
+
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re_phy_new : %d",num_reg_re_phy_new);
+
+                  // rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
+                    }
+                }
+
+	    }
+      }
+
+#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true)
+    {
+      uint32_t limit = 4;
+      
+      log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * Dump RAT (Register_Address_Translation_unit)");
+      for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+        for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+          {
+            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end[%d].context[%d] - rat_depth : %d",i,j,rat_depth[i][j]);
+          
+            for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
+              {
+                std::string str = "";
+                for (uint32_t x=0; x<limit; x++)
+                  {
+                    uint32_t index = k+x;
+                    if (index >= _param->_nb_general_register_logic)
+                      break;
+                    else
+                      str+=toString("GPR[%.4d] - %.5d | ",index,rat_gpr_speculative [i][j][index]);
+                  }
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
+              }
+
+            for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
+              for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
+                {
+                  std::string str = "";
+                  for (uint32_t x=0; x<limit; x++)
+                    {
+                      uint32_t index = k+x;
+                      if (index >= _param->_nb_general_register_logic)
+                        break;
+                      else
+                        str+=toString("GPR_%d[%.4d] - %.5d | ",l,index,rat_gpr_save [i][j][l][index]);
+                    }
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
+                }
+            
+            for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
+              {
+                std::string str = "";
+                
+                for (uint32_t x=0; x<limit; x++)
+                  {
+                    uint32_t index = k+x;
+                    if (index >= _param->_nb_special_register_logic)
+                      break;
+                    else
+                      str+=toString("SPR[%.4d] - %.5d | ",index,rat_spr_speculative [i][j][index]);
+                  }
+                log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
+              }
+
+            for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
+              for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
+                {
+                  std::string str = "";
+                  for (uint32_t x=0; x<limit; x++)
+                    {
+                      uint32_t index = k+x;
+                      if (index >= _param->_nb_special_register_logic)
+                        break;
+                      else
+                        str+=toString("SPR_%d[%.4d] - %.5d | ",l,index,rat_spr_save [i][j][l][index]);
+                    }
+                  log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * %s",str.c_str());
+                }
+
+          }
+    }
+#endif
+
+    log_end(Register_Address_Translation_unit,FUNCTION);
+  };
+
+}; // end namespace register_address_translation_unit
+}; // end namespace register_translation_unit
+}; // end namespace rename_unit
+}; // end namespace ooo_engine
+}; // end namespace multi_ooo_engine
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,5 +1,0 @@
-Register_translation_unit_Glue
-1	4	*2	# nb_inst_insert
-1	4	*2	# nb_inst_retire
-5  	5  	*2	# size_general_register
-2 	2 	*2	# size_special_register
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,5 @@
+Register_translation_unit_Glue
+1	4	*2	# nb_inst_insert
+1	4	*2	# nb_inst_retire
+5  	5  	*2	# size_general_register
+2 	2 	*2	# size_special_register
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Register_translation_unit
-1	1	*2	#nb_front_end       
-1	1	*2	#nb_context          [nb_front_end]
-64	64	*2	#nb_general_register
-4	4	*2	#nb_special_register
-1	1	*4	#nb_inst_insert     
-1	1	*4	#nb_inst_retire     
-1	1	*4	#nb_reg_free        
-1	1	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Register_translation_unit
-1	1	*2	#nb_front_end       
-1	1	*2	#nb_context          [nb_front_end]
-64	64	*2	#nb_general_register
-16	16	*2	#nb_special_register
-1	4	*4	#nb_inst_insert     
-1	4	*4	#nb_inst_retire     
-1	4	*4	#nb_reg_free        
-8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1a.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Register_translation_unit
-1	1	*2	#nb_front_end       
-1	1	*2	#nb_context          [nb_front_end]
-64	64	*2	#nb_general_register
-16	16	*2	#nb_special_register
-1	4	*4	#nb_inst_insert     
-1	4	*4	#nb_inst_retire     
-1	4	*4	#nb_reg_free        
-8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4a.cfg	(revision 144)
+++ 	(revision )
@@ -1,12 +1,0 @@
-Register_translation_unit
-4	4	*2	#nb_front_end       
-1	1	*2	#nb_context          [0] [nb_front_end]
-1	1	*2	#nb_context          [1] [nb_front_end]
-1	1	*2	#nb_context          [2] [nb_front_end]
-1	1	*2	#nb_context          [3] [nb_front_end]
-256	256	*2	#nb_general_register
-32	32	*2	#nb_special_register
-4	4	*4	#nb_inst_insert     
-4	4	*4	#nb_inst_retire     
-4	4	*4	#nb_reg_free        
-8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4b.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4b.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Register_translation_unit
-1	1	*2	#nb_front_end       
-4	4	*2	#nb_context          [0] [nb_front_end]
-256	256	*2	#nb_general_register
-32	32	*2	#nb_special_register
-4	4	*4	#nb_inst_insert     
-4	4	*4	#nb_inst_retire     
-4	4	*4	#nb_reg_free        
-8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4c.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4c.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Register_translation_unit
-2	2	*2	#nb_front_end       
-2	2	*2	#nb_context          [0] [nb_front_end]
-2	2	*2	#nb_context          [1] [nb_front_end]
-256	256	*2	#nb_general_register
-32	32	*2	#nb_special_register
-4	4	*4	#nb_inst_insert     
-4	4	*4	#nb_inst_retire     
-4	4	*4	#nb_reg_free        
-8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4d.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4d.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Register_translation_unit
-2	2	*2	#nb_front_end       
-1	1	*2	#nb_context          [0] [nb_front_end]
-3	3	*2	#nb_context          [1] [nb_front_end]
-256	256	*2	#nb_general_register
-32	32	*2	#nb_special_register
-4	4	*4	#nb_inst_insert     
-4	4	*4	#nb_inst_retire     
-4	4	*4	#nb_reg_free        
-8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,9 @@
+Register_translation_unit
+1	1	*2	#nb_front_end       
+1	1	*2	#nb_context          [nb_front_end]
+64	64	*2	#nb_general_register
+4	4	*2	#nb_special_register
+1	1	*4	#nb_inst_insert     
+1	1	*4	#nb_inst_retire     
+1	1	*4	#nb_reg_free        
+1	1	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_1.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_1.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_1.gen	(revision 145)
@@ -0,0 +1,9 @@
+Register_translation_unit
+1	1	*2	#nb_front_end       
+1	1	*2	#nb_context          [nb_front_end]
+64	64	*2	#nb_general_register
+16	16	*2	#nb_special_register
+1	4	*4	#nb_inst_insert     
+1	4	*4	#nb_inst_retire     
+1	4	*4	#nb_reg_free        
+8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_1a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_1a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_1a.gen	(revision 145)
@@ -0,0 +1,9 @@
+Register_translation_unit
+1	1	*2	#nb_front_end       
+1	1	*2	#nb_context          [nb_front_end]
+64	64	*2	#nb_general_register
+16	16	*2	#nb_special_register
+1	4	*4	#nb_inst_insert     
+1	4	*4	#nb_inst_retire     
+1	4	*4	#nb_reg_free        
+8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4a.gen	(revision 145)
@@ -0,0 +1,12 @@
+Register_translation_unit
+4	4	*2	#nb_front_end       
+1	1	*2	#nb_context          [0] [nb_front_end]
+1	1	*2	#nb_context          [1] [nb_front_end]
+1	1	*2	#nb_context          [2] [nb_front_end]
+1	1	*2	#nb_context          [3] [nb_front_end]
+256	256	*2	#nb_general_register
+32	32	*2	#nb_special_register
+4	4	*4	#nb_inst_insert     
+4	4	*4	#nb_inst_retire     
+4	4	*4	#nb_reg_free        
+8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4b.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4b.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4b.gen	(revision 145)
@@ -0,0 +1,9 @@
+Register_translation_unit
+1	1	*2	#nb_front_end       
+4	4	*2	#nb_context          [0] [nb_front_end]
+256	256	*2	#nb_general_register
+32	32	*2	#nb_special_register
+4	4	*4	#nb_inst_insert     
+4	4	*4	#nb_inst_retire     
+4	4	*4	#nb_reg_free        
+8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4c.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4c.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4c.gen	(revision 145)
@@ -0,0 +1,10 @@
+Register_translation_unit
+2	2	*2	#nb_front_end       
+2	2	*2	#nb_context          [0] [nb_front_end]
+2	2	*2	#nb_context          [1] [nb_front_end]
+256	256	*2	#nb_general_register
+32	32	*2	#nb_special_register
+4	4	*4	#nb_inst_insert     
+4	4	*4	#nb_inst_retire     
+4	4	*4	#nb_reg_free        
+8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4d.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4d.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration/config-thread_4d.gen	(revision 145)
@@ -0,0 +1,10 @@
+Register_translation_unit
+2	2	*2	#nb_front_end       
+1	1	*2	#nb_context          [0] [nb_front_end]
+3	3	*2	#nb_context          [1] [nb_front_end]
+256	256	*2	#nb_general_register
+32	32	*2	#nb_special_register
+4	4	*4	#nb_inst_insert     
+4	4	*4	#nb_inst_retire     
+4	4	*4	#nb_reg_free        
+8	8	*2	#nb_bank            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_mono_thread.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_mono_thread.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Stat_List_unit
-1	1	*2	#_nb_front_end          
-1	1	*2	#_nb_context            
-64	64	*2	#_nb_general_register   
-16	16	*2	#_nb_special_register   
-1	4	*2	#_nb_inst_insert        
-1	4	*2	#_nb_inst_retire        
-1	4	*2	#_nb_reg_free           
-4	4	*2	#_nb_bank               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_multi_thread.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_multi_thread.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Stat_List_unit
-2	2	*2	#_nb_front_end          
-1	3	+1	#_nb_context            [0]
-2	2	*2	#_nb_context            [1]
-256	256	*2	#_nb_general_register   
-64	64	*2	#_nb_special_register   
-4	4	*2	#_nb_inst_insert        
-4	4	*2	#_nb_inst_retire        
-4	4	*2	#_nb_reg_free           
-4	8	*2	#_nb_bank               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/configuration/config_mono_thread.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/configuration/config_mono_thread.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/configuration/config_mono_thread.gen	(revision 145)
@@ -0,0 +1,9 @@
+Stat_List_unit
+1	1	*2	#_nb_front_end          
+1	1	*2	#_nb_context            
+64	64	*2	#_nb_general_register   
+16	16	*2	#_nb_special_register   
+1	4	*2	#_nb_inst_insert        
+1	4	*2	#_nb_inst_retire        
+1	4	*2	#_nb_reg_free           
+4	4	*2	#_nb_bank               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/configuration/config_multi_thread.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/configuration/config_multi_thread.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/configuration/config_multi_thread.gen	(revision 145)
@@ -0,0 +1,10 @@
+Stat_List_unit
+2	2	*2	#_nb_front_end          
+1	3	+1	#_nb_context            [0]
+2	2	*2	#_nb_context            [1]
+256	256	*2	#_nb_general_register   
+64	64	*2	#_nb_special_register   
+4	4	*2	#_nb_inst_insert        
+4	4	*2	#_nb_inst_retire        
+4	4	*2	#_nb_reg_free           
+4	8	*2	#_nb_bank               
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp	(revision 145)
@@ -17,4 +17,39 @@
 namespace register_translation_unit {
 namespace stat_list_unit {
+
+  
+#if (DEBUG >= DEBUG_TRACE)
+# define dump_stat_list                                                 \
+  do                                                                    \
+    {                                                                   \
+      log_printf(TRACE,Stat_List_unit,FUNCTION,"  * Dump Stat List");   \
+      log_printf(TRACE,Stat_List_unit,FUNCTION,"    * reg_GPR_PTR_FREE : %d",reg_GPR_PTR_FREE); \
+      log_printf(TRACE,Stat_List_unit,FUNCTION,"    * reg_SPR_PTR_FREE : %d",reg_SPR_PTR_FREE); \
+                                                                        \
+      for (uint32_t i=0; i<_param->_nb_bank; i++)                       \
+        for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) \
+          log_printf(TRACE,Stat_List_unit,FUNCTION,"    * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d", \
+                     i,                                                 \
+                     j,                                                 \
+                     (i<<_param->_shift_gpr)|j,                         \
+                     gpr_stat_list[i][j]._is_free,                      \
+                     gpr_stat_list[i][j]._is_link,                      \
+                     gpr_stat_list[i][j]._is_use                        \
+                     );                                                 \
+      for (uint32_t i=0; i<_param->_nb_bank; i++)                       \
+        for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) \
+          log_printf(TRACE,Stat_List_unit,FUNCTION,"    * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d", \
+                     i,                                                 \
+                     j,                                                 \
+                     (i<<_param->_shift_spr)|j,                         \
+                     spr_stat_list[i][j]._is_free,                      \
+                     spr_stat_list[i][j]._is_link,                      \
+                     spr_stat_list[i][j]._is_use                        \
+                     );                                                 \
+    }                                                                   \
+  while (0)
+#else
+# define dump_stat_list
+#endif
 
 
@@ -107,5 +142,5 @@
             for (uint32_t i=0; i<_param->_nb_bank; i++)
               for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++)
-                if (not gpr_stat_list [i][j]._is_free)
+                if (not (gpr_stat_list [i][j]._is_free or gpr_stat_list [i][j].can_free()))
                   list_gpr_not_free+=toString((i<<_param->_shift_gpr)|j)+" ";   
 
@@ -114,6 +149,12 @@
             for (uint32_t i=0; i<_param->_nb_bank; i++)
               for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++)
-                if (not spr_stat_list [i][j]._is_free)
+                if (not (spr_stat_list [i][j]._is_free or spr_stat_list [i][j].can_free()))
                   list_spr_not_free+=toString((i<<_param->_shift_spr)|j)+" ";   
+
+          if (error_nb_gpr_free     or
+              error_nb_spr_free     or
+              error_rob_nb_gpr_free or
+              error_rob_nb_spr_free)
+            dump_stat_list;
 
           if (error_nb_gpr_free)
@@ -334,36 +375,6 @@
 
 
-#if (DEBUG >= DEBUG_TRACE)
-    {
-      log_printf(TRACE,Stat_List_unit,FUNCTION,"  * Dump Stat List");
-      log_printf(TRACE,Stat_List_unit,FUNCTION,"    * reg_GPR_PTR_FREE : %d",reg_GPR_PTR_FREE);
-      log_printf(TRACE,Stat_List_unit,FUNCTION,"    * reg_SPR_PTR_FREE : %d",reg_SPR_PTR_FREE);
-      
-      for (uint32_t i=0; i<_param->_nb_bank; i++)
-        for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++)
-          log_printf(TRACE,Stat_List_unit,FUNCTION,"    * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d",
-                     i,
-                     j,
-                     (i<<_param->_shift_gpr)|j,
-                     gpr_stat_list[i][j]._is_free,
-                     gpr_stat_list[i][j]._is_link,
-                     gpr_stat_list[i][j]._is_use// ,
-//                      gpr_stat_list[i][j]._is_valid,
-//                      gpr_stat_list[i][j]._counter
-                     );
-      for (uint32_t i=0; i<_param->_nb_bank; i++)
-        for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++)
-          log_printf(TRACE,Stat_List_unit,FUNCTION,"    * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d",
-                     i,
-                     j,
-                     (i<<_param->_shift_spr)|j,
-                     spr_stat_list[i][j]._is_free,
-                     spr_stat_list[i][j]._is_link,
-                     spr_stat_list[i][j]._is_use// ,
-//                      spr_stat_list[i][j]._is_valid,
-//                      spr_stat_list[i][j]._counter
-                     );
-    }
-#endif
+    dump_stat_list;
+
 
 #ifdef DEBUG_TEST
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Register_translation_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Register_translation_unit.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Register_translation_unit.h	(revision 145)
@@ -144,4 +144,9 @@
   public    : SC_IN (Tdepth_t          )  ***  in_RETIRE_EVENT_DEPTH       ;//[nb_front_end][nb_context]
 
+    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MIN                ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MAX                ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_DEPTH_FULL               ;//[nb_front_end][nb_context]
+
     // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 #ifdef DEBUG_TEST
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp	(revision 145)
@@ -123,10 +123,10 @@
       ALLOC1_SIGNAL_IN ( in_RETIRE_FRONT_END_ID      ,"front_end_id"      ,Tcontext_t        ,_param->_size_front_end_id          );
       ALLOC1_SIGNAL_IN ( in_RETIRE_CONTEXT_ID        ,"context_id"        ,Tcontext_t        ,_param->_size_context_id            );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RA           ,"read_ra"           ,Tcontrol_t        ,1                                   );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RA_PHY    ,"num_reg_ra_phy"    ,Tgeneral_address_t,_param->_size_general_register      );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RB           ,"read_rb"           ,Tcontrol_t        ,1                                   );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RB_PHY    ,"num_reg_rb_phy"    ,Tgeneral_address_t,_param->_size_general_register      );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RC           ,"read_rc"           ,Tcontrol_t        ,1                                   );
-//       ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RC_PHY    ,"num_reg_rc_phy"    ,Tspecial_address_t,_param->_size_special_register      );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RA           ,"read_ra"           ,Tcontrol_t        ,1                                   );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RA_PHY    ,"num_reg_ra_phy"    ,Tgeneral_address_t,_param->_size_general_register      );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RB           ,"read_rb"           ,Tcontrol_t        ,1                                   );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RB_PHY    ,"num_reg_rb_phy"    ,Tgeneral_address_t,_param->_size_general_register      );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RC           ,"read_rc"           ,Tcontrol_t        ,1                                   );
+//    ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RC_PHY    ,"num_reg_rc_phy"    ,Tspecial_address_t,_param->_size_special_register      );
       ALLOC1_SIGNAL_IN ( in_RETIRE_WRITE_RD          ,"write_rd"          ,Tcontrol_t        ,1                                   );
       ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RD_LOG    ,"num_reg_rd_log"    ,Tgeneral_address_t,_param->_size_general_register_logic);
@@ -155,4 +155,15 @@
 
       ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
+    }
+
+    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);
+
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN                        ,"MIN"                        ,Tdepth_t         ,_param->_size_depth                  ,_param->_nb_front_end, _param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX                        ,"MAX"                        ,Tdepth_t         ,_param->_size_depth                  ,_param->_nb_front_end, _param->_nb_context[it1]); 
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL                       ,"FULL"                       ,Tcontrol_t       ,1                                    ,_param->_nb_front_end, _param->_nb_context[it1]); 
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]);
     }
 
@@ -429,4 +440,24 @@
                                 dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_DEPTH");
               }
+          }
+
+      for (uint32_t i=0; i<_param->_nb_front_end; i++)
+        for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+          {
+            dest = _name;
+            
+#ifdef POSITION
+            _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j),
+                                       dest,"depth_"+toString(i)+"_"+toString(j));
+#endif     
+            if (_param->_have_port_depth)
+              {
+	    PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" ,
+                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" );
+	    PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" ,
+                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" );
+              }
+	    PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL",
+                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL");
           }
     }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp	(revision 145)
@@ -102,4 +102,8 @@
         DELETE2_SIGNAL_COND( in_RETIRE_EVENT_DEPTH          ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth     ,_param->_rat_scheme == RAT_DEPTH_SAVE);
 
+        DELETE2_SIGNAL     ( in_DEPTH_MIN                   ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth);
+        DELETE2_SIGNAL     ( in_DEPTH_MAX                   ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth);
+        DELETE2_SIGNAL     ( in_DEPTH_FULL                  ,_param->_nb_front_end,_param->_nb_context[it1],1                  );
+
 #ifdef DEBUG_TEST
         DELETE0_SIGNAL     ( in_INFO_ROB_EMPTY  ,1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/config_mono_front_end.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/config_mono_front_end.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-Rename_select
-1	1	+1	# nb_front_end             
-1	1	+1	# nb_context            [0] [nb_front_end]
-1	1	+1	# max_branch_speculated    
-32	32	*2	# size_general_data        
-1	4	*4	# nb_inst_rename           
-1	4	*4	# nb_inst_decod         [0] [nb_front_end]
-1	1	*4	# nb_front_end_select      
-0	1	+1	# priority                 
-0	1	+1	# load_balancing           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/config_multi_front_end.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/config_multi_front_end.cfg	(revision 144)
+++ 	(revision )
@@ -1,16 +1,0 @@
-Rename_select
-4	4	+1	# nb_front_end             
-2	2	+1	# nb_context            [0] [nb_front_end]
-4	4	+1	# nb_context            [1] [nb_front_end]
-3	3	+1	# nb_context            [2] [nb_front_end]
-1	1	+1	# nb_context            [3] [nb_front_end]
-1	1	+1	# max_branch_speculated    
-32	32	*2	# size_general_data        
-4	4	*4	# nb_inst_rename           
-3	3	*4	# nb_inst_decod         [0] [nb_front_end]
-1	1	*4	# nb_inst_decod         [1] [nb_front_end]
-2	2	*4	# nb_inst_decod         [2] [nb_front_end]
-4	4	*4	# nb_inst_decod         [3] [nb_front_end]
-1	4	+1	# nb_front_end_select      
-0	1	+1	# priority                 
-0	1	+1	# load_balancing           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/configuration/config_mono_front_end.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/configuration/config_mono_front_end.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/configuration/config_mono_front_end.gen	(revision 145)
@@ -0,0 +1,10 @@
+Rename_select
+1	1	+1	# nb_front_end             
+1	1	+1	# nb_context            [0] [nb_front_end]
+1	1	+1	# max_branch_speculated    
+32	32	*2	# size_general_data        
+1	4	*4	# nb_inst_rename           
+1	4	*4	# nb_inst_decod         [0] [nb_front_end]
+1	1	*4	# nb_front_end_select      
+0	1	+1	# priority                 
+0	1	+1	# load_balancing           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/configuration/config_multi_front_end.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/configuration/config_multi_front_end.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/configuration/config_multi_front_end.gen	(revision 145)
@@ -0,0 +1,16 @@
+Rename_select
+4	4	+1	# nb_front_end             
+2	2	+1	# nb_context            [0] [nb_front_end]
+4	4	+1	# nb_context            [1] [nb_front_end]
+3	3	+1	# nb_context            [2] [nb_front_end]
+1	1	+1	# nb_context            [3] [nb_front_end]
+1	1	+1	# max_branch_speculated    
+32	32	*2	# size_general_data        
+4	4	*4	# nb_inst_rename           
+3	3	*4	# nb_inst_decod         [0] [nb_front_end]
+1	1	*4	# nb_inst_decod         [1] [nb_front_end]
+2	2	*4	# nb_inst_decod         [2] [nb_front_end]
+4	4	*4	# nb_inst_decod         [3] [nb_front_end]
+1	4	+1	# nb_front_end_select      
+0	1	+1	# priority                 
+0	1	+1	# load_balancing           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,7 +1,0 @@
-Rename_unit_Glue
-1	1	+1	# nb_front_end          
-1	1	+1	# nb_context     [0] [nb_front_end]
-1	1	+1	# nb_inst_insert        
-1	1	+1	# nb_inst_retire        
-32	32	+1	# size_general_data
-2	2	+1	# size_special_register
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,7 @@
+Rename_unit_Glue
+1	1	+1	# nb_front_end          
+1	1	+1	# nb_context     [0] [nb_front_end]
+1	1	+1	# nb_inst_insert        
+1	1	+1	# nb_inst_retire        
+32	32	+1	# size_general_data
+2	2	+1	# size_special_register
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h	(revision 145)
@@ -69,4 +69,5 @@
   public    : SC_OUT(Tcontext_t        )   ** out_INSERT_CONTEXT_ID                             ;//[nb_inst_insert]
   public    : SC_OUT(Tdepth_t          )   ** out_INSERT_DEPTH                                  ;//[nb_inst_insert]
+  public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_SAVE_RAT                               ;//[nb_inst_insert]
   public    : SC_OUT(Ttype_t           )   ** out_INSERT_TYPE                                   ;//[nb_inst_insert]
   public    : SC_OUT(Toperation_t      )   ** out_INSERT_OPERATION                              ;//[nb_inst_insert]
@@ -82,4 +83,5 @@
   public    : SC_IN (Tcontext_t        )   **  in_INSERT_RENAME_SELECT_CONTEXT_ID               ;//[nb_inst_insert]
   public    : SC_IN (Tdepth_t          )   **  in_INSERT_RENAME_SELECT_DEPTH                    ;//[nb_inst_insert]
+  public    : SC_IN (Tcontrol_t        )   **  in_INSERT_RENAME_SELECT_SAVE_RAT                 ;//[nb_inst_insert]
   public    : SC_IN (Ttype_t           )   **  in_INSERT_RENAME_SELECT_TYPE                     ;//[nb_inst_insert]
   public    : SC_IN (Toperation_t      )   **  in_INSERT_RENAME_SELECT_OPERATION                ;//[nb_inst_insert]
@@ -94,4 +96,5 @@
   public    : SC_OUT(Tcontext_t        )   ** out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID        ;//[nb_inst_insert]
   public    : SC_OUT(Tdepth_t          )   ** out_INSERT_REGISTER_TRANSLATION_DEPTH             ;//[nb_inst_insert]
+  public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_REGISTER_TRANSLATION_SAVE_RAT          ;//[nb_inst_insert]
   public    : SC_IN (Tspecial_address_t)   **  in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW;//[nb_inst_insert]
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp	(revision 145)
@@ -163,6 +163,10 @@
 	    if (_param->_have_port_context_id)
 	    sensitive << (*(in_INSERT_RENAME_SELECT_CONTEXT_ID                [i]));
-            if (_param->_have_port_depth and (_param->_rat_scheme == RAT_DEPTH_SAVE))
+            if (_param->_rat_scheme == RAT_DEPTH_SAVE)
+              {
+            if (_param->_have_port_depth)
 	    sensitive << (*(in_INSERT_RENAME_SELECT_DEPTH                     [i]));
+	    sensitive << (*(in_INSERT_RENAME_SELECT_SAVE_RAT                  [i]));
+              }
 	    sensitive << (*(in_INSERT_RENAME_SELECT_TYPE                      [i]))
 		      << (*(in_INSERT_RENAME_SELECT_OPERATION                 [i]))
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp	(revision 145)
@@ -66,4 +66,5 @@
       ALLOC1_SIGNAL_OUT     (out_INSERT_CONTEXT_ID                             ,"CONTEXT_ID"                             ,Tcontext_t        ,_param->_size_context_id);
       ALLOC1_SIGNAL_OUT_COND(out_INSERT_DEPTH                                  ,"DEPTH"                                  ,Tdepth_t          ,_param->_size_depth,_param->_rat_scheme == RAT_DEPTH_SAVE);
+      ALLOC1_SIGNAL_OUT_COND(out_INSERT_SAVE_RAT                               ,"SAVE_RAT"                               ,Tcontrol_t        ,1,_param->_rat_scheme == RAT_DEPTH_SAVE);
       ALLOC1_SIGNAL_OUT     (out_INSERT_TYPE                                   ,"TYPE"                                   ,Ttype_t           ,_param->_size_type);
       ALLOC1_SIGNAL_OUT     (out_INSERT_OPERATION                              ,"OPERATION"                              ,Toperation_t      ,_param->_size_operation);
@@ -79,4 +80,5 @@
       ALLOC1_SIGNAL_IN      ( in_INSERT_RENAME_SELECT_CONTEXT_ID               ,"RENAME_SELECT_CONTEXT_ID"               ,Tcontext_t        ,_param->_size_context_id);
       ALLOC1_SIGNAL_IN_COND ( in_INSERT_RENAME_SELECT_DEPTH                    ,"RENAME_SELECT_DEPTH"                    ,Tdepth_t          ,_param->_size_depth,_param->_rat_scheme == RAT_DEPTH_SAVE);
+      ALLOC1_SIGNAL_IN_COND ( in_INSERT_RENAME_SELECT_SAVE_RAT                 ,"RENAME_SELECT_SAVE_RAT"                 ,Tcontrol_t        ,1,_param->_rat_scheme == RAT_DEPTH_SAVE);
       ALLOC1_SIGNAL_IN      ( in_INSERT_RENAME_SELECT_TYPE                     ,"RENAME_SELECT_TYPE"                     ,Ttype_t           ,_param->_size_type);
       ALLOC1_SIGNAL_IN      ( in_INSERT_RENAME_SELECT_OPERATION                ,"RENAME_SELECT_OPERATION"                ,Toperation_t      ,_param->_size_operation);
@@ -91,4 +93,5 @@
       ALLOC1_SIGNAL_OUT     (out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID        ,"REGISTER_TRANSLATION_CONTEXT_ID"        ,Tcontext_t        ,_param->_size_context_id);
       ALLOC1_SIGNAL_OUT_COND(out_INSERT_REGISTER_TRANSLATION_DEPTH             ,"REGISTER_TRANSLATION_DEPTH"             ,Tdepth_t          ,_param->_size_depth,_param->_rat_scheme == RAT_DEPTH_SAVE);
+      ALLOC1_SIGNAL_OUT_COND(out_INSERT_REGISTER_TRANSLATION_SAVE_RAT          ,"REGISTER_TRANSLATION_SAVE_RAT"          ,Tcontrol_t        ,1,_param->_rat_scheme == RAT_DEPTH_SAVE);
       ALLOC1_SIGNAL_IN      ( in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW,"REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_size_special_register);
       ALLOC1_SIGNAL_OUT     (out_INSERT_LOAD_STORE_QUEUE_POINTER_VAL           ,"LOAD_STORE_QUEUE_POINTER_VAL"           ,Tcontrol_t        ,1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert.cpp	(revision 145)
@@ -32,5 +32,6 @@
 	Tcontext_t         FRONT_END_ID       = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_RENAME_SELECT_FRONT_END_ID [i]):0;
 	Tcontext_t         CONTEXT_ID         = (_param->_have_port_context_id  )?PORT_READ(in_INSERT_RENAME_SELECT_CONTEXT_ID   [i]):0;
-	Tdepth_t           DEPTH              = ((_param->_rat_scheme == RAT_DEPTH_SAVE) and _param->_have_port_depth)?PORT_READ(in_INSERT_RENAME_SELECT_DEPTH [i]):0;
+	Tdepth_t           DEPTH              = ((_param->_rat_scheme == RAT_DEPTH_SAVE) and _param->_have_port_depth)?PORT_READ(in_INSERT_RENAME_SELECT_DEPTH    [i]):0;
+	Tcontrol_t         SAVE_RAT           = ( _param->_rat_scheme == RAT_DEPTH_SAVE                              )?PORT_READ(in_INSERT_RENAME_SELECT_SAVE_RAT [i]):0;
 	Ttype_t            TYPE               = PORT_READ(in_INSERT_RENAME_SELECT_TYPE                      [i]);
 	Toperation_t       OPERATION          = PORT_READ(in_INSERT_RENAME_SELECT_OPERATION                 [i]);
@@ -97,9 +98,14 @@
 	PORT_WRITE(out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID       [i],CONTEXT_ID        );
 	PORT_WRITE(out_INSERT_LOAD_STORE_QUEUE_POINTER_CONTEXT_ID   [i],CONTEXT_ID        );
-	  }
-        if (_param->_have_port_depth and (_param->_rat_scheme == RAT_DEPTH_SAVE))
-	  {
+	  }	
+        if (_param->_rat_scheme == RAT_DEPTH_SAVE)
+          {
+        if (_param->_have_port_depth)
+          {
 	PORT_WRITE(out_INSERT_DEPTH                                 [i],DEPTH             );
 	PORT_WRITE(out_INSERT_REGISTER_TRANSLATION_DEPTH            [i],DEPTH             );
+          }
+	PORT_WRITE(out_INSERT_SAVE_RAT                              [i],SAVE_RAT          );
+	PORT_WRITE(out_INSERT_REGISTER_TRANSLATION_SAVE_RAT         [i],SAVE_RAT          );
           }
 	PORT_WRITE(out_INSERT_TYPE                                  [i],TYPE              );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,20 +1,0 @@
-Rename_unit
-1	1	+1	# nb_front_end                     
-1	1	+1	# nb_context                       [0]    [nb_front_end]
-1	1	+1	# nb_inst_decod                    [0]    [nb_front_end]
-1	1	+1	# nb_inst_insert                   
-1	1	+1	# nb_inst_retire                   
-1	1	+1	# nb_load_store_queue              
-2	2	+1	# size_store_queue                 [0]    [nb_load_store_queue]
-1	1	+1	# size_load_queue                  [0]    [nb_load_store_queue]
-1	1	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
-1	1	+1	# rename_select_priority           
-1	1	+1	# rename_select_load_balancing     
-1	1	+1	# rename_select_nb_front_end_select
-1 	1	+1	# max_branch_speculated            
-32	32	+1	# size_general_data                
-64	64	+1	# nb_general_register              
-4	4	+1	# nb_special_register              
-1	1	+1	# nb_reg_free                      
-1	1	+1	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_1a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_1a.cfg	(revision 144)
+++ 	(revision )
@@ -1,20 +1,0 @@
-Rename_unit
-1	1	+1	# nb_front_end                     
-1	1	+1	# nb_context                       [0]    [nb_front_end]
-4	4	+1	# nb_inst_decod                    [0]    [nb_front_end]
-4	4	+1	# nb_inst_insert                   
-4	4	+1	# nb_inst_retire                   
-1	1	+1	# nb_load_store_queue              
-8	8	+1	# size_store_queue                 [0]    [nb_load_store_queue]
-8	8	+1	# size_load_queue                  [0]    [nb_load_store_queue]
-8	8	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
-1	1	+1	# rename_select_priority           
-1	1	+1	# rename_select_load_balancing     
-1	1	+1	# rename_select_nb_front_end_select
-4 	4	+1	# max_branch_speculated            
-32	32	+1	# size_general_data                
-64	64	+1	# nb_general_register              
-8	8	+1	# nb_special_register              
-2	2	+1	# nb_reg_free                      
-4	8	*2	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4a.cfg	(revision 144)
+++ 	(revision )
@@ -1,23 +1,0 @@
-Rename_unit
-1	1	+1	# nb_front_end                     
-4	4	+1	# nb_context                       [0]    [nb_front_end]
-4	4	+1	# nb_inst_decod                    [0]    [nb_front_end]
-4	4	+1	# nb_inst_insert                   
-4	4	+1	# nb_inst_retire                   
-1	1	+1	# nb_load_store_queue              
-8	8	+1	# size_store_queue                 [0]    [nb_load_store_queue]
-8	8	+1	# size_load_queue                  [0]    [nb_load_store_queue]
-4	4	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
-0	0	+1	# link_load_store_unit_with_thread [0][1] [nb_front_end][nb_context]
-0	0	+1	# link_load_store_unit_with_thread [0][2] [nb_front_end][nb_context]
-0	0	+1	# link_load_store_unit_with_thread [0][3] [nb_front_end][nb_context]
-1	1	+1	# rename_select_priority           
-1	1	+1	# rename_select_load_balancing     
-1	1	+1	# rename_select_nb_front_end_select
-4 	4	+1	# max_branch_speculated            
-32	32      +1	# size_general_data                
-256	256     +1	# nb_general_register              
-16	16	+1	# nb_special_register              
-2	2	+1	# nb_reg_free                      
-8	8	*2	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4b.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4b.cfg	(revision 144)
+++ 	(revision )
@@ -1,26 +1,0 @@
-Rename_unit
-1	1	+1	# nb_front_end                     
-4	4	+1	# nb_context                       [0]    [nb_front_end]
-4	4	+1	# nb_inst_decod                    [0]    [nb_front_end]
-4	4	+1	# nb_inst_insert                   
-4	4	+1	# nb_inst_retire                   
-2	2	+1	# nb_load_store_queue              
-8	8	+1	# size_store_queue                 [0]    [nb_load_store_queue]
-4	4	+1	# size_store_queue                 [1]    [nb_load_store_queue]
-8	8	+1	# size_load_queue                  [0]    [nb_load_store_queue]
-4	4	+1	# size_load_queue                  [1]    [nb_load_store_queue]
-4	4	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
-2	2	+1	# nb_inst_memory                   [1]    [nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
-1	1	+1	# link_load_store_unit_with_thread [0][1] [nb_front_end][nb_context]
-1	1	+1	# link_load_store_unit_with_thread [0][2] [nb_front_end][nb_context]
-0	0	+1	# link_load_store_unit_with_thread [0][3] [nb_front_end][nb_context]
-1	1	+1	# rename_select_priority           
-1	1	+1	# rename_select_load_balancing     
-1	1	+1	# rename_select_nb_front_end_select
-4 	4	+1	# max_branch_speculated            
-32	32      +1	# size_general_data                
-256	256     +1	# nb_general_register              
-16	16	+1	# nb_special_register              
-2	2	+1	# nb_reg_free                      
-8	8	*2	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,20 @@
+Rename_unit
+1	1	+1	# nb_front_end                     
+1	1	+1	# nb_context                       [0]    [nb_front_end]
+1	1	+1	# nb_inst_decod                    [0]    [nb_front_end]
+1	1	+1	# nb_inst_insert                   
+1	1	+1	# nb_inst_retire                   
+1	1	+1	# nb_load_store_queue              
+2	2	+1	# size_store_queue                 [0]    [nb_load_store_queue]
+1	1	+1	# size_load_queue                  [0]    [nb_load_store_queue]
+1	1	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
+1	1	+1	# rename_select_priority           
+1	1	+1	# rename_select_load_balancing     
+1	1	+1	# rename_select_nb_front_end_select
+1 	1	+1	# max_branch_speculated            
+32	32	+1	# size_general_data                
+64	64	+1	# nb_general_register              
+4	4	+1	# nb_special_register              
+1	1	+1	# nb_reg_free                      
+1	1	+1	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_1a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_1a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_1a.gen	(revision 145)
@@ -0,0 +1,20 @@
+Rename_unit
+1	1	+1	# nb_front_end                     
+1	1	+1	# nb_context                       [0]    [nb_front_end]
+4	4	+1	# nb_inst_decod                    [0]    [nb_front_end]
+4	4	+1	# nb_inst_insert                   
+4	4	+1	# nb_inst_retire                   
+1	1	+1	# nb_load_store_queue              
+8	8	+1	# size_store_queue                 [0]    [nb_load_store_queue]
+8	8	+1	# size_load_queue                  [0]    [nb_load_store_queue]
+8	8	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
+1	1	+1	# rename_select_priority           
+1	1	+1	# rename_select_load_balancing     
+1	1	+1	# rename_select_nb_front_end_select
+4 	4	+1	# max_branch_speculated            
+32	32	+1	# size_general_data                
+64	64	+1	# nb_general_register              
+8	8	+1	# nb_special_register              
+2	2	+1	# nb_reg_free                      
+4	8	*2	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_4a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_4a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_4a.gen	(revision 145)
@@ -0,0 +1,23 @@
+Rename_unit
+1	1	+1	# nb_front_end                     
+4	4	+1	# nb_context                       [0]    [nb_front_end]
+4	4	+1	# nb_inst_decod                    [0]    [nb_front_end]
+4	4	+1	# nb_inst_insert                   
+4	4	+1	# nb_inst_retire                   
+1	1	+1	# nb_load_store_queue              
+8	8	+1	# size_store_queue                 [0]    [nb_load_store_queue]
+8	8	+1	# size_load_queue                  [0]    [nb_load_store_queue]
+4	4	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
+0	0	+1	# link_load_store_unit_with_thread [0][1] [nb_front_end][nb_context]
+0	0	+1	# link_load_store_unit_with_thread [0][2] [nb_front_end][nb_context]
+0	0	+1	# link_load_store_unit_with_thread [0][3] [nb_front_end][nb_context]
+1	1	+1	# rename_select_priority           
+1	1	+1	# rename_select_load_balancing     
+1	1	+1	# rename_select_nb_front_end_select
+4 	4	+1	# max_branch_speculated            
+32	32      +1	# size_general_data                
+256	256     +1	# nb_general_register              
+16	16	+1	# nb_special_register              
+2	2	+1	# nb_reg_free                      
+8	8	*2	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_4b.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_4b.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/configuration/config-thread_4b.gen	(revision 145)
@@ -0,0 +1,26 @@
+Rename_unit
+1	1	+1	# nb_front_end                     
+4	4	+1	# nb_context                       [0]    [nb_front_end]
+4	4	+1	# nb_inst_decod                    [0]    [nb_front_end]
+4	4	+1	# nb_inst_insert                   
+4	4	+1	# nb_inst_retire                   
+2	2	+1	# nb_load_store_queue              
+8	8	+1	# size_store_queue                 [0]    [nb_load_store_queue]
+4	4	+1	# size_store_queue                 [1]    [nb_load_store_queue]
+8	8	+1	# size_load_queue                  [0]    [nb_load_store_queue]
+4	4	+1	# size_load_queue                  [1]    [nb_load_store_queue]
+4	4	+1	# nb_inst_memory                   [0]    [nb_load_store_queue]
+2	2	+1	# nb_inst_memory                   [1]    [nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context]
+1	1	+1	# link_load_store_unit_with_thread [0][1] [nb_front_end][nb_context]
+1	1	+1	# link_load_store_unit_with_thread [0][2] [nb_front_end][nb_context]
+0	0	+1	# link_load_store_unit_with_thread [0][3] [nb_front_end][nb_context]
+1	1	+1	# rename_select_priority           
+1	1	+1	# rename_select_load_balancing     
+1	1	+1	# rename_select_nb_front_end_select
+4 	4	+1	# max_branch_speculated            
+32	32      +1	# size_general_data                
+256	256     +1	# nb_general_register              
+16	16	+1	# nb_special_register              
+2	2	+1	# nb_reg_free                      
+8	8	*2	# nb_bank                          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h	(revision 145)
@@ -117,4 +117,5 @@
   public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_LAST_EVENT           ;//[nb_inst_insert]
   public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_IS_DELAY_SLOT        ;//[nb_inst_insert]
+  public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_SAVE_RAT             ;//[nb_inst_insert]
 #ifdef DEBUG
   public    : SC_OUT(Taddress_t        )   ** out_INSERT_ADDRESS              ;//[nb_inst_insert]
@@ -194,4 +195,9 @@
   public    : SC_IN (Tspr_t            )  ***  in_SPR_READ_SR                 ;//[nb_front_end][nb_context]
 
+    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MIN                   ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MAX                   ;//[nb_front_end][nb_context]
+  public    : SC_IN (Tcontrol_t        )  ***  in_DEPTH_FULL                  ;//[nb_front_end][nb_context]
+
     // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 #ifdef DEBUG_TEST
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp	(revision 145)
@@ -15,6 +15,4 @@
 namespace ooo_engine {
 namespace rename_unit {
-
-
 
 #undef  FUNCTION
@@ -101,52 +99,53 @@
       ALLOC1_INTERFACE_BEGIN("insert",OUT,WEST , _("Instruction with physical register"), _param->_nb_inst_insert);
       
-      ALLOC1_VALACK_OUT(out_INSERT_VAL                  ,VAL);
-      ALLOC1_VALACK_IN ( in_INSERT_ACK                  ,ACK);
-      ALLOC1_SIGNAL_OUT(out_INSERT_FRONT_END_ID         ,"front_end_id"         ,Tcontext_t        ,_param->_size_front_end_id          );
-      ALLOC1_SIGNAL_OUT(out_INSERT_CONTEXT_ID           ,"context_id"           ,Tcontext_t        ,_param->_size_context_id            );
-      ALLOC1_SIGNAL_OUT(out_INSERT_DEPTH                ,"depth"                ,Tdepth_t          ,_param->_size_depth                 );
-#ifdef STATISTICS
-      ALLOC1_SIGNAL_OUT(out_INSERT_INSTRUCTION          ,"instruction"          ,uint32_t          ,32);
-#endif
-      ALLOC1_SIGNAL_OUT(out_INSERT_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type                  );
-      ALLOC1_SIGNAL_OUT(out_INSERT_OPERATION            ,"operation"            ,Toperation_t      ,_param->_size_operation             );
-      ALLOC1_SIGNAL_OUT(out_INSERT_NO_EXECUTE           ,"no_execute"           ,Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_LAST_EVENT           ,"last_event"           ,Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_IS_DELAY_SLOT        ,"is_delay_slot"        ,Tcontrol_t        ,1                                   );
+      ALLOC1_VALACK_OUT     (out_INSERT_VAL                  ,VAL);
+      ALLOC1_VALACK_IN      ( in_INSERT_ACK                  ,ACK);
+      ALLOC1_SIGNAL_OUT     (out_INSERT_FRONT_END_ID         ,"front_end_id"         ,Tcontext_t        ,_param->_size_front_end_id          );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_CONTEXT_ID           ,"context_id"           ,Tcontext_t        ,_param->_size_context_id            );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_DEPTH                ,"depth"                ,Tdepth_t          ,_param->_size_depth                 );
+#ifdef STATISTICS           
+      ALLOC1_SIGNAL_OUT     (out_INSERT_INSTRUCTION          ,"instruction"          ,uint32_t          ,32);
+#endif                      
+      ALLOC1_SIGNAL_OUT     (out_INSERT_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type                  );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_OPERATION            ,"operation"            ,Toperation_t      ,_param->_size_operation             );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NO_EXECUTE           ,"no_execute"           ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_LAST_EVENT           ,"last_event"           ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_IS_DELAY_SLOT        ,"is_delay_slot"        ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT_COND(out_INSERT_SAVE_RAT             ,"save_rat"             ,Tcontrol_t        ,1                                   ,_param->_rat_scheme == RAT_DEPTH_SAVE);
 #ifdef DEBUG
-      ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS              ,"address"              ,Taddress_t        ,_param->_size_instruction_address   );
-#endif
-      ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS_NEXT         ,"address_next"         ,Taddress_t        ,_param->_size_instruction_address   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_IMMEDIAT             ,"immediat"             ,Tgeneral_data_t   ,_param->_size_general_data          );
-      ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr       );
-      ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr       );
-      ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr        );
-      ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION_USE        ,"exception_use"        ,Texception_t      ,_param->_size_exception_use         );
-      ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION            ,"exception"            ,Texception_t      ,_param->_size_exception             );
-      ALLOC1_SIGNAL_OUT(out_INSERT_READ_RA              ,"read_ra"              ,Tcontrol_t        ,1                                   );
-#ifdef DEBUG
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RA_LOG       ,"num_reg_ra_log"       ,Tgeneral_address_t,_param->_size_general_register_logic);
-#endif
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RA_PHY       ,"num_reg_ra_phy"       ,Tgeneral_address_t,_param->_size_general_register      );
-      ALLOC1_SIGNAL_OUT(out_INSERT_READ_RB              ,"read_rb"              ,Tcontrol_t        ,1                                   );
-#ifdef DEBUG
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RB_LOG       ,"num_reg_rb_log"       ,Tgeneral_address_t,_param->_size_general_register_logic);
-#endif
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RB_PHY       ,"num_reg_rb_phy"       ,Tgeneral_address_t,_param->_size_general_register      );
-      ALLOC1_SIGNAL_OUT(out_INSERT_READ_RC              ,"read_rc"              ,Tcontrol_t        ,1                                   );
-#ifdef DEBUG
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RC_LOG       ,"num_reg_rc_log"       ,Tspecial_address_t,_param->_size_special_register_logic);
-#endif
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RC_PHY       ,"num_reg_rc_phy"       ,Tspecial_address_t,_param->_size_special_register      );
-      ALLOC1_SIGNAL_OUT(out_INSERT_WRITE_RD             ,"write_rd"             ,Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RD_LOG       ,"num_reg_rd_log"       ,Tgeneral_address_t,_param->_size_general_register_logic);
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RD_PHY_OLD   ,"num_reg_rd_phy_old"   ,Tgeneral_address_t,_param->_size_general_register      );
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RD_PHY_NEW   ,"num_reg_rd_phy_new"   ,Tgeneral_address_t,_param->_size_general_register      );
-      ALLOC1_SIGNAL_OUT(out_INSERT_WRITE_RE             ,"write_re"             ,Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_LOG       ,"num_reg_re_log"       ,Tspecial_address_t,_param->_size_special_register_logic);
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_OLD   ,"num_reg_re_phy_old"   ,Tspecial_address_t,_param->_size_special_register      );
-      ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_NEW   ,"num_reg_re_phy_new"   ,Tspecial_address_t,_param->_size_special_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_ADDRESS              ,"address"              ,Taddress_t        ,_param->_size_instruction_address   );
+#endif                      
+      ALLOC1_SIGNAL_OUT     (out_INSERT_ADDRESS_NEXT         ,"address_next"         ,Taddress_t        ,_param->_size_instruction_address   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_IMMEDIAT             ,"immediat"             ,Tgeneral_data_t   ,_param->_size_general_data          );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr       );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t        ,_param->_size_store_queue_ptr       );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_STORE_QUEUE_EMPTY    ,"store_queue_empty"    ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr        );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_EXCEPTION_USE        ,"exception_use"        ,Texception_t      ,_param->_size_exception_use         );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_EXCEPTION            ,"exception"            ,Texception_t      ,_param->_size_exception             );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_READ_RA              ,"read_ra"              ,Tcontrol_t        ,1                                   );
+#ifdef DEBUG                
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RA_LOG       ,"num_reg_ra_log"       ,Tgeneral_address_t,_param->_size_general_register_logic);
+#endif                      
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RA_PHY       ,"num_reg_ra_phy"       ,Tgeneral_address_t,_param->_size_general_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_READ_RB              ,"read_rb"              ,Tcontrol_t        ,1                                   );
+#ifdef DEBUG                
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RB_LOG       ,"num_reg_rb_log"       ,Tgeneral_address_t,_param->_size_general_register_logic);
+#endif                      
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RB_PHY       ,"num_reg_rb_phy"       ,Tgeneral_address_t,_param->_size_general_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_READ_RC              ,"read_rc"              ,Tcontrol_t        ,1                                   );
+#ifdef DEBUG                
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RC_LOG       ,"num_reg_rc_log"       ,Tspecial_address_t,_param->_size_special_register_logic);
+#endif                      
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RC_PHY       ,"num_reg_rc_phy"       ,Tspecial_address_t,_param->_size_special_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_WRITE_RD             ,"write_rd"             ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RD_LOG       ,"num_reg_rd_log"       ,Tgeneral_address_t,_param->_size_general_register_logic);
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RD_PHY_OLD   ,"num_reg_rd_phy_old"   ,Tgeneral_address_t,_param->_size_general_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RD_PHY_NEW   ,"num_reg_rd_phy_new"   ,Tgeneral_address_t,_param->_size_general_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_WRITE_RE             ,"write_re"             ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RE_LOG       ,"num_reg_re_log"       ,Tspecial_address_t,_param->_size_special_register_logic);
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RE_PHY_OLD   ,"num_reg_re_phy_old"   ,Tspecial_address_t,_param->_size_special_register      );
+      ALLOC1_SIGNAL_OUT     (out_INSERT_NUM_REG_RE_PHY_NEW   ,"num_reg_re_phy_new"   ,Tspecial_address_t,_param->_size_special_register      );
 
       ALLOC1_INTERFACE_END(_param->_nb_inst_insert);
@@ -210,4 +209,15 @@
 
       ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
+    }
+
+    // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);
+
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN                        ,"MIN"                        ,Tdepth_t         ,_param->_size_depth                  ,_param->_nb_front_end, _param->_nb_context[it1]);
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX                        ,"MAX"                        ,Tdepth_t         ,_param->_size_depth                  ,_param->_nb_front_end, _param->_nb_context[it1]); 
+      _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL                       ,"FULL"                       ,Tcontrol_t       ,1                                    ,_param->_nb_front_end, _param->_nb_context[it1]); 
+
+      ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]);
     }
 
@@ -440,4 +450,5 @@
 #endif
 
+          if (_param->_rat_scheme != RAT_DEPTH_SAVE)
 	  COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_SAVE_RAT"  ,
 		                   dest, "in_RENAME_"    +toString(i)+"_SAVE_RAT"  );
@@ -483,4 +494,7 @@
 	  COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+              "_DEPTH"        ,
 		                   dest, "in_INSERT_"    +toString(i)+"_RENAME_SELECT_DEPTH"        );
+          if (_param->_rat_scheme == RAT_DEPTH_SAVE)
+	  COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+              "_SAVE_RAT"     ,
+		                   dest, "in_INSERT_"    +toString(i)+"_RENAME_SELECT_SAVE_RAT"     );
 	  COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+              "_TYPE"         ,
 			           dest, "in_INSERT_"    +toString(i)+"_RENAME_SELECT_TYPE"         );
@@ -559,4 +573,7 @@
 	  COMPONENT_MAP(_component,src , "in_RENAME_"+toString(i)+                     "_DEPTH"        ,
 			           dest,"out_INSERT_"+toString(i)+"_REGISTER_TRANSLATION_DEPTH"        );
+          if (_param->_rat_scheme == RAT_DEPTH_SAVE)
+	  COMPONENT_MAP(_component,src , "in_RENAME_"+toString(i)+                     "_SAVE_RAT"     ,
+			           dest,"out_INSERT_"+toString(i)+"_REGISTER_TRANSLATION_SAVE_RAT"     );
 
 	  //  in_RENAME_SAVE_RAS          - rename_select
@@ -733,4 +750,23 @@
           }
 
+      for (uint32_t i=0; i<_param->_nb_front_end; i++)
+        for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+          {
+            dest = _name;
+            
+#ifdef POSITION
+            _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j),
+                                       dest,"depth_"+toString(i)+"_"+toString(j));
+#endif     
+            if (_param->_have_port_depth)
+              {
+	    PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" ,
+                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" );
+	    PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" ,
+                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" );
+              }
+	    PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL",
+                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL");
+          }
 
 #ifdef DEBUG_TEST
@@ -909,4 +945,7 @@
 	  PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_DEPTH"        ,
 		              dest,"out_INSERT_"+toString(i)+"_DEPTH"        );
+          if (_param->_rat_scheme == RAT_DEPTH_SAVE)
+	  PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_SAVE_RAT"     ,
+		              dest,"out_INSERT_"+toString(i)+"_SAVE_RAT"     );
 	  PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_TYPE"         ,
 		              dest,"out_INSERT_"+toString(i)+"_TYPE"         );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp	(revision 145)
@@ -75,4 +75,5 @@
         DELETE1_SIGNAL     (out_INSERT_LAST_EVENT           ,_param->_nb_inst_insert,1                                   );
         DELETE1_SIGNAL     (out_INSERT_IS_DELAY_SLOT        ,_param->_nb_inst_insert,1                                   );
+        DELETE1_SIGNAL_COND(out_INSERT_SAVE_RAT             ,_param->_nb_inst_insert,1                                   ,_param->_rat_scheme == RAT_DEPTH_SAVE);
 #ifdef DEBUG               
         DELETE1_SIGNAL     (out_INSERT_ADDRESS              ,_param->_nb_inst_insert,_param->_size_instruction_address   );
@@ -147,5 +148,9 @@
         DELETE2_SIGNAL_COND( in_RETIRE_EVENT_DEPTH          ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth     ,_param->_rat_scheme == RAT_DEPTH_SAVE);
         
-        DELETE2_SIGNAL     (in_SPR_READ_SR                  ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr);
+        DELETE2_SIGNAL     ( in_SPR_READ_SR                 ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr);
+
+        DELETE2_SIGNAL     ( in_DEPTH_MIN                   ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth);
+        DELETE2_SIGNAL     ( in_DEPTH_MAX                   ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth);
+        DELETE2_SIGNAL     ( in_DEPTH_FULL                  ,_param->_nb_front_end,_param->_nb_context[it1],1                  );
 
 #ifdef DEBUG_TEST
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,43 +1,0 @@
-OOO_Engine
-1	1	+1	# nb_front_end                                        
-1	1	+1	# nb_context                        [0]               [nb_front_end]
-1	1	+1	# nb_rename_unit                                      
-1	1	+1	# nb_execute_loop                                     
-1	1	+1	# nb_inst_decod                     [0]               [nb_front_end]
-1	1	+1	# nb_inst_insert                    [0]               [nb_rename_unit]
-1	1	+1	# nb_inst_retire                    [0]               [nb_rename_unit]
-1	1	+1	# nb_inst_execute                   [0]               [nb_execute_loop]
-1	1	+1	# nb_inst_reexecute                                   
-1	1	+1	# nb_inst_commit                                      
-1	1	+1	# nb_inst_branch_complete                             
-1	1	+1	# nb_branch_speculated              [0][0]            [nb_front_end][nb_context]
-1	1	+1	# size_nb_inst_decod  
-1	1	+1	# nb_rename_unit_select                    
-1	1	+1	# nb_execute_loop_select                   
-32	32	*2	# size_general_data                        
-2	2	*2	# size_special_data                        
-0	0	+1	# link_rename_unit_with_front_end   [0]               [nb_front_end]
-1	1	+1	# size_re_order_buffer                     
-1	1	+1	# nb_re_order_buffer_bank                  
-1	1	+1	# commit_priority                          
-1	1	+1	# commit_load_balancing                    
-1	1	+1	# size_issue_queue
-0	1	+1	# issue_queue_scheme
-1	1	+1	# nb_issue_queue_bank                      
-1	1	+1	# issue_priority                           
-1	1	+1	# issue_load_balancing                     
-1	1	+1	# size_reexecute_queue                     
-1	1	+1	# reexecute_priority                       
-1	1	+1	# reexecute_load_balancing                 
-1	1	+1	# rename_select_priority            [0]               [nb_rename_unit]
-1	1	+1	# rename_select_load_balancing      [0]               [nb_rename_unit]
-1	1	+1	# rename_select_nb_front_end_select [0]               [nb_rename_unit]
-64	64	+1	# nb_general_register               [0]               [nb_rename_unit]
-4	4	+1	# nb_special_register               [0]               [nb_rename_unit]
-1	1	+1	# nb_reg_free                       [0]               [nb_rename_unit]
-1	1	+1	# nb_rename_unit_bank               [0]               [nb_rename_unit]
-1	1	+1	# nb_load_store_queue               [0]               [nb_rename_unit]
-2	2	+1	# size_store_queue                  [0][0]            [nb_rename_unit][nb_load_store_queue]
-1	1	+1	# size_load_queue                   [0][0]            [nb_rename_unit][nb_load_store_queue]
-1	1	+1	# nb_inst_memory                    [0][0]            [nb_rename_unit][nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread  [0][0]            [nb_front_end][nb_context]           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,43 @@
+OOO_Engine
+1	1	+1	# nb_front_end                                        
+1	1	+1	# nb_context                        [0]               [nb_front_end]
+1	1	+1	# nb_rename_unit                                      
+1	1	+1	# nb_execute_loop                                     
+1	1	+1	# nb_inst_decod                     [0]               [nb_front_end]
+1	1	+1	# nb_inst_insert                    [0]               [nb_rename_unit]
+1	1	+1	# nb_inst_retire                    [0]               [nb_rename_unit]
+1	1	+1	# nb_inst_execute                   [0]               [nb_execute_loop]
+1	1	+1	# nb_inst_reexecute                                   
+1	1	+1	# nb_inst_commit                                      
+1	1	+1	# nb_inst_branch_complete                             
+1	1	+1	# nb_branch_speculated              [0][0]            [nb_front_end][nb_context]
+1	1	+1	# size_nb_inst_decod  
+1	1	+1	# nb_rename_unit_select                    
+1	1	+1	# nb_execute_loop_select                   
+32	32	*2	# size_general_data                        
+2	2	*2	# size_special_data                        
+0	0	+1	# link_rename_unit_with_front_end   [0]               [nb_front_end]
+1	1	+1	# size_re_order_buffer                     
+1	1	+1	# nb_re_order_buffer_bank                  
+1	1	+1	# commit_priority                          
+1	1	+1	# commit_load_balancing                    
+1	1	+1	# size_issue_queue
+0	1	+1	# issue_queue_scheme
+1	1	+1	# nb_issue_queue_bank                      
+1	1	+1	# issue_priority                           
+1	1	+1	# issue_load_balancing                     
+1	1	+1	# size_reexecute_queue                     
+1	1	+1	# reexecute_priority                       
+1	1	+1	# reexecute_load_balancing                 
+1	1	+1	# rename_select_priority            [0]               [nb_rename_unit]
+1	1	+1	# rename_select_load_balancing      [0]               [nb_rename_unit]
+1	1	+1	# rename_select_nb_front_end_select [0]               [nb_rename_unit]
+64	64	+1	# nb_general_register               [0]               [nb_rename_unit]
+4	4	+1	# nb_special_register               [0]               [nb_rename_unit]
+1	1	+1	# nb_reg_free                       [0]               [nb_rename_unit]
+1	1	+1	# nb_rename_unit_bank               [0]               [nb_rename_unit]
+1	1	+1	# nb_load_store_queue               [0]               [nb_rename_unit]
+2	2	+1	# size_store_queue                  [0][0]            [nb_rename_unit][nb_load_store_queue]
+1	1	+1	# size_load_queue                   [0][0]            [nb_rename_unit][nb_load_store_queue]
+1	1	+1	# nb_inst_memory                    [0][0]            [nb_rename_unit][nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread  [0][0]            [nb_front_end][nb_context]           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration/debug.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration/debug.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration/debug.gen	(revision 145)
@@ -0,0 +1,43 @@
+OOO_Engine
+1	1	+1	# nb_front_end                                        
+1	1	+1	# nb_context                        [0]               [nb_front_end]
+1	1	+1	# nb_rename_unit                                      
+1	1	+1	# nb_execute_loop                                     
+1	1	+1	# nb_inst_decod                     [0]               [nb_front_end]
+1	1	+1	# nb_inst_insert                    [0]               [nb_rename_unit]
+1	1	+1	# nb_inst_retire                    [0]               [nb_rename_unit]
+1	1	+1	# nb_inst_execute                   [0]               [nb_execute_loop]
+1	1	+1	# nb_inst_reexecute                                   
+1	1	+1	# nb_inst_commit                                      
+1	1	+1	# nb_inst_branch_complete                             
+1	1	+1	# nb_branch_speculated              [0][0]            [nb_front_end][nb_context]
+1	1	+1	# size_nb_inst_decod  
+1	1	+1	# nb_rename_unit_select                    
+1	1	+1	# nb_execute_loop_select                   
+32	32	*2	# size_general_data                        
+2	2	*2	# size_special_data                        
+0	0	+1	# link_rename_unit_with_front_end   [0]               [nb_front_end]
+1	1	+1	# size_re_order_buffer                     
+1	1	+1	# nb_re_order_buffer_bank                  
+1	1	+1	# commit_priority                          
+1	1	+1	# commit_load_balancing                    
+1	1	+1	# size_issue_queue
+1	1	+1	# issue_queue_scheme
+1	1	+1	# nb_issue_queue_bank                      
+1	1	+1	# issue_priority                           
+1	1	+1	# issue_load_balancing                     
+1	1	+1	# size_reexecute_queue                     
+1	1	+1	# reexecute_priority                       
+1	1	+1	# reexecute_load_balancing                 
+1	1	+1	# rename_select_priority            [0]               [nb_rename_unit]
+1	1	+1	# rename_select_load_balancing      [0]               [nb_rename_unit]
+1	1	+1	# rename_select_nb_front_end_select [0]               [nb_rename_unit]
+64	64	+1	# nb_general_register               [0]               [nb_rename_unit]
+4	4	+1	# nb_special_register               [0]               [nb_rename_unit]
+1	1	+1	# nb_reg_free                       [0]               [nb_rename_unit]
+1	1	+1	# nb_rename_unit_bank               [0]               [nb_rename_unit]
+1	1	+1	# nb_load_store_queue               [0]               [nb_rename_unit]
+2	2	+1	# size_store_queue                  [0][0]            [nb_rename_unit][nb_load_store_queue]
+1	1	+1	# size_load_queue                   [0][0]            [nb_rename_unit][nb_load_store_queue]
+1	1	+1	# nb_inst_memory                    [0][0]            [nb_rename_unit][nb_load_store_queue]
+0	0	+1	# link_load_store_unit_with_thread  [0][0]            [nb_front_end][nb_context]           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/debug.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/debug.cfg	(revision 144)
+++ 	(revision )
@@ -1,43 +1,0 @@
-OOO_Engine
-1	1	+1	# nb_front_end                                        
-1	1	+1	# nb_context                        [0]               [nb_front_end]
-1	1	+1	# nb_rename_unit                                      
-1	1	+1	# nb_execute_loop                                     
-1	1	+1	# nb_inst_decod                     [0]               [nb_front_end]
-1	1	+1	# nb_inst_insert                    [0]               [nb_rename_unit]
-1	1	+1	# nb_inst_retire                    [0]               [nb_rename_unit]
-1	1	+1	# nb_inst_execute                   [0]               [nb_execute_loop]
-1	1	+1	# nb_inst_reexecute                                   
-1	1	+1	# nb_inst_commit                                      
-1	1	+1	# nb_inst_branch_complete                             
-1	1	+1	# nb_branch_speculated              [0][0]            [nb_front_end][nb_context]
-1	1	+1	# size_nb_inst_decod  
-1	1	+1	# nb_rename_unit_select                    
-1	1	+1	# nb_execute_loop_select                   
-32	32	*2	# size_general_data                        
-2	2	*2	# size_special_data                        
-0	0	+1	# link_rename_unit_with_front_end   [0]               [nb_front_end]
-1	1	+1	# size_re_order_buffer                     
-1	1	+1	# nb_re_order_buffer_bank                  
-1	1	+1	# commit_priority                          
-1	1	+1	# commit_load_balancing                    
-1	1	+1	# size_issue_queue
-1	1	+1	# issue_queue_scheme
-1	1	+1	# nb_issue_queue_bank                      
-1	1	+1	# issue_priority                           
-1	1	+1	# issue_load_balancing                     
-1	1	+1	# size_reexecute_queue                     
-1	1	+1	# reexecute_priority                       
-1	1	+1	# reexecute_load_balancing                 
-1	1	+1	# rename_select_priority            [0]               [nb_rename_unit]
-1	1	+1	# rename_select_load_balancing      [0]               [nb_rename_unit]
-1	1	+1	# rename_select_nb_front_end_select [0]               [nb_rename_unit]
-64	64	+1	# nb_general_register               [0]               [nb_rename_unit]
-4	4	+1	# nb_special_register               [0]               [nb_rename_unit]
-1	1	+1	# nb_reg_free                       [0]               [nb_rename_unit]
-1	1	+1	# nb_rename_unit_bank               [0]               [nb_rename_unit]
-1	1	+1	# nb_load_store_queue               [0]               [nb_rename_unit]
-2	2	+1	# size_store_queue                  [0][0]            [nb_rename_unit][nb_load_store_queue]
-1	1	+1	# size_load_queue                   [0][0]            [nb_rename_unit][nb_load_store_queue]
-1	1	+1	# nb_inst_memory                    [0][0]            [nb_rename_unit][nb_load_store_queue]
-0	0	+1	# link_load_store_unit_with_thread  [0][0]            [nb_front_end][nb_context]           
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,4 +1,0 @@
-Special_Register_unit
-1	1	+1 # nb_front_end         
-1	1	+1 # nb_context        [0] [nb_front_end]
-1	1	+1 # nb_inst_reexecute    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,4 @@
+Special_Register_unit
+1	1	+1 # nb_front_end         
+1	1	+1 # nb_context        [0] [nb_front_end]
+1	1	+1 # nb_inst_reexecute    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h	(revision 145)
@@ -208,5 +208,5 @@
   public    : SC_OUT(Tcounter_t        )  *** out_NB_INST_COMMIT_MEM               ;//[nb_front_end][nb_context]
   public    : SC_IN (Tcounter_t        )  ***  in_NB_INST_DECOD_ALL                ;//[nb_front_end][nb_context]
-                                                                                   
+
     // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~         
   public    : SC_IN (Tdepth_t          )  ***  in_DEPTH_MIN                        ;//[nb_front_end][nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h	(revision 145)
@@ -98,5 +98,4 @@
   public : uint32_t            * _rename_unit_size_front_end_id                ;//[nb_rename_unit]
   public : uint32_t            * _rename_unit_size_context_id                  ;//[nb_rename_unit]
-  public : Trat_scheme_t       * _commit_unit_rat_scheme                       ;//[nb_front_end]
   public : uint32_t              _max_nb_context                               ;
   public : uint32_t              _max_branch_speculated                        ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp	(revision 145)
@@ -534,4 +534,7 @@
             COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)                +"_IS_DELAY_SLOT" ,
                                      dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT" );
+            if (_param->_rat_scheme[i] == RAT_DEPTH_SAVE)
+            COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)                +"_SAVE_RAT"      ,
+                                     dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_SAVE_RAT"      );
 //          COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)                +"_HAVE_EVENT"    ,
 //                                   dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_HAVE_EVENT"    );
@@ -633,6 +636,4 @@
 #endif
 
-
-
             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_VAL"               ,
                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_VAL"               );
@@ -670,16 +671,16 @@
             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_LOAD_QUEUE_PTR_WRITE" ,
                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_LOAD_QUEUE_PTR_WRITE" );
-//             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_READ_RA"              ,
-//                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RA"              );
-//             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RA_PHY"       ,
-//                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RA_PHY"       );
-//             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_READ_RB"              ,
-//                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RB"              );
-//             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RB_PHY"       ,
-//                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RB_PHY"       );
-//             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_READ_RC"              ,
-//                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RC"              );
-//             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RC_PHY"       ,
-//                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RC_PHY"       );
+//          COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_READ_RA"              ,
+//                                   dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RA"              );
+//          COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RA_PHY"       ,
+//                                   dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RA_PHY"       );
+//          COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_READ_RB"              ,
+//                                   dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RB"              );
+//          COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RB_PHY"       ,
+//                                   dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RB_PHY"       );
+//          COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_READ_RC"              ,
+//                                   dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RC"              );
+//          COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RC_PHY"       ,
+//                                   dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RC_PHY"       );
             COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+                "_NUM_REG_RD_LOG"       ,
                                      dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RD_LOG"       );
@@ -755,4 +756,36 @@
               }
         }
+
+        // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+        {
+          std::vector<uint32_t>::iterator it = _param->_link_front_end_with_rename_unit[i].begin();
+          uint32_t x = 0;
+          for (uint32_t j=0; j<_param->_nb_front_end; j++)
+            if (j == *it)
+              {
+                for (uint32_t k=0; k<_param->_nb_context[j]; k++)
+                  {
+                    dest = _name;
+                    
+#ifdef POSITION
+                    _component->interface_map (src ,"spr_read_"+toString(x)+"_"+toString(k),
+                                               dest,"spr_"     +toString(j)+"_"+toString(k));
+#endif
+
+                    if (_param->_have_port_depth)
+                      {
+                    PORT_MAP(_component,src , "in_DEPTH_"+toString(x)+"_"+toString(k)+"_MIN" ,
+                                        dest, "in_DEPTH_"+toString(j)+"_"+toString(k)+"_MIN" );
+                    PORT_MAP(_component,src , "in_DEPTH_"+toString(x)+"_"+toString(k)+"_MAX" ,
+                                        dest, "in_DEPTH_"+toString(j)+"_"+toString(k)+"_MAX" );
+                      }
+                    PORT_MAP(_component,src , "in_DEPTH_"+toString(x)+"_"+toString(k)+"_FULL",
+                                        dest, "in_DEPTH_"+toString(j)+"_"+toString(k)+"_FULL");
+                  }
+                x++;
+                ++it;
+              }
+        }
+
 
         // ~~~~~[ Interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -919,4 +952,5 @@
             //  out_RETIRE_CONTEXT_ID                - component_rename_unit
             ////out_RETIRE_RENAME_UNIT_ID            - component_rename_unit
+            //  out_RETIRE_DEPTH                     - component_rename_unit
             //  out_RETIRE_USE_STORE_QUEUE           - component_rename_unit
             //  out_RETIRE_USE_LOAD_QUEUE            - component_rename_unit
@@ -981,5 +1015,4 @@
           COMPONENT_MAP(_component,src ,"out_COMMIT_"+toString(i)+"_NUM_REG_RD" ,
                                    dest, "in_COMMIT_"+toString(i)+"_NUM_REG_RD" );
-          //@@@@@@@@@@
 	}
       
@@ -1111,24 +1144,24 @@
           }
 
-      // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
-      for (uint32_t i=0; i<_param->_nb_front_end; i++)
-        for (uint32_t j=0; j<_param->_nb_context[i]; j++)
-          {
-            dest = _name;
-#ifdef POSITION
-            _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j),
-                                       dest,"depth_"+toString(i)+"_"+toString(j));
-#endif
-
-            if (_param->_have_port_depth)
-              {
-            PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN",
-                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN");
-            PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX",
-                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX");
-              }
-            PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL",
-                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL");
-          }
+//      // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
+//      for (uint32_t i=0; i<_param->_nb_front_end; i++)
+//        for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+//          {
+//            dest = _name;
+//#ifdef POSITION
+//            _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j),
+//                                       dest,"depth_"+toString(i)+"_"+toString(j));
+//#endif
+//
+//            if (_param->_have_port_depth)
+//              {
+//            PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN",
+//                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN");
+//            PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX",
+//                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX");
+//              }
+//            PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL",
+//                                dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL");
+//          }
 
       // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp	(revision 145)
@@ -82,51 +82,50 @@
     log_begin(OOO_Engine,FUNCTION);
 
-    _nb_front_end                      = nb_front_end                     ;
-    _nb_context                        = nb_context                       ;
-    _nb_rename_unit                    = nb_rename_unit                   ;
-    _nb_execute_loop                   = nb_execute_loop                  ;
-    _nb_inst_decod                     = nb_inst_decod                    ;
-    _nb_inst_insert                    = nb_inst_insert                   ;
-    _nb_inst_retire                    = nb_inst_retire                   ;
-//  _nb_inst_issue                     = nb_inst_issue                    ;
-    _nb_inst_execute                   = nb_inst_execute                  ;
-    _nb_inst_reexecute                 = nb_inst_reexecute                ;
-    _nb_inst_commit                    = nb_inst_commit                   ;
-    _nb_inst_branch_complete           = nb_inst_branch_complete          ;
-    _nb_branch_speculated              = nb_branch_speculated             ;
-    _nb_rename_unit_select             = nb_rename_unit_select            ;
-    _nb_execute_loop_select            = nb_execute_loop_select           ;
-//  _size_general_data                 = size_general_data                ;
-//  _size_special_data                 = size_special_data                ;
-    _link_rename_unit_with_front_end   = link_rename_unit_with_front_end  ;
-    _size_re_order_buffer              = size_re_order_buffer             ;
-    _nb_re_order_buffer_bank           = nb_re_order_buffer_bank          ;
-    _retire_ooo_scheme                 = retire_ooo_scheme                ;
-    _commit_priority                   = commit_priority                  ;
-    _commit_load_balancing             = commit_load_balancing            ;
-    _size_issue_queue                  = size_issue_queue                 ;
-    _issue_queue_scheme                = issue_queue_scheme               ;
-    _nb_issue_queue_bank               = nb_issue_queue_bank              ;
-    _issue_priority                    = issue_priority                   ;
-    _issue_load_balancing              = issue_load_balancing             ;
-//  _table_routing                     = table_routing                    ;
-//  _table_issue_type                  = table_issue_type                 ;
-    _size_reexecute_queue              = size_reexecute_queue             ;
-    _rename_select_priority            = rename_select_priority           ;
-    _rename_select_load_balancing      = rename_select_load_balancing     ;
-    _rename_select_nb_front_end_select = rename_select_nb_front_end_select;
-    _nb_general_register               = nb_general_register              ;
-    _nb_special_register               = nb_special_register              ;
-    _rat_scheme                        = rat_scheme                       ;
-    _nb_reg_free                       = nb_reg_free                      ;
-    _nb_rename_unit_bank               = nb_rename_unit_bank              ;
-//  _size_read_counter                 = size_read_counter                ;
-    _nb_load_store_queue               = nb_load_store_queue              ;
-    _size_store_queue                  = size_store_queue                 ;
-    _size_load_queue                   = size_load_queue                  ;
-    _nb_inst_memory                    = nb_inst_memory                   ;
-    _link_load_store_unit_with_thread  = link_load_store_unit_with_thread ;
-    _implement_group                   = implement_group                  ;
-
+    _nb_front_end                        = nb_front_end                     ;
+    _nb_context                          = nb_context                       ;
+    _nb_rename_unit                      = nb_rename_unit                   ;
+    _nb_execute_loop                     = nb_execute_loop                  ;
+    _nb_inst_decod                       = nb_inst_decod                    ;
+    _nb_inst_insert                      = nb_inst_insert                   ;
+    _nb_inst_retire                      = nb_inst_retire                   ;
+//  _nb_inst_issue                       = nb_inst_issue                    ;
+    _nb_inst_execute                     = nb_inst_execute                  ;
+    _nb_inst_reexecute                   = nb_inst_reexecute                ;
+    _nb_inst_commit                      = nb_inst_commit                   ;
+    _nb_inst_branch_complete             = nb_inst_branch_complete          ;
+    _nb_branch_speculated                = nb_branch_speculated             ;
+    _nb_rename_unit_select               = nb_rename_unit_select            ;
+    _nb_execute_loop_select              = nb_execute_loop_select           ;
+//  _size_general_data                   = size_general_data                ;
+//  _size_special_data                   = size_special_data                ;
+    _link_rename_unit_with_front_end     = link_rename_unit_with_front_end  ;
+    _size_re_order_buffer                = size_re_order_buffer             ;
+    _nb_re_order_buffer_bank             = nb_re_order_buffer_bank          ;
+    _retire_ooo_scheme                   = retire_ooo_scheme                ;
+    _commit_priority                     = commit_priority                  ;
+    _commit_load_balancing               = commit_load_balancing            ;
+    _size_issue_queue                    = size_issue_queue                 ;
+    _issue_queue_scheme                  = issue_queue_scheme               ;
+    _nb_issue_queue_bank                 = nb_issue_queue_bank              ;
+    _issue_priority                      = issue_priority                   ;
+    _issue_load_balancing                = issue_load_balancing             ;
+//  _table_routing                       = table_routing                    ;
+//  _table_issue_type                    = table_issue_type                 ;
+    _size_reexecute_queue                = size_reexecute_queue             ;
+    _rename_select_priority              = rename_select_priority           ;
+    _rename_select_load_balancing        = rename_select_load_balancing     ;
+    _rename_select_nb_front_end_select   = rename_select_nb_front_end_select;
+    _nb_general_register                 = nb_general_register              ;
+    _nb_special_register                 = nb_special_register              ;
+    _rat_scheme                          = rat_scheme                       ;
+    _nb_reg_free                         = nb_reg_free                      ;
+    _nb_rename_unit_bank                 = nb_rename_unit_bank              ;
+//  _size_read_counter                   = size_read_counter                ;
+    _nb_load_store_queue                 = nb_load_store_queue              ;
+    _size_store_queue                    = size_store_queue                 ;
+    _size_load_queue                     = size_load_queue                  ;
+    _nb_inst_memory                      = nb_inst_memory                   ;
+    _link_load_store_unit_with_thread    = link_load_store_unit_with_thread ;
+    _implement_group                     = implement_group                  ;
     _nb_thread                           = nb_thread                          ;
     _translate_num_context_to_num_thread = translate_num_context_to_num_thread;
@@ -144,4 +143,5 @@
         _link_front_end_with_rename_unit[num_rename_unit].push_back(i);
       }
+
     _rename_unit_size_front_end_id                = new uint32_t    [_nb_rename_unit];
     _rename_unit_size_context_id                  = new uint32_t    [_nb_rename_unit];
@@ -197,9 +197,4 @@
           }
       }
-
-    ALLOC1(_commit_unit_rat_scheme,Trat_scheme_t,_nb_front_end);
-
-    for (uint32_t num_front_end=0; num_front_end<_nb_front_end; ++num_front_end)
-      _commit_unit_rat_scheme [num_front_end] = rat_scheme [_link_rename_unit_with_front_end [num_front_end]];
 
     _max_nb_context                = max<uint32_t>(_nb_context,_nb_front_end);
@@ -265,27 +260,28 @@
     _param_commit_unit           = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Parameters  
       (
-       _nb_front_end            ,
-       _nb_context              ,
-       _nb_rename_unit          ,
-       _size_re_order_buffer    ,
-       _nb_re_order_buffer_bank ,
-       _retire_ooo_scheme       ,
-       _nb_inst_insert          ,
-       _nb_inst_retire          ,
-       _nb_inst_commit          ,
-       _nb_inst_reexecute       ,
-       _nb_inst_branch_complete ,
-       _nb_branch_speculated    ,
-        size_nb_inst_decod      ,
-        size_general_data       ,
-        size_store_queue_ptr    ,
-        size_load_queue_ptr     ,
-        size_general_register   ,
-        size_special_register   ,
-       _commit_unit_rat_scheme  ,
-       _issue_priority          ,
-       _issue_load_balancing    ,
-       _nb_rename_unit_select   ,
-       _nb_thread               ,
+       _nb_front_end                   ,
+       _nb_context                     ,
+       _nb_rename_unit                 ,
+       _size_re_order_buffer           ,
+       _nb_re_order_buffer_bank        ,
+       _retire_ooo_scheme              ,
+       _nb_inst_insert                 ,
+       _nb_inst_retire                 ,
+       _nb_inst_commit                 ,
+       _nb_inst_reexecute              ,
+       _nb_inst_branch_complete        ,
+       _nb_branch_speculated           ,
+        size_nb_inst_decod             ,
+        size_general_data              ,
+        size_store_queue_ptr           ,
+        size_load_queue_ptr            ,
+        size_general_register          ,
+        size_special_register          ,
+       _rat_scheme                     ,
+       _link_front_end_with_rename_unit,
+       _issue_priority                 ,
+       _issue_load_balancing           ,
+       _nb_rename_unit_select          ,
+       _nb_thread                      ,
        _translate_num_context_to_num_thread
        );
@@ -430,6 +426,4 @@
     delete [] _link_front_end_with_rename_unit             ;
 
-    DELETE1(_commit_unit_rat_scheme,_nb_front_end);
-
     for (uint32_t i=0; i<_nb_rename_unit; i++)
     delete    _param_rename_unit [i]      ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_msg_error.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_msg_error.cpp	(revision 145)
@@ -36,5 +36,10 @@
           test.error(toString(_("Front_end [%d] is linked with invalid rename_unit.\n"),i));
         else
-          _is_link [x] = true;
+          {
+            if (_is_link [x])
+              test.error(toString(_("Front_end [%d] can't be connected with multiple rename_unit.\n"),i));
+            else
+              _is_link [x] = true;
+          }
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-min.cfg	(revision 144)
+++ 	(revision )
@@ -1,135 +1,0 @@
-Core
-32	32	+1	# size_general_data                                                                    
-2	2	+1	# size_special_data                                                                    
-1	1	+1	# nb_thread                                                                            
-1	1	+1	# size_ifetch_queue                       [0]       [nb_thread]                                  
-1	1	+1	# nb_inst_fetch                           [0]       [nb_thread]                                  
-2	2	+1	# ras_size_queue                          [0]       [nb_thread]                                  
-1	1	+1	# upt_size_queue                          [0]       [nb_thread]                                  
-1	1	+1	# ufpt_size_queue                         [0]       [nb_thread]                                  
-1	1	+1	# nb_decod_bloc                                                                           
-1	1	+1	# size_decod_queue                        [0]       [nb_decod_bloc]                              
-0	1	+1	# decod_queue_scheme                      [0]       [nb_decod_bloc]                              
-1	1	+1	# nb_inst_decod                           [0]       [nb_decod_bloc]                              
-1	1	+1	# nb_context_select                       [0]       [nb_decod_bloc]                              
-1	1	+1	# context_select_priority                 [0]       [nb_decod_bloc]                              
-1	1	+1	# context_select_load_balancing           [0]       [nb_decod_bloc]                              
-1	1	+1	# nb_rename_bloc                                                                          
-1	1	+1	# nb_inst_insert                          [0]       [nb_rename_bloc]
-1	1	+1	# nb_inst_retire                          [0]       [nb_rename_bloc]
-1	1	+1	# rename_select_priority                  [0]       [nb_rename_bloc]                             
-1	1	+1	# rename_select_load_balancing            [0]       [nb_rename_bloc]                             
-1	1	+1	# rename_select_nb_front_end_select       [0]       [nb_rename_bloc]                             
-64	64	+1	# nb_general_register                     [0]       [nb_rename_bloc]                             
-4	4	+1	# nb_special_register                     [0]       [nb_rename_bloc]                             
-1	1	+1	# nb_reg_free                             [0]       [nb_rename_bloc]                             
-1	1	+1	# nb_rename_unit_bank                     [0]       [nb_rename_bloc]                             
-1	1	+1	# nb_read_bloc                                                                            
-1	1	+1	# size_read_queue                         [0]       [nb_read_bloc]                               
-1	1	+1	# size_reservation_station                [0]       [nb_read_bloc]                               
-1	1	+1	# nb_inst_retire_reservation_station      [0]       [nb_read_bloc]                               
-1	1	+1	# nb_write_bloc                                                                           
-1	1	+1	# size_write_queue                        [0]       [nb_write_bloc]                              
-1	1	+1	# size_execute_queue                      [0]       [nb_write_bloc]                              
-0	0	+1	# nb_bypass_write                         [0]       [nb_write_bloc]                              
-0	0	+1	# write_queue_scheme                      [0]       [nb_write_bloc]                              
-1	1	+1	# nb_load_store_unit                                                                      
-2	2	+1	# size_store_queue                        [0]       [nb_load_store_unit]                         
-1	1	+1	# size_load_queue                         [0]       [nb_load_store_unit]                         
-1	1	+1	# size_speculative_access_queue           [0]       [nb_load_store_unit]                         
-1	1	+1	# nb_port_check                           [0]       [nb_load_store_unit]                         
-2	2	+1	# speculative_load                        [0]       [nb_load_store_unit]                         
-0	0	+1	# nb_bypass_memory                        [0]       [nb_load_store_unit]                         
-1	1	+1	# nb_cache_port                           [0]       [nb_load_store_unit]                         
-1	1	+1	# nb_inst_memory                          [0]       [nb_load_store_unit]                         
-1	1	+1	# nb_functionnal_unit                                                                     
-1	1	+1	# nb_inst_functionnal_unit                [0]       [nb_functionnal_unit]                        
-1	1	+1	# nb_icache_port                                                                          
-1	1	+1	# icache_access_priority                                                                  
-1	1	+1	# icache_access_load_balancing                                                            
-1	1	+1	# nb_dcache_port                                                                          
-1	1	+1	# dcache_access_priority                                                                  
-1	1	+1	# dcache_access_load_balancing                                                            
-1	1	+1	# nb_front_end                                                                            
-1	1	+1	# nb_context                              [0]       [nb_front_end]                               
-1	1	+1	# nb_decod_unit                           [0]       [nb_front_end]                               
-1	1	+1	# nb_inst_branch_predict                  [0]       [nb_front_end]                               
-1	1	+1	# nb_inst_branch_decod                    [0]       [nb_front_end]                               
-1	1	+1	# nb_inst_branch_update                   [0]       [nb_front_end]                               
-1	1	+1	# btb_size_queue                          [0]       [nb_front_end]                               
-1	1	+1	# btb_associativity                       [0]       [nb_front_end]                               
-2	2	+1	# btb_size_counter                        [0]       [nb_front_end]                               
-1	1	+1	# btb_victim_scheme                       [0]       [nb_front_end]                               
-1	1	+1	# dir_predictor_scheme                    [0]       [nb_front_end]                               
-1	1	+1	# dir_have_bht                            [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_have_bht                            [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_have_bht                            [0][2]    [nb_front_end][3]                            
-1	1	+1	# dir_bht_size_shifter                    [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_bht_size_shifter                    [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_bht_size_shifter                    [0][2]    [nb_front_end][3]                            
-1	1	+1	# dir_bht_nb_shifter                      [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_bht_nb_shifter                      [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_bht_nb_shifter                      [0][2]    [nb_front_end][3]                            
-1	1	+1	# dir_have_pht                            [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_have_pht                            [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_have_pht                            [0][2]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_size_counter                    [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_size_counter                    [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_size_counter                    [0][2]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_nb_counter                      [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_nb_counter                      [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_nb_counter                      [0][2]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_size_address_share              [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_size_address_share              [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_size_address_share              [0][2]    [nb_front_end][3]                            
-1	1	+1	# nb_ooo_engine                                                                           
-1	1	+1	# nb_rename_unit                          [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_inst_issue                           [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_inst_reexecute                       [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_inst_commit                          [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_inst_branch_complete                 [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_rename_unit_select                   [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_execute_loop_select                  [0]       [nb_ooo_engine]                              
-1	1	+1	# size_re_order_buffer                    [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_re_order_buffer_bank                 [0]       [nb_ooo_engine]                              
-1	1	+1	# commit_priority                         [0]       [nb_ooo_engine]                              
-1	1	+1	# commit_load_balancing                   [0]       [nb_ooo_engine]                              
-1	1	+1	# size_issue_queue                        [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_issue_queue_bank                     [0]       [nb_ooo_engine]                              
-1	1	+1	# issue_priority                          [0]       [nb_ooo_engine]                              
-1	1	+1	# issue_load_balancing                    [0]       [nb_ooo_engine]                              
-1	1	+1	# size_reexecute_queue                    [0]       [nb_ooo_engine]                              
-1	1	+1	# reexecute_priority                      [0]       [nb_ooo_engine]                              
-1	1	+1	# reexecute_load_balancing                [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_execute_loop                                                                         
-1	1	+1	# nb_read_unit                            [0]       [nb_execute_loop]                            
-2	2	+1	# nb_execute_unit                         [0]       [nb_execute_loop]                            
-1	1	+1	# nb_write_unit                           [0]       [nb_execute_loop]                            
-1	1	+1	# nb_gpr_bank                             [0]       [nb_execute_loop]                            
-1	1	+1	# nb_gpr_port_read_by_bank                [0]       [nb_execute_loop]                            
-1	1	+1	# nb_gpr_port_write_by_bank               [0]       [nb_execute_loop]                            
-1	1	+1	# nb_spr_bank                             [0]       [nb_execute_loop]                            
-1	1	+1	# nb_spr_port_read_by_bank                [0]       [nb_execute_loop]                            
-1	1	+1	# nb_spr_port_write_by_bank               [0]       [nb_execute_loop]                            
-1	1	+1	# execution_unit_to_write_unit_priority   [0]       [nb_execute_loop]                            
-1	1	+1	# read_unit_to_execution_unit_priority    [0]       [nb_execute_loop]                            
-0	0	+1	# link_context_with_thread                [0]       [nb_thread]                                  
-0	0	+1	# link_decod_unit_with_decod_bloc         [0]       [nb_decod_bloc]                              
-0	0	+1	# link_rename_unit_with_rename_bloc       [0]       [nb_rename_bloc]                             
-0	0	+1	# link_read_unit_with_read_bloc           [0]       [nb_read_bloc]                               
-0	0	+1	# link_write_unit_with_write_bloc         [0]       [nb_write_bloc]                              
-0	0	+1	# link_execute_unit_with_functionnal_unit [0]       [nb_functionnal_unit]                        
-1	1	+1	# link_execute_unit_with_load_store_unit  [0]       [nb_load_store_unit]                         
-0	0	+1	# link_decod_bloc_with_thread             [0]       [nb_thread]                                  
-0	0	+1	# link_rename_bloc_with_front_end         [0]       [nb_front_end]                               
-1	1	+1	# table_dispatch                          [0][0][0] [nb_ooo_engine][nb_inst_issue][nb_read_bloc] 
-1	1	+1	# link_read_bloc_and_load_store_unit      [0][0]    [nb_read_bloc][nb_load_store_unit]           
-1	1	+1	# link_read_bloc_and_functionnal_unit     [0][0]    [nb_read_bloc][nb_functionnal_unit]          
-1	1	+1	# link_write_bloc_and_load_store_unit     [0][0]    [nb_write_bloc][nb_load_store_unit]          
-1	1	+1	# link_write_bloc_and_functionnal_unit    [0][0]    [nb_write_bloc][nb_functionnal_unit]         
-0	0	+1	# link_load_store_unit_with_thread        [0]       [nb_thread]                                  
-1	1	+1	# link_thread_and_functionnal_unit        [0][0]    [nb_thread][nb_functionnal_unit]             
-0	0	+1	# link_icache_port_with_thread            [0]       [nb_thread]                                  
-0	0	+1	# link_dcache_port_with_load_store_unit   [0][0]    [nb_load_store_unit][nb_cache_port]          
-1	1	+1	# dispatch_priority                                                                    
-1	1	+1	# dispatch_load_balancing                                                              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-w1a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-w1a.cfg	(revision 144)
+++ 	(revision )
@@ -1,135 +1,0 @@
-Core
-32	32	+1	# size_general_data                                                                    
-2	2	+1	# size_special_data                                                                    
-1	1	+1	# nb_thread                                                                            
-4	4	+1	# size_ifetch_queue                       [0]       [nb_thread]                                  
-1	1	+1	# nb_inst_fetch                           [0]       [nb_thread]                                  
-4	4	+1	# ras_size_queue                          [0]       [nb_thread]                                  
-4	4	+1	# upt_size_queue                          [0]       [nb_thread]                                  
-2	2	+1	# ufpt_size_queue                         [0]       [nb_thread]                                  
-1	1	+1	# nb_decod_bloc                                                                           
-4	4	+1	# size_decod_queue                        [0]       [nb_decod_bloc]                              
-0	1	+1	# decod_queue_scheme                      [0]       [nb_decod_bloc]                              
-1	1	+1	# nb_inst_decod                           [0]       [nb_decod_bloc]                              
-1	1	+1	# nb_context_select                       [0]       [nb_decod_bloc]                              
-1	1	+1	# context_select_priority                 [0]       [nb_decod_bloc]                              
-1	1	+1	# context_select_load_balancing           [0]       [nb_decod_bloc]                              
-1	1	+1	# nb_rename_bloc                                                                          
-1	1	+1	# nb_inst_insert                          [0]       [nb_rename_bloc]
-1	1	+1	# nb_inst_retire                          [0]       [nb_rename_bloc]
-1	1	+1	# rename_select_priority                  [0]       [nb_rename_bloc]                             
-1	1	+1	# rename_select_load_balancing            [0]       [nb_rename_bloc]                             
-1	1	+1	# rename_select_nb_front_end_select       [0]       [nb_rename_bloc]                             
-64	64	+1	# nb_general_register                     [0]       [nb_rename_bloc]                             
-4	4	+1	# nb_special_register                     [0]       [nb_rename_bloc]                             
-1	1	+1	# nb_reg_free                             [0]       [nb_rename_bloc]                             
-1	1	+1	# nb_rename_unit_bank                     [0]       [nb_rename_bloc]                             
-1	1	+1	# nb_read_bloc                                                                            
-4	4	+1	# size_read_queue                         [0]       [nb_read_bloc]                               
-4	4	+1	# size_reservation_station                [0]       [nb_read_bloc]                               
-1	1	+1	# nb_inst_retire_reservation_station      [0]       [nb_read_bloc]                               
-1	1	+1	# nb_write_bloc                                                                           
-4	4	+1	# size_write_queue                        [0]       [nb_write_bloc]                              
-4	4	+1	# size_execute_queue                      [0]       [nb_write_bloc]                              
-0	0	+1	# nb_bypass_write                         [0]       [nb_write_bloc]                              
-0	0	+1	# write_queue_scheme                      [0]       [nb_write_bloc]                              
-1	1	+1	# nb_load_store_unit                                                                      
-4	4	+1	# size_store_queue                        [0]       [nb_load_store_unit]                         
-4	4	+1	# size_load_queue                         [0]       [nb_load_store_unit]                         
-4	4	+1	# size_speculative_access_queue           [0]       [nb_load_store_unit]                         
-1	1	+1	# nb_port_check                           [0]       [nb_load_store_unit]                         
-2	2	+1	# speculative_load                        [0]       [nb_load_store_unit]                         
-0	0	+1	# nb_bypass_memory                        [0]       [nb_load_store_unit]                         
-1	1	+1	# nb_cache_port                           [0]       [nb_load_store_unit]                         
-1	1	+1	# nb_inst_memory                          [0]       [nb_load_store_unit]                         
-1	1	+1	# nb_functionnal_unit                                                                     
-1	1	+1	# nb_inst_functionnal_unit                [0]       [nb_functionnal_unit]                        
-1	1	+1	# nb_icache_port                                                                          
-1	1	+1	# icache_access_priority                                                                  
-1	1	+1	# icache_access_load_balancing                                                            
-1	1	+1	# nb_dcache_port                                                                          
-1	1	+1	# dcache_access_priority                                                                  
-1	1	+1	# dcache_access_load_balancing                                                            
-1	1	+1	# nb_front_end                                                                            
-1	1	+1	# nb_context                              [0]       [nb_front_end]                               
-1	1	+1	# nb_decod_unit                           [0]       [nb_front_end]                               
-1	1	+1	# nb_inst_branch_predict                  [0]       [nb_front_end]                               
-1	1	+1	# nb_inst_branch_decod                    [0]       [nb_front_end]                               
-1	1	+1	# nb_inst_branch_update                   [0]       [nb_front_end]                               
-32	32	+1	# btb_size_queue                          [0]       [nb_front_end]                               
-2	2	+1	# btb_associativity                       [0]       [nb_front_end]                               
-2	2	+1	# btb_size_counter                        [0]       [nb_front_end]                               
-3	3	+1	# btb_victim_scheme                       [0]       [nb_front_end]                               
-1	1	+1	# dir_predictor_scheme                    [0]       [nb_front_end]                               
-1	1	+1	# dir_have_bht                            [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_have_bht                            [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_have_bht                            [0][2]    [nb_front_end][3]                            
-1	1	+1	# dir_bht_size_shifter                    [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_bht_size_shifter                    [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_bht_size_shifter                    [0][2]    [nb_front_end][3]                            
-1	1	+1	# dir_bht_nb_shifter                      [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_bht_nb_shifter                      [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_bht_nb_shifter                      [0][2]    [nb_front_end][3]                            
-1	1	+1	# dir_have_pht                            [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_have_pht                            [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_have_pht                            [0][2]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_size_counter                    [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_size_counter                    [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_size_counter                    [0][2]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_nb_counter                      [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_nb_counter                      [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_nb_counter                      [0][2]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_size_address_share              [0][0]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_size_address_share              [0][1]    [nb_front_end][3]                            
-1	1	+1	# dir_pht_size_address_share              [0][2]    [nb_front_end][3]                            
-1	1	+1	# nb_ooo_engine                                                                           
-1	1	+1	# nb_rename_unit                          [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_inst_issue                           [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_inst_reexecute                       [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_inst_commit                          [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_inst_branch_complete                 [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_rename_unit_select                   [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_execute_loop_select                  [0]       [nb_ooo_engine]                              
-32	32	+1	# size_re_order_buffer                    [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_re_order_buffer_bank                 [0]       [nb_ooo_engine]                              
-1	1	+1	# commit_priority                         [0]       [nb_ooo_engine]                              
-1	1	+1	# commit_load_balancing                   [0]       [nb_ooo_engine]                              
-4	4	+1	# size_issue_queue                        [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_issue_queue_bank                     [0]       [nb_ooo_engine]                              
-1	1	+1	# issue_priority                          [0]       [nb_ooo_engine]                              
-1	1	+1	# issue_load_balancing                    [0]       [nb_ooo_engine]                              
-4	4	+1	# size_reexecute_queue                    [0]       [nb_ooo_engine]                              
-1	1	+1	# reexecute_priority                      [0]       [nb_ooo_engine]                              
-1	1	+1	# reexecute_load_balancing                [0]       [nb_ooo_engine]                              
-1	1	+1	# nb_execute_loop                                                                         
-1	1	+1	# nb_read_unit                            [0]       [nb_execute_loop]                            
-2	2	+1	# nb_execute_unit                         [0]       [nb_execute_loop]                            
-1	1	+1	# nb_write_unit                           [0]       [nb_execute_loop]                            
-1	1	+1	# nb_gpr_bank                             [0]       [nb_execute_loop]                            
-1	1	+1	# nb_gpr_port_read_by_bank                [0]       [nb_execute_loop]                            
-1	1	+1	# nb_gpr_port_write_by_bank               [0]       [nb_execute_loop]                            
-1	1	+1	# nb_spr_bank                             [0]       [nb_execute_loop]                            
-1	1	+1	# nb_spr_port_read_by_bank                [0]       [nb_execute_loop]                            
-1	1	+1	# nb_spr_port_write_by_bank               [0]       [nb_execute_loop]                            
-1	1	+1	# execution_unit_to_write_unit_priority   [0]       [nb_execute_loop]                            
-1	1	+1	# read_unit_to_execution_unit_priority    [0]       [nb_execute_loop]                            
-0	0	+1	# link_context_with_thread                [0]       [nb_thread]                                  
-0	0	+1	# link_decod_unit_with_decod_bloc         [0]       [nb_decod_bloc]                              
-0	0	+1	# link_rename_unit_with_rename_bloc       [0]       [nb_rename_bloc]                             
-0	0	+1	# link_read_unit_with_read_bloc           [0]       [nb_read_bloc]                               
-0	0	+1	# link_write_unit_with_write_bloc         [0]       [nb_write_bloc]                              
-0	0	+1	# link_execute_unit_with_functionnal_unit [0]       [nb_functionnal_unit]                        
-1	1	+1	# link_execute_unit_with_load_store_unit  [0]       [nb_load_store_unit]                         
-0	0	+1	# link_decod_bloc_with_thread             [0]       [nb_thread]                                  
-0	0	+1	# link_rename_bloc_with_front_end         [0]       [nb_front_end]                               
-1	1	+1	# table_dispatch                          [0][0][0] [nb_ooo_engine][nb_inst_issue][nb_read_bloc] 
-1	1	+1	# link_read_bloc_and_load_store_unit      [0][0]    [nb_read_bloc][nb_load_store_unit]           
-1	1	+1	# link_read_bloc_and_functionnal_unit     [0][0]    [nb_read_bloc][nb_functionnal_unit]          
-1	1	+1	# link_write_bloc_and_load_store_unit     [0][0]    [nb_write_bloc][nb_load_store_unit]          
-1	1	+1	# link_write_bloc_and_functionnal_unit    [0][0]    [nb_write_bloc][nb_functionnal_unit]         
-0	0	+1	# link_load_store_unit_with_thread        [0]       [nb_thread]                                  
-1	1	+1	# link_thread_and_functionnal_unit        [0][0]    [nb_thread][nb_functionnal_unit]             
-0	0	+1	# link_icache_port_with_thread            [0]       [nb_thread]                                  
-0	0	+1	# link_dcache_port_with_load_store_unit   [0][0]    [nb_load_store_unit][nb_cache_port]          
-1	1	+1	# dispatch_priority                                                                    
-1	1	+1	# dispatch_load_balancing                                                              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/configuration/config-min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/configuration/config-min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/configuration/config-min.gen	(revision 145)
@@ -0,0 +1,135 @@
+Core
+32	32	+1	# size_general_data                                                                    
+2	2	+1	# size_special_data                                                                    
+1	1	+1	# nb_thread                                                                            
+1	1	+1	# size_ifetch_queue                       [0]       [nb_thread]                                  
+1	1	+1	# nb_inst_fetch                           [0]       [nb_thread]                                  
+2	2	+1	# ras_size_queue                          [0]       [nb_thread]                                  
+1	1	+1	# upt_size_queue                          [0]       [nb_thread]                                  
+1	1	+1	# ufpt_size_queue                         [0]       [nb_thread]                                  
+1	1	+1	# nb_decod_bloc                                                                           
+1	1	+1	# size_decod_queue                        [0]       [nb_decod_bloc]                              
+0	1	+1	# decod_queue_scheme                      [0]       [nb_decod_bloc]                              
+1	1	+1	# nb_inst_decod                           [0]       [nb_decod_bloc]                              
+1	1	+1	# nb_context_select                       [0]       [nb_decod_bloc]                              
+1	1	+1	# context_select_priority                 [0]       [nb_decod_bloc]                              
+1	1	+1	# context_select_load_balancing           [0]       [nb_decod_bloc]                              
+1	1	+1	# nb_rename_bloc                                                                          
+1	1	+1	# nb_inst_insert                          [0]       [nb_rename_bloc]
+1	1	+1	# nb_inst_retire                          [0]       [nb_rename_bloc]
+1	1	+1	# rename_select_priority                  [0]       [nb_rename_bloc]                             
+1	1	+1	# rename_select_load_balancing            [0]       [nb_rename_bloc]                             
+1	1	+1	# rename_select_nb_front_end_select       [0]       [nb_rename_bloc]                             
+64	64	+1	# nb_general_register                     [0]       [nb_rename_bloc]                             
+4	4	+1	# nb_special_register                     [0]       [nb_rename_bloc]                             
+1	1	+1	# nb_reg_free                             [0]       [nb_rename_bloc]                             
+1	1	+1	# nb_rename_unit_bank                     [0]       [nb_rename_bloc]                             
+1	1	+1	# nb_read_bloc                                                                            
+1	1	+1	# size_read_queue                         [0]       [nb_read_bloc]                               
+1	1	+1	# size_reservation_station                [0]       [nb_read_bloc]                               
+1	1	+1	# nb_inst_retire_reservation_station      [0]       [nb_read_bloc]                               
+1	1	+1	# nb_write_bloc                                                                           
+1	1	+1	# size_write_queue                        [0]       [nb_write_bloc]                              
+1	1	+1	# size_execute_queue                      [0]       [nb_write_bloc]                              
+0	0	+1	# nb_bypass_write                         [0]       [nb_write_bloc]                              
+0	0	+1	# write_queue_scheme                      [0]       [nb_write_bloc]                              
+1	1	+1	# nb_load_store_unit                                                                      
+2	2	+1	# size_store_queue                        [0]       [nb_load_store_unit]                         
+1	1	+1	# size_load_queue                         [0]       [nb_load_store_unit]                         
+1	1	+1	# size_speculative_access_queue           [0]       [nb_load_store_unit]                         
+1	1	+1	# nb_port_check                           [0]       [nb_load_store_unit]                         
+2	2	+1	# speculative_load                        [0]       [nb_load_store_unit]                         
+0	0	+1	# nb_bypass_memory                        [0]       [nb_load_store_unit]                         
+1	1	+1	# nb_cache_port                           [0]       [nb_load_store_unit]                         
+1	1	+1	# nb_inst_memory                          [0]       [nb_load_store_unit]                         
+1	1	+1	# nb_functionnal_unit                                                                     
+1	1	+1	# nb_inst_functionnal_unit                [0]       [nb_functionnal_unit]                        
+1	1	+1	# nb_icache_port                                                                          
+1	1	+1	# icache_access_priority                                                                  
+1	1	+1	# icache_access_load_balancing                                                            
+1	1	+1	# nb_dcache_port                                                                          
+1	1	+1	# dcache_access_priority                                                                  
+1	1	+1	# dcache_access_load_balancing                                                            
+1	1	+1	# nb_front_end                                                                            
+1	1	+1	# nb_context                              [0]       [nb_front_end]                               
+1	1	+1	# nb_decod_unit                           [0]       [nb_front_end]                               
+1	1	+1	# nb_inst_branch_predict                  [0]       [nb_front_end]                               
+1	1	+1	# nb_inst_branch_decod                    [0]       [nb_front_end]                               
+1	1	+1	# nb_inst_branch_update                   [0]       [nb_front_end]                               
+1	1	+1	# btb_size_queue                          [0]       [nb_front_end]                               
+1	1	+1	# btb_associativity                       [0]       [nb_front_end]                               
+2	2	+1	# btb_size_counter                        [0]       [nb_front_end]                               
+1	1	+1	# btb_victim_scheme                       [0]       [nb_front_end]                               
+1	1	+1	# dir_predictor_scheme                    [0]       [nb_front_end]                               
+1	1	+1	# dir_have_bht                            [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_have_bht                            [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_have_bht                            [0][2]    [nb_front_end][3]                            
+1	1	+1	# dir_bht_size_shifter                    [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_bht_size_shifter                    [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_bht_size_shifter                    [0][2]    [nb_front_end][3]                            
+1	1	+1	# dir_bht_nb_shifter                      [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_bht_nb_shifter                      [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_bht_nb_shifter                      [0][2]    [nb_front_end][3]                            
+1	1	+1	# dir_have_pht                            [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_have_pht                            [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_have_pht                            [0][2]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_size_counter                    [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_size_counter                    [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_size_counter                    [0][2]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_nb_counter                      [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_nb_counter                      [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_nb_counter                      [0][2]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_size_address_share              [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_size_address_share              [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_size_address_share              [0][2]    [nb_front_end][3]                            
+1	1	+1	# nb_ooo_engine                                                                           
+1	1	+1	# nb_rename_unit                          [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_inst_issue                           [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_inst_reexecute                       [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_inst_commit                          [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_inst_branch_complete                 [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_rename_unit_select                   [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_execute_loop_select                  [0]       [nb_ooo_engine]                              
+1	1	+1	# size_re_order_buffer                    [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_re_order_buffer_bank                 [0]       [nb_ooo_engine]                              
+1	1	+1	# commit_priority                         [0]       [nb_ooo_engine]                              
+1	1	+1	# commit_load_balancing                   [0]       [nb_ooo_engine]                              
+1	1	+1	# size_issue_queue                        [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_issue_queue_bank                     [0]       [nb_ooo_engine]                              
+1	1	+1	# issue_priority                          [0]       [nb_ooo_engine]                              
+1	1	+1	# issue_load_balancing                    [0]       [nb_ooo_engine]                              
+1	1	+1	# size_reexecute_queue                    [0]       [nb_ooo_engine]                              
+1	1	+1	# reexecute_priority                      [0]       [nb_ooo_engine]                              
+1	1	+1	# reexecute_load_balancing                [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_execute_loop                                                                         
+1	1	+1	# nb_read_unit                            [0]       [nb_execute_loop]                            
+2	2	+1	# nb_execute_unit                         [0]       [nb_execute_loop]                            
+1	1	+1	# nb_write_unit                           [0]       [nb_execute_loop]                            
+1	1	+1	# nb_gpr_bank                             [0]       [nb_execute_loop]                            
+1	1	+1	# nb_gpr_port_read_by_bank                [0]       [nb_execute_loop]                            
+1	1	+1	# nb_gpr_port_write_by_bank               [0]       [nb_execute_loop]                            
+1	1	+1	# nb_spr_bank                             [0]       [nb_execute_loop]                            
+1	1	+1	# nb_spr_port_read_by_bank                [0]       [nb_execute_loop]                            
+1	1	+1	# nb_spr_port_write_by_bank               [0]       [nb_execute_loop]                            
+1	1	+1	# execution_unit_to_write_unit_priority   [0]       [nb_execute_loop]                            
+1	1	+1	# read_unit_to_execution_unit_priority    [0]       [nb_execute_loop]                            
+0	0	+1	# link_context_with_thread                [0]       [nb_thread]                                  
+0	0	+1	# link_decod_unit_with_decod_bloc         [0]       [nb_decod_bloc]                              
+0	0	+1	# link_rename_unit_with_rename_bloc       [0]       [nb_rename_bloc]                             
+0	0	+1	# link_read_unit_with_read_bloc           [0]       [nb_read_bloc]                               
+0	0	+1	# link_write_unit_with_write_bloc         [0]       [nb_write_bloc]                              
+0	0	+1	# link_execute_unit_with_functionnal_unit [0]       [nb_functionnal_unit]                        
+1	1	+1	# link_execute_unit_with_load_store_unit  [0]       [nb_load_store_unit]                         
+0	0	+1	# link_decod_bloc_with_thread             [0]       [nb_thread]                                  
+0	0	+1	# link_rename_bloc_with_front_end         [0]       [nb_front_end]                               
+1	1	+1	# table_dispatch                          [0][0][0] [nb_ooo_engine][nb_inst_issue][nb_read_bloc] 
+1	1	+1	# link_read_bloc_and_load_store_unit      [0][0]    [nb_read_bloc][nb_load_store_unit]           
+1	1	+1	# link_read_bloc_and_functionnal_unit     [0][0]    [nb_read_bloc][nb_functionnal_unit]          
+1	1	+1	# link_write_bloc_and_load_store_unit     [0][0]    [nb_write_bloc][nb_load_store_unit]          
+1	1	+1	# link_write_bloc_and_functionnal_unit    [0][0]    [nb_write_bloc][nb_functionnal_unit]         
+0	0	+1	# link_load_store_unit_with_thread        [0]       [nb_thread]                                  
+1	1	+1	# link_thread_and_functionnal_unit        [0][0]    [nb_thread][nb_functionnal_unit]             
+0	0	+1	# link_icache_port_with_thread            [0]       [nb_thread]                                  
+0	0	+1	# link_dcache_port_with_load_store_unit   [0][0]    [nb_load_store_unit][nb_cache_port]          
+1	1	+1	# dispatch_priority                                                                    
+1	1	+1	# dispatch_load_balancing                                                              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/configuration/config-w1a.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/configuration/config-w1a.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/configuration/config-w1a.gen	(revision 145)
@@ -0,0 +1,135 @@
+Core
+32	32	+1	# size_general_data                                                                    
+2	2	+1	# size_special_data                                                                    
+1	1	+1	# nb_thread                                                                            
+4	4	+1	# size_ifetch_queue                       [0]       [nb_thread]                                  
+1	1	+1	# nb_inst_fetch                           [0]       [nb_thread]                                  
+4	4	+1	# ras_size_queue                          [0]       [nb_thread]                                  
+4	4	+1	# upt_size_queue                          [0]       [nb_thread]                                  
+2	2	+1	# ufpt_size_queue                         [0]       [nb_thread]                                  
+1	1	+1	# nb_decod_bloc                                                                           
+4	4	+1	# size_decod_queue                        [0]       [nb_decod_bloc]                              
+0	1	+1	# decod_queue_scheme                      [0]       [nb_decod_bloc]                              
+1	1	+1	# nb_inst_decod                           [0]       [nb_decod_bloc]                              
+1	1	+1	# nb_context_select                       [0]       [nb_decod_bloc]                              
+1	1	+1	# context_select_priority                 [0]       [nb_decod_bloc]                              
+1	1	+1	# context_select_load_balancing           [0]       [nb_decod_bloc]                              
+1	1	+1	# nb_rename_bloc                                                                          
+1	1	+1	# nb_inst_insert                          [0]       [nb_rename_bloc]
+1	1	+1	# nb_inst_retire                          [0]       [nb_rename_bloc]
+1	1	+1	# rename_select_priority                  [0]       [nb_rename_bloc]                             
+1	1	+1	# rename_select_load_balancing            [0]       [nb_rename_bloc]                             
+1	1	+1	# rename_select_nb_front_end_select       [0]       [nb_rename_bloc]                             
+64	64	+1	# nb_general_register                     [0]       [nb_rename_bloc]                             
+4	4	+1	# nb_special_register                     [0]       [nb_rename_bloc]                             
+1	1	+1	# nb_reg_free                             [0]       [nb_rename_bloc]                             
+1	1	+1	# nb_rename_unit_bank                     [0]       [nb_rename_bloc]                             
+1	1	+1	# nb_read_bloc                                                                            
+4	4	+1	# size_read_queue                         [0]       [nb_read_bloc]                               
+4	4	+1	# size_reservation_station                [0]       [nb_read_bloc]                               
+1	1	+1	# nb_inst_retire_reservation_station      [0]       [nb_read_bloc]                               
+1	1	+1	# nb_write_bloc                                                                           
+4	4	+1	# size_write_queue                        [0]       [nb_write_bloc]                              
+4	4	+1	# size_execute_queue                      [0]       [nb_write_bloc]                              
+0	0	+1	# nb_bypass_write                         [0]       [nb_write_bloc]                              
+0	0	+1	# write_queue_scheme                      [0]       [nb_write_bloc]                              
+1	1	+1	# nb_load_store_unit                                                                      
+4	4	+1	# size_store_queue                        [0]       [nb_load_store_unit]                         
+4	4	+1	# size_load_queue                         [0]       [nb_load_store_unit]                         
+4	4	+1	# size_speculative_access_queue           [0]       [nb_load_store_unit]                         
+1	1	+1	# nb_port_check                           [0]       [nb_load_store_unit]                         
+2	2	+1	# speculative_load                        [0]       [nb_load_store_unit]                         
+0	0	+1	# nb_bypass_memory                        [0]       [nb_load_store_unit]                         
+1	1	+1	# nb_cache_port                           [0]       [nb_load_store_unit]                         
+1	1	+1	# nb_inst_memory                          [0]       [nb_load_store_unit]                         
+1	1	+1	# nb_functionnal_unit                                                                     
+1	1	+1	# nb_inst_functionnal_unit                [0]       [nb_functionnal_unit]                        
+1	1	+1	# nb_icache_port                                                                          
+1	1	+1	# icache_access_priority                                                                  
+1	1	+1	# icache_access_load_balancing                                                            
+1	1	+1	# nb_dcache_port                                                                          
+1	1	+1	# dcache_access_priority                                                                  
+1	1	+1	# dcache_access_load_balancing                                                            
+1	1	+1	# nb_front_end                                                                            
+1	1	+1	# nb_context                              [0]       [nb_front_end]                               
+1	1	+1	# nb_decod_unit                           [0]       [nb_front_end]                               
+1	1	+1	# nb_inst_branch_predict                  [0]       [nb_front_end]                               
+1	1	+1	# nb_inst_branch_decod                    [0]       [nb_front_end]                               
+1	1	+1	# nb_inst_branch_update                   [0]       [nb_front_end]                               
+32	32	+1	# btb_size_queue                          [0]       [nb_front_end]                               
+2	2	+1	# btb_associativity                       [0]       [nb_front_end]                               
+2	2	+1	# btb_size_counter                        [0]       [nb_front_end]                               
+3	3	+1	# btb_victim_scheme                       [0]       [nb_front_end]                               
+1	1	+1	# dir_predictor_scheme                    [0]       [nb_front_end]                               
+1	1	+1	# dir_have_bht                            [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_have_bht                            [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_have_bht                            [0][2]    [nb_front_end][3]                            
+1	1	+1	# dir_bht_size_shifter                    [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_bht_size_shifter                    [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_bht_size_shifter                    [0][2]    [nb_front_end][3]                            
+1	1	+1	# dir_bht_nb_shifter                      [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_bht_nb_shifter                      [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_bht_nb_shifter                      [0][2]    [nb_front_end][3]                            
+1	1	+1	# dir_have_pht                            [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_have_pht                            [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_have_pht                            [0][2]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_size_counter                    [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_size_counter                    [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_size_counter                    [0][2]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_nb_counter                      [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_nb_counter                      [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_nb_counter                      [0][2]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_size_address_share              [0][0]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_size_address_share              [0][1]    [nb_front_end][3]                            
+1	1	+1	# dir_pht_size_address_share              [0][2]    [nb_front_end][3]                            
+1	1	+1	# nb_ooo_engine                                                                           
+1	1	+1	# nb_rename_unit                          [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_inst_issue                           [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_inst_reexecute                       [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_inst_commit                          [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_inst_branch_complete                 [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_rename_unit_select                   [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_execute_loop_select                  [0]       [nb_ooo_engine]                              
+32	32	+1	# size_re_order_buffer                    [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_re_order_buffer_bank                 [0]       [nb_ooo_engine]                              
+1	1	+1	# commit_priority                         [0]       [nb_ooo_engine]                              
+1	1	+1	# commit_load_balancing                   [0]       [nb_ooo_engine]                              
+4	4	+1	# size_issue_queue                        [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_issue_queue_bank                     [0]       [nb_ooo_engine]                              
+1	1	+1	# issue_priority                          [0]       [nb_ooo_engine]                              
+1	1	+1	# issue_load_balancing                    [0]       [nb_ooo_engine]                              
+4	4	+1	# size_reexecute_queue                    [0]       [nb_ooo_engine]                              
+1	1	+1	# reexecute_priority                      [0]       [nb_ooo_engine]                              
+1	1	+1	# reexecute_load_balancing                [0]       [nb_ooo_engine]                              
+1	1	+1	# nb_execute_loop                                                                         
+1	1	+1	# nb_read_unit                            [0]       [nb_execute_loop]                            
+2	2	+1	# nb_execute_unit                         [0]       [nb_execute_loop]                            
+1	1	+1	# nb_write_unit                           [0]       [nb_execute_loop]                            
+1	1	+1	# nb_gpr_bank                             [0]       [nb_execute_loop]                            
+1	1	+1	# nb_gpr_port_read_by_bank                [0]       [nb_execute_loop]                            
+1	1	+1	# nb_gpr_port_write_by_bank               [0]       [nb_execute_loop]                            
+1	1	+1	# nb_spr_bank                             [0]       [nb_execute_loop]                            
+1	1	+1	# nb_spr_port_read_by_bank                [0]       [nb_execute_loop]                            
+1	1	+1	# nb_spr_port_write_by_bank               [0]       [nb_execute_loop]                            
+1	1	+1	# execution_unit_to_write_unit_priority   [0]       [nb_execute_loop]                            
+1	1	+1	# read_unit_to_execution_unit_priority    [0]       [nb_execute_loop]                            
+0	0	+1	# link_context_with_thread                [0]       [nb_thread]                                  
+0	0	+1	# link_decod_unit_with_decod_bloc         [0]       [nb_decod_bloc]                              
+0	0	+1	# link_rename_unit_with_rename_bloc       [0]       [nb_rename_bloc]                             
+0	0	+1	# link_read_unit_with_read_bloc           [0]       [nb_read_bloc]                               
+0	0	+1	# link_write_unit_with_write_bloc         [0]       [nb_write_bloc]                              
+0	0	+1	# link_execute_unit_with_functionnal_unit [0]       [nb_functionnal_unit]                        
+1	1	+1	# link_execute_unit_with_load_store_unit  [0]       [nb_load_store_unit]                         
+0	0	+1	# link_decod_bloc_with_thread             [0]       [nb_thread]                                  
+0	0	+1	# link_rename_bloc_with_front_end         [0]       [nb_front_end]                               
+1	1	+1	# table_dispatch                          [0][0][0] [nb_ooo_engine][nb_inst_issue][nb_read_bloc] 
+1	1	+1	# link_read_bloc_and_load_store_unit      [0][0]    [nb_read_bloc][nb_load_store_unit]           
+1	1	+1	# link_read_bloc_and_functionnal_unit     [0][0]    [nb_read_bloc][nb_functionnal_unit]          
+1	1	+1	# link_write_bloc_and_load_store_unit     [0][0]    [nb_write_bloc][nb_load_store_unit]          
+1	1	+1	# link_write_bloc_and_functionnal_unit    [0][0]    [nb_write_bloc][nb_functionnal_unit]         
+0	0	+1	# link_load_store_unit_with_thread        [0]       [nb_thread]                                  
+1	1	+1	# link_thread_and_functionnal_unit        [0][0]    [nb_thread][nb_functionnal_unit]             
+0	0	+1	# link_icache_port_with_thread            [0]       [nb_thread]                                  
+0	0	+1	# link_dcache_port_with_load_store_unit   [0][0]    [nb_load_store_unit][nb_cache_port]          
+1	1	+1	# dispatch_priority                                                                    
+1	1	+1	# dispatch_load_balancing                                                              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/main.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/main.cpp	(revision 145)
@@ -768,5 +768,6 @@
 
          _dispatch_priority                             ,
-         _dispatch_load_balancing                       
+         _dispatch_load_balancing                       ,
+         true // is_toplevel
          );
       
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Core.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Core.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Core.h	(revision 145)
@@ -31,4 +31,5 @@
 #endif
 #include "Behavioural/include/Usage.h"
+// #include "Behavioural/include/Function_pointer.h"
 
 #include "Common/include/ToString.h"
@@ -131,5 +132,6 @@
 #endif
    Parameters                                  * param,
-   morpheo::behavioural::Tusage_t                usage
+   morpheo::behavioural::Tusage_t                usage// ,
+   // morpheo::behavioural::Function_pointer      * function_pointer
    );
   public  :          ~Core             (void);
@@ -140,6 +142,11 @@
 						   morpheo::behavioural::Parameters_Statistics * param_statistics
 #else
-						   void
+                                                   void
 #endif
+
+// #ifdef STATISTICS
+// 						   morpheo::behavioural::Parameters_Statistics * param_statistics,
+// #endif
+//                                                    morpheo::behavioural::Function_pointer      * function_pointer
 						   );
   private : void        deallocation              (void);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h	(revision 145)
@@ -538,5 +538,6 @@
 
   Tpriority_t             dispatch_priority                             ,
-  Tload_balancing_t       dispatch_load_balancing                       
+  Tload_balancing_t       dispatch_load_balancing                       ,
+  bool                    is_toplevel=false
                         );
 //   public : Parameters  (Parameters & param) ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core.cpp	(revision 145)
@@ -25,6 +25,7 @@
    morpheo::behavioural::Parameters_Statistics * param_statistics,
 #endif
-   morpheo::behavioural::core::Parameters * param,
-   morpheo::behavioural::Tusage_t usage
+   Parameters * param,
+   morpheo::behavioural::Tusage_t           usage// ,
+   // morpheo::behavioural::Function_pointer * function_pointer
    ):
     _name              (name)
@@ -48,4 +49,5 @@
 		param_statistics
 #endif
+                // function_pointer
 		);
 
@@ -72,4 +74,7 @@
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
+
+        // if (function_pointer==NULL)
+        //   {
 	log_printf(INFO,Core,FUNCTION,_("<%s> Method - transition"),_name.c_str());
 
@@ -77,8 +82,14 @@
 	dont_initialize ();
 	sensitive << (*(in_CLOCK)).pos();
-	
+
 # ifdef SYSTEMCASS_SPECIFIC
 	// List dependency information
 # endif    
+        //   }
+        // else
+        //   {
+        //     function_pointer->transition_add(static_cast<f_t>(&morpheo::behavioural::core::Core::transition));
+        //   }
+
       }
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp	(revision 145)
@@ -24,4 +24,10 @@
    void
 #endif
+
+// #ifdef STATISTICS
+//    morpheo::behavioural::Parameters_Statistics * param_statistics,
+// #endif
+//    morpheo::behavioural::Function_pointer      * function_pointer
+
    )
   {
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_transition.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_transition.cpp	(revision 145)
@@ -10,8 +10,7 @@
 #include "Behavioural/Core/include/Core.h"
 
-namespace morpheo                    {
+namespace morpheo {
 namespace behavioural {
 namespace core {
-
 
 #undef  FUNCTION
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp	(revision 145)
@@ -248,5 +248,6 @@
 
   Tpriority_t             dispatch_priority                             ,
-  Tload_balancing_t       dispatch_load_balancing                       
+  Tload_balancing_t       dispatch_load_balancing                       ,
+  bool                    is_toplevel
                         )
   {
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,4 +1,0 @@
-Comparator
-32      32      *2      # size_data
-0       1       +1      # is_signed
-0       5       +1      # type
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,4 @@
+Comparator
+32      32      *2      # size_data
+0       1       +1      # is_signed
+0       5       +1      # type
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,3 +1,0 @@
-Counter
-2	31	*2	# size_data
-1	6	+1	# nb_port
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,3 @@
+Counter
+2	31	*2	# size_data
+1	6	+1	# nb_port
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,1 +1,0 @@
-Divider
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Divider/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,1 @@
+Divider
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,5 +1,0 @@
-Multiplier
-16       32     *2      #size_data
-0        1      +1      #sign
-6       32      *3      #latency
-1        1      +1      #delay
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Multiplier/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,5 @@
+Multiplier
+16       32     *2      #size_data
+0        1      +1      #sign
+6       32      *3      #latency
+1        1      +1      #delay
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/config_mono_gpr.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/config_mono_gpr.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-Priority
-0	1	+1	# priority      
-0	1	+1	# load_balancing
-1	1	+1	# nb_grp                 
-1	16	*4	# nb_elt         [0] [nb_grp]
-1	1	+1	# nb_grp_select          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/config_multi_gpr.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/config_multi_gpr.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-Priority
-0	1	+1	# priority      
-0	1	+1	# load_balancing
-4	4	+1	# nb_grp                 
-4	4	*4	# nb_elt         [0] [nb_grp]
-1	1	*4	# nb_elt         [1] [nb_grp]
-16	16	*4	# nb_elt         [2] [nb_grp]
-2	2	*4	# nb_elt         [3] [nb_grp]
-1	4	+1	# nb_grp_select          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/configuration/config_mono_gpr.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/configuration/config_mono_gpr.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/configuration/config_mono_gpr.gen	(revision 145)
@@ -0,0 +1,6 @@
+Priority
+0	1	+1	# priority      
+0	1	+1	# load_balancing
+1	1	+1	# nb_grp                 
+1	16	*4	# nb_elt         [0] [nb_grp]
+1	1	+1	# nb_grp_select          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/configuration/config_multi_gpr.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/configuration/config_multi_gpr.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/configuration/config_multi_gpr.gen	(revision 145)
@@ -0,0 +1,9 @@
+Priority
+0	1	+1	# priority      
+0	1	+1	# load_balancing
+4	4	+1	# nb_grp                 
+4	4	*4	# nb_elt         [0] [nb_grp]
+1	1	*4	# nb_elt         [1] [nb_grp]
+16	16	*4	# nb_elt         [2] [nb_grp]
+2	2	*4	# nb_elt         [3] [nb_grp]
+1	4	+1	# nb_grp_select          
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/Makefile.mkf
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/Makefile.mkf	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/Makefile.mkf	(revision 145)
@@ -0,0 +1,68 @@
+#
+# Makefile generated by MKF configure script
+#
+
+all: Queue_0.ngc Queue_1.ngc Queue_2.ngc Queue_3.ngc
+
+Queue_0.ngc: Queue_0.prj
+	echo run -keep_hierarchy yes -iobuf no -top Queue_0 -ifn Queue_0.prj -ofn Queue_0.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+Queue_0.prj: Queue_0_Pack.vhdl Queue_0.vhdl
+	for i in Queue_0_Pack.vhdl Queue_0.vhdl ; do echo "vhdl work $$i" ; done > Queue_0.prj
+
+Queue_0_Pack.vhdl:
+
+Queue_0.vhdl:
+
+Queue_1.ngc: Queue_1.prj
+	echo run -keep_hierarchy yes -iobuf no -top Queue_1 -ifn Queue_1.prj -ofn Queue_1.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+Queue_1.prj: Queue_1_Pack.vhdl Queue_1.vhdl
+	for i in Queue_1_Pack.vhdl Queue_1.vhdl ; do echo "vhdl work $$i" ; done > Queue_1.prj
+
+Queue_1_Pack.vhdl:
+
+Queue_1.vhdl:
+
+Queue_2.ngc: Queue_2.prj
+	echo run -keep_hierarchy yes -iobuf no -top Queue_2 -ifn Queue_2.prj -ofn Queue_2.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+Queue_2.prj: Queue_2_Pack.vhdl Queue_2.vhdl
+	for i in Queue_2_Pack.vhdl Queue_2.vhdl ; do echo "vhdl work $$i" ; done > Queue_2.prj
+
+Queue_2_Pack.vhdl:
+
+Queue_2.vhdl:
+
+Queue_3.ngc: Queue_3.prj
+	echo run -keep_hierarchy yes -iobuf no -top Queue_3 -ifn Queue_3.prj -ofn Queue_3.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+Queue_3.prj: Queue_3_Pack.vhdl Queue_3.vhdl
+	for i in Queue_3_Pack.vhdl Queue_3.vhdl ; do echo "vhdl work $$i" ; done > Queue_3.prj
+
+Queue_3_Pack.vhdl:
+
+Queue_3.vhdl:
+
+clean:
+	rm -f Queue_0.ngc
+	rm -f Queue_0.lso
+	rm -f -r xst
+	rm -f Queue_0.prj
+	rm -f Queue_1.ngc
+	rm -f Queue_1.lso
+	rm -f -r xst
+	rm -f Queue_1.prj
+	rm -f Queue_2.ngc
+	rm -f Queue_2.lso
+	rm -f -r xst
+	rm -f Queue_2.prj
+	rm -f Queue_3.ngc
+	rm -f Queue_3.lso
+	rm -f -r xst
+	rm -f Queue_3.prj
+
+re: clean all
+
+install:
+
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_min.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-Queue
-1	1 	*2	#_size_queue	
-1	1	*2	#_size_data 
-0  	1  	+1	#_nb_port_slot
-0       0       +1      #_have_port_write
-0       0       +1      #_have_port_read
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_size_queue_log2.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_size_queue_log2.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-Queue
-1	32 	*2	#_size_queue	
-32	32	*2	#_size_data 
-0  	0  	*2	#_nb_port_slot
-1       1       +1      #_have_port_write
-1       1       +1      #_have_port_read
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_size_queue_no_log2.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_size_queue_no_log2.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-Queue
-3	256	*4	#_size_queue	
-32	32	*2	#_size_data 
-0  	0  	*2	#_nb_port_slot
-1       1       +1      #_have_port_write
-1       1       +1      #_have_port_read
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_slot_out_size_queue_log2.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_slot_out_size_queue_log2.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-Queue
-8	8 	*2	#_size_queue	
-32	32	*2	#_size_data 
-1  	8  	*2	#_nb_port_slot
-1       1       +1      #_have_port_write
-1       1       +1      #_have_port_read
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_slot_out_size_queue_no_log2.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_slot_out_size_queue_no_log2.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-Queue
-11	11	*4	#_size_queue	
-32	32	*2	#_size_data 
-1  	8  	*2	#_nb_port_slot
-1       1       +1      #_have_port_write
-1       1       +1      #_have_port_read
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_min.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_min.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_min.gen	(revision 145)
@@ -0,0 +1,6 @@
+Queue
+1	1 	*2	#_size_queue	
+1	1	*2	#_size_data 
+0  	1  	+1	#_nb_port_slot
+0       0       +1      #_have_port_write
+0       0       +1      #_have_port_read
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_size_queue_log2.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_size_queue_log2.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_size_queue_log2.gen	(revision 145)
@@ -0,0 +1,6 @@
+Queue
+1	32 	*2	#_size_queue	
+32	32	*2	#_size_data 
+0  	0  	*2	#_nb_port_slot
+1       1       +1      #_have_port_write
+1       1       +1      #_have_port_read
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_size_queue_no_log2.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_size_queue_no_log2.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_size_queue_no_log2.gen	(revision 145)
@@ -0,0 +1,6 @@
+Queue
+3	256	*4	#_size_queue	
+32	32	*2	#_size_data 
+0  	0  	*2	#_nb_port_slot
+1       1       +1      #_have_port_write
+1       1       +1      #_have_port_read
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_slot_out_size_queue_log2.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_slot_out_size_queue_log2.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_slot_out_size_queue_log2.gen	(revision 145)
@@ -0,0 +1,6 @@
+Queue
+8	8 	*2	#_size_queue	
+32	32	*2	#_size_data 
+1  	8  	*2	#_nb_port_slot
+1       1       +1      #_have_port_write
+1       1       +1      #_have_port_read
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_slot_out_size_queue_no_log2.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_slot_out_size_queue_no_log2.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/configuration/config_slot_out_size_queue_no_log2.gen	(revision 145)
@@ -0,0 +1,6 @@
+Queue
+11	11	*4	#_size_queue	
+32	32	*2	#_size_data 
+1  	8  	*2	#_nb_port_slot
+1       1       +1      #_have_port_write
+1       1       +1      #_have_port_read
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/Makefile	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/Makefile	(revision 145)
@@ -0,0 +1,24 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_COMPONENT			= .
+include				$(DIR_COMPONENT)/Makefile.defs
+
+#-----[ Library ]------------------------------------------
+LIBRARY				= $(DIR_LIB)/libRegisterFile_Internal_Banked.a
+
+
+#-----[ include ]------------------------------------------
+
+all				: $(LIBRARY_NEED)
+				@$(MAKE) all_component
+
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Component
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/Makefile.defs
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/Makefile.defs	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/Makefile.defs	(revision 145)
@@ -0,0 +1,13 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+ENTITY                          = RegisterFile_Internal_Banked
+
+#-----[ Directory ]----------------------------------------
+DIR_COMPONENT_MORPHEO		= ../../../..
+DIR_MORPHEO			= $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/Makefile.deps
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/Makefile.deps	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/Makefile.deps	(revision 145)
@@ -0,0 +1,37 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+# DIR_MORPHEO must be defined
+
+RegisterFile_Internal_Banked			= yes
+
+ifndef Behavioural
+include 					$(DIR_MORPHEO)/Behavioural/Makefile.deps
+endif
+
+#-----[ Library ]------------------------------------------
+
+RegisterFile_Internal_Banked_LIBRARY		= 	-lRegisterFile_Internal_Banked		\
+							$(Behavioural_LIBRARY)	
+
+#-----[ Rules ]--------------------------------------------
+
+RegisterFile_Internal_Banked_library_only	:
+						@\
+						$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked --makefile=Makefile;
+	
+RegisterFile_Internal_Banked_library_clean_only	:
+						@\
+						$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked --makefile=Makefile clean;
+
+RegisterFile_Internal_Banked_library			: RegisterFile_Internal_Banked_library_only
+						@\
+						$(MAKE)  Behavioural_library;
+	
+RegisterFile_Internal_Banked_library_clean	: RegisterFile_Internal_Banked_library_clean_only
+						@\
+						$(MAKE)  Behavioural_library_clean;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/Makefile	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/Makefile	(revision 145)
@@ -0,0 +1,32 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_COMPONENT                   = ../
+include                         $(DIR_COMPONENT)/Makefile.defs
+
+LIBRARY				= $(RegisterFile_Internal_Banked_LIBRARY)
+
+DIR_LIBRARY			= $(RegisterFile_Internal_Banked_DIR_LIBRARY)
+
+#-----[ include ]------------------------------------------
+
+all				:
+				@$(MAKE) all_selftest
+
+library				: RegisterFile_Internal_Banked_library
+
+library_clean			: RegisterFile_Internal_Banked_library_clean
+
+local_clean			:
+
+include                         ../Makefile.deps
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Selftest
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Synthesis
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/configuration/config_read.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/configuration/config_read.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/configuration/config_read.gen	(revision 145)
@@ -0,0 +1,5 @@
+RegisterFile_Internal_Banked
+1	8 	*2	# nb_port_read
+1	1	*2	# nb_port_write
+512 	512	*2	# nb_word
+32	32	*2	# size_word
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/configuration/config_size.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/configuration/config_size.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/configuration/config_size.gen	(revision 145)
@@ -0,0 +1,5 @@
+RegisterFile_Internal_Banked
+4	4 	*2	# nb_port_read
+2	2	*2	# nb_port_write
+1   	128	*2	# nb_word
+32	32	*2	# size_word
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/configuration/config_write.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/configuration/config_write.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/configuration/config_write.gen	(revision 145)
@@ -0,0 +1,5 @@
+RegisterFile_Internal_Banked
+1	1 	*2	# nb_port_read
+2	8	*2	# nb_port_write
+512	512	*2	# nb_word
+32	32	*2	# size_word
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/include/test.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/include/test.h	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/include/test.h	(revision 145)
@@ -0,0 +1,27 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <string>
+#include <iostream>
+#include <sys/time.h>
+#include "Common/include/Time.h"
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h"
+
+using namespace std;
+using namespace morpheo;
+using namespace morpheo::behavioural;
+using namespace morpheo::behavioural::generic;
+using namespace morpheo::behavioural::generic::registerfile;
+using namespace morpheo::behavioural::generic::registerfile::registerfile_internal_banked;
+
+void test   (string name,
+	     morpheo::behavioural::generic::registerfile::registerfile_internal_banked::Parameters * param);
+
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/mkf.info
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/mkf.info	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/mkf.info	(revision 145)
@@ -0,0 +1,21 @@
+
+# state_0
+target_dep	all	state_0.ngc
+target_dep	state_0.ngc	state_0.prj
+target_dep	state_0.prj	state_0_Pack.vhdl state_0.vhdl
+
+# state_1
+target_dep	all	state_1.ngc
+target_dep	state_1.ngc	state_1.prj
+target_dep	state_1.prj	state_1_Pack.vhdl state_1.vhdl
+
+# state_2
+target_dep	all	state_2.ngc
+target_dep	state_2.ngc	state_2.prj
+target_dep	state_2.prj	state_2_Pack.vhdl state_2.vhdl
+
+# state_3
+target_dep	all	state_3.ngc
+target_dep	state_3.ngc	state_3.prj
+target_dep	state_3.prj	state_3_Pack.vhdl state_3.vhdl
+
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/src/main.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/src/main.cpp	(revision 145)
@@ -0,0 +1,47 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/include/test.h"
+
+#define NB_PARAMS 4
+
+void usage (string exec)
+{
+  cerr << "<Usage> " << exec << " name_instance list_params" << endl
+       << "list_params is :" << endl
+       << " - nb_port_read       (unsigned int)" << endl
+       << " - nb_port_write      (unsigned int)" << endl
+       << " - nb_word            (unsigned int)" << endl
+       << " - size_word          (unsigned int)" << endl;
+  exit (1);
+}
+
+#ifndef SYSTEMC
+int main    (int argc, char * argv[])
+#else
+int sc_main (int argc, char * argv[])
+#endif
+{
+  if (argc <  2+NB_PARAMS)
+    usage (argv[0]);
+
+  const string   name               = argv[1];
+  const uint32_t nb_port_read       = atoi(argv[2]);
+  const uint32_t nb_port_write      = atoi(argv[3]);
+  const uint32_t nb_word            = atoi(argv[4]);
+  const uint32_t size_word          = atoi(argv[5]);
+  
+  morpheo::behavioural::generic::registerfile::registerfile_internal_banked::Parameters * param = new morpheo::behavioural::generic::registerfile::registerfile_internal_banked::Parameters
+    (nb_port_read ,
+     nb_port_write,
+     nb_word      ,
+     size_word    );
+  
+  test (name,param);
+
+  return (EXIT_SUCCESS);
+}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/src/test.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/src/test.cpp	(revision 145)
@@ -0,0 +1,244 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test
+ */
+
+#define NB_ITERATION 1
+#define CYCLE_MAX    100000*NB_ITERATION
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest/include/test.h"
+#include "Common/include/Test.h"
+
+void test (string name,
+	   morpheo::behavioural::generic::registerfile::registerfile_internal_banked::Parameters * _param)
+{
+  cout << "<" << name << "> : Simulation SystemC" << endl;
+
+  try 
+    {
+      cout << _param->print(1);
+      _param->test();
+    }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      cout << "<" << name << "> : " <<  error.what ();
+      return;
+    }
+  catch (...)
+    {
+      cerr << "<" << name << "> : This test must generate a error" << endl;
+      exit (EXIT_FAILURE);
+    }
+
+  _model.set_model(MODEL_SYSTEMC,true);
+
+  Tusage_t _usage = USE_ALL;
+
+//   _usage = usage_unset(_usage,USE_SYSTEMC              );
+//   _usage = usage_unset(_usage,USE_VHDL                 );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
+//   _usage = usage_unset(_usage,USE_POSITION             );
+//   _usage = usage_unset(_usage,USE_STATISTICS           );
+//   _usage = usage_unset(_usage,USE_INFORMATION          );
+
+#ifdef STATISTICS
+  morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,100);
+#endif
+  RegisterFile_Internal_Banked * registerfile = new RegisterFile_Internal_Banked 
+    (name.c_str()
+#ifdef STATISTICS
+     ,_param_stat
+#endif
+     ,_param
+     ,_usage);
+  
+#ifdef SYSTEMC
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  sc_clock                                 CLOCK ("clock", 1.0, 0.5);
+  sc_signal<Tcontrol_t>                    NRESET;
+  
+  sc_signal<Tcontrol_t>                    READ_VAL      [_param->_nb_port_read];
+  sc_signal<Tcontrol_t>                    READ_ACK      [_param->_nb_port_read];
+  sc_signal<Taddress_t>                    READ_ADDRESS  [_param->_nb_port_read];
+  sc_signal<Tdata_t>                       READ_DATA     [_param->_nb_port_read];
+
+  sc_signal<Tcontrol_t>                    WRITE_VAL     [_param->_nb_port_write];
+  sc_signal<Tcontrol_t>                    WRITE_ACK     [_param->_nb_port_write];
+  sc_signal<Taddress_t>                    WRITE_ADDRESS [_param->_nb_port_write];
+  sc_signal<Tdata_t>                       WRITE_DATA    [_param->_nb_port_write];
+
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+  
+  cout << "<" << name << "> Instanciation of registerfile" << endl;
+  
+  (*(registerfile->in_CLOCK))        (CLOCK);
+  (*(registerfile->in_NRESET))       (NRESET);
+
+  for (uint32_t i=0; i<_param->_nb_port_read; i++)
+    {
+      (*(registerfile-> in_READ_VAL      [i]))        (READ_VAL      [i]);
+      (*(registerfile->out_READ_ACK      [i]))        (READ_ACK      [i]);
+      if (_param->_have_port_address)
+      (*(registerfile-> in_READ_ADDRESS  [i]))        (READ_ADDRESS  [i]);
+      (*(registerfile->out_READ_DATA     [i]))        (READ_DATA     [i]);
+    }
+  for (uint32_t i=0; i<_param->_nb_port_write; i++)
+    {
+      (*(registerfile-> in_WRITE_VAL     [i]))        (WRITE_VAL     [i]);
+      (*(registerfile->out_WRITE_ACK     [i]))        (WRITE_ACK     [i]);
+      if (_param->_have_port_address)
+      (*(registerfile-> in_WRITE_ADDRESS [i]))        (WRITE_ADDRESS [i]);
+      (*(registerfile-> in_WRITE_DATA    [i]))        (WRITE_DATA    [i]);
+    }
+  
+  cout << "<" << name << "> Start Simulation ............" << endl;
+  Time * _time = new Time();
+
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  // Initialisation
+
+  SC_START(0);
+  
+  for (uint32_t i=0; i<_param->_nb_port_write; i++)
+    WRITE_VAL [i] .write (0);
+  for (uint32_t i=0; i<_param->_nb_port_read; i++)
+    READ_VAL  [i] .write (0);
+
+  NRESET.write(0);
+
+  SC_START(5);
+
+  NRESET.write(1);
+
+  for (uint32_t i=0; i<_param->_nb_port_write; i++)
+    TEST(Tcontrol_t,WRITE_ACK [i],1);
+  for (uint32_t i=0; i<_param->_nb_port_read; i++)
+    TEST(Tcontrol_t,READ_ACK  [i],1);
+
+  for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++)
+    {
+      cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl;
+
+      // random init
+      uint32_t grain = 0;
+      //uint32_t grain = static_cast<uint32_t>(time(NULL));
+      
+      srand(grain);
+
+      Tdata_t tab [_param->_nb_word];
+      
+      for (uint32_t i=0; i<_param->_nb_word; i++)
+	tab[i]= rand()%(1<<(_param->_size_word-1));
+      
+      Taddress_t address_next = 0;
+      Taddress_t nb_ack = 0;
+      
+      while (nb_ack < _param->_nb_word)
+	{
+          
+	  cout << "cycle : " << static_cast<uint32_t> (simulation_cycle()) << endl;
+
+	  for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
+	    {
+	      if ((address_next < _param->_nb_word) and
+		  (WRITE_VAL [num_port].read() == 0))
+		{
+		  cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl;
+		  
+		  WRITE_VAL     [num_port] .write(1);
+		  WRITE_DATA    [num_port] .write(tab[address_next]);
+		  WRITE_ADDRESS [num_port] .write(address_next++);
+		  
+		  // Address can be not a multiple of nb_port_write
+		  if (address_next >= _param->_nb_word)
+		    break;
+		}
+	    }
+
+  
+	  SC_START(1);
+
+	  // reset write_val port
+	  for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
+	    {
+	      if ((WRITE_ACK [num_port].read() == 1) and
+		  (WRITE_VAL [num_port].read() == 1))
+		{
+		  WRITE_VAL  [num_port] .write(0);
+		  nb_ack ++;
+		}
+	    }
+
+// 	  SC_START(0);
+	}
+      
+      address_next = 0;
+      nb_ack       = 0;
+
+      cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl;
+      
+      Tdata_t read_address       [_param->_nb_port_read];
+
+      while (nb_ack < _param->_nb_word)
+	{
+	  cout << "cycle : " << static_cast<uint32_t> (simulation_cycle()) << endl;
+	  
+	  for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
+	    {
+	      if ((address_next < _param->_nb_word) and
+		  (READ_VAL [num_port].read() == 0))
+		{
+		  read_address [num_port] = address_next++;
+
+		  READ_VAL     [num_port].write(1);
+		  READ_ADDRESS [num_port].write(read_address [num_port]);
+
+		  if (address_next >= _param->_nb_word)
+		    break;
+		}
+	    }
+
+
+	  SC_START(1);
+
+	  // reset write_val port
+	  for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
+	    {
+	      if ((READ_ACK [num_port].read() == 1) and
+		  (READ_VAL [num_port].read() == 1))
+		{
+		  READ_VAL  [num_port] .write(0);
+
+		  cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl;
+
+		  TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]);
+		  nb_ack ++;
+		}
+	    }
+
+// 	  SC_START(0);
+	}
+    }
+
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+
+  TEST_STR(bool,true,true, "End of Simulation");
+  delete _time;
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
+
+#endif
+
+  delete registerfile;
+}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/Makefile	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/Makefile	(revision 145)
@@ -0,0 +1,19 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_COMPONENT			= ../
+include				$(DIR_COMPONENT)/Makefile.defs
+
+#-----[ include ]------------------------------------------
+
+all				:
+				$(MAKE) all_documentation
+
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Documentation
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/RegisterFile_Monolithic.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/RegisterFile_Monolithic.tex	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/RegisterFile_Monolithic.tex	(revision 145)
@@ -0,0 +1,38 @@
+\documentclass[10pt,a4paper,twocolumn]{article}
+
+\def\dirdoc{tex}
+\def\dirschema{eps}
+
+% Package de variables d'environnement : Titre, command etc ...
+\usepackage{../../../../../Behavioural/doc/sty/doc-style}
+\usepackage{sty/header}
+
+
+%------------------------------------------------------------------------------
+% Début document
+%------------------------------------------------------------------------------
+
+\pagestyle{empty}
+
+\begin{document}
+
+% Créez une page de titre
+\maketitle
+\thispagestyle{empty}
+
+%Table des matières et des figures
+%\tableofcontents
+%\newpage
+%\listoffigures
+
+%------------------------------------------------------------------------------
+% Ajout du corps du documents
+%------------------------------------------------------------------------------
+
+\input{tex/root}
+
+%------------------------------------------------------------------------------
+% Fin d'ajout du corps du document
+%------------------------------------------------------------------------------
+
+\end{document}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/sty/header.sty
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/sty/header.sty	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/sty/header.sty	(revision 145)
@@ -0,0 +1,12 @@
+\def\review{YYYY/MM/DD}
+%\def\review{\number\day/\number\month/\number\year\xspace}
+
+\title{RegisterFile\_Internal\_Banked}
+ 
+\author{}
+
+\affiliation{}
+
+\email{}
+
+\date{\review}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/01_introduction.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/01_introduction.tex	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/01_introduction.tex	(revision 145)
@@ -0,0 +1,1 @@
+\Section{Introduction}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/02_features.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/02_features.tex	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/02_features.tex	(revision 145)
@@ -0,0 +1,1 @@
+\Section{Features}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/03_description.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/03_description.tex	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/03_description.tex	(revision 145)
@@ -0,0 +1,1 @@
+\Section{Functional Description}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/04_pinout.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/04_pinout.tex	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/04_pinout.tex	(revision 145)
@@ -0,0 +1,1 @@
+\Section{Pin out}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/05_parameters.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/05_parameters.tex	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/05_parameters.tex	(revision 145)
@@ -0,0 +1,1 @@
+\Section{Parameters}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/06_performance.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/06_performance.tex	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/06_performance.tex	(revision 145)
@@ -0,0 +1,1 @@
+\Section{Performance}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/07_details.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/07_details.tex	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/07_details.tex	(revision 145)
@@ -0,0 +1,1 @@
+\Section{Details}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/08_history.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/08_history.tex	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/08_history.tex	(revision 145)
@@ -0,0 +1,10 @@
+\Section{Revision History}
+
+\begin{tabular}{|c|c|c|}
+\hline
+Revision Date & By  & Modifications\\
+\hline
+\hline
+yyyy/mm/dd    & xxx & Initial document \\
+\hline
+\end{tabular}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/root.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/root.tex	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/doc/tex/root.tex	(revision 145)
@@ -0,0 +1,8 @@
+\input{\dirdoc/01_introduction}
+\input{\dirdoc/02_features}
+\input{\dirdoc/03_description}
+\input{\dirdoc/04_pinout}
+\input{\dirdoc/05_parameters}
+\input{\dirdoc/06_performance}
+\input{\dirdoc/07_details}
+\input{\dirdoc/08_history}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/Parameters.h	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/Parameters.h	(revision 145)
@@ -0,0 +1,62 @@
+#ifndef morpheo_behavioural_generic_registerfile_registerfile_internal_banked_Parameters_h
+#define morpheo_behavioural_generic_registerfile_registerfile_internal_banked_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Common/include/Debug.h"
+#include "Behavioural/include/Parameters.h"
+#include <math.h>
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+#define PTR_IS_REGFILE
+
+  class Parameters : public morpheo::behavioural::Parameters
+  {
+  public :       uint32_t    _nb_port_read ;
+  public :       uint32_t    _nb_port_write;
+  public :       uint32_t    _nb_word      ;
+  public :       uint32_t    _size_word    ;
+  public :       std::string _init_value   ;
+
+  public : const uint32_t    _nb_internal_port_read ;
+  public : const uint32_t    _nb_internal_port_write;
+
+  public :       uint32_t    _size_address;
+  public :       uint32_t    _size_ptr_write;
+  public :       bool        _have_port_address;
+  public :       bool        _have_init_value;
+
+  public : Parameters (uint32_t    nb_port_read ,
+		       uint32_t    nb_port_write,
+		       uint32_t    nb_word      ,
+		       uint32_t    size_word    ,
+                       std::string init_value="");
+//   public : Parameters (Parameters & param) ;
+  public : ~Parameters () ;
+
+  public :        void            copy       (void);
+
+  public :        Parameters_test msg_error  (void);
+
+  public :        std::string   print      (uint32_t depth);
+  public : friend std::ostream& operator<< (std::ostream& output_stream,
+					    morpheo::behavioural::generic::registerfile::registerfile_internal_banked::Parameters & x);
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h	(revision 145)
@@ -0,0 +1,137 @@
+#ifndef morpheo_behavioural_generic_registerfile_registerfile_internal_banked_RegisterFile_Internal_Banked
+#define morpheo_behavioural_generic_registerfile_registerfile_internal_banked_RegisterFile_Internal_Banked
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include "Common/include/Debug.h"
+#include "Common/include/ToString.h"
+#include <iostream>
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/Parameters.h"
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/Types.h"
+#ifdef STATISTICS
+#include "Behavioural/include/Stat.h"
+#endif
+#include "Behavioural/include/Component.h"
+#ifdef VHDL
+#include "Behavioural/include/Vhdl.h"
+#endif
+#include "Behavioural/include/Usage.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+  typedef enum {RW_READ, RW_WRITE} rw_t;
+
+  class RegisterFile_Internal_Banked 
+#if SYSTEMC
+    : public sc_module
+#endif
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Parameters
+  protected : const std::string       _name;
+  protected : const Parameters * _param;
+  private   : const Tusage_t     _usage;
+
+#ifdef STATISTICS
+  public    : Stat                           * _stat;
+    
+  // private   : counter_t                      * _stat_nb_read;
+  // private   : counter_t                      * _stat_nb_write;
+  private   : counters_t                     * _stat_port_read;
+  private   : counters_t                     * _stat_port_write;
+#endif
+
+  public    : Component                      * _component;
+  private   : Interfaces                     * _interfaces;
+
+#ifdef SYSTEMC
+    // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // Interface
+  public    : SC_CLOCK                      *  in_CLOCK        ;
+  public    : SC_IN       (Tcontrol_t)      *  in_NRESET       ;
+
+    // ----- Interface Read
+  public    : SC_IN       (Tcontrol_t)     **  in_READ_VAL     ;
+  public    : SC_OUT      (Tcontrol_t)     ** out_READ_ACK     ;
+  public    : SC_IN       (Taddress_t)     **  in_READ_ADDRESS ;
+  public    : SC_OUT      (Tdata_t)        ** out_READ_DATA    ;
+
+    // ----- Interface Write
+  public    : SC_IN       (Tcontrol_t)     **  in_WRITE_VAL    ;
+  public    : SC_OUT      (Tcontrol_t)     ** out_WRITE_ACK    ;
+  public    : SC_IN       (Taddress_t)     **  in_WRITE_ADDRESS;
+  public    : SC_IN       (Tdata_t)        **  in_WRITE_DATA   ;
+
+    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+  private   : Tdata_t * reg_DATA;
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#endif
+
+    // -----[ methods ]---------------------------------------------------
+
+#ifdef SYSTEMC
+    SC_HAS_PROCESS (RegisterFile_Internal_Banked);
+#endif					       
+  public  : RegisterFile_Internal_Banked
+  (
+#ifdef SYSTEMC
+   sc_module_name                              name
+#else					       
+   std::string                                      name
+#endif					       
+#ifdef STATISTICS
+   ,morpheo::behavioural::Parameters_Statistics * param_statistics
+#endif
+   ,Parameters                                  * param
+   ,morpheo::behavioural::Tusage_t                usage
+   );
+
+  public  :          ~RegisterFile_Internal_Banked  (void);
+					       
+  private : void     allocation                (void);
+  private : void     deallocation              (void);
+					       
+#ifdef SYSTEMC				       
+  public  : void     constant                  (void);
+  public  : void     transition                (void);
+//public  : void     genMoore                  (void) {/* empty */};
+  public  : void     genMealy_read             (void);
+#endif					       
+
+#ifdef STATISTICS
+  public  : void     statistics_declaration    (morpheo::behavioural::Parameters_Statistics * param_statistics);
+#endif					       
+
+#if VHDL				       
+  private : void     vhdl                      (void);
+  private : void     vhdl_declaration          (Vhdl * & vhdl);
+  private : void     vhdl_body                 (Vhdl * & vhdl);
+#endif					       
+					       
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+  private : void     end_cycle                 (void);
+#endif
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/Types.h	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/Types.h	(revision 145)
@@ -0,0 +1,29 @@
+#ifndef morpheo_behavioural_generic_registerfile_registerfile_internal_banked_Type_h
+#define morpheo_behavioural_generic_registerfile_registerfile_internal_banked_Type_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Types.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+//typedef uint32_t Taddress_t;
+typedef uint64_t Tdata_t;
+  // typedef Tgeneral_data_t Tdata_t;
+ 
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/Parameters.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/Parameters.cpp	(revision 145)
@@ -0,0 +1,63 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/Parameters.h"
+#include "Common/include/Log2.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+  Parameters::Parameters (uint32_t    nb_port_read ,
+			  uint32_t    nb_port_write,
+			  uint32_t    nb_word      ,
+			  uint32_t    size_word    ,
+                          std::string init_value
+			  ):
+    _nb_internal_port_read  (1),
+    _nb_internal_port_write (1)
+  { 
+    _nb_port_read       = nb_port_read ;
+    _nb_port_write      = nb_port_write;
+    _nb_word            = nb_word      ;
+    _size_word          = size_word    ;
+    _init_value         = init_value   ;
+
+    _size_address       = log2(_nb_word);
+    _size_ptr_write     = log2(_nb_port_write);
+    _have_port_address  = _size_address != 0;
+    _have_init_value    = init_value != "";
+
+    test();
+  };
+  
+//   Parameters::Parameters (Parameters & param) :
+//     _nb_port_read      (param._nb_port_read ),
+//     _nb_port_write     (param._nb_port_write),
+//     _nb_word           (param._nb_word      ),
+//     _size_word         (param._size_word    ),
+//     _size_address      (param._size_address ),
+//     _have_port_address (param._have_port_address)
+//   {
+//     test();
+//   };
+
+  Parameters::~Parameters () 
+  {
+  };
+
+  void Parameters::copy (void) 
+  { 
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/Parameters_msg_error.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/Parameters_msg_error.cpp	(revision 145)
@@ -0,0 +1,44 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <stdint.h>
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/Parameters.h"
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/Types.h"
+#include <sstream>
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+  Parameters_test Parameters::msg_error(void)
+  {
+    Parameters_test test("RegisterFile_Internal_Banked");
+
+    if ((8*sizeof(Tdata_t)) < _size_word)
+      test.error("Type \"Tdata_t\" is too little to the size defined by size_word");
+
+    if ((8*sizeof(Taddress_t)) < log2(_nb_word))
+      test.error("type \"Taddress_t\" is too little to the size defined by nb_word");
+
+    if (_nb_port_read < 1)
+      test.error("you need a read port");
+
+    if (_nb_port_write < 1)
+      test.error("you need a write port");
+
+    // Need test init_value
+
+    return test;
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/Parameters_print.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/Parameters_print.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/Parameters_print.cpp	(revision 145)
@@ -0,0 +1,44 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <stdint.h>
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/Parameters.h"
+#include "Behavioural/include/XML.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+  std::string Parameters::print (uint32_t depth)
+  {
+    XML xml ("registerfile_internal_banked");
+
+    xml.balise_open("registerfile_internal_banked");
+    xml.singleton_begin("nb_port_read      "); xml.attribut("value",toString(_nb_port_read      )); xml.singleton_end();
+    xml.singleton_begin("nb_port_write     "); xml.attribut("value",toString(_nb_port_write     )); xml.singleton_end();
+    xml.singleton_begin("nb_word           "); xml.attribut("value",toString(_nb_word           )); xml.singleton_end();
+    xml.singleton_begin("size_word         "); xml.attribut("value",toString(_size_word         )); xml.singleton_end();
+    xml.balise_close();
+
+    return xml.get_body(depth);
+  };
+
+  std::ostream& operator<< (std::ostream& output_stream ,
+			    morpheo::behavioural::generic::registerfile::registerfile_internal_banked::Parameters & x)
+  {
+    output_stream << x.print(0);
+    
+    return output_stream;
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked.cpp	(revision 145)
@@ -0,0 +1,111 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+  RegisterFile_Internal_Banked::RegisterFile_Internal_Banked 
+  (
+#ifdef SYSTEMC
+   sc_module_name name,
+#else
+   std::string name        ,
+#endif
+#ifdef STATISTICS
+   morpheo::behavioural::Parameters_Statistics            * param_statistics,
+#endif
+   morpheo::behavioural::generic::registerfile::registerfile_internal_banked::Parameters * param,
+   morpheo::behavioural::Tusage_t usage
+   ):
+    _name  (name),
+    _param (param),
+    _usage (usage)
+  {
+    log_printf(FUNC,RegisterFile_Internal_Banked,"RegisterFile_Internal_Banked","Begin");
+
+// #if DEBUG_RegisterFile_Internal_Banked == true
+//     log_printf(INFO,RegisterFile_Internal_Banked,FUNCTION,_("<%s> Parameters"),_name.c_str());
+
+//     std::cout << *param << std::endl;
+// #endif    
+
+    log_printf(INFO,RegisterFile_Internal_Banked,"RegisterFile_Internal_Banked","Allocation");
+    allocation ();
+
+#ifdef STATISTICS
+    if (usage_is_set(_usage,USE_STATISTICS))
+      statistics_declaration(param_statistics);
+#endif
+
+#ifdef VHDL
+    // generate the vhdl
+    if (usage_is_set(_usage,USE_VHDL))
+      vhdl();
+#endif
+
+#ifdef SYSTEMC
+    if (usage_is_set(_usage,USE_SYSTEMC))
+      {
+
+# ifdef SYSTEMCASS_SPECIFIC
+        constant();
+#else
+	SC_METHOD (constant);
+// 	dont_initialize ();
+#endif
+
+	SC_METHOD (transition);
+	dont_initialize ();
+	sensitive << (*(in_CLOCK)).pos();
+
+	SC_METHOD (genMealy_read);
+	dont_initialize ();
+	sensitive << (*(in_CLOCK)).neg()
+		  << (*(in_NRESET));
+
+	for (uint32_t i=0; i<_param->_nb_port_read; i++)
+	  {
+	    sensitive << *(in_READ_VAL     [i]);
+	    if (_param->_have_port_address)
+	      sensitive << *(in_READ_ADDRESS [i]);
+	  }
+	
+# ifdef SYSTEMCASS_SPECIFIC
+	// List dependency information
+	for (uint32_t i=0; i<_param->_nb_port_read; i++)
+	  {
+	    (*(out_READ_DATA  [i])) (*( in_READ_VAL     [i]));
+	    if (_param->_have_port_address)
+	      (*(out_READ_DATA  [i])) (*( in_READ_ADDRESS [i]));
+	  }
+# endif    
+      }
+#endif
+    
+    log_printf(FUNC,RegisterFile_Internal_Banked,"RegisterFile_Internal_Banked","End");
+  };
+  
+  RegisterFile_Internal_Banked::~RegisterFile_Internal_Banked (void)
+  {
+#ifdef STATISTICS
+    if (usage_is_set(_usage,USE_STATISTICS))
+      delete _stat;
+#endif
+
+    deallocation ();
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_allocation.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_allocation.cpp	(revision 145)
@@ -0,0 +1,81 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h"
+#include "Behavioural/include/Allocation.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+  void RegisterFile_Internal_Banked::allocation (void)
+  {
+    _component   = new Component (_usage);
+
+    Entity * entity = _component->set_entity (_name                   
+					     ,"RegisterFile_Internal_Banked"
+#ifdef POSITION
+					     ,REGISTER                 
+#endif
+					      );
+    
+    _interfaces = entity->set_interfaces();
+
+    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      Interface * interface = _interfaces->set_interface(""
+#ifdef POSITION
+							 , IN
+							 ,SOUTH
+							 ,_("Generalist interface")
+#endif
+							 );
+      
+      in_CLOCK              = interface->set_signal_clk              ("clock" ,1);
+      in_NRESET             = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
+    }
+
+    // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    { 
+      ALLOC1_INTERFACE_BEGIN("read",IN,WEST,_("Interface Read"),_param->_nb_port_read);
+
+      ALLOC1_VALACK_IN ( in_READ_VAL    ,VAL);
+      ALLOC1_VALACK_OUT(out_READ_ACK    ,ACK);
+      ALLOC1_SIGNAL_IN ( in_READ_ADDRESS,"address",Taddress_t,_param->_size_address);
+      ALLOC1_SIGNAL_OUT(out_READ_DATA   ,"data"   ,Tdata_t   ,_param->_size_word);
+
+      ALLOC1_INTERFACE_END(_param->_nb_port_read);
+    }
+
+    // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      ALLOC1_INTERFACE_BEGIN("write",IN,EAST,_("Interface Write"),_param->_nb_port_write);
+
+      ALLOC1_VALACK_IN ( in_WRITE_VAL    ,VAL);
+      ALLOC1_VALACK_OUT(out_WRITE_ACK    ,ACK);
+      ALLOC1_SIGNAL_IN ( in_WRITE_ADDRESS,"address",Taddress_t,_param->_size_address);
+      ALLOC1_SIGNAL_IN ( in_WRITE_DATA   ,"data"   ,Tdata_t   ,_param->_size_word);
+
+      ALLOC1_INTERFACE_END(_param->_nb_port_write);
+    }
+
+    if (usage_is_set(_usage,USE_SYSTEMC))
+      ALLOC1(reg_DATA,Tdata_t,_param->_nb_word);
+    
+#ifdef POSITION
+    if (usage_is_set(_usage,USE_POSITION))
+      _component->generate_file();
+#endif
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_constant.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_constant.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_constant.cpp	(revision 145)
@@ -0,0 +1,37 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+#undef  FUNCTION
+#define FUNCTION "RegisterFile_Internal_Banked::constant"
+  void RegisterFile_Internal_Banked::constant (void)
+  {
+    log_begin(RegisterFile_Internal_Banked,FUNCTION);
+    log_function(RegisterFile_Internal_Banked,FUNCTION,_name.c_str());
+    
+    for (uint32_t i=0; i<_param->_nb_port_read       ; i++)
+      PORT_WRITE(out_READ_ACK        [i], 1);
+    for (uint32_t i=0; i<_param->_nb_port_write      ; i++)
+      PORT_WRITE(out_WRITE_ACK       [i], 1);
+
+    log_end(RegisterFile_Internal_Banked,FUNCTION);
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_deallocation.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_deallocation.cpp	(revision 145)
@@ -0,0 +1,44 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h"
+#include "Behavioural/include/Allocation.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+  void RegisterFile_Internal_Banked::deallocation (void)
+  {
+    delete _component;
+
+    if (usage_is_set(_usage,USE_SYSTEMC))
+      {
+	delete    in_CLOCK;
+	delete    in_NRESET;
+
+        DELETE1_SIGNAL( in_READ_VAL     ,_param->_nb_port_read,1);
+        DELETE1_SIGNAL(out_READ_ACK     ,_param->_nb_port_read,1);
+        DELETE1_SIGNAL( in_READ_ADDRESS ,_param->_nb_port_read,_param->_size_address);
+        DELETE1_SIGNAL(out_READ_DATA    ,_param->_nb_port_read,_param->_size_word);
+        
+        DELETE1_SIGNAL( in_WRITE_VAL    ,_param->_nb_port_write,1);
+        DELETE1_SIGNAL(out_WRITE_ACK    ,_param->_nb_port_write,1);
+        DELETE1_SIGNAL( in_WRITE_ADDRESS,_param->_nb_port_write,_param->_size_address);
+        DELETE1_SIGNAL( in_WRITE_DATA   ,_param->_nb_port_write,_param->_size_word);
+        
+        DELETE1(reg_DATA,_param->_nb_word);
+      }
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_end_cycle.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_end_cycle.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_end_cycle.cpp	(revision 145)
@@ -0,0 +1,42 @@
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+  void RegisterFile_Internal_Banked::end_cycle (void)
+  {
+    log_printf(FUNC,RegisterFile,"end_cycle","Begin");
+
+#ifdef STATISTICS
+    if (usage_is_set(_usage,USE_STATISTICS))
+      _stat->end_cycle();
+#endif    
+
+#ifdef VHDL_TESTBENCH
+    // Evaluation before read the ouput signal
+    
+//  sc_start(0);
+    if (usage_is_set(_usage,USE_VHDL_TESTBENCH))
+      _interfaces->testbench();
+#endif
+
+    log_printf(FUNC,RegisterFile,"end_cycle","End");
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_genMealy_read.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_genMealy_read.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_genMealy_read.cpp	(revision 145)
@@ -0,0 +1,59 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+#undef  FUNCTION
+#define FUNCTION "RegisterFile_Internal_Banked::genMealy_read"
+  void RegisterFile_Internal_Banked::genMealy_read (void)
+  {
+    log_begin(RegisterFile_Internal_Banked,FUNCTION);
+    log_function(RegisterFile_Internal_Banked,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET))
+      {
+    for (uint32_t i=0; i<_param->_nb_port_read; i++)
+      {
+	// Have a write?
+ 	if ( PORT_READ(in_READ_VAL [i]) == 1)
+ 	  {
+	    Taddress_t address;
+	    if (_param->_have_port_address)
+	      address = PORT_READ(in_READ_ADDRESS[i]);
+	    else
+	      address = 0;
+	    Tdata_t    data    = reg_DATA[address];
+
+	    log_printf(TRACE,RegisterFile,FUNCTION,"  * [%d] -> %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));
+
+	    // Write in registerFile
+	    PORT_WRITE(out_READ_DATA[i],data);
+ 	  }
+	else
+	  {
+	    //log_printf(TRACE,RegisterFile,FUNCTION,"Read  [%d] : No   transaction",i);
+	    PORT_WRITE(out_READ_DATA[i],0);
+	  }
+      }
+      }
+
+    log_end(RegisterFile_Internal_Banked,FUNCTION);
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_statistics_declaration.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_statistics_declaration.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_statistics_declaration.cpp	(revision 145)
@@ -0,0 +1,43 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+  void RegisterFile_Internal_Banked::statistics_declaration (morpheo::behavioural::Parameters_Statistics * param_statistics)
+  {
+    _stat = new Stat (static_cast<std::string>(_name),
+		      "RegisterFile_Internal_Banked",
+		      param_statistics);
+
+    if (_param->_nb_port_read>0)
+    _stat_port_read         = _stat->create_counters("port_read",_param->_nb_port_read,"",
+                                                     _("Cycle number cycle with %d read(s)."),
+                                                     _("Percent of cycle number cycle with %d read(s)."),
+                                                     _("Average of read per cycle.")
+                                                     );
+
+    if (_param->_nb_port_write>0)
+    _stat_port_write        = _stat->create_counters("port_write",_param->_nb_port_write,"",
+                                                     _("Cycle number cycle with %d write(s)."),
+                                                     _("Percent of cycle number cycle with %d write(s)."),
+                                                     _("Average of write per cycle.")
+                                                     );
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_transition.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_transition.cpp	(revision 145)
@@ -0,0 +1,134 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+#undef  FUNCTION
+#define FUNCTION "RegisterFile_Internal_Banked::transition"
+  void RegisterFile_Internal_Banked::transition (void)
+  {
+    log_begin(RegisterFile_Internal_Banked,FUNCTION);
+    log_function(RegisterFile_Internal_Banked,FUNCTION,_name.c_str());
+
+    if (PORT_READ(in_NRESET) == 0)
+      {
+        if (_param->_have_init_value)
+          {
+            for (uint32_t i=0; i<_param->_nb_word; ++i)
+              reg_DATA[i] = fromString<Tdata_t>(_param->_init_value);
+          }
+        else
+          {
+            for (uint32_t i=0; i<_param->_nb_word; ++i)
+              reg_DATA[i] = 0;
+          }
+      }
+    else
+      {
+#ifdef STATISTICS
+        uint32_t stat_nb_read      =0;
+        uint32_t stat_nb_write     =0;
+#endif
+        for (uint32_t i=0; i<_param->_nb_port_write; i++)
+          {
+            log_printf(TRACE,RegisterFile,FUNCTION,"  * WRITE [%d] : %d",i,PORT_READ(in_WRITE_VAL[i]));
+
+            // Have a write?
+            if ( PORT_READ(in_WRITE_VAL[i]) == true)
+              {
+#ifdef STATISTICS
+                stat_nb_write++;
+#endif
+
+// #ifdef STATISTICS
+//                 if (usage_is_set(_usage,USE_STATISTICS))
+//                   (*_stat_nb_write) ++;
+// #endif    
+
+                Taddress_t address = (_param->_have_port_address)?PORT_READ(in_WRITE_ADDRESS[i]):0;
+                Tdata_t    data    = PORT_READ(in_WRITE_DATA   [i]);
+
+                log_printf(TRACE,RegisterFile,FUNCTION,"    * address : %d",address);
+                log_printf(TRACE,RegisterFile,FUNCTION,"    * gloup");
+                log_printf(TRACE,RegisterFile,FUNCTION,"    * data    : %d",data);
+                
+                log_printf(TRACE,RegisterFile,FUNCTION,"  * [%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));
+
+#ifdef DEBUG_TEST
+                if (address >= _param->_nb_word)
+                  throw ERRORMORPHEO(FUNCTION,toString(_("Address (%d) is invalid (size : %d).\n"),address,_param->_nb_word));
+#endif
+                
+                // Write in registerFile
+                reg_DATA[address] = data;
+              }
+          }
+
+#ifdef STATISTICS
+        if (usage_is_set(_usage,USE_STATISTICS))
+          {
+            for (uint32_t i=0; i<_param->_nb_port_read; i++)
+              if ( PORT_READ(in_READ_VAL [i]) == 1)
+                {
+                  stat_nb_read ++;
+                  // (*_stat_nb_read) ++;
+                }
+
+            if (_param->_nb_port_read>0)
+            (*_stat_port_read      ) += stat_nb_read;
+            if (_param->_nb_port_write>0)
+            (*_stat_port_write     ) += stat_nb_write;
+          }
+#endif    
+      }
+
+#if defined(DEBUG_RegisterFile_Internal_Banked) and DEBUG_RegisterFile_Internal_Banked and (DEBUG >= DEBUG_TRACE)
+# if 1
+    {
+      log_printf(TRACE,RegisterFile,FUNCTION,"  * Dump RegisterFile");
+
+      uint32_t limit = 4;
+      
+      for (uint32_t i=0; i<_param->_nb_word; i+=limit)
+        {
+          std::string str = "";
+          
+          for (uint32_t j=0; j<limit; j++)
+            {
+              uint32_t index = i+j;
+              if (index >= _param->_nb_word)
+                break;
+              else
+                str+=toString("[%.4d] %.8x ",index,reg_DATA[index]);
+            }
+
+          log_printf(TRACE,RegisterFile,FUNCTION,"  %s",str.c_str());
+        }
+    }
+# endif
+#endif
+
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+    end_cycle();
+#endif
+
+    log_end(RegisterFile_Internal_Banked,FUNCTION);
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_vhdl.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_vhdl.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_vhdl.cpp	(revision 145)
@@ -0,0 +1,38 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h"
+#include "Behavioural/include/Vhdl.h"
+#include "Common/include/ToString.h"
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+  void RegisterFile_Internal_Banked::vhdl (void)
+  {
+    Vhdl * vhdl = new Vhdl (_name);
+
+    _interfaces->set_port     (vhdl);
+    _component ->vhdl_instance(vhdl);
+
+    vhdl_declaration (vhdl);
+    vhdl_body        (vhdl);
+
+    vhdl->generate_file();
+
+    delete vhdl;
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_vhdl_body.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_vhdl_body.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_vhdl_body.cpp	(revision 145)
@@ -0,0 +1,162 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+  void RegisterFile_Internal_Banked::vhdl_body (Vhdl * & vhdl)
+  {
+    vhdl->set_body   (0,"");
+    vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    vhdl->set_comment(0," Ackitement");
+    vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    vhdl->set_body   (0,"");
+
+    for (uint32_t num_read=0; num_read<_param->_nb_port_read; ++num_read)
+      vhdl->set_body   (0,"out_READ_"+toString(num_read)+"_ACK  <= '1';");
+    for (uint32_t num_write=0; num_write<_param->_nb_port_write; ++num_write)
+      vhdl->set_body   (0,"out_WRITE_"+toString(num_write)+"_ACK <= '1';");
+
+    vhdl->set_body   (0,"");
+    vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    vhdl->set_comment(0," Read RegisterFile");
+    vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    vhdl->set_body   (0,"");
+
+    if (_param->_size_ptr_write>0)
+      for (uint32_t num_read=0; num_read<_param->_nb_port_read; ++num_read)
+        {
+#ifdef PTR_IS_REGFILE
+          std::string str_address;
+          if (_param->_have_port_address)
+            str_address = "conv_integer(in_READ_"+toString(num_read)+"_ADDRESS)";
+          else
+            str_address = "0";
+
+          vhdl->set_body   (0,"READ_NUM_BANK_"+toString(num_read)+" <= reg_PTR_WRITE("+str_address+");");
+#else
+
+          vhdl->set_body   (0,"with in_READ_"+toString(num_read)+"_ADDRESS select");
+          vhdl->set_body   (1,"READ_NUM_BANK_"+toString(num_read)+" <=");
+          for (uint32_t num_word=0; num_word<_param->_nb_word-1; ++num_word)
+            vhdl->set_body   (1,"reg_PTR_WRITE_"+toString(num_word)+" when "+std_logic_cst(_param->_size_address,num_word)+",");
+          vhdl->set_body   (1,"reg_PTR_WRITE_"+toString(_param->_nb_word-1)+" when others;");
+#endif
+        }
+    vhdl->set_body   (0,"");
+
+    for (uint32_t num_read=0; num_read<_param->_nb_port_read; ++num_read)
+      {
+	std::string str_address;
+	if (_param->_have_port_address)
+	  str_address = "conv_integer(in_READ_"+toString(num_read)+"_ADDRESS)";
+	else
+	  str_address = "0";
+
+	vhdl->set_body   (0,"out_READ_"+toString(num_read)+"_DATA <=");
+        for (uint32_t num_write=0; num_write<_param->_nb_port_write; ++num_write)
+          {
+            std::string str_ptr_write="";
+            if (_param->_size_ptr_write>0)
+              str_ptr_write = " and READ_NUM_BANK_"+toString(num_read)+" = "+std_logic_cst(_param->_size_ptr_write,num_write);
+
+            vhdl->set_body   (1,"reg_DATA_"+toString(num_write)+"_"+toString(num_read)+"("+str_address+") when in_READ_"+toString(num_read)+"_VAL = '1'"+str_ptr_write+" else");
+          }
+        vhdl->set_body   (1,std_logic_others(_param->_size_word,0)+";");
+      }
+
+    vhdl->set_body   (0,"");
+    vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    vhdl->set_comment(0," Write RegisterFile");
+    vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    vhdl->set_body   (0,"");
+
+    vhdl->set_body   (0,"RegisterFile_write: process (in_CLOCK)");
+    vhdl->set_body   (0,"begin  -- process RegisterFile_write");
+    vhdl->set_body   (1,"if in_CLOCK'event and in_CLOCK = '1' then");
+
+    if (_param->_have_init_value)
+      {
+        vhdl->set_body   (2,"if in_NRESET = '0' then");
+        
+        std::string init_value = ((_param->_size_word>1)?"\"":"'")+_param->_init_value+((_param->_size_word>1)?"\"":"'");
+        
+        for (uint32_t num_word=0; num_word<_param->_nb_word; ++num_word)
+          {
+            for (uint32_t num_read=0; num_read<_param->_nb_port_read; ++num_read)
+              vhdl->set_body   (3,"reg_DATA_0_"+toString(num_read)+"("+toString(num_word)+") <= "+init_value+";");
+
+            if (_param->_size_ptr_write>0)
+              {
+#ifdef PTR_IS_REGFILE
+                vhdl->set_body   (3,"reg_PTR_WRITE("+toString(num_word)+") <= "+std_logic_cst(_param->_size_ptr_write,0)+";");
+#else
+                vhdl->set_body   (3,"reg_PTR_WRITE_"+toString(num_word)+" <= "+std_logic_cst(_param->_size_ptr_write,0)+";");
+#endif
+              }
+          }
+        vhdl->set_body   (2,"else");
+      }
+    // else
+    //   {
+    //     vhdl->set_body   (2,"if in_NRESET = '0' then");
+        
+    //     for (uint32_t num_word=0; num_word<_param->_nb_word; ++num_word)
+    //         if (_param->_size_ptr_write>0)
+    //           vhdl->set_body   (3,"reg_PTR_WRITE("+toString(num_word)+") <= "+std_logic_cst(_param->_size_ptr_write,0)+";");
+    //     vhdl->set_body   (2,"else");
+    //   }
+      
+    
+    for (uint32_t num_write=0; num_write<_param->_nb_port_write; ++num_write)
+      {
+	std::string str_address;
+	if (_param->_have_port_address)
+	  str_address = "conv_integer(in_WRITE_"+toString(num_write)+"_ADDRESS)";
+	else
+	  str_address = "0";
+
+	vhdl->set_body   (2,"if (in_WRITE_"+toString(num_write)+"_VAL = '1') then");
+        for (uint32_t num_read=0; num_read<_param->_nb_port_read; ++num_read)
+          vhdl->set_body   (3,"reg_DATA_"+toString(num_write)+"_"+toString(num_read)+"("+str_address+") <= in_WRITE_"+toString(num_write)+"_DATA;");
+
+        if (_param->_size_ptr_write>0)
+          {
+#ifdef PTR_IS_REGFILE
+          vhdl->set_body   (3,"reg_PTR_WRITE("+str_address+") <= "+std_logic_cst(_param->_size_ptr_write,num_write)+";");
+#else
+          for (uint32_t num_word=0; num_word<_param->_nb_word; ++num_word)
+            {
+              vhdl->set_body   (3,"if (in_WRITE_"+toString(num_write)+"_ADDRESS = "+std_logic_cst(_param->_size_address,num_word)+") then");
+              vhdl->set_body   (4,"reg_PTR_WRITE_"+toString(num_word)+" <= "+std_logic_cst(_param->_size_ptr_write,num_write)+";");
+              vhdl->set_body   (3,"end if;");
+            }
+#endif
+          }
+	vhdl->set_body   (2,"end if;");
+      }
+
+    vhdl->set_body   (1,"end if;");
+
+    if (_param->_have_init_value)
+      vhdl->set_body   (1,"end if;");
+
+    vhdl->set_body   (0,"end process RegisterFile_write;");
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_vhdl_declaration.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_vhdl_declaration.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/src/RegisterFile_Internal_Banked_vhdl_declaration.cpp	(revision 145)
@@ -0,0 +1,49 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Internal_Banked/include/RegisterFile_Internal_Banked.h"
+#include "Behavioural/include/Vhdl.h"
+#include "Common/include/ToString.h"
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+namespace registerfile_internal_banked    {
+
+  void RegisterFile_Internal_Banked::vhdl_declaration (Vhdl * & vhdl)
+  {
+    vhdl->set_type ("Tregfile", "array " + _std_logic_range(_param->_nb_word) + " of " + std_logic(_param->_size_word));
+
+    for (uint32_t num_write=0; num_write<_param->_nb_port_write; ++num_write)
+      for (uint32_t num_read=0; num_read<_param->_nb_port_read; ++num_read)
+        vhdl->set_signal ("reg_DATA_"+toString(num_write)+"_"+toString(num_read), "Tregfile");
+
+    if (_param->_size_ptr_write > 0)
+      {
+        for (uint32_t num_read=0; num_read<_param->_nb_port_read; ++num_read)
+          vhdl->set_signal ("READ_NUM_BANK_"+toString(num_read), _param->_size_ptr_write);
+      }
+#ifdef PTR_IS_REGFILE
+    if (_param->_size_ptr_write > 0)
+      {
+    vhdl->set_type ("Tptr_write", "array " + _std_logic_range(_param->_nb_word) + " of " + std_logic(_param->_size_ptr_write));
+    vhdl->set_signal ("reg_PTR_WRITE", "Tptr_write");
+      }
+#else
+    if (_param->_size_ptr_write > 0)
+      for (uint32_t num_word=0; num_word<_param->_nb_word; ++num_word)
+        vhdl->set_signal ("reg_PTR_WRITE_"+toString(num_word), _param->_size_ptr_write);
+#endif
+  };
+
+}; // end namespace registerfile_internal_banked
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/Makefile	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/Makefile	(revision 145)
@@ -2,11 +2,12 @@
 # $Id$
 # 
-# [ Description ]
+# [ Description ]
 # 
 # Makefile
 # 
 
-#-----[ Directory ]----------------------------------------
-DIR_MORPHEO			= ../../../../..
+#-----[ Directory ]----------------------------------------
+DIR_COMPONENT                   = ../
+include                         $(DIR_COMPONENT)/Makefile.defs
 
 LIBRARY				= $(RegisterFile_Monolithic_LIBRARY)
@@ -14,7 +15,7 @@
 DIR_LIBRARY			= $(RegisterFile_Monolithic_DIR_LIBRARY)
 
-#-----[ include ]------------------------------------------
+#-----[ include ]------------------------------------------
 
-all				: library
+all				:
 				@$(MAKE) all_selftest
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_mixte.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_mixte.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-RegisterFile_Monolithic
-0	0 	*2	# nb_port_read
-0	0	*2	# nb_port_write
-1	8	*2	# nb_port_read_write
-32 	32 	*2	# nb_word
-32	32	*2	# size_word
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_read.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_read.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-RegisterFile_Monolithic
-1	8 	*2	# nb_port_read
-1	1	*2	# nb_port_write
-0	0	*2	# nb_port_read_write
-512 	512	*2	# nb_word
-32	32	*2	# size_word
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_size.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_size.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-RegisterFile_Monolithic
-4	4 	*2	# nb_port_read
-2	2	*2	# nb_port_write
-0	0	*2	# nb_port_read_write
-1   	128	*2	# nb_word
-32	32	*2	# size_word
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_write.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_write.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-RegisterFile_Monolithic
-1	1 	*2	# nb_port_read
-2	8	*2	# nb_port_write
-0	0	*2	# nb_port_read_write
-512	512	*2	# nb_word
-32	32	*2	# size_word
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration/config_mixte.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration/config_mixte.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration/config_mixte.gen	(revision 145)
@@ -0,0 +1,6 @@
+RegisterFile_Monolithic
+0	0 	*2	# nb_port_read
+0	0	*2	# nb_port_write
+1	8	*2	# nb_port_read_write
+32 	32 	*2	# nb_word
+32	32	*2	# size_word
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration/config_read.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration/config_read.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration/config_read.gen	(revision 145)
@@ -0,0 +1,6 @@
+RegisterFile_Monolithic
+1	8 	*2	# nb_port_read
+1	1	*2	# nb_port_write
+0	0	*2	# nb_port_read_write
+512 	512	*2	# nb_word
+32	32	*2	# size_word
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration/config_size.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration/config_size.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration/config_size.gen	(revision 145)
@@ -0,0 +1,6 @@
+RegisterFile_Monolithic
+4	4 	*2	# nb_port_read
+2	2	*2	# nb_port_write
+0	0	*2	# nb_port_read_write
+1   	128	*2	# nb_word
+32	32	*2	# size_word
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration/config_write.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration/config_write.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration/config_write.gen	(revision 145)
@@ -0,0 +1,6 @@
+RegisterFile_Monolithic
+1	1 	*2	# nb_port_read
+2	8	*2	# nb_port_write
+0	0	*2	# nb_port_read_write
+512	512	*2	# nb_word
+32	32	*2	# size_word
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info	(revision 145)
@@ -1,6 +1,6 @@
 
-# RegisterFile_Monolithic_0
-target_dep	all	RegisterFile_Monolithic_0.ngc
-target_dep	RegisterFile_Monolithic_0.ngc	RegisterFile_Monolithic_0.prj
-target_dep	RegisterFile_Monolithic_0.prj	RegisterFile_Monolithic_0_Pack.vhdl RegisterFile_Monolithic_0.vhdl
+# debug_0
+target_dep	all	debug_0.ngc
+target_dep	debug_0.ngc	debug_0.prj
+target_dep	debug_0.prj	debug_0_Pack.vhdl debug_0.vhdl
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h	(revision 145)
@@ -22,5 +22,5 @@
 #include "Behavioural/include/Stat.h"
 #endif
-#include "Behavioural/include/Component.h"
+// #include "Behavioural/include/Component.h"
 #ifdef VHDL
 #include "Behavioural/include/Vhdl.h"
@@ -28,9 +28,17 @@
 #include "Behavioural/include/Usage.h"
 
+
+
 namespace morpheo                    {
 namespace behavioural                {
+
+  class Component;
+  class Interfaces;
+
 namespace generic                    {
 namespace registerfile               {
 namespace registerfile_monolithic    {
+
+// #define VHDL_GAISLER
 
   typedef enum {RW_READ, RW_WRITE} rw_t;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Types.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Types.h	(revision 145)
@@ -17,5 +17,6 @@
 namespace registerfile_monolithic    {
 
-//   typedef uint32_t Taddress_t;
+//typedef uint32_t Taddress_t;
+//typedef uint64_t Tdata_t;
   typedef Tgeneral_data_t Tdata_t;
  
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp	(revision 145)
@@ -8,4 +8,5 @@
 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h"
 #include "Behavioural/include/Allocation.h"
+#include "Behavioural/include/Component.h"
 
 namespace morpheo                    {
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp	(revision 145)
@@ -8,4 +8,5 @@
 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h"
 #include "Behavioural/include/Allocation.h"
+#include "Behavioural/include/Component.h"
 
 namespace morpheo                    {
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl.cpp	(revision 145)
@@ -10,4 +10,6 @@
 #include "Behavioural/include/Vhdl.h"
 #include "Common/include/ToString.h"
+#include "Behavioural/include/Component.h"
+
 namespace morpheo                    {
 namespace behavioural                {
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp	(revision 145)
@@ -17,4 +17,6 @@
   void RegisterFile_Monolithic::vhdl_body (Vhdl * & vhdl)
   {
+#ifndef VHDL_GAISLER
+
     vhdl->set_body   (0,"");
     vhdl->set_comment(0,"---------------------------------------------------------------------------");
@@ -107,6 +109,142 @@
     if (_param->_have_init_value)
       vhdl->set_body   (1,"end if;");
-
     vhdl->set_body   (0,"end process RegisterFile_write;");
+
+#else
+    // vhdl->set_body   (0,"");
+    // vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    // vhdl->set_comment(0," Ackitement");
+    // vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    // vhdl->set_body   (0,"");
+
+    // for (uint32_t i = 0; i < _param->_nb_port_read; i++)
+    //   vhdl->set_body   (0,"out_READ_"+toString(i)+"_ACK  <= '1';");
+    // for (uint32_t i = 0; i < _param->_nb_port_write; i++)
+    //   vhdl->set_body   (0,"out_WRITE_"+toString(i)+"_ACK <= '1';");
+    // for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
+    //   vhdl->set_body   (0,"out_READ_WRITE_"+toString(i)+"_ACK  <= '1';");
+
+    // vhdl->set_body   (0,"");
+    // vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    // vhdl->set_comment(0," Read RegisterFile");
+    // vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    // vhdl->set_body   (0,"");
+
+    // for (uint32_t num_read=0; num_read<_param->_nb_port_read; ++num_read)
+    //   {
+    //     vhdl->set_body   (0,"with in_READ_"+toString(num_read)+"_ADDRESS select");
+    //       vhdl->set_body   (1,"out_READ_"+toString(num_read)+"_DATA <=");
+    //       for (uint32_t num_word=0; num_word<_param->_nb_word-1; ++num_word)
+    //         vhdl->set_body   (1,"reg_DATA_"+toString(num_word)+" when "+std_logic_cst(_param->_size_address,num_word)+",");
+    //       vhdl->set_body   (1,"reg_DATA_"+toString(_param->_nb_word-1)+" when others;");
+    //   }
+
+    // vhdl->set_body   (0,"");
+    // vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    // vhdl->set_comment(0," Write RegisterFile");
+    // vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    // vhdl->set_body   (0,"");
+
+    // vhdl->set_body   (0,"RegisterFile_write: process (in_CLOCK)");
+    // vhdl->set_body   (0,"begin  -- process RegisterFile_write");
+    // vhdl->set_body   (1,"if in_CLOCK'event and in_CLOCK = '1' then");
+
+    // for (uint32_t num_write = 0; num_write < _param->_nb_port_write; num_write++)
+    //   {
+    //     vhdl->set_body   (2,"if (in_WRITE_"+toString(num_write)+"_VAL = '1') then");
+    //     for (uint32_t num_word=0; num_word<_param->_nb_word; ++num_word)
+    //       {
+    //         vhdl->set_body   (3,"if (in_WRITE_"+toString(num_write)+"_ADDRESS = "+std_logic_cst(_param->_size_address,num_word)+") then");
+    //         vhdl->set_body   (4,"reg_DATA_"+toString(num_word)+" <= in_WRITE_"+toString(num_write)+"_DATA;");
+    //         vhdl->set_body   (3,"end if;");
+    //       }
+    //     vhdl->set_body   (2,"end if;");
+    //   }
+    
+    // vhdl->set_body   (1,"end if;");
+    // vhdl->set_body   (0,"end process RegisterFile_write;");
+
+    vhdl->set_body   (0,"combinatory : process (");
+    for (uint32_t num_read=0; num_read<_param->_nb_port_read; ++num_read)
+      {
+        vhdl->set_body   (1,"in_READ_"+toString(num_read)+"_VAL,");
+	if (_param->_have_port_address)
+        vhdl->set_body   (1,"in_READ_"+toString(num_read)+"_ADDRESS,");
+      }
+    for (uint32_t num_write=0; num_write<_param->_nb_port_write; ++num_write)
+      {
+        vhdl->set_body   (1,"in_WRITE_"+toString(num_write)+"_VAL,");
+	if (_param->_have_port_address)
+        vhdl->set_body   (1,"in_WRITE_"+toString(num_write)+"_ADDRESS,");
+        vhdl->set_body   (1,"in_WRITE_"+toString(num_write)+"_DATA,");
+      }
+    for (uint32_t num_write = 0; num_write < _param->_nb_port_write; num_write++)
+    vhdl->set_body   (1,"in_NRESET,");
+    vhdl->set_body   (1,"reg_DATA)");
+    vhdl->set_body   (1,"variable sig_DATA : Treg;");
+    vhdl->set_body   (0,"begin");
+    vhdl->set_body   (1,"");
+    vhdl->set_body   (1,"sig_DATA := reg_DATA;");
+
+    vhdl->set_body   (1,"");
+    vhdl->set_body   (1," -- ack");
+    vhdl->set_body   (1,"");
+    
+    for (uint32_t i = 0; i < _param->_nb_port_read; i++)
+      vhdl->set_body   (1,"out_READ_"+toString(i)+"_ACK  <= '1';");
+    for (uint32_t i = 0; i < _param->_nb_port_write; i++)
+      vhdl->set_body   (1,"out_WRITE_"+toString(i)+"_ACK <= '1';");
+    for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
+      vhdl->set_body   (1,"out_READ_WRITE_"+toString(i)+"_ACK  <= '1';");
+    vhdl->set_body   (1,"");
+    vhdl->set_body   (1," -- Read");
+    vhdl->set_body   (1,"");
+
+    for (uint32_t i = 0; i < _param->_nb_port_read; i++)
+      {
+	std::string str_address;
+	if (_param->_have_port_address)
+	  str_address = "conv_integer(in_READ_"+toString(i)+"_ADDRESS)";
+	else
+	  str_address = "0";
+
+        vhdl->set_body   (1,"if (in_READ_"+toString(i)+"_VAL = '1') then"),
+	vhdl->set_body   (2,"out_READ_"+toString(i)+"_DATA <= sig_DATA.reg ("+str_address+");");
+        vhdl->set_body   (1,"else"),
+	vhdl->set_body   (2,"out_READ_"+toString(i)+"_DATA <= "+std_logic_others(_param->_size_word,0)+";");
+        vhdl->set_body   (1,"end if;");
+      }
+    vhdl->set_body   (1,"");
+    vhdl->set_body   (1," -- write");
+    vhdl->set_body   (1,"");
+
+    for (uint32_t i = 0; i < _param->_nb_port_write; i++)
+      {
+	std::string str_address;
+	if (_param->_have_port_address)
+	  str_address = "conv_integer(in_WRITE_"+toString(i)+"_ADDRESS)";
+	else
+	  str_address = "0";
+
+	vhdl->set_body   (1,"if (in_WRITE_"+toString(i)+"_VAL = '1') then");
+	vhdl->set_body   (2,"sig_DATA.reg("+str_address+") := in_WRITE_"+toString(i)+"_DATA;");
+	vhdl->set_body   (1,"end if;");
+      }
+
+    vhdl->set_body   (1,"");
+    vhdl->set_body   (1,"reg_DATA_next <= sig_DATA;");
+    vhdl->set_body   (1,"");
+    vhdl->set_body   (0,"end process combinatory;");
+
+
+    vhdl->set_body   (0,"sequential: process (in_CLOCK)");
+    vhdl->set_body   (0,"begin");
+    vhdl->set_body   (1,"if rising_edge(in_CLOCK) then");
+    vhdl->set_body   (2,"reg_DATA <= reg_DATA_NEXT;");
+    vhdl->set_body   (1,"end if;");
+    vhdl->set_body   (0,"end process sequential;");
+
+#endif
+
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_declaration.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_declaration.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_declaration.cpp	(revision 145)
@@ -18,7 +18,18 @@
   void RegisterFile_Monolithic::vhdl_declaration (Vhdl * & vhdl)
   {
+#ifndef VHDL_GAISLER
     vhdl->set_type ("Tregfile", "array " + _std_logic_range(_param->_nb_word) + " of " + std_logic(_param->_size_word));
 
     vhdl->set_signal ("reg_DATA", "Tregfile");
+#else
+    // for (uint32_t i=0; i<_param->_nb_word; ++i)
+    //   vhdl->set_signal ("reg_DATA_"+toString(i), _param->_size_word);
+
+    vhdl->set_type ("Tregfile", "array " + _std_logic_range(_param->_nb_word) + " of " + std_logic(_param->_size_word));
+    vhdl->set_type ("Treg", "record reg : Tregfile; end record");
+
+    vhdl->set_signal ("reg_DATA"     , "Treg");
+    vhdl->set_signal ("reg_DATA_next", "Treg");
+#endif
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/16x_1r_1w.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/16x_1r_1w.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-12	12	*2	# nb_port_read
-6	6	*2	# nb_port_write
-256	256	+1	# nb_word
-32	32	*2 	# size_word
-16	16	*2	# nb_bank
-1  	1   	*2	# nb_port_read_by_bank
-1 	1	*2	# nb_port_write_by_bank
-0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/16x_2r_1w.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/16x_2r_1w.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-12	12	*2	# nb_port_read
-6	6	*2	# nb_port_write
-256	256	+1	# nb_word
-32	32	*2 	# size_word
-16	16	*2	# nb_bank
-2  	2   	*2	# nb_port_read_by_bank
-1 	1	*2	# nb_port_write_by_bank
-0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/2x_10r_5w.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/2x_10r_5w.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-12	12	*2	# nb_port_read
-6	6	*2	# nb_port_write
-256	256	+1	# nb_word
-32	32	*2 	# size_word
-2	2	*2	# nb_bank
-10  	10  	*2	# nb_port_read_by_bank
-5 	5	*2	# nb_port_write_by_bank
-0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/2x_6r_3w.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/2x_6r_3w.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-12	12	*2	# nb_port_read
-6	6	*2	# nb_port_write
-256	256	+1	# nb_word
-32	32	*2 	# size_word
-2	2	*2	# nb_bank
-6  	6   	*2	# nb_port_read_by_bank
-3 	3	*2	# nb_port_write_by_bank
-0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/2x_8r_4w.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/2x_8r_4w.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-12	12	*2	# nb_port_read
-6	6	*2	# nb_port_write
-256	256	+1	# nb_word
-32	32	*2 	# size_word
-2	2	*2	# nb_bank
-8  	8   	*2	# nb_port_read_by_bank
-4 	4	*2	# nb_port_write_by_bank
-0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/32x_1r_1w.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/32x_1r_1w.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-12	12	*2	# nb_port_read
-6	6	*2	# nb_port_write
-256	256	+1	# nb_word
-32	32	*2 	# size_word
-32	32	*2	# nb_bank
-1  	1   	*2	# nb_port_read_by_bank
-1 	1	*2	# nb_port_write_by_bank
-0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/4x_4r_2w.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/4x_4r_2w.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-12	12	*2	# nb_port_read
-6	6	*2	# nb_port_write
-256	256	+1	# nb_word
-32	32	*2 	# size_word
-4	4	*2	# nb_bank
-4  	4   	*2	# nb_port_read_by_bank
-2 	2	*2	# nb_port_write_by_bank
-0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/4x_6r_3w.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/4x_6r_3w.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-12	12	*2	# nb_port_read
-6	6	*2	# nb_port_write
-256	256	+1	# nb_word
-32	32	*2 	# size_word
-4	4	*2	# nb_bank
-6  	6   	*2	# nb_port_read_by_bank
-3 	3	*2	# nb_port_write_by_bank
-0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/4x_8r_4w.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/4x_8r_4w.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-12	12	*2	# nb_port_read
-6	6	*2	# nb_port_write
-256	256	+1	# nb_word
-32	32	*2 	# size_word
-4	4	*2	# nb_bank
-8  	8   	*2	# nb_port_read_by_bank
-4 	4	*2	# nb_port_write_by_bank
-0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/8x_2r_1w.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/8x_2r_1w.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-12	12	*2	# nb_port_read
-6	6	*2	# nb_port_write
-256	256	+1	# nb_word
-32	32	*2 	# size_word
-8	8	*2	# nb_bank
-2  	2   	*2	# nb_port_read_by_bank
-1 	1	*2	# nb_port_write_by_bank
-0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/8x_4r_2w.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/8x_4r_2w.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-12	12	*2	# nb_port_read
-6	6	*2	# nb_port_write
-256	256	+1	# nb_word
-32	32	*2 	# size_word
-8	8	*2	# nb_bank
-4  	4   	*2	# nb_port_read_by_bank
-2 	2	*2	# nb_port_write_by_bank
-0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/Makefile	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/Makefile	(revision 145)
@@ -9,5 +9,5 @@
 #-----[ Directory ]----------------------------------------
 DIR_COMPONENT			= ../
-include				$(DIR_COMPONENT)/Makefile.defs
+include                         $(DIR_COMPONENT)/Makefile.defs                                                                                                                                                   
 
 LIBRARY				= $(RegisterFile_Multi_Banked_LIBRARY)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/config-mono_bank-mux_port.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/config-mono_bank-mux_port.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-11	11	*2	# nb_port_read
-5	5	*2	# nb_port_write
-256  	256    	+1	# nb_word
-32	32	*2	# size_word
-1	1	*2	# nb_bank
-4 	4  	*2	# nb_port_read_by_bank
-2	2	*2	# nb_port_write_by_bank
-0	1	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/config-mono_bank.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/config-mono_bank.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-11	11	*2	# nb_port_read
-5	5	*2	# nb_port_write
-256  	256    	+1	# nb_word
-32	32	*2	# size_word
-1	1	*2	# nb_bank
-11	11 	*2	# nb_port_read_by_bank
-5	5	*2	# nb_port_write_by_bank
-0	1	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/config-multi_bank.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/config-multi_bank.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-11	11	*2	# nb_port_read
-5	5	*2	# nb_port_write
-256  	256    	+1	# nb_word
-32	32	*2	# size_word
-2	16	*2	# nb_bank
-3	3 	*2	# nb_port_read_by_bank
-2	2	*2	# nb_port_write_by_bank
-0	1	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/config-one_reg.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/config-one_reg.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-11	11	*2	# nb_port_read
-5	5	*2	# nb_port_write
-256  	256    	+1	# nb_word
-32	32	*2	# size_word
-256	256	*2	# nb_bank
-3	3 	*2	# nb_port_read_by_bank
-2	2	*2	# nb_port_write_by_bank
-0	1	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/config-size.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/config-size.cfg	(revision 144)
+++ 	(revision )
@@ -1,9 +1,0 @@
-RegisterFile_Multi_Banked
-11	11	*2	# nb_port_read
-5	5	*2	# nb_port_write
-1  	32    	*2	# nb_word
-32	32	*2	# size_word
-1	1	*2	# nb_bank
-3	3 	*2	# nb_port_read_by_bank
-2	2	*2	# nb_port_write_by_bank
-0	1	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/16x_1r_1w.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/16x_1r_1w.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/16x_1r_1w.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+12	12	*2	# nb_port_read
+6	6	*2	# nb_port_write
+256	256	+1	# nb_word
+32	32	*2 	# size_word
+16	16	*2	# nb_bank
+1  	1   	*2	# nb_port_read_by_bank
+1 	1	*2	# nb_port_write_by_bank
+0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/16x_2r_1w.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/16x_2r_1w.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/16x_2r_1w.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+12	12	*2	# nb_port_read
+6	6	*2	# nb_port_write
+256	256	+1	# nb_word
+32	32	*2 	# size_word
+16	16	*2	# nb_bank
+2  	2   	*2	# nb_port_read_by_bank
+1 	1	*2	# nb_port_write_by_bank
+0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/2x_10r_5w.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/2x_10r_5w.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/2x_10r_5w.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+12	12	*2	# nb_port_read
+6	6	*2	# nb_port_write
+256	256	+1	# nb_word
+32	32	*2 	# size_word
+2	2	*2	# nb_bank
+10  	10  	*2	# nb_port_read_by_bank
+5 	5	*2	# nb_port_write_by_bank
+0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/2x_6r_3w.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/2x_6r_3w.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/2x_6r_3w.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+12	12	*2	# nb_port_read
+6	6	*2	# nb_port_write
+256	256	+1	# nb_word
+32	32	*2 	# size_word
+2	2	*2	# nb_bank
+6  	6   	*2	# nb_port_read_by_bank
+3 	3	*2	# nb_port_write_by_bank
+0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/2x_8r_4w.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/2x_8r_4w.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/2x_8r_4w.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+12	12	*2	# nb_port_read
+6	6	*2	# nb_port_write
+256	256	+1	# nb_word
+32	32	*2 	# size_word
+2	2	*2	# nb_bank
+8  	8   	*2	# nb_port_read_by_bank
+4 	4	*2	# nb_port_write_by_bank
+0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/32x_1r_1w.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/32x_1r_1w.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/32x_1r_1w.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+12	12	*2	# nb_port_read
+6	6	*2	# nb_port_write
+256	256	+1	# nb_word
+32	32	*2 	# size_word
+32	32	*2	# nb_bank
+1  	1   	*2	# nb_port_read_by_bank
+1 	1	*2	# nb_port_write_by_bank
+0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/4x_4r_2w.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/4x_4r_2w.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/4x_4r_2w.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+12	12	*2	# nb_port_read
+6	6	*2	# nb_port_write
+256	256	+1	# nb_word
+32	32	*2 	# size_word
+4	4	*2	# nb_bank
+4  	4   	*2	# nb_port_read_by_bank
+2 	2	*2	# nb_port_write_by_bank
+0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/4x_6r_3w.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/4x_6r_3w.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/4x_6r_3w.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+12	12	*2	# nb_port_read
+6	6	*2	# nb_port_write
+256	256	+1	# nb_word
+32	32	*2 	# size_word
+4	4	*2	# nb_bank
+6  	6   	*2	# nb_port_read_by_bank
+3 	3	*2	# nb_port_write_by_bank
+0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/4x_8r_4w.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/4x_8r_4w.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/4x_8r_4w.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+12	12	*2	# nb_port_read
+6	6	*2	# nb_port_write
+256	256	+1	# nb_word
+32	32	*2 	# size_word
+4	4	*2	# nb_bank
+8  	8   	*2	# nb_port_read_by_bank
+4 	4	*2	# nb_port_write_by_bank
+0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/8x_2r_1w.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/8x_2r_1w.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/8x_2r_1w.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+12	12	*2	# nb_port_read
+6	6	*2	# nb_port_write
+256	256	+1	# nb_word
+32	32	*2 	# size_word
+8	8	*2	# nb_bank
+2  	2   	*2	# nb_port_read_by_bank
+1 	1	*2	# nb_port_write_by_bank
+0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/8x_4r_2w.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/8x_4r_2w.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/8x_4r_2w.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+12	12	*2	# nb_port_read
+6	6	*2	# nb_port_write
+256	256	+1	# nb_word
+32	32	*2 	# size_word
+8	8	*2	# nb_bank
+4  	4   	*2	# nb_port_read_by_bank
+2 	2	*2	# nb_port_write_by_bank
+0	0	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-mono_bank-mux_port.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-mono_bank-mux_port.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-mono_bank-mux_port.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+11	11	*2	# nb_port_read
+5	5	*2	# nb_port_write
+256  	256    	+1	# nb_word
+32	32	*2	# size_word
+1	1	*2	# nb_bank
+4 	4  	*2	# nb_port_read_by_bank
+2	2	*2	# nb_port_write_by_bank
+0	1	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-mono_bank.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-mono_bank.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-mono_bank.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+11	11	*2	# nb_port_read
+5	5	*2	# nb_port_write
+256  	256    	+1	# nb_word
+32	32	*2	# size_word
+1	1	*2	# nb_bank
+11	11 	*2	# nb_port_read_by_bank
+5	5	*2	# nb_port_write_by_bank
+0	1	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-multi_bank.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-multi_bank.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-multi_bank.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+11	11	*2	# nb_port_read
+5	5	*2	# nb_port_write
+256  	256    	+1	# nb_word
+32	32	*2	# size_word
+2	16	*2	# nb_bank
+3	3 	*2	# nb_port_read_by_bank
+2	2	*2	# nb_port_write_by_bank
+0	1	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-one_reg.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-one_reg.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-one_reg.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+11	11	*2	# nb_port_read
+5	5	*2	# nb_port_write
+256  	256    	+1	# nb_word
+32	32	*2	# size_word
+256	256	*2	# nb_bank
+3	3 	*2	# nb_port_read_by_bank
+2	2	*2	# nb_port_write_by_bank
+0	1	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-size.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-size.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/configuration/config-size.gen	(revision 145)
@@ -0,0 +1,9 @@
+RegisterFile_Multi_Banked
+11	11	*2	# nb_port_read
+5	5	*2	# nb_port_write
+1  	32    	*2	# nb_word
+32	32	*2	# size_word
+1	1	*2	# nb_bank
+3	3 	*2	# nb_port_read_by_bank
+2	2	*2	# nb_port_write_by_bank
+0	1	+1	# crossbar
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info	(revision 145)
@@ -1,11 +1,61 @@
 
-# RegisterFile_Multi_Banked_0
-target_dep	all	RegisterFile_Multi_Banked_0.ngc
-target_dep	RegisterFile_Multi_Banked_0.ngc	RegisterFile_Multi_Banked_0.prj
-target_dep	RegisterFile_Multi_Banked_0.prj	RegisterFile_Multi_Banked_0_bank_Pack.vhdl RegisterFile_Multi_Banked_0_bank.vhdl RegisterFile_Multi_Banked_0_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports.vhdl RegisterFile_Multi_Banked_0_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_2_ports.vhdl RegisterFile_Multi_Banked_0.vhdl
+# info_00
+target_dep	all	info_00.ngc
+target_dep	info_00.ngc	info_00.prj
+target_dep	info_00.prj	info_00_bank_Pack.vhdl info_00_bank.vhdl info_00_Pack.vhdl info_00_select_4_ports_Pack.vhdl info_00_select_4_ports.vhdl info_00_select_8_ports_Pack.vhdl info_00_select_8_ports.vhdl info_00.vhdl
 
-# RegisterFile_Multi_Banked_1
-target_dep	all	RegisterFile_Multi_Banked_1.ngc
-target_dep	RegisterFile_Multi_Banked_1.ngc	RegisterFile_Multi_Banked_1.prj
-target_dep	RegisterFile_Multi_Banked_1.prj	RegisterFile_Multi_Banked_1_bank_Pack.vhdl RegisterFile_Multi_Banked_1_bank.vhdl RegisterFile_Multi_Banked_1_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports.vhdl RegisterFile_Multi_Banked_1_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_2_ports.vhdl RegisterFile_Multi_Banked_1.vhdl
+# info_01
+target_dep	all	info_01.ngc
+target_dep	info_01.ngc	info_01.prj
+target_dep	info_01.prj	info_01_bank_Pack.vhdl info_01_bank.vhdl info_01_Pack.vhdl info_01_select_4_ports_Pack.vhdl info_01_select_4_ports.vhdl info_01_select_8_ports_Pack.vhdl info_01_select_8_ports.vhdl info_01.vhdl
 
+# info_02
+target_dep	all	info_02.ngc
+target_dep	info_02.ngc	info_02.prj
+target_dep	info_02.prj	info_02_bank_Pack.vhdl info_02_bank.vhdl info_02_Pack.vhdl info_02_select_4_ports_Pack.vhdl info_02_select_4_ports.vhdl info_02_select_8_ports_Pack.vhdl info_02_select_8_ports.vhdl info_02.vhdl
+
+# info_03
+target_dep	all	info_03.ngc
+target_dep	info_03.ngc	info_03.prj
+target_dep	info_03.prj	info_03_bank_Pack.vhdl info_03_bank.vhdl info_03_Pack.vhdl info_03_select_16_ports_Pack.vhdl info_03_select_16_ports.vhdl info_03_select_4_ports_Pack.vhdl info_03_select_4_ports.vhdl info_03.vhdl
+
+# info_04
+target_dep	all	info_04.ngc
+target_dep	info_04.ngc	info_04.prj
+target_dep	info_04.prj	info_04_bank_Pack.vhdl info_04_bank.vhdl info_04_Pack.vhdl info_04_select_16_ports_Pack.vhdl info_04_select_16_ports.vhdl info_04_select_4_ports_Pack.vhdl info_04_select_4_ports.vhdl info_04.vhdl
+
+# info_05
+target_dep	all	info_05.ngc
+target_dep	info_05.ngc	info_05.prj
+target_dep	info_05.prj	info_05_bank_Pack.vhdl info_05_bank.vhdl info_05_Pack.vhdl info_05_select_16_ports_Pack.vhdl info_05_select_16_ports.vhdl info_05_select_4_ports_Pack.vhdl info_05_select_4_ports.vhdl info_05.vhdl
+
+# result_06
+target_dep	all	result_06.ngc
+target_dep	result_06.ngc	result_06.prj
+target_dep	result_06.prj	result_06_bank_Pack.vhdl result_06_bank.vhdl result_06_Pack.vhdl result_06_select_4_ports_Pack.vhdl result_06_select_4_ports.vhdl result_06_select_8_ports_Pack.vhdl result_06_select_8_ports.vhdl result_06.vhdl
+
+# result_07
+target_dep	all	result_07.ngc
+target_dep	result_07.ngc	result_07.prj
+target_dep	result_07.prj	result_07_bank_Pack.vhdl result_07_bank.vhdl result_07_Pack.vhdl result_07_select_4_ports_Pack.vhdl result_07_select_4_ports.vhdl result_07_select_8_ports_Pack.vhdl result_07_select_8_ports.vhdl result_07.vhdl
+
+# result_08
+target_dep	all	result_08.ngc
+target_dep	result_08.ngc	result_08.prj
+target_dep	result_08.prj	result_08_bank_Pack.vhdl result_08_bank.vhdl result_08_Pack.vhdl result_08_select_4_ports_Pack.vhdl result_08_select_4_ports.vhdl result_08_select_8_ports_Pack.vhdl result_08_select_8_ports.vhdl result_08.vhdl
+
+# result_09
+target_dep	all	result_09.ngc
+target_dep	result_09.ngc	result_09.prj
+target_dep	result_09.prj	result_09_bank_Pack.vhdl result_09_bank.vhdl result_09_Pack.vhdl result_09_select_16_ports_Pack.vhdl result_09_select_16_ports.vhdl result_09_select_4_ports_Pack.vhdl result_09_select_4_ports.vhdl result_09.vhdl
+
+# result_10
+target_dep	all	result_10.ngc
+target_dep	result_10.ngc	result_10.prj
+target_dep	result_10.prj	result_10_bank_Pack.vhdl result_10_bank.vhdl result_10_Pack.vhdl result_10_select_16_ports_Pack.vhdl result_10_select_16_ports.vhdl result_10_select_4_ports_Pack.vhdl result_10_select_4_ports.vhdl result_10.vhdl
+
+# result_11
+target_dep	all	result_11.ngc
+target_dep	result_11.ngc	result_11.prj
+target_dep	result_11.prj	result_11_bank_Pack.vhdl result_11_bank.vhdl result_11_Pack.vhdl result_11_select_16_ports_Pack.vhdl result_11_select_16_ports.vhdl result_11_select_4_ports_Pack.vhdl result_11_select_4_ports.vhdl result_11.vhdl
+
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/main.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/main.cpp	(revision 145)
@@ -8,5 +8,5 @@
 #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/include/test.h"
 
-#define NB_PARAMS 0
+#define NB_PARAMS 8
 
 void usage (int argc, char * argv[])
@@ -40,5 +40,5 @@
     usage (argc, argv);
 
-  const string   name      = argv[1];
+  const string      name                  = argv[1];
   const uint32_t    nb_port_read          = atoi(argv[2]);
   const uint32_t    nb_port_write         = atoi(argv[3]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp	(revision 145)
@@ -42,6 +42,8 @@
      _param,
      _usage);
-  
-#ifdef SYSTEMC
+
+#if 0  
+// #ifdef SYSTEMC
+
   /*********************************************************************
    * Déclarations des signaux
@@ -229,5 +231,4 @@
    ********************************************************/
 
-  TEST_OK("End of Simulation");
   delete _time;
   cout << "<" << name << "> ............ Stop Simulation" << endl;
@@ -236,4 +237,5 @@
   delete NRESET;
 #endif
+  TEST_OK("End of Simulation");
 
   delete _RegisterFile_Multi_Banked;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Types.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Types.h	(revision 145)
@@ -19,4 +19,5 @@
 
 //typedef uint32_t Taddress_t;
+//typedef uint64_t Tdata_t;
   typedef Tgeneral_data_t Tdata_t;
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/config-mono_bank-mux_port.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/config-mono_bank-mux_port.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-RegisterFile
-11	11	*2	# nb_port_read
-5	5	*2	# nb_port_write
-256  	256    	+1	# nb_word
-32	32	*2	# size_word
-1	1	*2	# nb_bank
-4 	4  	*2	# nb_port_read_by_bank
-2	2	*2	# nb_port_write_by_bank
-0	1	+1	# crossbar
-0	1	+1	# Monolithic / Multi Banked
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/config-mono_bank.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/config-mono_bank.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-RegisterFile
-11	11	*2	# nb_port_read
-5	5	*2	# nb_port_write
-256  	256    	+1	# nb_word
-32	32	*2	# size_word
-1	1	*2	# nb_bank
-11	11 	*2	# nb_port_read_by_bank
-5	5	*2	# nb_port_write_by_bank
-0	1	+1	# crossbar
-0	1	+1	# Monolithic / Multi Banked
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/config-multi_bank.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/config-multi_bank.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-RegisterFile
-11	11	*2	# nb_port_read
-5	5	*2	# nb_port_write
-256  	256    	+1	# nb_word
-32	32	*2	# size_word
-2	16	*2	# nb_bank
-3	3 	*2	# nb_port_read_by_bank
-2	2	*2	# nb_port_write_by_bank
-0	1	+1	# crossbar
-0	1	+1	# Monolithic / Multi Banked
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/config-one_reg.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/config-one_reg.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-RegisterFile
-11	11	*2	# nb_port_read
-5	5	*2	# nb_port_write
-256  	256    	+1	# nb_word
-32	32	*2	# size_word
-256	256	*2	# nb_bank
-3	3 	*2	# nb_port_read_by_bank
-2	2	*2	# nb_port_write_by_bank
-0	1	+1	# crossbar
-0	1	+1	# Monolithic / Multi Banked
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/config-size.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/config-size.cfg	(revision 144)
+++ 	(revision )
@@ -1,10 +1,0 @@
-RegisterFile
-11	11	*2	# nb_port_read
-5	5	*2	# nb_port_write
-1  	32    	*2	# nb_word
-32	32	*2	# size_word
-1	1	*2	# nb_bank
-3	3 	*2	# nb_port_read_by_bank
-2	2	*2	# nb_port_write_by_bank
-0	1	+1	# crossbar
-0	1	+1	# Monolithic / Multi Banked
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-mono_bank-mux_port.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-mono_bank-mux_port.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-mono_bank-mux_port.gen	(revision 145)
@@ -0,0 +1,10 @@
+RegisterFile
+11	11	*2	# nb_port_read
+5	5	*2	# nb_port_write
+256  	256    	+1	# nb_word
+32	32	*2	# size_word
+1	1	*2	# nb_bank
+4 	4  	*2	# nb_port_read_by_bank
+2	2	*2	# nb_port_write_by_bank
+0	1	+1	# crossbar
+0	1	+1	# Monolithic / Multi Banked
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-mono_bank.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-mono_bank.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-mono_bank.gen	(revision 145)
@@ -0,0 +1,10 @@
+RegisterFile
+11	11	*2	# nb_port_read
+5	5	*2	# nb_port_write
+256  	256    	+1	# nb_word
+32	32	*2	# size_word
+1	1	*2	# nb_bank
+11	11 	*2	# nb_port_read_by_bank
+5	5	*2	# nb_port_write_by_bank
+0	1	+1	# crossbar
+0	1	+1	# Monolithic / Multi Banked
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-multi_bank.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-multi_bank.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-multi_bank.gen	(revision 145)
@@ -0,0 +1,10 @@
+RegisterFile
+11	11	*2	# nb_port_read
+5	5	*2	# nb_port_write
+256  	256    	+1	# nb_word
+32	32	*2	# size_word
+2	16	*2	# nb_bank
+3	3 	*2	# nb_port_read_by_bank
+2	2	*2	# nb_port_write_by_bank
+0	1	+1	# crossbar
+0	1	+1	# Monolithic / Multi Banked
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-one_reg.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-one_reg.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-one_reg.gen	(revision 145)
@@ -0,0 +1,10 @@
+RegisterFile
+11	11	*2	# nb_port_read
+5	5	*2	# nb_port_write
+256  	256    	+1	# nb_word
+32	32	*2	# size_word
+256	256	*2	# nb_bank
+3	3 	*2	# nb_port_read_by_bank
+2	2	*2	# nb_port_write_by_bank
+0	1	+1	# crossbar
+0	1	+1	# Monolithic / Multi Banked
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-size.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-size.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration/config-size.gen	(revision 145)
@@ -0,0 +1,10 @@
+RegisterFile
+11	11	*2	# nb_port_read
+5	5	*2	# nb_port_write
+1  	32    	*2	# nb_word
+32	32	*2	# size_word
+1	1	*2	# nb_bank
+3	3 	*2	# nb_port_read_by_bank
+2	2	*2	# nb_port_write_by_bank
+0	1	+1	# crossbar
+0	1	+1	# Monolithic / Multi Banked
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_compact.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_compact.cfg	(revision 144)
+++ 	(revision )
@@ -1,4 +1,0 @@
-Select_Priority_Fixed
-2	16	*2	# nb_entity
-0	0	+1	# encoding_one_hot
-1	1	+1	# encoding_compact
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_dual.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_dual.cfg	(revision 144)
+++ 	(revision )
@@ -1,4 +1,0 @@
-Select_Priority_Fixed
-2	16	*2	# nb_entity
-1	1	+1	# encoding_one_hot
-1	1	+1	# encoding_compact
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_one_hot.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_one_hot.cfg	(revision 144)
+++ 	(revision )
@@ -1,4 +1,0 @@
-Select_Priority_Fixed
-2	16	*2	# nb_entity
-1	1	+1	# encoding_one_hot
-0	0	+1	# encoding_compact
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/configuration/config_compact.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/configuration/config_compact.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/configuration/config_compact.gen	(revision 145)
@@ -0,0 +1,4 @@
+Select_Priority_Fixed
+2	16	*2	# nb_entity
+0	0	+1	# encoding_one_hot
+1	1	+1	# encoding_compact
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/configuration/config_dual.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/configuration/config_dual.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/configuration/config_dual.gen	(revision 145)
@@ -0,0 +1,4 @@
+Select_Priority_Fixed
+2	16	*2	# nb_entity
+1	1	+1	# encoding_one_hot
+1	1	+1	# encoding_compact
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/configuration/config_one_hot.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/configuration/config_one_hot.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/configuration/config_one_hot.gen	(revision 145)
@@ -0,0 +1,4 @@
+Select_Priority_Fixed
+2	16	*2	# nb_entity
+1	1	+1	# encoding_one_hot
+0	0	+1	# encoding_compact
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/config_rotate.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/config_rotate.cfg	(revision 144)
+++ 	(revision )
@@ -1,7 +1,0 @@
-Shifter
-16	16	*4	# size_data  
-2	2	+1	# nb_port    
-0	0       +1	# shift_value
-1	2	+1	# rotate     
-0	2	+1	# direction  
-0	0	+1	# carry      
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/config_shift.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/config_shift.cfg	(revision 144)
+++ 	(revision )
@@ -1,7 +1,0 @@
-Shifter
-16	16	*4	# size_data  
-1	2	+1	# nb_port    
-0	2	+1	# shift_value
-0	0	+1	# rotate     
-0	2	+1	# direction  
-0	2	+1	# carry      
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,7 +1,0 @@
-Shifter
-16	16	*4	# size_data  
-1	2	+1	# nb_port    
-0	2	+1	# shift_value
-0	0	+1	# rotate     
-0	2	+1	# direction  
-0	2	+1	# carry      
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration/config_rotate.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration/config_rotate.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration/config_rotate.gen	(revision 145)
@@ -0,0 +1,7 @@
+Shifter
+16	16	*4	# size_data  
+2	2	+1	# nb_port    
+0	0       +1	# shift_value
+1	2	+1	# rotate     
+0	2	+1	# direction  
+0	0	+1	# carry      
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration/config_shift.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration/config_shift.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration/config_shift.gen	(revision 145)
@@ -0,0 +1,7 @@
+Shifter
+16	16	*4	# size_data  
+1	2	+1	# nb_port    
+0	2	+1	# shift_value
+0	0	+1	# rotate     
+0	2	+1	# direction  
+0	2	+1	# carry      
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,7 @@
+Shifter
+16	16	*4	# size_data  
+1	2	+1	# nb_port    
+0	2	+1	# shift_value
+0	0	+1	# rotate     
+0	2	+1	# direction  
+0	2	+1	# carry      
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,7 +1,0 @@
-Sort
-8	8	*2	# nb_input           
-1	8	*2	# nb_output          
-1	1	+1	# ascending          
-16	16	*2	# size_data          
-1	1	+1	# have_port_index_out
-1	1	+1	# have_port_data_out 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,7 @@
+Sort
+8	8	*2	# nb_input           
+1	8	*2	# nb_output          
+1	1	+1	# ascending          
+16	16	*2	# size_data          
+1	1	+1	# have_port_index_out
+1	1	+1	# have_port_data_out 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,6 +1,0 @@
-Victim
-3	3	+1	# victim_scheme
-2	8	*4	# nb_entity    
-1	8	*4	# nb_entry     
-1	4	*4	# nb_access    
-0	1	+1	# table_global 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,6 @@
+Victim
+3	3	+1	# victim_scheme
+2	8	*4	# nb_entity    
+1	8	*4	# nb_entry     
+1	4	*4	# nb_access    
+0	1	+1	# table_global 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,5 +1,0 @@
-Victim_Pseudo_LRU
-4	16	*4	# nb_entity 
-1	4	*4	# nb_access		# 1	4	*4	# nb_update 
-1	16	*4	# size_table
-0	1	+1	# table_global
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,5 @@
+Victim_Pseudo_LRU
+4	16	*4	# nb_entity 
+1	4	*4	# nb_access		# 1	4	*4	# nb_update 
+1	16	*4	# size_table
+0	1	+1	# table_global
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Selftest
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Selftest	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Selftest	(revision 145)
@@ -8,17 +8,17 @@
 
 #-----[ Directory ]----------------------------------------
-DIR_BIN				= $(DIR_TMP)/bin
-DIR_CFG_GEN			= $(DIR_TMP)/configuration_generated
+DIR_BIN				= $(DIR_TMP)/bin/$(ENTITY)
+DIR_CFG_GEN			= $(DIR_TMP)/configuration_generated/$(ENTITY)
 DIR_CFG_USER			= configuration
 DIR_LOG				= log
 
 #-----[ Variables ]----------------------------------------
-CFG_FILE_EXTENSION		= cfg
-CFG_FILE_DEBUG       		= debug.$(CFG_FILE_EXTENSION)
+CFG_FILE_PATH                   = $(DIR_CFG_USER)
+CFG_FILE_EXTENSION		= gen
+CFG_FILE_DEBUG       		= $(CFG_FILE_PATH)/debug.$(CFG_FILE_EXTENSION)
 
 OBJECTS      			= $(OBJECTS_COMMON)
 
 LIBS		   		= -lm $(SYSTEMC_LIBNAME_$(SIMULATOR_SYSTEMC))
-#                                 $(OR1K_LIBNAME) -lbfd  
 
 MODELTECH_LIBRARY               = $(addprefix -lib ,$(addsuffix .a, $(subst -l,$(DIR_LIB)/lib,$(LIBRARY))))
@@ -29,5 +29,5 @@
 EXEC_PARAMS 			= $(SYSTEMC_EXEC_PARAMS_$(SIMULATOR_SYSTEMC))
 EXEC_LOG			= $(patsubst $(DIR_CFG_GEN)/%.cfg,$(DIR_LOG)/%.exec.log,$(wildcard $(DIR_CFG_GEN)/*.cfg))	\
-				  $(patsubst $(DIR_CFG_USER)/%.cfg,$(DIR_LOG)/%.exec.log,$(wildcard $(DIR_CFG_USER)/*.cfg))
+				  $(patsubst $(DIR_CFG_USER)/%.cfg,$(DIR_LOG)/%.exec.log,$(wildcard $(DIR_CFG_GEN)/*.cfg))
 BIN				= Selftest.x
 EXEC				= $(DIR_BIN)/$(BIN)
@@ -37,5 +37,4 @@
 #.NOTPARALLEL			: clean clean_all help
 
-vpath	%.cfg	$(DIR_CFG_USER):$(DIR_CFG_GEN)
 vpath	%.x	$(DIR_BIN)
 
@@ -47,5 +46,5 @@
 execute_only                    : 
 				@\
-				$(MAKE) $(EXEC_LOG);					\
+                                $(MAKE) $(EXEC_LOG);\
 				declare -i all_ok=1;					\
 				for i in $(EXEC_LOG); do				\
@@ -86,5 +85,5 @@
 					files=$(CFG_FILE_DEBUG);									\
 				else													\
-					files=$$($(LS) *.$(CFG_FILE_EXTENSION) );							\
+					files=$$($(LS) $(CFG_FILE_PATH)/*.$(CFG_FILE_EXTENSION) );							\
 				fi;													\
 																	\
@@ -172,5 +171,5 @@
 				done;
 
-$(DIR_LOG)/%.exec.log		: %.cfg  $(EXEC)
+$(DIR_LOG)/%.exec.log		: $(DIR_CFG_GEN)/%.cfg  $(EXEC)
 				@\
 				$(ECHO) "Execute            : $*";\
@@ -218,8 +217,17 @@
 				esac;
 
-$(DIR_BIN) $(DIR_LOG) $(DIR_CFG_GEN) :
+$(DIR_BIN) $(DIR_LOG)		:
 				@\
 				$(ECHO) "Create directory   : $@";\
-				$(MKDIR) $@;
+				$(MKDIR) $@;\
+
+$(DIR_CFG_GEN)			:
+				@\
+				$(ECHO) "Create directory   : $@";\
+				$(MKDIR) $@;\
+				$(LS) $(DIR_CFG_USER)/*.cfg &> /dev/null; \
+				if $(TEST) $$? -eq 0; then \
+					$(CP) $(DIR_CFG_USER)/*.cfg $@; \
+				fi;
 
 selftest_clean			: local_clean config_clean 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf	(revision 145)
@@ -3,8 +3,11 @@
 #
 
-all: _Generic/Queue/SelfTest _Generic/RegisterFile/RegisterFile_Monolithic/SelfTest _Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest
+all: _Generic/Queue/SelfTest _Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest _Generic/RegisterFile/RegisterFile_Monolithic/SelfTest _Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest
 
 _Generic/Queue/SelfTest:
 	gmake all -C Generic/Queue/SelfTest
+
+_Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest:
+	gmake all -C Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest
 
 _Generic/RegisterFile/RegisterFile_Monolithic/SelfTest:
@@ -16,4 +19,5 @@
 clean:
 	gmake clean -C Generic/Queue/SelfTest
+	gmake clean -C Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest
 	gmake clean -C Generic/RegisterFile/RegisterFile_Monolithic/SelfTest
 	gmake clean -C Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest
@@ -23,4 +27,5 @@
 install:
 	gmake install -C Generic/Queue/SelfTest
+	gmake install -C Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest
 	gmake install -C Generic/RegisterFile/RegisterFile_Monolithic/SelfTest
 	gmake install -C Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,1 +1,0 @@
-@COMPONENT
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,1 @@
+@COMPONENT
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/configuration.cfg	(revision 144)
+++ 	(revision )
@@ -1,1 +1,0 @@
-@COMPONENT
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/configuration/configuration.gen
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/configuration/configuration.gen	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/configuration/configuration.gen	(revision 145)
@@ -0,0 +1,1 @@
+@COMPONENT
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/doc/sty/doc-style.sty
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/doc/sty/doc-style.sty	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/doc/sty/doc-style.sty	(revision 145)
@@ -3,5 +3,5 @@
 \usepackage{makeidx}
 \usepackage{palatino}
-\usepackage{fancyheadings}
+%\usepackage{fancyheadings}
 \usepackage{float}
 \usepackage{verbatim}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Allocation.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Allocation.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Allocation.h	(revision 145)
@@ -14,17 +14,21 @@
 // =====[ ALLOCATION / DELETE of ARRAY ]=================================
 // ======================================================================
-#define ALLOC0(var,type)                        \
+#define ALLOC0_COND(var,type,cond)              \
   do                                            \
     {                                           \
-      var = new type;                           \
-    } while (0)
-
-#define ALLOC1(var,type,s1)                     \
+      if (cond)                                 \
+        var = new type;                         \
+    } while (0)
+
+
+#define ALLOC1_COND(var,type,s1,cond)           \
   do                                            \
     {                                           \
-      var = new type [s1];                      \
-    } while (0)
-
-#define ALLOC2(var,type,s1,s2)                   \
+      if (cond)                                 \
+        var = new type [s1];                    \
+    } while (0)
+
+
+#define ALLOC2_COND(var,type,s1,s2,cond)         \
   do                                             \
     {                                            \
@@ -32,9 +36,10 @@
       for (uint32_t it1=0; it1<s1; ++it1)        \
         {                                        \
-          var [it1] = new type [s2];             \
+          if (cond)                              \
+            var [it1] = new type [s2];           \
         }                                        \
     } while (0)
 
-#define ALLOC3(var,type,s1,s2,s3)                \
+#define ALLOC3_COND(var,type,s1,s2,s3,cond)      \
   do                                             \
     {                                            \
@@ -45,50 +50,62 @@
           for (uint32_t it2=0; it2<s2; ++it2)    \
             {                                    \
-              var [it1][it2] = new type [s3];    \
+              if (cond)                          \
+                var [it1][it2] = new type [s3];  \
             }                                    \
         }                                        \
     } while (0)
 
-#define ALLOC4(var,type,s1,s2,s3,s4)                    \
-  do                                                    \
-    {                                                   \
-      var = new type *** [s1];                          \
-      for (uint32_t it1=0; it1<s1; ++it1)               \
-        {                                               \
-          var [it1] = new type ** [s2];                 \
-          for (uint32_t it2=0; it2<s2; ++it2)           \
-            {                                           \
-              var [it1][it2] = new type * [s3];         \
-              for (uint32_t it3=0; it3<s3; ++it3)       \
-                {                                       \
-                  var [it1][it2][it3] = new type [s4];  \
-                }                                       \
-            }                                           \
-        }                                               \
-    } while (0)
-
-#define DELETE0(var)                            \
+#define ALLOC4_COND(var,type,s1,s2,s3,s4,cond)                  \
+  do                                                            \
+    {                                                           \
+      var = new type *** [s1];                                  \
+      for (uint32_t it1=0; it1<s1; ++it1)                       \
+        {                                                       \
+          var [it1] = new type ** [s2];                         \
+          for (uint32_t it2=0; it2<s2; ++it2)                   \
+            {                                                   \
+              var [it1][it2] = new type * [s3];                 \
+              for (uint32_t it3=0; it3<s3; ++it3)               \
+                {                                               \
+                  if (cond)                                     \
+                    var [it1][it2][it3] = new type [s4];        \
+                }                                               \
+            }                                                   \
+        }                                                       \
+    } while (0)
+
+#define ALLOC0(var,type)             ALLOC0_COND(var,type,true)
+#define ALLOC1(var,type,s1)          ALLOC1_COND(var,type,s1,true)
+#define ALLOC2(var,type,s1,s2)       ALLOC2_COND(var,type,s1,s2,true)
+#define ALLOC3(var,type,s1,s2,s3)    ALLOC3_COND(var,type,s1,s2,s3,true)
+#define ALLOC4(var,type,s1,s2,s3,s4) ALLOC4_COND(var,type,s1,s2,s3,s4,true)
+
+
+#define DELETE0_COND(var,cond)                  \
   do                                            \
     {                                           \
-      delete var;                               \
-    } while (0)
-
-#define DELETE1(var,s1)                         \
+      if (cond)                                 \
+        delete var;                             \
+    } while (0)
+
+#define DELETE1_COND(var,s1,cond)               \
   do                                            \
     {                                           \
-      delete [] var;                            \
-    } while (0)
-
-#define DELETE2(var,s1,s2)                      \
+      if (cond)                                 \
+        delete [] var;                          \
+    } while (0)
+
+#define DELETE2_COND(var,s1,s2,cond)            \
   do                                            \
     {                                            \
       for (uint32_t it1=0; it1<s1; ++it1)        \
         {                                        \
-          delete [] var [it1];                   \
+          if (cond)                              \
+            delete [] var [it1];                 \
         }                                        \
       delete [] var;                             \
     } while (0)
 
-#define DELETE3(var,s1,s2,s3)                    \
+#define DELETE3_COND(var,s1,s2,s3,cond)          \
   do                                             \
     {                                            \
@@ -97,5 +114,6 @@
           for (uint32_t it2=0; it2<s2; ++it2)    \
             {                                    \
-              delete [] var [it1][it2];          \
+              if (cond)                          \
+                delete [] var [it1][it2];        \
             }                                    \
           delete [] var [it1];                   \
@@ -104,5 +122,5 @@
     } while (0)
 
-#define DELETE4(var,s1,s2,s3,s4)                        \
+#define DELETE4_COND(var,s1,s2,s3,s4,cond)              \
   do                                                    \
     {                                                   \
@@ -113,5 +131,6 @@
               for (uint32_t it3=0; it3<s3; ++it3)       \
                 {                                       \
-                  delete [] var [it1][it2][it3];        \
+                  if (cond)                             \
+                    delete [] var [it1][it2][it3];      \
                 }                                       \
               delete [] var [it1][it2];                 \
@@ -121,4 +140,10 @@
       delete [] var;                                    \
     } while (0)
+
+#define DELETE0(var)             DELETE1_COND(var,true)
+#define DELETE1(var,s1)          DELETE1_COND(var,s1,true)
+#define DELETE2(var,s1,s2)       DELETE2_COND(var,s1,s2,true)
+#define DELETE3(var,s1,s2,s3)    DELETE3_COND(var,s1,s2,s3,true)
+#define DELETE4(var,s1,s2,s3,s4) DELETE4_COND(var,s1,s2,s3,s4,true)
 
 // ======================================================================
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Debug_component.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Debug_component.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Debug_component.h	(revision 145)
@@ -19,4 +19,5 @@
 #  define       DEBUG_Queue_Control                               true 
 #  define       DEBUG_RegisterFile                                true
+#  define         DEBUG_RegisterFile_Internal_Banked              true 
 #  define         DEBUG_RegisterFile_Monolithic                   true 
 #  define         DEBUG_RegisterFile_Multi_Banked                 true
@@ -119,4 +120,5 @@
 #  define NAME_Queue_Control                              "Queue_Control"
 #  define NAME_RegisterFile                               "RegisterFile"
+#  define NAME_RegisterFile_Internal_Banked               "RegisterFile_Internal_Banked"
 #  define NAME_RegisterFile_Monolithic                    "RegisterFile_Monolithic"
 #  define NAME_RegisterFile_Multi_Banked                  "RegisterFile_Multi_Banked"
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Function_pointer.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Function_pointer.h	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Function_pointer.h	(revision 145)
@@ -0,0 +1,37 @@
+#ifndef morpheo_behavioural_Function_pointer_h
+#define morpheo_behavioural_Function_pointer_h
+# if 0
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <list>
+#include "systemc.h"
+
+namespace morpheo     {
+namespace behavioural {
+  
+  typedef void(sc_process_host::*f_t)(void);
+
+  class Function_pointer
+  {
+  private : std::list<f_t> * _transition;
+  private : std::list<f_t> * _genMoore  ;
+
+  public  :       Function_pointer (void);
+  public  :      ~Function_pointer (void);
+  public  : void transition_add    (f_t f);
+  public  : void transition_exec   (void);
+  public  : void genMoore_add      (f_t f);
+  public  : void genMoore_exec     (void);
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+# endif
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h	(revision 145)
@@ -158,5 +158,5 @@
 
       if (test<T>(_size) == false)
-	throw (ErrorMorpheo (toString(_("Signal \"%s\" : size is too small (%d bits) to the associate type (%d bits).\n"),_name.c_str(),_size,8*sizeof(T))));
+        throw (ErrorMorpheo (toString(_("Signal \"%s\" : size is too small (%d bits) to the associate type (%d bits).\n"),_name.c_str(),_size,8*sizeof(T))));
 
       _is_allocate    = true;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info	(revision 145)
@@ -16,4 +16,5 @@
 # build src directory content
  target_dep		all		Generic/Queue/SelfTest
+ target_dep		all		Generic/RegisterFile/RegisterFile_Internal_Banked/SelfTest
  target_dep		all		Generic/RegisterFile/RegisterFile_Monolithic/SelfTest
  target_dep		all		Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Function_pointer.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Function_pointer.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Function_pointer.cpp	(revision 145)
@@ -0,0 +1,28 @@
+#if 0
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Function_pointer.h"
+
+namespace morpheo     {
+namespace behavioural {
+  
+  Function_pointer::Function_pointer (void)
+  {
+    _transition = new std::list<f_t>;
+    _genMoore   = new std::list<f_t>;
+  }
+  
+  Function_pointer::~Function_pointer (void)
+  {
+    delete _transition;
+    delete _genMoore  ;
+  }
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Function_pointer_add.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Function_pointer_add.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Function_pointer_add.cpp	(revision 145)
@@ -0,0 +1,26 @@
+#if 0
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Function_pointer.h"
+
+namespace morpheo     {
+namespace behavioural {
+  
+  void Function_pointer::transition_add (f_t f)
+  {
+    _transition->push_back(f);
+  }
+  
+  void Function_pointer::genMoore_add (f_t f)
+  {
+    _genMoore->push_back(f);
+  }
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Function_pointer_exec.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Function_pointer_exec.cpp	(revision 145)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Function_pointer_exec.cpp	(revision 145)
@@ -0,0 +1,32 @@
+#if 0
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Function_pointer.h"
+
+namespace morpheo     {
+namespace behavioural {
+  
+  void Function_pointer::transition_exec (void)
+  {
+    // for (std::list<f_t>::iterator it=_transition->begin();
+    //      it!=_transition->end();
+    //      ++it)
+    //   (*it)();
+  }
+  
+  void Function_pointer::genMoore_exec (void)
+  {
+    // for (std::list<f_t>::iterator it=_genMoore->begin();
+    //      it!=_genMoore->end();
+    //      ++it)
+    //   (*it)();
+  }
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_dealloc.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_dealloc.cpp	(revision 144)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_dealloc.cpp	(revision 145)
@@ -17,6 +17,6 @@
     log_printf(FUNC,Behavioural,FUNCTION,"Begin");
 
+#warning "FIXME : Signal::dealloc"
 
-#warning "FIXME : Signal::dealloc"
 
     // switch (_direction)
