Changeset 15 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src
- Timestamp:
- Apr 5, 2007, 4:17:30 PM (17 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src/main.cpp
r10 r15 6 6 */ 7 7 8 #include "Behavioural/Generic/RegisterFile _Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/include/test.h"8 #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/include/test.h" 9 9 10 10 #define NB_PARAMS 5 … … 14 14 cerr << "<Usage> " << argv[0] << " name_instance list_params" << endl 15 15 << "list_params is :" << endl 16 << " - nb_port_read (unsigned int)" << endl 17 << " - nb_port_write (unsigned int)" << endl 18 << " - size_address (unsigned int)" << endl 19 << " - size_word (unsigned int)" << endl 20 << " - nb_bank (unsigned int)" << endl 16 << " - nb_port_read (uint32_t )" << endl 17 << " - nb_port_write (uint32_t )" << endl 18 << " - size_address (uint32_t )" << endl 19 << " - size_word (uint32_t )" << endl 20 << " - nb_bank (uint32_t )" << endl 21 << " - nb_port_read_by_bank (uint32_t )" << endl 22 << " - nb_port_write_by_bank (uint32_t )" << endl 23 << " - crossbar (Tcrossbar_t)" << endl 21 24 << "" << endl; 22 25 … … 37 40 usage (argc, argv); 38 41 39 const string name = argv[1]; 40 const uint32_t nb_port_read = atoi(argv[2]); 41 const uint32_t nb_port_write = atoi(argv[3]); 42 const uint32_t size_address = atoi(argv[4]); 43 const uint32_t size_word = atoi(argv[5]); 44 const uint32_t nb_bank = atoi(argv[6]); 42 const string name = argv[1]; 43 const uint32_t nb_port_read = atoi(argv[2]); 44 const uint32_t nb_port_write = atoi(argv[3]); 45 const uint32_t size_address = atoi(argv[4]); 46 const uint32_t size_word = atoi(argv[5]); 47 const uint32_t nb_bank = atoi(argv[6]); 48 const uint32_t nb_port_read_by_bank = atoi(argv[7]); 49 const uint32_t nb_port_write_by_bank = atoi(argv[8]); 50 const Tcrossbar_t crossbar = fromString<Tcrossbar_t>(argv[9]); 45 51 46 52 try 47 53 { 48 morpheo::behavioural::generic::registerfile_multi_banked::registerfile_multi_banked_glue::Parameters param (nb_port_read , 49 nb_port_write, 50 size_address , 51 size_word , 52 nb_bank ); 53 54 morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::Parameters param (nb_port_read , 55 nb_port_write , 56 size_address , 57 size_word , 58 nb_bank , 59 nb_port_read_by_bank , 60 nb_port_write_by_bank, 61 crossbar ); 62 54 63 cout << param.print(1); 55 64 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src/test.cpp
r10 r15 7 7 */ 8 8 9 #define NB_ITERATION 1 10 11 #include "Behavioural/Generic/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/include/test.h" 9 #define NB_ITERATION 16 10 11 #define LABEL(str) do {cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; _RegisterFile_Multi_Banked_Glue->vhdl_testbench_label(str);} while (0) 12 13 #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/include/test.h" 12 14 #include "Include/Test.h" 15 #include "Include/BitManipulation.h" 13 16 14 17 void test (string name, 15 morpheo::behavioural::generic::registerfile _multi_banked::registerfile_multi_banked_glue::Parameters _param)18 morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::Parameters _param) 16 19 { 17 20 cout << "<" << name << "> : Simulation SystemC" << endl; … … 19 22 RegisterFile_Multi_Banked_Glue * _RegisterFile_Multi_Banked_Glue = new RegisterFile_Multi_Banked_Glue (name.c_str(), 20 23 #ifdef STATISTICS 21 24 morpheo::behavioural::Parameters_Statistics(5,50), 22 25 #endif 23 26 _param); 24 27 25 28 #ifdef SYSTEMC … … 33 36 sc_signal<Taddress_t> ** READ_IN_ADDRESS ; 34 37 sc_signal<Tdata_t > ** READ_IN_DATA ; 35 sc_signal<Tcontrol_t> 36 sc_signal<Tcontrol_t> 38 sc_signal<Tcontrol_t> **** READ_SELECT_VAL ; 39 sc_signal<Tcontrol_t> **** READ_SELECT_ACK ; 37 40 sc_signal<Tcontrol_t> *** READ_OUT_VAL ; 38 41 sc_signal<Tcontrol_t> *** READ_OUT_ACK ; … … 41 44 sc_signal<Tcontrol_t> ** WRITE_IN_VAL ; 42 45 sc_signal<Tcontrol_t> ** WRITE_IN_ACK ; 43 sc_signal<Tcontrol_t> ** WRITE_SELECT_VAL ;44 sc_signal<Tcontrol_t> ** WRITE_SELECT_ACK ;45 46 sc_signal<Taddress_t> ** WRITE_IN_ADDRESS ; 46 47 sc_signal<Tdata_t > ** WRITE_IN_DATA ; 48 sc_signal<Tcontrol_t> **** WRITE_SELECT_VAL ; 49 sc_signal<Tcontrol_t> **** WRITE_SELECT_ACK ; 47 50 sc_signal<Tcontrol_t> *** WRITE_OUT_VAL ; 48 51 sc_signal<Tcontrol_t> *** WRITE_OUT_ACK ; … … 58 61 READ_IN_ADDRESS = new sc_signal<Taddress_t> * [_param._nb_port_read]; 59 62 READ_IN_DATA = new sc_signal<Tdata_t > * [_param._nb_port_read]; 60 READ_SELECT_VAL = new sc_signal<Tcontrol_t> * [_param._nb_port_read];61 READ_SELECT_ACK = new sc_signal<Tcontrol_t> * [_param._nb_port_read];62 63 63 64 for (uint32_t i=0; i<_param._nb_port_read; i++) … … 71 72 rename = "READ_IN_DATA_"+toString(i)+" "; 72 73 READ_IN_DATA [i] = new sc_signal<Tdata_t > (rename.c_str()); 73 rename = "READ_SELECT_VAL_"+toString(i)+" "; 74 READ_SELECT_VAL [i] = new sc_signal<Tcontrol_t> (rename.c_str()); 75 rename = "READ_SELECT_ACK_"+toString(i)+" "; 76 READ_SELECT_ACK [i] = new sc_signal<Tcontrol_t> (rename.c_str()); 77 } 74 } 75 76 READ_SELECT_VAL = new sc_signal<Tcontrol_t> *** [_param._nb_bank]; 77 READ_SELECT_ACK = new sc_signal<Tcontrol_t> *** [_param._nb_bank]; 78 79 for (uint32_t i=0; i<_param._nb_bank; i++) 80 { 81 READ_SELECT_VAL [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_read_by_bank]; 82 READ_SELECT_ACK [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_read_by_bank]; 83 84 for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) 85 { 86 READ_SELECT_VAL [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_read_port [j]]; 87 READ_SELECT_ACK [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_read_port [j]]; 88 89 for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port [j]; k++) 90 { 91 rename="READ_SELECT_VAL_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" "; 92 READ_SELECT_VAL [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str()); 93 94 rename="READ_SELECT_ACK_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" "; 95 READ_SELECT_ACK [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str()); 96 } 97 } 98 } 78 99 79 100 READ_OUT_VAL = new sc_signal<Tcontrol_t> ** [_param._nb_bank]; … … 106 127 WRITE_IN_ADDRESS = new sc_signal<Taddress_t> * [_param._nb_port_write]; 107 128 WRITE_IN_DATA = new sc_signal<Tdata_t > * [_param._nb_port_write]; 108 WRITE_SELECT_VAL = new sc_signal<Tcontrol_t> * [_param._nb_port_write];109 WRITE_SELECT_ACK = new sc_signal<Tcontrol_t> * [_param._nb_port_write];110 111 129 for (uint32_t i=0; i<_param._nb_port_write; i++) 112 130 { … … 119 137 rename = "WRITE_IN_DATA_"+toString(i)+" "; 120 138 WRITE_IN_DATA [i] = new sc_signal<Tdata_t > (rename.c_str()); 121 122 rename = "WRITE_SELECT_VAL_"+toString(i)+" "; 123 WRITE_SELECT_VAL [i] = new sc_signal<Tcontrol_t> (rename.c_str()); 124 rename = "WRITE_SELECT_ACK_"+toString(i)+" "; 125 WRITE_SELECT_ACK [i] = new sc_signal<Tcontrol_t> (rename.c_str()); 126 } 139 } 140 141 WRITE_SELECT_VAL = new sc_signal<Tcontrol_t> *** [_param._nb_bank]; 142 WRITE_SELECT_ACK = new sc_signal<Tcontrol_t> *** [_param._nb_bank]; 143 144 for (uint32_t i=0; i<_param._nb_bank; i++) 145 { 146 WRITE_SELECT_VAL [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_write_by_bank]; 147 WRITE_SELECT_ACK [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_write_by_bank]; 148 149 for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) 150 { 151 WRITE_SELECT_VAL [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_write_port [j]]; 152 WRITE_SELECT_ACK [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_write_port [j]]; 153 154 for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port [j]; k++) 155 { 156 rename="WRITE_SELECT_VAL_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" "; 157 WRITE_SELECT_VAL [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str()); 158 159 rename="WRITE_SELECT_ACK_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" "; 160 WRITE_SELECT_ACK [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str()); 161 } 162 } 163 } 127 164 128 165 WRITE_OUT_VAL = new sc_signal<Tcontrol_t> ** [_param._nb_bank]; … … 165 202 (*(_RegisterFile_Multi_Banked_Glue-> in_READ_IN_ADDRESS [i])) (*(READ_IN_ADDRESS [i])); 166 203 (*(_RegisterFile_Multi_Banked_Glue->out_READ_IN_DATA [i])) (*(READ_IN_DATA [i])); 167 (*(_RegisterFile_Multi_Banked_Glue-> in_READ_SELECT_VAL [i])) (*(READ_SELECT_VAL [i])); 168 (*(_RegisterFile_Multi_Banked_Glue->out_READ_SELECT_ACK [i])) (*(READ_SELECT_ACK [i])); 169 } 204 } 205 206 for (uint32_t i=0; i<_param._nb_bank; i++) 207 for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) 208 for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++) 209 { 210 (*(_RegisterFile_Multi_Banked_Glue->out_READ_SELECT_VAL [i][j][k])) (*(READ_SELECT_VAL [i][j][k])); 211 (*(_RegisterFile_Multi_Banked_Glue-> in_READ_SELECT_ACK [i][j][k])) (*(READ_SELECT_ACK [i][j][k])); 212 } 213 170 214 for (uint32_t i=0; i<_param._nb_bank; i++) 171 215 for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) … … 183 227 (*(_RegisterFile_Multi_Banked_Glue-> in_WRITE_IN_ADDRESS [i])) (*(WRITE_IN_ADDRESS [i])); 184 228 (*(_RegisterFile_Multi_Banked_Glue-> in_WRITE_IN_DATA [i])) (*(WRITE_IN_DATA [i])); 185 (*(_RegisterFile_Multi_Banked_Glue-> in_WRITE_SELECT_VAL [i])) (*(WRITE_SELECT_VAL [i])); 186 (*(_RegisterFile_Multi_Banked_Glue->out_WRITE_SELECT_ACK [i])) (*(WRITE_SELECT_ACK [i])); 187 } 229 } 230 231 for (uint32_t i=0; i<_param._nb_bank; i++) 232 for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) 233 for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port[j]; k++) 234 { 235 (*(_RegisterFile_Multi_Banked_Glue->out_WRITE_SELECT_VAL [i][j][k])) (*(WRITE_SELECT_VAL [i][j][k])); 236 (*(_RegisterFile_Multi_Banked_Glue-> in_WRITE_SELECT_ACK [i][j][k])) (*(WRITE_SELECT_ACK [i][j][k])); 237 } 188 238 189 239 for (uint32_t i=0; i<_param._nb_bank; i++) … … 197 247 198 248 249 cout << "<" << name << "> Start Simulation ............" << endl; 250 199 251 /******************************************************** 200 252 * Simulation - Begin 201 253 ********************************************************/ 202 254 203 cout << "<" << name << "> Start Simulation ............" << endl;204 255 // Initialisation 205 256 … … 210 261 211 262 sc_start(0); 212 _RegisterFile_Multi_Banked_Glue->vhdl_testbench_label("Initialisation"); 213 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl; 214 215 216 _RegisterFile_Multi_Banked_Glue->vhdl_testbench_label("Loop of Test"); 217 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl; 263 264 LABEL("Initialisation"); 265 266 uint32_t read_in_num_bank [_param._nb_port_read]; // Number of bank 267 //Tcontrol_t read_in_valid [_param._nb_port_read]; 268 Tcontrol_t read_in_ack [_param._nb_port_read]; // to test 269 Tdata_t read_in_data [_param._nb_port_read]; // to test 270 Tcontrol_t read_out_val [_param._nb_bank][_param._nb_port_read_by_bank]; 271 Tcontrol_t read_out_ack [_param._nb_bank][_param._nb_port_read_by_bank]; 272 Taddress_t read_out_address [_param._nb_bank][_param._nb_port_read_by_bank]; 273 Tcontrol_t read_is_busy [_param._nb_port_read]; 274 Tcontrol_t read_select_val [_param._nb_bank][_param._nb_port_read ]; 275 Tcontrol_t read_select_ack [_param._nb_bank][_param._nb_port_read ]; 276 277 LABEL("Loop of Test"); 218 278 219 279 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 220 280 { 221 _RegisterFile_Multi_Banked_Glue->vhdl_testbench_label("Iteration "+toString(iteration)); 222 281 LABEL("Iteration "+toString(iteration)); 282 283 LABEL("Test read_in"); 284 285 // Write in interface "read_in" 286 for (uint32_t i=0; i<_param._nb_port_read; i++) 287 { 288 read_in_num_bank [i] = rand() % _param._nb_bank; 289 Tcontrol_t read_in_valid = (rand() % 2) != 0; 290 291 Taddress_t address = (read_in_num_bank[i] << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i); 292 293 read_is_busy [i] = (read_in_valid == 0); 294 read_in_ack [i] = 0; 295 read_in_data [i] = 0; 296 READ_IN_VAL [i]->write(read_in_valid); 297 READ_IN_ADDRESS [i]->write(address); 298 299 for (uint32_t j=0; j<_param._nb_bank; j++) 300 read_select_ack [j][i] = 0; 301 } 302 303 for (uint32_t i=0; i<_param._nb_bank; i++) 304 for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) 305 { 306 read_out_ack [i][j] = (rand() % 2) != 0; 307 READ_OUT_ACK [i][j]->write(read_out_ack [i][j]); 308 READ_OUT_DATA [i][j]->write((j<<1)|1); // (j<<1)|1 afin de n'avoir jamais 0 309 } 310 311 // compute the good read_select 312 for (uint32_t i=0; i<_param._nb_bank; i++) 313 for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) 314 { 315 bool find = false; // have find a port_in to link with this port_out 316 for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++) 317 { 318 319 uint32_t num_port; // number of port 320 321 // compute the good number of port 322 if (_param._crossbar == FULL_CROSSBAR) 323 num_port = k; 324 else 325 num_port = _param._link_port_read [i]; 326 327 read_select_val [i][num_port] = read_out_ack [i][j] && not read_is_busy [num_port]; 328 329 if ((read_out_ack [i][j] == 0) || find) 330 read_select_ack [i][num_port] = 0; // read_out is busy or already find 331 else 332 { 333 // find a busy port? 334 find = not read_is_busy [num_port]; 335 read_is_busy [num_port]|= find; 336 read_select_ack [i][num_port] = find; 337 338 if (find) 339 { 340 read_in_ack [num_port] = 1; 341 read_in_data [num_port] = ((j<<1)|1); 342 read_out_val [i][j] = 1; 343 read_out_address [i][j] = (read_in_num_bank[i] << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i); 344 } 345 } 346 347 READ_SELECT_ACK [i][j][k]->write(read_select_ack [i][num_port]); 348 } 349 } 350 351 // next cycle 223 352 sc_start(1); 353 354 // // lot of test 355 // public : SC_OUT(Tcontrol_t) ** out_READ_IN_ACK ; 356 // public : SC_OUT(Tdata_t ) ** out_READ_IN_DATA ; 357 358 // public : SC_OUT(Tcontrol_t) **** out_READ_SELECT_VAL ; 359 360 // public : SC_OUT(Tcontrol_t) *** out_READ_OUT_VAL ; 361 // public : SC_OUT(Taddress_t) *** out_READ_OUT_ADDRESS ; 362 224 363 } 225 364 … … 238 377 delete READ_IN_ADDRESS [i]; 239 378 delete READ_IN_DATA [i]; 240 delete READ_SELECT_VAL [i];241 delete READ_SELECT_ACK [i];242 379 } 243 380 … … 246 383 delete READ_IN_ADDRESS; 247 384 delete READ_IN_DATA ; 248 delete READ_SELECT_VAL; 249 delete READ_SELECT_ACK; 385 386 for (uint32_t i=0; i<_param._nb_bank; i++) 387 { 388 for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) 389 { 390 for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++) 391 { 392 delete READ_SELECT_VAL [i][j][k]; 393 delete READ_SELECT_ACK [i][j][k]; 394 } 395 delete READ_SELECT_VAL [i][j]; 396 delete READ_SELECT_ACK [i][j]; 397 } 398 delete READ_SELECT_VAL [i]; 399 delete READ_SELECT_ACK [i]; 400 } 401 delete READ_SELECT_VAL; 402 delete READ_SELECT_ACK; 250 403 251 404 for (uint32_t i=0; i<_param._nb_bank; i++) … … 276 429 delete WRITE_IN_ADDRESS [i]; 277 430 delete WRITE_IN_DATA [i]; 278 delete WRITE_SELECT_VAL [i];279 delete WRITE_SELECT_ACK [i];280 431 } 281 432 … … 284 435 delete WRITE_IN_ADDRESS; 285 436 delete WRITE_IN_DATA ; 437 438 for (uint32_t i=0; i<_param._nb_bank; i++) 439 { 440 for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) 441 { 442 for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port[j]; k++) 443 { 444 delete WRITE_SELECT_VAL [i][j][k]; 445 delete WRITE_SELECT_ACK [i][j][k]; 446 } 447 delete WRITE_SELECT_VAL [i][j]; 448 delete WRITE_SELECT_ACK [i][j]; 449 } 450 delete WRITE_SELECT_VAL [i]; 451 delete WRITE_SELECT_ACK [i]; 452 } 286 453 delete WRITE_SELECT_VAL; 287 454 delete WRITE_SELECT_ACK;
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