Changes in trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src/test.cpp [23:15]

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src/test.cpp (modified) (16 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src/test.cpp

@@ -9 +9 @@
 #define NB_ITERATION 16
 
-#define TEXT(str)  do {cout << "<" << name << "> : " << str << endl;} while (0)
 #define LABEL(str) do {cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; _RegisterFile_Multi_Banked_Glue->vhdl_testbench_label(str);} while (0)
 
@@ -19 +18 @@
            morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::Parameters _param)
 {
-  TEXT("Simulation SystemC");
+  cout << "<" << name << "> : Simulation SystemC" << endl;
 
   RegisterFile_Multi_Banked_Glue * _RegisterFile_Multi_Banked_Glue = new RegisterFile_Multi_Banked_Glue (name.c_str(),
@@ -193 +192 @@
    ********************************************************/
   
-   TEXT("Instanciation of _RegisterFile_Multi_Banked_Glue");
+  cout << "<" << name << "> Instanciation of _RegisterFile_Multi_Banked_Glue" << endl;
   
   (*(_RegisterFile_Multi_Banked_Glue->in_CLOCK))        (*(CLOCK));
@@ -248 +247 @@
 
 
-   TEXT("Start Simulation ............");
+  cout << "<" << name << "> Start Simulation ............" << endl;
   
   /********************************************************
@@ -266 +265 @@
 
   uint32_t   read_in_num_bank [_param._nb_port_read]; // Number of bank
-  Tcontrol_t read_is_busy     [_param._nb_port_read];
-  bool       read_out_find    [_param._nb_bank][_param._nb_port_read_by_bank];  
-  uint32_t   read_out_port    [_param._nb_bank][_param._nb_port_read_by_bank];  
-
+//Tcontrol_t read_in_valid    [_param._nb_port_read];
   Tcontrol_t read_in_ack      [_param._nb_port_read]; // to test
   Tdata_t    read_in_data     [_param._nb_port_read]; // to test
   Tcontrol_t read_out_val     [_param._nb_bank][_param._nb_port_read_by_bank];  
+  Tcontrol_t read_out_ack     [_param._nb_bank][_param._nb_port_read_by_bank];  
   Taddress_t read_out_address [_param._nb_bank][_param._nb_port_read_by_bank];  
-  Tcontrol_t read_select_val  [_param._nb_bank][_param._nb_port_read_by_bank][_param._nb_port_read];
+  Tcontrol_t read_is_busy     [_param._nb_port_read];
+  Tcontrol_t read_select_val  [_param._nb_bank][_param._nb_port_read        ];
+  Tcontrol_t read_select_ack  [_param._nb_bank][_param._nb_port_read        ];
 
   LABEL("Loop of Test");
@@ -282 +281 @@
       LABEL("Iteration "+toString(iteration));
       
-      //LABEL("Test read_in");
+      LABEL("Test read_in");
       
       // Write in interface "read_in"
@@ -288 +287 @@
         {
           read_in_num_bank  [i] =  rand() % _param._nb_bank;
-          Tcontrol_t read_in_val = (rand() % 2) != 0;
+          Tcontrol_t read_in_valid = (rand() % 2) != 0;
 
           Taddress_t address    = (read_in_num_bank[i] << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i);
 
-          read_is_busy      [i] = (read_in_val == 0);   // invalid = busy
-          read_in_ack       [i] = 0;                    // init
-          read_in_data      [i] = 0;                    // init
-          READ_IN_VAL       [i]->write(read_in_val);    // write signal
-          READ_IN_ADDRESS   [i]->write(address);        // write signal
+          read_is_busy      [i] = (read_in_valid == 0);
+          read_in_ack       [i] = 0;
+          read_in_data      [i] = 0;
+          READ_IN_VAL       [i]->write(read_in_valid);
+          READ_IN_ADDRESS   [i]->write(address);
+
+          for (uint32_t j=0; j<_param._nb_bank; j++)
+            read_select_ack [j][i] = 0;
         }
 
+      for (uint32_t i=0; i<_param._nb_bank; i++)
+        for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
+          {
+            read_out_ack      [i][j] = (rand() % 2) != 0;
+            READ_OUT_ACK      [i][j]->write(read_out_ack      [i][j]);
+            READ_OUT_DATA     [i][j]->write((j<<1)|1); // (j<<1)|1 afin de n'avoir jamais 0
+          }
+      
       // compute the good read_select
       for (uint32_t i=0; i<_param._nb_bank; i++)
         for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
           {
-            Tcontrol_t read_out_ack = (rand() % 2) != 0;
-            READ_OUT_ACK     [i][j]->write(read_out_ack);
-            READ_OUT_DATA    [i][j]->write((j<<1)|1);            // (j<<1)|1 afin de n'avoir jamais 0
-
-            read_out_find    [i][j] = false;
-            read_out_port    [i][j] = 0;
-
-            read_out_val     [i][j] = 0;
-            read_out_address [i][j] = 0;
-
             bool find = false; // have find a port_in to link with this port_out
             for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
               {
+
                 uint32_t num_port; // number of port
                 
@@ -322 +323 @@
                   num_port = k;
                 else
-                  num_port = k*_param._nb_port_read_by_bank+j;
-
-                read_select_val [i][j][k] = read_out_ack and not read_is_busy [num_port] and (read_in_num_bank[num_port] == i); // select val if port is not busy and out accept a data
-                Tcontrol_t read_select_ack = 0;
-
-                // test a previous find
-                if (not ((read_out_ack == 0) || find))
+                  num_port = _param._link_port_read [i];
+
+                read_select_val [i][num_port] = read_out_ack [i][j] && not read_is_busy [num_port];
+                
+                if ((read_out_ack [i][j] == 0) || find)
+                  read_select_ack [i][num_port] = 0; // read_out is busy or already find
+                else
                   {
                     // find a busy port?
-                    find                      = read_select_val;
-                    read_is_busy   [num_port]|= find; // port became busy if find
-                    read_select_ack           = find; // ack if find
+                    find = not read_is_busy [num_port];
+                    read_is_busy       [num_port]|= find;
+                    read_select_ack [i][num_port] = find;
 
                     if (find)
                       {
-                        read_out_find    [i][j] = true;
-                        read_out_port    [i][j] = num_port;
-
-                        // know the good output
                         read_in_ack      [num_port] = 1;
                         read_in_data     [num_port] = ((j<<1)|1);
                         read_out_val     [i][j]     = 1;
-                        read_out_address [i][j]     = (i << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & num_port);
+                        read_out_address [i][j]     = (read_in_num_bank[i] << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i);
                       }
                   }
                 
-                READ_SELECT_ACK [i][j][k]->write(read_select_ack);
+                READ_SELECT_ACK [i][j][k]->write(read_select_ack [i][num_port]);
               }
           }
@@ -355 +352 @@
       sc_start(1);
 
-      // test output
-
-      TEXT ("===== Test Output =====");
-      for (uint32_t i=0; i<_param._nb_port_read; i++)
-        {
-          TEXT ("Read_in         [" << i << "]       : "
-                << READ_IN_VAL [i]->read() << ","
-                << read_in_ack [i]         << " - "
-                << "Reg[" << READ_IN_ADDRESS [i]->read() << "] -> "
-                << read_in_data [i] << " "
-                << "{bank : " << read_in_num_bank[i] << "}"
-                );
-
-          TEST (Tcontrol_t, read_in_ack  [i], READ_IN_ACK  [i]->read());
-          if (READ_IN_VAL [i]->read() and READ_IN_ACK [i]->read())
-          TEST (Tdata_t   , read_in_data [i], READ_IN_DATA [i]->read());
-        }
-
-      cout << endl;
-      for (uint32_t i=0; i<_param._nb_bank; i++)
-        for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
-          {
-            TEXT ("Read_out        [" << i << "][" << j << "]    : "
-                  << read_out_val [i][j]         << ","
-                  << READ_OUT_ACK [i][j]->read() << " - "
-                  << "Reg[" << read_out_address [i][j] << "] -> "
-                  << READ_OUT_DATA [i][j]->read() << " - "
-                  << "[" << read_out_find [i][j]<< " , "
-                  << read_out_port    [i][j] << "]"               
-                  );
-
-            TEST (Tcontrol_t, read_out_val     [i][j], READ_OUT_VAL     [i][j]->read());
-            if (READ_OUT_VAL [i][j]->read() and READ_OUT_ACK [i][j]->read())
-            TEST (Taddress_t, read_out_address [i][j], READ_OUT_ADDRESS [i][j]->read());
-
-            for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
-              {
-                uint32_t num_port; // number of port
-                
-                // compute the good number of port
-                if (_param._crossbar == FULL_CROSSBAR)
-                  num_port = k;
-                else
-                  num_port = k*_param._nb_port_read_by_bank+j;
-                
-                TEXT (" * Read_select  [" << i << "][" << j << "][" << k << "] : "
-                      << read_select_val [i][j][k]         << ","
-                      << READ_SELECT_ACK [i][j][k]->read() << " - "
-                      << "link with read_in[" << num_port << "]"
-                      );
-                
-                TEST (Tcontrol_t, read_select_val  [i][j][k], READ_SELECT_VAL  [i][j][k]->read());
-              }
-            
-            
-            
-          }
-
-    }
-
-  sc_start(0);
+//       // lot of test
+//   public    : SC_OUT(Tcontrol_t)           ** out_READ_IN_ACK       ;
+//   public    : SC_OUT(Tdata_t   )           ** out_READ_IN_DATA      ;
+
+//   public    : SC_OUT(Tcontrol_t)         **** out_READ_SELECT_VAL   ;
+
+//   public    : SC_OUT(Tcontrol_t)          *** out_READ_OUT_VAL      ;
+//   public    : SC_OUT(Taddress_t)          *** out_READ_OUT_ADDRESS  ;
+
+    }
 
   /********************************************************
@@ -421 +367 @@
    ********************************************************/
 
-  TEXT("............ Stop Simulation");
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
 
   delete CLOCK;
 
-  TEXT("delete read_in");
   for (uint32_t i=0; i<_param._nb_port_read; i++)
     {
-//       TEXT("1, i " << i);
       delete READ_IN_VAL       [i];
-//       TEXT("2");
       delete READ_IN_ACK       [i];
-//       TEXT("3");
       delete READ_IN_ADDRESS   [i];
-//       TEXT("4");
       delete READ_IN_DATA      [i];
-//       TEXT("5");
     }
                                                       
@@ -444 +384 @@
   delete READ_IN_DATA   ;
 
-  TEXT("delete read_select");
    for (uint32_t i=0; i<_param._nb_bank; i++)
      {
@@ -463 +402 @@
    delete READ_SELECT_ACK;
 
-  TEXT("delete read_out");
    for (uint32_t i=0; i<_param._nb_bank; i++)
      {
@@ -485 +423 @@
   delete READ_OUT_DATA   ;
 
-  TEXT("delete write_in");
   for (uint32_t i=0; i<_param._nb_port_write; i++)
     {
@@ -499 +436 @@
   delete WRITE_IN_DATA   ;
 
-  TEXT("delete write_select");
   for (uint32_t i=0; i<_param._nb_bank; i++)
     {
@@ -518 +454 @@
   delete WRITE_SELECT_ACK;
   
-  TEXT("delete write_out");
   for (uint32_t i=0; i<_param._nb_bank; i++)
     {
@@ -542 +477 @@
 #endif
 
-
   delete _RegisterFile_Multi_Banked_Glue;
 }