Index: trunk/INSTALL =================================================================== --- trunk/INSTALL (revision 2) +++ trunk/INSTALL (revision 2) @@ -0,0 +1,39 @@ +-------------------------------------------------- + install.txt +-------------------------------------------------- + +Follow this step to install the Morpheo Tools Chain + +1) Install GNU-Toolchain + +cf Tools-source/or1k_toolchain-build-instructions.txt + +2) Install newlib + +Now you can compile a software and use the libc and libm + +3) Install a simulator + +3a) systemC +... + +3b) systemCASS + +4) Install soclib + +... + +5) Link + +This step consist at create all symbolik link + * Morpheo/Tools : + - newlib + - or1k + - soclib + - systemc (or systemcass) + * Morpheo/Software/*/src/sys/ + - crt0.s with $TOOLS/newlib/libgloss/or32/crt0.S + * Morpheo/IPs/systemC/shared/ + - mapping_memory.h + +6) Enjoy Index: trunk/IPs/systemC/hierarchy_memory/Makefile =================================================================== --- trunk/IPs/systemC/hierarchy_memory/Makefile (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/Makefile (revision 2) @@ -0,0 +1,32 @@ +RM = rm -f + +INCDIR = -I. -I.. \ + -I$(IPS) \ + -I$(TOOLS)/systemc/include \ + -I$(TOOLS)/soclib/include + +LIBDIR = -L. -L.. \ + -L$(TOOLS)/or1k/lib \ + -L$(TOOLS)/soclib/lib-$(TARGET_ARCH) \ + -L$(TOOLS)/systemc/lib-$(TARGET_ARCH) + +LIBS = -lm -lsystemc -lsoclib -lbfd -liberty -ldl + +#DEBUG = -DDEBUG + +CXX = g++ +CXX_OPT = -g3 -Wall $(INCDIR) $(LIBDIR) $(DEBUG) +CXXFILT = c++filt + +EXE = $(patsubst %.cpp,%.x ,$(wildcard *.cpp) ) +HEADERS = $(wildcard *.h) + +all : $(EXE) + ./$(EXE) + +%.x : %.cpp $(HEADERS) + $(CXX) $(CXX_OPT) -o $@ $< $(LIBS) 2>&1 | $(CXXFILT) +#(TOOLS)/soclib/lib/loadexec.o + +clean : + $(RM) $(EXE) *~ tty_* Index: trunk/IPs/systemC/hierarchy_memory/cache/Makefile =================================================================== --- trunk/IPs/systemC/hierarchy_memory/cache/Makefile (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/cache/Makefile (revision 2) @@ -0,0 +1,18 @@ +INCLUDE = -I../../../ +# DEBUG = -DDEBUG +DEBUG = +CXX = g++ +CXX_OPT = -g3 -Wall -Werror -ansi $(INCLUDE) $(DEBUG) +RM = rm -f + +EXE = $(patsubst %.cpp,%.x ,$(wildcard *.cpp) ) +HEADERS = $(wildcard *.h) + +all : $(EXE) + ./$(EXE) + +%.x : %.cpp $(HEADERS) + $(CXX) $(CXX_OPT) -o $@ $< + +clean : + $(RM) $(EXE) *~ Index: trunk/IPs/systemC/hierarchy_memory/cache/access_port.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/cache/access_port.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/cache/access_port.h (revision 2) @@ -0,0 +1,39 @@ +#ifndef ACCESS_PORT_H +#define ACCESS_PORT_H + +#include "address.h" +#include "type_rsp_cache.h" +#include +using namespace std; + +namespace hierarchy_memory { +namespace cache { +namespace cache_multilevel { +namespace cache_onelevel { + + class access_port_t + { + public : bool valid; + public : address_t address; + public : uint32_t trdid; + public : type_rsp_cache_t hit; + public : uint32_t num_associativity; // on hit : update lru + public : uint32_t latence; // on miss : wait + + friend ostream& operator<< (ostream& output_stream, const access_port_t &x) + { + output_stream << x.valid << " " + << x.hit << " " + << x.address << " " + << x.trdid << " " + << x.num_associativity << " " + << x.latence; + + return output_stream; + } + + }; + +};};};}; + +#endif //!ACCESS_PORT_H Index: trunk/IPs/systemC/hierarchy_memory/cache/address.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/cache/address.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/cache/address.h (revision 2) @@ -0,0 +1,33 @@ +#ifndef ADDRESS_H +#define ADDRESS_H + +#include +#include +using namespace std; + +namespace hierarchy_memory { + namespace cache { + namespace cache_multilevel { + namespace cache_onelevel { + + class address_t + { + public : uint32_t tag; + public : uint32_t familly; + public : uint32_t offset; + + friend ostream& operator<< (ostream& output_stream, const address_t &x) + { + output_stream << hex + << setw(8) << setfill('0') << x.tag << " " + << setw(8) << setfill('0') << x.familly << " " + << setw(8) << setfill('0') << x.offset + << dec; + + return output_stream; + } + }; + + };};};}; + +#endif //!ADDRESS_H Index: trunk/IPs/systemC/hierarchy_memory/cache/cache.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/cache/cache.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/cache/cache.h (revision 2) @@ -0,0 +1,239 @@ +#ifndef CACHE_H +#define CACHE_H + +#include +#include +#include +#include "cache_multilevel.h" +#include "cache_onelevel.h" +#include "type_req_cache.h" +#include "type_rsp_cache.h" + +using namespace std; +using namespace hierarchy_memory::cache::cache_multilevel; + + +namespace hierarchy_memory { + namespace cache { + typedef enum + { + INSTRUCTION_CACHE , + DATA_CACHE + } cache_t; + + class param_t + { + public : const char * name ; + public : uint32_t nb_entity ; + public : cache_multilevel::param_t * param_icache_dedicated; // 1 each entity + public : cache_multilevel::param_t * param_dcache_dedicated; // 1 each entity + public : cache_multilevel::param_t param_cache_shared ; // 1 to all entity and I/D is unify + + public : param_t () {}; + + public : param_t (const char * name , + uint32_t nb_entity , + cache_multilevel::param_t * param_icache_dedicated, + cache_multilevel::param_t * param_dcache_dedicated, + cache_multilevel::param_t param_cache_shared + ) : + name (name) + { + this->name = name ; + this->nb_entity = nb_entity ; + this->param_icache_dedicated = param_icache_dedicated ; + this->param_dcache_dedicated = param_dcache_dedicated ; + this->param_cache_shared = param_cache_shared ; + } + + friend ostream& operator<< (ostream& output_stream, const param_t & x) + { + output_stream << "<" << x.name << ">" << endl + << " * nb_entity : " << x.nb_entity << endl; + + for (uint32_t it = 0; it < x.nb_entity; it ++) + output_stream << x.param_icache_dedicated [it] << endl; + for (uint32_t it = 0; it < x.nb_entity; it ++) + output_stream << x.param_dcache_dedicated [it] << endl; + + output_stream << x.param_cache_shared << endl; + + return output_stream; + } + + };//end param_t + + + class Cache + { + private : char * name ; + protected: const uint32_t nb_entity ; + protected: uint32_t nb_iport ; + protected: uint32_t nb_dport ; + + protected: Cache_Multilevel ** icache_dedicated; + protected: Cache_Multilevel ** dcache_dedicated; + protected: Cache_Multilevel * cache_shared ; + + //*****[ constructor ]***** + public : Cache (param_t param): + nb_entity (param.nb_entity) + { + uint32_t size_name = strlen(param.name)+1; + name = new char [size_name]; + strncpy(name,param.name,size_name); + + cache_shared = new Cache_Multilevel (param.param_cache_shared); + icache_dedicated = new Cache_Multilevel * [nb_entity]; + dcache_dedicated = new Cache_Multilevel * [nb_entity]; + + nb_iport = 0; + nb_dport = 0; + for (uint32_t it = 0; it < nb_entity ; it++) + { + icache_dedicated [it] = new Cache_Multilevel (param.param_icache_dedicated[it]); + dcache_dedicated [it] = new Cache_Multilevel (param.param_dcache_dedicated[it]); + nb_iport += param.param_icache_dedicated[it].nb_port; + nb_dport += param.param_dcache_dedicated[it].nb_port; + } + + information(); + }; + + //*****[ destructor ]***** + public : ~Cache () + { + for (uint32_t it = 0; it < nb_entity ; it++) + { + delete icache_dedicated [it]; + delete dcache_dedicated [it]; + } + delete cache_shared ; + }; + + //*****[ reset ]***** + void reset () + { + cache_shared -> reset(); + // Reset buffer of respons + for (uint32_t it = 0; it < nb_entity; it++) + { + icache_dedicated [it] ->reset(); + dcache_dedicated [it] ->reset(); + } + }//end reset + + //*****[ transition ]***** + void transition() + { + cache_shared -> transition(); + // Transition buffer of respons + for (uint32_t it = 0; it < nb_entity; it++) + { + icache_dedicated [it] ->transition(); + dcache_dedicated [it] ->transition(); + } + }//end transition + + //*****[ range_port ]***** + public : uint32_t range_port (cache_t type_cache, + uint32_t num_entity) + { + uint32_t nb_port_dedicated = 0; + + if (type_cache == INSTRUCTION_CACHE) + for (uint32_t it = 1; it < num_entity; it++ ) + nb_port_dedicated += icache_dedicated [it]->nb_port; + else + { + nb_port_dedicated = nb_iport; + for (uint32_t it = 1; it < num_entity; it++) + nb_port_dedicated += dcache_dedicated [it]->nb_port; + } + return nb_port_dedicated; + } + + //*****[ latence ]***** + // Return the time to have the data + // latence is call on the same port in a single cycle, only the last access is save + // { NOTE } : type_cache = 0 : icache, 1 : dcache + public : uint32_t latence (cache_t type_cache, + uint32_t num_entity, + uint32_t num_port , + uint32_t address , + uint32_t trdid , + type_req_cache_t type , + direction_req_cache_t dir ) + { + if (num_entity >= nb_entity) + { + cerr << " {ERROR} num_entity ("<< num_entity << ") can be >= nb_entity (" << nb_entity << ")" << endl; + exit (1); + } + + Cache_Multilevel * cache; + if (type_cache == INSTRUCTION_CACHE) + cache = icache_dedicated [num_entity]; + else + cache = dcache_dedicated [num_entity]; + + if (num_port >= cache->nb_port) + { + cerr << " {ERROR} num_port ("<< num_port << ") can be >= nb_port (" << cache->nb_port << ")" << endl; + exit (1); + } + // Make a access with this level "dedicated" + + access_t access_dedicated = cache->access(num_port,address,trdid,type,dir); + + // cout << "access_dedicated : " << access_dedicated << endl; + + if (access_dedicated.hit == MISS) + { + // Make a access with this level "shared" + access_t access_shared = cache_shared->access(range_port (type_cache,num_entity)+num_port,address,trdid,type,dir); + // cout << "access_shared : " << access_shared << endl; + + cache_shared->update_access (access_shared); + + access_dedicated.last_nb_level = cache->nb_level; // Update all cache + access_dedicated.latence += access_shared.latence; + + // cout << "access_dedicated (after) : " << access_dedicated << endl; + } + + cache->update_access (access_dedicated); + return access_dedicated.latence; + } + + //*****[ information ]***** + public : void information (void) + { + cout << "<" << name << ">" << endl; + + for (uint32_t it = 0; it < nb_entity; it ++) + icache_dedicated [it]->information(); + for (uint32_t it = 0; it < nb_entity; it ++) + dcache_dedicated [it]->information(); + + cache_shared->information(); + } + + + friend ostream& operator<< (ostream& output_stream, const Cache & x) + { + output_stream << "<" << x.name << ">" << endl; + + for (uint32_t it = 0; it < x.nb_entity; it ++) + output_stream << *x.icache_dedicated [it] << endl; + for (uint32_t it = 0; it < x.nb_entity; it ++) + output_stream << *x.dcache_dedicated [it] << endl; + + output_stream << *x.cache_shared << endl; + + return output_stream; + } + + };//end Cache + };}; +#endif //!CACHE_H Index: trunk/IPs/systemC/hierarchy_memory/cache/cache_multilevel.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/cache/cache_multilevel.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/cache/cache_multilevel.h (revision 2) @@ -0,0 +1,186 @@ +#ifndef CACHE_MULTILEVEL_H +#define CACHE_MULTILEVEL_H + +#include +#include +#include +#include "cache_onelevel.h" +#include "type_req_cache.h" +#include "type_rsp_cache.h" + +using namespace std; +using namespace hierarchy_memory::cache::cache_multilevel::cache_onelevel; + +namespace hierarchy_memory { + namespace cache { + namespace cache_multilevel { + + class param_t + { + public : const char * name ; + public : uint32_t nb_level ; + public : uint32_t nb_port ; + public : param_cache_t * param_cache ; + + public : param_t () {}; + + public : param_t (const char * name , + uint32_t nb_level , + uint32_t nb_port , + param_cache_t * param_cache ) : + name (name) + { + //this->name = name ; + this->nb_level = nb_level ; + this->nb_port = nb_port ; + this->param_cache = param_cache ; + } + + friend ostream& operator<< (ostream& output_stream, const param_t & x) + { + output_stream << "<" << x.name << "> " + << x.nb_level << " " + << x.nb_port; + + for (uint32_t it = 0; it < x.nb_level; it ++) + output_stream << endl << x.param_cache [it]; + return output_stream; + } + + };//end param_t + + class access_t + { + public : uint32_t num_port ; + public : type_rsp_cache_t hit ; // result of access + public : uint32_t latence ; // Latence of access + public : uint32_t last_nb_level; // if access is not a hit : last level of cache before a error + + public : access_t (uint32_t num_port , + type_rsp_cache_t hit , + uint32_t latence , + uint32_t last_nb_level) + { + this->num_port = num_port ; + this->hit = hit ; + this->latence = latence ; + this->last_nb_level = last_nb_level; + } + + friend ostream& operator<< (ostream& output_stream, const access_t & x) + { + output_stream << "[" + << x.num_port << "] " + << x.hit << " " + << x.latence << " " + << x.last_nb_level; + return output_stream; + } + };//access_t + + class Cache_Multilevel + { + private : char * name; + protected : Cache_OneLevel ** hierarchy_cache; + public : const uint32_t nb_level; + public : const uint32_t nb_port ; + + //*****[ constructor ]***** + public : Cache_Multilevel (param_t param) : + nb_level (param.nb_level), + nb_port (param.nb_port ) + { + uint32_t size_name = strlen(param.name)+1; + name = new char [size_name]; + strncpy(name,param.name,size_name); + + hierarchy_cache = new Cache_OneLevel * [nb_level]; + + // Creation of Cache hierarchy + for (uint32_t it = 0; it < nb_level; it ++) + hierarchy_cache [it] = new Cache_OneLevel (cache_onelevel::param_t(param.nb_port , + param.param_cache [it])); + } + + //*****[ destructor ]***** + public : ~Cache_Multilevel () + { + for (uint32_t it = 0; it < nb_level; it ++) + delete hierarchy_cache [it]; + }; + //*****[ reset ]***** + public : void reset () + { + for (uint32_t it = 0; it < nb_level; it ++) + hierarchy_cache [it]->reset(); + } + + //*****[ transition ]***** + public : void transition () + { + for (uint32_t it = 0; it < nb_level; it ++) + hierarchy_cache [it]->transition(); + } + + //*****[ access ]***** + public : access_t access (uint32_t num_port, uint32_t address, uint32_t trdid, type_req_cache_t type, direction_req_cache_t dir) + { + uint32_t time = 0; + uint32_t last_nb_level = (nb_level==0)?0:(nb_level-1); + type_rsp_cache_t hit = MISS; + + for (uint32_t it_nb_level = 0; it_nb_level < nb_level; it_nb_level ++) + { + hit = hierarchy_cache[it_nb_level]->access(num_port,address,trdid,type,dir); + time += hierarchy_cache [it_nb_level]->latence (num_port); + + if ( (hit == HIT_CACHE) || + (hit == HIT_WRITE_BUFFER) || + (hit == HIT_BYPASS) ) + { + last_nb_level = it_nb_level; + break; + } + } + return access_t (num_port,hit,time,last_nb_level); + } + + //*****[ update_access ]***** + public : uint32_t update_access (access_t cur_access) + { + for (uint32_t it = 0; it < cur_access.last_nb_level; it ++) + hierarchy_cache [it]->update_latence (cur_access.num_port,cur_access.latence); + + return cur_access.latence; + } + + //*****[ latence ]***** + // Return the time to have the data + // latence is call on the same port in a single cycle, only the last access is save + public : uint32_t latence (uint32_t num_port, uint32_t address, uint32_t trdid, type_req_cache_t type, direction_req_cache_t dir) + { + return update_access (access (num_port, address, trdid, type, dir)); + } + + //*****[ information ]***** + public : void information (void) + { + cout << "<" << name << ">" << endl; + for (uint32_t it = 0; it < nb_level; it ++) + hierarchy_cache [it]->information(); + } + + friend ostream& operator<< (ostream& output_stream, const Cache_Multilevel & x) + { + output_stream << "<" << x.name << ">" << endl; + + for (uint32_t it = 0; it < x.nb_level; it ++) + output_stream << *x.hierarchy_cache [it] << endl; + + return output_stream; + } + }; + + };};}; +#endif //!CACHE_MULTILEVEL_H + Index: trunk/IPs/systemC/hierarchy_memory/cache/cache_onelevel.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/cache/cache_onelevel.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/cache/cache_onelevel.h (revision 2) @@ -0,0 +1,523 @@ +#ifndef CACHE_ONELEVEL_H +#define CACHE_ONELEVEL_H + +#include +#include +#include +#include +#include "../file/sort_file_dynamic.h" +#include "type_req_cache.h" +#include "tag.h" +#include "address.h" +#include "access_port.h" +#include "write_buffer.h" + +using namespace std; +using namespace hierarchy_memory::sort_file; +using namespace hierarchy_memory::cache::cache_multilevel; + +namespace hierarchy_memory { +namespace cache { +namespace cache_multilevel { +namespace cache_onelevel { + + class param_cache_t + { + public : const char * name ; + public : uint32_t nb_line ; + public : uint32_t size_line ; + public : uint32_t size_word ; + public : uint32_t associativity; + public : uint32_t hit_latence ; + public : uint32_t miss_penality; + + public : param_cache_t () {}; + + public : param_cache_t (const char * name , + uint32_t nb_line , + uint32_t size_line , + uint32_t size_word , + uint32_t associativity, + uint32_t hit_latence , + uint32_t miss_penality + ) : + name (name) + { + //this->name = name ; + this->nb_line = nb_line ; + this->size_line = size_line ; + this->size_word = size_word ; + this->associativity = associativity; + this->hit_latence = hit_latence ; + this->miss_penality = miss_penality; + } + + friend ostream& operator<< (ostream& output_stream, const param_cache_t & x) + { + output_stream << "<" << x.name << "> " + << x.nb_line << " " + << x.size_line << " " + << x.size_word << " " + << x.associativity << " " + << x.hit_latence << " " + << x.miss_penality; + + return output_stream; + } + };//end param_cache_t + + class param_t + { + public : uint32_t nb_port ; + public : param_cache_t param_cache; + + public : param_t (uint32_t nb_port , + param_cache_t param_cache) + { + this->nb_port = nb_port ; + this->param_cache = param_cache ; + } + + friend ostream& operator<< (ostream& output_stream, const param_t & x) + { + output_stream << x.nb_port << " " + << x.param_cache; + return output_stream; + } + + };//end param_t + + class Cache_OneLevel + { + protected : const uint32_t nb_port ; + protected : const uint32_t nb_line ; + protected : const uint32_t size_line ; + protected : const uint32_t size_word ; + protected : const uint32_t associativity ; + protected : const uint32_t hit_latence ; + protected : const uint32_t miss_penality ; + + private : char * name; + private : tag_t ** tag; + private : access_port_t * access_port; + private : address_t size_address; + private : Sort_File_Dynamic * write_buffer; + + //*****[ constructor ]***** + public : Cache_OneLevel (param_t param): + nb_port (param.nb_port ), + nb_line (param.param_cache.nb_line ), + size_line (param.param_cache.size_line ), + size_word (param.param_cache.size_word ), + associativity (param.param_cache.associativity), + hit_latence (param.param_cache.hit_latence ), + miss_penality (param.param_cache.miss_penality) + { + uint32_t size_name = strlen(param.param_cache.name)+1; + name = new char [size_name]; + strncpy(name,param.param_cache.name,size_name); + + if ((nb_line * size_line * associativity) == 0) + { + cerr << "<" << name << ".{Cache_OneLevel}> all parameter must be greater that 0" << endl; + cerr << " nb_line : " << nb_line << endl; + cerr << " size_line : " << size_line << endl; + cerr << " associativity : " << associativity << endl; + exit(1); + } + if ((nb_line % associativity) != 0) + { + cerr << "<" << name << ".{Cache_OneLevel}> nb_line must be a mutiple of associativity" << endl; + cerr << " * nb_line : " << nb_line << endl; + cerr << " * associativity : " << associativity << endl; + exit(1); + } + + if ((double)nb_line != ::pow(2,::log2(nb_line))) + { + cerr << "<" << name << ".{Cache_OneLevel}> nb_line must be a mutiple of 2^n" << endl; + cerr << " * nb_line : " << nb_line << endl; + exit(1); + } + + if ((double)size_line != ::pow(2,::log2(size_line))) + { + cerr << "<" << name << ".{Cache_OneLevel}> size_line must be a mutiple of 2^n" << endl; + cerr << " * size_line : " << size_line << endl; + exit(1); + } + + if ((double)size_word != ::pow(2,::log2(size_word))) + { + cerr << "<" << name << ".{Cache_OneLevel}> size_word must be a mutiple of 2^n" << endl; + cerr << " * size_word : " << size_word << endl; + exit(1); + } + + write_buffer= new Sort_File_Dynamic (sort_file::param_t("write_buffer",5)); + access_port = new access_port_t [nb_port]; + tag = new tag_t * [nb_line/associativity]; + for (uint32_t it = 0; it < nb_line/associativity; it ++) + tag [it] = new tag_t [associativity]; + + size_address.offset = (uint32_t) log2(size_line * size_word); + size_address.familly = (uint32_t) log2(nb_line/associativity); + size_address.tag = 32 - size_address.familly - size_address.offset; + } + + //*****[ destructor ]***** + public : ~Cache_OneLevel () + { +// delete tag; +// delete access_port; + }; + + //*****[ reset ]***** + public : void reset () + { + for (uint32_t x = 0; x < nb_port; x ++) + access_port[x].valid = false; + + for (uint32_t x = 0; x < nb_line/associativity; x ++) + for (uint32_t y = 0; y < associativity; y ++) + { + tag[x][y].valid = false; + tag[x][y].index_lru = y; + } + write_buffer->reset(); + } + + //*****[ transition ]***** + public : void transition () + { + // scan all port - test if have a transaction + for (int32_t x = nb_port-1; x >= 0; x --) + { + if (access_port[x].valid == true) + { + access_port[x].valid = false; + + // Update LRU + // * hit : now + // * miss : after the return of next cache + + if (access_port[x].hit == HIT_CACHE) + {// Hit + update_lru(access_port[x].address.familly,access_port[x].num_associativity); + } + + if (access_port[x].hit == MISS) + {// Miss + // Write in write_buffer + write_buffer->push(access_port[x].latence,write_buffer_t(access_port[x].address,access_port[x].trdid)); + } + } + } + + // Test if a write_buffer have the result + while ((write_buffer->empty() == false) && (write_buffer->read(0).delay == 0)) + { + // Save in the cache + write_buffer_t val = write_buffer->pop(); + + uint32_t num_tag = val.address.tag; + uint32_t num_familly = val.address.familly; + uint32_t num_associativity = index_victim(num_familly); + + tag [num_familly][num_associativity].valid = true; + tag [num_familly][num_associativity].address = num_tag; + tag [num_familly][num_associativity].trdid = val.trdid; + + update_lru(num_familly,num_associativity); + } + + write_buffer->transition(); + } + //*****[ update_lru ]***** + private : void update_lru (uint32_t familly, uint32_t num_associativity) + { + uint32_t current_lru = tag [familly][num_associativity].index_lru; + + for (uint32_t k = 0; k < associativity; k ++) + if (tag [familly][k].index_lru < current_lru) + tag [familly][k].index_lru ++; + tag [familly][num_associativity].index_lru = 0; + } + + //*****[ index_victim ]***** + // return the index of the nex victim + public : uint32_t index_victim (uint32_t familly) + { + uint32_t victim = 0; + while (tag [familly][victim].index_lru != (associativity-1)) + { + victim ++; + } + + return victim; + } + + //*****[ translate_address ]***** + private : address_t translate_address (uint32_t address) + { + address_t address_translated; + uint32_t shift; + + address_translated.offset = (address & ((uint32_t)-1 >> (32-(size_address.offset )))); + address -= address_translated.offset; + shift = size_address.offset; + address_translated.familly = (address & ((uint32_t)-1 >> (32-(size_address.familly + shift))))>>shift; + address -= address_translated.familly; + shift += size_address.familly; + address_translated.tag = (address & ((uint32_t)-1 >> (32-(size_address.tag + shift))))>>shift; + + return address_translated; + } + + //******************** + //******************** + + //*****[ access ]***** + // Return hit (true) + // uncache is to stocke the address on the cache + public : type_rsp_cache_t access (uint32_t nb_port, uint32_t address, uint32_t trdid, type_req_cache_t type, direction_req_cache_t dir) + { + switch (type) + { + case UNCACHED : return access_uncached (nb_port,address,trdid ); break; + case INVALIDATE : return access_invalidate (nb_port,address,trdid ); break; + case FLUSH : return access_flush (nb_port,address,trdid ); break; + case PREFETCH : // no difference with the simple read cached (have no add a prefetch cache) + case CACHED : return access_cached (nb_port,address,trdid,dir); break; + default : cout << " unkonow type : " << endl; exit(1); break; + } + } + + // *****[ access_cached ]***** + public : type_rsp_cache_t access_cached (uint32_t nb_port, uint32_t address, uint32_t trdid, direction_req_cache_t dir) + { + address_t address_translate = translate_address(address); + uint32_t num_associativity = hit_cache (trdid, address_translate); + uint32_t num_port = hit_access_port (trdid, address_translate); + uint32_t num_write_buffer = hit_write_buffer (trdid, address_translate); + + if (num_port == this->nb_port) + num_port = nb_port; + + uint32_t latence ; + type_rsp_cache_t res = MISS; + + bool is_in_cache = (num_associativity != associativity); + bool is_in_access_port = (num_port != nb_port); + bool is_in_write_buffer = false; + + if (is_in_access_port == true) + { + res = HIT_BYPASS; + latence = access_port[num_port].latence; //already compute + } + else + if (is_in_cache == true) + { + res = HIT_CACHE; + latence = 0; // Hit !!! + } + else + { + // Search in the write buffer, and test if have a miss + if ( num_write_buffer == write_buffer->nb_slot_use()) + { + res = MISS; + latence = miss_penality; // miss -> access at down of cache, + respons at the up of cache + } + else + { + res = HIT_WRITE_BUFFER; + is_in_write_buffer = true; + latence = write_buffer->read(num_write_buffer).delay; + } + } + + // access_port valid = there are a new request to update + // -> no previous request in the same cycle (hit in a access port) + // -> no previous request in the previous cycle (hit in the write buffer) + + access_port[nb_port].valid = ((is_in_access_port || is_in_write_buffer) == false); + access_port[nb_port].address = address_translate; + access_port[nb_port].trdid = trdid; + access_port[nb_port].hit = res; + access_port[nb_port].num_associativity = num_associativity; + access_port[nb_port].latence = latence; + + return res; + } + + // *****[ access_uncached ]***** + public : type_rsp_cache_t access_uncached (uint32_t nb_port, uint32_t address, uint32_t trdid) + { + access_port[nb_port].valid = false; + access_port[nb_port].trdid = trdid; + access_port[nb_port].hit = MISS; + access_port[nb_port].latence = miss_penality; + + return MISS; + } + // *****[ access_invalidate ]***** + public : type_rsp_cache_t access_invalidate (uint32_t nb_port, uint32_t address, uint32_t trdid) + { + cerr << "<" << name << ".{Cache_OneLevel}.access_invalidate> Not implemented" << endl; + exit (0); + return MISS; + } + + // *****[ access_flush ]***** + public : type_rsp_cache_t access_flush (uint32_t nb_port, uint32_t address, uint32_t trdid) + { + cerr << "<" << name << ".{Cache_OneLevel}.access_flush> Not implemented" << endl; + exit (0); + return MISS; + } + + //****************************** + //****************************** + + //*****[ hit_write_buffer ]***** + + // If a instruction is in the write_buffer, return the position + // else, return the number of elt in the write_buffer + public : uint32_t hit_write_buffer (uint32_t trdid, address_t address) + { + uint32_t num_write_buffer = 0; + // Scan the write_buffer + for (num_write_buffer = 0; num_write_buffer < write_buffer->nb_slot_use(); num_write_buffer ++) + { + slot_t val = write_buffer->read(num_write_buffer); + + if ( (val.data.trdid == trdid ) && + (val.data.address.tag == address.tag ) && + (val.data.address.familly == address.familly)) + break; + } + + return num_write_buffer; + } + + //*****[ hit_access_port ]***** + // return the number of associativity if hit + // return nb_accosiativity if miss + public : uint32_t hit_cache (uint32_t trdid, address_t address) + { + uint32_t num_associativity; + for (num_associativity = 0; num_associativity < associativity; num_associativity ++) + // Hit if : + // * in the line + // * in a way associative + // -> there are the same tag + // the same trdid + // is valid + if ( (tag [address.familly][num_associativity].address == address.tag) && + (tag [address.familly][num_associativity].valid == true ) && + (tag [address.familly][num_associativity].trdid == trdid ) ) + break; + + return num_associativity; + } + + //*****[ hit_access_port ]***** + // Return the number of port if hit + // Return nb_port if miss + public : uint32_t hit_access_port (uint32_t trdid, address_t address) + { + uint32_t it_num_port = 0; + + // scan all port - test if have a transaction + for (it_num_port = 0; it_num_port < nb_port; it_num_port ++) + if ( (access_port[it_num_port].valid == true ) && + (access_port[it_num_port].trdid == trdid ) && + (access_port[it_num_port].address.tag == address.tag ) && + (access_port[it_num_port].address.familly == address.familly)) + break; + + return it_num_port; + } + + //*****[ need_slot ]***** + public : uint32_t need_slot () + { + uint32_t res = 0; + // scan all port - test if have a transaction + for (uint32_t x = 0; x < nb_port; x ++) + if (access_port[x].valid == true) + res ++; + + return res; + } + + //*****[ latence ]***** + // Return the time to have the data + // uncache is to stocke the address on the cache + public : uint32_t latence (uint32_t num_port) + { + uint32_t res = hit_latence + access_port[num_port].latence; + + return res; + } + + //*****[ update_latence ]***** + // Return the time to have the data + // uncache is to stocke the address on the cache + public : bool update_latence (uint32_t nb_port, uint32_t latence) + { + access_port[nb_port].latence = latence-hit_latence; + return access_port[nb_port].valid; + } + + //*****[ information ]***** + public : void information (void) + { + cout << "<" << name << ">" << endl + << " * Information" << endl + << " * Capacity : " << nb_line * size_line * size_word << " bytes" << endl + << " * Nb line : " << nb_line << endl + << " * Size line : " << size_line << endl + << " * Size word : " << size_word << endl + << " * Associativity : " << associativity << endl + << " * Timing : " << endl + << " * Hit latence : " << hit_latence << endl + << " * Miss penality : " << miss_penality << endl + << " * Nb port : " << nb_port << endl + << endl; + } + + friend ostream& operator<< (ostream& output_stream, const Cache_OneLevel & x) + { + output_stream << "<" << x.name << ">" << endl + << " * Capacity : " << x.nb_line * x.size_line * x.size_word << " bytes" << endl + << " * Nb line : " << x.nb_line << endl + << " * Size line : " << x.size_line << endl + << " * Size word : " << x.size_word << endl + << " * Associativity : " << x.associativity << endl + << " * Timing : " << endl + << " * Hit latence : " << x.hit_latence << endl + << " * Miss penality : " << x.miss_penality << endl + << " * Nb port : " << x.nb_port << endl + << endl; + + output_stream << " * Tag" << endl; + for (uint32_t i = 0; i < x.nb_line / x.associativity; i ++) + { + for (uint32_t j = 0; j < x.associativity; j ++) + output_stream << x.tag [i][j] << " | "; + output_stream << endl; + } + + output_stream << endl; + output_stream << *x.write_buffer << endl; + + return output_stream; + } + + }; +};};};}; +#endif //!CACHE_ONELEVEL_H + Index: trunk/IPs/systemC/hierarchy_memory/cache/main.cpp =================================================================== --- trunk/IPs/systemC/hierarchy_memory/cache/main.cpp (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/cache/main.cpp (revision 2) @@ -0,0 +1,760 @@ +#include "cache.h" +#include "type_req_cache.h" +#include +using namespace hierarchy_memory; +using namespace hierarchy_memory::cache; +using namespace std; + +//-----[ Routine de test ]--------------------------------------- + +void test_ko (char * file, uint32_t line) +{ + cerr << "***** Test KO *****" << endl + << " - File : " << file << endl + << " - Line : " << line << endl; + exit (line); +}; + +void test_ok () +{ + cout << "***** Test OK *****" << endl; + exit (0); +}; + +template +void test(T exp1, T exp2, char * file, uint32_t line) +{ + if (exp1 != exp2) + { + cerr << "Expression is different : " << endl + << " - exp1 : " << exp1 << endl + << " - exp2 : " << exp2 << endl; + + test_ko (file,line); + } +}; + +#define TEST(type,exp1,exp2) do { test (exp1,exp2,__FILE__,__LINE__);} while(0) + +//-----[ main ]-------------------------------------------------- +int main () +{ + cout << "
Begin" << endl; + + // name , nb_line, size_line, size_word, associativity, hit_latence, miss_penality +#define L1a_CACHE "L1a_CACHE", 4, 2, 4, 4, 1, 5 +#define L1b_CACHE "L1b_CACHE", 4, 4, 4, 2, 2, 4 +#define L1c_CACHE "L1c_CACHE", 4, 2, 4, 1, 1, 6 +#define L1d_CACHE "L1d_CACHE", 4, 2, 4, 4, 2, 3 +#define L2_CACHE "L2_CACHE" , 8, 4, 4, 2, 2, 8 +#define L3_CACHE "L3_CACHE" , 16, 8, 4, 1, 3, 15 + + cout << " * 3 caches" << endl; + cout << " * L1 : 4 lines - 2 words - associtivity 4 ways" << endl; + cout << " * L2 : 8 lines - 4 words - associtivity 2 ways" << endl; + cout << " * L3 : 16 lines - 8 words - associtivity 1 ways" << endl; + + { + const uint32_t NB_CACHE = 2; + const uint32_t NB_PORT = 3; + + cout << "
Test de \"Cache_Multilevel\"" << endl; + + param_cache_t param_cache [NB_CACHE] = { param_cache_t (L1a_CACHE) , + param_cache_t (L2_CACHE) }; + Cache_Multilevel my_cache (cache_multilevel::param_t("my_cache_multilevel",NB_CACHE, NB_PORT, param_cache)); + + my_cache.reset(); + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 0] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl; + for (uint32_t i = 0; i < NB_PORT; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 1] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl; + + for (uint32_t i = 0; i < NB_PORT; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),15); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 2] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl; + + for (uint32_t i = 0; i < NB_PORT; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),14); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 3] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl; + + for (uint32_t i = 0; i < NB_PORT; i ++) + { + uint address = 0x200+i*4; + TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 4] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 5] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 6] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 7] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl; + + for (uint32_t i = 0; i < NB_PORT; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),9); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 8] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 9] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 10] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 11] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 12] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 13] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 14] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 15] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 16] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 17] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 18] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 19] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 20] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl; + + for (uint32_t i = 0; i < NB_PORT; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),1); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 21] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl; + + for (uint32_t i = 0; i < NB_PORT; i ++) + { + uint address = 0x200+i*4; + TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),1); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 22] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl; + + for (uint32_t i = 0; i < NB_PORT; i ++) + { + uint address = 0x300+i*4; + TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 23] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl; + + for (uint32_t i = 0; i < NB_PORT; i ++) + { + uint address = 0x400+i*4; + TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 24] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl; + + for (uint32_t i = 0; i < NB_PORT; i ++) + { + uint address = 0x500+i*4; + TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),(uint32_t)16); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [+40] **********" << endl; + cout << "**************************************" << endl; + for (uint32_t it = 24; it < 40; it ++) + { + cout << it << endl; + my_cache.transition(); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 40] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + cout << my_cache << endl; + + cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl; + + for (uint32_t i = 0; i < NB_PORT; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16); + } + + }//end test Cache_Multilevel + + cout << "-------------------------------------------------------------------------" << endl; + cout << "-------------------------------------------------------------------------" << endl; + cout << "-------------------------------------------------------------------------" << endl; + + { + const uint32_t nb_entity = 2; + const uint32_t nb_iport = 3; + const uint32_t nb_dport = 2; + + cout << "
Test de \"Cache\"" << endl; + + param_cache_t param_cache_1a [1] = { param_cache_t (L1a_CACHE) }; + param_cache_t param_cache_1b [1] = { param_cache_t (L1b_CACHE) }; + param_cache_t param_cache_1c [1] = { param_cache_t (L1c_CACHE) }; + param_cache_t param_cache_1d [1] = { param_cache_t (L1d_CACHE) }; + param_cache_t param_cache_2 [2] = { param_cache_t (L2_CACHE) , + param_cache_t (L3_CACHE) }; + + cache_multilevel::param_t param_icache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_icache_dedicated[0]",1,nb_iport,param_cache_1a), + cache_multilevel::param_t ("param_icache_dedicated[1]",1,nb_iport,param_cache_1b)}; + + cache_multilevel::param_t param_dcache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_dcache_dedicated[0]",1,nb_dport,param_cache_1c), + cache_multilevel::param_t ("param_dcache_dedicated[1]",1,nb_dport,param_cache_1d)}; + + cache_multilevel::param_t param_cache_shared ("param_cache_shared", 2, nb_entity*(nb_iport+nb_dport), param_cache_2); + + cache::param_t param_cache ("cache" , + nb_entity , + param_icache_dedicated , + param_dcache_dedicated , + param_cache_shared ); + + Cache my_cache (param_cache); + + ////cout << my_cache << endl; + my_cache.reset(); + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 0] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ),34); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 1] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + // cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x200+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ),34); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 2] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x300+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ),(uint32_t)34); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 3] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ),31); + } + + //cout << my_cache << endl; + + cout << "***** Read of " << nb_dport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_dport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (DATA_CACHE,1,i,address,0,CACHED,READ),30); // miss penality is 3 + } + + //cout << my_cache << endl; + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 4] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,1,CACHED,READ),(uint32_t)34); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [+34] **********" << endl; + cout << "**************************************" << endl; + for (uint32_t it = 0; it < 30; it ++) + { + cout << it << endl; + my_cache.transition(); + if (it == 0) + cout << my_cache << endl; + + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 34] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x200+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ), 2); + } + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_dport; i ++) + { + uint address = 0x200+i*4; + TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,0,CACHED,READ),20); // Miss L1-L2 Hit L3 + } + + + }//end test Cache + + cout << "-------------------------------------------------------------------------" << endl; + cout << "-------------------------------------------------------------------------" << endl; + cout << "-------------------------------------------------------------------------" << endl; + + + { + const uint32_t nb_entity = 1; + const uint32_t nb_iport = 3; + const uint32_t nb_dport = 2; + + cout << "
Test de \"Cache\"" << endl; + + param_cache_t param_cache_1a [1] = { param_cache_t (L1a_CACHE) }; + param_cache_t param_cache_1b [1] = { param_cache_t (L1b_CACHE) }; + + cache_multilevel::param_t param_icache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_icache_dedicated[0]",1,nb_iport,param_cache_1a)}; + + cache_multilevel::param_t param_dcache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_dcache_dedicated[0]",1,nb_dport,param_cache_1b)}; + + cache_multilevel::param_t param_cache_shared ("param_cache_shared",0, 0, NULL); + + cache::param_t param_cache ("cache" , + nb_entity , + param_icache_dedicated , + param_dcache_dedicated , + param_cache_shared ); + + Cache my_cache (param_cache); + + cout << my_cache << endl; + + my_cache.reset(); + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 0] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)6); + } + + cout << "***** Read of " << nb_dport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_dport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)6); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 1] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)5); + } + + + } + + { + const uint32_t nb_entity = 1; + const uint32_t nb_iport = 3; + const uint32_t nb_dport = 2; + + cout << "
Test de \"Cache\"" << endl; + + param_cache_t param_cache_2 [1] = { param_cache_t (L2_CACHE)}; + + cache_multilevel::param_t param_icache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_icache_dedicated[0]",0,nb_iport,NULL)}; + + cache_multilevel::param_t param_dcache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_dcache_dedicated[0]",0,nb_dport,NULL)}; + + cache_multilevel::param_t param_cache_shared ("param_cache_shared",1, nb_entity * (nb_iport + nb_dport), param_cache_2); + + cache::param_t param_cache ("cache" , + nb_entity , + param_icache_dedicated , + param_dcache_dedicated , + param_cache_shared ); + + Cache my_cache (param_cache); + + cout << my_cache << endl; + + my_cache.reset(); + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 0] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)10); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 1] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)9); + } + + cout << "***** Read of " << nb_dport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_dport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)9); + } + + + } + + cout << "-------------------------------------------------------------------------" << endl; + cout << "-------------------------------------------------------------------------" << endl; + cout << "-------------------------------------------------------------------------" << endl; + + { + const uint32_t nb_entity = 1; + const uint32_t nb_iport = 3; + const uint32_t nb_dport = 2; + + cout << "
Test des Types et direction" << endl; + + param_cache_t param_cache_1a [1] = { param_cache_t (L1a_CACHE) }; + param_cache_t param_cache_1b [1] = { param_cache_t (L1b_CACHE) }; + param_cache_t param_cache_2 [1] = { param_cache_t (L2_CACHE) }; + + cache_multilevel::param_t param_icache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_icache_dedicated[0]",1,nb_iport,param_cache_1a)}; + cache_multilevel::param_t param_dcache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_dcache_dedicated[0]",1,nb_dport,param_cache_1b)}; + cache_multilevel::param_t param_cache_shared ("param_cache_shared",1, nb_entity*(nb_iport+nb_dport), param_cache_2); + + cache::param_t param_cache ("cache" , + nb_entity , + param_icache_dedicated , + param_dcache_dedicated , + param_cache_shared ); + + Cache my_cache (param_cache); + + // cout << my_cache << endl; + my_cache.reset(); + + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 0] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + //cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)16); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [+ 9] **********" << endl; + cout << "**************************************" << endl; + for (uint32_t it = 1; it < 9; it ++) + { + cout << it << endl; + my_cache.transition(); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 9] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); + cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x200+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)16); + } + + cout << "***** Read of " << nb_dport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_dport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)8); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 5] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); +// cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)6); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 6] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); +// cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,UNCACHED,READ),(uint32_t)16); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 7] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); +// cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)4); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [+18] **********" << endl; + cout << "**************************************" << endl; + for (uint32_t it = 8; it < 18; it ++) + { + cout << it << endl; + my_cache.transition(); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 18] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); +// cout << my_cache << endl; + + cout << "***** Read of " << nb_iport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_iport; i ++) + { + uint address = 0x100+i*4; + TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)1); + } + + cout << "***** Read of " << nb_dport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_dport; i ++) + { + uint address = 0x200+i*4; + TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)8); + } + + cout << "**************************************" << endl; + cout << "********** TRANSITION [ 19] **********" << endl; + cout << "**************************************" << endl; + my_cache.transition(); +// cout << my_cache << endl; + + cout << "***** Read of " << nb_dport << " consecutive address *****" << endl; + for (uint32_t i = 0; i < nb_dport; i ++) + { + uint address = 0x200+i; + TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)7); + } + + } + + test_ok (); +}//end main Index: trunk/IPs/systemC/hierarchy_memory/cache/tag.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/cache/tag.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/cache/tag.h (revision 2) @@ -0,0 +1,33 @@ +#ifndef TAG_H +#define TAG_H + +#include +using namespace std; + +namespace hierarchy_memory { +namespace cache { +namespace cache_multilevel { +namespace cache_onelevel { + +class tag_t +{ +public : bool valid ; +public : uint32_t address ; +public : uint32_t trdid ; +public : uint32_t index_lru; + + friend ostream& operator<< (ostream& output_stream, const tag_t &x) + { + output_stream << x.valid << " " + << hex << setw(8) << setfill('0') << x.address << " " << dec + << x.trdid << " " + << x.index_lru; + + return output_stream; + } + +}; + +};};};}; + +#endif //!TAG_H Index: trunk/IPs/systemC/hierarchy_memory/cache/type_req_cache.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/cache/type_req_cache.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/cache/type_req_cache.h (revision 2) @@ -0,0 +1,24 @@ +#ifndef TYPE_REQ_CACHE_H +#define TYPE_REQ_CACHE_H + +namespace hierarchy_memory +{ +typedef enum + { + READ , + WRITE , + NONE + } direction_req_cache_t; + +typedef enum + { + CACHED , // address can be in the cache + UNCACHED , // Always miss (not address in cache) + INVALIDATE , // The direction is not used + PREFETCH , // The direction is not used + FLUSH // The direction is not used + } type_req_cache_t; +}; + +#endif //!TYPE_REQ_CACHE_H + Index: trunk/IPs/systemC/hierarchy_memory/cache/type_rsp_cache.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/cache/type_rsp_cache.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/cache/type_rsp_cache.h (revision 2) @@ -0,0 +1,17 @@ +#ifndef TYPE_RSP_CACHE_H +#define TYPE_RSP_CACHE_H + +namespace hierarchy_memory +{ + typedef enum + { + HIT_CACHE , + HIT_BYPASS , + HIT_WRITE_BUFFER , + MISS + } type_rsp_cache_t; +}; + + +#endif //!TYPE_RSP_CACHE_H + Index: trunk/IPs/systemC/hierarchy_memory/cache/write_buffer.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/cache/write_buffer.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/cache/write_buffer.h (revision 2) @@ -0,0 +1,40 @@ +#ifndef WRITE_BUFFER_H +#define WRITE_BUFFER_H + +#include "address.h" +#include +using namespace std; + +namespace hierarchy_memory { +namespace cache { +namespace cache_multilevel { +namespace cache_onelevel { + + class write_buffer_t + { + public : address_t address; + public : uint32_t trdid; + + public : write_buffer_t () + { + } + + public : write_buffer_t (address_t address, uint32_t trdid) + { + this->address = address; + this->trdid = trdid; + } + + friend ostream& operator<< (ostream& output_stream, const write_buffer_t &x) + { + output_stream << x.address << " " + << x.trdid; + + return output_stream; + } + + }; + +};};};}; + +#endif //!WRITE_BUFFER_H Index: trunk/IPs/systemC/hierarchy_memory/data/Makefile =================================================================== --- trunk/IPs/systemC/hierarchy_memory/data/Makefile (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/data/Makefile (revision 2) @@ -0,0 +1,27 @@ +RM = rm -f + +INCDIR = -I../../ \ + -I$(TOOLS)/soclib/include + +LIBDIR = -L$(TOOLS)/soclib/lib-$(TARGET_ARCH) \ + -L$(TOOLS)/or1k/lib/ + +LIB = -lsoclib -lbfd -liberty + +CXX = g++ +CXX_OPT = -g3 -Wall -Werror -ansi $(INCDIR) +LXX_OPT = $(LIBDIR) $(LIB) + +EXE = $(patsubst %.cpp,%.x ,$(wildcard *.cpp) ) +HEADERS = $(wildcard *.h) + +all : $(EXE) + ./$(EXE) + +%.x : %.cpp $(HEADERS) + $(CXX) $(CXX_OPT) -o $@ $< $(LXX_OPT) +# $(CXX) $(CXX_OPT) -c -o $@.o $< +# $(CXX) -o $@ $@.o $(LXX_OPT) + +clean : + $(RM) $(EXE) *~ *.o Index: trunk/IPs/systemC/hierarchy_memory/data/data.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/data/data.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/data/data.h (revision 2) @@ -0,0 +1,173 @@ +#ifndef DATA_H +#define DATA_H + +#include +#include +#include "segment.h" +#include "shared/soclib_segment_table.h" + +using namespace std; + +namespace hierarchy_memory { +namespace data { + + class entity_t + { + public : bool present; + public : segment_t * segment; + + public : entity_t (bool present) + { + this->present = present; + } + + public : entity_t (bool present , + segment_t * segment ) + { + this->present = present; + this->segment = segment; + } + + friend ostream& operator<< (ostream& output_stream, const entity_t & x) + { + output_stream << x.present; + if (x.present == true) + output_stream << " " << *x.segment; + + return output_stream; + } + }; //end entity_t + + class param_t + { + public : char * name ; + public : uint32_t max_seg ; + public : unsigned int globalIndex; + public : unsigned int localIndex ; + public : SOCLIB_SEGMENT_TABLE * segtab ; + + public : param_t (char * name , + uint32_t max_seg , + unsigned int globalIndex, + unsigned int localIndex , + SOCLIB_SEGMENT_TABLE * segtab ) + { + this->name = name ; + this->max_seg = max_seg ; + this->globalIndex = globalIndex; + this->localIndex = localIndex ; + this->segtab = segtab ; + } + }; //end param_t + + class Data + { + private : char * name; + protected : const uint32_t max_seg; + protected : uint32_t nb_seg; + protected : segment_t ** segment; + + public : Data (param_t param) : + max_seg (param.max_seg) + { + uint32_t size_name = strlen(param.name)+1; + name = new char [size_name]; + strncpy(name,param.name,size_name); + + std::list seglist = param.segtab->getSegmentList(param.globalIndex,param.localIndex); + std::list::iterator iter; + nb_seg = 0; + + segment = new segment_t * [max_seg]; + + for (iter = seglist.begin() ; iter != seglist.end() ; ++iter , nb_seg ++) + { + SEGMENT_TABLE_ENTRY entry = *iter; + if (nb_seg >= max_seg) + { + cerr << "The number of seg can't be higher that " << max_seg << endl; + exit (1); + } + segment [nb_seg] = new segment_t (entry); + + param.segtab->setAddrAlloc(entry.getBase(),(void *)(segment [nb_seg]->data_addr())); + } + } + + //*****[ init ]***** + public : bool init (char * section, const char * filename, const char ** list_section) + { + for (uint32_t it = 0; it < nb_seg; it ++) + if (segment[it]->test(section) == true) + return segment[it]->init(filename,list_section); + + return false; + } + + //*****[ read ]***** + // Read a lot of byte + public : bool read (uint32_t address, uint32_t size, char * & data_dest) + { + uint32_t num_seg = 0; + bool res = false; + for (num_seg = 0; num_seg < nb_seg; num_seg ++) + if (segment[num_seg]->test (address,size) == true) + { + segment[num_seg]->read (address,size,data_dest); + res = true; + break; + } + + return res; + } + + //*****[ entity ]***** + public : entity_t entity (uint32_t address, uint32_t size) + { + for (uint32_t num_seg = 0; num_seg < nb_seg; num_seg ++) + if (segment[num_seg]->test (address,size) == true) + return entity_t (true,segment[num_seg]); + + return entity_t (false); + } + + public : entity_t entity (char * name) + { + for (uint32_t num_seg = 0; num_seg < nb_seg; num_seg ++) + if (segment[num_seg]->test(name) == true) + return entity_t (true,segment[num_seg]); + + return entity_t (false); + } + + //*****[ write ]***** + // Write a lot of byte + public : bool write (uint32_t address, uint32_t size, char * & data_src) + { + uint32_t num_seg = 0; + bool res = false; + for (num_seg = 0; num_seg < nb_seg; num_seg ++) + if (segment[num_seg]->test (address,size) == true) + { + segment[num_seg]->write (address,size,data_src); + res = true; + break; + } + + return res; + } + + public : friend ostream& operator<< (ostream& output_stream, const Data & x) + { + output_stream << "<" << x.name << ">" << endl + << " * nb_seg : " << x.nb_seg << endl + << " * max_seg : " << x.max_seg << endl; + + for (uint32_t it = 0; it < x.nb_seg; it ++) + output_stream << *x.segment[it] << endl; + return output_stream; + }; + }; + +};}; //end namespace +#endif //!DATA_H Index: trunk/IPs/systemC/hierarchy_memory/data/main.cpp =================================================================== --- trunk/IPs/systemC/hierarchy_memory/data/main.cpp (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/data/main.cpp (revision 2) @@ -0,0 +1,163 @@ +#include "data.h" +#include + +#define TEXT_BASE 0x00000000 +#define TEXT_SIZE 0x00005000 + +#define DATA_CACHED_BASE 0x10000000 +#define DATA_CACHED_SIZE 0x00000100 + +#define DATA_UNCACHED_BASE 0x40000000 +#define DATA_UNCACHED_SIZE 0x00000100 + +#define STACK_BASE 0x50000000 +#define STACK_SIZE 0x00000200 + +#define TTY_BASE 0x60000000 +#define TTY_SIZE 0x00000100 + +#define SIM2OS_BASE 0x70000000 +#define SIM2OS_SIZE 0x00000100 + +#define RAMLOCK_BASE 0x80000000 +#define RAMLOCK_SIZE 0x00000100 + +using namespace hierarchy_memory::data; +using namespace std; + +void test_ko (int val) +{ + cout << "***** Test(" << val << ") KO *****" << endl; + exit (val); +} + +void test_ok () +{ + cout << "***** Test OK *****" << endl; + exit (0); +} + +static uint32_t num_test = 1; + +template +void test(T exp1, T exp2) +{ + if (exp1 != exp2) + test_ko (num_test); + num_test ++; +} + +int main () +{ + cout << "
Test de \"Data\"" << endl; + + cout << " * Create a Data" << endl; + + SOCLIB_SEGMENT_TABLE segtable; + segtable.setMSBNumber (8); + segtable.setDefaultTarget(0,0); + + //shared data segment + + + + // Add a segment :name , address of base , size , global index , local index, uncache + segtable.addSegment("text" , TEXT_BASE , TEXT_SIZE , 0 ,0 , false); + segtable.addSegment("data" , DATA_CACHED_BASE , DATA_CACHED_SIZE , 0 ,0 , false); + segtable.addSegment("data_unc" , DATA_UNCACHED_BASE , DATA_UNCACHED_SIZE , 0 ,0 , true ); + segtable.addSegment("stack" , STACK_BASE , STACK_SIZE , 0 ,0 , false); + segtable.addSegment("tty" , TTY_BASE , TTY_SIZE , 0 ,0 , true ); + segtable.addSegment("sim2os" , SIM2OS_BASE , SIM2OS_SIZE , 0 ,0 , true ); + segtable.addSegment("ramlock" , RAMLOCK_BASE , RAMLOCK_SIZE , 0 ,0 , true ); + + Data my_data = Data(param_t("my_data",16,0,0,&segtable)); + + const char * sections_text [] = {".text",NULL}; + const char * sections_data [] = {".data",".rodata",".sdata",".sbss",".bss", NULL}; + const char * sections_stack [] = {".stack",NULL}; + const char * filename = "soft.x"; + + test (my_data.init("text" , filename, sections_text) ,true); + test (my_data.init("stack" , filename, sections_stack),true); + test (my_data.init("data" , filename, sections_data) ,true); + + segtable.print(); + + cout << my_data << endl; + + uint32_t size, offset; + char * data = new char [100]; + + // ************************************************************* + offset = 0; + size = 32; + + cout << " * Read of bytes [" << DATA_CACHED_BASE+offset << ":" << DATA_CACHED_BASE+offset+size << "[" << endl; + + test (my_data.read(DATA_CACHED_BASE+offset,size,data), true); + + for (uint32_t it = 0; it < size; it ++) + { + if (it % 4 == 0) + printf("\n"); + + printf("%.2x",(unsigned char)(data[it])); + } + printf("\n"); + + // ************************************************************* + offset = 8; + size = 16; + char * data_src = new char [100]; + sprintf(data_src,"123456780abcdef0"); + + cout << " * Write of bytes [" << DATA_CACHED_BASE+offset << ":" << DATA_CACHED_BASE+offset+size << "[" << endl; + + test (my_data.write(DATA_CACHED_BASE+offset,size,data_src), true); + + for (uint32_t it = 0; it < size; it ++) + { + if (it % 4 == 0) + printf("\n"); + + printf("%.2x",(unsigned char)(data_src[it])); + } + printf("\n"); + + // ************************************************************* + offset = 0; + size = 32; + cout << " * Read of bytes [" << DATA_CACHED_BASE+offset << ":" << DATA_CACHED_BASE+offset+size << "[" << endl; + + test (my_data.read(DATA_CACHED_BASE+offset,size,data), true); + + for (uint32_t it = 0; it < size; it ++) + { + if (it % 4 == 0) + printf("\n"); + + printf("%.2x",(unsigned char)(data[it])); + } + printf("\n"); + + // ************************************************************* + + cout << " * Recherche of address" << endl; + test (my_data.entity(0x00000034, 2).present,true ); + test (my_data.entity(0x00005000, 1).present,false); + test (my_data.entity(0x00004FFD, 2).present,true ); + test (my_data.entity(0x00004FFD, 4).present,false); + test (my_data.entity(0x10000000, 1).present,true ); + test (my_data.entity(0x0FFFFFFF,10).present,false); + + cout << " * Typage" << endl; + cout << my_data.entity(TTY_BASE,TTY_SIZE) << endl; + my_data.entity(TTY_BASE,TTY_SIZE).segment->define_target (TYPE_TTY,0); + cout << my_data.entity(TTY_BASE,TTY_SIZE) << endl; + + cout << my_data.entity("ramlock") << endl; + my_data.entity("ramlock").segment->define_target (TYPE_RAMLOCK,0); + cout << my_data.entity("ramlock") << endl; + + test_ok (); +} Index: trunk/IPs/systemC/hierarchy_memory/data/segment.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/data/segment.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/data/segment.h (revision 2) @@ -0,0 +1,165 @@ +#ifndef SEGMENT_H +#define SEGMENT_H + +#include +#include +#include +#include "type_target.h" +#include "shared/soclib_segment_table.h" + +using namespace std; + +extern "C" void loadexec(void **emem, int *esize, int *eoffset, const char *file, const char ** sections); + + +namespace hierarchy_memory { +namespace data { + + class segment_t + { + protected : uint32_t base; + protected : uint32_t size; + protected : bool uncached; + protected : char * name; + protected : char * data; + protected : type_target_t type; + protected : uint32_t index; + + public : segment_t () + { + base = 0; + size = 0; + uncached = false; + name = NULL; + data = NULL; + type = TYPE_MEMORY; + index = 0; + } + + public : segment_t (SEGMENT_TABLE_ENTRY segment) + { + uint32_t size_name = strlen (segment.getName())+1; + + base = segment.getBase(); + size = segment.getSize(); + uncached = segment.getUncached(); + name = new char [size_name]; + name = strncpy (name, segment.getName(),size_name); + data = new char [size]; + type = TYPE_MEMORY; + index = 0; + }; + + //*****[ init ]***** + public : bool init (const char * filename,const char ** sections) + { + void * ptab; + int size = this->size; + int offset = 0; + + loadexec(&ptab,&size,&offset,filename,sections); + + cout << " - size : " << size << endl; + cout << " - offset : " << offset << endl; + + if (size > (int)this->size) + { + cerr << " : segment " << name << " is to small : size is " << this->size << " and requiert is " << size << endl; + return false; + } + + memcpy(data, ptab, size); + + free (ptab); + + return true; + } + + //*****[ define_target ]***** + public : void define_target (type_target_t type, uint32_t index) + { + this->type = type; + this->index = index; + } + + //*****[ getType ]***** + public : type_target_t getType () + { + return type; + } + + //*****[ getIndex ]***** + public : uint32_t getIndex () + { + return index; + } + + //*****[ getBase ]***** + public : uint32_t getBase () + { + return base; + } + + //*****[ getSize ]***** + public : uint32_t getSize () + { + return size; + } + + //*****[ getUncached ]***** + public : uint32_t getUncached () + { + return uncached; + } + + //*****[ data_addr ]***** + // Return the data address + public : char * data_addr () + { + return data; + } + + //*****[ test ]***** + public : bool test (char * name) + { + return (strcmp(this->name,name) == 0); + } + + public : bool test (uint32_t address, uint32_t size) + { + bool res = (((address ) >= this->base ) && + ((address+size) <= (this->base+this->size))); + + return res; + } + + //*****[ read ]***** + public : void read (uint32_t address, uint32_t size, char * & data_dest) + { + for (uint32_t it = 0; it < size ; it ++) + data_dest [it] = data[address-base+it]; + } + + //*****[ write ]***** + public : void write (uint32_t address, uint32_t size, char * & data_src) + { + for (uint32_t it = 0; it < size ; it ++) + data[address-base+it] = data_src [it]; + } + + friend ostream& operator<< (ostream& output_stream, const segment_t & x) + { + output_stream << "Segment \"" << x.name << "\"" << endl + << hex + << " * base : " << setw(8) << setfill('0') << x.base << endl + << " * size : " << setw(8) << setfill('0') << x.size << endl + << dec + << " * uncached : " << x.uncached << endl + << " * type : " << x.type << endl; + + return output_stream; + }; + }; + +};}; //end namespace +#endif //!SEGMENT_H Index: trunk/IPs/systemC/hierarchy_memory/data/type_target.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/data/type_target.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/data/type_target.h (revision 2) @@ -0,0 +1,16 @@ +#ifndef TYPE_TARGET_H +#define TYPE_TARGET_H + +namespace hierarchy_memory { +namespace data { + + typedef enum + { + TYPE_MEMORY , + TYPE_TTY , + TYPE_RAMLOCK , + TYPE_SIM2OS + } type_target_t; + +};}; //end namespace +#endif //!TYPE_TARGET_H Index: trunk/IPs/systemC/hierarchy_memory/endianness/endianness.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/endianness/endianness.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/endianness/endianness.h (revision 2) @@ -0,0 +1,166 @@ +#ifndef _ENDIANNESS_H +#define _ENDIANNESS_H +//=====[ endianness ]========================================================== + +/* + * file : endianness.h + * date (yyyy/mm/dd) : 2006/05/02 + * authors : Rosiere Mathieu + */ + +#include + +#define LittleEndian false +#define BigEndian true + +union TestEndian +{ + unsigned long total; + struct + { + unsigned char octet1; + unsigned char octet2; + unsigned char octet3; + unsigned char octet4; + } octets; +}; + +//-----[ hostEndianness ]------------------------------------------------------ +/* + * false : LitteEndian + * true : BigEndian + */ +inline bool hostEndianness() +{ + union TestEndian test_endian; + test_endian.total = 0xFF; + + return (test_endian.octets.octet1 == 0xFF)?LittleEndian:BigEndian; +} + +//-----[ cpuEndianness ]------------------------------------------------------- +/* + * false : LitteEndian + * true : BigEndian + */ +inline bool cpuEndianness(unsigned int cpu_id) +{ + return(BigEndian); + + /* + * Comment connaitre l'endianness ? + * static : table generee dans le top level + * dynamique : table generee par un l'equivalent de hostEndianness et ecrivant dans un segment precis de la ram + */ +} + +//-----[ isSameEndianness ]---------------------------------------------------- + +/* + * The host machine and the simulate processeur have the same endianness + */ +inline bool isSameEndianness(unsigned int cpu_id) +{ + return ((hostEndianness() ^ cpuEndianness(cpu_id)) == false); +} + +//-----[ swapBytes ]----------------------------------------------------------- +/* + * swapBytes -> change the endiannes + * exemple for 16 and size_access = 4, [0123456789abcdef] -> [32107654ba98fedc] + */ +inline char * swapBytes (char * string_src , unsigned int size_string, unsigned int size_access) +{ + char string_tmp [size_string]; + + if (size_access == 1) + return string_src; + + if (size_string % size_access != 0) + { + cerr << " : Size of string must be a multiple of size_access." << endl; + exit(1); + } + + // size_access : + // 1 -> bytes + // 2 -> half + // 4 -> word + // 8 -> doubleword + + memcpy (string_tmp,string_src,size_string); + + // Loop to reorganize the string + for (unsigned int it_size_string = 0 ; it_size_string < size_string; it_size_string += size_access) + { + // Permutation +// for (unsigned int it_size_access = 0 ; it_size_access < size_access; it_size_access ++) +// string_src [it_size_string+it_size_access] = string_tmp [it_size_string + (size_access-1) - it_size_access]; + switch (size_access) + { + case 2 : + { + string_src[it_size_string+0] = string_tmp[it_size_string+1]; + string_src[it_size_string+1] = string_tmp[it_size_string+0]; + break; + } + case 4 : + { + string_src[it_size_string+0] = string_tmp[it_size_string+3]; + string_src[it_size_string+1] = string_tmp[it_size_string+2]; + string_src[it_size_string+2] = string_tmp[it_size_string+1]; + string_src[it_size_string+3] = string_tmp[it_size_string+0]; + break; + } + case 8 : + { + string_src[it_size_string+0] = string_tmp[it_size_string+7]; + string_src[it_size_string+1] = string_tmp[it_size_string+6]; + string_src[it_size_string+2] = string_tmp[it_size_string+5]; + string_src[it_size_string+3] = string_tmp[it_size_string+4]; + string_src[it_size_string+4] = string_tmp[it_size_string+3]; + string_src[it_size_string+5] = string_tmp[it_size_string+2]; + string_src[it_size_string+6] = string_tmp[it_size_string+1]; + string_src[it_size_string+7] = string_tmp[it_size_string+0]; + break; + } + default : + { + cerr << " : Illegal size of access (size_access = " << size_access << ")" << endl; + exit(1); + break; + } + }//end switch(size_access) + }//end it_size_string + + +// cout << "size_access : " << size_access << endl; +// cout << "size_string : " << size_string << endl; + +// for (unsigned int it_size_string = 0 ; it_size_string < size_string; it_size_string ++) +// printf("%.2x",(unsigned int)string_src[it_size_string]); +// printf("\n"); + +// // Loop to reorganize the string +// for (unsigned int it_size_string = 0 ; it_size_string < size_string; it_size_string += size_access) +// { +// switch (size_access) +// { +// case 2 : string_src[it_size_string] = bswap_16((unsigned short) string_src[it_size_string]); break; +// case 4 : string_src[it_size_string] = bswap_32((unsigned int ) string_src[it_size_string]); break; +// case 8 : string_src[it_size_string] = bswap_64((unsigned long int)string_src[it_size_string]); break; +// default : +// { +// cerr << " : Illegal size of access (size_access = " << size_access << ")" << endl; +// exit(1); +// break; +// } +// }//end switch(size_access) + +// for (unsigned int it_size_string = 0 ; it_size_string < size_string; it_size_string ++) +// printf("%.2x",(unsigned int)string_src[it_size_string]); +// printf("\n"); + + return string_src; +} +#endif //_ENDIANNESS_H Index: trunk/IPs/systemC/hierarchy_memory/file/Makefile =================================================================== --- trunk/IPs/systemC/hierarchy_memory/file/Makefile (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/file/Makefile (revision 2) @@ -0,0 +1,16 @@ + +CXX = g++ +CXX_OPT = -g3 -Wall -Werror -ansi +RM = rm -f + +EXE = $(patsubst %.cpp,%.x ,$(wildcard *.cpp) ) +HEADERS = $(wildcard *.h) + +all : $(EXE) + ./$(EXE) + +%.x : %.cpp $(HEADERS) + $(CXX) $(CXX_OPT) -o $@ $< + +clean : + $(RM) $(EXE) *~ Index: trunk/IPs/systemC/hierarchy_memory/file/entry.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/file/entry.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/file/entry.h (revision 2) @@ -0,0 +1,67 @@ +#ifndef ENTRY_H +#define ENTRY_H + +#include +#include + +using namespace std; // Utilisation de l'espace de nommage standard + +namespace hierarchy_memory +{ + namespace sort_file + { + class Entry + { + public : uint32_t trdid ; // number of thread + public : uint32_t pktid ; // number of packet + public : uint32_t nb_word; + public : uint32_t size_word; + public : char ** data ; + public : uint32_t error ; + + Entry () {}; + + Entry (uint32_t trdid , + uint32_t pktid , + uint32_t nb_word , + uint32_t size_word, + char ** data , + uint32_t error + ) + { + this->trdid = trdid; + this->pktid = pktid; + this->nb_word = nb_word; + this->size_word = size_word; + this->data = new char * [nb_word]; + this->error = error; + + for (uint32_t num_word = 0; num_word < nb_word; num_word++) + { + this->data[num_word] = new char [size_word]; + memcpy(this->data[num_word],data[num_word],size_word); + } + }; + + friend ostream& operator<< (ostream& output_stream, Entry x) + { + output_stream << x.trdid << " " + << x.pktid << " " + << x.error << " "; + + output_stream << hex; + + for (uint32_t it_nb_word = 0; it_nb_word < x.nb_word; it_nb_word ++) + { + for (uint32_t it_size_word = x.size_word; it_size_word > 0 ; it_size_word --) + output_stream << setw(2) << setfill('0') << (0xff & (static_cast(x.data [it_nb_word][it_size_word-1]))); + output_stream << " - "; + } + output_stream << dec; + + return output_stream; + } + }; + }; //sort_file +}; //hierarchy_memory +#endif //!ENTRY_H Index: trunk/IPs/systemC/hierarchy_memory/file/entry_test.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/file/entry_test.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/file/entry_test.h (revision 2) @@ -0,0 +1,42 @@ +#ifndef ENTRY_H +#define ENTRY_H + +#include +#include +using namespace std; // Utilisation de l'espace de nommage standard + +namespace hierarchy_memory +{ + namespace sort_file + { + class Entry + { + public : uint32_t trdid; // number of thread + public : uint32_t pktid; // number of packet + public : uint64_t data; + + Entry () + { + trdid = 0; + pktid = 0; + data = 0; + }; + + Entry (uint32_t trdid , + uint32_t pktid , + uint64_t data ) + { + this->trdid = trdid; + this->pktid = pktid; + this->data = data ; + }; + + friend ostream& operator<< (ostream& output_stream, Entry x) + { + output_stream << x.trdid << " " << x.pktid << " " << hex << x.data << dec; + return output_stream; + } + }; + }; //sort_file +}; //hierarchy_memory +#endif //!ENTRY_H Index: trunk/IPs/systemC/hierarchy_memory/file/file.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/file/file.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/file/file.h (revision 2) @@ -0,0 +1,83 @@ +#ifndef FILE_H +#define FILE_H + +#include +#include +#include "slot.h" + +using namespace std; + +namespace hierarchy_memory +{ + namespace sort_file + { + template + class File + { + protected : char * name; + protected : uint32_t nb_slot; // number of slot + protected : uint32_t size; // size of file + protected : slot_t * slot; + + public : File (char * name, + uint32_t size) + { + uint32_t size_name = strlen(name)+1; + this->name = new char [size_name]; + strncpy(this->name,name,size_name); + + nb_slot = 0; + this->size = size; + slot = new slot_t [size]; + }; + + public : virtual ~File () + { + }; + + // *****[ empty ]***** + // Test if the file is empty + public : bool empty () + { + return (nb_slot == 0); + } + + // *****[ full ]***** + // Test if the file is full + public : bool full () + { + return (nb_slot == size); + } + + // *****[ nb_slot_free ]***** + // return the number of free slot + public : uint32_t nb_slot_free () + { + return (size-nb_slot); + } + + // *****[ nb_slot_use ]***** + // return the number of use slot + public : uint32_t nb_slot_use () + { + return (nb_slot); + } + + // *****[ pop ]***** + // read the file, and update the pointer + public : virtual T pop () {return T();}; + + // *****[ pop ]***** + // read the file, and update the pointer + public : virtual T pop (uint32_t num) {return T();}; + + // *****[ push ]***** + // Push a new value (they must have a slot free) + public : virtual bool push (T val) {return false;}; + + }; // File + + }; //sort_file +}; //hierarchy_memory +#endif //!FILE_H + Index: trunk/IPs/systemC/hierarchy_memory/file/main.cpp =================================================================== --- trunk/IPs/systemC/hierarchy_memory/file/main.cpp (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/file/main.cpp (revision 2) @@ -0,0 +1,187 @@ +#include "sort_file.h" +#include "sort_file_dynamic.h" +#include "entry_test.h" +#include + +using namespace hierarchy_memory::sort_file; +using namespace std; + +void test_ko (int val) +{ + cout << "***** Test(" << val << ") KO *****" << endl; + exit (val); +}; + +void test_ok () +{ + cout << "***** Test OK *****" << endl; + exit (0); +}; + +static uint32_t num_test = 1; + +template +void test(T exp1, T exp2) +{ + if (exp1 != exp2) + { + cerr << "exp1 : " << exp1 << endl; + cerr << "exp2 : " << exp2 << endl; + test_ko (num_test); + } + num_test ++; +}; + +int main () +{ + { + cout << "
Test de \"Sort_File\"" << endl; + + cout << " * creation d'une Sort_File de taille 5" << endl; + Sort_File my_Sort_File = Sort_File (param_t("my_file",5)); + my_Sort_File.reset(); + cout << my_Sort_File << endl; + + cout << " * must be empty ..." << endl; + if ( (my_Sort_File.empty() == false) || + (my_Sort_File.full () == true ) ) + test_ko (1); + + cout << " * insert 6 elements" << endl; + + if (my_Sort_File.push((uint32_t)5,Entry(1,1,0x44444444)) != true ) test_ko (2); cout << my_Sort_File << endl; + if (my_Sort_File.push((uint32_t)6,Entry(2,2,0x55555555)) != true ) test_ko (3); cout << my_Sort_File << endl; + if (my_Sort_File.push((uint32_t)3,Entry(3,3,0x22222222)) != true ) test_ko (4); cout << my_Sort_File << endl; + if (my_Sort_File.push((uint32_t)5,Entry(4,4,0x33333333)) != true ) test_ko (5); cout << my_Sort_File << endl; + if (my_Sort_File.push((uint32_t)1,Entry(5,5,0x11111111)) != true ) test_ko (6); cout << my_Sort_File << endl; + if (my_Sort_File.push((uint32_t)4,Entry(6,6,0x00000BAD)) != false) test_ko (7); cout << my_Sort_File << endl; + + cout << " * must be full ..." << endl; + if ( (my_Sort_File.empty() == true ) || + (my_Sort_File.full () == false) ) + test_ko (8); + + cout << " * extract 6 elements" << endl; + if (my_Sort_File.pop().data != 0x11111111) test_ko (9); + if (my_Sort_File.pop().data != 0x22222222) test_ko (10); + if (my_Sort_File.pop().data != 0x33333333) test_ko (11); + if (my_Sort_File.pop().data != 0x44444444) test_ko (12); + if (my_Sort_File.pop().data != 0x55555555) test_ko (13); + + cout << " * ajout de 8 elements (reset apres le deuxieme)" << endl; + + if (my_Sort_File.push((uint32_t)5,Entry(1,1,0x44444444)) != true ) test_ko (14); cout << my_Sort_File << endl; + if (my_Sort_File.push((uint32_t)6,Entry(2,2,0x55555555)) != true ) test_ko (15); cout << my_Sort_File << endl; + my_Sort_File.reset(); + if (my_Sort_File.push((uint32_t)3,Entry(3,3,0x22222222)) != true ) test_ko (16); cout << my_Sort_File << endl; + if (my_Sort_File.push((uint32_t)5,Entry(4,4,0x33333333)) != true ) test_ko (17); cout << my_Sort_File << endl; + if (my_Sort_File.push((uint32_t)5,Entry(1,1,0x44444444)) != true ) test_ko (18); cout << my_Sort_File << endl; + if (my_Sort_File.push((uint32_t)7,Entry(2,2,0x55555555)) != true ) test_ko (19); cout << my_Sort_File << endl; + if (my_Sort_File.push((uint32_t)1,Entry(5,5,0x11111111)) != true ) test_ko (20); cout << my_Sort_File << endl; + if (my_Sort_File.push((uint32_t)4,Entry(6,6,0x00000BAD)) != false) test_ko (21); cout << my_Sort_File << endl; + + cout << " * 3 transitions" << endl; + + my_Sort_File.transition(); cout << my_Sort_File << endl; + my_Sort_File.transition(); cout << my_Sort_File << endl; + my_Sort_File.transition(); cout << my_Sort_File << endl; + + cout << " * extract 1 element" << endl; + + if (my_Sort_File.pop().data != 0x11111111) test_ko (22); + + cout << my_Sort_File << endl; + + for (uint32_t it = 0; it < my_Sort_File.nb_slot_use(); it ++) + { + slot_t val = my_Sort_File.read(it); + cout << val.delay << " " << val.data << endl; + } + + cout << " * Test pop(n)" << endl; + + test (my_Sort_File.pop(1).data, 0x44444444); + test (my_Sort_File.pop(2).data, 0x55555555); + test (my_Sort_File.pop(0).data, 0x22222222); + test (my_Sort_File.pop(0).data, 0x33333333); + } + + { + cout << "
Test de \"Sort_File_Dynamic\"" << endl; + + cout << " * creation d'une Sort_File de taille 5" << endl; + Sort_File_Dynamic my_Sort_File_Dynamic = Sort_File_Dynamic (param_t("my_file_dynamic",5)); + my_Sort_File_Dynamic.reset(); + cout << my_Sort_File_Dynamic << endl; + + cout << " * must be empty ..." << endl; + if ( (my_Sort_File_Dynamic.empty() == false) || + (my_Sort_File_Dynamic.full () == true ) ) + test_ko (1); + + if (my_Sort_File_Dynamic.push(5,Entry(1,1, 4)) != true ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(6,Entry(2,2, 6)) != true ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(3,Entry(3,3, 2)) != true ) test_ko ( 4); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(5,Entry(4,4, 5)) != true ) test_ko ( 5); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(1,Entry(5,5, 1)) != true ) test_ko ( 6); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(4,Entry(6,6, 3)) != true ) test_ko ( 7); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(9,Entry(1,1,12)) != true ) test_ko ( 8); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(6,Entry(2,2, 7)) != true ) test_ko ( 9); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(7,Entry(3,3, 8)) != true ) test_ko (10); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(7,Entry(4,4, 9)) != true ) test_ko (11); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(8,Entry(5,5,11)) != true ) test_ko (12); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(7,Entry(6,6,10)) != true ) test_ko (13); cout << my_Sort_File_Dynamic << endl; + + if (my_Sort_File_Dynamic.pop().data != 1 ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 2 ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 3 ) test_ko ( 4); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 4 ) test_ko ( 5); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 5 ) test_ko ( 6); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 6 ) test_ko ( 7); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 7 ) test_ko ( 8); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 8 ) test_ko ( 9); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 9 ) test_ko (10); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 10 ) test_ko (11); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 11 ) test_ko (12); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 12 ) test_ko (13); cout << my_Sort_File_Dynamic << endl; + + + if (my_Sort_File_Dynamic.push(5,Entry(1,1, 4)) != true ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(6,Entry(2,2, 6)) != true ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(3,Entry(3,3, 2)) != true ) test_ko ( 4); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(5,Entry(4,4, 5)) != true ) test_ko ( 5); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(1,Entry(5,5, 1)) != true ) test_ko ( 6); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(4,Entry(6,6, 3)) != true ) test_ko ( 7); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(9,Entry(1,1,12)) != true ) test_ko ( 8); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(6,Entry(2,2, 7)) != true ) test_ko ( 9); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(7,Entry(3,3, 8)) != true ) test_ko (10); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(7,Entry(4,4, 9)) != true ) test_ko (11); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(8,Entry(5,5,11)) != true ) test_ko (12); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(7,Entry(6,6,10)) != true ) test_ko (13); cout << my_Sort_File_Dynamic << endl; + + if (my_Sort_File_Dynamic.pop().data != 1 ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 2 ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl; + + if (my_Sort_File_Dynamic.push(0,Entry(1,1, 1)) != true ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(0,Entry(2,2, 2)) != true ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 1 ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 2 ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(0,Entry(1,1, 1)) != true ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(0,Entry(2,2, 2)) != true ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 1 ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 2 ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(0,Entry(1,1, 1)) != true ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(0,Entry(2,2, 2)) != true ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 1 ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 2 ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(0,Entry(1,1, 1)) != true ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.push(0,Entry(2,2, 2)) != true ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 1 ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl; + if (my_Sort_File_Dynamic.pop().data != 2 ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl; + + + } + + test_ok (); + +} Index: trunk/IPs/systemC/hierarchy_memory/file/param.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/file/param.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/file/param.h (revision 2) @@ -0,0 +1,32 @@ +#ifndef PARAM_H +#define PARAM_H + +#include +#include +#include "slot.h" +#include "file.h" + +using namespace std; +using namespace hierarchy_memory::sort_file; + +namespace hierarchy_memory +{ + namespace sort_file + { + class param_t + { + public : char * name; + public : uint32_t size; + + public : param_t (char * name, + uint32_t size) + { + this->name = name; + this->size = size; + } + }; + + }; //sort_file +}; //hierarchy_memory +#endif //!PARAM_H + Index: trunk/IPs/systemC/hierarchy_memory/file/slot.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/file/slot.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/file/slot.h (revision 2) @@ -0,0 +1,39 @@ +#ifndef SLOT_H +#define SLOT_H + +#include +#include + +using namespace std; + +namespace hierarchy_memory +{ + namespace sort_file + { + template + class slot_t + { + public : uint32_t delay; // delay of disponibilty of data + public : T data; + + public : slot_t () + { + } + + public : slot_t (uint32_t delay, T data) + { + this->delay = delay; + this->data = data; + } + + public : friend ostream& operator<< (ostream& output_stream, const slot_t & x) + { + output_stream << x.delay << " " << x.data; + return output_stream; + } + }; + + }; //sort_file +}; //hierarchy_memory +#endif //!SLOT_H + Index: trunk/IPs/systemC/hierarchy_memory/file/sort_file.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/file/sort_file.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/file/sort_file.h (revision 2) @@ -0,0 +1,165 @@ +#ifndef SORT_FILE_H +#define SORT_FILE_H + +#include +#include +#include "file.h" +#include "slot.h" +#include "param.h" + +using namespace std; +using namespace hierarchy_memory::sort_file; + +namespace hierarchy_memory +{ + namespace sort_file + { + /* + * Cicurlar file, sort by delay + */ + + template + class Sort_File : public File + { + // *****[ variables ]***** + protected : uint32_t ptr_read; // pointer of the next slot to read + protected : uint32_t ptr_write; // pointer of the next slot to write + + // *****[ constructor ]***** + public : Sort_File (param_t param) : File (param.name,param.size) + { + + }; + + // *****[ destructor ]***** + public : ~Sort_File () + { + }; + + // *****[ reset ]***** + // Reset the file in the empty state + public : void reset () + { + ptr_read = 0; + ptr_write = 0; + File ::nb_slot = 0; + //nb_slot = 0; + }; + + // *****[ transition ]***** + // Decrease the delay at all cycle + public : void transition () + { + for (uint32_t it = 0; it < File ::nb_slot; it ++) + { + uint32_t ptr = (ptr_read + it)%File ::size; + + if (File ::slot[ptr].delay != 0) + File ::slot[ptr] .delay --; + } + } + + // *****[ read ]***** + // return the n-eme slot. + // (first = 0) + public : slot_t read (uint32_t num) + { + if (num >= File ::nb_slot) + { + cerr << " {ERROR} can't read because : num (" << num << ") >= nb_slot (" << File ::nb_slot << ")" << endl; + exit(1); + } + + return File ::slot[(ptr_read + num)%File ::size]; + }; + + // *****[ pop ]***** + // read the file, and update the pointer + public : T pop () + { + return pop (0); + } + + // *****[ pop ]***** + // read the file, and update the pointer + public : T pop (uint32_t num) + { + if (num >= File ::nb_slot) + { + cerr << " {ERROR} can't read because : num (" << num << ") >= nb_slot (" << File ::nb_slot << ")" << endl; + exit(1); + } + + T val = File ::slot [(ptr_read+num)%File ::size].data; + + // Reorganize the file + + for (uint32_t it = 0; it < num; it ++) + { + uint32_t ptr = (ptr_read + num - it )%File ::size; + uint32_t ptr_next = (ptr-1)%File ::size; + + File ::slot [ptr] = File ::slot [ptr_next]; + } + + File ::nb_slot --; + ptr_read = (ptr_read+1)%File ::size; + + return val; + } + + // *****[ push ]***** + // Push a new value (they must have a slot free) + // Is sort by delay + public : bool push (uint32_t delay, T val) + { + // If full -> quit + if (File ::nb_slot == File ::size) + return false; + + uint32_t ptr = ptr_write; + + // Scan the fill to find the good position (keep the sort) + for (uint32_t it = 0; it < File ::nb_slot; it ++) + { + uint32_t ptr_scan = (ptr-1)%File ::size; + + if (File ::slot[ptr_scan].delay <= delay) + break; //find + + // reformor the file + File ::slot [ptr] = File ::slot [ptr_scan]; + ptr = ptr_scan; + } + + File ::slot [ptr] = slot_t (delay,val); + ptr_write = (ptr_write+1)%File ::size; // update the pointer + File ::nb_slot ++; + + return true; + } + + // *****[ print ]***** + public : friend ostream& operator<< (ostream& output_stream, const Sort_File & x) + { + output_stream << "<" << x.name << ">" << endl; + output_stream << " * ptr_read : " << x.ptr_read << endl; + output_stream << " * ptr_write : " << x.ptr_write << endl; + output_stream << " * nb_slot : " << x.nb_slot << endl; + output_stream << " * size : " << x.size << endl; + + for (uint32_t it = 0; it < x.nb_slot; it ++) + { + uint32_t ptr = (x.ptr_read+it)%x.size; + output_stream << x.slot [ptr] << endl; + } + + return output_stream; + }; + + }; + + }; //sort_file +}; //hierarchy_memory +#endif //!SORT_FILE_H + Index: trunk/IPs/systemC/hierarchy_memory/file/sort_file_dynamic.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/file/sort_file_dynamic.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/file/sort_file_dynamic.h (revision 2) @@ -0,0 +1,224 @@ +#ifndef SORT_FILE_DYNAMIC_H +#define SORT_FILE_DYNAMIC_H + +#include +#include +#include "file.h" +#include "slot.h" +#include "param.h" + +using namespace std; + +namespace hierarchy_memory +{ + namespace sort_file + { + /* + * File, sort by delay with a dynamic size + */ + + template + class Sort_File_Dynamic : public File + { + // *****[ variables ]***** + protected : uint32_t ptr_read ; // pointer of the next slot to read + protected : uint32_t ptr_write; // pointer of the next slot to write + private : uint32_t factor ; + private : const uint32_t size_base; + // *****[ constructor ]***** + public : Sort_File_Dynamic (param_t param) : File (param.name,param.size), size_base (param.size) + { + factor = 1; + }; + + // *****[ destructor ]***** + public : ~Sort_File_Dynamic () + { + }; + + // *****[ must_decrease ]***** + // Test if the file must be decrease + private : bool must_decrease (void) + { + return ( (factor > 1 ) && + (((100*File ::nb_slot)/File ::size) <= 33)); + } + + // *****[ must_increase ]***** + // Test if the file must be increase + private : bool must_increase (void) + { + return (((100*File ::nb_slot)/File ::size) >= 90); + } + + // *****[ increase ]***** + // increase the file + private : void increase (void) + { + factor ++; + change_size (factor*size_base); + } + + // *****[ decrease ]***** + // decrease the file + private : void decrease (void) + { + factor --; + change_size (factor*size_base); + } + + // *****[ change_size ]***** + // decrease the file + private : void change_size (uint32_t new_size) + { + uint32_t old_size = File ::size; + slot_t * new_slot = new slot_t [new_size]; + + // copy data + for (uint32_t it = 0; it < File ::nb_slot; it ++) + { + uint32_t ptr = (ptr_read+it)%old_size; + + new_slot [it] = File ::slot [ptr]; + } + // Change information + delete File ::slot; + File ::slot = new_slot; + File ::size = new_size; + ptr_write = File ::nb_slot; + ptr_read = 0; + } + + // *****[ reset ]***** + // Reset the file in the empty state + public : void reset (void) + { + ptr_read = 0; + ptr_write = 0; + File ::nb_slot = 0; + //nb_slot = 0; + }; + + // *****[ transition ]***** + // Decrease the delay at all cycle + public : void transition () + { + for (uint32_t it = 0; it < File ::nb_slot; it ++) + { + uint32_t ptr = (ptr_read + it)%File ::size; + + if (File ::slot[ptr].delay != 0) + File ::slot[ptr] .delay --; + } + } + + // *****[ read ]***** + // return the n-eme slot. + // (first = 0) + public : slot_t read (uint32_t num) + { + if (num >= File ::nb_slot) + { + cerr << " {ERROR} can't read because : num (" << num << ") >= nb_slot (" << File ::nb_slot << ")" << endl; + exit(1); + } + + return File ::slot[(ptr_read + num)%File ::size]; + }; + + // *****[ pop ]***** + // read the file, and update the pointer + public : T pop () + { + return pop (0); + } + + // *****[ pop ]***** + // read the file, and update the pointer + public : T pop (uint32_t num) + { + if (num >= File ::nb_slot) + { + cerr << " {ERROR} can't read because : num (" << num << ") >= nb_slot (" << File ::nb_slot << ")" << endl; + exit(1); + } + + // If full -> quit + if (must_decrease() == true) + decrease(); + + + T val = File ::slot [(ptr_read+num)%File ::size].data; + + // Reorganize the file + + for (uint32_t it = 0; it < num; it ++) + { + uint32_t ptr = (ptr_read + num - it )%File ::size; + uint32_t ptr_next = (ptr-1)%File ::size; + + File ::slot [ptr] = File ::slot [ptr_next]; + } + + File ::nb_slot --; + ptr_read = (ptr_read+1)%File ::size; + + return val; + } + + // *****[ push ]***** + // Push a new value (they must have a slot free) + // Is sort by delay + public : bool push (uint32_t delay, T val) + { + // If full -> quit + if (must_increase() == true) + increase(); + + uint32_t ptr = ptr_write; + + // Scan the fill to find the good position (keep the sort) + for (uint32_t it = 0; it < File ::nb_slot; it ++) + { + uint32_t ptr_scan = (ptr != 0)?ptr:(File ::size); + ptr_scan --; + + if (File ::slot[ptr_scan].delay <= delay) + break; //find + + // reformor the file + File ::slot [ptr] = File ::slot [ptr_scan]; + ptr = ptr_scan; + } + + File ::slot [ptr] = slot_t (delay,val); + ptr_write = (ptr_write+1)%File ::size; // update the pointer + File ::nb_slot ++; + + return true; + } + // *****[ print ]***** + public : friend ostream& operator<< (ostream& output_stream, const Sort_File_Dynamic & x) + { + output_stream << "<" << x.name << ">" << endl; + output_stream << " * ptr_read : " << x.ptr_read << endl; + output_stream << " * ptr_write : " << x.ptr_write << endl; + output_stream << " * nb_slot : " << x.nb_slot << endl; + output_stream << " * size : " << x.size << endl; + output_stream << " * factor : " << x.factor << endl; + + for (uint32_t it = 0; it < x.nb_slot; it ++) + { + uint32_t ptr = (x.ptr_read+it)%x.size; + output_stream << x.slot [ptr] << endl; + } + + return output_stream; + }; + + + }; + }; //sort_file +}; //hierarchy_memory +#endif //!SORT_FILE_DYNAMIC_H + Index: trunk/IPs/systemC/hierarchy_memory/hierarchy_memory.h =================================================================== --- trunk/IPs/systemC/hierarchy_memory/hierarchy_memory.h (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/hierarchy_memory.h (revision 2) @@ -0,0 +1,952 @@ +#ifndef HIERARCHY_MEMORY_H +#define HIERARCHY_MEMORY_H +#include +#include +#include + +#include +#include "shared/soclib_segment_table.h" +#include "shared/soclib_caches_interfaces.h" + +#include "hierarchy_memory/data/data.h" +#include "hierarchy_memory/file/sort_file.h" +#include "hierarchy_memory/file/entry.h" +#include "hierarchy_memory/cache/cache.h" +#include "hierarchy_memory/ramlock/ramlock.h" +#include "hierarchy_memory/tty/tty.h" +#include "hierarchy_memory/sim2os/sim2os.h" + +#include "hierarchy_memory/cache/type_req_cache.h" + +using namespace std; +using namespace hierarchy_memory::data; +using namespace hierarchy_memory::sort_file; +using namespace hierarchy_memory::cache; +using namespace hierarchy_memory::ramlock; +using namespace hierarchy_memory::tty; +using namespace hierarchy_memory::sim2os; + +namespace hierarchy_memory +{ + template + class param_entity_t + { + public : uint32_t address ; + public : uint32_t size ; + public : T param ; + + public : param_entity_t () {}; + + public : param_entity_t (uint32_t address , + uint32_t size , + T param ) + { + this->address = address ; + this->size = size ; + this->param = param ; + } + };//end param_entity_t + + class param_t + { + public : uint32_t nb_entity_tty; + public : param_entity_t * param_tty; + public : uint32_t nb_entity_ramlock; + public : param_entity_t * param_ramlock; + public : param_entity_t param_sim2os; + public : cache::param_t param_cache; + + public : param_t () {}; + + public : param_t (uint32_t nb_entity_tty , + param_entity_t * param_tty , + uint32_t nb_entity_ramlock , + param_entity_t * param_ramlock , + param_entity_t param_sim2os , + cache::param_t param_cache) + { + this->nb_entity_tty = nb_entity_tty; + this->param_tty = param_tty; + this->nb_entity_ramlock = nb_entity_ramlock; + this->param_ramlock = param_ramlock; + this->param_sim2os = param_sim2os; + this->param_cache = param_cache; + } + };//end param_t + + template + + class HIERARCHY_MEMORY : sc_module + { + //--------------------------------------------------------------------------------------------- + //-----[ PORT ]-------------------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + + public : sc_in_clk CLK; + public : sc_in NRESET; + public : ICACHE_CACHE_PORTS ** ICACHE; + public : DCACHE_CACHE_PORTS ** DCACHE; + + //--------------------------------------------------------------------------------------------- + //-----[ INTERNAL SIGNAL ]--------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + private: bool ** irsp_val; + private: bool ** drsp_val; + + private: bool ** ireq_ack; + private: bool ** dreq_ack; + + //--------------------------------------------------------------------------------------------- + //-----[ COMPONENT ]--------------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + private: Data * component_data; + private: Sort_File ** component_buffer_irsp; + private: Sort_File ** component_buffer_drsp; + + private: Sim2os * component_sim2os; + private: Tty ** component_tty; + private: Ramlock ** component_ramlock; + + private: Cache * component_cache; + //--------------------------------------------------------------------------------------------- + //-----[ VARIABLE ] --------------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + + private: char * NAME; // instance name + private: uint32_t * nb_iport; + private: uint32_t * nb_dport; + private: const uint32_t nb_context; + private: const uint32_t nb_entity; + private: const uint32_t nb_entity_tty; + private: const uint32_t nb_entity_ramlock; + + private: char ** read_iram; + private: char * read_dram; + private: char * write_dram; + + private: bool * context_stop; // to determine which context have send the signal stop (a same thread can send many signal) + private: uint32_t nb_context_stop; // stop the simulation when all context have send the stop signal + //--------------------------------------------------------------------------------------------- + //-----[ CONSTRUCTOR ]------------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + SC_HAS_PROCESS(HIERARCHY_MEMORY); + + public : HIERARCHY_MEMORY (// Fixe parameter + sc_module_name insname , + uint32_t globalIndex , // VCI target index + uint32_t localIndex , + SOCLIB_SEGMENT_TABLE * segtab , // segment table pointer + // variable parameter + uint32_t nb_entity , + uint32_t nb_context , + //*****[ buffer respons ]***** + uint32_t size_buffer_irsp , + uint32_t size_buffer_drsp , + //*****[ entity_param ]***** + param_t param + ): + nb_context (nb_context ), + nb_entity (nb_entity ), + nb_entity_tty (param.nb_entity_tty ), + nb_entity_ramlock (param.nb_entity_ramlock) + { + uint32_t size_name = strlen(insname)+1; + NAME = new char [size_name]; + strncpy(NAME,insname,size_name); + + // *****[ Signal creation ]***** + ICACHE = new ICACHE_CACHE_PORTS * [nb_entity]; + DCACHE = new DCACHE_CACHE_PORTS * [nb_entity]; + + nb_iport = new uint32_t [nb_entity]; + nb_dport = new uint32_t [nb_entity]; + + irsp_val = new bool * [nb_entity]; + drsp_val = new bool * [nb_entity]; + + ireq_ack = new bool * [nb_entity]; + dreq_ack = new bool * [nb_entity]; + + for (uint32_t it = 0; it < nb_entity; it++) + { + nb_iport [it] = param.param_cache.param_icache_dedicated [it].nb_port; + nb_dport [it] = param.param_cache.param_dcache_dedicated [it].nb_port; + + irsp_val [it] = new bool [nb_iport[it]]; + drsp_val [it] = new bool [nb_dport[it]]; + + ireq_ack [it] = new bool [nb_iport[it]]; + dreq_ack [it] = new bool [nb_dport[it]]; + + ICACHE [it] = new ICACHE_CACHE_PORTS [nb_iport [it]]; + DCACHE [it] = new DCACHE_CACHE_PORTS [nb_dport [it]]; + } + + read_iram = new char * [NB_IWORD]; + for (unsigned int num_word = 0; num_word < NB_IWORD; num_word ++) + read_iram [num_word] = new char [SIZE_IDATA/8]; + + read_dram = new char [SIZE_DDATA/8]; + write_dram = new char [SIZE_DDATA/8]; + + // *****[ Create internal structure ]***** + + component_data = new Data (data::param_t("component_data", 16, globalIndex, localIndex, segtab)); + component_buffer_irsp = new Sort_File * [nb_entity]; + component_buffer_drsp = new Sort_File * [nb_entity]; + + for (uint32_t it = 0; it < nb_entity; it++) + { + char name [100]; + sprintf(name,"component_buffer_irsp[%d]",it); + component_buffer_irsp [it] = new Sort_File (sort_file::param_t(name,size_buffer_irsp)); + sprintf(name,"component_buffer_drsp[%d]",it); + component_buffer_drsp [it] = new Sort_File (sort_file::param_t(name,size_buffer_drsp)); + + } + + component_cache = new Cache (param.param_cache); + component_tty = new Tty * [nb_entity_tty ]; + component_ramlock = new Ramlock * [nb_entity_ramlock]; + + for (uint32_t it = 0; it < nb_entity_tty ; it++) + { + component_tty [it] = new Tty (param.param_tty[it] .param); + entity_t entity = component_data->entity(param.param_tty[it].address, param.param_tty[it].size); + + if (entity.present == false) + { + cerr << " the tty [" << it << "] have not a segment in the segment table" << endl; + exit (1); + } + + entity.segment->define_target(TYPE_TTY,it); + } + + for (uint32_t it = 0; it < nb_entity_ramlock; it++) + { + component_ramlock [it] = new Ramlock (param.param_ramlock[it].param); + entity_t entity = component_data->entity(param.param_ramlock[it].address, param.param_ramlock[it].size); + + if (entity.present == false) + { + cerr << " the ramlock [" << it << "] have not a segment in the segment table" << endl; + exit (1); + } + + entity.segment->define_target(TYPE_RAMLOCK,it); + } + + component_sim2os = new Sim2os (param.param_sim2os.param); + entity_t entity = component_data->entity(param.param_sim2os.address, param.param_sim2os.size); + + if (entity.present == false) + { + cerr << " the sim2os have not a segment in the segment table" << endl; + exit (1); + } + + entity.segment->define_target(TYPE_SIM2OS,0); + + nb_context_stop = 0; + context_stop = new bool [1< Successful Instanciation" << endl; + }; + + //--------------------------------------------------------------------------------------------- + //-----[ DESTRUCTOR ]-------------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + public : ~HIERARCHY_MEMORY () + { + for (uint32_t it = 0; it < nb_entity_ramlock; it++) + delete component_ramlock [it]; + for (uint32_t it = 0; it < nb_entity_tty ; it++) + delete component_tty [it]; + + for (uint32_t it = 0; it < nb_entity ; it++) + { + delete component_buffer_drsp [it]; + delete component_buffer_irsp [it]; + } + + delete component_cache ; + delete component_data ; + delete component_sim2os ; + } + + //--------------------------------------------------------------------------------------------- + //-----[ req_type2cache_type ]----------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + + class req_type2cache_type_t + { + public : type_req_cache_t type ; + public : direction_req_cache_t direction ; + + public : req_type2cache_type_t () {}; + + public : req_type2cache_type_t (type_req_cache_t type , + direction_req_cache_t direction ) + { + this->type = type ; + this->direction = direction; + }; + }; + + req_type2cache_type_t ireq_type2cache_type (uint32_t ireq_type, bool uncached) + { + type_req_cache_t type ; + direction_req_cache_t direction; + + switch (ireq_type) + { + case ITYPE_READ : direction=READ ; type=CACHED ; break; + case ITYPE_INVALIDATE : direction=NONE ; type=INVALIDATE; break; + case ITYPE_PREFETCH : direction=NONE ; type=PREFETCH ; break; + default : cerr << " Unkown type (" << type << ")" << endl; exit(1); + } + + return req_type2cache_type_t (type,direction); + } + + req_type2cache_type_t dreq_type2cache_type (uint32_t dreq_type, bool uncached) + { + type_req_cache_t type ; + direction_req_cache_t direction; + + switch (dreq_type) + { + case DTYPE_READ : direction=READ ; type=((uncached==true)?UNCACHED:CACHED); break; + case DTYPE_INVALIDATE : direction=NONE ; type=INVALIDATE ; break; + case DTYPE_WRITE : direction=WRITE; type=((uncached==true)?UNCACHED:CACHED); break; + case DTYPE_WRITE_ACK : direction=WRITE; type=((uncached==true)?UNCACHED:CACHED); break; + case DTYPE_FLUSH : direction=NONE ; type=FLUSH ; break; + case DTYPE_PREFETCH : direction=NONE ; type=INVALIDATE ; break; + + default : cerr << " Unkown type (" << type << ")" << endl; exit(1); + } + + return req_type2cache_type_t (type,direction); + } + //--------------------------------------------------------------------------------------------- + //-----[ init ]-------------------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + public : bool init (char * section, const char * filename, const char ** list_section) + { + return component_data->init(section,filename,list_section); + } + //--------------------------------------------------------------------------------------------- + //-----[ reset ]------------------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + public : void reset () + { + component_cache -> reset(); + // Reset buffer of respons + for (uint32_t it = 0; it < nb_entity; it++) + { + component_buffer_irsp [it] ->reset(); + component_buffer_drsp [it] ->reset(); + } + for (uint32_t it = 0; it < nb_entity_ramlock; it++) + component_ramlock [it] ->reset(); + for (uint32_t it = 0; it < nb_entity_tty ; it++) + component_tty [it] ->reset(); + }//end reset + + //--------------------------------------------------------------------------------------------- + //-----[ itoa ]-------------------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + private :char * itoa (uint32_t int_src, char * string_dest, uint32_t size) + { + for (unsigned int it_size = 0; it_size < size; it_size ++) + { + string_dest [it_size] = (int_src & 0xFF); + //string_dest [size-it_size-1] = (int_src & 0xFF); + + int_src >>= 8; + } + return string_dest; + } + + //--------------------------------------------------------------------------------------------- + //-----[ stop ]-------------------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + public : bool stop () + { + return (nb_context_stop >= nb_context); + } + + //--------------------------------------------------------------------------------------------- + //-----[ transition ]-------------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + public : void transition() + { + if (NRESET.read() == false) + { + reset (); + return; + } + + //~~~~~[ respons ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // POP All buffer of respons + for (uint32_t num_entity = 0; num_entity < nb_entity; num_entity++) + { + for (uint32_t num_port = nb_iport [num_entity]; num_port > 0 ; num_port --) + if ((irsp_val[num_entity][num_port-1] && ICACHE [num_entity][num_port-1].RSP_ACK.read())==true) + component_buffer_irsp [num_entity]->pop(num_port-1); + + for (uint32_t num_port = nb_dport [num_entity]; num_port > 0 ; num_port --) + if ((drsp_val[num_entity][num_port-1] && DCACHE [num_entity][num_port-1].RSP_ACK.read())==true) + component_buffer_drsp [num_entity]->pop(num_port-1); + } + + //~~~~~[ request ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // cout << "" << endl; + for (uint32_t num_entity = 0; num_entity < nb_entity; num_entity++) + { + // ****************** + // ***** ICACHE ***** + // ****************** + for (uint32_t num_port = 0; num_port < nb_iport [num_entity]; num_port ++) + { + // Test if transaction + if ( (ICACHE [num_entity][num_port].REQ_VAL.read() && ireq_ack [num_entity][num_port]) == false) + continue; + + entity_t entity = component_data->entity((uint32_t)ICACHE [num_entity][num_port].REQ_ADDR.read(), SIZE_IDATA/8); + bool uncached = false; + bool bus_error = false; + + sc_uint<2> type = ICACHE[num_entity][num_port].REQ_TYPE .read(); + // A lot of flag + bool must_read = ((type == DTYPE_READ ) ); + bool must_ack = ((type == DTYPE_READ ) ); + + // Test the type of the address : if != MEMORY -> error + if ((entity.present == true) && (entity.segment->getType() == TYPE_MEMORY)) + { + if (must_read == true) // Test if must read the ram + for (unsigned int num_word = 0; num_word < NB_IWORD; num_word ++) + { + uint32_t addr = (uint32_t) ICACHE [num_entity][num_port].REQ_ADDR.read()+num_word*(SIZE_IDATA/8); + bus_error |= !component_data->read(addr , + SIZE_IDATA/8 , + read_iram[num_word]); + + if (isSameEndianness((uint32_t)ICACHE[num_entity][num_port].REQ_TRDID.read()) == false) + read_iram[num_word] = swapBytes(read_iram[num_word],SIZE_IDATA/8,4); + } + uncached = entity.segment->getUncached(); + } + else + { + // Have a bus error + bus_error = true; + uncached = true; + } + + req_type2cache_type_t cache_type = ireq_type2cache_type ((uint32_t)type,uncached); + // Simplification : the size of a line is a multiple of size_iword (no test) + uint32_t latence = component_cache->latence(INSTRUCTION_CACHE , + num_entity , + num_port , + (uint32_t)ICACHE [num_entity][num_port].REQ_ADDR .read() , + (uint32_t)ICACHE [num_entity][num_port].REQ_TRDID.read() , + cache_type.type , + cache_type.direction ); + + // If is a respons -> compute the latence and push in the write_buffer + if (must_ack == true) + { + if (bus_error == true) + cout << "Icache : have a bus error" << endl + << " * num_entity : " << num_entity << endl + << " * num_port : " << num_port << endl + << hex + << " * req_addr : " << (uint32_t)ICACHE [num_entity][num_port].REQ_ADDR .read() << endl + << dec + << " * req_trdid : " << (uint32_t)ICACHE [num_entity][num_port].REQ_TRDID.read() << endl + << " * req_pktid : " << (uint32_t)ICACHE [num_entity][num_port].REQ_PKTID.read() << endl; + + component_buffer_irsp [num_entity]->push(latence, + Entry((uint32_t)ICACHE [num_entity][num_port].REQ_TRDID.read() , + (uint32_t)ICACHE [num_entity][num_port].REQ_PKTID.read() , + NB_IWORD , + SIZE_IDATA/8 , + read_iram , + (bus_error==true)?ERR_BUS:ERR_NO ) + ); + } + }//num_port + + // ****************** + // ***** DCACHE ***** + // ****************** + + for (uint32_t num_port = 0; num_port < nb_dport [num_entity]; num_port ++) + { + // Test if transaction +// cout << "[" << num_entity << "]" +// << "[" << num_port << "] " +// << "dreq_val : " << DCACHE [num_entity][num_port].REQ_VAL.read() << " " +// << "dreq_ack : " << dreq_ack [num_entity][num_port] << endl; + + if ( (DCACHE [num_entity][num_port].REQ_VAL.read() && dreq_ack [num_entity][num_port]) == false) + continue; + + entity_t entity = component_data->entity((uint32_t)DCACHE [num_entity][num_port].REQ_ADDR.read(), SIZE_DDATA/8); + + bool uncached = DCACHE [num_entity][num_port].REQ_UNC.read(); + bool bus_error = false; + + uint32_t addr = (uint32_t) DCACHE [num_entity][num_port].REQ_ADDR.read(); + sc_uint wdata = DCACHE[num_entity][num_port].REQ_WDATA .read(); + sc_uint<3> type = DCACHE[num_entity][num_port].REQ_TYPE .read(); + uint32_t nb_bytes = access_nb_bytes(DCACHE[num_entity][num_port].REQ_ACCESS.read()); + // A lot of flag + bool must_read = ((type == DTYPE_READ )); + bool must_write = ((type == DTYPE_WRITE ) || + (type == DTYPE_WRITE_ACK ) ); + bool must_ack = ((type == DTYPE_READ ) || + (type == DTYPE_WRITE_ACK ) ); + + // Test the type of the address + if (entity.present == true) + { + switch (entity.segment->getType()) + { + // ACCESS AT A RAM + case TYPE_MEMORY : + { + if (must_read == true) + { + // Read + bus_error |= !component_data->read(addr , + SIZE_DDATA/8 , // always read a complete word + read_dram ); + + for (unsigned int it_size_data = nb_bytes; it_size_data < SIZE_DDATA/8; it_size_data+=nb_bytes) + memcpy(&(read_dram[it_size_data]),&(read_dram[0]),nb_bytes); + + // Permutation if problem of endianness + if (isSameEndianness((uint32_t)DCACHE[num_entity][num_port].REQ_TRDID.read()) == false) + read_dram = swapBytes(read_dram , SIZE_DDATA/8, nb_bytes); + } + + if (must_write == true) + { + // Write + for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++) + write_dram [it_nb_bytes] = wdata.range(8*(it_nb_bytes+1)-1,8*it_nb_bytes); + } + break; + } + //ACCESS AT THE TTY + case TYPE_TTY : + { + if (must_write == false) + { + bus_error = true; + break; + } + uint32_t num_tty = (addr - entity.segment->getBase())>>4; + uint32_t num_print = ((addr>>2) & 0x3); + + switch (num_print) + { + case 0 : // Write TTY + { + uint32_t num_component_tty = entity.segment->getIndex(); + char char_write = (char)wdata.range( 7, 0); + bus_error |= !component_tty [num_component_tty]->write(num_tty,char_write); + break; + } + case 1 : // STOP + { + printf("\n\t***** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x *****\n" + ,(unsigned int)sc_simulation_time() + ,(unsigned int)addr + ,(unsigned int)wdata.range(31,24) + ,(unsigned int)wdata.range(23,16) + ,(unsigned int)wdata.range(15, 8) + ,(unsigned int)wdata.range( 7, 0) + ); + + uint32_t trdid = (uint32_t) DCACHE[num_entity][num_port].REQ_TRDID.read(); + + if (context_stop [trdid] == false) + { + context_stop [trdid] = true; + nb_context_stop ++; + + if (nb_context_stop >= nb_context) + sc_stop(); + } + + break; + } + case 2 : // PRINT + { + printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n" + ,(unsigned int)sc_simulation_time() + ,(unsigned int)addr + ,(unsigned int)wdata.range(31,24) + ,(unsigned int)wdata.range(23,16) + ,(unsigned int)wdata.range(15, 8) + ,(unsigned int)wdata.range( 7, 0) + ); + + break; + } + default : + { + printf("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print); + exit(1); + } + } + + break; + } + case TYPE_RAMLOCK : + { + // Access is on a byte, else error + if (nb_bytes != 1) + { + bus_error = true; + break; + } + uint32_t num_ramlock = (addr - entity.segment->getBase()); // Char access + uint32_t num_component_ramlock = entity.segment->getIndex(); + bus_error |= !component_ramlock [num_component_ramlock]->test(num_ramlock); + + if (bus_error == true) + break; + + memset (read_dram,0,SIZE_DDATA/8); + + if (must_read == true) + read_dram [0] = (char)component_ramlock [num_component_ramlock]->read (num_ramlock); + if (must_write == true) + read_dram [0] = (char)component_ramlock [num_component_ramlock]->write(num_ramlock); + + /* + printf("Access ramlock ( %d )\n" ,(uint32_t)sc_simulation_time()); + printf(" * addr : %.8x\n" ,(uint32_t)addr); + printf(" * trdid : %d\n" ,(uint32_t)DCACHE[num_entity][num_port].REQ_TRDID.read()); + printf(" * r/w : %d/%d\n",must_read,must_write); + printf(" * val : %d\n" ,(uint32_t)read_dram[0]); + */ + break; + } + case TYPE_SIM2OS : + { + // Mapping : + // [0] number of service - Wonly - A write in this register lunch the execution of service + // [1] result - Ronly - Content the result of the service + // [2] error - Ronly - Content the code of errno + // [3+] argument - Wonly - it's all argument to execute the service + + uint32_t num_reg = (addr - entity.segment->getBase())>>2; + + switch (num_reg) + { + case 0 : // ---> number of service + { + if (must_write == false) + { + cerr << "<" << NAME << "> {ERROR} : SIM2OS[0] is not accessible in Read" << endl; + bus_error = true; + } + else + { + printf(" service : %.8x\n",(uint32_t)wdata); + component_sim2os->execute(int2service((uint32_t)wdata)); + } + break; + } + case 1 : // ---> result + { + if (must_read == false) + { + cerr << "<" << NAME << "> {ERROR} : SIM2OS[1] is not accessible in Write" << endl; + bus_error = true; + } + else + { + // Decomposition en groupe octect + uint32_t result = (uint32_t) component_sim2os->result; + printf(" result : %.8x (%d)\n",result,result); + + read_dram = itoa(result,read_dram,SIZE_DDATA/8); + } + break; + } + case 2 : // ---> error + { + if (must_read == false) + { + cerr << "<" << NAME << "> {ERROR} : SIM2OS[2] is not accessible in Write" << endl; + bus_error = true; + } + else + { + // Decomposition en groupe octect + uint32_t error = (uint32_t) component_sim2os->error; + printf(" error : %.8x\n",error); + read_dram = itoa(error ,read_dram,SIZE_DDATA/8); + } + break; + } + default : // ---> argument + { + if (must_write == false) + { + cerr << "<" << NAME << "> {ERROR} : SIM2OS[" << num_reg << "] is not accessible in Write" << endl; + bus_error = true; + } + else + { + uint32_t data = (uint32_t)wdata; + printf(" argument[%d] : %.8x\n",num_reg-1,data); + component_sim2os->parameter(num_reg-2,(void *)data); + } + break; + } + }//end switch num_reg + + break; + } + default : + { + // Have a bus error + bus_error = true; + break; + } + }// switch + uncached |= entity.segment->getUncached(); + } + else + uncached = true; // If segment don't exist : it's the system bus that determine if the segment exist + + + if ((must_write == true) && (bus_error == false)) + { + // Permutation if problem of endianness + if (isSameEndianness((uint32_t)DCACHE[num_entity][num_port].REQ_TRDID.read()) == false) + write_dram = swapBytes(write_dram, SIZE_DDATA/8, nb_bytes); + + bus_error |= !component_data->write(addr , + nb_bytes, // take the good access + write_dram ); + } + + + // Acces at the cache !!! + req_type2cache_type_t cache_type = dreq_type2cache_type (type, uncached); + + uint32_t latence = component_cache->latence(DATA_CACHE , + num_entity , + num_port , + (uint32_t)DCACHE [num_entity][num_port].REQ_ADDR .read() , + (uint32_t)DCACHE [num_entity][num_port].REQ_TRDID.read() , + cache_type.type , + cache_type.direction ); + + // If is a respons -> compute the latence and push in the write_buffer + if ( must_ack == true) + { + if (bus_error == true) + cout << "Dcache : have a bus error" << endl; + component_buffer_drsp [num_entity]->push(latence, + Entry((uint32_t)DCACHE [num_entity][num_port].REQ_TRDID.read() , + (uint32_t)DCACHE [num_entity][num_port].REQ_PKTID.read() , + 1 , + SIZE_DDATA/8 , + &read_dram , + (bus_error==true)?ERR_BUS:ERR_NO ) + ); + } + }// dnb_port + }//num_entity + + // Transition for each component + component_cache -> transition(); + // Transition buffer of respons + for (uint32_t it = 0; it < nb_entity; it++) + { + component_buffer_irsp [it] ->transition(); + component_buffer_drsp [it] ->transition(); + } + component_sim2os->transition(); + + }//end transition + + //--------------------------------------------------------------------------------------------- + //-----[ genMoore ]---------------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + public : void genMoore() + { + //Scan all entity and for each entity scan all port + for (uint32_t num_entity = 0; num_entity < nb_entity; num_entity++) + { + //##### REQUEST ##### + uint32_t nb_slot_free = component_buffer_irsp [num_entity]->nb_slot_free (); + for (uint32_t num_port = 0; num_port < nb_iport [num_entity]; num_port ++) + { + ireq_ack [num_entity][num_port] = (num_port < nb_slot_free); + + ICACHE [num_entity][num_port].REQ_ACK.write (ireq_ack [num_entity][num_port]); + } + + nb_slot_free = component_buffer_drsp [num_entity]->nb_slot_free (); + for (uint32_t num_port = 0; num_port < nb_dport [num_entity]; num_port ++) + { + dreq_ack [num_entity][num_port] = (num_port < nb_slot_free ); + + DCACHE [num_entity][num_port].REQ_ACK.write (dreq_ack [num_entity][num_port]); + } + + //##### RESPONS ##### + // ~~~~~> ICACHE <~~~~~ + for (uint32_t num_port = 0; num_port < nb_iport [num_entity]; num_port ++) + { + // Test the number of element in the respons's buffer + if (num_port >= component_buffer_irsp [num_entity]->nb_slot_use()) + { + irsp_val[num_entity][num_port] = 0; // No respons + } + else + { + slot_t slot = component_buffer_irsp [num_entity]->read(num_port); + + irsp_val[num_entity][num_port] = (slot.delay == 0); // respons if have a result + ICACHE [num_entity][num_port].RSP_TRDID.write((sc_uint )slot.data.trdid); + ICACHE [num_entity][num_port].RSP_PKTID.write((sc_uint)slot.data.pktid); + ICACHE [num_entity][num_port].RSP_ERR .write((sc_uint<2> )slot.data.error); + + for (uint32_t num_word = 0; num_word < NB_IWORD; num_word ++) + { + sc_uint data; + + for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_IDATA / 8; it_nb_bytes ++) + { +#if defined(systemcass) + RANGE_SET_VAL(SIZE_IDATA , + data , + 8*(it_nb_bytes+1)-1, + 8*it_nb_bytes , + slot.data.data [num_word][it_nb_bytes]); +#else //#elif defined(systemc) + data.range(8*(it_nb_bytes+1)-1,8*it_nb_bytes) = slot.data.data [num_word][it_nb_bytes]; +#endif + } + ICACHE [num_entity][num_port].RSP_INS [num_word].write(data); + } + } + + ICACHE [num_entity][num_port].RSP_VAL.write(irsp_val[num_entity][num_port]); + }//end nb_iport + + // ~~~~~> DCACHE <~~~~~ + for (uint32_t num_port = 0; num_port < nb_dport [num_entity]; num_port ++) + { + if (num_port >= component_buffer_drsp [num_entity]->nb_slot_use()) + { + drsp_val[num_entity][num_port] = 0; // No respons + } + else + { + slot_t slot = component_buffer_drsp [num_entity]->read(num_port); + + drsp_val[num_entity][num_port] = (slot.delay == 0); + DCACHE [num_entity][num_port].RSP_TRDID = (sc_uint )slot.data.trdid; + DCACHE [num_entity][num_port].RSP_PKTID = (sc_uint)slot.data.pktid; + DCACHE [num_entity][num_port].RSP_ERR = (sc_uint<2> )slot.data.error; + + sc_uint data; + + for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++) + { +#if defined(systemcass) + RANGE_SET_VAL(SIZE_DDATA , + data , + 8*(it_nb_bytes+1)-1, + 8*it_nb_bytes , + slot.data.data [0][it_nb_bytes]); +#else //#elif defined(systemc) + data.range(8*(it_nb_bytes+1)-1,8*it_nb_bytes) = slot.data.data [0][it_nb_bytes]; +#endif + } + DCACHE [num_entity][num_port].RSP_RDATA.write(data); + } + DCACHE [num_entity][num_port].RSP_VAL = drsp_val[num_entity][num_port]; + }//nb_dport + }//nb_entity + }//end genMoore + + //--------------------------------------------------------------------------------------------- + //-----[ operator<< ]-------------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------- + + friend ostream& operator<< (ostream& output_stream, const HIERARCHY_MEMORY &x) + { + output_stream << "<" << x.NAME << ">" << endl + << " * nb_entity : " << x.nb_entity << endl; + + output_stream << " -----[ component_data ]-----------------------------------" << endl; + output_stream << *x.component_data << endl; + + output_stream << " -----[ component_cache ]----------------------------------" << endl; + output_stream << *x.component_cache; + + output_stream << " -----[ component_buffer_irsp ]----------------------------" << endl; + for (uint32_t num_entity = 0; num_entity < x.nb_entity; num_entity++) + { + output_stream << " * nb_iport [" << num_entity << "] : " << x.nb_iport [num_entity] << endl; + output_stream << *x.component_buffer_irsp [num_entity]; + } + + output_stream << " -----[ component_buffer_drsp ]----------------------------" << endl; + for (uint32_t num_entity = 0; num_entity < x.nb_entity; num_entity++) + { + output_stream << " * nb_dport [" << num_entity << "] : " << x.nb_dport [num_entity] << endl; + output_stream << *x.component_buffer_drsp [num_entity]; + } + + // output_stream << " -----[ component_ramlock ]--------------------------------" << endl; + // output_stream << " * nb_entity_ramlock : " << x.nb_entity_ramlock << endl; + // for (uint32_t it = 0; it < x.nb_entity_ramlock; it++) + // output_stream << *x.component_ramlock [it]; + + // output_stream << " -----[ component_tty ]------------------------------------" << endl; + // output_stream << " * nb_entity_tty : " << x.nb_entity_tty << endl; + // for (uint32_t it = 0; it < x.nb_entity_tty ; it++) + // output_stream << *x.component_tty [it]; + + // output_stream << *x.component_sim2os; + + return output_stream; + } + + };//class +}; + +#endif //!HIERARCHY_MEMORY_H Index: trunk/IPs/systemC/hierarchy_memory/main.cpp =================================================================== --- trunk/IPs/systemC/hierarchy_memory/main.cpp (revision 2) +++ trunk/IPs/systemC/hierarchy_memory/main.cpp (revision 2) @@ -0,0 +1,787 @@ +#include "hierarchy_memory.h" +#include +#include + +#define TEXT_BASE 0x00000000 +#define TEXT_SIZE 0x00005000 + +#define DATA_CACHED_BASE 0x10000000 +#define DATA_CACHED_SIZE 0x00000100 + +#define DATA_UNCACHED_BASE 0x40000000 +#define DATA_UNCACHED_SIZE 0x00000100 + +#define STACK_BASE 0x50000000 +#define STACK_SIZE 0x00000200 + +#define TTY1_BASE 0x60000000 +#define TTY1_SIZE 0x00000100 + +#define TTY2_BASE 0x60000100 +#define TTY2_SIZE 0x00000200 + +#define SIM2OS_BASE 0x70000000 +#define SIM2OS_SIZE 0x00000100 + +#define RAMLOCK_BASE 0x80000000 +#define RAMLOCK_SIZE 0x00000100 + +// using namespace hierarchy_memory::data; +using namespace std; +using namespace hierarchy_memory; + +//-----[ Routine de test ]--------------------------------------- + +void test_ko (char * file, uint32_t line) +{ + cerr << "***** Test KO *****" << endl + << " - File : " << file << endl + << " - Line : " << line << endl; + exit (line); +}; + +void test_ok () +{ + cout << "***** Test OK *****" << endl; + exit (0); +}; + +template +void test(T exp1, T exp2, char * file, uint32_t line) +{ + if (exp1 != exp2) + { + cerr << "Expression is different : " << endl + << " - exp1 : " << exp1 << endl + << " - exp2 : " << exp2 << endl; + + test_ko (file,line); + } +}; + +#define TEST(type,exp1,exp2) do { test (exp1,exp2,__FILE__,__LINE__);} while(0) + +int sc_main(int argc, char* argv[]) +{ + cout << "
Test de \"HIERARCHY_MEMORY\"" << endl; + + /********************************************************************* + * Declarations des constantes + *********************************************************************/ + const uint32_t nb_context = 6; + const uint32_t nb_cluster = 2; + const uint32_t nb_iport = 1; + const uint32_t nb_dport = 3; + const uint32_t size_trdid = 5; + const uint32_t size_ipktid = 4; + const uint32_t size_iaddr = 32; + const uint32_t size_idata = 32; + const uint32_t nb_iword = 2; + const uint32_t size_dpktid = 2; + const uint32_t size_daddr = 32; + const uint32_t size_ddata = 32; + + const uint32_t size_buffer_irsp = 9; + const uint32_t size_buffer_drsp = 7; + /********************************************************************* + * Declarations des signaux + *********************************************************************/ + cout << " * Declaration of signals" << endl; + sc_clock CLK ("clock",1,0.5); + sc_signal NRESET; + + ICACHE_SIGNALS ** icache_signals; + DCACHE_SIGNALS ** dcache_signals; + + icache_signals = new ICACHE_SIGNALS * [nb_cluster]; + dcache_signals = new DCACHE_SIGNALS * [nb_cluster]; + + for (uint32_t x = 0; x < nb_cluster; x ++) + { + icache_signals[x] = new ICACHE_SIGNALS [nb_iport]; + dcache_signals[x] = new DCACHE_SIGNALS [nb_dport]; + } + + /********************************************************************* + * Segmentation table + *********************************************************************/ + cout << " * Segment_table" << endl; + + SOCLIB_SEGMENT_TABLE segtable; + segtable.setMSBNumber (8); + segtable.setDefaultTarget(0,0); + + // Add a segment :name , address of base , size , global index , local index, uncache + segtable.addSegment("text" , TEXT_BASE , TEXT_SIZE , 0 ,0 , false); + segtable.addSegment("data" , DATA_CACHED_BASE , DATA_CACHED_SIZE , 0 ,0 , false); + segtable.addSegment("data_unc" , DATA_UNCACHED_BASE , DATA_UNCACHED_SIZE , 0 ,0 , true ); + segtable.addSegment("stack" , STACK_BASE , STACK_SIZE , 0 ,0 , false); + segtable.addSegment("tty1" , TTY1_BASE , TTY1_SIZE , 0 ,0 , true ); + segtable.addSegment("tty2" , TTY2_BASE , TTY2_SIZE , 0 ,0 , true ); + segtable.addSegment("sim2os" , SIM2OS_BASE , SIM2OS_SIZE , 0 ,0 , true ); + segtable.addSegment("ramlock" , RAMLOCK_BASE , RAMLOCK_SIZE , 0 ,0 , true ); + + const char * sections_text [] = {".text",NULL}; + const char * sections_data [] = {".data",".rodata",".sdata",".sbss",".bss", NULL}; + const char * sections_stack [] = {".stack",NULL}; + const char * filename = "soft.x"; + + /********************************************************************* + * Declaration of component + *********************************************************************/ + char * name_tty1[nb_context/2] = { "tty_0", + "tty_1", + "tty_2"}; + + char * name_tty2[nb_context/2] = { "tty_3", + "tty_4", + "tty_5"}; + + // nb_line, size_line, size_word, associativity, hit_latence, miss_penality +#define L1_ICACHE "L1_ICACHE", 4, 2, 4, 4, 1, 4 +#define L1_DCACHE "L1_DCACHE", 4, 2, 4, 4, 1, 4 +#define L2_CACHE "L2_CACHE", 8, 4, 4, 2, 2, 7 +#define L3_CACHE "L3_CACHE", 16, 8, 4, 1, 3, 12 + + param_cache_t param_icache_1 [1] = { param_cache_t (L1_ICACHE) }; + param_cache_t param_dcache_1 [1] = { param_cache_t (L1_DCACHE) }; + param_cache_t param_cache_2 [2] = { param_cache_t (L2_CACHE) , + param_cache_t (L3_CACHE) }; + + cache::cache_multilevel::param_t param_icache_dedicated [nb_cluster] = {cache::cache_multilevel::param_t ("param_icache_dedicated[0]",1, nb_iport, param_icache_1), + cache::cache_multilevel::param_t ("param_icache_dedicated[1]",1, nb_iport, param_icache_1), + }; + + cache::cache_multilevel::param_t param_dcache_dedicated [nb_cluster] = {cache::cache_multilevel::param_t ("param_dcache_dedicated[0]",1, nb_dport, param_dcache_1), + cache::cache_multilevel::param_t ("param_dcache_dedicated[1]",1, nb_dport, param_dcache_1), + }; + + cache::cache_multilevel::param_t param_cache_shared ("param_cache_shared",2, nb_cluster*(nb_iport+nb_dport), param_cache_2); + + cache::param_t param_cache ("cache" , + nb_cluster , + param_icache_dedicated, + param_dcache_dedicated, + param_cache_shared ); + param_entity_t param_tty [2] = {param_entity_t (TTY1_BASE , TTY1_SIZE , tty::param_t ("tty1" , nb_context/2, name_tty1,true)), + param_entity_t (TTY2_BASE , TTY2_SIZE , tty::param_t ("tty2" , nb_context/2, name_tty2,true))}; + param_entity_t param_ramlock [1] = {param_entity_t(RAMLOCK_BASE, RAMLOCK_SIZE, ramlock::param_t("ramlock", RAMLOCK_SIZE))}; + + + param_entity_t param_sim2os = param_entity_t(SIM2OS_BASE, SIM2OS_SIZE, sim2os::param_t("sim2os",&segtable)); + +#define PARAM_MEMORY 2,param_tty,1,param_ramlock,param_sim2os,param_cache +#define PARAM "memory", 0,0, &segtable,nb_cluster, nb_context,size_buffer_irsp, size_buffer_drsp, hierarchy_memory::param_t(PARAM_MEMORY) +#define TEMPLATE size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword, size_dpktid, size_daddr, size_ddata + + HIERARCHY_MEMORY