Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src/test.cpp	(revision 15)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src/test.cpp	(revision 23)
@@ -9,4 +9,5 @@
 #define NB_ITERATION 16
 
+#define TEXT(str)  do {cout << "<" << name << "> : " << str << endl;} while (0)
 #define LABEL(str) do {cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; _RegisterFile_Multi_Banked_Glue->vhdl_testbench_label(str);} while (0)
 
@@ -18,5 +19,5 @@
 	   morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::Parameters _param)
 {
-  cout << "<" << name << "> : Simulation SystemC" << endl;
+  TEXT("Simulation SystemC");
 
   RegisterFile_Multi_Banked_Glue * _RegisterFile_Multi_Banked_Glue = new RegisterFile_Multi_Banked_Glue (name.c_str(),
@@ -192,5 +193,5 @@
    ********************************************************/
   
-  cout << "<" << name << "> Instanciation of _RegisterFile_Multi_Banked_Glue" << endl;
+   TEXT("Instanciation of _RegisterFile_Multi_Banked_Glue");
   
   (*(_RegisterFile_Multi_Banked_Glue->in_CLOCK))        (*(CLOCK));
@@ -247,5 +248,5 @@
 
 
-  cout << "<" << name << "> Start Simulation ............" << endl;
+   TEXT("Start Simulation ............");
   
   /********************************************************
@@ -265,13 +266,13 @@
 
   uint32_t   read_in_num_bank [_param._nb_port_read]; // Number of bank
-//Tcontrol_t read_in_valid    [_param._nb_port_read];
+  Tcontrol_t read_is_busy     [_param._nb_port_read];
+  bool       read_out_find    [_param._nb_bank][_param._nb_port_read_by_bank];  
+  uint32_t   read_out_port    [_param._nb_bank][_param._nb_port_read_by_bank];  
+
   Tcontrol_t read_in_ack      [_param._nb_port_read]; // to test
   Tdata_t    read_in_data     [_param._nb_port_read]; // to test
   Tcontrol_t read_out_val     [_param._nb_bank][_param._nb_port_read_by_bank];  
-  Tcontrol_t read_out_ack     [_param._nb_bank][_param._nb_port_read_by_bank];  
   Taddress_t read_out_address [_param._nb_bank][_param._nb_port_read_by_bank];  
-  Tcontrol_t read_is_busy     [_param._nb_port_read];
-  Tcontrol_t read_select_val  [_param._nb_bank][_param._nb_port_read        ];
-  Tcontrol_t read_select_ack  [_param._nb_bank][_param._nb_port_read        ];
+  Tcontrol_t read_select_val  [_param._nb_bank][_param._nb_port_read_by_bank][_param._nb_port_read];
 
   LABEL("Loop of Test");
@@ -281,5 +282,5 @@
       LABEL("Iteration "+toString(iteration));
       
-      LABEL("Test read_in");
+      //LABEL("Test read_in");
       
       // Write in interface "read_in"
@@ -287,34 +288,32 @@
 	{
 	  read_in_num_bank  [i] =  rand() % _param._nb_bank;
-	  Tcontrol_t read_in_valid = (rand() % 2) != 0;
+	  Tcontrol_t read_in_val = (rand() % 2) != 0;
 
 	  Taddress_t address    = (read_in_num_bank[i] << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i);
 
-	  read_is_busy      [i] = (read_in_valid == 0);
-	  read_in_ack       [i] = 0;
-	  read_in_data      [i] = 0;
-	  READ_IN_VAL       [i]->write(read_in_valid);
-	  READ_IN_ADDRESS   [i]->write(address);
-
-	  for (uint32_t j=0; j<_param._nb_bank; j++)
-	    read_select_ack [j][i] = 0;
+	  read_is_busy      [i] = (read_in_val == 0);   // invalid = busy
+	  read_in_ack       [i] = 0;                    // init
+	  read_in_data      [i] = 0;                    // init
+	  READ_IN_VAL       [i]->write(read_in_val);    // write signal
+	  READ_IN_ADDRESS   [i]->write(address);        // write signal
 	}
 
-      for (uint32_t i=0; i<_param._nb_bank; i++)
-	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
-	  {
-	    read_out_ack      [i][j] = (rand() % 2) != 0;
-	    READ_OUT_ACK      [i][j]->write(read_out_ack      [i][j]);
-	    READ_OUT_DATA     [i][j]->write((j<<1)|1); // (j<<1)|1 afin de n'avoir jamais 0
-	  }
-      
       // compute the good read_select
       for (uint32_t i=0; i<_param._nb_bank; i++)
 	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
 	  {
+	    Tcontrol_t read_out_ack = (rand() % 2) != 0;
+	    READ_OUT_ACK     [i][j]->write(read_out_ack);
+	    READ_OUT_DATA    [i][j]->write((j<<1)|1);            // (j<<1)|1 afin de n'avoir jamais 0
+
+	    read_out_find    [i][j] = false;
+	    read_out_port    [i][j] = 0;
+
+	    read_out_val     [i][j] = 0;
+	    read_out_address [i][j] = 0;
+
 	    bool find = false; // have find a port_in to link with this port_out
 	    for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
 	      {
-
 		uint32_t num_port; // number of port
 		
@@ -323,27 +322,31 @@
 		  num_port = k;
 		else
-		  num_port = _param._link_port_read [i];
-
-		read_select_val [i][num_port] = read_out_ack [i][j] && not read_is_busy [num_port];
-		
-		if ((read_out_ack [i][j] == 0) || find)
-		  read_select_ack [i][num_port] = 0; // read_out is busy or already find
-		else
+		  num_port = k*_param._nb_port_read_by_bank+j;
+
+		read_select_val [i][j][k] = read_out_ack and not read_is_busy [num_port] and (read_in_num_bank[num_port] == i); // select val if port is not busy and out accept a data
+		Tcontrol_t read_select_ack = 0;
+
+		// test a previous find
+		if (not ((read_out_ack == 0) || find))
 		  {
 		    // find a busy port?
-		    find = not read_is_busy [num_port];
-		    read_is_busy       [num_port]|= find;
-		    read_select_ack [i][num_port] = find;
+		    find                      = read_select_val;
+		    read_is_busy   [num_port]|= find; // port became busy if find
+		    read_select_ack           = find; // ack if find
 
 		    if (find)
 		      {
+			read_out_find    [i][j] = true;
+			read_out_port    [i][j] = num_port;
+
+			// know the good output
 			read_in_ack      [num_port] = 1;
 			read_in_data     [num_port] = ((j<<1)|1);
 			read_out_val     [i][j]     = 1;
-			read_out_address [i][j]     = (read_in_num_bank[i] << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i);
+			read_out_address [i][j]     = (i << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & num_port);
 		      }
 		  }
 		
-		READ_SELECT_ACK [i][j][k]->write(read_select_ack [i][num_port]);
+		READ_SELECT_ACK [i][j][k]->write(read_select_ack);
 	      }
 	  }
@@ -352,14 +355,65 @@
       sc_start(1);
 
-//       // lot of test
-//   public    : SC_OUT(Tcontrol_t)           ** out_READ_IN_ACK       ;
-//   public    : SC_OUT(Tdata_t   )           ** out_READ_IN_DATA      ;
-
-//   public    : SC_OUT(Tcontrol_t)         **** out_READ_SELECT_VAL   ;
-
-//   public    : SC_OUT(Tcontrol_t)          *** out_READ_OUT_VAL      ;
-//   public    : SC_OUT(Taddress_t)          *** out_READ_OUT_ADDRESS  ;
+      // test output
+
+      TEXT ("===== Test Output =====");
+      for (uint32_t i=0; i<_param._nb_port_read; i++)
+	{
+	  TEXT ("Read_in         [" << i << "]       : "
+		<< READ_IN_VAL [i]->read() << ","
+		<< read_in_ack [i]         << " - "
+		<< "Reg[" << READ_IN_ADDRESS [i]->read() << "] -> "
+		<< read_in_data [i] << " "
+		<< "{bank : " << read_in_num_bank[i] << "}"
+		);
+
+	  TEST (Tcontrol_t, read_in_ack  [i], READ_IN_ACK  [i]->read());
+	  if (READ_IN_VAL [i]->read() and READ_IN_ACK [i]->read())
+	  TEST (Tdata_t   , read_in_data [i], READ_IN_DATA [i]->read());
+	}
+
+      cout << endl;
+      for (uint32_t i=0; i<_param._nb_bank; i++)
+	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
+	  {
+	    TEXT ("Read_out        [" << i << "][" << j << "]    : "
+		  << read_out_val [i][j]         << ","
+		  << READ_OUT_ACK [i][j]->read() << " - "
+		  << "Reg[" << read_out_address [i][j] << "] -> "
+		  << READ_OUT_DATA [i][j]->read() << " - "
+		  << "[" << read_out_find [i][j]<< " , "
+		  << read_out_port    [i][j] << "]"		  
+		  );
+
+	    TEST (Tcontrol_t, read_out_val     [i][j], READ_OUT_VAL     [i][j]->read());
+	    if (READ_OUT_VAL [i][j]->read() and READ_OUT_ACK [i][j]->read())
+	    TEST (Taddress_t, read_out_address [i][j], READ_OUT_ADDRESS [i][j]->read());
+
+	    for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
+	      {
+		uint32_t num_port; // number of port
+		
+		// compute the good number of port
+		if (_param._crossbar == FULL_CROSSBAR)
+		  num_port = k;
+		else
+		  num_port = k*_param._nb_port_read_by_bank+j;
+		
+		TEXT (" * Read_select  [" << i << "][" << j << "][" << k << "] : "
+		      << read_select_val [i][j][k]         << ","
+		      << READ_SELECT_ACK [i][j][k]->read() << " - "
+		      << "link with read_in[" << num_port << "]"
+		      );
+		
+		TEST (Tcontrol_t, read_select_val  [i][j][k], READ_SELECT_VAL  [i][j][k]->read());
+	      }
+	    
+	    
+	    
+	  }
 
     }
+
+  sc_start(0);
 
   /********************************************************
@@ -367,14 +421,20 @@
    ********************************************************/
 
-  cout << "<" << name << "> ............ Stop Simulation" << endl;
+  TEXT("............ Stop Simulation");
 
   delete CLOCK;
 
+  TEXT("delete read_in");
   for (uint32_t i=0; i<_param._nb_port_read; i++)
     {
+//       TEXT("1, i " << i);
       delete READ_IN_VAL       [i];
+//       TEXT("2");
       delete READ_IN_ACK       [i];
+//       TEXT("3");
       delete READ_IN_ADDRESS   [i];
+//       TEXT("4");
       delete READ_IN_DATA      [i];
+//       TEXT("5");
     }
   						      
@@ -384,4 +444,5 @@
   delete READ_IN_DATA   ;
 
+  TEXT("delete read_select");
    for (uint32_t i=0; i<_param._nb_bank; i++)
      {
@@ -402,4 +463,5 @@
    delete READ_SELECT_ACK;
 
+  TEXT("delete read_out");
    for (uint32_t i=0; i<_param._nb_bank; i++)
      {
@@ -423,4 +485,5 @@
   delete READ_OUT_DATA   ;
 
+  TEXT("delete write_in");
   for (uint32_t i=0; i<_param._nb_port_write; i++)
     {
@@ -436,4 +499,5 @@
   delete WRITE_IN_DATA   ;
 
+  TEXT("delete write_select");
   for (uint32_t i=0; i<_param._nb_bank; i++)
     {
@@ -454,4 +518,5 @@
   delete WRITE_SELECT_ACK;
   
+  TEXT("delete write_out");
   for (uint32_t i=0; i<_param._nb_bank; i++)
     {
@@ -477,4 +542,5 @@
 #endif
 
+
   delete _RegisterFile_Multi_Banked_Glue;
 }
