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  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/src/Parameters.cpp

    r15 r23  
    3131    _nb_port_write_by_bank (nb_port_write_by_bank),
    3232    _crossbar              (crossbar             ),
    33     _shift_address         (static_cast<uint32_t>(ceil(log2(_nb_bank))))
     33    _shift_address         (_size_address-static_cast<uint32_t>(ceil(log2(_nb_bank))))
    3434  {
    3535    log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"Parameters","Begin");
     
    3939        // All port_src is connected with one port_dest on each bank
    4040       
    41         _link_port_read  = new uint32_t [_nb_port_read ];
    42         for (uint32_t i=0; i<_nb_port_read ; i++)
    43           _link_port_read  [i] = i%_nb_port_read_by_bank;
     41        _link_port_read_in_to_out          = new uint32_t [_nb_port_read ];
     42        _link_port_read_in_to_select       = new uint32_t [_nb_port_read ];
     43        _link_port_write_in_to_out         = new uint32_t [_nb_port_write];
     44        _link_port_write_in_to_select      = new uint32_t [_nb_port_write];
     45        uint32_t _nb_port_select_by_bank_read_port  [_nb_port_read_by_bank ];
     46        uint32_t _nb_port_select_by_bank_write_port [_nb_port_write_by_bank];
     47       
     48        // init
     49        for (uint32_t i=0; i<_nb_port_read_by_bank ;i++)
     50          _nb_port_select_by_bank_read_port  [i] = 0;
     51       
     52        for (uint32_t i=0; i<_nb_port_read         ;i++)
     53          {
     54            uint32_t x = i%_nb_port_read_by_bank;
     55            _link_port_read_in_to_out          [i] = x;
     56            _link_port_read_in_to_select       [i] = _nb_port_select_by_bank_read_port [x];
     57            _nb_port_select_by_bank_read_port  [x] ++;
     58          }
    4459
    45         _link_port_write = new uint32_t [_nb_port_write];
    46         for (uint32_t i=0; i<_nb_port_write; i++)
    47           _link_port_write [i] = i%_nb_port_write_by_bank;
     60        // init
     61        for (uint32_t i=0; i<_nb_port_write_by_bank ;i++)
     62          _nb_port_select_by_bank_write_port [i] = 0;
     63       
     64        for (uint32_t i=0; i<_nb_port_write         ;i++)
     65          {
     66            uint32_t x = i%_nb_port_write_by_bank;
     67            _link_port_write_in_to_out         [i] = x;
     68            _link_port_write_in_to_select      [i] = _nb_port_select_by_bank_write_port [x];
     69            _nb_port_select_by_bank_write_port [x] ++;
     70          }
    4871      }
    4972    // else : don't allocate
    5073
    51     _nb_port_select_by_bank_read_port  = new uint32_t [_nb_port_read_by_bank ];
    52    
    53     if (_crossbar == FULL_CROSSBAR)
    54       // All port_src is connected with all port_dest on each bank
    55       for (uint32_t i=0; i<_nb_port_read_by_bank ;i++)
    56         _nb_port_select_by_bank_read_port [i] = _nb_port_read;
    57     else
    58       // All port_src is connected with one port_dest on each bank
    59       {
    60         for (uint32_t i=0; i<_nb_port_read_by_bank ;i++)
    61           _nb_port_select_by_bank_read_port [i] = 0;
    62 
    63         for (uint32_t i=0; i<_nb_port_read         ;i++)
    64           _nb_port_select_by_bank_read_port [_link_port_read [i]] ++;
    65       }
    66    
    67     _nb_port_select_by_bank_write_port = new uint32_t [_nb_port_write_by_bank];
    68 
    69     if (_crossbar == FULL_CROSSBAR)
    70       // All port_src is connected with all port_dest on each bank
    71       for (uint32_t i=0; i<_nb_port_write_by_bank ;i++)
    72         _nb_port_select_by_bank_write_port [i] = _nb_port_write;
    73     else
    74       // All port_src is connected with one port_dest on each bank
    75       {
    76         for (uint32_t i=0; i<_nb_port_write_by_bank ;i++)
    77           _nb_port_select_by_bank_write_port [i] = 0;
    78 
    79         for (uint32_t i=0; i<_nb_port_write         ;i++)
    80           _nb_port_select_by_bank_write_port [_link_port_write[i]] ++;
    81       }
    82    
    8374    test();
    8475    log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"Parameters","End");
     
    9788   {
    9889    log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"Parameters (copy)","Begin");
    99 
    100     _nb_port_select_by_bank_read_port  = new uint32_t [_nb_port_read_by_bank ];
    101     for (uint32_t i=0; i<_nb_port_read_by_bank; i++)
    102       _nb_port_select_by_bank_read_port [i] = param._nb_port_select_by_bank_read_port [i];
    103    
    104     _nb_port_select_by_bank_write_port = new uint32_t [_nb_port_write_by_bank ];
    105     for (uint32_t i=0; i<_nb_port_write_by_bank; i++)
    106       _nb_port_select_by_bank_write_port[i] = param._nb_port_select_by_bank_write_port [i];
    107    
    10890    test();
    10991    log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"Parameters (copy)","End");
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