- Timestamp:
- Jul 5, 2007, 5:50:19 PM (17 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU
- Files:
-
- 1 deleted
- 11 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/configuration.cfg
r15 r42 1 1 Victim_Pseudo_LRU 2 4 4*2 # nb_entity3 1 1 +2 # nb_access4 1 1 +2 # nb_update5 1 1 2 4 16 *2 # nb_entity 3 1 4 *2 # nb_access 4 1 4 *2 # nb_update 5 1 16 *2 # size_table -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Victim_Pseudo_LRU.h
r15 r42 40 40 #include "Behavioural/include/Vhdl.h" 41 41 #endif 42 #ifdef VHDL_TESTBENCH 43 #include "Behavioural/include/Vhdl_Testbench.h" 42 #ifdef POSITION 43 #include "Behavioural/include/Component.h" 44 #else 45 #include "Behavioural/include/Interfaces.h" 44 46 #endif 45 47 … … 175 177 #endif 176 178 177 #ifdef VHDL_TESTBENCH 178 private : Vhdl_Testbench * _vhdl_testbench; 179 #endif 179 #ifdef POSITION 180 private : Component * _component; 181 #endif 182 private : Interfaces * _interfaces; 180 183 181 184 #ifdef SYSTEMC … … 237 240 #if VHDL 238 241 public : void vhdl (void); 239 private : void vhdl_port (Vhdl & vhdl);240 private : void vhdl_declaration (Vhdl & vhdl);241 private : void vhdl_body (Vhdl & vhdl);242 private : void vhdl_port (Vhdl * & vhdl); 243 private : void vhdl_declaration (Vhdl * & vhdl); 244 private : void vhdl_body (Vhdl * & vhdl); 242 245 #endif 243 246 244 247 #ifdef VHDL_TESTBENCH 245 private : void vhdl_testbench (Vhdl_Testbench & vhdl_testbench); 246 private : void vhdl_testbench_port (Vhdl_Testbench & vhdl_testbench); 247 private : void vhdl_testbench_transition (Vhdl_Testbench & vhdl_testbench); 248 private : void vhdl_testbench_transition (void); 248 249 #endif 249 250 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU.cpp
r15 r42 28 28 log_printf(FUNC,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Begin"); 29 29 30 #ifdef SYSTEMC 31 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Allocation"); 32 allocation (); 33 #endif 34 30 35 #ifdef STATISTICS 31 36 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Allocation of statistics"); … … 37 42 #endif 38 43 39 #ifdef VHDL_TESTBENCH40 // Creation of a testbench41 // -> port42 // -> clock's signals43 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Creation of Testbench");44 _vhdl_testbench = new Vhdl_Testbench (_name);45 vhdl_testbench_port (*_vhdl_testbench);46 _vhdl_testbench->set_clock ("in_CLOCK",true);47 #endif48 49 44 #ifdef VHDL 50 45 // generate the vhdl … … 54 49 55 50 #ifdef SYSTEMC 56 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Allocation");57 allocation ();58 59 51 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Definition of sc_method"); 60 52 SC_METHOD (transition); … … 100 92 #endif 101 93 102 #ifdef VHDL_TESTBENCH103 // generate the test bench104 _vhdl_testbench->generate_file();105 delete _vhdl_testbench;106 #endif107 108 94 #ifdef STATISTICS 109 95 _stat->generate_file(statistics(0)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp
r15 r42 17 17 void Victim_Pseudo_LRU::allocation (void) 18 18 { 19 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 20 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET");19 #ifdef POSITION 20 _component = new Component (); 21 21 22 // -----[ Interface access ]------------------------------------------- 23 in_ACCESS_VAL = new SC_IN (Tcontrol_t) * [_param._nb_access]; 24 out_ACCESS_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_access]; 25 if (_param._size_table>1) 26 in_ACCESS_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_access]; 27 out_ACCESS_ENTITY = new SC_OUT(Tentity_t ) * [_param._nb_access]; 22 Entity * entity = _component->set_entity (_name , 23 "Select_Priority_Fixed", 24 COMBINATORY ); 28 25 29 for (uint32_t i=0; i<_param._nb_access; i++) 30 { 31 string rename; 26 _interfaces = entity->set_interfaces(); 27 #else 28 _interfaces = new Interfaces(); 29 #endif 32 30 33 rename = "in_ACCESS_VAL[" + toString(i) + "]"; 34 in_ACCESS_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 31 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 { 33 Interface_fifo * interface = _interfaces->set_interface("", IN ,WEST, "Generalist interface"); 34 35 in_CLOCK = interface->set_signal_clk ("clock" ,1); 36 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1); 37 } 35 38 36 rename = "out_ACCESS_ACK[" + toString(i) + "]"; 37 out_ACCESS_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 39 // ~~~~~[ Interface : "access" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 40 { 41 in_ACCESS_VAL = new SC_IN (Tcontrol_t) * [_param._nb_access]; 42 out_ACCESS_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_access]; 43 if (_param._size_table>1) 44 in_ACCESS_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_access]; 45 out_ACCESS_ENTITY = new SC_OUT(Tentity_t ) * [_param._nb_access]; 46 47 for (uint32_t i=0; i<_param._nb_access; i++) 48 { 49 Interface_fifo * interface = _interfaces->set_interface("access_"+toString(i), IN ,WEST, "Access"); 38 50 39 if (_param._size_table>1)40 {41 rename = "in_ACCESS_ADDRESS[" + toString(i) + "]";42 in_ACCESS_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str());43 }44 rename = "out_ACCESS_ENTITY[" + toString(i) + "]";45 out_ACCESS_ENTITY [i] = new SC_OUT(Tentity_t ) (rename.c_str());46 51 in_ACCESS_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 52 out_ACCESS_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 53 54 if (_param._size_table>1) 55 in_ACCESS_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address",static_cast<uint32_t>(log2(_param._size_table))); 56 out_ACCESS_ENTITY [i] = interface->set_signal_out <Tentity_t> ("entity" ,static_cast<uint32_t>(log2(_param._nb_entity ))); 57 } 58 } 47 59 48 // -----[ Interface update ]------------------------------------------- 49 in_UPDATE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_update]; 50 out_UPDATE_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_update]; 51 if (_param._size_table>1) 52 in_UPDATE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_update]; 53 in_UPDATE_ENTITY = new SC_IN (Tentity_t ) * [_param._nb_update]; 60 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 61 62 { 63 in_UPDATE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_update]; 64 out_UPDATE_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_update]; 65 if (_param._size_table>1) 66 in_UPDATE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_update]; 67 in_UPDATE_ENTITY = new SC_IN (Tentity_t ) * [_param._nb_update]; 68 69 for (uint32_t i=0; i<_param._nb_update; i++) 70 { 71 Interface_fifo * interface = _interfaces->set_interface("update_"+toString(i), IN ,EAST, "Update"); 54 72 55 for (uint32_t i=0; i<_param._nb_update; i++) 56 { 57 string rename; 58 59 rename = "in_UPDATE_VAL[" + toString(i) + "]"; 60 in_UPDATE_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 61 62 rename = "out_UPDATE_ACK[" + toString(i) + "]";; 63 out_UPDATE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 64 65 if (_param._size_table>1) 66 { 67 rename = "in_UPDATE_ADDRESS[" + toString(i) + "]"; 68 in_UPDATE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 69 } 70 71 rename = "in_UPDATE_ENTITY[" + toString(i) + "]"; 72 in_UPDATE_ENTITY [i] = new SC_IN (Tentity_t ) (rename.c_str()); 73 } 74 73 in_UPDATE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 74 out_UPDATE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 75 if (_param._size_table>1) 76 in_UPDATE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address",static_cast<uint32_t>(log2(_param._size_table))); 77 in_UPDATE_ENTITY [i] = interface->set_signal_in <Tentity_t> ("entity" ,static_cast<uint32_t>(log2(_param._nb_entity ))); 78 } 79 } 75 80 // -----[ Register ]--------------------------------------------------- 76 81 reg_TABLE = new entry_t * [_param._size_table]; … … 81 86 // -----[ Internal ]--------------------------------------------------- 82 87 internal_ACCESS_ENTITY = new Tentity_t [_param._nb_entity]; 88 89 #ifdef POSITION 90 _component->generate_file(); 91 #endif 83 92 }; 84 93 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_deallocation.cpp
r15 r42 17 17 void Victim_Pseudo_LRU::deallocation (void) 18 18 { 19 delete in_CLOCK;20 delete in_NRESET;19 delete in_CLOCK; 20 delete in_NRESET; 21 21 // -----[ Interface access ]------------------------------------------- 22 for (uint32_t i=0; i<_param._nb_access; i++) 23 { 24 delete in_ACCESS_VAL [i]; 25 delete out_ACCESS_ACK [i]; 26 if (_param._size_table>1) 27 delete in_ACCESS_ADDRESS [i]; 28 delete out_ACCESS_ENTITY [i]; 29 } 30 31 delete in_ACCESS_VAL ; 32 delete out_ACCESS_ACK ; 22 delete [] in_ACCESS_VAL ; 23 delete [] out_ACCESS_ACK ; 33 24 if (_param._size_table>1) 34 delete in_ACCESS_ADDRESS;35 delete out_ACCESS_ENTITY ;25 delete [] in_ACCESS_ADDRESS; 26 delete [] out_ACCESS_ENTITY ; 36 27 37 28 // -----[ Interface update ]------------------------------------------- 38 for (uint32_t i=0; i<_param._nb_update; i++) 39 { 40 delete in_UPDATE_VAL [i]; 41 delete out_UPDATE_ACK [i]; 42 if (_param._size_table>1) 43 delete in_UPDATE_ADDRESS [i]; 44 delete in_UPDATE_ENTITY [i]; 45 } 46 delete in_UPDATE_VAL ; 47 delete out_UPDATE_ACK ; 29 delete [] in_UPDATE_VAL ; 30 delete [] out_UPDATE_ACK ; 48 31 if (_param._size_table>1) 49 delete in_UPDATE_ADDRESS;50 delete in_UPDATE_ENTITY ;32 delete [] in_UPDATE_ADDRESS; 33 delete [] in_UPDATE_ENTITY ; 51 34 52 35 // -----[ Register ]--------------------------------------------------- 53 for (uint32_t i=0; i<_param._size_table; i++) 54 { 55 delete reg_TABLE [i]; 56 } 57 delete reg_TABLE; 36 delete [] reg_TABLE; 58 37 59 38 // -----[ Internal ]--------------------------------------------------- 60 delete internal_ACCESS_ENTITY; 39 delete [] internal_ACCESS_ENTITY; 40 41 #ifdef POSITION 42 delete _component; 43 #else 44 delete _interfaces; 45 #endif 61 46 }; 62 47 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_transition.cpp
r15 r42 67 67 68 68 #ifdef VHDL_TESTBENCH 69 vhdl_testbench_transition ( *_vhdl_testbench);69 vhdl_testbench_transition (); 70 70 #endif 71 71 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl.cpp
r15 r42 22 22 23 23 log_printf(TRACE,Victim_Pseudo_LRU,"vhdl","Construction of vhdl"); 24 Vhdl vhdl (_name);24 Vhdl * vhdl = new Vhdl (_name); 25 25 26 26 log_printf(TRACE,Victim_Pseudo_LRU,"vhdl","Set library"); 27 vhdl .set_library_work (_name + "_Pack");27 vhdl->set_library_work (_name + "_Pack"); 28 28 29 29 log_printf(TRACE,Victim_Pseudo_LRU,"vhdl","Set port"); … … 34 34 vhdl_body (vhdl); 35 35 log_printf(TRACE,Victim_Pseudo_LRU,"vhdl","Generate File"); 36 vhdl.generate_file(); 36 vhdl->generate_file(); 37 38 delete vhdl; 37 39 log_printf(FUNC,Victim_Pseudo_LRU,"vhdl","End"); 38 40 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_body.cpp
r15 r42 15 15 namespace victim_pseudo_lru { 16 16 17 void Victim_Pseudo_LRU::vhdl_body (Vhdl & vhdl)17 void Victim_Pseudo_LRU::vhdl_body (Vhdl * & vhdl) 18 18 { 19 vhdl .set_body ("");20 vhdl .set_body ("-----------------------------------------------------------------------------");21 vhdl .set_body ("-- Access");22 vhdl .set_body ("-----------------------------------------------------------------------------");23 vhdl .set_body ("");24 vhdl .set_body ("-- Tree of Pseudo-LRU - example to 8 entity");25 vhdl .set_body ("--");26 vhdl .set_body ("-- 4-5-6-7? ");27 vhdl .set_body ("-- 0_______|_______1 ");28 vhdl .set_body ("-- | | ");29 vhdl .set_body ("-- 2-3? 6-7? ");30 vhdl .set_body ("-- 0___|___1 0___|___1 ");31 vhdl .set_body ("-- | | | | ");32 vhdl .set_body ("-- 1? 3? 5? 7? ");33 vhdl .set_body ("-- 0_|_1 0_|_1 0_|_1 0_|_1 ");34 vhdl .set_body ("-- | | | | | | | | ");35 vhdl .set_body ("-- Way Way Way Way Way Way Way Way ");36 vhdl .set_body ("-- 0 1 2 3 4 5 6 7 ");37 for (uint32_t i=0; i<_param._nb_access; i++) 38 { 39 vhdl .set_body ("");19 vhdl->set_body (""); 20 vhdl->set_body ("-----------------------------------------------------------------------------"); 21 vhdl->set_body ("-- Access"); 22 vhdl->set_body ("-----------------------------------------------------------------------------"); 23 vhdl->set_body (""); 24 vhdl->set_body ("-- Tree of Pseudo-LRU - example to 8 entity"); 25 vhdl->set_body ("--"); 26 vhdl->set_body ("-- 4-5-6-7? "); 27 vhdl->set_body ("-- 0_______|_______1 "); 28 vhdl->set_body ("-- | | "); 29 vhdl->set_body ("-- 2-3? 6-7? "); 30 vhdl->set_body ("-- 0___|___1 0___|___1 "); 31 vhdl->set_body ("-- | | | | "); 32 vhdl->set_body ("-- 1? 3? 5? 7? "); 33 vhdl->set_body ("-- 0_|_1 0_|_1 0_|_1 0_|_1 "); 34 vhdl->set_body ("-- | | | | | | | | "); 35 vhdl->set_body ("-- Way Way Way Way Way Way Way Way "); 36 vhdl->set_body ("-- 0 1 2 3 4 5 6 7 "); 37 for (uint32_t i=0; i<_param._nb_access; i++) 38 { 39 vhdl->set_body (""); 40 40 // Read the table 41 41 … … 43 43 44 44 if (_param._size_table>1) 45 access_address = "conv_integer(in_ACCESS_ ADDRESS_"+toString(i)+")";45 access_address = "conv_integer(in_ACCESS_"+toString(i)+"_ADDRESS)"; 46 46 else 47 47 access_address = "0"; 48 48 49 vhdl .set_body ("access_entry_"+toString(i)+" <= reg_TABLE ("+access_address+");");50 vhdl .set_body ("");49 vhdl->set_body ("access_entry_"+toString(i)+" <= reg_TABLE ("+access_address+");"); 50 vhdl->set_body (""); 51 51 52 52 for (int32_t j=static_cast<uint32_t>(log2(_param._nb_entity)-1); j>=0; j--) 53 53 { 54 vhdl .set_body ("access_entity_"+toString(i)+"("+toString(j)+") <= ");54 vhdl->set_body ("access_entity_"+toString(i)+"("+toString(j)+") <= "); 55 55 56 56 uint32_t cpt=0; … … 72 72 string print_else = (k==(1<<j)-1)?" ":"else "; 73 73 74 vhdl .set_body ("\t"+print_else+"access_entry_"+toString(i)+"("+toString(k)+") "+cond);74 vhdl->set_body ("\t"+print_else+"access_entry_"+toString(i)+"("+toString(k)+") "+cond); 75 75 cpt ++; 76 76 } 77 vhdl .set_body ("\t;");77 vhdl->set_body ("\t;"); 78 78 } 79 79 } 80 80 81 vhdl .set_body ("");82 vhdl .set_body ("-----------------------------------------------------------------------------");83 vhdl .set_body ("-- Update");84 vhdl .set_body ("-----------------------------------------------------------------------------");85 vhdl .set_body ("");86 vhdl .set_body ("-- port access");81 vhdl->set_body (""); 82 vhdl->set_body ("-----------------------------------------------------------------------------"); 83 vhdl->set_body ("-- Update"); 84 vhdl->set_body ("-----------------------------------------------------------------------------"); 85 vhdl->set_body (""); 86 vhdl->set_body ("-- port access"); 87 87 for (uint32_t i=0; i<_param._nb_access; i++) 88 88 for (int32_t j=static_cast<uint32_t>(log2(_param._nb_entity)-1); j>=0; j--) … … 107 107 } 108 108 109 vhdl .set_body ("access_next_entry_"+toString(i)+"("+toString(k)+") <=");110 vhdl .set_body ("\tnot access_entity_"+toString(i)+"("+toString(j)+") "+cond);109 vhdl->set_body ("access_next_entry_"+toString(i)+"("+toString(k)+") <="); 110 vhdl->set_body ("\tnot access_entity_"+toString(i)+"("+toString(j)+") "+cond); 111 111 if (have_cond == true) 112 vhdl .set_body ("\telse access_entry_"+toString(i)+"("+toString(k)+")");113 vhdl .set_body ("\t;");112 vhdl->set_body ("\telse access_entry_"+toString(i)+"("+toString(k)+")"); 113 vhdl->set_body ("\t;"); 114 114 cpt ++; 115 115 } 116 116 } 117 117 118 vhdl .set_body ("");119 vhdl .set_body ("-- port update");118 vhdl->set_body (""); 119 vhdl->set_body ("-- port update"); 120 120 for (uint32_t i=0; i<_param._nb_update; i++) 121 121 for (int32_t j=static_cast<uint32_t>(log2(_param._nb_entity)-1); j>=0; j--) … … 137 137 else 138 138 cond += " and"; 139 cond += " in_UPDATE_ ENTITY_"+toString(i)+"("+toString(l)+")='"+toString((cpt>>(l-(j+1)))&1)+"'";139 cond += " in_UPDATE_"+toString(i)+"_ENTITY("+toString(l)+")='"+toString((cpt>>(l-(j+1)))&1)+"'"; 140 140 } 141 141 142 vhdl .set_body ("update_next_entry_"+toString(i)+"("+toString(k)+") <=");143 vhdl .set_body ("\tnot in_UPDATE_ENTITY_"+toString(i)+"("+toString(j)+") "+cond);142 vhdl->set_body ("update_next_entry_"+toString(i)+"("+toString(k)+") <="); 143 vhdl->set_body ("\tnot in_UPDATE_"+toString(i)+"_ENTITY("+toString(j)+") "+cond); 144 144 if (have_cond == true) 145 145 { … … 147 147 148 148 if (_param._size_table>1) 149 update_address = "conv_integer(in_UPDATE_ ADDRESS_"+toString(i)+")";149 update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)"; 150 150 else 151 151 update_address = "0"; 152 152 153 vhdl .set_body ("\telse reg_TABLE ("+update_address+")("+toString(k)+")");153 vhdl->set_body ("\telse reg_TABLE ("+update_address+")("+toString(k)+")"); 154 154 } 155 vhdl .set_body ("\t;");155 vhdl->set_body ("\t;"); 156 156 cpt ++; 157 157 } 158 158 } 159 159 160 vhdl .set_body ("");161 vhdl .set_body ("-----------------------------------------------------------------------------");162 vhdl .set_body ("-- Transition");163 vhdl .set_body ("-----------------------------------------------------------------------------");164 vhdl .set_body ("");165 166 vhdl .set_body ("reg_TABLE_write: process (in_CLOCK)");167 vhdl .set_body ("begin");168 vhdl .set_body ("\tif in_CLOCK'event and in_CLOCK = '1' then");169 vhdl .set_body ("\t\t-- Access port");160 vhdl->set_body (""); 161 vhdl->set_body ("-----------------------------------------------------------------------------"); 162 vhdl->set_body ("-- Transition"); 163 vhdl->set_body ("-----------------------------------------------------------------------------"); 164 vhdl->set_body (""); 165 166 vhdl->set_body ("reg_TABLE_write: process (in_CLOCK)"); 167 vhdl->set_body ("begin"); 168 vhdl->set_body ("\tif in_CLOCK'event and in_CLOCK = '1' then"); 169 vhdl->set_body ("\t\t-- Access port"); 170 170 for (uint32_t i=0; i<_param._nb_access; i++) 171 171 { … … 173 173 174 174 if (_param._size_table>1) 175 access_address = "conv_integer(in_ACCESS_ ADDRESS_"+toString(i)+")";175 access_address = "conv_integer(in_ACCESS_"+toString(i)+"_ADDRESS)"; 176 176 else 177 177 access_address = "0"; 178 178 179 vhdl .set_body ("\t\tif (in_ACCESS_VAL_"+toString(i)+"= '1') then");180 vhdl .set_body ("\t\t\treg_TABLE ("+access_address+") <= access_next_entry_"+toString(i)+";");181 vhdl .set_body ("\t\tend if;");182 } 183 184 vhdl .set_body ("\t\t-- Update port");179 vhdl->set_body ("\t\tif (in_ACCESS_"+toString(i)+"_VAL = '1') then"); 180 vhdl->set_body ("\t\t\treg_TABLE ("+access_address+") <= access_next_entry_"+toString(i)+";"); 181 vhdl->set_body ("\t\tend if;"); 182 } 183 184 vhdl->set_body ("\t\t-- Update port"); 185 185 for (uint32_t i=0; i<_param._nb_update; i++) 186 186 { … … 188 188 189 189 if (_param._size_table>1) 190 update_address = "conv_integer(in_UPDATE_ ADDRESS_"+toString(i)+")";190 update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)"; 191 191 else 192 192 update_address = "0"; 193 193 194 vhdl .set_body ("\t\tif (in_UPDATE_VAL_"+toString(i)+"= '1') then");195 vhdl .set_body ("\t\t\treg_TABLE ("+update_address+") <= update_next_entry_"+toString(i)+";");196 vhdl .set_body ("\t\tend if;");197 } 198 199 vhdl .set_body ("\tend if;");200 vhdl .set_body ("end process reg_TABLE_write;");201 202 vhdl .set_body ("");203 vhdl .set_body ("-----------------------------------------------------------------------------");204 vhdl .set_body ("-- Output");205 vhdl .set_body ("-----------------------------------------------------------------------------");206 vhdl .set_body ("");207 vhdl .set_body ("-- Ack is always ");208 vhdl .set_body ("");209 for (uint32_t i=0; i<_param._nb_access; i++) 210 { 211 vhdl .set_body ("out_ACCESS_ACK_"+toString(i)+"<= '1';");212 vhdl .set_body ("out_ACCESS_ENTITY_"+toString(i)+" <= access_entity_"+toString(i)+" when in_ACCESS_VAL_"+toString(i)+"= '1' else (others => '0');");213 } 214 vhdl .set_body ("");194 vhdl->set_body ("\t\tif (in_UPDATE_"+toString(i)+"_VAL = '1') then"); 195 vhdl->set_body ("\t\t\treg_TABLE ("+update_address+") <= update_next_entry_"+toString(i)+";"); 196 vhdl->set_body ("\t\tend if;"); 197 } 198 199 vhdl->set_body ("\tend if;"); 200 vhdl->set_body ("end process reg_TABLE_write;"); 201 202 vhdl->set_body (""); 203 vhdl->set_body ("-----------------------------------------------------------------------------"); 204 vhdl->set_body ("-- Output"); 205 vhdl->set_body ("-----------------------------------------------------------------------------"); 206 vhdl->set_body (""); 207 vhdl->set_body ("-- Ack is always "); 208 vhdl->set_body (""); 209 for (uint32_t i=0; i<_param._nb_access; i++) 210 { 211 vhdl->set_body ("out_ACCESS_"+toString(i)+"_ACK <= '1';"); 212 vhdl->set_body ("out_ACCESS_"+toString(i)+"_ENTITY <= access_entity_"+toString(i)+" when in_ACCESS_"+toString(i)+"_VAL = '1' else (others => '0');"); 213 } 214 vhdl->set_body (""); 215 215 for (uint32_t i=0; i<_param._nb_update; i++) 216 216 { 217 vhdl .set_body ("out_UPDATE_ACK_"+toString(i)+"<= '1';");217 vhdl->set_body ("out_UPDATE_"+toString(i)+"_ACK <= '1';"); 218 218 } 219 219 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_declaration.cpp
r15 r42 16 16 17 17 18 void Victim_Pseudo_LRU::vhdl_declaration (Vhdl & vhdl)18 void Victim_Pseudo_LRU::vhdl_declaration (Vhdl * & vhdl) 19 19 { 20 vhdl .set_type ("Ttable", "array (" + toString(_param._size_table-1) + " downto 0) of "+std_logic(_param._nb_entity-1));20 vhdl->set_type ("Ttable", "array (" + toString(_param._size_table-1) + " downto 0) of "+std_logic(_param._nb_entity-1)); 21 21 22 22 23 vhdl .set_signal ("reg_TABLE", "Ttable");23 vhdl->set_signal ("reg_TABLE", "Ttable"); 24 24 for (uint32_t i=0; i<_param._nb_access; i++) 25 25 { 26 vhdl .set_signal ("access_entry_"+toString(i)+" ",std_logic(_param._nb_entity-1));27 vhdl .set_signal ("access_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1));28 vhdl .set_signal ("access_entity_"+toString(i)+" ",std_logic(static_cast<uint32_t>(log2(_param._nb_entity))));26 vhdl->set_signal ("access_entry_"+toString(i)+" ",std_logic(_param._nb_entity-1)); 27 vhdl->set_signal ("access_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1)); 28 vhdl->set_signal ("access_entity_"+toString(i)+" ",std_logic(static_cast<uint32_t>(log2(_param._nb_entity)))); 29 29 } 30 30 31 31 for (uint32_t i=0; i<_param._nb_update; i++) 32 32 { 33 vhdl .set_signal ("update_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1));33 vhdl->set_signal ("update_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1)); 34 34 } 35 35 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_port.cpp
r15 r42 16 16 17 17 18 void Victim_Pseudo_LRU::vhdl_port (Vhdl & vhdl)18 void Victim_Pseudo_LRU::vhdl_port (Vhdl * & vhdl) 19 19 { 20 vhdl.set_port ("in_CLOCK ", IN, 1); 21 vhdl.set_port ("in_NRESET", IN, 1); 22 23 for (uint32_t i = 0; i < _param._nb_access; i ++) 24 { 25 vhdl.set_port (" in_ACCESS_VAL_"+toString(i)+" ",IN ,std_logic(1)); 26 vhdl.set_port ("out_ACCESS_ACK_"+toString(i)+" ",OUT,std_logic(1)); 27 if (_param._size_table>1) 28 vhdl.set_port (" in_ACCESS_ADDRESS_"+toString(i)+" ",IN ,std_logic(static_cast<uint32_t>(log2(_param._size_table)))); 29 vhdl.set_port ("out_ACCESS_ENTITY_"+toString(i)+" ",OUT,std_logic(static_cast<uint32_t>(log2(_param._nb_entity)))); 30 } 31 32 for (uint32_t i = 0; i < _param._nb_update; i ++) 33 { 34 vhdl.set_port (" in_UPDATE_VAL_"+toString(i)+" ",IN ,std_logic(1)); 35 vhdl.set_port ("out_UPDATE_ACK_"+toString(i)+" ",OUT,std_logic(1)); 36 if (_param._size_table>1) 37 vhdl.set_port (" in_UPDATE_ADDRESS_"+toString(i)+" ",IN ,std_logic(static_cast<uint32_t>(log2(_param._size_table)))); 38 vhdl.set_port (" in_UPDATE_ENTITY_"+toString(i)+" ",IN ,std_logic(static_cast<uint32_t>(log2(_param._nb_entity)))); 39 } 20 _interfaces->set_port(vhdl); 40 21 }; 41 22 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_testbench_transition.cpp
r15 r42 16 16 17 17 18 void Victim_Pseudo_LRU::vhdl_testbench_transition ( Vhdl_Testbench & vhdl_testbench)18 void Victim_Pseudo_LRU::vhdl_testbench_transition (void) 19 19 { 20 #ifndef SYSTEMCASS_SPECIFIC 21 sc_cycle(0); 22 #endif 23 vhdl_testbench.add_input (PORT_READ(in_NRESET)); 20 // Evaluation before read the ouput signal 21 sc_start(0); 24 22 25 for (uint32_t i = 0; i < _param._nb_access; i ++) 26 { 27 vhdl_testbench.add_input (PORT_READ( in_ACCESS_VAL [i])); 28 vhdl_testbench.add_output (PORT_READ(out_ACCESS_ACK [i])); 29 if (_param._size_table>1) 30 vhdl_testbench.add_input (PORT_READ( in_ACCESS_ADDRESS [i])); 31 vhdl_testbench.add_output (PORT_READ(out_ACCESS_ENTITY [i])); 32 } 33 34 for (uint32_t i = 0; i < _param._nb_update; i ++) 35 { 36 vhdl_testbench.add_input (PORT_READ( in_UPDATE_VAL [i])); 37 vhdl_testbench.add_output (PORT_READ(out_UPDATE_ACK [i])); 38 if (_param._size_table>1) 39 vhdl_testbench.add_input (PORT_READ( in_UPDATE_ADDRESS [i])); 40 vhdl_testbench.add_input (PORT_READ( in_UPDATE_ENTITY [i])); 41 } 42 43 vhdl_testbench.add_test(true); 44 45 vhdl_testbench.new_cycle (); // always at the end 23 _interfaces->testbench(); 46 24 }; 47 25
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