Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h	(revision 41)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h	(revision 42)
@@ -44,5 +44,7 @@
 		PORT_VHDL_NO_TESTBENCH_NO  ,
 		CLOCK_VHDL_YES             ,
-		CLOCK_VHDL_NO              } presence_port_t;
+		CLOCK_VHDL_NO              ,
+		RESET_VHDL_YES             ,
+		RESET_VHDL_NO              } presence_port_t;
 
   class Signal
@@ -56,8 +58,12 @@
   private   : const presence_port_t _presence_port;
 
+  private   : Signal *              _signal       ;
+  private   : bool                  _is_allocate  ;
+  private   : void *                _sc_signal    ;
+  private   : bool                  _is_map       ;
+  private   : void *                _sc_signal_map;
+  private   : type_info_t           _type_info    ;
+
 #ifdef VHDL_TESTBENCH
-  private   : void *                _signal       ;
-  private   : type_info_t           _type_info    ;
-
   private   : list<string>        * _list_value   ;
 #endif
@@ -71,5 +77,15 @@
   public    :                   ~Signal         ();
 
-#ifdef VHDL_TESTBENCH
+  public    : string            get_name        (void);
+  public    : uint32_t          get_size        (void);
+  public    : Signal *          get_signal_link (void);
+
+  public    : bool              presence_vhdl      (void);
+  public    : bool              presence_testbench (void);
+
+  public    : void              mapping         (Signal * signal);
+  public    : void              link            (Signal * signal);
+
+#ifdef SYSTEMC         
   public    :template <typename T>
              T                  read (void)
@@ -88,9 +104,9 @@
       switch (_type_info)
 	{
-	case BOOL     : return (static_cast<sc_in  <bool    > *>(_signal)->read()); 
-	case UINT8_T  : return (static_cast<sc_in  <uint8_t > *>(_signal)->read()); 
-	case UINT16_T : return (static_cast<sc_in  <uint16_t> *>(_signal)->read());
-	case UINT32_T : return (static_cast<sc_in  <uint32_t> *>(_signal)->read()); 
-	case UINT64_T : return (static_cast<sc_in  <uint64_t> *>(_signal)->read()); 
+	case BOOL     : return (static_cast<sc_in  <bool    > *>(_sc_signal_map)->read()); 
+	case UINT8_T  : return (static_cast<sc_in  <uint8_t > *>(_sc_signal_map)->read()); 
+	case UINT16_T : return (static_cast<sc_in  <uint16_t> *>(_sc_signal_map)->read());
+	case UINT32_T : return (static_cast<sc_in  <uint32_t> *>(_sc_signal_map)->read()); 
+	case UINT64_T : return (static_cast<sc_in  <uint64_t> *>(_sc_signal_map)->read()); 
 	default       : throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow."));
 	}
@@ -102,9 +118,9 @@
       switch (_type_info)
 	{
-	case BOOL     : return (static_cast<sc_out <bool    > *>(_signal)->read()); 
-	case UINT8_T  : return (static_cast<sc_out <uint8_t > *>(_signal)->read()); 
-	case UINT16_T : return (static_cast<sc_out <uint16_t> *>(_signal)->read());
-	case UINT32_T : return (static_cast<sc_out <uint32_t> *>(_signal)->read()); 
-	case UINT64_T : return (static_cast<sc_out <uint64_t> *>(_signal)->read()); 
+	case BOOL     : return (static_cast<sc_out <bool    > *>(_sc_signal_map)->read()); 
+	case UINT8_T  : return (static_cast<sc_out <uint8_t > *>(_sc_signal_map)->read()); 
+	case UINT16_T : return (static_cast<sc_out <uint16_t> *>(_sc_signal_map)->read());
+	case UINT32_T : return (static_cast<sc_out <uint32_t> *>(_sc_signal_map)->read()); 
+	case UINT64_T : return (static_cast<sc_out <uint64_t> *>(_sc_signal_map)->read()); 
 	default       : throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow."));
 	}
@@ -117,5 +133,7 @@
 	throw (ErrorMorpheo ("Signal \""+_name+"\" : already allocate."));
 
-      _signal    = port;
+      _is_allocate = true;
+      _sc_signal      = port;
+      _sc_signal_map  = port;
 
       if (typeid(T) == typeid(bool    ))
@@ -136,16 +154,21 @@
 	_type_info = UNKNOW;
     }
-
-  public    : void              testbench        (void);
-  public    : void              testbench_body   (Vhdl           * & vhdl          ,
-						  string             counter_name  );
-  public    : void              testbench_test_ok(Vhdl           * & vhdl          );
-#endif
+#endif
+
 #ifdef VHDL
   public    : void              set_port        (Vhdl * & vhdl);
 #  ifdef VHDL_TESTBENCH
-  public    : string            get_clock       (void);
+  public    : Signal *          get_clock       (void);
+  public    : Signal *          get_reset       (void);
+  public    : uint32_t          get_reset_cycle (bool active_low);
+
   public    : void              set_signal      (Vhdl * & vhdl);
   public    : void              get_name_vhdl   (list<string> * & list_signal);
+
+  public    : void              testbench        (void);
+  public    : void              testbench_body   (Vhdl           * & vhdl          ,
+						  string             counter_name  ,
+						  string             reset_name    );
+  public    : void              testbench_test_ok(Vhdl           * & vhdl          );
 #  endif
 #endif
@@ -162,8 +185,12 @@
     switch (x)
       {
-      case morpheo::behavioural::PORT_VHDL_YES_TESTBENCH_YES : return "Port is in VHDL's model and TestBench's model" ; break;
-      case morpheo::behavioural::PORT_VHDL_YES_TESTBENCH_NO  : return "Port is in VHDL's model                      " ; break;
-      case morpheo::behavioural::PORT_VHDL_NO_TESTBENCH_YES  : return "Port is in                  TestBench's model" ; break;
-      case morpheo::behavioural::PORT_VHDL_NO_TESTBENCH_NO   : return "Port is in none model                        " ; break;
+      case morpheo::behavioural::PORT_VHDL_YES_TESTBENCH_YES : return "Port  is in VHDL's model and TestBench's model" ; break;
+      case morpheo::behavioural::PORT_VHDL_YES_TESTBENCH_NO  : return "Port  is in VHDL's model                      " ; break;
+      case morpheo::behavioural::PORT_VHDL_NO_TESTBENCH_YES  : return "Port  is in                  TestBench's model" ; break;
+      case morpheo::behavioural::PORT_VHDL_NO_TESTBENCH_NO   : return "Port  is in none model                        " ; break;
+      case morpheo::behavioural::CLOCK_VHDL_YES              : return "Clock is in VHDL's model                     " ; break;
+      case morpheo::behavioural::CLOCK_VHDL_NO               : return "Clock is not in VHDL's model                 " ; break;
+      case morpheo::behavioural::RESET_VHDL_YES              : return "Reset is in VHDL's model                     " ; break;
+      case morpheo::behavioural::RESET_VHDL_NO               : return "Reset is not in VHDL's model                 " ; break;
       default                                                : return "";                                               break;
       }
