Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_testbench_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_testbench_transition.cpp	(revision 5)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_testbench_transition.cpp	(revision 44)
@@ -21,84 +21,6 @@
     log_printf(FUNC,Meta_Predictor_Glue,"vhdl_testbench_transition","Begin");
 
-    // Evaluation before read the ouput signal
-    sc_start(0);
-
-    // In order with file Meta_Predictor_Glue_vhdl_testbench_port.cpp
-    // Warning : if a output depend of a subcomponent, take directly the port of subcomponent
-    // (because we have no control on the ordonnancer's policy)
-
-    for (uint32_t i=0; i<_param._nb_prediction; i++)
-      {
-	if (_param._have_meta_predictor)
-	  {
-	_vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_0_ACK [i]));
-	_vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_1_ACK [i]));
-	  }
-	_vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_2_ACK [i]));
-	_vhdl_testbench->add_output(PORT_READ(out_PREDICT_ACK [i]));
-
-	if (_param._have_meta_predictor)
-	  {
-	if (_param._predictor_0_have_bht)
-	_vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_0_BHT_HISTORY [i]));
-	if (_param._predictor_0_have_pht)
-	_vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_0_PHT_HISTORY [i]));
-	if (_param._predictor_1_have_bht)
-	_vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_1_BHT_HISTORY [i]));
-	if (_param._predictor_1_have_pht)
-	_vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_1_PHT_HISTORY [i]));
-	  }
-	if (_param._predictor_2_have_bht)
-	_vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_2_BHT_HISTORY [i]));
-	if (_param._predictor_2_have_pht)
-	_vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_2_PHT_HISTORY [i]));
-
-	_vhdl_testbench->add_output(PORT_READ(out_PREDICT_HISTORY [i]));
-	_vhdl_testbench->add_output(PORT_READ(out_PREDICT_DIRECTION [i]));
-      }
-
-    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
-      {
-	if (_param._have_meta_predictor)
-	  {
-	_vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL             [i]));
-	_vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_2_VAL [i]));
-
-	_vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PREDICTOR_0_ACK [i]));
-	_vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PREDICTOR_1_ACK [i]));
-	  }
-	_vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PREDICTOR_2_ACK [i]));
-	_vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_ACK [i]));
-
-	if (_param._have_meta_predictor)
-	  {
-	if (_param._predictor_0_have_bht)
-	_vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY [i]));
-	if (_param._predictor_0_have_pht)
-	_vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY [i]));
-	if (_param._predictor_1_have_bht)
-	_vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY [i]));
-	if (_param._predictor_1_have_pht)
-	_vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY [i]));
-	  }
-	if (_param._predictor_2_have_bht)
-	_vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY [i]));
-	if (_param._predictor_2_have_pht)
-	_vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY [i]));
-
-	_vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_HISTORY   [i]));
-	if (_param._have_meta_predictor)
-	  {
-	_vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_DIRECTION [i]));
-	_vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION [i]));
-	  }
-      }
-    
-    // add_test :
-    //  - True  : the cycle must be compare with the output of systemC
-    //  - False : no test
-    _vhdl_testbench->add_test(true);
-
-    _vhdl_testbench->new_cycle (); // always at the end
+//  sc_start(0);
+    _interfaces->testbench();
 
     log_printf(FUNC,Meta_Predictor_Glue,"vhdl_testbench_transition","End");
