Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Makefile (revision 45) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = . +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libMeta_Predictor.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Makefile.defs (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Makefile.defs (revision 45) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Makefile.deps (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Makefile.deps (revision 45) @@ -0,0 +1,45 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Two_Level_Branch_Predictor +include $(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Makefile.deps +endif +ifndef Meta_Predictor_Glue +include $(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/Makefile.deps +endif + +Meta_Predictor = yes + +#-----[ Library ]------------------------------------------ +Meta_Predictor_LIBRARY = -lMeta_Predictor \ + $(Meta_Predictor_Glue_LIBRARY) \ + $(Two_Level_Branch_Predictor_LIBRARY) \ + $(Behavioural_LIBRARY) + +Meta_Predictor_DIR_LIBRARY = -L$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/lib \ + $(Meta_Predictor_Glue_DIR_LIBRARY) \ + $(Two_Level_Branch_Predictor_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Meta_Predictor_library : + @$(MAKE) Behavioural_library + @$(MAKE) Meta_Predictor_Glue_library + @$(MAKE) Two_Level_Branch_Predictor_library + @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor --makefile=Makefile + +Meta_Predictor_library_clean : + @$(MAKE) Behavioural_library_clean + @$(MAKE) Meta_Predictor_Glue_library_clean + @$(MAKE) Two_Level_Branch_Predictor_library_clean + @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor --makefile=Makefile clean Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/Makefile (revision 45) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = . +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libMeta_Predictor_Glue.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/Makefile.defs (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/Makefile.defs (revision 45) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/Makefile.deps (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/Makefile.deps (revision 45) @@ -0,0 +1,31 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif + +Meta_Predictor_Glue = yes + +#-----[ Library ]------------------------------------------ +Meta_Predictor_Glue_LIBRARY = -lMeta_Predictor_Glue \ + $(Behavioural_LIBRARY) + +Meta_Predictor_Glue_DIR_LIBRARY = -L$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/lib \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Meta_Predictor_Glue_library : + @$(MAKE) Behavioural_library + @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue --makefile=Makefile + +Meta_Predictor_Glue_library_clean : + @$(MAKE) Behavioural_library_clean + @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue --makefile=Makefile clean Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/Makefile (revision 45) @@ -0,0 +1,29 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_MORPHEO = ../../../../../.. + +LIBRARY = $(Meta_Predictor_Glue_LIBRARY) + +DIR_LIBRARY = $(Meta_Predictor_Glue_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Meta_Predictor_Glue_library + +library_clean : Meta_Predictor_Glue_library_clean + +include ../Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/config0.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/config0.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/config0.cfg (revision 45) @@ -0,0 +1,16 @@ +Meta_Predictor_Glue +0 1 +1 # have_meta_predictor +0 1 +1 # predictor_0_have_bht +4 4 +1 # predictor_0_bht_size_shifter +1 1 +1 # predictor_0_have_pht +2 2 +1 # predictor_0_pht_size_counter +1 1 +1 # predictor_1_have_bht +3 3 +1 # predictor_1_bht_size_shifter +0 1 +1 # predictor_1_have_pht +4 4 +1 # predictor_1_pht_size_counter +1 1 +1 # predictor_2_have_bht +2 2 +1 # predictor_2_bht_size_shifter +0 1 +1 # predictor_2_have_pht +4 4 +1 # predictor_2_pht_size_counter +2 2 +1 # nb_prediction +2 2 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/config1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/config1.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/config1.cfg (revision 45) @@ -0,0 +1,16 @@ +Meta_Predictor_Glue +0 1 +1 # have_meta_predictor +1 1 +1 # predictor_0_have_bht +4 4 +1 # predictor_0_bht_size_shifter +0 1 +1 # predictor_0_have_pht +2 2 +1 # predictor_0_pht_size_counter +0 1 +1 # predictor_1_have_bht +3 3 +1 # predictor_1_bht_size_shifter +1 1 +1 # predictor_1_have_pht +4 4 +1 # predictor_1_pht_size_counter +0 1 +1 # predictor_2_have_bht +2 2 +1 # predictor_2_bht_size_shifter +1 1 +1 # predictor_2_have_pht +4 4 +1 # predictor_2_pht_size_counter +2 2 +1 # nb_prediction +2 2 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/configuration.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/configuration.cfg (revision 45) @@ -0,0 +1,16 @@ +Meta_Predictor_Glue +0 1 +1 # have_meta_predictor +0 1 +1 # predictor_0_have_bht +4 4 +1 # predictor_0_bht_size_shifter +1 1 +1 # predictor_0_have_pht +2 2 +1 # predictor_0_pht_size_counter +1 1 +1 # predictor_1_have_bht +3 3 +1 # predictor_1_bht_size_shifter +0 1 +1 # predictor_1_have_pht +4 4 +1 # predictor_1_pht_size_counter +1 1 +1 # predictor_2_have_bht +2 2 +1 # predictor_2_bht_size_shifter +0 1 +1 # predictor_2_have_pht +4 4 +1 # predictor_2_pht_size_counter +1 1 +1 # nb_prediction +1 1 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/include/test.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/include/test.h (revision 45) @@ -0,0 +1,28 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include +#include + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::stage_1_ifetch; +using namespace morpheo::behavioural::stage_1_ifetch::predictor; +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor; + +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::meta_predictor_glue; + +void test (string name, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::meta_predictor_glue::Parameters param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/src/main.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/src/main.cpp (revision 45) @@ -0,0 +1,104 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/SelfTest/include/test.h" + +#define NB_PARAMS 15 + +void usage (string exec) +{ + cerr << " " << exec << " name_instance list_params" << endl + << "list_params is :" << endl + << " - have_meta_predictor (bool )" << endl + << " - predictor_0_have_bht (bool )" << endl + << " - predictor_0_bht_size_shifter (uint32_t)" << endl + << " - predictor_0_have_pht (bool )" << endl + << " - predictor_0_pht_size_counter (uint32_t)" << endl + << " - predictor_1_have_bht (bool )" << endl + << " - predictor_1_bht_size_shifter (uint32_t)" << endl + << " - predictor_1_have_pht (bool )" << endl + << " - predictor_1_pht_size_counter (uint32_t)" << endl + << " - predictor_2_have_bht (bool )" << endl + << " - predictor_2_bht_size_shifter (uint32_t)" << endl + << " - predictor_2_have_pht (bool )" << endl + << " - predictor_2_pht_size_counter (uint32_t)" << endl + << " - nb_prediction (uint32_t)" << endl + << " - nb_branch_complete (uint32_t)" << endl; + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc != 2+NB_PARAMS) + usage (argv[0]); + + const string name = argv[1]; + + const bool have_meta_predictor = atoi(argv[ 2]); + + const bool predictor_0_have_bht = atoi(argv[ 3]); + const uint32_t predictor_0_bht_size_shifter = atoi(argv[ 4]); + const bool predictor_0_have_pht = atoi(argv[ 5]); + const uint32_t predictor_0_pht_size_counter = atoi(argv[ 6]); + + const bool predictor_1_have_bht = atoi(argv[ 7]); + const uint32_t predictor_1_bht_size_shifter = atoi(argv[ 8]); + const bool predictor_1_have_pht = atoi(argv[ 9]); + const uint32_t predictor_1_pht_size_counter = atoi(argv[10]); + + const bool predictor_2_have_bht = atoi(argv[11]); + const uint32_t predictor_2_bht_size_shifter = atoi(argv[12]); + const bool predictor_2_have_pht = atoi(argv[13]); + const uint32_t predictor_2_pht_size_counter = atoi(argv[14]); + + const uint32_t nb_prediction = atoi(argv[15]); + const uint32_t nb_branch_complete = atoi(argv[16]); + + try + { + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::meta_predictor_glue::Parameters param (have_meta_predictor , + predictor_0_have_bht , + predictor_0_bht_size_shifter , + predictor_0_have_pht , + predictor_0_pht_size_counter , + + predictor_1_have_bht , + predictor_1_bht_size_shifter , + predictor_1_have_pht , + predictor_1_pht_size_counter , + + predictor_2_have_bht , + predictor_2_bht_size_shifter , + predictor_2_have_pht , + predictor_2_pht_size_counter , + + nb_prediction , + nb_branch_complete ); + + cout << param.print(1); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + cout << "<" << name << "> : " << error.what (); + exit (EXIT_FAILURE); + } + catch (...) + { + cerr << "<" << name << "> : This test must generate a error" << endl; + exit (EXIT_FAILURE); + } + + return (EXIT_SUCCESS); +} + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/src/test.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/SelfTest/src/test.cpp (revision 45) @@ -0,0 +1,486 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#define NB_ITERATION 1024 + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/SelfTest/include/test.h" +#include "Common/include/Test.h" + +void test (string name, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::meta_predictor_glue::Parameters _param) +{ + cout << "<" << name << "> : Simulation SystemC" << endl; + + Meta_Predictor_Glue * _Meta_Predictor_Glue = new Meta_Predictor_Glue (name.c_str(), +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics(5,50), +#endif + _param); + +#ifdef SYSTEMC + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + sc_clock * CLOCK; + sc_signal * NRESET; + + // Interface Predict + sc_signal ** PREDICT_PREDICTOR_0_ACK ; + sc_signal ** PREDICT_PREDICTOR_1_ACK ; + sc_signal ** PREDICT_PREDICTOR_2_ACK ; + sc_signal ** PREDICT_ACK ; + + sc_signal ** PREDICT_PREDICTOR_0_BHT_HISTORY ; + sc_signal ** PREDICT_PREDICTOR_0_PHT_HISTORY ; + sc_signal ** PREDICT_PREDICTOR_1_BHT_HISTORY ; + sc_signal ** PREDICT_PREDICTOR_1_PHT_HISTORY ; + sc_signal ** PREDICT_PREDICTOR_2_BHT_HISTORY ; + sc_signal ** PREDICT_PREDICTOR_2_PHT_HISTORY ; + sc_signal ** PREDICT_HISTORY ; + sc_signal ** PREDICT_DIRECTION ; + + // Interface Branch_complete + sc_signal ** BRANCH_COMPLETE_VAL ; + sc_signal ** BRANCH_COMPLETE_PREDICTOR_2_VAL ; + + sc_signal ** BRANCH_COMPLETE_PREDICTOR_0_ACK ; + sc_signal ** BRANCH_COMPLETE_PREDICTOR_1_ACK ; + sc_signal ** BRANCH_COMPLETE_PREDICTOR_2_ACK ; + sc_signal ** BRANCH_COMPLETE_ACK ; + + sc_signal ** BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY; + sc_signal ** BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY; + sc_signal ** BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY; + sc_signal ** BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY; + sc_signal ** BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY; + sc_signal ** BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY; + sc_signal ** BRANCH_COMPLETE_HISTORY ; + sc_signal ** BRANCH_COMPLETE_DIRECTION ; + sc_signal ** BRANCH_COMPLETE_PREDICTOR_2_DIRECTION ; + string rename; + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + CLOCK = new sc_clock ("clock", 1.0, 0.5); + NRESET = new sc_signal ("nreset"); +#endif + + // Interface Predict + + PREDICT_PREDICTOR_0_ACK = new sc_signal * [_param._nb_prediction ]; + PREDICT_PREDICTOR_1_ACK = new sc_signal * [_param._nb_prediction ]; + PREDICT_PREDICTOR_2_ACK = new sc_signal * [_param._nb_prediction ]; + PREDICT_ACK = new sc_signal * [_param._nb_prediction ]; + PREDICT_PREDICTOR_0_BHT_HISTORY = new sc_signal * [_param._nb_prediction ]; + PREDICT_PREDICTOR_0_PHT_HISTORY = new sc_signal * [_param._nb_prediction ]; + PREDICT_PREDICTOR_1_BHT_HISTORY = new sc_signal * [_param._nb_prediction ]; + PREDICT_PREDICTOR_1_PHT_HISTORY = new sc_signal * [_param._nb_prediction ]; + PREDICT_PREDICTOR_2_BHT_HISTORY = new sc_signal * [_param._nb_prediction ]; + PREDICT_PREDICTOR_2_PHT_HISTORY = new sc_signal * [_param._nb_prediction ]; + PREDICT_HISTORY = new sc_signal * [_param._nb_prediction ]; + PREDICT_DIRECTION = new sc_signal * [_param._nb_prediction ]; + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + rename = "PREDICT_PREDICTOR_0_ACK_" +toString(i); + PREDICT_PREDICTOR_0_ACK [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_PREDICTOR_1_ACK_" +toString(i); + PREDICT_PREDICTOR_1_ACK [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_PREDICTOR_2_ACK_" +toString(i); + PREDICT_PREDICTOR_2_ACK [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_ACK_" +toString(i); + PREDICT_ACK [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_PREDICTOR_0_BHT_HISTORY_"+toString(i); + PREDICT_PREDICTOR_0_BHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_PREDICTOR_0_PHT_HISTORY_"+toString(i); + PREDICT_PREDICTOR_0_PHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_PREDICTOR_1_BHT_HISTORY_"+toString(i); + PREDICT_PREDICTOR_1_BHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_PREDICTOR_1_PHT_HISTORY_"+toString(i); + PREDICT_PREDICTOR_1_PHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_PREDICTOR_2_BHT_HISTORY_"+toString(i); + PREDICT_PREDICTOR_2_BHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_PREDICTOR_2_PHT_HISTORY_"+toString(i); + PREDICT_PREDICTOR_2_PHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_HISTORY_" +toString(i); + PREDICT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_DIRECTION_" +toString(i); + PREDICT_DIRECTION [i] = new sc_signal (rename.c_str()); + } + + // Interface Branch_complete + BRANCH_COMPLETE_VAL = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_PREDICTOR_2_VAL = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_PREDICTOR_0_ACK = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_PREDICTOR_1_ACK = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_PREDICTOR_2_ACK = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_ACK = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_HISTORY = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_DIRECTION = new sc_signal * [_param._nb_branch_complete ]; + BRANCH_COMPLETE_PREDICTOR_2_DIRECTION = new sc_signal * [_param._nb_branch_complete ]; + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + rename = "BRANCH_COMPLETE_VAL_" +toString(i); + BRANCH_COMPLETE_VAL [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_PREDICTOR_2_VAL_" +toString(i); + BRANCH_COMPLETE_PREDICTOR_2_VAL [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_PREDICTOR_0_ACK_" +toString(i); + BRANCH_COMPLETE_PREDICTOR_0_ACK [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_PREDICTOR_1_ACK_" +toString(i); + BRANCH_COMPLETE_PREDICTOR_1_ACK [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_PREDICTOR_2_ACK_" +toString(i); + BRANCH_COMPLETE_PREDICTOR_2_ACK [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_ACK_" +toString(i); + BRANCH_COMPLETE_ACK [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY_"+toString(i); + BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY_"+toString(i); + BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY_"+toString(i); + BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY_"+toString(i); + BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY_"+toString(i); + BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY_"+toString(i); + BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_HISTORY_" +toString(i); + BRANCH_COMPLETE_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_DIRECTION_" +toString(i); + BRANCH_COMPLETE_DIRECTION [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_PREDICTOR_2_DIRECTION_" +toString(i); + BRANCH_COMPLETE_PREDICTOR_2_DIRECTION [i] = new sc_signal (rename.c_str()); + } + + /******************************************************** + * Instanciation + ********************************************************/ + + cout << "<" << name << "> Instanciation of _Meta_Predictor_Glue" << endl; + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + (*(_Meta_Predictor_Glue->in_CLOCK)) (*(CLOCK)); + (*(_Meta_Predictor_Glue->in_NRESET)) (*(NRESET)); +#endif + + // Interface Predict + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + if (_param._have_meta_predictor) + { + (*(_Meta_Predictor_Glue-> in_PREDICT_PREDICTOR_0_ACK [i])) (*(PREDICT_PREDICTOR_0_ACK [i])); + (*(_Meta_Predictor_Glue-> in_PREDICT_PREDICTOR_1_ACK [i])) (*(PREDICT_PREDICTOR_1_ACK [i])); + } + (*(_Meta_Predictor_Glue-> in_PREDICT_PREDICTOR_2_ACK [i])) (*(PREDICT_PREDICTOR_2_ACK [i])); + (*(_Meta_Predictor_Glue->out_PREDICT_ACK [i])) (*(PREDICT_ACK [i])); + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + (*(_Meta_Predictor_Glue-> in_PREDICT_PREDICTOR_0_BHT_HISTORY [i])) (*(PREDICT_PREDICTOR_0_BHT_HISTORY [i])); + if (_param._predictor_0_have_pht) + (*(_Meta_Predictor_Glue-> in_PREDICT_PREDICTOR_0_PHT_HISTORY [i])) (*(PREDICT_PREDICTOR_0_PHT_HISTORY [i])); + if (_param._predictor_1_have_bht) + (*(_Meta_Predictor_Glue-> in_PREDICT_PREDICTOR_1_BHT_HISTORY [i])) (*(PREDICT_PREDICTOR_1_BHT_HISTORY [i])); + if (_param._predictor_1_have_pht) + (*(_Meta_Predictor_Glue-> in_PREDICT_PREDICTOR_1_PHT_HISTORY [i])) (*(PREDICT_PREDICTOR_1_PHT_HISTORY [i])); + } + if (_param._predictor_2_have_bht) + (*(_Meta_Predictor_Glue-> in_PREDICT_PREDICTOR_2_BHT_HISTORY [i])) (*(PREDICT_PREDICTOR_2_BHT_HISTORY [i])); + if (_param._predictor_2_have_pht) + (*(_Meta_Predictor_Glue-> in_PREDICT_PREDICTOR_2_PHT_HISTORY [i])) (*(PREDICT_PREDICTOR_2_PHT_HISTORY [i])); + (*(_Meta_Predictor_Glue->out_PREDICT_HISTORY [i])) (*(PREDICT_HISTORY [i])); + (*(_Meta_Predictor_Glue->out_PREDICT_DIRECTION [i])) (*(PREDICT_DIRECTION [i])); + } + + // Interface Branch_complete + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + if (_param._have_meta_predictor) + { + (*(_Meta_Predictor_Glue-> in_BRANCH_COMPLETE_VAL [i])) (*(BRANCH_COMPLETE_VAL [i])); + (*(_Meta_Predictor_Glue->out_BRANCH_COMPLETE_PREDICTOR_2_VAL [i])) (*(BRANCH_COMPLETE_PREDICTOR_2_VAL [i])); + + (*(_Meta_Predictor_Glue-> in_BRANCH_COMPLETE_PREDICTOR_0_ACK [i])) (*(BRANCH_COMPLETE_PREDICTOR_0_ACK [i])); + (*(_Meta_Predictor_Glue-> in_BRANCH_COMPLETE_PREDICTOR_1_ACK [i])) (*(BRANCH_COMPLETE_PREDICTOR_1_ACK [i])); + } + (*(_Meta_Predictor_Glue-> in_BRANCH_COMPLETE_PREDICTOR_2_ACK [i])) (*(BRANCH_COMPLETE_PREDICTOR_2_ACK [i])); + (*(_Meta_Predictor_Glue->out_BRANCH_COMPLETE_ACK [i])) (*(BRANCH_COMPLETE_ACK [i])); + + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + (*(_Meta_Predictor_Glue->out_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY [i])) (*(BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY [i])); + if (_param._predictor_0_have_pht) + (*(_Meta_Predictor_Glue->out_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY [i])) (*(BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY [i])); + if (_param._predictor_1_have_bht) + (*(_Meta_Predictor_Glue->out_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY [i])) (*(BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY [i])); + if (_param._predictor_1_have_pht) + (*(_Meta_Predictor_Glue->out_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY [i])) (*(BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY [i])); + } + if (_param._predictor_2_have_bht) + (*(_Meta_Predictor_Glue->out_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY [i])) (*(BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY [i])); + if (_param._predictor_2_have_pht) + (*(_Meta_Predictor_Glue->out_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY [i])) (*(BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY [i])); + (*(_Meta_Predictor_Glue-> in_BRANCH_COMPLETE_HISTORY [i])) (*(BRANCH_COMPLETE_HISTORY [i])); + if (_param._have_meta_predictor) + { + (*(_Meta_Predictor_Glue-> in_BRANCH_COMPLETE_DIRECTION [i])) (*(BRANCH_COMPLETE_DIRECTION [i])); + (*(_Meta_Predictor_Glue->out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION [i])) (*(BRANCH_COMPLETE_PREDICTOR_2_DIRECTION [i])); + } + } + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + cout << "<" << name << "> Start Simulation ............" << endl; + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + sc_start(0); + cout << "{"+toString(static_cast(sc_simulation_time()))+"} Initialisation" << endl; + + NRESET->write(0); + sc_start(5); + NRESET->write(1); + // No need initialisation + + cout << "{"+toString(static_cast(sc_simulation_time()))+"} Loop of Test" << endl; + + Tcontrol_t predict_ack [_param._nb_prediction]; + Thistory_t predict_history [_param._nb_prediction]; + Tcontrol_t predict_direction [_param._nb_prediction]; + + Tcontrol_t branch_complete_predictor_2_val [_param._nb_branch_complete]; + Tcontrol_t branch_complete_ack [_param._nb_branch_complete]; + Tbht_history_t branch_complete_predictor_0_bht_history [_param._nb_branch_complete]; + Tpht_history_t branch_complete_predictor_0_pht_history [_param._nb_branch_complete]; + Tbht_history_t branch_complete_predictor_1_bht_history [_param._nb_branch_complete]; + Tpht_history_t branch_complete_predictor_1_pht_history [_param._nb_branch_complete]; + Tbht_history_t branch_complete_predictor_2_bht_history [_param._nb_branch_complete]; + Tpht_history_t branch_complete_predictor_2_pht_history [_param._nb_branch_complete]; + Tcontrol_t branch_complete_predictor_2_direction [_param._nb_branch_complete]; + + uint32_t shift_0 = 0; + uint32_t shift_1 = shift_0 + _param._predictor_0_bht_size_shifter; + uint32_t shift_2 = shift_1 + _param._predictor_0_pht_size_counter; + uint32_t shift_3 = shift_2 + _param._predictor_1_bht_size_shifter; + uint32_t shift_4 = shift_3 + _param._predictor_1_pht_size_counter; + uint32_t shift_5 = shift_4 + _param._predictor_2_bht_size_shifter; +//uint32_t shift_6 = shift_5 + _param._predictor_2_pht_size_counter; + + cout << "shift_0 : " << shift_0 << endl; + cout << "shift_1 : " << shift_1 << endl; + cout << "shift_2 : " << shift_2 << endl; + cout << "shift_3 : " << shift_3 << endl; + cout << "shift_4 : " << shift_4 << endl; + cout << "shift_5 : " << shift_5 << endl; + + for (uint32_t iteration=0; iterationwrite (predictor_0_ack); + PREDICT_PREDICTOR_1_ACK [i] ->write (predictor_1_ack); + PREDICT_PREDICTOR_2_ACK [i] ->write (predictor_2_ack); + + predictor_0_bht_history = rand() % (_param._predictor_0_bht_size_shifter+1); + predictor_0_pht_history = rand() % (_param._predictor_0_pht_size_counter+1); + predictor_1_bht_history = rand() % (_param._predictor_1_bht_size_shifter+1); + predictor_1_pht_history = rand() % (_param._predictor_1_pht_size_counter+1); + predictor_2_bht_history = rand() % (_param._predictor_2_bht_size_shifter+1); + predictor_2_pht_history = rand() % (_param._predictor_2_pht_size_counter+1); + + predict_history [i] = ( (predictor_0_bht_history << shift_0) | + (predictor_0_pht_history << shift_1) | + (predictor_1_bht_history << shift_2) | + (predictor_1_pht_history << shift_3) | + (predictor_2_bht_history << shift_4) | + (predictor_2_pht_history << shift_5) ); + + cout << "{"+toString(static_cast(sc_simulation_time()))+"} predict [" << i << "]" << endl + << " _2_ " << predictor_2_bht_history << " - " << predictor_2_pht_history << endl + << " _/ " << endl + << " | |-1- " << predictor_1_bht_history << " - " << predictor_1_pht_history << endl + << " --| | " << endl + << " |_|-0- " << predictor_0_bht_history << " - " << predictor_0_pht_history << endl; + + + Tcontrol_t predict_direction_predictor_2; + + if (_param._predictor_2_have_pht) + predict_direction_predictor_2 = (predictor_2_pht_history & (1<<(_param._predictor_2_pht_size_counter-1))) != 0; + else + predict_direction_predictor_2 = (predictor_2_bht_history & (1<<(_param._predictor_2_bht_size_shifter-1))) != 0; + + if (_param._have_meta_predictor == false) + predict_direction [i] = predict_direction_predictor_2; + else + if (predict_direction_predictor_2 == false) + if (_param._predictor_0_have_pht) + predict_direction [i] = (predictor_0_pht_history & (1<<(_param._predictor_0_pht_size_counter-1))) != 0; + else + predict_direction [i] = (predictor_0_bht_history & (1<<(_param._predictor_0_bht_size_shifter-1))) != 0; + else + if (_param._predictor_1_have_pht) + predict_direction [i] = (predictor_1_pht_history & (1<<(_param._predictor_1_pht_size_counter-1))) != 0; + else + predict_direction [i] = (predictor_1_bht_history & (1<<(_param._predictor_1_bht_size_shifter-1))) != 0; + + PREDICT_PREDICTOR_0_BHT_HISTORY [i]->write(predictor_0_bht_history); + PREDICT_PREDICTOR_0_PHT_HISTORY [i]->write(predictor_0_pht_history); + PREDICT_PREDICTOR_1_BHT_HISTORY [i]->write(predictor_1_bht_history); + PREDICT_PREDICTOR_1_PHT_HISTORY [i]->write(predictor_1_pht_history); + PREDICT_PREDICTOR_2_BHT_HISTORY [i]->write(predictor_2_bht_history); + PREDICT_PREDICTOR_2_PHT_HISTORY [i]->write(predictor_2_pht_history); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + Tcontrol_t predictor_0_ack , predictor_1_ack , predictor_2_ack ; + + predictor_0_ack = not _param._have_meta_predictor or ((rand()%2) != 0); + predictor_1_ack = not _param._have_meta_predictor or ((rand()%2) != 0); + predictor_2_ack = ((rand()%2) != 0); + branch_complete_ack [i] = predictor_0_ack and predictor_1_ack and predictor_2_ack; + + BRANCH_COMPLETE_PREDICTOR_0_ACK [i] ->write (predictor_0_ack); + BRANCH_COMPLETE_PREDICTOR_1_ACK [i] ->write (predictor_1_ack); + BRANCH_COMPLETE_PREDICTOR_2_ACK [i] ->write (predictor_2_ack); + + branch_complete_predictor_0_bht_history [i] = rand() % (1<<_param._predictor_0_bht_size_shifter); + branch_complete_predictor_0_pht_history [i] = rand() % (1<<_param._predictor_0_pht_size_counter); + branch_complete_predictor_1_bht_history [i] = rand() % (1<<_param._predictor_1_bht_size_shifter); + branch_complete_predictor_1_pht_history [i] = rand() % (1<<_param._predictor_1_pht_size_counter); + branch_complete_predictor_2_bht_history [i] = rand() % (1<<_param._predictor_2_bht_size_shifter); + branch_complete_predictor_2_pht_history [i] = rand() % (1<<_param._predictor_2_pht_size_counter); + + Thistory_t history = ((branch_complete_predictor_0_bht_history [i] << shift_0) | + (branch_complete_predictor_0_pht_history [i] << shift_1) | + (branch_complete_predictor_1_bht_history [i] << shift_2) | + (branch_complete_predictor_1_pht_history [i] << shift_3) | + (branch_complete_predictor_2_bht_history [i] << shift_4) | + (branch_complete_predictor_2_pht_history [i] << shift_5) ); + + BRANCH_COMPLETE_HISTORY [i]->write (history); + + cout << " [" << i << "] : " << endl + << hex + << " * " << history << endl + << " - " << branch_complete_predictor_0_bht_history [i] << endl + << " - " << branch_complete_predictor_0_pht_history [i] << endl + << " - " << branch_complete_predictor_1_bht_history [i] << endl + << " - " << branch_complete_predictor_1_pht_history [i] << endl + << " - " << branch_complete_predictor_2_bht_history [i] << endl + << " - " << branch_complete_predictor_2_pht_history [i] << endl + << dec; + + Tcontrol_t direction_0 = ((_param._predictor_0_have_pht)?(branch_complete_predictor_0_pht_history [i] >> (_param._predictor_0_pht_size_counter-1)):(branch_complete_predictor_0_bht_history [i] >> (_param._predictor_0_bht_size_shifter-1)))&1; + Tcontrol_t direction_1 = ((_param._predictor_1_have_pht)?(branch_complete_predictor_1_pht_history [i] >> (_param._predictor_1_pht_size_counter-1)):(branch_complete_predictor_1_bht_history [i] >> (_param._predictor_1_bht_size_shifter-1)))&1; + Tcontrol_t direction_2 = ((_param._predictor_2_have_pht)?(branch_complete_predictor_2_pht_history [i] >> (_param._predictor_2_pht_size_counter-1)):(branch_complete_predictor_2_bht_history [i] >> (_param._predictor_2_bht_size_shifter-1)))&1; + + Tcontrol_t direction = ((rand()%2) != 0); + Tcontrol_t val = ((rand()%2) != 0); + + cout << "{"+toString(static_cast(sc_simulation_time()))+"} " << endl + << " * val : " << val << endl + << " * direction_good : " << direction << endl + << " * direction_0 : " << direction_0 << endl + << " * direction_1 : " << direction_1 << endl + << " * direction_2 : " << direction_2 << endl; + + BRANCH_COMPLETE_VAL [i] ->write (val); + BRANCH_COMPLETE_DIRECTION [i] ->write (direction); + + if (val == 0) + { + branch_complete_predictor_2_val [i] = val; + } + else + { + branch_complete_predictor_2_val [i] = (direction_0 xor direction_1); + if (direction_2 == 0) + if (direction_0 == direction) + branch_complete_predictor_2_direction [i] = 0; + else + branch_complete_predictor_2_direction [i] = 1; + else + if (direction_1 == direction) + branch_complete_predictor_2_direction [i] = 1; + else + branch_complete_predictor_2_direction [i] = 0; + } + } + + sc_start(1); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + TEST(Tcontrol_t , PREDICT_ACK [i]->read(), predict_ack [i]); + TEST(Tcontrol_t , PREDICT_HISTORY [i]->read(), predict_history [i]); + TEST(Tcontrol_t , PREDICT_DIRECTION [i]->read(), predict_direction [i]); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + TEST(Tcontrol_t , BRANCH_COMPLETE_ACK [i]->read(), branch_complete_ack [i]); + + if (_param._have_meta_predictor) + { + TEST(Tcontrol_t , BRANCH_COMPLETE_PREDICTOR_2_VAL [i]->read(), branch_complete_predictor_2_val [i]); + + if (branch_complete_predictor_2_val [i]) + TEST(Tcontrol_t , BRANCH_COMPLETE_PREDICTOR_2_DIRECTION [i]->read(), branch_complete_predictor_2_direction [i]); + + if (_param._predictor_0_have_bht) + TEST(Tbht_history_t, BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY [i]->read(), branch_complete_predictor_0_bht_history [i]); + if (_param._predictor_0_have_pht) + TEST(Tpht_history_t, BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY [i]->read(), branch_complete_predictor_0_pht_history [i]); + if (_param._predictor_1_have_bht) + TEST(Tbht_history_t, BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY [i]->read(), branch_complete_predictor_1_bht_history [i]); + if (_param._predictor_1_have_pht) + TEST(Tpht_history_t, BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY [i]->read(), branch_complete_predictor_1_pht_history [i]); + } + if (_param._predictor_2_have_bht) + TEST(Tbht_history_t, BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY [i]->read(), branch_complete_predictor_2_bht_history [i]); + if (_param._predictor_2_have_pht) + TEST(Tpht_history_t, BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY [i]->read(), branch_complete_predictor_2_pht_history [i]); + } + } + + /******************************************************** + * Simulation - End + ********************************************************/ + + cout << "<" << name << "> ............ Stop Simulation" << endl; + +#endif + + delete _Meta_Predictor_Glue; +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/VERSION =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/VERSION (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/VERSION (revision 45) @@ -0,0 +1,1 @@ +v0.4 Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/Makefile (revision 45) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = .. +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/Meta_Predictor_Glue.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/Meta_Predictor_Glue.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/Meta_Predictor_Glue.tex (revision 45) @@ -0,0 +1,38 @@ +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/sty/header.sty (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/sty/header.sty (revision 45) @@ -0,0 +1,12 @@ +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Meta\_Predictor\_Glue} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/01_introduction.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/01_introduction.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/02_features.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/02_features.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/03_description.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/03_description.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/04_pinout.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/04_pinout.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/05_parameters.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/05_parameters.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/06_performance.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/06_performance.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/07_details.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/07_details.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/08_history.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/08_history.tex (revision 45) @@ -0,0 +1,10 @@ +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/root.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/doc/tex/root.tex (revision 45) @@ -0,0 +1,8 @@ +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h (revision 45) @@ -0,0 +1,162 @@ +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_meta_predictor_glue_Meta_Predictor_Glue_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_meta_predictor_glue_Meta_Predictor_Glue_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Statistics.h" +#endif +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Component.h" + +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + class Meta_Predictor_Glue +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const string _name; + + protected : const Parameters _param; +//#ifdef STATISTICS +// protected : const morpheo::behavioural::Parameters_Statistics _param_statistics; +//#endif + +#ifdef STATISTICS + private : Statistics * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // Interface + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // Interface Predict + public : SC_IN (Tcontrol_t) ** in_PREDICT_PREDICTOR_0_ACK ; + public : SC_IN (Tcontrol_t) ** in_PREDICT_PREDICTOR_1_ACK ; + public : SC_IN (Tcontrol_t) ** in_PREDICT_PREDICTOR_2_ACK ; + public : SC_OUT(Tcontrol_t) ** out_PREDICT_ACK ; + + public : SC_IN (Tbht_history_t) ** in_PREDICT_PREDICTOR_0_BHT_HISTORY ; + public : SC_IN (Tpht_history_t) ** in_PREDICT_PREDICTOR_0_PHT_HISTORY ; + public : SC_IN (Tbht_history_t) ** in_PREDICT_PREDICTOR_1_BHT_HISTORY ; + public : SC_IN (Tpht_history_t) ** in_PREDICT_PREDICTOR_1_PHT_HISTORY ; + public : SC_IN (Tbht_history_t) ** in_PREDICT_PREDICTOR_2_BHT_HISTORY ; + public : SC_IN (Tpht_history_t) ** in_PREDICT_PREDICTOR_2_PHT_HISTORY ; + public : SC_OUT(Thistory_t) ** out_PREDICT_HISTORY ; + public : SC_OUT(Tcontrol_t) ** out_PREDICT_DIRECTION ; + + // Interface Branch_complete + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_VAL ; + public : SC_OUT(Tcontrol_t) ** out_BRANCH_COMPLETE_PREDICTOR_2_VAL ; + + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_PREDICTOR_0_ACK ; + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_PREDICTOR_1_ACK ; + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_PREDICTOR_2_ACK ; + public : SC_OUT(Tcontrol_t) ** out_BRANCH_COMPLETE_ACK ; + + public : SC_OUT(Tbht_history_t) ** out_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY; + public : SC_OUT(Tpht_history_t) ** out_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY; + public : SC_OUT(Tbht_history_t) ** out_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY; + public : SC_OUT(Tpht_history_t) ** out_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY; + public : SC_OUT(Tbht_history_t) ** out_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY; + public : SC_OUT(Tpht_history_t) ** out_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY; + public : SC_IN (Thistory_t) ** in_BRANCH_COMPLETE_HISTORY ; + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_DIRECTION ; + public : SC_OUT(Tcontrol_t) ** out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION ; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Meta_Predictor_Glue); +#endif + public : Meta_Predictor_Glue ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics param_statistics, +#endif + Parameters param ); + + public : Meta_Predictor_Glue (Parameters param ); + public : ~Meta_Predictor_Glue (void); + +#ifdef SYSTEMC + private : void allocation (void); + private : void deallocation (void); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + public : void transition (void); +#endif + public : void genMealy_predict_ack (void); + public : void genMealy_predict_history (void); + public : void genMealy_branch_complete_val (void); + public : void genMealy_branch_complete_ack (void); + public : void genMealy_branch_complete_history (void); + +#endif +#ifdef STATISTICS + public : string statistics (uint32_t depth); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif +#ifdef VHDL_TESTBENCH + private : void vhdl_testbench_transition (void); +#endif + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/include/Parameters.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/include/Parameters.h (revision 45) @@ -0,0 +1,90 @@ +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_meta_predictor_glue_Parameters_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_meta_predictor_glue_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" +#include "Behavioural/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : const bool _have_meta_predictor ; + + public : const bool _predictor_0_have_bht ; + public : const uint32_t _predictor_0_bht_size_shifter ; + public : const bool _predictor_0_have_pht ; + public : const uint32_t _predictor_0_pht_size_counter ; + + public : const bool _predictor_1_have_bht ; + public : const uint32_t _predictor_1_bht_size_shifter ; + public : const bool _predictor_1_have_pht ; + public : const uint32_t _predictor_1_pht_size_counter ; + + public : const bool _predictor_2_have_bht ; + public : const uint32_t _predictor_2_bht_size_shifter ; + public : const bool _predictor_2_have_pht ; + public : const uint32_t _predictor_2_pht_size_counter ; + + public : const uint32_t _nb_prediction ; + public : const uint32_t _nb_branch_complete ; + + public : const uint32_t _size_history ; + + public : const uint32_t _shift_0; + public : const uint32_t _shift_1; + public : const uint32_t _shift_2; + public : const uint32_t _shift_3; + public : const uint32_t _shift_4; + public : const uint32_t _shift_5; + public : const uint32_t _shift_6; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (bool have_meta_predictor , + bool predictor_0_have_bht , + uint32_t predictor_0_bht_size_shifter , + bool predictor_0_have_pht , + uint32_t predictor_0_pht_size_counter , + bool predictor_1_have_bht , + uint32_t predictor_1_bht_size_shifter , + bool predictor_1_have_pht , + uint32_t predictor_1_pht_size_counter , + bool predictor_2_have_bht , + uint32_t predictor_2_bht_size_shifter , + bool predictor_2_have_pht , + uint32_t predictor_2_pht_size_counter , + uint32_t nb_prediction , + uint32_t nb_branch_complete ); + public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : string msg_error (void); + + public : string print (uint32_t depth); + public : friend ostream& operator<< (ostream& output_stream, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::meta_predictor_glue::Parameters & x); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/include/Statistics.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/include/Statistics.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/include/Statistics.h (revision 45) @@ -0,0 +1,59 @@ +#ifdef STATISTICS +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_meta_predictor_glue_Statistics_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_meta_predictor_glue_Statistics_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" +#include "Behavioural/include/Statistics.h" +#include "Behavioural/include/Parameters_Statistics.h" +//#include "Behavioural/Generic/Group/include/Statistics.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Parameters.h" + +//using namespace morpheo::behavioural::generic::group; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + class Statistics : public morpheo::behavioural::Statistics + { + // -----[ fields ]---------------------------------------------------- + private : const Parameters _parameters; + + // -----[ methods ]--------------------------------------------------- + public : Statistics (string name , + morpheo::behavioural::Parameters_Statistics parameters_statistics , + Parameters parameters + ); +//public : Statistics (Statistics & stat); + public : ~Statistics () ; + + public : string print_body (uint32_t depth); + public : string print (uint32_t depth); + public : void add (); + + public : friend ostream& operator<< (ostream& output_stream, + const Statistics & x); + + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/include/Types.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/include/Types.h (revision 45) @@ -0,0 +1,34 @@ +#ifdef SYSTEMC +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_meta_predictor_glue_Type_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_meta_predictor_glue_Type_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + typedef uint32_t Thistory_t; + typedef uint32_t Tbht_history_t; + typedef uint32_t Tpht_history_t; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue.cpp (revision 45) @@ -0,0 +1,271 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + +#ifdef SYSTEMC + Meta_Predictor_Glue::Meta_Predictor_Glue (sc_module_name name, +#else + Meta_Predictor_Glue::Meta_Predictor_Glue (string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics param_statistics, +#endif + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::meta_predictor_glue::Parameters param ): + _name (name) + ,_param (param) +// #ifdef STATISTICS +// ,_param_statistics (param_statistics) +// #endif + { + log_printf(FUNC,Meta_Predictor_Glue,"Meta_Predictor_Glue","Begin"); + + log_printf(INFO,Meta_Predictor_Glue,"Meta_Predictor_Glue","Allocation"); + allocation (); + +#ifdef STATISTICS + log_printf(INFO,Meta_Predictor_Glue,"Meta_Predictor_Glue","Allocation of statistics"); + + // Allocation of statistics + _stat = new Statistics (static_cast(_name), + param_statistics , + param); +#endif + +#ifdef VHDL + // generate the vhdl + log_printf(INFO,Meta_Predictor_Glue,"Meta_Predictor_Glue","VHDL's generation"); + vhdl(); +#endif + +#ifdef SYSTEMC +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + log_printf(INFO,Meta_Predictor_Glue,"Meta_Predictor_Glue","method - transition"); + + SC_METHOD (transition); + dont_initialize (); + sensitive_pos << *(in_CLOCK); +#endif + + log_printf(INFO,Meta_Predictor_Glue,"Meta_Predictor_Glue","method - genMealy_predict_ack"); + SC_METHOD (genMealy_predict_ack); + dont_initialize (); + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + sensitive << *(in_PREDICT_PREDICTOR_2_ACK [i]); + + if (_param._have_meta_predictor) + { + sensitive << *(in_PREDICT_PREDICTOR_0_ACK [i]) + << *(in_PREDICT_PREDICTOR_1_ACK [i]); + } + } + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + (*(out_PREDICT_ACK [i])) (*(in_PREDICT_PREDICTOR_2_ACK [i])); + + if (_param._have_meta_predictor) + { + (*(out_PREDICT_ACK [i])) (*(in_PREDICT_PREDICTOR_0_ACK [i])); + (*(out_PREDICT_ACK [i])) (*(in_PREDICT_PREDICTOR_1_ACK [i])); + } + } +#endif + + log_printf(INFO,Meta_Predictor_Glue,"Meta_Predictor_Glue","method - genMealy_predict_history"); + SC_METHOD (genMealy_predict_history); + dont_initialize (); + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + if (_param._predictor_2_have_bht) + sensitive << *(in_PREDICT_PREDICTOR_2_BHT_HISTORY [i]); + if (_param._predictor_2_have_pht) + sensitive << *(in_PREDICT_PREDICTOR_2_PHT_HISTORY [i]); + + if (_param._have_meta_predictor) + { + if (_param._predictor_1_have_bht) + sensitive << *(in_PREDICT_PREDICTOR_1_BHT_HISTORY [i]); + if (_param._predictor_1_have_pht) + sensitive << *(in_PREDICT_PREDICTOR_1_PHT_HISTORY [i]); + + if (_param._predictor_0_have_bht) + sensitive << *(in_PREDICT_PREDICTOR_0_BHT_HISTORY [i]); + if (_param._predictor_0_have_pht) + sensitive << *(in_PREDICT_PREDICTOR_0_PHT_HISTORY [i]); + } + } + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + if (_param._predictor_2_have_bht) + (*(out_PREDICT_HISTORY [i])) (*(in_PREDICT_PREDICTOR_2_BHT_HISTORY [i])); + if (_param._predictor_2_have_pht) + (*(out_PREDICT_HISTORY [i])) (*(in_PREDICT_PREDICTOR_2_PHT_HISTORY [i])); + + if (_param._have_meta_predictor) + { + if (_param._predictor_1_have_bht) + (*(out_PREDICT_HISTORY [i])) (*(in_PREDICT_PREDICTOR_1_BHT_HISTORY [i])); + if (_param._predictor_1_have_pht) + (*(out_PREDICT_HISTORY [i])) (*(in_PREDICT_PREDICTOR_1_PHT_HISTORY [i])); + + if (_param._predictor_0_have_bht) + (*(out_PREDICT_HISTORY [i])) (*(in_PREDICT_PREDICTOR_0_BHT_HISTORY [i])); + if (_param._predictor_0_have_pht) + (*(out_PREDICT_HISTORY [i])) (*(in_PREDICT_PREDICTOR_0_PHT_HISTORY [i])); + } + + if (_param._predictor_2_have_bht) + (*(out_PREDICT_DIRECTION [i])) (*(in_PREDICT_PREDICTOR_2_BHT_HISTORY [i])); + if (_param._predictor_2_have_pht) + (*(out_PREDICT_DIRECTION [i])) (*(in_PREDICT_PREDICTOR_2_PHT_HISTORY [i])); + + if (_param._have_meta_predictor) + { + if (_param._predictor_1_have_bht) + (*(out_PREDICT_DIRECTION [i])) (*(in_PREDICT_PREDICTOR_1_BHT_HISTORY [i])); + if (_param._predictor_1_have_pht) + (*(out_PREDICT_DIRECTION [i])) (*(in_PREDICT_PREDICTOR_1_PHT_HISTORY [i])); + + if (_param._predictor_0_have_bht) + (*(out_PREDICT_DIRECTION [i])) (*(in_PREDICT_PREDICTOR_0_BHT_HISTORY [i])); + if (_param._predictor_0_have_pht) + (*(out_PREDICT_DIRECTION [i])) (*(in_PREDICT_PREDICTOR_0_PHT_HISTORY [i])); + } + } +#endif + + if (_param._have_meta_predictor) + { + log_printf(INFO,Meta_Predictor_Glue,"Meta_Predictor_Glue","method - genMealy_branch_complete_val"); + SC_METHOD (genMealy_branch_complete_val); + dont_initialize (); + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + sensitive << *(in_BRANCH_COMPLETE_VAL [i]) + << *(in_BRANCH_COMPLETE_HISTORY [i]) + << *(in_BRANCH_COMPLETE_DIRECTION [i]); + } + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + (*(out_BRANCH_COMPLETE_PREDICTOR_2_VAL [i])) (*(in_BRANCH_COMPLETE_VAL [i])); + (*(out_BRANCH_COMPLETE_PREDICTOR_2_VAL [i])) (*(in_BRANCH_COMPLETE_HISTORY [i])); + (*(out_BRANCH_COMPLETE_PREDICTOR_2_VAL [i])) (*(in_BRANCH_COMPLETE_DIRECTION [i])); + + (*(out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION [i])) (*(in_BRANCH_COMPLETE_VAL [i])); + (*(out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION [i])) (*(in_BRANCH_COMPLETE_HISTORY [i])); + (*(out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION [i])) (*(in_BRANCH_COMPLETE_DIRECTION [i])); + } +#endif + } + + log_printf(INFO,Meta_Predictor_Glue,"Meta_Predictor_Glue","method - genMealy_branch_complete_ack"); + SC_METHOD (genMealy_branch_complete_ack); + dont_initialize (); + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + sensitive << *(in_BRANCH_COMPLETE_PREDICTOR_2_ACK [i]); + + if (_param._have_meta_predictor) + { + sensitive << *(in_BRANCH_COMPLETE_PREDICTOR_0_ACK [i]) + << *(in_BRANCH_COMPLETE_PREDICTOR_1_ACK [i]); + } + } + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + (*(out_BRANCH_COMPLETE_ACK [i])) (*(in_BRANCH_COMPLETE_PREDICTOR_2_ACK [i])); + + if (_param._have_meta_predictor) + { + (*(out_BRANCH_COMPLETE_ACK [i])) (*(in_BRANCH_COMPLETE_PREDICTOR_0_ACK [i])); + (*(out_BRANCH_COMPLETE_ACK [i])) (*(in_BRANCH_COMPLETE_PREDICTOR_1_ACK [i])); + } + } +#endif + + log_printf(INFO,Meta_Predictor_Glue,"Meta_Predictor_Glue","method - genMealy_branch_complete_history"); + SC_METHOD (genMealy_branch_complete_history); + dont_initialize (); + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + sensitive << *(in_BRANCH_COMPLETE_HISTORY [i]); + } + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + if (_param._predictor_2_have_bht) + (*(out_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY [i])) (*( in_BRANCH_COMPLETE_HISTORY [i])); + if (_param._predictor_2_have_pht) + (*(out_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY [i])) (*( in_BRANCH_COMPLETE_HISTORY [i])); + + if (_param._have_meta_predictor) + { + if (_param._predictor_1_have_bht) + (*(out_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY [i])) (*( in_BRANCH_COMPLETE_HISTORY [i])); + if (_param._predictor_1_have_pht) + (*(out_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY [i])) (*( in_BRANCH_COMPLETE_HISTORY [i])); + + if (_param._predictor_0_have_bht) + (*(out_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY [i])) (*( in_BRANCH_COMPLETE_HISTORY [i])); + if (_param._predictor_0_have_pht) + (*(out_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY [i])) (*( in_BRANCH_COMPLETE_HISTORY [i])); + } + } +#endif + +#endif + log_printf(FUNC,Meta_Predictor_Glue,"Meta_Predictor_Glue","End"); + }; + + Meta_Predictor_Glue::~Meta_Predictor_Glue (void) + { + log_printf(FUNC,Meta_Predictor_Glue,"~Meta_Predictor_Glue","Begin"); + +#ifdef STATISTICS + log_printf(INFO,Meta_Predictor_Glue,"~Meta_Predictor_Glue","Generate Statistics"); + _stat->generate_file(statistics(0)); + + delete _stat; +#endif + +#ifdef SYSTEMC + log_printf(INFO,Meta_Predictor_Glue,"~Meta_Predictor_Glue","Dealocation"); + deallocation (); +#endif + + log_printf(FUNC,Meta_Predictor_Glue,"~Meta_Predictor_Glue","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_allocation.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_allocation.cpp (revision 45) @@ -0,0 +1,206 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + void Meta_Predictor_Glue::allocation (void) + { + string rename; + + log_printf(FUNC,Meta_Predictor_Glue,"allocation","Begin"); + + _component = new Component (); + + Entity * entity = _component->set_entity (_name + ,"Two_Level_Branch_Predictor_Glue" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + , IN + , SOUTH + , "Generalist interface" +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1,CLOCK_VHDL_NO); + in_NRESET = interface->set_signal_in ("nreset",1,RESET_VHDL_NO); + } + + + // ~~~~~[ Interface : "Predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + if (_param._have_meta_predictor) + { + in_PREDICT_PREDICTOR_0_ACK = new SC_IN (Tcontrol_t) * [_param._nb_prediction ]; + in_PREDICT_PREDICTOR_1_ACK = new SC_IN (Tcontrol_t) * [_param._nb_prediction ]; + } + in_PREDICT_PREDICTOR_2_ACK = new SC_IN (Tcontrol_t) * [_param._nb_prediction ]; + out_PREDICT_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_prediction ]; + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + in_PREDICT_PREDICTOR_0_BHT_HISTORY = new SC_IN (Tbht_history_t) * [_param._nb_prediction ]; + if (_param._predictor_0_have_pht) + in_PREDICT_PREDICTOR_0_PHT_HISTORY = new SC_IN (Tpht_history_t) * [_param._nb_prediction ]; + if (_param._predictor_1_have_bht) + in_PREDICT_PREDICTOR_1_BHT_HISTORY = new SC_IN (Tbht_history_t) * [_param._nb_prediction ]; + if (_param._predictor_1_have_pht) + in_PREDICT_PREDICTOR_1_PHT_HISTORY = new SC_IN (Tpht_history_t) * [_param._nb_prediction ]; + } + if (_param._predictor_2_have_bht) + in_PREDICT_PREDICTOR_2_BHT_HISTORY = new SC_IN (Tbht_history_t) * [_param._nb_prediction ]; + if (_param._predictor_2_have_pht) + in_PREDICT_PREDICTOR_2_PHT_HISTORY = new SC_IN (Tpht_history_t) * [_param._nb_prediction ]; + out_PREDICT_HISTORY = new SC_OUT(Thistory_t) * [_param._nb_prediction ]; + out_PREDICT_DIRECTION = new SC_OUT(Tcontrol_t) * [_param._nb_prediction ]; + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) +#ifdef POSITION + , IN + , WEST + , "Interface Predict" +#endif + ); + + if (_param._have_meta_predictor) + { + in_PREDICT_PREDICTOR_0_ACK [i] = interface->set_signal_in ("predictor_0_ack" , 1); + in_PREDICT_PREDICTOR_1_ACK [i] = interface->set_signal_in ("predictor_1_ack" , 1); + } + in_PREDICT_PREDICTOR_2_ACK [i] = interface->set_signal_in ("predictor_2_ack" , 1); + + out_PREDICT_ACK [i] = interface->set_signal_out ("ack" , 1); + + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + in_PREDICT_PREDICTOR_0_BHT_HISTORY [i] = interface->set_signal_in ("predictor_0_bht_history", _param._predictor_0_bht_size_shifter); + if (_param._predictor_0_have_pht) + in_PREDICT_PREDICTOR_0_PHT_HISTORY [i] = interface->set_signal_in ("predictor_0_pht_history", _param._predictor_0_pht_size_counter); + if (_param._predictor_1_have_bht) + in_PREDICT_PREDICTOR_1_BHT_HISTORY [i] = interface->set_signal_in ("predictor_1_bht_history", _param._predictor_1_bht_size_shifter); + if (_param._predictor_1_have_pht) + in_PREDICT_PREDICTOR_1_PHT_HISTORY [i] = interface->set_signal_in ("predictor_1_pht_history", _param._predictor_1_pht_size_counter); + } + if (_param._predictor_2_have_bht) + in_PREDICT_PREDICTOR_2_BHT_HISTORY [i] = interface->set_signal_in ("predictor_2_bht_history", _param._predictor_2_bht_size_shifter); + if (_param._predictor_2_have_pht) + in_PREDICT_PREDICTOR_2_PHT_HISTORY [i] = interface->set_signal_in ("predictor_2_pht_history", _param._predictor_2_pht_size_counter); + out_PREDICT_HISTORY [i] = interface->set_signal_out ("history" , _param._size_history); + out_PREDICT_DIRECTION [i] = interface->set_signal_out ("direction" , 1); + } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + if (_param._have_meta_predictor) + { + in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete ]; + out_BRANCH_COMPLETE_PREDICTOR_2_VAL = new SC_OUT(Tcontrol_t) * [_param._nb_branch_complete ]; + + in_BRANCH_COMPLETE_PREDICTOR_0_ACK = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete ]; + in_BRANCH_COMPLETE_PREDICTOR_1_ACK = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete ]; + } + in_BRANCH_COMPLETE_PREDICTOR_2_ACK = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete ]; + out_BRANCH_COMPLETE_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_branch_complete ]; + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + out_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY = new SC_OUT(Tbht_history_t) * [_param._nb_branch_complete ]; + if (_param._predictor_0_have_pht) + out_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY = new SC_OUT(Tpht_history_t) * [_param._nb_branch_complete ]; + if (_param._predictor_1_have_bht) + out_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY = new SC_OUT(Tbht_history_t) * [_param._nb_branch_complete ]; + if (_param._predictor_1_have_pht) + out_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY = new SC_OUT(Tpht_history_t) * [_param._nb_branch_complete ]; + } + if (_param._predictor_2_have_bht) + out_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY = new SC_OUT(Tbht_history_t) * [_param._nb_branch_complete ]; + if (_param._predictor_2_have_pht) + out_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY = new SC_OUT(Tpht_history_t) * [_param._nb_branch_complete ]; + in_BRANCH_COMPLETE_HISTORY = new SC_IN (Thistory_t) * [_param._nb_branch_complete ]; + if (_param._have_meta_predictor) + { + in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete ]; + out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION = new SC_OUT(Tcontrol_t) * [_param._nb_branch_complete ]; + } + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i) +#ifdef POSITION + , IN + , EAST + , "Interface branch complete" +#endif + ); + + if (_param._have_meta_predictor) + { + in_BRANCH_COMPLETE_VAL [i] = interface->set_signal_in ("val" , 1); + out_BRANCH_COMPLETE_PREDICTOR_2_VAL [i] = interface->set_signal_out ("predictor_2_val", 1); + in_BRANCH_COMPLETE_PREDICTOR_0_ACK [i] = interface->set_signal_in ("predictor_0_ack", 1); + in_BRANCH_COMPLETE_PREDICTOR_1_ACK [i] = interface->set_signal_in ("predictor_1_ack", 1); + } + in_BRANCH_COMPLETE_PREDICTOR_2_ACK [i] = interface->set_signal_in ("predictor_2_ack" , 1); + out_BRANCH_COMPLETE_ACK [i] = interface->set_signal_out ("ack" , 1); + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + out_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY [i] = interface->set_signal_out ("predictor_0_bht_history" , _param._predictor_0_bht_size_shifter ); + if (_param._predictor_0_have_pht) + out_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY [i] = interface->set_signal_out ("predictor_0_pht_history" , _param._predictor_0_pht_size_counter); + if (_param._predictor_1_have_bht) + out_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY [i] = interface->set_signal_out ("predictor_1_bht_history" , _param._predictor_1_bht_size_shifter ); + if (_param._predictor_1_have_pht) + out_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY [i] = interface->set_signal_out ("predictor_1_pht_history" , _param._predictor_1_pht_size_counter ); + } + if (_param._predictor_2_have_bht) + out_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY [i] = interface->set_signal_out ("predictor_2_bht_history" , _param._predictor_2_bht_size_shifter); + if (_param._predictor_2_have_pht) + out_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY [i] = interface->set_signal_out ("predictor_2_pht_history" , _param._predictor_2_pht_size_counter); + in_BRANCH_COMPLETE_HISTORY [i] = interface->set_signal_in ("history" , _param._size_history); + if (_param._have_meta_predictor) + { + in_BRANCH_COMPLETE_DIRECTION [i] = interface->set_signal_in ("direction" , 1); + out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION [i] = interface->set_signal_out ("predictor_2_direction" , 1); + } + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#ifdef POSITION + _component->generate_file(); +#endif + + log_printf(FUNC,Meta_Predictor_Glue,"allocation","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_deallocation.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_deallocation.cpp (revision 45) @@ -0,0 +1,95 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + void Meta_Predictor_Glue::deallocation (void) + { + log_printf(FUNC,Meta_Predictor_Glue,"deallocation","Begin"); + + delete in_CLOCK; + delete in_NRESET; + + if (_param._have_meta_predictor) + { + delete [] in_PREDICT_PREDICTOR_0_ACK; + delete [] in_PREDICT_PREDICTOR_1_ACK; + } + delete [] in_PREDICT_PREDICTOR_2_ACK; + delete [] out_PREDICT_ACK ; + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + delete [] in_PREDICT_PREDICTOR_0_BHT_HISTORY; + if (_param._predictor_0_have_pht) + delete [] in_PREDICT_PREDICTOR_0_PHT_HISTORY; + if (_param._predictor_1_have_bht) + delete [] in_PREDICT_PREDICTOR_1_BHT_HISTORY; + if (_param._predictor_1_have_pht) + delete [] in_PREDICT_PREDICTOR_1_PHT_HISTORY ; + } + if (_param._predictor_2_have_bht) + delete [] in_PREDICT_PREDICTOR_2_BHT_HISTORY ; + if (_param._predictor_2_have_pht) + delete [] in_PREDICT_PREDICTOR_2_PHT_HISTORY ; + delete [] out_PREDICT_HISTORY ; + delete [] out_PREDICT_DIRECTION ; + + if (_param._have_meta_predictor) + { + delete [] in_BRANCH_COMPLETE_VAL ; + delete [] out_BRANCH_COMPLETE_PREDICTOR_2_VAL ; + + delete [] in_BRANCH_COMPLETE_PREDICTOR_0_ACK ; + delete [] in_BRANCH_COMPLETE_PREDICTOR_1_ACK ; + } + delete [] in_BRANCH_COMPLETE_PREDICTOR_2_ACK ; + delete [] out_BRANCH_COMPLETE_ACK ; + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + delete [] out_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY ; + if (_param._predictor_0_have_pht) + delete [] out_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY ; + if (_param._predictor_1_have_bht) + delete [] out_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY ; + if (_param._predictor_1_have_pht) + delete [] out_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY ; + } + if (_param._predictor_2_have_bht) + delete [] out_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY ; + if (_param._predictor_2_have_pht) + delete [] out_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY ; + delete [] in_BRANCH_COMPLETE_HISTORY ; + if (_param._have_meta_predictor) + { + delete [] in_BRANCH_COMPLETE_DIRECTION ; + delete [] out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION ; + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete _component; + + log_printf(FUNC,Meta_Predictor_Glue,"deallocation","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_branch_complete_ack.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_branch_complete_ack.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_branch_complete_ack.cpp (revision 45) @@ -0,0 +1,40 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + void Meta_Predictor_Glue::genMealy_branch_complete_ack (void) + { + log_printf(FUNC,Meta_Predictor_Glue,"genMealy_branch_complete_ack","Begin"); + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + Tcontrol_t predictor_0_ack = not _param._have_meta_predictor or PORT_READ(in_BRANCH_COMPLETE_PREDICTOR_0_ACK [i]); + Tcontrol_t predictor_1_ack = not _param._have_meta_predictor or PORT_READ(in_BRANCH_COMPLETE_PREDICTOR_1_ACK [i]); + Tcontrol_t predictor_2_ack = PORT_READ(in_BRANCH_COMPLETE_PREDICTOR_2_ACK [i]); + + PORT_WRITE(out_BRANCH_COMPLETE_ACK [i], predictor_0_ack and predictor_1_ack and predictor_2_ack); + } + + log_printf(FUNC,Meta_Predictor_Glue,"genMealy_branch_complete_ack","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_branch_complete_history.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_branch_complete_history.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_branch_complete_history.cpp (revision 45) @@ -0,0 +1,55 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" +#include "Common/include/BitManipulation.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + void Meta_Predictor_Glue::genMealy_branch_complete_history (void) + { + log_printf(FUNC,Meta_Predictor_Glue,"genMealy_branch_complete_history","Begin"); + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + Thistory_t history = PORT_READ(in_BRANCH_COMPLETE_HISTORY [i]); + + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + PORT_WRITE(out_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY [i], (history >> _param._shift_0) & gen_mask(_param._predictor_0_bht_size_shifter)); + if (_param._predictor_0_have_pht) + PORT_WRITE(out_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY [i], (history >> _param._shift_1) & gen_mask(_param._predictor_0_pht_size_counter)); + } + + if (_param._predictor_1_have_bht) + PORT_WRITE(out_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY [i], (history >> _param._shift_2) & gen_mask(_param._predictor_1_bht_size_shifter)); + if (_param._predictor_1_have_pht) + PORT_WRITE(out_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY [i], (history >> _param._shift_3) & gen_mask(_param._predictor_1_pht_size_counter)); + + if (_param._predictor_2_have_bht) + PORT_WRITE(out_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY [i], (history >> _param._shift_4) & gen_mask(_param._predictor_2_bht_size_shifter)); + if (_param._predictor_2_have_pht) + PORT_WRITE(out_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY [i], (history >> _param._shift_5) & gen_mask(_param._predictor_2_pht_size_counter)); + } + + log_printf(FUNC,Meta_Predictor_Glue,"genMealy_branch_complete_history","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_branch_complete_val.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_branch_complete_val.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_branch_complete_val.cpp (revision 45) @@ -0,0 +1,82 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + void Meta_Predictor_Glue::genMealy_branch_complete_val (void) + { + log_printf(FUNC,Meta_Predictor_Glue,"genMealy_branch_complete_val","Begin"); + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + Tcontrol_t val = PORT_READ(in_BRANCH_COMPLETE_VAL [i]); + Thistory_t history = PORT_READ(in_BRANCH_COMPLETE_HISTORY [i]); + Tcontrol_t direction = PORT_READ(in_BRANCH_COMPLETE_DIRECTION [i]); + + Tcontrol_t predictor_0_direction = (history>>(_param._shift_2-1))&1; + Tcontrol_t predictor_1_direction = (history>>(_param._shift_4-1))&1; +// Tcontrol_t predictor_2_direction = (history>>(_param._shift_6-1))&1; + +// log_printf(TRACE,Meta_Predictor_Glue,"genMealy_branch_complete_val","direction_(predictor_0 %d, predictor_1 %d, predictor_2 %d, good %d)", predictor_0_direction, predictor_1_direction, predictor_2_direction, direction); + log_printf(TRACE,Meta_Predictor_Glue,"genMealy_branch_complete_val","direction_(predictor_0 %d, predictor_1 %d, good %d)", predictor_0_direction, predictor_1_direction, direction); + + log_printf(TRACE,Meta_Predictor_Glue,"genMealy_branch_complete_val"," * direction_0 : %d >>(%d-1)",history,_param._shift_2); + log_printf(TRACE,Meta_Predictor_Glue,"genMealy_branch_complete_val"," * direction_1 : %d >>(%d-1)",history,_param._shift_4); + log_printf(TRACE,Meta_Predictor_Glue,"genMealy_branch_complete_val"," * direction_2 : %d >>(%d-1)",history,_param._shift_6); + + /* + dir_0 dir_1 dir_2 | good_dir || next_dir_2 + ------------------+-----------++----------- + 0 0 0 | 0 || no change + 1 0 0 | 0 || 1 select pred_0 but miss + 0 1 0 | 0 || 0 select pred_0 and hit + 1 1 0 | 0 || no change + 0 0 1 | 0 || no change + 1 0 1 | 0 || 1 select pred_1 and hit + 0 1 1 | 0 || 0 select pred_1 but miss + 1 1 1 | 0 || no change + 0 0 0 | 1 || no change + 1 0 0 | 1 || 0 select pred_0 and hit + 0 1 0 | 1 || 1 select pred_0 but miss + 1 1 0 | 1 || no change + 0 0 1 | 1 || no change + 1 0 1 | 1 || 0 select pred_1 but miss + 0 1 1 | 1 || 1 select pred_1 and hit + 1 1 1 | 1 || no change + + next_dir_2 = (good_dir and dir_1) or (not good_dir and dir_0) + */ + + Tcontrol_t branch_complete_predictor_2_val = val and (predictor_0_direction xor predictor_1_direction); + Tcontrol_t branch_complete_predictor_2_direction = ( (not direction and predictor_0_direction) or + ( direction and predictor_1_direction) ); + + log_printf(TRACE,Meta_Predictor_Glue,"genMealy_branch_complete_val","branch_complete_predictor_2_( val %d, direction %d)",branch_complete_predictor_2_val, branch_complete_predictor_2_direction); + + // Modify meta_predictor if have a branch_complete and twice prediction have not predict the same way + PORT_WRITE(out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION [i], branch_complete_predictor_2_direction); + PORT_WRITE(out_BRANCH_COMPLETE_PREDICTOR_2_VAL [i], branch_complete_predictor_2_val ); + } + + log_printf(FUNC,Meta_Predictor_Glue,"genMealy_branch_complete_val","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_predict_ack.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_predict_ack.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_predict_ack.cpp (revision 45) @@ -0,0 +1,41 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + void Meta_Predictor_Glue::genMealy_predict_ack (void) + { + log_printf(FUNC,Meta_Predictor_Glue,"genMealy_predict_ack","Begin"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + Tcontrol_t predictor_0_ack = not _param._have_meta_predictor or PORT_READ(in_PREDICT_PREDICTOR_0_ACK [i]); + Tcontrol_t predictor_1_ack = not _param._have_meta_predictor or PORT_READ(in_PREDICT_PREDICTOR_1_ACK [i]); + Tcontrol_t predictor_2_ack = PORT_READ(in_PREDICT_PREDICTOR_2_ACK [i]); + + PORT_WRITE(out_PREDICT_ACK [i], predictor_0_ack and predictor_1_ack and predictor_2_ack); + } + + log_printf(FUNC,Meta_Predictor_Glue,"genMealy_predict_ack","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_predict_history.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_predict_history.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_predict_history.cpp (revision 45) @@ -0,0 +1,102 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + void Meta_Predictor_Glue::genMealy_predict_history (void) + { + log_printf(FUNC,Meta_Predictor_Glue,"genMealy_predict_history","Begin"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + Thistory_t history = 0; + Tpht_history_t predictor_0_pht_history =0, predictor_1_pht_history =0, predictor_2_pht_history =0; + Tbht_history_t predictor_0_bht_history =0, predictor_1_bht_history =0, predictor_2_bht_history =0; + Tcontrol_t predictor_0_pht_direction=0, predictor_1_pht_direction=0, predictor_2_pht_direction=0; + Tcontrol_t predictor_0_bht_direction=0, predictor_1_bht_direction=0, predictor_2_bht_direction=0; + Tcontrol_t predictor_0_direction, predictor_1_direction, predictor_2_direction; + Tcontrol_t predictor_direction; + + if (_param._predictor_2_have_pht) + { + predictor_2_pht_history = PORT_READ(in_PREDICT_PREDICTOR_2_PHT_HISTORY [i]); + predictor_2_pht_direction = predictor_2_pht_history >> (_param._predictor_2_pht_size_counter-1); + history |= (predictor_2_pht_history << _param._shift_5); + } + if (_param._predictor_2_have_bht) + { + predictor_2_bht_history = PORT_READ(in_PREDICT_PREDICTOR_2_BHT_HISTORY [i]); + predictor_2_bht_direction = predictor_2_bht_history >> (_param._predictor_2_bht_size_shifter-1); + history |= (predictor_2_bht_history << _param._shift_4); + } + + predictor_2_direction = (_param._predictor_2_have_pht==true)?predictor_2_pht_direction:predictor_2_bht_direction; + + if (_param._have_meta_predictor) + { + if (_param._predictor_1_have_pht) + { + predictor_1_pht_history = PORT_READ(in_PREDICT_PREDICTOR_1_PHT_HISTORY [i]); + predictor_1_pht_direction = predictor_1_pht_history >> (_param._predictor_1_pht_size_counter-1); + history |= (predictor_1_pht_history << _param._shift_3); + } + if (_param._predictor_1_have_bht) + { + predictor_1_bht_history = PORT_READ(in_PREDICT_PREDICTOR_1_BHT_HISTORY [i]); + predictor_1_bht_direction = predictor_1_bht_history >> (_param._predictor_1_bht_size_shifter-1); + history |= (predictor_1_bht_history << _param._shift_2) ; + } + if (_param._predictor_0_have_pht) + { + predictor_0_pht_history = PORT_READ(in_PREDICT_PREDICTOR_0_PHT_HISTORY [i]); + predictor_0_pht_direction = predictor_0_pht_history >> (_param._predictor_0_pht_size_counter-1); + history |= (predictor_0_pht_history << _param._shift_1); + } + if (_param._predictor_0_have_bht) + { + predictor_0_bht_history = PORT_READ(in_PREDICT_PREDICTOR_0_BHT_HISTORY [i]); + predictor_0_bht_direction = predictor_0_bht_history >> (_param._predictor_0_bht_size_shifter-1); + history |= (predictor_0_bht_history << _param._shift_0); + } + + predictor_0_direction = (_param._predictor_0_have_pht==true)?predictor_0_pht_direction:predictor_0_bht_direction; + predictor_1_direction = (_param._predictor_1_have_pht==true)?predictor_1_pht_direction:predictor_1_bht_direction; + + // Meta predictor : take direction of prediction_2 and select the good predictor. + predictor_direction = (predictor_2_direction==0)?predictor_0_direction:predictor_1_direction; + + log_printf(TRACE,Meta_Predictor_Glue,"genMealy_predict_history","predict_direction = %d - predictor(_0 %d, _1 %d, _2 %d)",predictor_direction,predictor_0_direction,predictor_1_direction,predictor_2_direction); + } + else + { + predictor_direction = predictor_2_direction; + log_printf(TRACE,Meta_Predictor_Glue,"genMealy_predict_history","predict_direction = %d - predictor_2 %d",predictor_direction,predictor_2_direction); + } + + PORT_WRITE(out_PREDICT_DIRECTION [i], predictor_direction); + PORT_WRITE(out_PREDICT_HISTORY [i], history ); + } + + log_printf(FUNC,Meta_Predictor_Glue,"genMealy_predict_history","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_statistics.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_statistics.cpp (revision 45) @@ -0,0 +1,37 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + string Meta_Predictor_Glue::statistics (uint32_t depth) + { + log_printf(FUNC,Meta_Predictor_Glue,"statistics","Begin"); + + string txt = _stat->print(depth); + + log_printf(FUNC,Meta_Predictor_Glue,"statistics","End"); + + return txt; + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_transition.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_transition.cpp (revision 45) @@ -0,0 +1,43 @@ +#ifdef SYSTEMC +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + void Meta_Predictor_Glue::transition (void) + { + log_printf(FUNC,Meta_Predictor_Glue,"transition","Begin"); + +#ifdef STATISTICS + _stat->add(); +#endif + +#ifdef VHDL_TESTBENCH + vhdl_testbench_transition (); +#endif + + log_printf(FUNC,Meta_Predictor_Glue,"transition","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl.cpp (revision 45) @@ -0,0 +1,45 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + void Meta_Predictor_Glue::vhdl (void) + { + log_printf(FUNC,Meta_Predictor_Glue,"vhdl","Begin"); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port (vhdl); + _component ->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_printf(FUNC,Meta_Predictor_Glue,"vhdl","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_body.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_body.cpp (revision 45) @@ -0,0 +1,144 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + void Meta_Predictor_Glue::vhdl_body (Vhdl * & vhdl) + { + log_printf(FUNC,Meta_Predictor_Glue,"vhdl_body","Begin"); + vhdl->set_body (""); + vhdl->set_body (" -- predict"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + string meta_predictor_ack = (_param._have_meta_predictor==true)?("in_PREDICT_"+toString(i)+"_PREDICTOR_0_ACK and in_PREDICT_"+toString(i)+"_PREDICTOR_1_ACK"):"'1'"; + + vhdl->set_body ("out_PREDICT_"+toString(i)+"_ACK <= "+meta_predictor_ack+" and "+"in_PREDICT_"+toString(i)+"_PREDICTOR_2_ACK;"); + + uint32_t index=_param._size_history; + + + if (_param._predictor_2_have_pht) + { + vhdl->set_body ("out_PREDICT_"+toString(i)+"_HISTORY"+std_logic_range(index-1,index-_param._predictor_2_pht_size_counter)+" <= in_PREDICT_"+toString(i)+"_PREDICTOR_2_PHT_HISTORY;"); + index-= _param._predictor_2_pht_size_counter; + } + if (_param._predictor_2_have_bht) + { + vhdl->set_body ("out_PREDICT_"+toString(i)+"_HISTORY"+std_logic_range(index-1,index-_param._predictor_2_bht_size_shifter)+" <= in_PREDICT_"+toString(i)+"_PREDICTOR_2_BHT_HISTORY;"); + index-= _param._predictor_2_bht_size_shifter; + } + + if (_param._have_meta_predictor) + { + if (_param._predictor_1_have_pht) + { + vhdl->set_body ("out_PREDICT_"+toString(i)+"_HISTORY"+std_logic_range(index-1,index-_param._predictor_1_pht_size_counter)+" <= in_PREDICT_"+toString(i)+"_PREDICTOR_1_PHT_HISTORY;"); + index-= _param._predictor_1_pht_size_counter; + } + if (_param._predictor_1_have_bht) + { + vhdl->set_body ("out_PREDICT_"+toString(i)+"_HISTORY"+std_logic_range(index-1,index-_param._predictor_1_bht_size_shifter)+" <= in_PREDICT_"+toString(i)+"_PREDICTOR_1_BHT_HISTORY;"); + index-= _param._predictor_1_bht_size_shifter; + } + + if (_param._predictor_0_have_pht) + { + vhdl->set_body ("out_PREDICT_"+toString(i)+"_HISTORY"+std_logic_range(index-1,index-_param._predictor_0_pht_size_counter)+" <= in_PREDICT_"+toString(i)+"_PREDICTOR_0_PHT_HISTORY;"); + index-= _param._predictor_0_pht_size_counter; + } + if (_param._predictor_0_have_bht) + { + vhdl->set_body ("out_PREDICT_"+toString(i)+"_HISTORY"+std_logic_range(index-1,index-_param._predictor_0_bht_size_shifter)+" <= in_PREDICT_"+toString(i)+"_PREDICTOR_0_BHT_HISTORY;"); + index-= _param._predictor_0_bht_size_shifter; + } + } + + // direction of prediction + vhdl->set_body (""); + if (_param._have_meta_predictor) + vhdl->set_body ("out_PREDICT_"+toString(i)+"_DIRECTION <= predict_"+toString(i)+"_predictor_0_direction when predict_"+toString(i)+"_predictor_2_direction='0' else predict_"+toString(i)+"_predictor_1_direction;"); + else + vhdl->set_body ("out_PREDICT_"+toString(i)+"_DIRECTION <= predict_"+toString(i)+"_predictor_2_direction;"); + } + + // Interface - branch_complete + + vhdl->set_body (""); + vhdl->set_body (" -- branch_complete"); + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + // branch_complete_predictor_2 val and directionn + if (_param._have_meta_predictor) + { + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_VAL <= (branch_complete_"+toString(i)+"_predictor_0_direction xor branch_complete_"+toString(i)+"_predictor_1_direction) and "+"in_BRANCH_COMPLETE_"+toString(i)+"_VAL;"); + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_DIRECTION <= (branch_complete_"+toString(i)+"_predictor_0_direction and not in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION) or (branch_complete_"+toString(i)+"_predictor_1_direction and in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION);"); + } + + string meta_predictor_ack = (_param._have_meta_predictor==true)?("in_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_0_ACK and in_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_1_ACK"):"'1'"; + + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_ACK <= "+meta_predictor_ack+" and "+"in_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_ACK;"); + + uint32_t index=_param._size_history; + + if (_param._predictor_2_have_pht) + { + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_PHT_HISTORY <= in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"+std_logic_range(index-1,index-_param._predictor_2_pht_size_counter)+";"); + index-= _param._predictor_2_pht_size_counter; + } + if (_param._predictor_2_have_bht) + { + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_BHT_HISTORY <= in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"+std_logic_range(index-1,index-_param._predictor_2_bht_size_shifter)+";"); + index-= _param._predictor_2_bht_size_shifter; + } + + if (_param._have_meta_predictor) + { + if (_param._predictor_1_have_pht) + { + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_1_PHT_HISTORY <= in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"+std_logic_range(index-1,index-_param._predictor_1_pht_size_counter)+";"); + index-= _param._predictor_1_pht_size_counter; + } + if (_param._predictor_1_have_bht) + { + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_1_BHT_HISTORY <= in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"+std_logic_range(index-1,index-_param._predictor_1_bht_size_shifter)+";"); + index-= _param._predictor_1_bht_size_shifter; + } + + if (_param._predictor_0_have_pht) + { + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_0_PHT_HISTORY <= in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"+std_logic_range(index-1,index-_param._predictor_0_pht_size_counter)+";"); + index-= _param._predictor_0_pht_size_counter; + } + if (_param._predictor_0_have_bht) + { + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_0_BHT_HISTORY <= in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"+std_logic_range(index-1,index-_param._predictor_0_bht_size_shifter)+";"); + index-= _param._predictor_0_bht_size_shifter; + } + } + } + + log_printf(FUNC,Meta_Predictor_Glue,"vhdl_body","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_declaration.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_declaration.cpp (revision 45) @@ -0,0 +1,75 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + void Meta_Predictor_Glue::vhdl_declaration (Vhdl * & vhdl) + { + log_printf(FUNC,Meta_Predictor_Glue,"vhdl_declaration","Begin"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_pht) + vhdl->set_alias ("predict_"+toString(i)+"_predictor_0_direction",std_logic(1), "in_PREDICT_"+toString(i)+"_PREDICTOR_0_PHT_HISTORY",std_logic_range(_param._predictor_0_pht_size_counter-1,_param._predictor_0_pht_size_counter-1)); + else + vhdl->set_alias ("predict_"+toString(i)+"_predictor_0_direction",std_logic(1), "in_PREDICT_"+toString(i)+"_PREDICTOR_0_BHT_HISTORY",std_logic_range(_param._predictor_0_bht_size_shifter-1,_param._predictor_0_bht_size_shifter-1)); + if (_param._predictor_1_have_pht) + vhdl->set_alias ("predict_"+toString(i)+"_predictor_1_direction",std_logic(1), "in_PREDICT_"+toString(i)+"_PREDICTOR_1_PHT_HISTORY",std_logic_range(_param._predictor_1_pht_size_counter-1,_param._predictor_1_pht_size_counter-1)); + else + vhdl->set_alias ("predict_"+toString(i)+"_predictor_1_direction",std_logic(1), "in_PREDICT_"+toString(i)+"_PREDICTOR_1_BHT_HISTORY",std_logic_range(_param._predictor_1_bht_size_shifter-1,_param._predictor_1_bht_size_shifter-1)); + } + + if (_param._predictor_2_have_pht) + vhdl->set_alias ("predict_"+toString(i)+"_predictor_2_direction",std_logic(1), "in_PREDICT_"+toString(i)+"_PREDICTOR_2_PHT_HISTORY",std_logic_range(_param._predictor_2_pht_size_counter-1,_param._predictor_2_pht_size_counter-1)); + else + vhdl->set_alias ("predict_"+toString(i)+"_predictor_2_direction",std_logic(1), "in_PREDICT_"+toString(i)+"_PREDICTOR_2_BHT_HISTORY",std_logic_range(_param._predictor_2_bht_size_shifter-1,_param._predictor_2_bht_size_shifter-1)); + } + + if (_param._have_meta_predictor) + { + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { +// if (_param._predictor_2_have_pht) +// vhdl->set_alias ("branch_complete_"+toString(i)+"_predictor_2_direction",std_logic(1)," in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY",std_logic_range(_param._shift_6-1, _param._shift_6-1)); +// else +// vhdl->set_alias ("branch_complete_"+toString(i)+"_predictor_2_direction",std_logic(1)," in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY",std_logic_range(_param._shift_5-1, _param._shift_5-1)); + + if (_param._predictor_1_have_pht) + vhdl->set_alias ("branch_complete_"+toString(i)+"_predictor_1_direction",std_logic(1)," in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY",std_logic_range(_param._shift_4-1, _param._shift_4-1)); + else + vhdl->set_alias ("branch_complete_"+toString(i)+"_predictor_1_direction",std_logic(1)," in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY",std_logic_range(_param._shift_3-1, _param._shift_3-1)); + + if (_param._predictor_0_have_pht) + vhdl->set_alias ("branch_complete_"+toString(i)+"_predictor_0_direction",std_logic(1)," in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY",std_logic_range(_param._shift_2-1, _param._shift_2-1)); + else + vhdl->set_alias ("branch_complete_"+toString(i)+"_predictor_0_direction",std_logic(1)," in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY",std_logic_range(_param._shift_1-1, _param._shift_1-1)); + + } + } + + log_printf(FUNC,Meta_Predictor_Glue,"vhdl_declaration","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_port.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_port.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_port.cpp (revision 45) @@ -0,0 +1,100 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + void Meta_Predictor_Glue::vhdl_port (Vhdl & vhdl) + { + log_printf(FUNC,Meta_Predictor_Glue,"vhdl_port","Begin"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + if (_param._have_meta_predictor) + { + vhdl.set_port (" in_PREDICT_PREDICTOR_0_ACK_"+toString(i)+" ", IN, 1); + vhdl.set_port (" in_PREDICT_PREDICTOR_1_ACK_"+toString(i)+" ", IN, 1); + } + vhdl.set_port (" in_PREDICT_PREDICTOR_2_ACK_"+toString(i)+" ", IN, 1); + vhdl.set_port ("out_PREDICT_ACK_"+toString(i)+" ",OUT, 1); + + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + vhdl.set_port (" in_PREDICT_PREDICTOR_0_BHT_HISTORY_"+toString(i)+" ", IN,_param._predictor_0_bht_size_shifter); + if (_param._predictor_0_have_pht) + vhdl.set_port (" in_PREDICT_PREDICTOR_0_PHT_HISTORY_"+toString(i)+" ", IN,_param._predictor_0_pht_size_counter); + if (_param._predictor_1_have_bht) + vhdl.set_port (" in_PREDICT_PREDICTOR_1_BHT_HISTORY_"+toString(i)+" ", IN,_param._predictor_1_bht_size_shifter); + if (_param._predictor_1_have_pht) + vhdl.set_port (" in_PREDICT_PREDICTOR_1_PHT_HISTORY_"+toString(i)+" ", IN,_param._predictor_1_pht_size_counter); + } + if (_param._predictor_2_have_bht) + vhdl.set_port (" in_PREDICT_PREDICTOR_2_BHT_HISTORY_"+toString(i)+" ", IN,_param._predictor_2_bht_size_shifter); + if (_param._predictor_2_have_pht) + vhdl.set_port (" in_PREDICT_PREDICTOR_2_PHT_HISTORY_"+toString(i)+" ", IN,_param._predictor_2_pht_size_counter); + + vhdl.set_port ("out_PREDICT_HISTORY_"+toString(i)+" ",OUT,_param._size_history); + vhdl.set_port ("out_PREDICT_DIRECTION_"+toString(i)+" ",OUT,1); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + if (_param._have_meta_predictor) + { + vhdl.set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", IN, 1); + vhdl.set_port ("out_BRANCH_COMPLETE_PREDICTOR_2_VAL_"+toString(i)+" ",OUT, 1); + + vhdl.set_port (" in_BRANCH_COMPLETE_PREDICTOR_0_ACK_"+toString(i)+" ", IN, 1); + vhdl.set_port (" in_BRANCH_COMPLETE_PREDICTOR_1_ACK_"+toString(i)+" ", IN, 1); + } + vhdl.set_port (" in_BRANCH_COMPLETE_PREDICTOR_2_ACK_"+toString(i)+" ", IN, 1); + vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" ",OUT, 1); + + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + vhdl.set_port ("out_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY_"+toString(i)+"",OUT,_param._predictor_0_bht_size_shifter); + if (_param._predictor_0_have_pht) + vhdl.set_port ("out_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY_"+toString(i)+"",OUT,_param._predictor_0_pht_size_counter); + if (_param._predictor_1_have_bht) + vhdl.set_port ("out_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY_"+toString(i)+"",OUT,_param._predictor_1_bht_size_shifter); + if (_param._predictor_1_have_pht) + vhdl.set_port ("out_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY_"+toString(i)+"",OUT,_param._predictor_1_pht_size_counter); + } + if (_param._predictor_2_have_bht) + vhdl.set_port ("out_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY_"+toString(i)+"",OUT,_param._predictor_2_bht_size_shifter); + if (_param._predictor_2_have_pht) + vhdl.set_port ("out_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY_"+toString(i)+"",OUT,_param._predictor_2_pht_size_counter); + + vhdl.set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+" ", IN,_param._size_history); + if (_param._have_meta_predictor) + { + vhdl.set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+" ", IN,1); + vhdl.set_port ("out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION_"+toString(i)+" ",OUT,1); + } + } + + log_printf(FUNC,Meta_Predictor_Glue,"vhdl_port","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_testbench_label.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_testbench_label.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_testbench_label.cpp (revision 45) @@ -0,0 +1,35 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + void Meta_Predictor_Glue::vhdl_testbench_label (string label) + { + log_printf(FUNC,Meta_Predictor_Glue,"vhdl_testbench_label","Begin"); + +#ifdef VHDL_TESTBENCH + _vhdl_testbench->add_label(label); +#endif + + log_printf(FUNC,Meta_Predictor_Glue,"vhdl_testbench_label","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_testbench_port.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_testbench_port.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_testbench_port.cpp (revision 45) @@ -0,0 +1,100 @@ +#ifdef VHDL_TESTBENCH +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + void Meta_Predictor_Glue::vhdl_testbench_port () + { + log_printf(FUNC,Meta_Predictor_Glue,"vhdl_testbench_port","Begin"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + if (_param._have_meta_predictor) + { + _vhdl_testbench->set_port (" in_PREDICT_PREDICTOR_0_ACK_"+toString(i)+" ", IN, 1); + _vhdl_testbench->set_port (" in_PREDICT_PREDICTOR_1_ACK_"+toString(i)+" ", IN, 1); + } + _vhdl_testbench->set_port (" in_PREDICT_PREDICTOR_2_ACK_"+toString(i)+" ", IN, 1); + _vhdl_testbench->set_port ("out_PREDICT_ACK_"+toString(i)+" ",OUT, 1); + + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + _vhdl_testbench->set_port (" in_PREDICT_PREDICTOR_0_BHT_HISTORY_"+toString(i)+" ", IN,_param._predictor_0_bht_size_shifter); + if (_param._predictor_0_have_pht) + _vhdl_testbench->set_port (" in_PREDICT_PREDICTOR_0_PHT_HISTORY_"+toString(i)+" ", IN,_param._predictor_0_pht_size_counter); + if (_param._predictor_1_have_bht) + _vhdl_testbench->set_port (" in_PREDICT_PREDICTOR_1_BHT_HISTORY_"+toString(i)+" ", IN,_param._predictor_1_bht_size_shifter); + if (_param._predictor_1_have_pht) + _vhdl_testbench->set_port (" in_PREDICT_PREDICTOR_1_PHT_HISTORY_"+toString(i)+" ", IN,_param._predictor_1_pht_size_counter); + } + if (_param._predictor_2_have_bht) + _vhdl_testbench->set_port (" in_PREDICT_PREDICTOR_2_BHT_HISTORY_"+toString(i)+" ", IN,_param._predictor_2_bht_size_shifter); + if (_param._predictor_2_have_pht) + _vhdl_testbench->set_port (" in_PREDICT_PREDICTOR_2_PHT_HISTORY_"+toString(i)+" ", IN,_param._predictor_2_pht_size_counter); + + _vhdl_testbench->set_port ("out_PREDICT_HISTORY_"+toString(i)+" ",OUT,_param._size_history); + _vhdl_testbench->set_port ("out_PREDICT_DIRECTION_"+toString(i)+" ",OUT,1); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + if (_param._have_meta_predictor) + { + _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", IN, 1); + _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_PREDICTOR_2_VAL_"+toString(i)+" ",OUT, 1); + + _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_PREDICTOR_0_ACK_"+toString(i)+" ", IN, 1); + _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_PREDICTOR_1_ACK_"+toString(i)+" ", IN, 1); + } + _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_PREDICTOR_2_ACK_"+toString(i)+" ", IN, 1); + _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" ",OUT, 1); + + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY_"+toString(i)+"",OUT,_param._predictor_0_bht_size_shifter); + if (_param._predictor_0_have_pht) + _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY_"+toString(i)+"",OUT,_param._predictor_0_pht_size_counter); + if (_param._predictor_1_have_bht) + _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY_"+toString(i)+"",OUT,_param._predictor_1_bht_size_shifter); + if (_param._predictor_1_have_pht) + _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY_"+toString(i)+"",OUT,_param._predictor_1_pht_size_counter); + } + if (_param._predictor_2_have_bht) + _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY_"+toString(i)+"",OUT,_param._predictor_2_bht_size_shifter); + if (_param._predictor_2_have_pht) + _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY_"+toString(i)+"",OUT,_param._predictor_2_pht_size_counter); + + _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+" ", IN,_param._size_history); + if (_param._have_meta_predictor) + { + _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+" ", IN,1); + _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION_"+toString(i)+" ",OUT,1); + } + } + + log_printf(FUNC,Meta_Predictor_Glue,"vhdl_testbench_port","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_testbench_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_testbench_transition.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_testbench_transition.cpp (revision 45) @@ -0,0 +1,36 @@ +#ifdef VHDL_TESTBENCH +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + void Meta_Predictor_Glue::vhdl_testbench_transition () + { + log_printf(FUNC,Meta_Predictor_Glue,"vhdl_testbench_transition","Begin"); + +// sc_start(0); + _interfaces->testbench(); + + log_printf(FUNC,Meta_Predictor_Glue,"vhdl_testbench_transition","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Parameters.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Parameters.cpp (revision 45) @@ -0,0 +1,119 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Parameters.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + Parameters::Parameters (bool have_meta_predictor , + bool predictor_0_have_bht , + uint32_t predictor_0_bht_size_shifter , + bool predictor_0_have_pht , + uint32_t predictor_0_pht_size_counter , + bool predictor_1_have_bht , + uint32_t predictor_1_bht_size_shifter , + bool predictor_1_have_pht , + uint32_t predictor_1_pht_size_counter , + bool predictor_2_have_bht , + uint32_t predictor_2_bht_size_shifter , + bool predictor_2_have_pht , + uint32_t predictor_2_pht_size_counter , + uint32_t nb_prediction , + uint32_t nb_branch_complete ) : + _have_meta_predictor (have_meta_predictor ), + + _predictor_0_have_bht ((have_meta_predictor==false)?false:predictor_0_have_bht ), + _predictor_0_bht_size_shifter ((_predictor_0_have_bht==false)?0:predictor_0_bht_size_shifter ), + _predictor_0_have_pht ((have_meta_predictor==false)?false:predictor_0_have_pht ), + _predictor_0_pht_size_counter ((_predictor_0_have_pht==false)?0:predictor_0_pht_size_counter ), + + _predictor_1_have_bht ((have_meta_predictor==false)?false:predictor_1_have_bht ), + _predictor_1_bht_size_shifter ((_predictor_1_have_bht==false)?0:predictor_1_bht_size_shifter ), + _predictor_1_have_pht ((have_meta_predictor==false)?false:predictor_1_have_pht ), + _predictor_1_pht_size_counter ((_predictor_1_have_pht==false)?0:predictor_1_pht_size_counter ), + + _predictor_2_have_bht (predictor_2_have_bht ), + _predictor_2_bht_size_shifter ((_predictor_2_have_bht==false)?0:predictor_2_bht_size_shifter ), + _predictor_2_have_pht (predictor_2_have_pht ), + _predictor_2_pht_size_counter ((_predictor_2_have_pht==false)?0:predictor_2_pht_size_counter ), + + _nb_prediction (nb_prediction ), + _nb_branch_complete (nb_branch_complete ), + + _size_history (_predictor_0_bht_size_shifter + _predictor_0_pht_size_counter + + _predictor_1_bht_size_shifter + _predictor_1_pht_size_counter + + _predictor_2_bht_size_shifter + _predictor_2_pht_size_counter ), + + _shift_0 (0), + _shift_1 (_shift_0 + _predictor_0_bht_size_shifter), + _shift_2 (_shift_1 + _predictor_0_pht_size_counter), + _shift_3 (_shift_2 + _predictor_1_bht_size_shifter), + _shift_4 (_shift_3 + _predictor_1_pht_size_counter), + _shift_5 (_shift_4 + _predictor_2_bht_size_shifter), + _shift_6 (_shift_5 + _predictor_2_pht_size_counter) + { + log_printf(FUNC,Meta_Predictor_Glue,"Parameters","Begin"); + test(); + log_printf(FUNC,Meta_Predictor_Glue,"Parameters","End"); + }; + + Parameters::Parameters (Parameters & param): + _have_meta_predictor (param._have_meta_predictor ), + + _predictor_0_have_bht (param._predictor_0_have_bht ), + _predictor_0_bht_size_shifter (param._predictor_0_bht_size_shifter ), + _predictor_0_have_pht (param._predictor_0_have_pht ), + _predictor_0_pht_size_counter (param._predictor_0_pht_size_counter ), + + _predictor_1_have_bht (param._predictor_1_have_bht ), + _predictor_1_bht_size_shifter (param._predictor_1_bht_size_shifter ), + _predictor_1_have_pht (param._predictor_1_have_pht ), + _predictor_1_pht_size_counter (param._predictor_1_pht_size_counter ), + + _predictor_2_have_bht (param._predictor_2_have_bht ), + _predictor_2_bht_size_shifter (param._predictor_2_bht_size_shifter ), + _predictor_2_have_pht (param._predictor_2_have_pht ), + _predictor_2_pht_size_counter (param._predictor_2_pht_size_counter ), + + _nb_prediction (param._nb_prediction ), + _nb_branch_complete (param._nb_branch_complete ), + + _size_history (param._size_history ), + + _shift_0 (param._shift_0 ), + _shift_1 (param._shift_1 ), + _shift_2 (param._shift_2 ), + _shift_3 (param._shift_3 ), + _shift_4 (param._shift_4 ), + _shift_5 (param._shift_5 ), + _shift_6 (param._shift_6 ) + + { + log_printf(FUNC,Meta_Predictor_Glue,"Parameters","Begin"); + test(); + log_printf(FUNC,Meta_Predictor_Glue,"Parameters","End"); + }; + + Parameters::~Parameters () + { + log_printf(FUNC,Meta_Predictor_Glue,"~Parameters","Begin"); + log_printf(FUNC,Meta_Predictor_Glue,"~Parameters","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Parameters_msg_error.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Parameters_msg_error.cpp (revision 45) @@ -0,0 +1,51 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Types.h" +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + string Parameters::msg_error(void) + { + log_printf(FUNC,Meta_Predictor_Glue,"msg_error","Begin"); + + string msg = ""; + + // note : size_shifter and size_counter is set at 0 if not need + if ((8*sizeof(Thistory_t)) < _size_history) + { + msg += " - type \"Thistory_t\" is too little to the total size of history (shifter's size and counter's size)\n"; + msg += " * predictor_0_bht_size_shifter : " + toString(_predictor_0_bht_size_shifter) + "\n"; + msg += " * predictor_0_pht_size_counter : " + toString(_predictor_0_pht_size_counter) + "\n"; + msg += " * predictor_1_bht_size_shifter : " + toString(_predictor_1_bht_size_shifter) + "\n"; + msg += " * predictor_1_pht_size_counter : " + toString(_predictor_1_pht_size_counter) + "\n"; + msg += " * predictor_2_bht_size_shifter : " + toString(_predictor_2_bht_size_shifter) + "\n"; + msg += " * predictor_2_pht_size_counter : " + toString(_predictor_2_pht_size_counter) + "\n"; + msg += " * Thistory_t (bits): " + toString(8*(sizeof(Thistory_t))) + "\n"; + } + + return msg; + + log_printf(FUNC,Meta_Predictor_Glue,"msg_error","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Parameters_print.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Parameters_print.cpp (revision 45) @@ -0,0 +1,99 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Parameters.h" +#include "Behavioural/include/XML.h" +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + string Parameters::print (uint32_t depth) + { + log_printf(FUNC,Meta_Predictor_Glue,"print","Begin"); + + XML xml ("meta_predictor_glue"); + + xml.balise_open("meta_predictor_glue"); + + xml. singleton_begin("have_meta_predictor "); + xml. attribut("value",toString(_have_meta_predictor )); + xml. singleton_end(); + + xml. singleton_begin("predictor_0_have_bht "); + xml. attribut("value",toString(_predictor_0_have_bht )); + xml. singleton_end(); + xml. singleton_begin("predictor_0_bht_size_shifter "); + xml. attribut("value",toString(_predictor_0_bht_size_shifter )); + xml. singleton_end(); + xml. singleton_begin("predictor_0_have_pht "); + xml. attribut("value",toString(_predictor_0_have_pht )); + xml. singleton_end(); + xml. singleton_begin("predictor_0_pht_size_counter "); + xml. attribut("value",toString(_predictor_0_pht_size_counter )); + xml. singleton_end(); + + xml. singleton_begin("predictor_1_have_bht "); + xml. attribut("value",toString(_predictor_1_have_bht )); + xml. singleton_end(); + xml. singleton_begin("predictor_1_bht_size_shifter "); + xml. attribut("value",toString(_predictor_1_bht_size_shifter )); + xml. singleton_end(); + xml. singleton_begin("predictor_1_have_pht "); + xml. attribut("value",toString(_predictor_1_have_pht )); + xml. singleton_end(); + xml. singleton_begin("predictor_1_pht_size_counter "); + xml. attribut("value",toString(_predictor_1_pht_size_counter )); + xml. singleton_end(); + + xml. singleton_begin("predictor_2_have_bht "); + xml. attribut("value",toString(_predictor_2_have_bht )); + xml. singleton_end(); + xml. singleton_begin("predictor_2_bht_size_shifter "); + xml. attribut("value",toString(_predictor_2_bht_size_shifter )); + xml. singleton_end(); + xml. singleton_begin("predictor_2_have_pht "); + xml. attribut("value",toString(_predictor_2_have_pht )); + xml. singleton_end(); + xml. singleton_begin("predictor_2_pht_size_counter "); + xml. attribut("value",toString(_predictor_2_pht_size_counter )); + xml. singleton_end(); + + xml. singleton_begin("nb_prediction "); + xml. attribut("value",toString(_nb_prediction )); + xml. singleton_end(); + xml. singleton_begin("nb_branch_complete "); + xml. attribut("value",toString(_nb_branch_complete )); + xml. singleton_end(); + + xml.balise_close(); + + log_printf(FUNC,Meta_Predictor_Glue,"print","End"); + + return xml.get_body(depth); + }; + + ostream& operator<< (ostream& output_stream , + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::meta_predictor_glue::Parameters & x) + { + output_stream << x.print(0); + + return output_stream; + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Statistics.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Statistics.cpp (revision 45) @@ -0,0 +1,44 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Statistics.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + Statistics::Statistics (string name , + morpheo::behavioural::Parameters_Statistics parameters_statistics , + Parameters parameters + ) : + morpheo::behavioural::Statistics(name , + parameters_statistics ), + _parameters(parameters) + { + log_printf(FUNC,Meta_Predictor_Glue,"Statistics","Begin"); + log_printf(FUNC,Meta_Predictor_Glue,"Statistics","End"); + }; + + Statistics::~Statistics () + { + log_printf(FUNC,Meta_Predictor_Glue,"~Statistics","Begin"); + log_printf(FUNC,Meta_Predictor_Glue,"~Statistics","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Statistics_add.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Statistics_add.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Statistics_add.cpp (revision 45) @@ -0,0 +1,35 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + void Statistics::add () + { + log_printf(FUNC,Meta_Predictor_Glue,"add","Begin"); + log_printf(FUNC,Meta_Predictor_Glue,"add","End"); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Statistics_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Statistics_print.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Statistics_print.cpp (revision 45) @@ -0,0 +1,53 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + string Statistics::print (uint32_t depth) + { + log_printf(FUNC,Meta_Predictor_Glue,"print","Begin"); + + string tab = string(depth,'\t'); + ostringstream msg; + + msg << tab << "" << endl + << print_body(depth+1) << endl + << tab << "" << endl; + + log_printf(FUNC,Meta_Predictor_Glue,"print","End"); + + return msg.str(); + }; + + ostream& operator<< (ostream& output_stream , + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::meta_predictor_glue::Statistics & x) + { + output_stream << x.print(0); + + return output_stream; + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Statistics_print_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Statistics_print_body.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor_Glue/src/Statistics_print_body.cpp (revision 45) @@ -0,0 +1,43 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace meta_predictor_glue { + + + string Statistics::print_body (uint32_t depth) + { + log_printf(FUNC,Meta_Predictor_Glue,"print_body","Begin"); + + string tab = string(depth,'\t'); + ostringstream msg; + + msg << tab << ""; + + log_printf(FUNC,Meta_Predictor_Glue,"print_body","End"); + + return msg.str(); + }; + +}; // end namespace meta_predictor_glue +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/Makefile (revision 45) @@ -0,0 +1,29 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_MORPHEO = ../../../../.. + +LIBRARY = $(Meta_Predictor_LIBRARY) + +DIR_LIBRARY = $(Meta_Predictor_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Meta_Predictor_library + +library_clean : Meta_Predictor_library_clean + +include ../Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/config-alpha_21264.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/config-alpha_21264.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/config-alpha_21264.cfg (revision 45) @@ -0,0 +1,26 @@ +Meta_Predictor +1 1 +1 # have_meta_predictor +1 1 +1 # predictor_0_have_bht +10 10 +1 # predictor_0_bht_size_shifter +1024 1024 *2 # predictor_0_bht_nb_shifter +1 1 +1 # predictor_0_have_pht +3 3 +1 # predictor_0_pht_size_counter +1024 1024 *2 # predictor_0_pht_nb_counter +0 0 +1 # predictor_0_pht_size_address_share +1 1 +1 # predictor_1_have_bht +12 12 +1 # predictor_1_bht_size_shifter +2 2 *2 # predictor_1_bht_nb_shifter +1 1 +1 # predictor_1_have_pht +2 2 +1 # predictor_1_pht_size_counter +4096 4096 *2 # predictor_1_pht_nb_counter +0 0 +1 # predictor_1_pht_size_address_share +0 0 +1 # predictor_2_have_bht +4 4 +1 # predictor_2_bht_size_shifter +256 256 *2 # predictor_2_bht_nb_shifter +1 1 +1 # predictor_2_have_pht +2 2 +1 # predictor_2_pht_size_counter +4096 4096 *2 # predictor_2_pht_nb_counter +0 0 +1 # predictor_2_pht_size_address_share +30 30 *2 # size_address +1 1 +1 # nb_prediction +1 1 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/configuration.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/configuration.cfg (revision 45) @@ -0,0 +1,26 @@ +Meta_Predictor +1 1 +1 # have_meta_predictor +1 1 +1 # predictor_0_have_bht +10 10 +1 # predictor_0_bht_size_shifter +1024 1024 *2 # predictor_0_bht_nb_shifter +1 1 +1 # predictor_0_have_pht +3 3 +1 # predictor_0_pht_size_counter +1024 1024 *2 # predictor_0_pht_nb_counter +0 0 +1 # predictor_0_pht_size_address_share +1 1 +1 # predictor_1_have_bht +12 12 +1 # predictor_1_bht_size_shifter +2 2 *2 # predictor_1_bht_nb_shifter +1 1 +1 # predictor_1_have_pht +2 2 +1 # predictor_1_pht_size_counter +4096 4096 *2 # predictor_1_pht_nb_counter +0 0 +1 # predictor_1_pht_size_address_share +0 0 +1 # predictor_2_have_bht +4 4 +1 # predictor_2_bht_size_shifter +256 256 *2 # predictor_2_bht_nb_shifter +1 1 +1 # predictor_2_have_pht +2 2 +1 # predictor_2_pht_size_counter +4096 4096 *2 # predictor_2_pht_nb_counter +0 0 +1 # predictor_2_pht_size_address_share +30 30 *2 # size_address +1 1 +1 # nb_prediction +1 1 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/include/test.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/include/test.h (revision 45) @@ -0,0 +1,26 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include +#include + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::stage_1_ifetch; +using namespace morpheo::behavioural::stage_1_ifetch::predictor; +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor; + +void test (string name, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::Parameters param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/mkf.info =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/mkf.info (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/mkf.info (revision 45) @@ -0,0 +1,6 @@ + +# Meta_Predictor_0 +target_dep all Meta_Predictor_0.ngc +target_dep Meta_Predictor_0.ngc Meta_Predictor_0.prj +target_dep Meta_Predictor_0.prj Meta_Predictor_0_Meta_Predictor_Glue_Pack.vhdl Meta_Predictor_0_Meta_Predictor_Glue.vhdl Meta_Predictor_0_Pack.vhdl Meta_Predictor_0_Two_Level_Branch_Predictor_2_Pack.vhdl Meta_Predictor_0_Two_Level_Branch_Predictor_2_Pattern_History_Table_Counter_Pack.vhdl Meta_Predictor_0_Two_Level_Branch_Predictor_2_Pattern_History_Table_Counter.vhdl Meta_Predictor_0_Two_Level_Branch_Predictor_2_Pattern_History_Table_Pack.vhdl Meta_Predictor_0_Two_Level_Branch_Predictor_2_Pattern_History_Table_RegisterFile_Pack.vhdl Meta_Predictor_0_Two_Level_Branch_Predictor_2_Pattern_History_Table_RegisterFile.vhdl Meta_Predictor_0_Two_Level_Branch_Predictor_2_Pattern_History_Table.vhdl Meta_Predictor_0_Two_Level_Branch_Predictor_2_Two_Level_Branch_Predictor_Glue_Pack.vhdl Meta_Predictor_0_Two_Level_Branch_Predictor_2_Two_Level_Branch_Predictor_Glue.vhdl Meta_Predictor_0_Two_Level_Branch_Predictor_2.vhdl Meta_Predictor_0.vhdl + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/src/main.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/src/main.cpp (revision 45) @@ -0,0 +1,131 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/SelfTest/include/test.h" + +#define NB_PARAMS 25 + +void usage (string exec) +{ + cerr << " " << exec << " name_instance list_params" << endl + << "list_params is :" << endl + << " - have_meta_predictor (bool )" << endl + << " - predictor_0_have_bht (bool )" << endl + << " - predictor_0_bht_size_shifter (uint32_t)" << endl + << " - predictor_0_bht_nb_shifter (uint32_t)" << endl + << " - predictor_0_have_pht (bool )" << endl + << " - predictor_0_pht_size_counter (uint32_t)" << endl + << " - predictor_0_pht_nb_counter (uint32_t)" << endl + << " - predictor_0_pht_size_address_share (uint32_t)" << endl + << " - predictor_1_have_bht (bool )" << endl + << " - predictor_1_bht_size_shifter (uint32_t)" << endl + << " - predictor_1_bht_nb_shifter (uint32_t)" << endl + << " - predictor_1_have_pht (bool )" << endl + << " - predictor_1_pht_size_counter (uint32_t)" << endl + << " - predictor_1_pht_nb_counter (uint32_t)" << endl + << " - predictor_1_pht_size_address_share (uint32_t)" << endl + << " - predictor_2_have_bht (bool )" << endl + << " - predictor_2_bht_size_shifter (uint32_t)" << endl + << " - predictor_2_bht_nb_shifter (uint32_t)" << endl + << " - predictor_2_have_pht (bool )" << endl + << " - predictor_2_pht_size_counter (uint32_t)" << endl + << " - predictor_2_pht_nb_counter (uint32_t)" << endl + << " - predictor_2_pht_size_address_share (uint32_t)" << endl + << " - size_address (uint32_t)" << endl + << " - nb_prediction (uint32_t)" << endl + << " - nb_branch_complete (uint32_t)" << endl; + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc != 2+NB_PARAMS) + usage (argv[0]); + + const string name = argv[1]; + + const bool have_meta_predictor = atoi(argv[ 2]); + + const bool predictor_0_have_bht = atoi(argv[ 3]); + const uint32_t predictor_0_bht_size_shifter = atoi(argv[ 4]); + const uint32_t predictor_0_bht_nb_shifter = atoi(argv[ 5]); + const bool predictor_0_have_pht = atoi(argv[ 6]); + const uint32_t predictor_0_pht_size_counter = atoi(argv[ 7]); + const uint32_t predictor_0_pht_nb_counter = atoi(argv[ 8]); + const uint32_t predictor_0_pht_size_address_share= atoi(argv[ 9]); + + const bool predictor_1_have_bht = atoi(argv[10]); + const uint32_t predictor_1_bht_size_shifter = atoi(argv[11]); + const uint32_t predictor_1_bht_nb_shifter = atoi(argv[12]); + const bool predictor_1_have_pht = atoi(argv[13]); + const uint32_t predictor_1_pht_size_counter = atoi(argv[14]); + const uint32_t predictor_1_pht_nb_counter = atoi(argv[15]); + const uint32_t predictor_1_pht_size_address_share= atoi(argv[16]); + + const bool predictor_2_have_bht = atoi(argv[17]); + const uint32_t predictor_2_bht_size_shifter = atoi(argv[18]); + const uint32_t predictor_2_bht_nb_shifter = atoi(argv[19]); + const bool predictor_2_have_pht = atoi(argv[20]); + const uint32_t predictor_2_pht_size_counter = atoi(argv[21]); + const uint32_t predictor_2_pht_nb_counter = atoi(argv[22]); + const uint32_t predictor_2_pht_size_address_share= atoi(argv[23]); + + const uint32_t size_address = atoi(argv[24]); + const uint32_t nb_prediction = atoi(argv[25]); + const uint32_t nb_branch_complete = atoi(argv[26]); + + try + { + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::Parameters param (have_meta_predictor , + predictor_0_have_bht , + predictor_0_bht_size_shifter , + predictor_0_bht_nb_shifter , + predictor_0_have_pht , + predictor_0_pht_size_counter , + predictor_0_pht_nb_counter , + predictor_0_pht_size_address_share, + predictor_1_have_bht , + predictor_1_bht_size_shifter , + predictor_1_bht_nb_shifter , + predictor_1_have_pht , + predictor_1_pht_size_counter , + predictor_1_pht_nb_counter , + predictor_1_pht_size_address_share, + predictor_2_have_bht , + predictor_2_bht_size_shifter , + predictor_2_bht_nb_shifter , + predictor_2_have_pht , + predictor_2_pht_size_counter , + predictor_2_pht_nb_counter , + predictor_2_pht_size_address_share, + size_address , + nb_prediction , + nb_branch_complete ); + + cout << param.print(1); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + cout << "<" << name << "> : " << error.what (); + exit (EXIT_FAILURE); + } + catch (...) + { + cerr << "<" << name << "> : This test must generate a error" << endl; + exit (EXIT_FAILURE); + } + + return (EXIT_SUCCESS); +} + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/src/test.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/src/test.cpp (revision 45) @@ -0,0 +1,156 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#define NB_ITERATION 1 + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/SelfTest/include/test.h" +#include "Common/include/Test.h" + +void test (string name, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::Parameters _param) +{ + cout << "<" << name << "> : Simulation SystemC" << endl; + + Meta_Predictor * _Meta_Predictor = new Meta_Predictor (name.c_str(), +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics(5,50), +#endif + _param); + +#ifdef SYSTEMC + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + sc_clock * CLOCK ; + sc_signal * NRESET ; + + // Interface Predict + sc_signal ** PREDICT_VAL ; + sc_signal ** PREDICT_ACK ; + sc_signal ** PREDICT_ADDRESS ; + sc_signal ** PREDICT_HISTORY ; + sc_signal ** PREDICT_DIRECTION ; + + // Interface Branch_complete + sc_signal ** BRANCH_COMPLETE_VAL ; + sc_signal ** BRANCH_COMPLETE_ACK ; + sc_signal ** BRANCH_COMPLETE_ADDRESS ; + sc_signal ** BRANCH_COMPLETE_HISTORY ; + sc_signal ** BRANCH_COMPLETE_DIRECTION ; + + string rename; + + CLOCK = new sc_clock ("clock", 1.0, 0.5); + NRESET = new sc_signal ("NRESET"); + + PREDICT_VAL = new sc_signal * [_param._nb_prediction ]; + PREDICT_ACK = new sc_signal * [_param._nb_prediction ]; + PREDICT_ADDRESS = new sc_signal * [_param._nb_prediction ]; + PREDICT_HISTORY = new sc_signal * [_param._nb_prediction ]; + PREDICT_DIRECTION = new sc_signal * [_param._nb_prediction ]; + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + rename = "PREDICT_VAL_" +toString(i); + PREDICT_VAL [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_ACK_" +toString(i); + PREDICT_ACK [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_ADDRESS_" +toString(i); + PREDICT_ADDRESS [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_HISTORY_" +toString(i); + PREDICT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_DIRECTION_" +toString(i); + PREDICT_DIRECTION [i] = new sc_signal (rename.c_str()); + } + + BRANCH_COMPLETE_VAL = new sc_signal * [_param._nb_branch_complete]; + BRANCH_COMPLETE_ACK = new sc_signal * [_param._nb_branch_complete]; + BRANCH_COMPLETE_ADDRESS = new sc_signal * [_param._nb_branch_complete]; + BRANCH_COMPLETE_HISTORY = new sc_signal * [_param._nb_branch_complete]; + BRANCH_COMPLETE_DIRECTION = new sc_signal * [_param._nb_branch_complete]; + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + rename = "BRANCH_COMPLETE_VAL_" +toString(i); + BRANCH_COMPLETE_VAL [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_ACK_" +toString(i); + BRANCH_COMPLETE_ACK [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_ADDRESS_" +toString(i); + BRANCH_COMPLETE_ADDRESS [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_HISTORY_" +toString(i); + BRANCH_COMPLETE_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_DIRECTION_" +toString(i); + BRANCH_COMPLETE_DIRECTION [i] = new sc_signal (rename.c_str()); + } + + /******************************************************** + * Instanciation + ********************************************************/ + + cout << "<" << name << "> Instanciation of _Meta_Predictor" << endl; + + (*(_Meta_Predictor->in_CLOCK )) (*(CLOCK )); + (*(_Meta_Predictor->in_NRESET)) (*(NRESET)); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + (*(_Meta_Predictor-> in_PREDICT_VAL [i])) (*(PREDICT_VAL [i])); + (*(_Meta_Predictor->out_PREDICT_ACK [i])) (*(PREDICT_ACK [i])); + (*(_Meta_Predictor-> in_PREDICT_ADDRESS [i])) (*(PREDICT_ADDRESS [i])); + (*(_Meta_Predictor->out_PREDICT_HISTORY [i])) (*(PREDICT_HISTORY [i])); + (*(_Meta_Predictor->out_PREDICT_DIRECTION [i])) (*(PREDICT_DIRECTION [i])); + } + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + (*(_Meta_Predictor-> in_BRANCH_COMPLETE_VAL [i])) (*(BRANCH_COMPLETE_VAL [i])); + (*(_Meta_Predictor->out_BRANCH_COMPLETE_ACK [i])) (*(BRANCH_COMPLETE_ACK [i])); + (*(_Meta_Predictor-> in_BRANCH_COMPLETE_ADDRESS [i])) (*(BRANCH_COMPLETE_ADDRESS [i])); + (*(_Meta_Predictor-> in_BRANCH_COMPLETE_HISTORY [i])) (*(BRANCH_COMPLETE_HISTORY [i])); + (*(_Meta_Predictor-> in_BRANCH_COMPLETE_DIRECTION [i])) (*(BRANCH_COMPLETE_DIRECTION [i])); + } + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + cout << "<" << name << "> Start Simulation ............" << endl; + + // Initialisation + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + sc_start(0); + + NRESET->write(0); + sc_start(5); + NRESET->write(1); + + cout << "{"+toString(static_cast(sc_simulation_time()))+"} Initialisation" << endl; + + cout << "{"+toString(static_cast(sc_simulation_time()))+"} Loop of Test" << endl; + + for (uint32_t iteration=0; iteration ............ Stop Simulation" << endl; + +#endif + + delete _Meta_Predictor; +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/Makefile (revision 45) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = . +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libBranch_History_Table.a + + +#-----[ include ]------------------------------------------ + +all : $(LIBRARY_NEED) + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/Makefile.defs (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/Makefile.defs (revision 45) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/Makefile.deps (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/Makefile.deps (revision 45) @@ -0,0 +1,45 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Shifter +include $(DIR_MORPHEO)/Behavioural/Generic/Shifter/Makefile.deps +endif +ifndef RegisterFile_Monolithic +include $(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/Makefile.deps +endif + +Branch_History_Table = yes + +#-----[ Library ]------------------------------------------ +Branch_History_Table_LIBRARY = -lBranch_History_Table \ + $(RegisterFile_Monolithic_LIBRARY) \ + $(Shifter_LIBRARY) \ + $(Behavioural_LIBRARY) + +Branch_History_Table_DIR_LIBRARY = -L$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/lib \ + $(RegisterFile_Monolithic_DIR_LIBRARY) \ + $(Shifter_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Branch_History_Table_library : + @$(MAKE) Behavioural_library + @$(MAKE) Shifter_library + @$(MAKE) RegisterFile_Monolithic_library + @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table --makefile=Makefile + +Branch_History_Table_library_clean : + @$(MAKE) Behavioural_library_clean + @$(MAKE) Shifter_library_clean + @$(MAKE) RegisterFile_Monolithic_library_clean + @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table --makefile=Makefile clean Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/Makefile (revision 45) @@ -0,0 +1,29 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_MORPHEO = ../../../../../../.. + +LIBRARY = $(Branch_History_Table_LIBRARY) + +DIR_LIBRARY = $(Branch_History_Table_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : library + @$(MAKE) all_selftest + +library : Branch_History_Table_library + +library_clean : Branch_History_Table_library_clean + +include ../Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/config0.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/config0.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/config0.cfg (revision 45) @@ -0,0 +1,5 @@ +Branch_History_Table +2 8 *2 # size_shifter +2 64 *4 # nb_shifter +1 1 +1 # nb_prediction +1 1 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/config1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/config1.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/config1.cfg (revision 45) @@ -0,0 +1,5 @@ +Branch_History_Table +2 8 *2 # size_shifter +2 64 *4 # nb_shifter +2 2 +1 # nb_prediction +2 2 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/include/test.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/include/test.h (revision 45) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include +#include + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::stage_1_ifetch; +using namespace morpheo::behavioural::stage_1_ifetch::predictor; +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor; +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor; + +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table; + +void test (string name, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Parameters param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/main.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/main.cpp (revision 45) @@ -0,0 +1,47 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test 0 + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/include/test.h" + +#define NB_PARAMS 4 + +void usage (string exec) +{ + cerr << " " << exec << " name_instance list_params" << endl + << "list_params is :" << endl + << " - size_shifter (unsigned int)" << endl + << " - nb_shifter (unsigned int)" << endl + << " - nb_prediction (unsigned int)" << endl + << " - nb_branch_complete (unsigned int)" << endl; + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc != 2+NB_PARAMS) + usage (argv[0]); + + const string name = argv[1]; + const uint32_t size_shifter = atoi(argv[2]); + const uint32_t nb_shifter = atoi(argv[3]); + const uint32_t nb_prediction = atoi(argv[4]); + const uint32_t nb_branch_complete = atoi(argv[5]); + + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Parameters param (size_shifter , + nb_shifter , + nb_prediction , + nb_branch_complete ); + + test (name,param); + + return (EXIT_SUCCESS); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/test.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/test.cpp (revision 45) @@ -0,0 +1,190 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#define NB_ITERATION 1024 + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/include/test.h" +#include "Common/include/BitManipulation.h" +#include "Common/include/Test.h" + +void test (string name, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Parameters param) +{ + cout << "<" << name << "> : Simulation SystemC" << endl; + + try + { + cout << param.print(1); + param.test(); + } + catch (morpheo::ErrorMorpheo & error) + { + cout << "<" << name << "> : " << error.what (); + return; + } + catch (...) + { + cerr << "<" << name << "> : This test must generate a error" << endl; + exit (EXIT_FAILURE); + } + + Branch_History_Table * _Branch_History_Table = new Branch_History_Table (name.c_str(), +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics(5,50), +#endif + param); + +#ifdef SYSTEMC + + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + sc_clock CLOCK ("clock", 1.0, 0.5); + sc_signal NRESET; + sc_signal PREDICT_VAL [param._nb_prediction]; + sc_signal PREDICT_ACK [param._nb_prediction]; + sc_signal PREDICT_ADDRESS [param._nb_prediction]; + sc_signal PREDICT_HISTORY [param._nb_prediction]; + + sc_signal BRANCH_COMPLETE_VAL [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_ACK [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_ADDRESS [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_HISTORY [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_DIRECTION [param._nb_branch_complete]; + + /******************************************************** + * Instanciation + ********************************************************/ + + cout << "<" << name << "> Instanciation of _Branch_History_Table" << endl; + + (*(_Branch_History_Table->in_CLOCK)) (CLOCK); + (*(_Branch_History_Table->in_NRESET)) (NRESET); + + for (uint32_t i=0; i in_PREDICT_VAL [i])) (PREDICT_VAL [i]); + (*(_Branch_History_Table->out_PREDICT_ACK [i])) (PREDICT_ACK [i]); + (*(_Branch_History_Table-> in_PREDICT_ADDRESS [i])) (PREDICT_ADDRESS [i]); + (*(_Branch_History_Table->out_PREDICT_HISTORY [i])) (PREDICT_HISTORY [i]); + } + + for (uint32_t i=0; i in_BRANCH_COMPLETE_VAL [i])) (BRANCH_COMPLETE_VAL [i]); + (*(_Branch_History_Table->out_BRANCH_COMPLETE_ACK [i])) (BRANCH_COMPLETE_ACK [i]); + (*(_Branch_History_Table-> in_BRANCH_COMPLETE_ADDRESS [i])) (BRANCH_COMPLETE_ADDRESS [i]); + (*(_Branch_History_Table-> in_BRANCH_COMPLETE_HISTORY [i])) (BRANCH_COMPLETE_HISTORY [i]); + (*(_Branch_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i])) (BRANCH_COMPLETE_DIRECTION [i]); + } + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + cout << "<" << name << "> Start Simulation ............" << endl; + // Initialisation + sc_start(0); + + srand(0); + //srand(time(NULL)); + + + cout << "{"+toString(static_cast(sc_simulation_time()))+"} Initialisation" << endl; + + NRESET.write(1); + for (uint32_t i=0; i (param._size_shifter); + Tcontrol_t direction = 0; + + while (address(sc_simulation_time()))+"} Loop of Test" << endl; + + for (uint32_t iteration=0; iteration(sc_simulation_time()))+"} ["+toString(num_port_branch_complete)+"]" << endl + << hex + << " - address : " << address << endl + << " - history old : " << history << endl + << " - direction : " << direction<< endl; + + BRANCH_COMPLETE_VAL [num_port_branch_complete].write(1); + BRANCH_COMPLETE_ADDRESS [num_port_branch_complete].write(address); + BRANCH_COMPLETE_HISTORY [num_port_branch_complete].write(history); + BRANCH_COMPLETE_DIRECTION [num_port_branch_complete].write(direction); + + // Wait Ack + do + { + sc_start(1); + } + while (BRANCH_COMPLETE_ACK[num_port_branch_complete].read()!=1); + + BRANCH_COMPLETE_VAL [num_port_branch_complete].write(0); + PREDICT_VAL [num_port_predict ].write(1); + PREDICT_ADDRESS [num_port_predict ].write(address); + + history = ((history<<1)&mask)|direction; + + // Wait Ack + do + { + sc_start(1); + } + while (PREDICT_ACK [num_port_predict ].read()!=1); + + PREDICT_VAL [num_port_predict ].write(0); + + cout << "{"+toString(static_cast(sc_simulation_time()))+"} ["+toString(num_port_predict)+"]" << endl + << " - history new : " << PREDICT_HISTORY [num_port_predict].read() << endl; + + TEST(Thistory_t,PREDICT_HISTORY [num_port_predict].read(),history); + + cout << dec; + } + + /******************************************************** + * Simulation - End + ********************************************************/ + + cout << "<" << name << "> ............ Stop Simulation" << endl; + +#endif + + delete _Branch_History_Table; +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/VERSION =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/VERSION (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/VERSION (revision 45) @@ -0,0 +1,1 @@ +v0.1 Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/Branch_History_Table.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/Branch_History_Table.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/Branch_History_Table.tex (revision 45) @@ -0,0 +1,38 @@ +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/Makefile (revision 45) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = .. +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/sty/header.sty (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/sty/header.sty (revision 45) @@ -0,0 +1,12 @@ +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Branch\_History\_Table} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/01_introduction.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/01_introduction.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/02_features.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/02_features.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/03_description.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/03_description.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/04_pinout.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/04_pinout.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/05_parameters.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/05_parameters.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/06_performance.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/06_performance.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/07_details.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/07_details.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/08_history.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/08_history.tex (revision 45) @@ -0,0 +1,10 @@ +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/root.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/doc/tex/root.tex (revision 45) @@ -0,0 +1,8 @@ +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h (revision 45) @@ -0,0 +1,138 @@ +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Branch_History_Table_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Branch_History_Table_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +// Internal structure +#include "Behavioural/Generic/Shifter/include/Shifter.h" +#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h" +#endif +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Component.h" + +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + class Branch_History_Table +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const string _name; + + protected : const Parameters _param; +#ifdef STATISTICS + protected : const morpheo::behavioural::Parameters_Statistics _param_statistics; +#endif +#ifdef STATISTICS + private : Statistics * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // Interface + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + public : SC_IN (Tcontrol_t) ** in_PREDICT_VAL ; + public : SC_OUT(Tcontrol_t) ** out_PREDICT_ACK ; + public : SC_IN (Taddress_t) ** in_PREDICT_ADDRESS ; + public : SC_OUT(Thistory_t) ** out_PREDICT_HISTORY ; + + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_VAL ; + public : SC_OUT(Tcontrol_t) ** out_BRANCH_COMPLETE_ACK ; + public : SC_IN (Taddress_t) ** in_BRANCH_COMPLETE_ADDRESS; + public : SC_IN (Thistory_t) ** in_BRANCH_COMPLETE_HISTORY; + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_DIRECTION; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : morpheo::behavioural::generic::shifter::Shifter * component_Shifter ; + public : morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic * component_RegisterFile; + + // -----[ methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Branch_History_Table); +#endif + public : Branch_History_Table ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics param_statistics, +#endif + Parameters param ); + + public : Branch_History_Table (Parameters param ); + public : ~Branch_History_Table (void); + +#ifdef SYSTEMC + private : void allocation (void); + private : void deallocation (void); + +#if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) + public : void transition (void); +#endif +#endif + +#ifdef STATISTICS + public : string statistics (uint32_t depth); +#endif +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif +#ifdef VHDL_TESTBENCH + private : void vhdl_testbench_transition (void); +#endif + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h (revision 45) @@ -0,0 +1,61 @@ +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Parameters_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" +#include "Behavioural/include/Parameters.h" +// Internal structure +#include "Behavioural/Generic/Shifter/include/Parameters.h" +#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : const uint32_t _size_shifter ; + public : const uint32_t _nb_shifter ; + public : const uint32_t _nb_prediction ; + public : const uint32_t _nb_branch_complete; + + public : morpheo::behavioural::generic::shifter::Parameters * _param_shifter; + public : morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param_registerfile; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t size_shifter , + uint32_t nb_shifter , + uint32_t nb_prediction , + uint32_t nb_branch_complete); + public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : string msg_error (void); + + public : string print (uint32_t depth); + public : friend ostream& operator<< (ostream& output_stream, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Parameters & x); + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h (revision 45) @@ -0,0 +1,65 @@ +#ifdef STATISTICS +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Statistics_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Statistics_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" +#include "Behavioural/include/Statistics.h" +#include "Behavioural/include/Parameters_Statistics.h" +#include "Behavioural/Generic/Shifter/include/Statistics.h" +#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Statistics.h" +//#include "Behavioural/Generic/Group/include/Statistics.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h" + +//using namespace morpheo::behavioural::generic::group; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + class Statistics : public morpheo::behavioural::Statistics + { + // -----[ fields ]---------------------------------------------------- + private : const Parameters _parameters; + + // -----[ methods ]--------------------------------------------------- + public : Statistics (string name , + morpheo::behavioural::Parameters_Statistics parameters_statistics , + Parameters parameters + ); +//public : Statistics (Statistics & stat); + public : ~Statistics () ; + + public : string print_body (uint32_t depth); + public : string print (uint32_t depth); + public : string print (uint32_t depth , + string component_stat ); + public : void add (); + + public : friend ostream& operator<< (ostream& output_stream, + const Statistics & x); + + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/include/Types.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/include/Types.h (revision 45) @@ -0,0 +1,34 @@ +#ifdef SYSTEMC +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Type_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Type_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + typedef uint32_t Thistory_t; + typedef uint32_t Taddress_t; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo + +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table.cpp (revision 45) @@ -0,0 +1,93 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + +#ifdef SYSTEMC + Branch_History_Table::Branch_History_Table (sc_module_name name, +#else + Branch_History_Table::Branch_History_Table (string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics param_statistics, +#endif + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Parameters param ): + _name (name) + ,_param (param) +#ifdef STATISTICS + ,_param_statistics (param_statistics) +#endif + { + +#ifdef SYSTEMC + allocation (); +#endif + +#ifdef STATISTICS + // Allocation of statistics + _stat = new Statistics (static_cast(_name), + param_statistics , + param); +#endif + +#ifdef VHDL + // generate the vhdl + vhdl(); +#endif + + +#ifdef SYSTEMC +// // Constant +// for (uint32_t i=0; i<_param._nb_prediction ; i++) +// PORT_WRITE(out_PREDICT_ACK [i],1); +// for (uint32_t i=0; i<_param._nb_branch_complete; i++) +// PORT_WRITE(out_BRANCH_COMPLETE_ACK [i],1); + +#if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) + SC_METHOD (transition); + dont_initialize (); + sensitive_pos << *(in_CLOCK); +#endif + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information +#endif + +#endif + }; + + Branch_History_Table::~Branch_History_Table (void) + { +#ifdef STATISTICS + + _stat->generate_file(statistics(0)); + + delete _stat; +#endif + +#ifdef SYSTEMC + deallocation (); +#endif + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_allocation.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_allocation.cpp (revision 45) @@ -0,0 +1,212 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + void Branch_History_Table::allocation (void) + { + _component = new Component (); + + Entity * entity = _component->set_entity (_name + ,"Branch_History_Table" +#ifdef POSITION + ,MIXTE +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + , IN + , SOUTH + , "Generalist interface" +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1); + in_NRESET = interface->set_signal_in ("nreset",1,RESET_VHDL_YES); + } + + // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction]; + out_PREDICT_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_prediction]; + in_PREDICT_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_prediction]; + out_PREDICT_HISTORY = new SC_OUT(Thistory_t) * [_param._nb_prediction]; + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) +#ifdef POSITION + , IN + , WEST + , "Interface Predict" +#endif + ); + + in_PREDICT_VAL [i] = interface->set_signal_valack_in ("val" , VAL); + out_PREDICT_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); + in_PREDICT_ADDRESS [i] = interface->set_signal_in ("address", static_cast(ceil(log2(_param._nb_shifter)))); + out_PREDICT_HISTORY [i] = interface->set_signal_out ("history", _param._size_shifter); + } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; + out_BRANCH_COMPLETE_ACK = new SC_OUT (Tcontrol_t) * [_param._nb_branch_complete]; + in_BRANCH_COMPLETE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_branch_complete]; + in_BRANCH_COMPLETE_HISTORY = new SC_IN (Thistory_t) * [_param._nb_branch_complete]; + in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i) +#ifdef POSITION + , IN + , EAST + , "Interface branch complete" +#endif + ); + + in_BRANCH_COMPLETE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); + out_BRANCH_COMPLETE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); + in_BRANCH_COMPLETE_ADDRESS [i] = interface->set_signal_in ("address" , static_cast(ceil(log2(_param._nb_shifter)))); + in_BRANCH_COMPLETE_HISTORY [i] = interface->set_signal_in ("history" , _param._size_shifter); + in_BRANCH_COMPLETE_DIRECTION [i] = interface->set_signal_in ("direction", 1); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + string name_component; + + // =====[ component_Shifter ]========================================= + + name_component = _name+"_Shifter"; + + component_Shifter = new morpheo::behavioural::generic::shifter::Shifter (name_component.c_str() +#ifdef STATISTICS + ,_param_statistics +#endif + ,*(_param._param_shifter)); + + _component->set_component (component_Shifter->_component +#ifdef POSITION + , 25 + , 25 + , 10 + , 10 +#endif + ); + + // =====[ component_RegisterFile ]==================================== + + name_component = _name+"_RegisterFile"; + + component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic(name_component.c_str(), +#ifdef STATISTICS + _param_statistics , +#endif + *(_param._param_registerfile)); + + _component->set_component (component_RegisterFile->_component +#ifdef POSITION + , 75 + , 75 + , 10 + , 10 +#endif + ); + + // ~~~~~[ Component - Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // =====[ component_RegisterFile - Instanciation ]==================== + +#ifdef POSITION + _component->interface_map (_name+"_RegisterFile","", + _name ,""); +#endif + + _component->port_map(_name+"_RegisterFile", "in_CLOCK" , _name,"in_CLOCK" ); + _component->port_map(_name+"_RegisterFile", "in_NRESET", _name,"in_NRESET"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { +#ifdef POSITION + _component->interface_map (_name+"_RegisterFile","read_" +toString(i), + _name ,"predict_"+toString(i)); +#endif + + _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_VAL" , _name, "in_PREDICT_"+toString(i)+"_VAL" ); + _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_ACK" , _name,"out_PREDICT_"+toString(i)+"_ACK" ); + _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_ADDRESS", _name, "in_PREDICT_"+toString(i)+"_ADDRESS"); + _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_DATA" , _name,"out_PREDICT_"+toString(i)+"_HISTORY"); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { +#ifdef POSITION + _component->interface_map (_name+"_RegisterFile","write_" +toString(i), + _name+"_Shifter" ,"shifter_"+toString(i)); +#endif + + _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); + _component->port_map(_name+"_RegisterFile","out_WRITE_"+toString(i)+"_ACK" , _name ,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK" ); + _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_ADDRESS", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); + _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA" , _name+"_Shifter","out_SHIFTER_" +toString(i)+"_DATA"); + } + + // =====[ component_Shifter - Instanciation ]========================= + +#if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) + +#ifdef POSITION + _component->interface_map (_name+"_Shifter","", + _name ,""); +#endif + + _component->port_map(_name+"_Shifter", "in_CLOCK" , _name,"in_CLOCK" ); + _component->port_map(_name+"_Shifter", "in_NRESET", _name,"in_NRESET"); + +#endif + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { +#ifdef POSITION + _component->interface_map (_name+"_Shifter","shifter_"+toString(i), + _name ,"branch_complete_"+toString(i)); + +#endif + + _component->port_map(_name+"_Shifter", "in_SHIFTER_" +toString(i)+"_DATA" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"); + _component->port_map(_name+"_Shifter", "in_SHIFTER_" +toString(i)+"_CARRY_IN", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION"); + _component->port_map(_name+"_Shifter", "out_SHIFTER_"+toString(i)+"_DATA" , _name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA"); + } + +#ifdef POSITION + _component->generate_file(); +#endif + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_deallocation.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_deallocation.cpp (revision 45) @@ -0,0 +1,49 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + void Branch_History_Table::deallocation (void) + { + delete in_CLOCK; + delete in_NRESET; + + delete [] in_PREDICT_VAL ; + delete [] out_PREDICT_ACK ; + delete [] in_PREDICT_ADDRESS; + delete [] out_PREDICT_HISTORY; + + delete [] in_BRANCH_COMPLETE_VAL ; + delete [] out_BRANCH_COMPLETE_ACK ; + delete [] in_BRANCH_COMPLETE_ADDRESS; + delete [] in_BRANCH_COMPLETE_HISTORY; + delete [] in_BRANCH_COMPLETE_DIRECTION; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete component_Shifter; + delete component_RegisterFile; + + delete _component; + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_statistics.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_statistics.cpp (revision 45) @@ -0,0 +1,36 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + string Branch_History_Table::statistics (uint32_t depth) + { + return _stat->print(depth, + component_Shifter ->statistics(depth+1) + + component_RegisterFile->statistics(depth+1) + ); + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_transition.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_transition.cpp (revision 45) @@ -0,0 +1,41 @@ +#ifdef SYSTEMC +#if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + void Branch_History_Table::transition (void) + { +#ifdef STATISTICS + _stat->add(); +#endif + +#ifdef VHDL_TESTBENCH + vhdl_testbench_transition (); +#endif + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl.cpp (revision 45) @@ -0,0 +1,44 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + void Branch_History_Table::vhdl (void) + { + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port (vhdl); + _component ->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_body.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_body.cpp (revision 45) @@ -0,0 +1,32 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + void Branch_History_Table::vhdl_body (Vhdl * & vhdl) + { + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_declaration.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_declaration.cpp (revision 45) @@ -0,0 +1,30 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + void Branch_History_Table::vhdl_declaration (Vhdl * & vhdl) + { + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_transition.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_transition.cpp (revision 45) @@ -0,0 +1,35 @@ +#ifdef VHDL_TESTBENCH +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + void Branch_History_Table::vhdl_testbench_transition (void) + { +// sc_start(0); + + _interfaces->testbench(); + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters.cpp (revision 45) @@ -0,0 +1,78 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + Parameters::Parameters (uint32_t size_shifter , + uint32_t nb_shifter , + uint32_t nb_prediction , + uint32_t nb_branch_complete) : + _size_shifter (size_shifter ), + _nb_shifter (nb_shifter ), + _nb_prediction (nb_prediction ), + _nb_branch_complete (nb_branch_complete) + { + _param_shifter = new morpheo::behavioural::generic::shifter::Parameters (size_shifter , + nb_branch_complete , + 1 , + morpheo::behavioural::generic::shifter::without_rotate , + morpheo::behavioural::generic::shifter::internal_left_shift, + morpheo::behavioural::generic::shifter::external_completion), + _param_registerfile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters (nb_prediction , + nb_branch_complete , + nb_shifter , + size_shifter ); + + test(); + }; + + Parameters::Parameters (Parameters & param) : + _size_shifter (param._size_shifter ), + _nb_shifter (param._nb_shifter ), + _nb_prediction (param._nb_prediction ), + _nb_branch_complete (param._nb_branch_complete) + { + _param_shifter = new morpheo::behavioural::generic::shifter::Parameters (param._size_shifter , + param._nb_branch_complete , + 1 , + morpheo::behavioural::generic::shifter::without_rotate , + morpheo::behavioural::generic::shifter::internal_left_shift, + morpheo::behavioural::generic::shifter::external_completion, + true), + + _param_registerfile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters (param._nb_prediction , + param._nb_branch_complete , + param._nb_shifter , + param._size_shifter ); + + + + test(); + }; + + Parameters::~Parameters () + { + delete _param_shifter; + delete _param_registerfile; + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters_msg_error.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters_msg_error.cpp (revision 45) @@ -0,0 +1,54 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Types.h" +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + string Parameters::msg_error(void) + { + string msg = ""; + + if (is_positive (_size_shifter) == false) + { + msg += " - size_shifter must be > 0\n"; + msg += " * size_shifter : " + toString(_size_shifter) + "\n"; + } + + if (is_positive (_nb_prediction) == false) + { + msg += " - nb_prediction must be > 0\n"; + msg += " * nb_prediction : " + toString(_nb_prediction) + "\n"; + } + + if (is_positive (_nb_branch_complete) == false) + { + msg += " - nb_branch_complete must be > 0\n"; + msg += " * nb_branch_complete : " + toString(_nb_branch_complete) + "\n"; + } + + return msg; + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters_print.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters_print.cpp (revision 45) @@ -0,0 +1,52 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h" +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + string Parameters::print (uint32_t depth) + { + string tab = string(depth,'\t'); + ostringstream msg; + msg << tab << "" << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t" << endl; + msg << _param_shifter ->print(depth+1); + msg << _param_registerfile->print(depth+1); + msg << tab << "" << endl; + + return msg.str(); + }; + + ostream& operator<< (ostream& output_stream , + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Parameters & x) + { + output_stream << x.print(0); + + return output_stream; + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics.cpp (revision 45) @@ -0,0 +1,42 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + Statistics::Statistics (string name , + morpheo::behavioural::Parameters_Statistics parameters_statistics , + Parameters parameters + ) : + morpheo::behavioural::Statistics(name , + parameters_statistics ), + _parameters(parameters) + { + }; + + Statistics::~Statistics () + { + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_add.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_add.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_add.cpp (revision 45) @@ -0,0 +1,35 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + + void Statistics::add () + { + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_print.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_print.cpp (revision 45) @@ -0,0 +1,55 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h" +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + string Statistics::print (uint32_t depth , + string component_statistics ) + { + string tab = string(depth,'\t'); + ostringstream msg; + + msg << tab << "" << endl + << print_body(depth+1) + << component_statistics + << tab << "" << endl; + + return msg.str(); + }; + + string Statistics::print (uint32_t depth) + { + return print(depth,""); + }; + + ostream& operator<< (ostream& output_stream , + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Statistics & x) + { + output_stream << x.print(0); + + return output_stream; + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_print_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_print_body.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_print_body.cpp (revision 45) @@ -0,0 +1,40 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace branch_history_table { + + string Statistics::print_body (uint32_t depth) + { + string tab = string(depth,'\t'); + ostringstream msg; + + msg << tab << ""; + + return msg.str(); + }; + +}; // end namespace branch_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Makefile (revision 45) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = . +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libTwo_Level_Branch_Predictor.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Makefile.defs (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Makefile.defs (revision 45) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Makefile.deps (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Makefile.deps (revision 45) @@ -0,0 +1,52 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Branch_History_Table +include $(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/Makefile.deps +endif +ifndef Pattern_History_Table +include $(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile.deps +endif +ifndef Two_Level_Branch_Predictor_Glue +include $(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile.deps +endif + +Two_Level_Branch_Predictor = yes + +#-----[ Library ]------------------------------------------ +Two_Level_Branch_Predictor_LIBRARY = -lTwo_Level_Branch_Predictor \ + $(Two_Level_Branch_Predictor_Glue_LIBRARY) \ + $(Branch_History_Table_LIBRARY) \ + $(Pattern_History_Table_LIBRARY) \ + $(Behavioural_LIBRARY) + +Two_Level_Branch_Predictor_DIR_LIBRARY = -L$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/lib \ + $(Two_Level_Branch_Predictor_Glue_DIR_LIBRARY) \ + $(Branch_History_Table_DIR_LIBRARY) \ + $(Pattern_History_Table_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Two_Level_Branch_Predictor_library : + @$(MAKE) Behavioural_library + @$(MAKE) Branch_History_Table_library + @$(MAKE) Pattern_History_Table_library + @$(MAKE) Two_Level_Branch_Predictor_Glue_library + @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor --makefile=Makefile + +Two_Level_Branch_Predictor_library_clean : + @$(MAKE) Behavioural_library_clean + @$(MAKE) Branch_History_Table_library_clean + @$(MAKE) Pattern_History_Table_library_clean + @$(MAKE) Two_Level_Branch_Predictor_Glue_library_clean + @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor --makefile=Makefile clean Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile (revision 45) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = . +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libPattern_History_Table.a + + +#-----[ include ]------------------------------------------ + +all : $(LIBRARY_NEED) + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile.defs (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile.defs (revision 45) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile.deps (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile.deps (revision 45) @@ -0,0 +1,45 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Counter +include $(DIR_MORPHEO)/Behavioural/Generic/Counter/Makefile.deps +endif +ifndef RegisterFile_Monolithic +include $(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/Makefile.deps +endif + +Pattern_History_Table = yes + +#-----[ Library ]------------------------------------------ +Pattern_History_Table_LIBRARY = -lPattern_History_Table \ + $(RegisterFile_Monolithic_LIBRARY) \ + $(Counter_LIBRARY) \ + $(Behavioural_LIBRARY) + +Pattern_History_Table_DIR_LIBRARY = -L$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/lib \ + $(RegisterFile_Monolithic_DIR_LIBRARY) \ + $(Counter_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Pattern_History_Table_library : + @$(MAKE) Behavioural_library + @$(MAKE) Counter_library + @$(MAKE) RegisterFile_Monolithic_library + @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table --makefile=Makefile + +Pattern_History_Table_library_clean : + @$(MAKE) Behavioural_library_clean + @$(MAKE) Counter_library_clean + @$(MAKE) RegisterFile_Monolithic_library_clean + @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table --makefile=Makefile clean Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/Makefile (revision 45) @@ -0,0 +1,29 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_MORPHEO = ../../../../../../.. + +LIBRARY = $(Pattern_History_Table_LIBRARY) + +DIR_LIBRARY = $(Pattern_History_Table_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : library + @$(MAKE) all_selftest + +library : Pattern_History_Table_library + +library_clean : Pattern_History_Table_library_clean + +include ../Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/config0.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/config0.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/config0.cfg (revision 45) @@ -0,0 +1,5 @@ +Pattern_History_Table +2 8 *2 # size_counter +2 64 *4 # nb_counter +1 1 +1 # nb_prediction +1 1 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/config1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/config1.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/config1.cfg (revision 45) @@ -0,0 +1,5 @@ +Pattern_History_Table +2 8 *2 # size_counter +2 64 *4 # nb_counter +2 2 +1 # nb_prediction +2 2 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/configuration.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/configuration.cfg (revision 45) @@ -0,0 +1,5 @@ +Pattern_History_Table +2 8 *2 # size_counter +2 64 *4 # nb_counter +1 2 +1 # nb_prediction +1 2 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/include/test.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/include/test.h (revision 45) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include +#include + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::stage_1_ifetch; +using namespace morpheo::behavioural::stage_1_ifetch::predictor; +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor; +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor; + +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table; + +void test (string name, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/mkf.info =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/mkf.info (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/mkf.info (revision 45) @@ -0,0 +1,6 @@ + +# Pattern_History_Table_0 +target_dep all Pattern_History_Table_0.ngc +target_dep Pattern_History_Table_0.ngc Pattern_History_Table_0.prj +target_dep Pattern_History_Table_0.prj Pattern_History_Table_0_Counter_Pack.vhdl Pattern_History_Table_0_Counter.vhdl Pattern_History_Table_0_Pack.vhdl Pattern_History_Table_0_RegisterFile_Pack.vhdl Pattern_History_Table_0_RegisterFile.vhdl Pattern_History_Table_0.vhdl + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/main.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/main.cpp (revision 45) @@ -0,0 +1,47 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test 0 + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/include/test.h" + +#define NB_PARAMS 4 + +void usage (string exec) +{ + cerr << " " << exec << " name_instance list_params" << endl + << "list_params is :" << endl + << " - size_counter (unsigned int)" << endl + << " - nb_counter (unsigned int)" << endl + << " - nb_prediction (unsigned int)" << endl + << " - nb_branch_complete (unsigned int)" << endl; + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc != 2+NB_PARAMS) + usage (argv[0]); + + const string name = argv[1]; + const uint32_t size_counter = atoi(argv[2]); + const uint32_t nb_counter = atoi(argv[3]); + const uint32_t nb_prediction = atoi(argv[4]); + const uint32_t nb_branch_complete = atoi(argv[5]); + + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters param (size_counter , + nb_counter , + nb_prediction , + nb_branch_complete ); + + test (name,param); + + return (EXIT_SUCCESS); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/test.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/test.cpp (revision 45) @@ -0,0 +1,187 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#define NB_ITERATION 512 + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/include/test.h" +#include "Common/include/Test.h" + +void test (string name, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters param) +{ + cout << "<" << name << "> : Simulation SystemC" << endl; + + try + { + cout << param.print(1); + param.test(); + } + catch (morpheo::ErrorMorpheo & error) + { + cout << "<" << name << "> : " << error.what (); + return; + } + catch (...) + { + cerr << "<" << name << "> : This test must generate a error" << endl; + exit (EXIT_FAILURE); + } + Pattern_History_Table * _Pattern_History_Table = new Pattern_History_Table (name.c_str(), +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics(5,50), +#endif + param); + +#ifdef SYSTEMC + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + sc_clock CLOCK ("clock", 1.0, 0.5); + sc_signal NRESET; + + sc_signal PREDICT_VAL [param._nb_prediction]; + sc_signal PREDICT_ACK [param._nb_prediction]; + sc_signal PREDICT_ADDRESS [param._nb_prediction]; + sc_signal PREDICT_HISTORY [param._nb_prediction]; + + sc_signal BRANCH_COMPLETE_VAL [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_ACK [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_ADDRESS [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_HISTORY [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_DIRECTION [param._nb_branch_complete]; + + /******************************************************** + * Instanciation + ********************************************************/ + + cout << "<" << name << "> Instanciation of _Pattern_History_Table" << endl; + + (*(_Pattern_History_Table->in_CLOCK)) (CLOCK); + (*(_Pattern_History_Table->in_NRESET)) (NRESET); + + for (uint32_t i=0; i in_PREDICT_VAL [i])) (PREDICT_VAL [i]); + (*(_Pattern_History_Table->out_PREDICT_ACK [i])) (PREDICT_ACK [i]); + (*(_Pattern_History_Table-> in_PREDICT_ADDRESS [i])) (PREDICT_ADDRESS [i]); + (*(_Pattern_History_Table->out_PREDICT_HISTORY [i])) (PREDICT_HISTORY [i]); + } + + for (uint32_t i=0; i in_BRANCH_COMPLETE_VAL [i])) (BRANCH_COMPLETE_VAL [i]); + (*(_Pattern_History_Table->out_BRANCH_COMPLETE_ACK [i])) (BRANCH_COMPLETE_ACK [i]); + (*(_Pattern_History_Table-> in_BRANCH_COMPLETE_ADDRESS [i])) (BRANCH_COMPLETE_ADDRESS [i]); + (*(_Pattern_History_Table-> in_BRANCH_COMPLETE_HISTORY [i])) (BRANCH_COMPLETE_HISTORY [i]); + (*(_Pattern_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i])) (BRANCH_COMPLETE_DIRECTION [i]); + } + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + cout << "<" << name << "> Start Simulation ............" << endl; + // Initialisation + + srand(0); + //srand(TIME(NULL)); + + sc_start(0); + cout << "{"+toString(static_cast(sc_simulation_time()))+"} Initialisation" << endl; + + NRESET.write(1); + + for (uint32_t i=0; i(sc_simulation_time()))+"} Loop of Test" << endl; + + for (uint32_t iteration=0; iteration(sc_simulation_time()))+"} ["+toString(num_port_branch_complete)+"]" << endl + << hex + << " - address : " << address << endl + << " - history old : " << history << endl + << " - direction : " << direction << endl; + + BRANCH_COMPLETE_VAL [num_port_branch_complete].write(1); + BRANCH_COMPLETE_ADDRESS [num_port_branch_complete].write(address); + BRANCH_COMPLETE_HISTORY [num_port_branch_complete].write(history); + BRANCH_COMPLETE_DIRECTION [num_port_branch_complete].write(direction); + + // Wait Ack + do + { + sc_start(1); + } + while (BRANCH_COMPLETE_ACK[num_port_branch_complete].read()!=1); + + BRANCH_COMPLETE_VAL [num_port_branch_complete].write(0); + PREDICT_VAL [num_port_predict ].write(1); + PREDICT_ADDRESS [num_port_predict ].write(address); + + history = (direction==1)?((history0)?history-1:history); + + // Wait Ack + do + { + sc_start(1); + } + while (PREDICT_ACK [num_port_predict ].read()!=1); + + PREDICT_VAL [num_port_predict ].write(0); + + cout << "{"+toString(static_cast(sc_simulation_time()))+"} ["+toString(num_port_predict)+"]" << endl + << " - history new : " << PREDICT_HISTORY [num_port_predict].read() << endl + << dec; + + TEST(Thistory_t,PREDICT_HISTORY [num_port_predict].read(),history); + } + + /******************************************************** + * Simulation - End + ********************************************************/ + + cout << "<" << name << "> ............ Stop Simulation" << endl; + +#endif + + delete _Pattern_History_Table; +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/VERSION =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/VERSION (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/VERSION (revision 45) @@ -0,0 +1,1 @@ +v0.2 Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/Makefile (revision 45) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = .. +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/Pattern_History_Table.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/Pattern_History_Table.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/Pattern_History_Table.tex (revision 45) @@ -0,0 +1,38 @@ +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/sty/header.sty (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/sty/header.sty (revision 45) @@ -0,0 +1,12 @@ +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Pattern\_History\_Table} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/01_introduction.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/01_introduction.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/02_features.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/02_features.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/03_description.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/03_description.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/04_pinout.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/04_pinout.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/05_parameters.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/05_parameters.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/06_performance.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/06_performance.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/07_details.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/07_details.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/08_history.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/08_history.tex (revision 45) @@ -0,0 +1,10 @@ +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/root.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/doc/tex/root.tex (revision 45) @@ -0,0 +1,8 @@ +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h (revision 45) @@ -0,0 +1,62 @@ +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Parameters_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" +#include "Behavioural/include/Parameters.h" +// Internal structure +#include "Behavioural/Generic/Counter/include/Parameters.h" +#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : const uint32_t _size_counter ; + public : const uint32_t _nb_counter ; + public : const uint32_t _nb_prediction ; + public : const uint32_t _nb_branch_complete; + + public : morpheo::behavioural::generic::counter::Parameters * _param_counter; + public : morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param_registerfile; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t size_counter , + uint32_t nb_counter , + uint32_t nb_prediction , + uint32_t nb_branch_complete); + public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : string msg_error (void); + + public : string print (uint32_t depth); + public : friend ostream& operator<< (ostream& output_stream, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters & x); + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h (revision 45) @@ -0,0 +1,143 @@ +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Pattern_History_Table_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Pattern_History_Table_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +// Internal structure +#include "Behavioural/Generic/Counter/include/Counter.h" +#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h" + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h" +#endif +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Component.h" + +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + class Pattern_History_Table +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const string _name; + + protected : const Parameters _param; +#ifdef STATISTICS + protected : const morpheo::behavioural::Parameters_Statistics _param_statistics; +#endif + +#ifdef STATISTICS + private : Statistics * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // Interface + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + public : SC_IN (Tcontrol_t) ** in_PREDICT_VAL ; + public : SC_OUT(Tcontrol_t) ** out_PREDICT_ACK ; + public : SC_IN (Taddress_t) ** in_PREDICT_ADDRESS ; + public : SC_OUT(Thistory_t) ** out_PREDICT_HISTORY ; + + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_VAL ; + public : SC_OUT(Tcontrol_t) ** out_BRANCH_COMPLETE_ACK ; + public : SC_IN (Taddress_t) ** in_BRANCH_COMPLETE_ADDRESS; + public : SC_IN (Thistory_t) ** in_BRANCH_COMPLETE_HISTORY; + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_DIRECTION; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_SIGNAL(Thistory_t) ** signal_BRANCH_COMPLETE_HISTORY; +#endif + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : morpheo::behavioural::generic::counter::Counter * component_Counter ; + public : morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic * component_RegisterFile; + + // -----[ methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Pattern_History_Table); +#endif + + public : Pattern_History_Table ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics param_statistics, +#endif + Parameters param ); + + public : Pattern_History_Table (Parameters param ); + public : ~Pattern_History_Table (void); + +#ifdef SYSTEMC + private : void allocation (void); + private : void deallocation (void); + +#if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) + public : void transition (void); +#endif +#endif + +#ifdef STATISTICS + public : string statistics (uint32_t depth); +#endif +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif +#ifdef VHDL_TESTBENCH + private : void vhdl_testbench_transition (void); +#endif + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h (revision 45) @@ -0,0 +1,65 @@ +#ifdef STATISTICS +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Statistics_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Statistics_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" +#include "Behavioural/include/Statistics.h" +#include "Behavioural/include/Parameters_Statistics.h" +#include "Behavioural/Generic/Counter/include/Statistics.h" +#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Statistics.h" +//#include "Behavioural/Generic/Group/include/Statistics.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h" + +//using namespace morpheo::behavioural::generic::group; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + class Statistics : public morpheo::behavioural::Statistics + { + // -----[ fields ]---------------------------------------------------- + private : const Parameters _parameters; + + // -----[ methods ]--------------------------------------------------- + public : Statistics (string name , + morpheo::behavioural::Parameters_Statistics parameters_statistics , + Parameters parameters + ); +//public : Statistics (Statistics & stat); + public : ~Statistics () ; + + public : string print_body (uint32_t depth); + public : string print (uint32_t depth); + public : string print (uint32_t depth, + string component_stat); + public : void add (); + + public : friend ostream& operator<< (ostream& output_stream, + const Statistics & x); + + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/include/Types.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/include/Types.h (revision 45) @@ -0,0 +1,34 @@ +#ifdef SYSTEMC +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Type_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Type_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + typedef uint32_t Thistory_t; + typedef uint32_t Taddress_t; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo + +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters.cpp (revision 45) @@ -0,0 +1,76 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + Parameters::Parameters (uint32_t size_counter , + uint32_t nb_counter , + uint32_t nb_prediction , + uint32_t nb_branch_complete) : + _size_counter (size_counter ), + _nb_counter (nb_counter ), + _nb_prediction (nb_prediction ), + _nb_branch_complete (nb_branch_complete) + { + log_printf(FUNC,Pattern_History_Table,"Parameters","Begin"); + + _param_counter = new morpheo::behavioural::generic::counter::Parameters (size_counter , + nb_branch_complete ); + _param_registerfile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters (nb_prediction , + nb_branch_complete , + nb_counter , + size_counter ); + + + test(); + log_printf(FUNC,Pattern_History_Table,"Parameters","End"); + }; + + Parameters::Parameters (Parameters & param) : + _size_counter (param._size_counter ), + _nb_counter (param._nb_counter ), + _nb_prediction (param._nb_prediction ), + _nb_branch_complete (param._nb_branch_complete) + { + log_printf(FUNC,Pattern_History_Table,"Parameters","Begin"); + + _param_counter = new morpheo::behavioural::generic::counter::Parameters (param._size_counter , + param._nb_branch_complete ); + + _param_registerfile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters (param._nb_prediction , + param._nb_branch_complete , + param._nb_counter , + param._size_counter ); + + test(); + log_printf(FUNC,Pattern_History_Table,"Parameters","End"); + }; + + Parameters::~Parameters () + { + log_printf(FUNC,Pattern_History_Table,"~Parameters","Begin"); + delete _param_counter; + delete _param_registerfile; + log_printf(FUNC,Pattern_History_Table,"~Parameters","End"); + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters_msg_error.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters_msg_error.cpp (revision 45) @@ -0,0 +1,58 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Types.h" +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + string Parameters::msg_error(void) + { + log_printf(FUNC,Pattern_History_Table,"msg_error","Begin"); + + string msg = ""; + + if (is_positive (_size_counter) == false) + { + msg += " - size_counter must be > 0\n"; + msg += " * size_counter : " + toString(_size_counter) + "\n"; + } + + if (is_positive (_nb_prediction) == false) + { + msg += " - nb_prediction must be > 0\n"; + msg += " * nb_prediction : " + toString(_nb_prediction) + "\n"; + } + + if (is_positive (_nb_branch_complete) == false) + { + msg += " - nb_branch_complete must be > 0\n"; + msg += " * nb_branch_complete : " + toString(_nb_branch_complete) + "\n"; + } + + return msg; + + log_printf(FUNC,Pattern_History_Table,"msg_error","End"); + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters_print.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters_print.cpp (revision 45) @@ -0,0 +1,56 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h" +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + string Parameters::print (uint32_t depth) + { + log_printf(FUNC,Pattern_History_Table,"print","Begin"); + + string tab = string(depth,'\t'); + ostringstream msg; + msg << tab << "" << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t" << endl; + msg << _param_counter ->print(depth+1); + msg << _param_registerfile->print(depth+1); + msg << tab << "" << endl; + + log_printf(FUNC,Pattern_History_Table,"print","End"); + + return msg.str(); + }; + + ostream& operator<< (ostream& output_stream , + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters & x) + { + output_stream << x.print(0); + + return output_stream; + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table.cpp (revision 45) @@ -0,0 +1,97 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + +#ifdef SYSTEMC + Pattern_History_Table::Pattern_History_Table (sc_module_name name, +#else + Pattern_History_Table::Pattern_History_Table (string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics param_statistics, +#endif + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters param ): + _name (name) + ,_param (param) +#ifdef STATISTICS + ,_param_statistics (param_statistics) +#endif + { + log_printf(FUNC,Pattern_History_Table,"Pattern_History_Table","Begin"); + +#ifdef SYSTEMC + allocation (); +#endif + +#ifdef STATISTICS + // Allocation of statistics + _stat = new Statistics (static_cast(_name), + param_statistics , + param); +#endif + +#ifdef VHDL + // generate the vhdl + vhdl(); +#endif + +#ifdef SYSTEMC +// // Constant +// for (uint32_t i=0; i<_param._nb_prediction ; i++) +// PORT_WRITE(out_PREDICT_ACK [i],1); +// for (uint32_t i=0; i<_param._nb_branch_complete; i++) +// PORT_WRITE(out_BRANCH_COMPLETE_ACK [i],1); + +#if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) + SC_METHOD (transition); + dont_initialize (); + sensitive_pos << *(in_CLOCK); +#endif + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information +#endif + +#endif + log_printf(FUNC,Pattern_History_Table,"Pattern_History_Table","End"); + }; + + Pattern_History_Table::~Pattern_History_Table (void) + { + log_printf(FUNC,Pattern_History_Table,"~Pattern_History_Table","Begin"); + +#ifdef STATISTICS + _stat->generate_file(statistics(0)); + + delete _stat; +#endif + +#ifdef SYSTEMC + deallocation (); +#endif + + log_printf(FUNC,Pattern_History_Table,"~Pattern_History_Table","End"); + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_allocation.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_allocation.cpp (revision 45) @@ -0,0 +1,217 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + void Pattern_History_Table::allocation (void) + { + log_printf(FUNC,Pattern_History_Table,"allocation","Begin"); + + _component = new Component (); + + Entity * entity = _component->set_entity (_name + ,"Pattern_History_Table" +#ifdef POSITION + ,MIXTE +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + , IN + , SOUTH + , "Generalist interface" +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1); + in_NRESET = interface->set_signal_in ("nreset",1,RESET_VHDL_YES); + } + + // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction]; + out_PREDICT_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_prediction]; + in_PREDICT_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_prediction]; + out_PREDICT_HISTORY = new SC_OUT(Thistory_t) * [_param._nb_prediction]; + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) +#ifdef POSITION + , IN + , WEST + , "Interface Predict" +#endif + ); + + in_PREDICT_VAL [i] = interface->set_signal_valack_in ("val" , VAL); + out_PREDICT_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); + in_PREDICT_ADDRESS [i] = interface->set_signal_in ("address", static_cast(ceil(log2(_param._nb_counter)))); + out_PREDICT_HISTORY [i] = interface->set_signal_out ("history", _param._size_counter); + } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; + out_BRANCH_COMPLETE_ACK = new SC_OUT (Tcontrol_t) * [_param._nb_branch_complete]; + in_BRANCH_COMPLETE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_branch_complete]; + in_BRANCH_COMPLETE_HISTORY = new SC_IN (Thistory_t) * [_param._nb_branch_complete]; + in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i) +#ifdef POSITION + , IN + , EAST + , "Interface branch complete" +#endif + ); + + in_BRANCH_COMPLETE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); + out_BRANCH_COMPLETE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); + in_BRANCH_COMPLETE_ADDRESS [i] = interface->set_signal_in ("address" , static_cast(ceil(log2(_param._nb_counter)))); + in_BRANCH_COMPLETE_HISTORY [i] = interface->set_signal_in ("history" , _param._size_counter); + in_BRANCH_COMPLETE_DIRECTION [i] = interface->set_signal_in ("direction", 1); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + string name_component; + + // =====[ component_Counter ]========================================= + + name_component = _name+"_Counter"; + + component_Counter = new morpheo::behavioural::generic::counter::Counter (name_component.c_str() +#ifdef STATISTICS + ,_param_statistics +#endif + ,*(_param._param_counter)); + + _component->set_component (component_Counter->_component +#ifdef POSITION + , 25 + , 25 + , 10 + , 10 +#endif + ); + + // =====[ component_RegisterFile ]==================================== + + name_component = _name+"_RegisterFile"; + + component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic(name_component.c_str(), +#ifdef STATISTICS + _param_statistics , +#endif + *(_param._param_registerfile)); + + _component->set_component (component_RegisterFile->_component +#ifdef POSITION + , 75 + , 75 + , 10 + , 10 +#endif + ); + + // ~~~~~[ Component - Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // =====[ component_RegisterFile - Instanciation ]==================== + +#ifdef POSITION + _component->interface_map (_name+"_RegisterFile","", + _name ,""); +#endif + + _component->port_map(_name+"_RegisterFile", "in_CLOCK" , _name,"in_CLOCK" ); + _component->port_map(_name+"_RegisterFile", "in_NRESET", _name,"in_NRESET"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { +#ifdef POSITION + _component->interface_map (_name+"_RegisterFile","read_" +toString(i), + _name ,"predict_"+toString(i)); +#endif + + _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_VAL" , _name, "in_PREDICT_"+toString(i)+"_VAL" ); + _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_ACK" , _name,"out_PREDICT_"+toString(i)+"_ACK" ); + _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_ADDRESS", _name, "in_PREDICT_"+toString(i)+"_ADDRESS"); + _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_DATA" , _name,"out_PREDICT_"+toString(i)+"_HISTORY"); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { +#ifdef POSITION + _component->interface_map (_name+"_RegisterFile","write_" +toString(i), + _name+"_Counter" ,"counter_"+toString(i)); +#endif + + _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); + _component->port_map(_name+"_RegisterFile","out_WRITE_"+toString(i)+"_ACK" , _name ,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK" ); + _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_ADDRESS", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); + _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA" , _name+"_Counter","out_COUNTER_" +toString(i)+"_DATA"); + } + + // =====[ component_Counter - Instanciation ]========================= + +#if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) + +#ifdef POSITION + _component->interface_map (_name+"_Counter","", + _name ,""); +#endif + + _component->port_map(_name+"_Counter", "in_CLOCK" , _name,"in_CLOCK" ); + _component->port_map(_name+"_Counter", "in_NRESET", _name,"in_NRESET"); + +#endif + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { +#ifdef POSITION + _component->interface_map (_name+"_Counter","counter_"+toString(i), + _name ,"branch_complete_"+toString(i)); + +#endif + + _component->port_map(_name+"_Counter", "in_COUNTER_" +toString(i)+"_DATA" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"); + _component->port_map(_name+"_Counter", "in_COUNTER_" +toString(i)+"_ADDSUB" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION"); + _component->port_map(_name+"_Counter", "out_COUNTER_"+toString(i)+"_DATA" , _name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA"); + } + +#ifdef POSITION + _component->generate_file(); +#endif + + log_printf(FUNC,Pattern_History_Table,"allocation","End"); + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_deallocation.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_deallocation.cpp (revision 45) @@ -0,0 +1,55 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + void Pattern_History_Table::deallocation (void) + { + log_printf(FUNC,Pattern_History_Table,"deallocation","Begin"); + + delete in_CLOCK; + delete in_NRESET; + + delete [] in_PREDICT_VAL ; + delete [] out_PREDICT_ACK ; + delete [] in_PREDICT_ADDRESS; + delete [] out_PREDICT_HISTORY; + + delete [] in_BRANCH_COMPLETE_VAL ; + delete [] out_BRANCH_COMPLETE_ACK ; + delete [] in_BRANCH_COMPLETE_ADDRESS; + delete [] in_BRANCH_COMPLETE_HISTORY; + delete [] in_BRANCH_COMPLETE_DIRECTION; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete component_Counter; + delete component_RegisterFile; + + delete _component; + + log_printf(FUNC,Pattern_History_Table,"deallocation","End"); + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_statistics.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_statistics.cpp (revision 45) @@ -0,0 +1,41 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + string Pattern_History_Table::statistics (uint32_t depth) + { + log_printf(FUNC,Pattern_History_Table,"statistics","Begin"); + + string stat_print = _stat->print(depth, + component_Counter ->statistics(depth+1) + + component_RegisterFile->statistics(depth+1) + ); + + log_printf(FUNC,Pattern_History_Table,"statistics","End"); + + return stat_print; + + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_transition.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_transition.cpp (revision 45) @@ -0,0 +1,45 @@ +#ifdef SYSTEMC +#if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + void Pattern_History_Table::transition (void) + { + log_printf(FUNC,Pattern_History_Table,"transition","Begin"); + +#ifdef STATISTICS + _stat->add(); +#endif + +#ifdef VHDL_TESTBENCH + vhdl_testbench_transition (); +#endif + + log_printf(FUNC,Pattern_History_Table,"transition","End"); + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl.cpp (revision 45) @@ -0,0 +1,49 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + void Pattern_History_Table::vhdl (void) + { + log_printf(FUNC,Pattern_History_Table,"vhdl","Begin"); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port (vhdl); + _component ->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_printf(FUNC,Pattern_History_Table,"vhdl","End"); + + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_body.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_body.cpp (revision 45) @@ -0,0 +1,42 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + void Pattern_History_Table::vhdl_body (Vhdl * & vhdl) + { + log_printf(FUNC,Pattern_History_Table,"vhdl_body","Begin"); + +// vhdl->set_body ("-- Output : always at '1'"); +// for (uint32_t i=0; i<_param._nb_branch_complete; i++) +// vhdl->set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';"); +// for (uint32_t i=0; i<_param._nb_prediction ; i++) +// vhdl->set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';"); +// vhdl->set_body (""); + + log_printf(FUNC,Pattern_History_Table,"vhdl_body","End"); + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_declaration.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_declaration.cpp (revision 45) @@ -0,0 +1,35 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + void Pattern_History_Table::vhdl_declaration (Vhdl * & vhdl) + { + log_printf(FUNC,Pattern_History_Table,"vhdl_declaration","Begin"); + + log_printf(FUNC,Pattern_History_Table,"vhdl_declaration","End"); + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_transition.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_transition.cpp (revision 45) @@ -0,0 +1,39 @@ +#ifdef VHDL_TESTBENCH +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + void Pattern_History_Table::vhdl_testbench_transition () + { + log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_transition","Begin"); + +// sc_start(0); + + _interfaces->testbench(); + + log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_transition","End"); + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics.cpp (revision 45) @@ -0,0 +1,46 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + Statistics::Statistics (string name , + morpheo::behavioural::Parameters_Statistics parameters_statistics , + Parameters parameters + ) : + morpheo::behavioural::Statistics(name , + parameters_statistics ), + _parameters(parameters) + { + log_printf(FUNC,Pattern_History_Table,"Statistics","Begin"); + log_printf(FUNC,Pattern_History_Table,"Statistics","End"); + }; + + Statistics::~Statistics () + { + log_printf(FUNC,Pattern_History_Table,"~Statistics","Begin"); + log_printf(FUNC,Pattern_History_Table,"~Statistics","End"); + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_add.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_add.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_add.cpp (revision 45) @@ -0,0 +1,37 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + void Statistics::add () + { + log_printf(FUNC,Pattern_History_Table,"add","Begin"); + log_printf(FUNC,Pattern_History_Table,"add","End"); + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_print.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_print.cpp (revision 45) @@ -0,0 +1,69 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + string Statistics::print (uint32_t depth , + string component_stat) + { + log_printf(FUNC,Pattern_History_Table,"print","Begin"); + + string tab = string(depth,'\t'); + ostringstream msg; + + msg << tab << "" << endl + << print_body(depth+1) + << component_stat + << tab << "" << endl; + + log_printf(FUNC,Pattern_History_Table,"print","End"); + + return msg.str(); + }; + + string Statistics::print (uint32_t depth) + { + string tab = string(depth,'\t'); + ostringstream msg; + + msg << tab << "" << endl + << print_body(depth+1) << endl + << tab << "" << endl; + + return msg.str(); + }; + + ostream& operator<< (ostream& output_stream , + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Statistics & x) + { + output_stream << x.print(0); + + return output_stream; + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_print_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_print_body.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_print_body.cpp (revision 45) @@ -0,0 +1,45 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace pattern_history_table { + + + string Statistics::print_body (uint32_t depth) + { + log_printf(FUNC,Pattern_History_Table,"print_body","Begin"); + + string tab = string(depth,'\t'); + ostringstream msg; + + msg << tab << ""; + + log_printf(FUNC,Pattern_History_Table,"print_body","End"); + + return msg.str(); + }; + +}; // end namespace pattern_history_table +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/Makefile (revision 45) @@ -0,0 +1,29 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_MORPHEO = ../../../../../.. + +LIBRARY = $(Two_Level_Branch_Predictor_LIBRARY) + +DIR_LIBRARY = $(Two_Level_Branch_Predictor_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Two_Level_Branch_Predictor_library + +library_clean : Two_Level_Branch_Predictor_library_clean + +include ../Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/config0.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/config0.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/config0.cfg (revision 45) @@ -0,0 +1,11 @@ +Two_Level_Branch_Predictor +0 1 +1 # have_bht +4 4 +1 # bht_size_shifter +32 32 *2 # bht_nb_shifter +1 1 +1 # have_pht +8 8 +1 # pht_size_counter +32 32 *2 # pht_nb_counter +2 2 +1 # pht_size_address_share +16 16 +1 # size_address +1 2 +1 # nb_prediction +1 2 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/config1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/config1.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/config1.cfg (revision 45) @@ -0,0 +1,11 @@ +Two_Level_Branch_Predictor +1 1 +1 # have_bht +4 4 +1 # bht_size_shifter +32 32 *2 # bht_nb_shifter +0 1 +1 # have_pht +8 8 +1 # pht_size_counter +32 32 *2 # pht_nb_counter +2 2 +1 # pht_size_address_share +16 16 +1 # size_address +1 2 +1 # nb_prediction +1 2 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/include/test.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/include/test.h (revision 45) @@ -0,0 +1,28 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include +#include + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::stage_1_ifetch; +using namespace morpheo::behavioural::stage_1_ifetch::predictor; +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor; + +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor; + +void test (string name, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/src/main.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/src/main.cpp (revision 45) @@ -0,0 +1,83 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/include/test.h" + +#define NB_PARAMS 10 + +void usage (string exec) +{ + cerr << " " << exec << " name_instance list_params" << endl + << "list_params is :" << endl + << " - have_bht (boolean )" << endl + << " - bht_size_shifter (unsigned int)" << endl + << " - bht_nb_shifter (unsigned int)" << endl + << " - have_pht (boolean )" << endl + << " - pht_size_counter (unsigned int)" << endl + << " - pht_nb_counter (unsigned int)" << endl + << " - pht_size_address_share (unsigned int)" << endl + << " - size_address (unsigned int)" << endl + << " - nb_prediction (unsigned int)" << endl + << " - nb_branch_complete (unsigned int)" << endl; + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + cout << " : Classic usage" << endl; + + if (argc != 2+NB_PARAMS) + usage (argv[0]); + + const string name = argv[1]; + const bool have_bht = atoi(argv[ 2]); + const uint32_t bht_size_shifter = atoi(argv[ 3]); + const uint32_t bht_nb_shifter = atoi(argv[ 4]); + const bool have_pht = atoi(argv[ 5]); + const uint32_t pht_size_counter = atoi(argv[ 6]); + const uint32_t pht_nb_counter = atoi(argv[ 7]); + const uint32_t pht_size_address_share = atoi(argv[ 8]); + const uint32_t size_address = atoi(argv[ 9]); + const uint32_t nb_prediction = atoi(argv[10]); + const uint32_t nb_branch_complete = atoi(argv[11]); + + try + { + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters param (have_bht , + bht_size_shifter , + bht_nb_shifter , + have_pht , + pht_size_counter , + pht_nb_counter , + pht_size_address_share , + size_address , + nb_prediction , + nb_branch_complete ); + + cout << param.print(1); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + cout << "<" << name << "> : " << error.what (); + exit (EXIT_FAILURE); + } + catch (...) + { + cerr << "<" << name << "> : This test must generate a error" << endl; + exit (EXIT_FAILURE); + } + + return (EXIT_SUCCESS); +} + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/src/test.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/SelfTest/src/test.cpp (revision 45) @@ -0,0 +1,307 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#define NB_ITERATION 512 + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/include/test.h" +#include "Common/include/Test.h" +#include "Common/include/BitManipulation.h" +void test (string name, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters param) +{ + cout << "<" << name << "> : Simulation SystemC" << endl; + + Two_Level_Branch_Predictor * _Two_Level_Branch_Predictor = new Two_Level_Branch_Predictor (name.c_str(), +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics(5,50), +#endif + param); + +#ifdef SYSTEMC + + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + sc_clock * CLOCK; + sc_signal * NRESET; + + sc_signal * PREDICT_VAL [param._nb_prediction]; + sc_signal * PREDICT_ACK [param._nb_prediction]; + sc_signal * PREDICT_ADDRESS [param._nb_prediction]; + sc_signal * PREDICT_BHT_HISTORY [param._nb_prediction]; + sc_signal * PREDICT_PHT_HISTORY [param._nb_prediction]; + + sc_signal * BRANCH_COMPLETE_VAL [param._nb_branch_complete]; + sc_signal * BRANCH_COMPLETE_ACK [param._nb_branch_complete]; + sc_signal * BRANCH_COMPLETE_ADDRESS [param._nb_branch_complete]; + sc_signal * BRANCH_COMPLETE_BHT_HISTORY [param._nb_branch_complete]; + sc_signal * BRANCH_COMPLETE_PHT_HISTORY [param._nb_branch_complete]; + sc_signal * BRANCH_COMPLETE_DIRECTION [param._nb_branch_complete]; + + // Rename signal + + string rename; + + CLOCK = new sc_clock ("clock", 1.0, 0.5); + NRESET = new sc_signal ("NRESET"); + + for (uint32_t i=0; i (rename.c_str()); + rename = "PREDICT_ACK_" +toString(i); + PREDICT_ACK [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_ADDRESS_" +toString(i); + PREDICT_ADDRESS [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_BHT_HISTORY_"+toString(i); + PREDICT_BHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "PREDICT_PHT_HISTORY_"+toString(i); + PREDICT_PHT_HISTORY [i] = new sc_signal (rename.c_str()); + } + + for (uint32_t i=0; i (rename.c_str()); + rename = "BRANCH_COMPLETE_ACK_" +toString(i); + BRANCH_COMPLETE_ACK [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_ADDRESS_" +toString(i); + BRANCH_COMPLETE_ADDRESS [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_BHT_HISTORY_"+toString(i); + BRANCH_COMPLETE_BHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_PHT_HISTORY_"+toString(i); + BRANCH_COMPLETE_PHT_HISTORY [i] = new sc_signal (rename.c_str()); + rename = "BRANCH_COMPLETE_DIRECTION_" +toString(i); + BRANCH_COMPLETE_DIRECTION [i] = new sc_signal (rename.c_str()); + } + + /******************************************************** + * Instanciation + ********************************************************/ + + cout << "<" << name << "> Instanciation of _Two_Level_Branch_Predictor" << endl; + + (*(_Two_Level_Branch_Predictor->in_CLOCK )) (*(CLOCK )); + (*(_Two_Level_Branch_Predictor->in_NRESET)) (*(NRESET)); + + for (uint32_t i=0; i in_PREDICT_VAL [i])) (*(PREDICT_VAL [i])); + (*(_Two_Level_Branch_Predictor->out_PREDICT_ACK [i])) (*(PREDICT_ACK [i])); + (*(_Two_Level_Branch_Predictor-> in_PREDICT_ADDRESS [i])) (*(PREDICT_ADDRESS [i])); + if (param._have_bht) + (*(_Two_Level_Branch_Predictor->out_PREDICT_BHT_HISTORY [i])) (*(PREDICT_BHT_HISTORY [i])); + if (param._have_pht) + (*(_Two_Level_Branch_Predictor->out_PREDICT_PHT_HISTORY [i])) (*(PREDICT_PHT_HISTORY [i])); + } + + for (uint32_t i=0; i in_BRANCH_COMPLETE_VAL [i])) (*(BRANCH_COMPLETE_VAL [i])); + (*(_Two_Level_Branch_Predictor->out_BRANCH_COMPLETE_ACK [i])) (*(BRANCH_COMPLETE_ACK [i])); + (*(_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_ADDRESS [i])) (*(BRANCH_COMPLETE_ADDRESS [i])); + if (param._have_bht) + (*(_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_BHT_HISTORY [i])) (*(BRANCH_COMPLETE_BHT_HISTORY [i])); + if (param._have_pht) + (*(_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_PHT_HISTORY [i])) (*(BRANCH_COMPLETE_PHT_HISTORY [i])); + (*(_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_DIRECTION [i])) (*(BRANCH_COMPLETE_DIRECTION [i])); + } + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + cout << "<" << name << "> Start Simulation ............" << endl; + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + const uint32_t num_port_predict = rand()%param._nb_prediction; + const uint32_t num_port_branch_complete = rand()%param._nb_branch_complete; + const Taddress_t address = rand()%param._size_address; + Tcontrol_t direction; + + sc_start(0); + + NRESET->write(0); + sc_start(5); + NRESET->write(1); + + for (uint32_t i=0; iwrite(0); + for (uint32_t i=0; iwrite(0); + + cout << "{"+toString(static_cast(sc_simulation_time()))+"} Initialisation" << endl; + + // Step 1 + BRANCH_COMPLETE_VAL [num_port_branch_complete]->write(1); + BRANCH_COMPLETE_DIRECTION [num_port_branch_complete]->write(0); + + if (param._have_pht) + { + // Step 1.1 -> pattern_history_table + + // Step 1.1.1 compute number of group. + uint32_t size_address_shift=0; + + if (param._have_bht) + size_address_shift=param._param_two_level_branch_predictor_glue->_pht_size_address_shift; + + uint32_t nb_group = (1<(sc_simulation_time()))+"} Init pht" << endl; + + BRANCH_COMPLETE_PHT_HISTORY [num_port_branch_complete]->write(0); + + // Step 1.1.2 for all group ... + for (uint32_t i=0; iwrite(i); + + for (uint32_t j=0; jwrite(j); + + sc_start(1); + + // wait ackwolegde + while (BRANCH_COMPLETE_ACK [num_port_branch_complete] -> read() == 0) + { + sc_start(1); + } + } + } + } + + if (param._have_bht) + { + // Step 1.2 -> branch_history_table + BRANCH_COMPLETE_BHT_HISTORY [num_port_branch_complete]->write(0); + + cout << "{"+toString(static_cast(sc_simulation_time()))+"} Init bht" << endl; + + for (uint32_t i=0; iwrite(i); + + sc_start(1); + } + + // wait ackwolegde + while (BRANCH_COMPLETE_ACK [num_port_branch_complete] -> read() == 0) + { + sc_start(1); + } + } + + // Step 2 + BRANCH_COMPLETE_VAL [num_port_branch_complete]->write(0); + PREDICT_ADDRESS [num_port_predict ]->write(address); + BRANCH_COMPLETE_ADDRESS [num_port_branch_complete]->write(address); + + cout << "{"+toString(static_cast(sc_simulation_time()))+"} Loop of Test" << endl + << " * predict_address : " << hex << address << dec << endl; + + // A lot of prediction + Tbht_history_t bht_history = 0; + Tpht_history_t pht_history [1<(1<(sc_simulation_time()))+"} Predict : bht_history " << bht_history << " - pht_history " << pht_history[bht_history] << endl; + + + // Ask a new prediction + PREDICT_VAL [num_port_predict ]->write(1); + + sc_start(1); + + // wait ackwolegde + while (PREDICT_ACK [num_port_predict] -> read() == 0) + { + sc_start(1); + } + PREDICT_ACK [num_port_predict ]->write(0); + + sc_start(0); + + // Test + cout << "{"+toString(static_cast(sc_simulation_time()))+"} Predict (Test) : " << endl; + if (param._have_bht) + { + cout << "\tbht_history " << PREDICT_BHT_HISTORY[num_port_predict]->read() << endl; + TEST(Tbht_history_t,bht_history ,PREDICT_BHT_HISTORY[num_port_predict]->read()); + } + if (param._have_pht) + { + cout << "\tpht_history " << PREDICT_PHT_HISTORY[num_port_predict]->read() << endl; + TEST(Tpht_history_t,pht_history[bht_history],PREDICT_PHT_HISTORY[num_port_predict]->read()); + } + + // update + direction = ((rand()%2)==1); + + BRANCH_COMPLETE_VAL [num_port_branch_complete]->write(1); + if (param._have_bht) + BRANCH_COMPLETE_BHT_HISTORY [num_port_branch_complete]->write(bht_history ); + + + if (param._have_pht) + BRANCH_COMPLETE_PHT_HISTORY [num_port_branch_complete]->write(pht_history[bht_history]); + BRANCH_COMPLETE_DIRECTION [num_port_branch_complete]->write(direction); + + if (param._have_pht) + if (direction == 0) + { + if (pht_history[bht_history] > 0) + pht_history[bht_history] --; + } + else + { + if (pht_history[bht_history] < (static_cast(1<(param._bht_size_shifter); + + sc_start(1); + + // wait ackwolegde + while (BRANCH_COMPLETE_ACK [num_port_branch_complete] -> read() == 0) + { + sc_start(1); + } + BRANCH_COMPLETE_VAL [num_port_branch_complete]->write(0); + } + + /******************************************************** + * Simulation - End + ********************************************************/ + + cout << "<" << name << "> ............ Stop Simulation" << endl; + +#endif + + delete _Two_Level_Branch_Predictor; +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile (revision 45) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = . +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libTwo_Level_Branch_Predictor_Glue.a + + +#-----[ include ]------------------------------------------ + +all : $(LIBRARY_NEED) + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile.defs (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile.defs (revision 45) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile.deps (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile.deps (revision 45) @@ -0,0 +1,31 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif + +Two_Level_Branch_Predictor_Glue = yes + +#-----[ Library ]------------------------------------------ +Two_Level_Branch_Predictor_Glue_LIBRARY = -lTwo_Level_Branch_Predictor_Glue \ + $(Behavioural_LIBRARY) + +Two_Level_Branch_Predictor_Glue_DIR_LIBRARY = -L$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/lib \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Two_Level_Branch_Predictor_Glue_library : + @$(MAKE) Behavioural_library + @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue --makefile=Makefile + +Two_Level_Branch_Predictor_Glue_library_clean : + @$(MAKE) Behavioural_library_clean + @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue --makefile=Makefile clean Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/Makefile (revision 45) @@ -0,0 +1,30 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_MORPHEO = ../../../../../../.. + +LIBRARY = $(Two_Level_Branch_Predictor_Glue_LIBRARY) + +DIR_LIBRARY = $(Two_Level_Branch_Predictor_Glue_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : library + @$(MAKE) all_selftest + +library : Two_Level_Branch_Predictor_Glue_library + +library_clean : Two_Level_Branch_Predictor_Glue_library_clean + +include ../Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/config0.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/config0.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/config0.cfg (revision 45) @@ -0,0 +1,10 @@ +Two_Level_Branch_Predictor_Glue +0 1 +1 # have_bht +11 11 +1 # bht_size_history +4 4 +1 # bht_size_address +1 1 +1 # have_pht +13 13 +1 # pht_size_address +2 2 +1 # pht_size_address_share +16 16 +1 # size_address +2 2 +1 # nb_prediction +2 2 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/config1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/config1.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/config1.cfg (revision 45) @@ -0,0 +1,10 @@ +Two_Level_Branch_Predictor_Glue +1 1 +1 # have_bht +11 11 +1 # bht_size_history +4 4 +1 # bht_size_address +0 1 +1 # have_pht +13 13 +1 # pht_size_address +0 2 +1 # pht_size_address_share +16 16 +1 # size_address +1 2 +1 # nb_prediction +1 2 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/configuration.cfg (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/configuration.cfg (revision 45) @@ -0,0 +1,10 @@ +Two_Level_Branch_Predictor_Glue +1 1 +1 # have_bht +11 11 +1 # bht_size_history +4 4 +1 # bht_size_address +0 1 +1 # have_pht +13 13 +1 # pht_size_address +0 2 +1 # pht_size_address_share +16 16 +1 # size_address +1 2 +1 # nb_prediction +1 2 +1 # nb_branch_complete Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/include/test.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/include/test.h (revision 45) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include +#include + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::stage_1_ifetch; +using namespace morpheo::behavioural::stage_1_ifetch::predictor; +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor; +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor; + +using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue; + +void test (string name, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/main.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/main.cpp (revision 45) @@ -0,0 +1,62 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/include/test.h" + +#define NB_PARAMS 9 + +void usage (string exec) +{ + cerr << " " << exec << " name_instance list_params" << endl + << "list_params is :" << endl + << " - have_bht (boolean )" << endl + << " - bht_size_history (unsigned int)" << endl + << " - bht_size_address (unsigned int)" << endl + << " - have_pht (boolean )" << endl + << " - pht_size_address (unsigned int)" << endl + << " - pht_size_address_share (unsigned int)" << endl + << " - size_address (unsigned int)" << endl + << " - nb_prediction (unsigned int)" << endl + << " - nb_branch_complete (unsigned int)" << endl; + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc != 2+NB_PARAMS) + usage (argv[0]); + + const string name = argv[1]; + const bool have_bht = atoi(argv[ 2]); + const uint32_t bht_size_history = atoi(argv[ 3]); + const uint32_t bht_size_address = atoi(argv[ 4]); + const bool have_pht = atoi(argv[ 5]); + const uint32_t pht_size_address = atoi(argv[ 6]); + const uint32_t pht_size_address_share = atoi(argv[ 7]); + const uint32_t size_address = atoi(argv[ 8]); + const uint32_t nb_prediction = atoi(argv[ 9]); + const uint32_t nb_branch_complete = atoi(argv[10]); + + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters param (have_bht , + bht_size_history , + bht_size_address , + have_pht , + pht_size_address , + pht_size_address_share, + size_address , + nb_prediction , + nb_branch_complete ); + + test (name,param); + + return (EXIT_SUCCESS); +} + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/test.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/test.cpp (revision 45) @@ -0,0 +1,251 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#define NB_ITERATION 64 + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/include/test.h" +#include "Common/include/BitManipulation.h" +#include "Common/include/Test.h" + +void test (string name, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters param) +{ + cout << "<" << name << "> : Simulation SystemC" << endl; + + try + { + cout << param.print(1); + param.test(); + } + catch (morpheo::ErrorMorpheo & error) + { + cout << "<" << name << "> : " << error.what (); + return; + } + catch (...) + { + cerr << "<" << name << "> : This test must generate a error" << endl; + exit (EXIT_FAILURE); + } + Two_Level_Branch_Predictor_Glue * _Two_Level_Branch_Predictor_Glue = new Two_Level_Branch_Predictor_Glue (name.c_str(), +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics(5,50), +#endif + param); + +#ifdef SYSTEMC + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + sc_clock CLOCK ("clock", 1.0, 0.5); + sc_signal NRESET; + + sc_signal PREDICT_BHT_ACK [param._nb_prediction]; + sc_signal PREDICT_PHT_ACK [param._nb_prediction]; + sc_signal PREDICT_ACK [param._nb_prediction]; + + sc_signal PREDICT_ADDRESS [param._nb_prediction]; + sc_signal PREDICT_BHT_HISTORY [param._nb_prediction]; + sc_signal PREDICT_BHT_ADDRESS [param._nb_prediction]; + sc_signal PREDICT_PHT_ADDRESS [param._nb_prediction]; + + sc_signal BRANCH_COMPLETE_BHT_ACK [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_PHT_ACK [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_ACK [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_ADDRESS [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_BHT_HISTORY [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_BHT_ADDRESS [param._nb_branch_complete]; + sc_signal BRANCH_COMPLETE_PHT_ADDRESS [param._nb_branch_complete]; + + /******************************************************** + * Instanciation + ********************************************************/ + + cout << "<" << name << "> Instanciation of _Two_Level_Branch_Predictor_Glue" << endl; + + (*(_Two_Level_Branch_Predictor_Glue->in_CLOCK)) (CLOCK); + (*(_Two_Level_Branch_Predictor_Glue->in_NRESET)) (NRESET); + + for (uint32_t i=0; i in_PREDICT_BHT_ACK [i])) (PREDICT_BHT_ACK [i]); + (*(_Two_Level_Branch_Predictor_Glue->out_PREDICT_BHT_ADDRESS [i])) (PREDICT_BHT_ADDRESS [i]); + } + if (param._have_bht and param._have_pht) + (*(_Two_Level_Branch_Predictor_Glue-> in_PREDICT_BHT_HISTORY [i])) (PREDICT_BHT_HISTORY [i]); + if (param._have_pht) + { + (*(_Two_Level_Branch_Predictor_Glue-> in_PREDICT_PHT_ACK [i])) (PREDICT_PHT_ACK [i]); + (*(_Two_Level_Branch_Predictor_Glue->out_PREDICT_PHT_ADDRESS [i])) (PREDICT_PHT_ADDRESS [i]); + } + (*(_Two_Level_Branch_Predictor_Glue->out_PREDICT_ACK [i])) (PREDICT_ACK [i]); + (*(_Two_Level_Branch_Predictor_Glue-> in_PREDICT_ADDRESS [i])) (PREDICT_ADDRESS [i]); + } + for (uint32_t i=0; i in_BRANCH_COMPLETE_BHT_ACK [i])) (BRANCH_COMPLETE_BHT_ACK [i]); + (*(_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_BHT_ADDRESS [i])) (BRANCH_COMPLETE_BHT_ADDRESS [i]); + } + if (param._have_bht and param._have_pht) + (*(_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_BHT_HISTORY [i])) (BRANCH_COMPLETE_BHT_HISTORY [i]); + + if (param._have_pht) + { + (*(_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_PHT_ACK [i])) (BRANCH_COMPLETE_PHT_ACK [i]); + (*(_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_PHT_ADDRESS [i])) (BRANCH_COMPLETE_PHT_ADDRESS [i]); + } + (*(_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_ACK [i])) (BRANCH_COMPLETE_ACK [i]); + (*(_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_ADDRESS [i])) (BRANCH_COMPLETE_ADDRESS [i]); + } + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + cout << "<" << name << "> Start Simulation ............" << endl; + // Initialisation + + Tcontrol_t predict_bht_ack; + Tcontrol_t predict_pht_ack; + + Tcontrol_t branch_complete_bht_ack; + Tcontrol_t branch_complete_pht_ack; + + srand(0); + //srand(time(NULL)); + + sc_start(0); + + cout << "{"+toString(static_cast(sc_simulation_time()))+"} Initialisation" << endl; + + NRESET.write(1); + + cout << "{"+toString(static_cast(sc_simulation_time()))+"} Test ack" << endl; + + for (uint32_t iteration=0; iteration(sc_simulation_time()))+"} Test address" << endl; + + for (uint32_t iteration=0; iteration(param._bht_size_address))); + + for (uint32_t i=0; i(param._bht_size_address))); + } + + // Pattern History Table + if (param._have_pht) + { + uint32_t shift = (param._have_bht==false)?0:(param._pht_size_address_shift); + + for (uint32_t i=0; i(param._pht_size_address))); + for (uint32_t i=0; i(param._pht_size_address))); + } + + sc_start(1); + } + /******************************************************** + * Simulation - End + ********************************************************/ + + cout << "<" << name << "> ............ Stop Simulation" << endl; + +#endif + + delete _Two_Level_Branch_Predictor_Glue; +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/VERSION =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/VERSION (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/VERSION (revision 45) @@ -0,0 +1,1 @@ +v0.3 Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/Makefile (revision 45) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = .. +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/Two_Level_Branch_Predictor_Glue.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/Two_Level_Branch_Predictor_Glue.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/Two_Level_Branch_Predictor_Glue.tex (revision 45) @@ -0,0 +1,38 @@ +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/sty/header.sty (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/sty/header.sty (revision 45) @@ -0,0 +1,12 @@ +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Two\_Level\_Branch\_Predictor\_Glue} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/01_introduction.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/01_introduction.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/02_features.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/02_features.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/03_description.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/03_description.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/04_pinout.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/04_pinout.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/05_parameters.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/05_parameters.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/06_performance.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/06_performance.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/07_details.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/07_details.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/08_history.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/08_history.tex (revision 45) @@ -0,0 +1,10 @@ +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/root.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/doc/tex/root.tex (revision 45) @@ -0,0 +1,8 @@ +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h (revision 45) @@ -0,0 +1,68 @@ +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Parameters_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" +#include "Behavioural/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : const bool _have_bht ; + public : const uint32_t _bht_size_history ; + public : const uint32_t _bht_size_address ; + public : const bool _have_pht ; + public : const uint32_t _pht_size_address ; + public : const uint32_t _pht_size_address_share; + public : const uint32_t _size_address ; + public : const uint32_t _nb_prediction ; + public : const uint32_t _nb_branch_complete ; + public : const uint32_t _pht_size_address_shift; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (bool have_bht , + uint32_t bht_size_history , + uint32_t bht_size_address , + bool have_pht , + uint32_t pht_size_address , + uint32_t pht_size_address_share, + uint32_t size_address , + uint32_t nb_prediction , + uint32_t nb_branch_complete ); + + public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : string msg_error (void); + + public : string print (uint32_t depth); + public : friend ostream& operator<< (ostream& output_stream, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters & x); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h (revision 45) @@ -0,0 +1,61 @@ +#ifdef STATISTICS +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Statistics_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Statistics_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" +#include "Behavioural/include/Statistics.h" +#include "Behavioural/include/Parameters_Statistics.h" +//#include "Behavioural/Generic/Group/include/Statistics.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h" + +//using namespace morpheo::behavioural::generic::group; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + class Statistics : public morpheo::behavioural::Statistics + { + // -----[ fields ]---------------------------------------------------- + private : const Parameters _parameters; + + // -----[ methods ]--------------------------------------------------- + public : Statistics (string name , + morpheo::behavioural::Parameters_Statistics parameters_statistics , + Parameters parameters + ); +//public : Statistics (Statistics & stat); + public : ~Statistics () ; + + public : string print_body (uint32_t depth); + public : string print (uint32_t depth); + public : void add (); + + public : friend ostream& operator<< (ostream& output_stream, + const Statistics & x); + + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h (revision 45) @@ -0,0 +1,148 @@ +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Two_Level_Branch_Predictor_Glue_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Two_Level_Branch_Predictor_Glue_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h" +#endif +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Component.h" + +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + class Two_Level_Branch_Predictor_Glue +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const string _name; + + protected : const Parameters _param; +//#ifdef STATISTICS +//protected : const morpheo::behavioural::Parameters_Statistics _param_statistics; +//#endif + +#ifdef STATISTICS + private : Statistics * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // Interface + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + public : SC_IN (Tcontrol_t) ** in_PREDICT_BHT_ACK ; + public : SC_IN (Tcontrol_t) ** in_PREDICT_PHT_ACK ; + public : SC_OUT(Tcontrol_t) ** out_PREDICT_ACK ; + + public : SC_IN (Taddress_t) ** in_PREDICT_ADDRESS ; + public : SC_IN (Tbht_history_t) ** in_PREDICT_BHT_HISTORY ; + public : SC_OUT(Taddress_t) ** out_PREDICT_BHT_ADDRESS ; + public : SC_OUT(Taddress_t) ** out_PREDICT_PHT_ADDRESS ; + + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_BHT_ACK ; + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_PHT_ACK ; + public : SC_OUT(Tcontrol_t) ** out_BRANCH_COMPLETE_ACK ; + + public : SC_IN (Taddress_t) ** in_BRANCH_COMPLETE_ADDRESS ; + public : SC_IN (Tbht_history_t) ** in_BRANCH_COMPLETE_BHT_HISTORY; + public : SC_OUT(Taddress_t) ** out_BRANCH_COMPLETE_BHT_ADDRESS; + public : SC_OUT(Taddress_t) ** out_BRANCH_COMPLETE_PHT_ADDRESS; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Two_Level_Branch_Predictor_Glue); +#endif + public : Two_Level_Branch_Predictor_Glue ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics param_statistics, +#endif + Parameters param ); + + public : Two_Level_Branch_Predictor_Glue (Parameters param ); + public : ~Two_Level_Branch_Predictor_Glue (void); + +#ifdef SYSTEMC + private : void allocation (void); + private : void deallocation (void); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + public : void transition (void); +#endif + public : void genMealy_predict_ack (void); + public : void genMealy_predict_bht_address (void); + public : void genMealy_predict_pht_address (void); + public : void genMealy_branch_complete_ack (void); + public : void genMealy_branch_complete_bht_address (void); + public : void genMealy_branch_complete_pht_address (void); +#endif + +#ifdef STATISTICS + public : string statistics (uint32_t depth); +#endif +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif +#ifdef VHDL_TESTBENCH + private : void vhdl_testbench_transition (void); +#endif + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Types.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Types.h (revision 45) @@ -0,0 +1,35 @@ +#ifdef SYSTEMC +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Type_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Type_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + typedef uint32_t Taddress_t ; + typedef uint32_t Tbht_history_t; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters.cpp (revision 45) @@ -0,0 +1,73 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + Parameters::Parameters (bool have_bht , + uint32_t bht_size_history , + uint32_t bht_size_address , + bool have_pht , + uint32_t pht_size_address , + uint32_t pht_size_address_share , + uint32_t size_address , + uint32_t nb_prediction , + uint32_t nb_branch_complete ): + _have_bht (have_bht ), + _bht_size_history (bht_size_history ), + _bht_size_address (bht_size_address ), + _have_pht (have_pht ), + _pht_size_address (pht_size_address ), + _pht_size_address_share (pht_size_address_share ), + _size_address (size_address ), + _nb_prediction (nb_prediction ), + _nb_branch_complete (nb_branch_complete ), + _pht_size_address_shift (bht_size_history-pht_size_address_share) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Parameters","Begin"); + test(); + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Parameters","End"); + }; + + Parameters::Parameters (Parameters & param): + _have_bht (param._have_bht ), + _bht_size_history (param._bht_size_history ), + _bht_size_address (param._bht_size_address ), + _have_pht (param._have_pht ), + _pht_size_address (param._pht_size_address ), + _pht_size_address_share (param._pht_size_address_share ), + _size_address (param._size_address ), + _nb_prediction (param._nb_prediction ), + _nb_branch_complete (param._nb_branch_complete ), + _pht_size_address_shift (param._pht_size_address_shift ) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Parameters","Begin"); + test(); + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Parameters","End"); + }; + + Parameters::~Parameters () + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Parameters","Begin"); + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Parameters","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters_msg_error.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters_msg_error.cpp (revision 45) @@ -0,0 +1,52 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Types.h" +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + string Parameters::msg_error(void) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"msg_error","Begin"); + + string msg = ""; + + if ((_have_bht and _have_pht) and (_pht_size_address_share >= _pht_size_address)) + { + msg += " - You can't have higher pht_size_address_share >= pht_size_address\n"; + msg += " * pht_size_address : " + toString(_pht_size_address ) + "\n"; + msg += " * pht_size_address_share : " + toString(_pht_size_address_share) + "\n"; + } + if ((_have_bht and _have_pht) and (_bht_size_history > _pht_size_address)) + { + msg += " - You can't have higher bht_size_history > pht_size_address\n"; + msg += " * bht_size_history : " + toString(_bht_size_history ) + "\n"; + msg += " * pht_size_address : " + toString(_pht_size_address ) + "\n"; + } + + return msg; + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"msg_error","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters_print.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters_print.cpp (revision 45) @@ -0,0 +1,59 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h" +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + string Parameters::print (uint32_t depth) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"print","Begin"); + + string tab = string(depth,'\t'); + ostringstream msg; + msg << tab << "" << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t " << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "" << endl; + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"print","End"); + + return msg.str(); + }; + + ostream& operator<< (ostream& output_stream , + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters & x) + { + output_stream << x.print(0); + + return output_stream; + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics.cpp (revision 45) @@ -0,0 +1,46 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + Statistics::Statistics (string name , + morpheo::behavioural::Parameters_Statistics parameters_statistics , + Parameters parameters + ) : + morpheo::behavioural::Statistics(name , + parameters_statistics ), + _parameters(parameters) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Statistics","Begin"); + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Statistics","End"); + }; + + Statistics::~Statistics () + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Statistics","Begin"); + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Statistics","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_add.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_add.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_add.cpp (revision 45) @@ -0,0 +1,37 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + void Statistics::add () + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"add","Begin"); + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"add","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_print.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_print.cpp (revision 45) @@ -0,0 +1,55 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + string Statistics::print (uint32_t depth) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"print","Begin"); + + string tab = string(depth,'\t'); + ostringstream msg; + + msg << tab << "" << endl + << print_body(depth+1) << endl + << tab << "" << endl; + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"print","End"); + + return msg.str(); + }; + + ostream& operator<< (ostream& output_stream , + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Statistics & x) + { + output_stream << x.print(0); + + return output_stream; + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_print_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_print_body.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_print_body.cpp (revision 45) @@ -0,0 +1,45 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + string Statistics::print_body (uint32_t depth) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"print_body","Begin"); + + string tab = string(depth,'\t'); + ostringstream msg; + + msg << tab << ""; + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"print_body","End"); + + return msg.str(); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue.cpp (revision 45) @@ -0,0 +1,205 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + +#ifdef SYSTEMC + Two_Level_Branch_Predictor_Glue::Two_Level_Branch_Predictor_Glue (sc_module_name name, +#else + Two_Level_Branch_Predictor_Glue::Two_Level_Branch_Predictor_Glue (string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics param_statistics, +#endif + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters param ): + _name (name) + ,_param (param) +// #ifdef STATISTICS +// ,_param_statistics (param_statistics) +// #endif + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Two_Level_Branch_Predictor_Glue","Begin"); + + allocation (); + +#ifdef STATISTICS + // Allocation of statistics + _stat = new Statistics (static_cast(_name), + param_statistics , + param); +#endif + +#ifdef VHDL + // generate the vhdl + vhdl(); +#endif + +#ifdef SYSTEMC +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + SC_METHOD (transition); + dont_initialize (); + sensitive_pos << *(in_CLOCK); +#endif + + SC_METHOD (genMealy_predict_ack); + dont_initialize (); + sensitive_neg << *(in_CLOCK); + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + if (_param._have_bht) + sensitive << (*(in_PREDICT_BHT_ACK [i])); + if (_param._have_pht) + sensitive << (*(in_PREDICT_PHT_ACK [i])); + } + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + if (_param._have_bht) + (*(out_PREDICT_ACK [i])) (*(in_PREDICT_BHT_ACK [i])); + if (_param._have_pht) + (*(out_PREDICT_ACK [i])) (*(in_PREDICT_PHT_ACK [i])); + } +#endif + + if (_param._have_bht) + { + SC_METHOD (genMealy_predict_bht_address); + dont_initialize (); + sensitive_neg << *(in_CLOCK); + for (uint32_t i=0; i<_param._nb_prediction; i++) + sensitive << (*(in_PREDICT_ADDRESS [i])); + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param._nb_prediction; i++) + (*(out_PREDICT_BHT_ADDRESS [i])) (*(in_PREDICT_ADDRESS [i])); +#endif + } + + if (_param._have_pht) + { + SC_METHOD (genMealy_predict_pht_address); + dont_initialize (); + sensitive_neg << *(in_CLOCK); + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + if (_param._have_bht) + sensitive << (*(in_PREDICT_BHT_HISTORY [i])); + sensitive << (*(in_PREDICT_ADDRESS [i])); + } + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + (*(out_PREDICT_PHT_ADDRESS [i])) (*(in_PREDICT_ADDRESS [i])); + if (_param._have_bht) + (*(out_PREDICT_PHT_ADDRESS [i])) (*(in_PREDICT_BHT_HISTORY [i])); + } +#endif + } + + SC_METHOD (genMealy_branch_complete_ack); + dont_initialize (); + sensitive_neg << *(in_CLOCK); + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + if (_param._have_bht) + sensitive << (*(in_BRANCH_COMPLETE_BHT_ACK [i])); + if (_param._have_pht) + sensitive << (*(in_BRANCH_COMPLETE_PHT_ACK [i])); + } + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + if (_param._have_bht) + (*(out_BRANCH_COMPLETE_ACK [i])) (*(in_BRANCH_COMPLETE_BHT_ACK [i])); + if (_param._have_pht) + (*(out_BRANCH_COMPLETE_ACK [i])) (*(in_BRANCH_COMPLETE_PHT_ACK [i])); + } +#endif + + if (_param._have_bht) + { + SC_METHOD (genMealy_branch_complete_bht_address); + dont_initialize (); + sensitive_neg << *(in_CLOCK); + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + sensitive << (*(in_BRANCH_COMPLETE_ADDRESS [i])); + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + (*(out_BRANCH_COMPLETE_BHT_ADDRESS [i])) (*(in_BRANCH_COMPLETE_ADDRESS [i])); +#endif + } + + if (_param._have_pht) + { + SC_METHOD (genMealy_branch_complete_pht_address); + dont_initialize (); + sensitive_neg << *(in_CLOCK); + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + if (_param._have_bht) + sensitive << (*(in_BRANCH_COMPLETE_BHT_HISTORY [i])); + sensitive << (*(in_BRANCH_COMPLETE_ADDRESS [i])); + } + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + (*(out_BRANCH_COMPLETE_PHT_ADDRESS [i])) (*(in_BRANCH_COMPLETE_ADDRESS [i])); + if (_param._have_bht) + (*(out_BRANCH_COMPLETE_PHT_ADDRESS [i])) (*(in_BRANCH_COMPLETE_BHT_HISTORY [i])); + } +#endif + } + +#endif + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Two_Level_Branch_Predictor_Glue","End"); + }; + + Two_Level_Branch_Predictor_Glue::~Two_Level_Branch_Predictor_Glue (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Two_Level_Branch_Predictor_Glue","Begin"); + +#ifdef STATISTICS + _stat->generate_file(statistics(0)); + + delete _stat; +#endif + +#ifdef SYSTEMC + deallocation (); +#endif + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Two_Level_Branch_Predictor_Glue","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_allocation.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_allocation.cpp (revision 45) @@ -0,0 +1,154 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + void Two_Level_Branch_Predictor_Glue::allocation (void) + { + string rename; + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"allocation","Begin"); + + _component = new Component (); + + Entity * entity = _component->set_entity (_name + ,"Two_Level_Branch_Predictor_Glue" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + , IN + , SOUTH + , "Generalist interface" +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1,CLOCK_VHDL_NO); + in_NRESET = interface->set_signal_in ("nreset",1,RESET_VHDL_NO); + } + + // ~~~~~[ Interface : "Predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (_param._have_bht) + { + in_PREDICT_BHT_ACK = new SC_IN (Tcontrol_t) * [_param._nb_prediction]; + out_PREDICT_BHT_ADDRESS = new SC_OUT(Taddress_t) * [_param._nb_prediction]; + } + if (_param._have_pht) + { + in_PREDICT_PHT_ACK = new SC_IN (Tcontrol_t) * [_param._nb_prediction]; + out_PREDICT_PHT_ADDRESS = new SC_OUT(Taddress_t) * [_param._nb_prediction]; + } + if (_param._have_bht and _param._have_pht) + in_PREDICT_BHT_HISTORY = new SC_IN (Tbht_history_t) * [_param._nb_prediction]; + out_PREDICT_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_prediction]; + in_PREDICT_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_prediction]; + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) +#ifdef POSITION + , IN + , WEST + , "Interface Predict" +#endif + ); + + if (_param._have_bht) + { + in_PREDICT_BHT_ACK [i] = interface->set_signal_in ("bht_ack" ,1); + out_PREDICT_BHT_ADDRESS [i] = interface->set_signal_out ("bht_address",_param._bht_size_address); + } + if (_param._have_pht) + { + in_PREDICT_PHT_ACK [i] = interface->set_signal_in ("pht_ack" ,1); + out_PREDICT_PHT_ADDRESS [i] = interface->set_signal_out ("pht_address",_param._pht_size_address); + } + if (_param._have_bht and _param._have_pht) + in_PREDICT_BHT_HISTORY [i] = interface->set_signal_in ("bht_history",_param._bht_size_history); + out_PREDICT_ACK [i] = interface->set_signal_out ("ack" ,1); + in_PREDICT_ADDRESS [i] = interface->set_signal_in ("address" ,_param._size_address); + } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + if (_param._have_bht) + { + in_BRANCH_COMPLETE_BHT_ACK = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; + out_BRANCH_COMPLETE_BHT_ADDRESS = new SC_OUT(Taddress_t) * [_param._nb_branch_complete]; + } + if (_param._have_pht) + { + in_BRANCH_COMPLETE_PHT_ACK = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; + out_BRANCH_COMPLETE_PHT_ADDRESS = new SC_OUT(Taddress_t) * [_param._nb_branch_complete]; + } + if (_param._have_bht and _param._have_pht) + in_BRANCH_COMPLETE_BHT_HISTORY = new SC_IN (Tbht_history_t) * [_param._nb_branch_complete]; + + out_BRANCH_COMPLETE_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_branch_complete]; + in_BRANCH_COMPLETE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_branch_complete]; + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i) +#ifdef POSITION + , IN + , EAST + , "Interface branch complete" +#endif + ); + if (_param._have_bht) + { + in_BRANCH_COMPLETE_BHT_ACK [i] = interface->set_signal_in ("bht_ack" ,1); + out_BRANCH_COMPLETE_BHT_ADDRESS [i] = interface->set_signal_out ("bht_address",_param._bht_size_address); + } + if (_param._have_pht) + { + in_BRANCH_COMPLETE_PHT_ACK [i] = interface->set_signal_in ("pht_ack" ,1); + out_BRANCH_COMPLETE_PHT_ADDRESS [i] = interface->set_signal_out ("pht_address",_param._pht_size_address); + } + if (_param._have_bht and _param._have_pht) + in_BRANCH_COMPLETE_BHT_HISTORY [i] = interface->set_signal_in ("bht_history",_param._bht_size_history); + + out_BRANCH_COMPLETE_ACK [i] = interface->set_signal_out ("ack" ,1); + in_BRANCH_COMPLETE_ADDRESS [i] = interface->set_signal_in ("address" ,_param._size_address); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#ifdef POSITION + _component->generate_file(); +#endif + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"allocation","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_deallocation.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_deallocation.cpp (revision 45) @@ -0,0 +1,72 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + void Two_Level_Branch_Predictor_Glue::deallocation (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"deallocation","Begin"); + + delete in_CLOCK; + delete in_NRESET; + + if (_param._have_bht) + { + delete [] in_PREDICT_BHT_ACK ; + delete [] out_PREDICT_BHT_ADDRESS; + } + if (_param._have_pht) + { + delete [] in_PREDICT_PHT_ACK ; + delete [] out_PREDICT_PHT_ADDRESS; + } + if (_param._have_bht and _param._have_pht) + delete [] in_PREDICT_BHT_HISTORY; + + delete [] out_PREDICT_ACK ; + delete [] in_PREDICT_ADDRESS ; + + if (_param._have_bht) + { + delete [] in_BRANCH_COMPLETE_BHT_ACK ; + delete [] out_BRANCH_COMPLETE_BHT_ADDRESS; + } + if (_param._have_pht) + { + delete [] in_BRANCH_COMPLETE_PHT_ACK ; + delete [] out_BRANCH_COMPLETE_PHT_ADDRESS; + } + if (_param._have_bht and _param._have_pht) + delete [] in_BRANCH_COMPLETE_BHT_HISTORY; + delete [] out_BRANCH_COMPLETE_ACK ; + delete [] in_BRANCH_COMPLETE_ADDRESS ; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete _component; + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"deallocation","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_ack.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_ack.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_ack.cpp (revision 45) @@ -0,0 +1,43 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" +#include "Common/include/BitManipulation.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + void Two_Level_Branch_Predictor_Glue::genMealy_branch_complete_ack (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_ack","Begin"); + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + // Ackwnolegde + bool bht_ack = (not _param._have_bht) or PORT_READ(in_BRANCH_COMPLETE_BHT_ACK [i]); + bool pht_ack = (not _param._have_pht) or PORT_READ(in_BRANCH_COMPLETE_PHT_ACK [i]); + + PORT_WRITE (out_BRANCH_COMPLETE_ACK [i], bht_ack and pht_ack); + } + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_ack","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_bht_address.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_bht_address.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_bht_address.cpp (revision 45) @@ -0,0 +1,43 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" +#include "Common/include/BitManipulation.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + void Two_Level_Branch_Predictor_Glue::genMealy_branch_complete_bht_address (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_address","Begin"); + + if (_param._have_bht) + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + // Address + Taddress_t address = PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]); + + PORT_WRITE (out_BRANCH_COMPLETE_BHT_ADDRESS [i], range(_param._size_address, address, _param._bht_size_address)); + } + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_address","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_pht_address.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_pht_address.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_pht_address.cpp (revision 45) @@ -0,0 +1,54 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" +#include "Common/include/BitManipulation.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + void Two_Level_Branch_Predictor_Glue::genMealy_branch_complete_pht_address (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_address","Begin"); + + if (_param._have_pht) + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + // Address + Taddress_t address = PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]); + Tbht_history_t history = 0; + + if (_param._have_bht) + { + history = PORT_READ (in_BRANCH_COMPLETE_BHT_HISTORY [i]); + address = address << _param._pht_size_address_shift; + } + + Taddress_t pht_address = (history ^ address) & gen_mask(_param._pht_size_address); + + log_printf(TRACE,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_address","out_BRANCH_COMPLETE_PHT_ADDRESS [%d]= %.8x xor %.8x<<%d = %.8x",i,history,PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]),_param._pht_size_address_shift, pht_address); + + PORT_WRITE (out_BRANCH_COMPLETE_PHT_ADDRESS [i], pht_address); + } + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_address","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_ack.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_ack.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_ack.cpp (revision 45) @@ -0,0 +1,43 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" +#include "Common/include/BitManipulation.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + void Two_Level_Branch_Predictor_Glue::genMealy_predict_ack (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_predict_ack","Begin"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + // Ackwnolegde + bool bht_ack = (not _param._have_bht) or PORT_READ(in_PREDICT_BHT_ACK [i]); + bool pht_ack = (not _param._have_pht) or PORT_READ(in_PREDICT_PHT_ACK [i]); + + PORT_WRITE (out_PREDICT_ACK [i], bht_ack and pht_ack); + } + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_predict_ack","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_bht_address.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_bht_address.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_bht_address.cpp (revision 45) @@ -0,0 +1,44 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" +#include "Common/include/BitManipulation.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + void Two_Level_Branch_Predictor_Glue::genMealy_predict_bht_address (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_predict_address","Begin"); + + if (_param._have_bht) + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + // Address + Taddress_t address = PORT_READ(in_PREDICT_ADDRESS [i]); + Taddress_t bht_address = range(_param._size_address, address, _param._bht_size_address); + + PORT_WRITE (out_PREDICT_BHT_ADDRESS [i], bht_address); + } + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_predict_address","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_pht_address.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_pht_address.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_pht_address.cpp (revision 45) @@ -0,0 +1,50 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" +#include "Common/include/BitManipulation.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + void Two_Level_Branch_Predictor_Glue::genMealy_predict_pht_address (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_predict_address","Begin"); + + if (_param._have_pht) + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + // Address + Taddress_t address = PORT_READ(in_PREDICT_ADDRESS [i]); + Tbht_history_t history = 0; + + if (_param._have_bht) + { + history = PORT_READ (in_PREDICT_BHT_HISTORY [i]); + address = address << _param._pht_size_address_shift; + } + + PORT_WRITE (out_PREDICT_PHT_ADDRESS [i], (history xor address) & gen_mask(_param._pht_size_address)); + } + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_predict_address","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_statistics.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_statistics.cpp (revision 45) @@ -0,0 +1,39 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + string Two_Level_Branch_Predictor_Glue::statistics (uint32_t depth) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"statistics","Begin"); + + string txt = _stat->print(depth); + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"statistics","End"); + + return txt; + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_transition.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_transition.cpp (revision 45) @@ -0,0 +1,45 @@ +#ifdef SYSTEMC +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + void Two_Level_Branch_Predictor_Glue::transition (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"transition","Begin"); + +#ifdef STATISTICS + _stat->add(); +#endif + +#ifdef VHDL_TESTBENCH + vhdl_testbench_transition (); +#endif + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"transition","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl.cpp (revision 45) @@ -0,0 +1,49 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + void Two_Level_Branch_Predictor_Glue::vhdl (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl","Begin"); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port (vhdl); + _component ->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl","End"); + + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_body.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_body.cpp (revision 45) @@ -0,0 +1,160 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + void Two_Level_Branch_Predictor_Glue::vhdl_body (Vhdl * & vhdl) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_body","Begin"); + + vhdl->set_body ("-- ack output"); + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + string bht_ack, pht_ack; + + if (_param._have_bht) + bht_ack = "in_PREDICT_"+toString(i)+"_BHT_ACK"; + else + bht_ack = "'1'"; + + if (_param._have_pht) + pht_ack = "in_PREDICT_"+toString(i)+"_PHT_ACK"; + else + pht_ack = "'1'"; + + vhdl->set_body ("out_PREDICT_"+toString(i)+"_ACK <= "+bht_ack+" and "+pht_ack+";"); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + string bht_ack, pht_ack; + + if (_param._have_bht) + bht_ack = "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_ACK"; + else + bht_ack = "'1'"; + + if (_param._have_pht) + pht_ack = "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_ACK"; + else + pht_ack = "'1'"; + + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_ACK <= "+bht_ack+" and "+pht_ack+";"); + } + + vhdl->set_body (""); + vhdl->set_body ("-- address output"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + // The address is higher than the address size of bht + if (_param._have_bht) + vhdl->set_body ("out_PREDICT_"+toString(i)+"_BHT_ADDRESS <= in_PREDICT_"+toString(i)+"_ADDRESS"+std_logic_range(_param._bht_size_address)+";"); + + if (_param._have_pht) + { + // For pht : 2 cases + if (_param._have_bht) + { + uint32_t min = 0; + uint32_t max = _param._pht_size_address; + + // A lot of case : + // + // pht_size_addr + // addr bht_history + // + // ---------] | + // |[--------- + // + // -----------|----] share + // | [------- + // + // -----------|----] no share + // | [----- + // + + // Test if address is share + if (_param._pht_size_address_shift > 0) + { + min = _param._pht_size_address_shift; + vhdl->set_body ("out_PREDICT_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(min) + " <= in_PREDICT_"+toString(i)+"_BHT_HISTORY"+std_logic_range(min)+";"); + } + + if (_param._bht_size_history < _param._pht_size_address) + { + max = _param._bht_size_history; + vhdl->set_body ("out_PREDICT_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(_param._pht_size_address-1,max) + " <= in_PREDICT_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address-1-_param._pht_size_address_shift, _param._pht_size_address_share)+";"); + } + + // intersection + if (_param._pht_size_address_share > 0) + vhdl->set_body ("out_PREDICT_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(max-1,min) + " <= in_PREDICT_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address_share-1,0)+" xor in_PREDICT_"+toString(i)+"_BHT_HISTORY"+std_logic_range(max-1,min)+";"); + } + else + vhdl->set_body ("out_PREDICT_"+toString(i)+"_PHT_ADDRESS <= in_PREDICT_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address)+";"); + } + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + // The address is higher than the address size of bht + if (_param._have_bht) + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_BHT_ADDRESS <= in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"+std_logic_range(_param._bht_size_address)+";"); + + if (_param._have_pht) + { + // For pht : 2 cases + if (_param._have_bht) + { + uint32_t min = 0; + uint32_t max = _param._pht_size_address; + + // Test if address is share + if (_param._pht_size_address_shift > 0) + { + min = _param._pht_size_address_shift; + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(min) + " <= in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY"+std_logic_range(min)+";"); + } + + if (_param._bht_size_history < _param._pht_size_address) + { + max = _param._bht_size_history; + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(_param._pht_size_address-1,max) + " <= in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address-1-_param._pht_size_address_shift, _param._pht_size_address_share)+";"); + } + + // intersection + if (_param._pht_size_address_share > 0) + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(max-1,min) + " <= in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address_share-1,0)+" xor in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY"+std_logic_range(max-1,min)+";"); + } + else + vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS <= in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address)+";"); + } + } + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_body","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_declaration.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_declaration.cpp (revision 45) @@ -0,0 +1,34 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + void Two_Level_Branch_Predictor_Glue::vhdl_declaration (Vhdl * & vhdl) + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_declaration","Begin"); + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_declaration","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_transition.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_transition.cpp (revision 45) @@ -0,0 +1,39 @@ +#ifdef VHDL_TESTBENCH +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { +namespace two_level_branch_predictor_glue { + + + void Two_Level_Branch_Predictor_Glue::vhdl_testbench_transition () + { + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_testbench_transition","Begin"); + +// sc_start(0); + + _interfaces->testbench(); + + log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_testbench_transition","End"); + }; + +}; // end namespace two_level_branch_predictor_glue +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/VERSION =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/VERSION (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/VERSION (revision 45) @@ -0,0 +1,1 @@ +v0.2 Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/Makefile (revision 45) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = .. +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/Two_Level_Branch_Predictor.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/Two_Level_Branch_Predictor.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/Two_Level_Branch_Predictor.tex (revision 45) @@ -0,0 +1,38 @@ +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/sty/header.sty (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/sty/header.sty (revision 45) @@ -0,0 +1,12 @@ +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Two\_Level\_Branch\_Predictor} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/01_introduction.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/01_introduction.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/02_features.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/02_features.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/03_description.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/03_description.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/04_pinout.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/04_pinout.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/05_parameters.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/05_parameters.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/06_performance.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/06_performance.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/07_details.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/07_details.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/08_history.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/08_history.tex (revision 45) @@ -0,0 +1,10 @@ +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/root.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/doc/tex/root.tex (revision 45) @@ -0,0 +1,8 @@ +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/include/Parameters.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/include/Parameters.h (revision 45) @@ -0,0 +1,77 @@ +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Parameters_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" +#include "Behavioural/include/Parameters.h" +// Internal structure +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : const bool _have_bht ; + public : const uint32_t _bht_size_shifter ; + public : const uint32_t _bht_nb_shifter ; + public : const bool _have_pht ; + public : const uint32_t _pht_size_counter ; + public : const uint32_t _pht_nb_counter ; + public : const uint32_t _pht_size_address_share; + public : const uint32_t _size_address ; + public : const uint32_t _nb_prediction ; + public : const uint32_t _nb_branch_complete ; + + public : const uint32_t _bht_size_address ; + public : const uint32_t _pht_size_address ; + + public : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Parameters * _param_branch_history_table; + public : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters * _param_pattern_history_table; + public : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters * _param_two_level_branch_predictor_glue; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (bool have_bht , + uint32_t bht_size_shifter , + uint32_t bht_nb_shifter , + bool have_pht , + uint32_t pht_size_counter , + uint32_t pht_nb_counter , + uint32_t pht_size_address_share, + uint32_t size_address , + uint32_t nb_prediction , + uint32_t nb_branch_complete ); + + public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : string msg_error (void); + + public : string print (uint32_t depth); + public : friend ostream& operator<< (ostream& output_stream, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters & x); + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/include/Statistics.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/include/Statistics.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/include/Statistics.h (revision 45) @@ -0,0 +1,66 @@ +#ifdef STATISTICS +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Statistics_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Statistics_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" +// Internal structure +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h" +#include "Behavioural/include/Statistics.h" +#include "Behavioural/include/Parameters_Statistics.h" +//#include "Behavioural/Generic/Group/include/Statistics.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h" + +//using namespace morpheo::behavioural::generic::group; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + class Statistics : public morpheo::behavioural::Statistics + { + // -----[ fields ]---------------------------------------------------- + private : const Parameters _parameters; + + // -----[ methods ]--------------------------------------------------- + public : Statistics (string name , + morpheo::behavioural::Parameters_Statistics parameters_statistics , + Parameters parameters + ); +//public : Statistics (Statistics & stat); + public : ~Statistics () ; + + public : string print_body (uint32_t depth); + public : string print (uint32_t depth); + public : string print (uint32_t depth, + string component_stat + ); + public : void add (); + + public : friend ostream& operator<< (ostream& output_stream, + const Statistics & x); + + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h (revision 45) @@ -0,0 +1,153 @@ +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Two_Level_Branch_Predictor_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Two_Level_Branch_Predictor_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +// Internal structure +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h" + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Statistics.h" +#endif +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Component.h" + +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + class Two_Level_Branch_Predictor +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const string _name; + + protected : const Parameters _param; +#ifdef STATISTICS + protected : const morpheo::behavioural::Parameters_Statistics _param_statistics; +#endif + +#ifdef STATISTICS + private : Statistics * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // Interface + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + // Interface Predict + public : SC_IN (Tcontrol_t) ** in_PREDICT_VAL ; + public : SC_OUT(Tcontrol_t) ** out_PREDICT_ACK ; + public : SC_IN (Taddress_t) ** in_PREDICT_ADDRESS ; + public : SC_OUT(Tbht_history_t) ** out_PREDICT_BHT_HISTORY ; + public : SC_OUT(Tpht_history_t) ** out_PREDICT_PHT_HISTORY ; + + // Interface Branch_complete + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_VAL ; + public : SC_OUT(Tcontrol_t) ** out_BRANCH_COMPLETE_ACK ; + public : SC_IN (Taddress_t) ** in_BRANCH_COMPLETE_ADDRESS ; + public : SC_IN (Tbht_history_t) ** in_BRANCH_COMPLETE_BHT_HISTORY; + public : SC_IN (Tpht_history_t) ** in_BRANCH_COMPLETE_PHT_HISTORY; + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_DIRECTION ; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : SC_SIGNAL(Tcontrol_t) ** signal_PREDICT_BHT_ACK ; + private : SC_SIGNAL(Tcontrol_t) ** signal_PREDICT_PHT_ACK ; + private : SC_SIGNAL(Taddress_t) ** signal_PREDICT_BHT_ADDRESS ; + private : SC_SIGNAL(Taddress_t) ** signal_PREDICT_PHT_ADDRESS ; + + private : SC_SIGNAL(Tcontrol_t) ** signal_BRANCH_COMPLETE_BHT_ACK ; + private : SC_SIGNAL(Tcontrol_t) ** signal_BRANCH_COMPLETE_PHT_ACK ; + private : SC_SIGNAL(Taddress_t) ** signal_BRANCH_COMPLETE_BHT_ADDRESS; + private : SC_SIGNAL(Taddress_t) ** signal_BRANCH_COMPLETE_PHT_ADDRESS; +#endif + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + protected : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Branch_History_Table * component_Branch_History_Table; + protected : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Pattern_History_Table * component_Pattern_History_Table; + protected : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Two_Level_Branch_Predictor_Glue * component_Two_Level_Branch_Predictor_Glue; + + // -----[ methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Two_Level_Branch_Predictor); +#endif + public : Two_Level_Branch_Predictor ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics param_statistics, +#endif + Parameters param ); + + public : Two_Level_Branch_Predictor (Parameters param ); + public : ~Two_Level_Branch_Predictor (void); + +#ifdef SYSTEMC + private : void allocation (void); + private : void deallocation (void); + +#if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) + public : void transition (void); +#endif +#endif +#ifdef STATISTICS + public : string statistics (uint32_t depth); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif +#ifdef VHDL_TESTBENCH + private : void vhdl_testbench_transition (void); +#endif + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/include/Types.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/include/Types.h (revision 45) @@ -0,0 +1,33 @@ +#ifdef SYSTEMC +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Type_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Type_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + typedef uint32_t Taddress_t ; + typedef uint32_t Tbht_history_t; + typedef uint32_t Tpht_history_t; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo + +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Parameters.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Parameters.cpp (revision 45) @@ -0,0 +1,129 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + Parameters::Parameters (bool have_bht , + uint32_t bht_size_shifter , + uint32_t bht_nb_shifter , + bool have_pht , + uint32_t pht_size_counter , + uint32_t pht_nb_counter , + uint32_t pht_size_address_share, + uint32_t size_address , + uint32_t nb_prediction , + uint32_t nb_branch_complete ) : + _have_bht (have_bht ), + _bht_size_shifter ((_have_bht == true)?bht_size_shifter:0), + _bht_nb_shifter ((_have_bht == true)?bht_nb_shifter :0), + _have_pht (have_pht ), + _pht_size_counter ((_have_pht == true)?pht_size_counter:0), + _pht_nb_counter ((_have_pht == true)?pht_nb_counter :0), + _pht_size_address_share (((_have_bht and _have_pht) == true)?pht_size_address_share:0), + _size_address (size_address ), + _nb_prediction (nb_prediction ), + _nb_branch_complete (nb_branch_complete), + _bht_size_address (static_cast(ceil(log2(bht_nb_shifter)))), + _pht_size_address (static_cast(ceil(log2(pht_nb_counter)))) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"Parameters","Begin"); + + if (_have_bht) + _param_branch_history_table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Parameters (_bht_size_shifter , + _bht_nb_shifter , + _nb_prediction , + _nb_branch_complete); + if (_have_pht) + _param_pattern_history_table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters (_pht_size_counter , + _pht_nb_counter , + _nb_prediction , + _nb_branch_complete); + + + _param_two_level_branch_predictor_glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters (_have_bht , + _bht_size_shifter , + _bht_size_address , + _have_pht , + _pht_size_address , + _pht_size_address_share, + _size_address , + _nb_prediction , + _nb_branch_complete ); + + test(); + log_printf(FUNC,Two_Level_Branch_Predictor,"Parameters","End"); + }; + + Parameters::Parameters (Parameters & param) : + _have_bht (param._have_bht ), + _bht_size_shifter (param._bht_size_shifter ), + _bht_nb_shifter (param._bht_nb_shifter ), + _have_pht (param._have_pht ), + _pht_size_counter (param._pht_size_counter ), + _pht_nb_counter (param._pht_nb_counter ), + _pht_size_address_share (param._pht_size_address_share), + _size_address (param._size_address ), + _nb_prediction (param._nb_prediction ), + _nb_branch_complete (param._nb_branch_complete ), + _bht_size_address (param._bht_size_address ), + _pht_size_address (param._pht_size_address ) + + { + log_printf(FUNC,Two_Level_Branch_Predictor,"Parameters","Begin"); + + if (_have_bht) + _param_branch_history_table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Parameters (_bht_size_shifter , + _bht_nb_shifter , + _nb_prediction , + _nb_branch_complete); + if (_have_pht) + _param_pattern_history_table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters (_pht_size_counter , + _pht_nb_counter , + _nb_prediction , + _nb_branch_complete); + + _param_two_level_branch_predictor_glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters (_have_bht , + _bht_size_shifter , + _bht_size_address , + _have_pht , + _pht_size_address , + _pht_size_address_share, + _size_address , + _nb_prediction , + _nb_branch_complete ); + + test(); + log_printf(FUNC,Two_Level_Branch_Predictor,"Parameters","End"); + }; + + Parameters::~Parameters () + { + log_printf(FUNC,Two_Level_Branch_Predictor,"~Parameters","Begin"); + + if (_have_bht) + delete _param_branch_history_table; + if (_have_pht) + delete _param_pattern_history_table; + delete _param_two_level_branch_predictor_glue; + log_printf(FUNC,Two_Level_Branch_Predictor,"~Parameters","End"); + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Parameters_msg_error.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Parameters_msg_error.cpp (revision 45) @@ -0,0 +1,84 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Types.h" +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + string Parameters::msg_error(void) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"msg_error","Begin"); + + string msg = ""; + + if (is_positive (_nb_prediction) == false) + { + msg += " - nb_prediction must be > 0\n"; + msg += " * nb_prediction : " + toString(_nb_prediction) + "\n"; + } + + if (is_positive (_nb_branch_complete) == false) + { + msg += " - nb_branch_complete must be > 0\n"; + msg += " * nb_branch_complete : " + toString(_nb_branch_complete) + "\n"; + } + + if ((_have_bht or _have_pht) == false) + { + msg += " - you have no Branch History Table and no Pattern History Table. You need a less of a BHT or a PHT\n"; + msg += " * have_bht : " + toString(_have_bht) + "\n"; + msg += " * have_pht : " + toString(_have_pht) + "\n"; + } + + if ( _have_bht and (_size_address < _bht_size_address)) + { + msg += " - the address's size must to large to the number of shifter in the Branch History Table.\n"; + msg += " * size_address : " + toString(_size_address ) + "\n"; + msg += " * have_bht : " + toString(_have_bht ) + "\n"; + msg += " * bht_size_address : " + toString(_bht_size_address) + "\n"; + msg += " * bht_nb_shifter : " + toString(_bht_nb_shifter ) + "\n"; + } + + if (_have_pht and ( (_size_address < _pht_size_address) or + (_have_bht and (_pht_size_address < _bht_size_address)))) + { + msg += " - the address's size concate with shifter_out must to large to the number of counter in the Pattern History Table.\n"; + msg += " * size_address : " + toString(_size_address ) + "\n"; + msg += " * have_bht : " + toString(_have_bht ) + "\n"; + msg += " * bht_size_address : " + toString(_bht_size_address) + "\n"; + msg += " * bht_nb_shifter : " + toString(_bht_nb_shifter ) + "\n"; + msg += " * have_pht : " + toString(_have_bht ) + "\n"; + msg += " * pht_size_address : " + toString(_pht_size_address) + "\n"; + msg += " * pht_nb_counter : " + toString(_pht_nb_counter ) + "\n"; + } + +// if ( not _have_bht and (_pht_size_address_share != 0)) +// { +// msg += " - you have no Branch History Table but size_address_share is > 0\n"; +// msg += " * have_bht : " + toString(_have_bht ) + "\n"; +// msg += " * pht_size_address_share : " + toString(_pht_size_address_share) + "\n"; +// } + + return msg; + + log_printf(FUNC,Two_Level_Branch_Predictor,"msg_error","End"); + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Parameters_print.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Parameters_print.cpp (revision 45) @@ -0,0 +1,62 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h" +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + string Parameters::print (uint32_t depth) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"print","Begin"); + + string tab = string(depth,'\t'); + ostringstream msg; + msg << tab << "" << endl + << tab << "\t " << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t " << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t" << endl + << tab << "\t" << endl; + if (_have_bht) + msg << _param_branch_history_table ->print(depth+1); + if (_have_pht) + msg << _param_pattern_history_table->print(depth+1); + msg << _param_two_level_branch_predictor_glue->print(depth+1); + msg << tab << "" << endl; + + log_printf(FUNC,Two_Level_Branch_Predictor,"print","End"); + + return msg.str(); + }; + + ostream& operator<< (ostream& output_stream , + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters & x) + { + output_stream << x.print(0); + + return output_stream; + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Statistics.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Statistics.cpp (revision 45) @@ -0,0 +1,44 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Statistics.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + Statistics::Statistics (string name , + morpheo::behavioural::Parameters_Statistics parameters_statistics , + Parameters parameters + ) : + morpheo::behavioural::Statistics(name , + parameters_statistics ), + _parameters(parameters) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"Statistics","Begin"); + log_printf(FUNC,Two_Level_Branch_Predictor,"Statistics","End"); + }; + + Statistics::~Statistics () + { + log_printf(FUNC,Two_Level_Branch_Predictor,"~Statistics","Begin"); + log_printf(FUNC,Two_Level_Branch_Predictor,"~Statistics","End"); + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Statistics_add.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Statistics_add.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Statistics_add.cpp (revision 45) @@ -0,0 +1,35 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + void Statistics::add () + { + log_printf(FUNC,Two_Level_Branch_Predictor,"add","Begin"); + log_printf(FUNC,Two_Level_Branch_Predictor,"add","End"); + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Statistics_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Statistics_print.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Statistics_print.cpp (revision 45) @@ -0,0 +1,60 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + string Statistics::print (uint32_t depth, + string component_stat + ) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"print","Begin"); + + string tab = string(depth,'\t'); + ostringstream msg; + + msg << tab << "" << endl + << print_body(depth+1) + << component_stat + << tab << "" << endl; + + log_printf(FUNC,Two_Level_Branch_Predictor,"print","End"); + + return msg.str(); + }; + + string Statistics::print (uint32_t depth) + { + return print(depth,""); + }; + + ostream& operator<< (ostream& output_stream , + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Statistics & x) + { + output_stream << x.print(0); + + return output_stream; + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Statistics_print_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Statistics_print_body.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Statistics_print_body.cpp (revision 45) @@ -0,0 +1,43 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + string Statistics::print_body (uint32_t depth) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"print_body","Begin"); + + string tab = string(depth,'\t'); + ostringstream msg; + + msg << tab << ""; + + log_printf(FUNC,Two_Level_Branch_Predictor,"print_body","End"); + + return msg.str(); + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor.cpp (revision 45) @@ -0,0 +1,92 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + +#ifdef SYSTEMC + Two_Level_Branch_Predictor::Two_Level_Branch_Predictor (sc_module_name name, +#else + Two_Level_Branch_Predictor::Two_Level_Branch_Predictor (string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics param_statistics, +#endif + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters param ): + _name (name) + ,_param (param) +#ifdef STATISTICS + ,_param_statistics (param_statistics) +#endif + { + log_printf(FUNC,Two_Level_Branch_Predictor,"Two_Level_Branch_Predictor","Begin"); + +#ifdef SYSTEMC + allocation (); +#endif + +#ifdef STATISTICS + // Allocation of statistics + _stat = new Statistics (static_cast(_name), + param_statistics , + param); +#endif + +#ifdef VHDL + // generate the vhdl + vhdl(); +#endif + +#ifdef SYSTEMC +#if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) + SC_METHOD (transition); + dont_initialize (); + sensitive_pos << *(in_CLOCK); +#endif + +// SC_METHOD (genMoore); +// dont_initialize (); +// sensitive_neg << *(in_CLOCK); + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information +#endif + +#endif + log_printf(FUNC,Two_Level_Branch_Predictor,"Two_Level_Branch_Predictor","End"); + }; + + Two_Level_Branch_Predictor::~Two_Level_Branch_Predictor (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"~Two_Level_Branch_Predictor","Begin"); + +#ifdef STATISTICS + _stat->generate_file(statistics(0)); + + delete _stat; +#endif + +#ifdef SYSTEMC + deallocation (); +#endif + + log_printf(FUNC,Two_Level_Branch_Predictor,"~Two_Level_Branch_Predictor","End"); + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_allocation.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_allocation.cpp (revision 45) @@ -0,0 +1,303 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + void Two_Level_Branch_Predictor::allocation (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"allocation","Begin"); + + _component = new Component (); + + Entity * entity = _component->set_entity (_name + ,"Two_Level_Branch_Predictor" +#ifdef POSITION + ,MIXTE +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + , IN + , SOUTH + , "Generalist interface" +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1); + in_NRESET = interface->set_signal_in ("nreset",1,RESET_VHDL_YES); + } + + // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction ]; + out_PREDICT_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_prediction ]; + in_PREDICT_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_prediction ]; + if (_param._have_bht) + out_PREDICT_BHT_HISTORY = new SC_OUT(Tbht_history_t) * [_param._nb_prediction ]; + if (_param._have_pht) + out_PREDICT_PHT_HISTORY = new SC_OUT(Tpht_history_t) * [_param._nb_prediction ]; + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) +#ifdef POSITION + , IN + , WEST + , "Interface Predict" +#endif + ); + + in_PREDICT_VAL [i] = interface->set_signal_valack_in ("val" , VAL); + out_PREDICT_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); + in_PREDICT_ADDRESS [i] = interface->set_signal_in ("address", _param._size_address); + if (_param._have_bht) + out_PREDICT_BHT_HISTORY [i] = interface->set_signal_out ("bht_history", _param._bht_size_shifter); + if (_param._have_pht) + out_PREDICT_PHT_HISTORY [i] = interface->set_signal_out ("pht_history", _param._pht_size_counter); + } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; + out_BRANCH_COMPLETE_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_branch_complete]; + in_BRANCH_COMPLETE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_branch_complete]; + if (_param._have_bht) + in_BRANCH_COMPLETE_BHT_HISTORY = new SC_IN (Tbht_history_t) * [_param._nb_branch_complete]; + if (_param._have_pht) + in_BRANCH_COMPLETE_PHT_HISTORY = new SC_IN (Tpht_history_t) * [_param._nb_branch_complete]; + in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i) +#ifdef POSITION + , IN + , EAST + , "Interface branch complete" +#endif + ); + + in_BRANCH_COMPLETE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); + out_BRANCH_COMPLETE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); + in_BRANCH_COMPLETE_ADDRESS [i] = interface->set_signal_in ("address" , _param._size_address); + if (_param._have_bht) + in_BRANCH_COMPLETE_BHT_HISTORY [i] = interface->set_signal_in ("bht_history", _param._bht_size_shifter); + if (_param._have_pht) + in_BRANCH_COMPLETE_PHT_HISTORY [i] = interface->set_signal_in ("pht_history", _param._pht_size_counter); + in_BRANCH_COMPLETE_DIRECTION [i] = interface->set_signal_in ("direction" , 1); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + string name_component; + + // =====[ component_Branch_History_Table ]============================ + if (_param._have_bht) + { + name_component = _name+"_Branch_History_Table"; + + component_Branch_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Branch_History_Table (name_component.c_str() +#ifdef STATISTICS + ,_param_statistics +#endif + ,*(_param._param_branch_history_table)); + + _component->set_component (component_Branch_History_Table->_component +#ifdef POSITION + , 75 + , 25 + , 10 + , 10 +#endif + ); + } + + // =====[ component_Pattern_History_Table ]=========================== + if (_param._have_pht) + { + name_component = _name+"_Pattern_History_Table"; + + component_Pattern_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table ::Pattern_History_Table (name_component.c_str() +#ifdef STATISTICS + ,_param_statistics +#endif + ,*(_param._param_pattern_history_table)); + + _component->set_component (component_Pattern_History_Table->_component +#ifdef POSITION + , 75 + , 75 + , 10 + , 10 +#endif + ); + } + + // =====[ component_Two_Level_Branch_Predictor_Glue ]================= + + name_component = _name+"_Two_Level_Branch_Predictor_Glue"; + + component_Two_Level_Branch_Predictor_Glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Two_Level_Branch_Predictor_Glue (name_component.c_str() +#ifdef STATISTICS + ,_param_statistics +#endif + ,*(_param._param_two_level_branch_predictor_glue)); + + _component->set_component (component_Two_Level_Branch_Predictor_Glue->_component +#ifdef POSITION + , 50 + , 75 + , 10 + , 10 +#endif + ); + + // ~~~~~[ Component - Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // =====[ component_Branch_History_Table - Instanciation ]============ + if (_param._have_bht) + { +#ifdef POSITION + _component->interface_map (_name+"_Branch_History_Table","", + _name ,""); +#endif + + _component->port_map(_name+"_Branch_History_Table", "in_CLOCK" , _name,"in_CLOCK" ); + _component->port_map(_name+"_Branch_History_Table", "in_NRESET", _name,"in_NRESET"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { +#ifdef POSITION + _component->interface_map (_name+"_Branch_History_Table","predict_"+toString(i), + _name ,"predict_"+toString(i)); +#endif + _component->port_map(_name+"_Branch_History_Table", "in_PREDICT_"+toString(i)+"_VAL" , _name , "in_PREDICT_"+toString(i)+"_VAL" ); + _component->port_map(_name+"_Branch_History_Table","out_PREDICT_"+toString(i)+"_ACK" , _name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_BHT_ACK" ); + _component->port_map(_name+"_Branch_History_Table", "in_PREDICT_"+toString(i)+"_ADDRESS", _name+"_Two_Level_Branch_Predictor_Glue","out_PREDICT_"+toString(i)+"_BHT_ADDRESS"); + _component->port_map(_name+"_Branch_History_Table","out_PREDICT_"+toString(i)+"_HISTORY", _name ,"out_PREDICT_"+toString(i)+"_BHT_HISTORY"); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { +#ifdef POSITION + _component->interface_map (_name+"_Branch_History_Table","branch_complete_"+toString(i), + _name ,"branch_complete_"+toString(i)); +#endif + _component->port_map(_name+"_Branch_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); + _component->port_map(_name+"_Branch_History_Table","out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , _name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_ACK" ); + _component->port_map(_name+"_Branch_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , _name+"_Two_Level_Branch_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_BHT_ADDRESS" ); + _component->port_map(_name+"_Branch_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY" ); + _component->port_map(_name+"_Branch_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" ); + } + } + + // =====[ component_Pattern_History_Table - Instanciation ]=========== + if (_param._have_pht) + { +#ifdef POSITION + _component->interface_map (_name+"_Pattern_History_Table","", + _name ,""); +#endif + + _component->port_map(_name+"_Pattern_History_Table", "in_CLOCK" , _name,"in_CLOCK" ); + _component->port_map(_name+"_Pattern_History_Table", "in_NRESET", _name,"in_NRESET"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { +#ifdef POSITION + _component->interface_map (_name+"_Pattern_History_Table","predict_"+toString(i), + _name ,"predict_"+toString(i)); +#endif + _component->port_map(_name+"_Pattern_History_Table", "in_PREDICT_"+toString(i)+"_VAL" , _name , "in_PREDICT_"+toString(i)+"_VAL" ); + _component->port_map(_name+"_Pattern_History_Table","out_PREDICT_"+toString(i)+"_ACK" , _name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PHT_ACK" ); + _component->port_map(_name+"_Pattern_History_Table", "in_PREDICT_"+toString(i)+"_ADDRESS", _name+"_Two_Level_Branch_Predictor_Glue","out_PREDICT_"+toString(i)+"_PHT_ADDRESS"); + _component->port_map(_name+"_Pattern_History_Table","out_PREDICT_"+toString(i)+"_HISTORY", _name ,"out_PREDICT_"+toString(i)+"_PHT_HISTORY"); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { +#ifdef POSITION + _component->interface_map (_name+"_Pattern_History_Table","branch_complete_"+toString(i), + _name ,"branch_complete_"+toString(i)); +#endif + _component->port_map(_name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); + _component->port_map(_name+"_Pattern_History_Table","out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , _name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_ACK" ); + _component->port_map(_name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , _name+"_Two_Level_Branch_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS" ); + _component->port_map(_name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_HISTORY" ); + _component->port_map(_name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" ); + } + } + + // =====[ component_Two_Level_Branch_Predictor_Glue - Instanciation ]= +#ifdef POSITION + _component->interface_map (_name+"_Two_Level_Branch_Predictor_Glue","", + _name ,""); +#endif + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_CLOCK" , _name,"in_CLOCK" ); + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_NRESET", _name,"in_NRESET"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + if (_param._have_bht) + { + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_BHT_ACK" , _name+"_Branch_History_Table" , "out_PREDICT_"+toString(i)+"_ACK" ); + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "out_PREDICT_"+toString(i)+"_BHT_ADDRESS", _name+"_Branch_History_Table" , "in_PREDICT_"+toString(i)+"_ADDRESS"); + } + if (_param._have_pht) + { + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PHT_ACK" , _name+"_Pattern_History_Table", "out_PREDICT_"+toString(i)+"_ACK" ); + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "out_PREDICT_"+toString(i)+"_PHT_ADDRESS", _name+"_Pattern_History_Table", "in_PREDICT_"+toString(i)+"_ADDRESS"); + } + if (_param._have_bht and _param._have_pht) + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_BHT_HISTORY" , _name+"_Branch_History_Table" ,"out_PREDICT_"+toString(i)+"_HISTORY"); + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue","out_PREDICT_"+toString(i)+"_ACK" , _name ,"out_PREDICT_"+toString(i)+"_ACK"); + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_ADDRESS" , _name , "in_PREDICT_"+toString(i)+"_ADDRESS"); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + if (_param._have_bht) + { + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_ACK" , _name+"_Branch_History_Table" , "out_BRANCH_COMPLETE_"+toString(i)+"_ACK" ); + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "out_BRANCH_COMPLETE_"+toString(i)+"_BHT_ADDRESS", _name+"_Branch_History_Table" , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); + } + if (_param._have_pht) + { + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_ACK" , _name+"_Pattern_History_Table", "out_BRANCH_COMPLETE_"+toString(i)+"_ACK" ); + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS", _name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); + } + if (_param._have_bht and _param._have_pht) + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY"); + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , _name ,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK"); + _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); + } +#ifdef POSITION + _component->generate_file(); +#endif + + log_printf(FUNC,Two_Level_Branch_Predictor,"allocation","End"); + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_deallocation.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_deallocation.cpp (revision 45) @@ -0,0 +1,61 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + void Two_Level_Branch_Predictor::deallocation (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"deallocation","Begin"); + + delete in_CLOCK; + delete in_NRESET; + + delete [] in_PREDICT_VAL ; + delete [] out_PREDICT_ACK ; + delete [] in_PREDICT_ADDRESS ; + if (_param._have_bht) + delete [] out_PREDICT_BHT_HISTORY; + if (_param._have_pht) + delete [] out_PREDICT_PHT_HISTORY; + + delete [] in_BRANCH_COMPLETE_VAL ; + delete [] out_BRANCH_COMPLETE_ACK ; + delete [] in_BRANCH_COMPLETE_ADDRESS ; + if (_param._have_bht) + delete [] in_BRANCH_COMPLETE_BHT_HISTORY; + if (_param._have_pht) + delete [] in_BRANCH_COMPLETE_PHT_HISTORY; + delete [] in_BRANCH_COMPLETE_DIRECTION ; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + if (_param._have_bht) + delete component_Branch_History_Table ; + if (_param._have_pht) + delete component_Pattern_History_Table; + delete component_Two_Level_Branch_Predictor_Glue; + delete _component; + + log_printf(FUNC,Two_Level_Branch_Predictor,"deallocation","End"); + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_statistics.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_statistics.cpp (revision 45) @@ -0,0 +1,45 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h" + + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + string Two_Level_Branch_Predictor::statistics (uint32_t depth) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"statistics","Begin"); + + string stat_component_Branch_History_Table = (_param._have_bht==false)?"":component_Branch_History_Table ->statistics(depth+1); + string stat_component_Pattern_History_Table = (_param._have_pht==false)?"":component_Pattern_History_Table ->statistics(depth+1); + + string txt = _stat->print(depth, + stat_component_Branch_History_Table + + stat_component_Pattern_History_Table + + component_Two_Level_Branch_Predictor_Glue->statistics(depth+1) + ); + + log_printf(FUNC,Two_Level_Branch_Predictor,"statistics","End"); + + return txt; + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_transition.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_transition.cpp (revision 45) @@ -0,0 +1,43 @@ +#ifdef SYSTEMC +#if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + void Two_Level_Branch_Predictor::transition (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"transition","Begin"); + +#ifdef STATISTICS + _stat->add(); +#endif + +#ifdef VHDL_TESTBENCH + vhdl_testbench_transition (); +#endif + + log_printf(FUNC,Two_Level_Branch_Predictor,"transition","End"); + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl.cpp (revision 45) @@ -0,0 +1,47 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + void Two_Level_Branch_Predictor::vhdl (void) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl","Begin"); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port (vhdl); + _component ->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl","End"); + + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_body.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_body.cpp (revision 45) @@ -0,0 +1,34 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + void Two_Level_Branch_Predictor::vhdl_body (Vhdl * & vhdl) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_body","Begin"); + + + log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_body","End"); + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_declaration.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_declaration.cpp (revision 45) @@ -0,0 +1,33 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + void Two_Level_Branch_Predictor::vhdl_declaration (Vhdl * & vhdl) + { + log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_declaration","Begin"); + + log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_declaration","End"); + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_transition.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_transition.cpp (revision 45) @@ -0,0 +1,37 @@ +#ifdef VHDL_TESTBENCH +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { +namespace two_level_branch_predictor { + + + void Two_Level_Branch_Predictor::vhdl_testbench_transition () + { + log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_testbench_transition","Begin"); + +// sc_start(0); + + _interfaces->testbench(); + + log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_testbench_transition","End"); + }; + +}; // end namespace two_level_branch_predictor +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/VERSION =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/VERSION (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/VERSION (revision 45) @@ -0,0 +1,1 @@ +v0.4 Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/Makefile (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/Makefile (revision 45) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = .. +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/Meta_Predictor.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/Meta_Predictor.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/Meta_Predictor.tex (revision 45) @@ -0,0 +1,37 @@ +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/sty/header.sty (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/sty/header.sty (revision 45) @@ -0,0 +1,12 @@ +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Meta\_Predictor} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/01_introduction.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/01_introduction.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/02_features.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/02_features.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/03_description.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/03_description.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/04_pinout.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/04_pinout.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/05_parameters.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/05_parameters.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/06_performance.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/06_performance.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/07_details.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/07_details.tex (revision 45) @@ -0,0 +1,1 @@ +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/08_history.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/08_history.tex (revision 45) @@ -0,0 +1,10 @@ +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/root.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/doc/tex/root.tex (revision 45) @@ -0,0 +1,8 @@ +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Meta_Predictor.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Meta_Predictor.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Meta_Predictor.h (revision 45) @@ -0,0 +1,169 @@ +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_Meta_Predictor_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_Meta_Predictor_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +// Internal structure +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Statistics.h" +#endif +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Component.h" + +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + class Meta_Predictor +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const string _name; + + protected : const Parameters _param; +#ifdef STATISTICS + protected : const morpheo::behavioural::Parameters_Statistics _param_statistics; +#endif + +#ifdef STATISTICS + private : Statistics * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // Interface + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // Interface Predict + public : SC_IN (Tcontrol_t) ** in_PREDICT_VAL ; + public : SC_OUT(Tcontrol_t) ** out_PREDICT_ACK ; + public : SC_IN (Taddress_t) ** in_PREDICT_ADDRESS ; + public : SC_OUT(Thistory_t) ** out_PREDICT_HISTORY ; + public : SC_OUT(Tcontrol_t) ** out_PREDICT_DIRECTION ; + + // Interface Branch_complete + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_VAL ; + public : SC_OUT(Tcontrol_t) ** out_BRANCH_COMPLETE_ACK ; + public : SC_IN (Taddress_t) ** in_BRANCH_COMPLETE_ADDRESS ; + public : SC_IN (Thistory_t) ** in_BRANCH_COMPLETE_HISTORY ; + public : SC_IN (Tcontrol_t) ** in_BRANCH_COMPLETE_DIRECTION ; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Two_Level_Branch_Predictor * component_Two_Level_Branch_Predictor_0; + public : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Two_Level_Branch_Predictor * component_Two_Level_Branch_Predictor_1; + public : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Two_Level_Branch_Predictor * component_Two_Level_Branch_Predictor_2; + public : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::meta_predictor_glue::Meta_Predictor_Glue * component_Meta_Predictor_Glue ; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // Interface Predict + private : SC_SIGNAL(Tcontrol_t) ** signal_PREDICT_PREDICTOR_0_ACK ; + private : SC_SIGNAL(Tcontrol_t) ** signal_PREDICT_PREDICTOR_1_ACK ; + private : SC_SIGNAL(Tcontrol_t) ** signal_PREDICT_PREDICTOR_2_ACK ; + + private : SC_SIGNAL(morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Tbht_history_t) ** signal_PREDICT_PREDICTOR_0_BHT_HISTORY; + private : SC_SIGNAL(morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Tpht_history_t) ** signal_PREDICT_PREDICTOR_0_PHT_HISTORY; + private : SC_SIGNAL(morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Tbht_history_t) ** signal_PREDICT_PREDICTOR_1_BHT_HISTORY; + private : SC_SIGNAL(morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Tpht_history_t) ** signal_PREDICT_PREDICTOR_1_PHT_HISTORY; + private : SC_SIGNAL(morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Tbht_history_t) ** signal_PREDICT_PREDICTOR_2_BHT_HISTORY; + private : SC_SIGNAL(morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Tpht_history_t) ** signal_PREDICT_PREDICTOR_2_PHT_HISTORY; + + + private : SC_SIGNAL(Tcontrol_t) ** signal_BRANCH_COMPLETE_PREDICTOR_0_ACK ; + private : SC_SIGNAL(Tcontrol_t) ** signal_BRANCH_COMPLETE_PREDICTOR_1_ACK ; + private : SC_SIGNAL(Tcontrol_t) ** signal_BRANCH_COMPLETE_PREDICTOR_2_VAL ; + private : SC_SIGNAL(Tcontrol_t) ** signal_BRANCH_COMPLETE_PREDICTOR_2_ACK ; + private : SC_SIGNAL(Tcontrol_t) ** signal_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION; + + private : SC_SIGNAL(morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Tbht_history_t) ** signal_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY; + private : SC_SIGNAL(morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Tpht_history_t) ** signal_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY; + private : SC_SIGNAL(morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Tbht_history_t) ** signal_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY; + private : SC_SIGNAL(morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Tpht_history_t) ** signal_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY; + private : SC_SIGNAL(morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Tbht_history_t) ** signal_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY; + private : SC_SIGNAL(morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Tpht_history_t) ** signal_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY; + +#endif + + // -----[ methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Meta_Predictor); +#endif + public : Meta_Predictor ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics param_statistics, +#endif + Parameters param ); + + public : Meta_Predictor (Parameters param ); + public : ~Meta_Predictor (void); + +#ifdef SYSTEMC + private : void allocation (void); + private : void deallocation (void); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + public : void transition (void); +#endif +#endif +#ifdef STATISTICS + public : string statistics (uint32_t depth); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif +#ifdef VHDL_TESTBENCH + private : void vhdl_testbench_transition (void); +#endif + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Parameters.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Parameters.h (revision 45) @@ -0,0 +1,109 @@ +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_Parameters_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" +#include "Behavioural/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : const bool _have_meta_predictor ; + + public : const bool _predictor_0_have_bht ; + public : const uint32_t _predictor_0_bht_size_shifter ; + public : const uint32_t _predictor_0_bht_nb_shifter ; + public : const bool _predictor_0_have_pht ; + public : const uint32_t _predictor_0_pht_size_counter ; + public : const uint32_t _predictor_0_pht_nb_counter ; + public : const uint32_t _predictor_0_pht_size_address_share; + + public : const bool _predictor_1_have_bht ; + public : const uint32_t _predictor_1_bht_size_shifter ; + public : const uint32_t _predictor_1_bht_nb_shifter ; + public : const bool _predictor_1_have_pht ; + public : const uint32_t _predictor_1_pht_size_counter ; + public : const uint32_t _predictor_1_pht_nb_counter ; + public : const uint32_t _predictor_1_pht_size_address_share; + + public : const bool _predictor_2_have_bht ; + public : const uint32_t _predictor_2_bht_size_shifter ; + public : const uint32_t _predictor_2_bht_nb_shifter ; + public : const bool _predictor_2_have_pht ; + public : const uint32_t _predictor_2_pht_size_counter ; + public : const uint32_t _predictor_2_pht_nb_counter ; + public : const uint32_t _predictor_2_pht_size_address_share; + + public : const uint32_t _size_address ; + public : const uint32_t _nb_prediction ; + public : const uint32_t _nb_branch_complete ; + + public : const uint32_t _size_history ; + + public : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters * _param_two_level_branch_predictor_0; + public : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters * _param_two_level_branch_predictor_1; + public : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters * _param_two_level_branch_predictor_2; + public : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::meta_predictor_glue::Parameters * _param_meta_predictor_glue; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (bool have_meta_predictor , + + bool predictor_0_have_bht , + uint32_t predictor_0_bht_size_shifter , + uint32_t predictor_0_bht_nb_shifter , + bool predictor_0_have_pht , + uint32_t predictor_0_pht_size_counter , + uint32_t predictor_0_pht_nb_counter , + uint32_t predictor_0_pht_size_address_share, + + bool predictor_1_have_bht , + uint32_t predictor_1_bht_size_shifter , + uint32_t predictor_1_bht_nb_shifter , + bool predictor_1_have_pht , + uint32_t predictor_1_pht_size_counter , + uint32_t predictor_1_pht_nb_counter , + uint32_t predictor_1_pht_size_address_share, + + bool predictor_2_have_bht , + uint32_t predictor_2_bht_size_shifter , + uint32_t predictor_2_bht_nb_shifter , + bool predictor_2_have_pht , + uint32_t predictor_2_pht_size_counter , + uint32_t predictor_2_pht_nb_counter , + uint32_t predictor_2_pht_size_address_share, + + uint32_t size_address , + uint32_t nb_prediction , + uint32_t nb_branch_complete ); + public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : string msg_error (void); + + public : string print (uint32_t depth); + public : friend ostream& operator<< (ostream& output_stream, + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::Parameters & x); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Statistics.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Statistics.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Statistics.h (revision 45) @@ -0,0 +1,58 @@ +#ifdef STATISTICS +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_Statistics_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_Statistics_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" +#include "Behavioural/include/Statistics.h" +#include "Behavioural/include/Parameters_Statistics.h" +//#include "Behavioural/Generic/Group/include/Statistics.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Parameters.h" + +//using namespace morpheo::behavioural::generic::group; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + class Statistics : public morpheo::behavioural::Statistics + { + // -----[ fields ]---------------------------------------------------- + private : const Parameters _parameters; + + // -----[ methods ]--------------------------------------------------- + public : Statistics (string name , + morpheo::behavioural::Parameters_Statistics parameters_statistics , + Parameters parameters + ); +//public : Statistics (Statistics & stat); + public : ~Statistics () ; + + public : string print_body (uint32_t depth); + public : string print (uint32_t depth); + public : string print (uint32_t depth, string component_stat); + public : void add (); + + public : friend ostream& operator<< (ostream& output_stream, + const Statistics & x); + + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Types.h (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Types.h (revision 45) @@ -0,0 +1,28 @@ +#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_Type_h +#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_Type_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + typedef uint32_t Taddress_t; + typedef uint32_t Thistory_t; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor.cpp (revision 45) @@ -0,0 +1,87 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + +#ifdef SYSTEMC + Meta_Predictor::Meta_Predictor (sc_module_name name, +#else + Meta_Predictor::Meta_Predictor (string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics param_statistics, +#endif + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::Parameters param ): + _name (name) + ,_param (param) +#ifdef STATISTICS + ,_param_statistics (param_statistics) +#endif + { + log_printf(FUNC,Meta_Predictor,"Meta_Predictor","Begin"); + +#ifdef SYSTEMC + allocation (); +#endif + +#ifdef STATISTICS + // Allocation of statistics + _stat = new Statistics (static_cast(_name), + param_statistics , + param); +#endif + +#ifdef VHDL + // generate the vhdl + vhdl(); +#endif + +#ifdef SYSTEMC +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + SC_METHOD (transition); + dont_initialize (); + sensitive_pos << *(in_CLOCK); +#endif + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information +#endif + +#endif + log_printf(FUNC,Meta_Predictor,"Meta_Predictor","End"); + }; + + Meta_Predictor::~Meta_Predictor (void) + { + log_printf(FUNC,Meta_Predictor,"~Meta_Predictor","Begin"); + +#ifdef STATISTICS + _stat->generate_file(statistics(0)); + + delete _stat; +#endif + +#ifdef SYSTEMC + deallocation (); +#endif + + log_printf(FUNC,Meta_Predictor,"~Meta_Predictor","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_allocation.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_allocation.cpp (revision 45) @@ -0,0 +1,437 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + void Meta_Predictor::allocation (void) + { + log_printf(FUNC,Meta_Predictor,"allocation","Begin"); + + _component = new Component (); + + Entity * entity = _component->set_entity (_name + ,"Meta_Predictor" +#ifdef POSITION + ,MIXTE +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + , IN + , SOUTH + , "Generalist interface" +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1); + in_NRESET = interface->set_signal_in ("nreset",1,RESET_VHDL_YES); + } + + // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction ]; + out_PREDICT_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_prediction ]; + in_PREDICT_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_prediction ]; + out_PREDICT_HISTORY = new SC_OUT(Thistory_t) * [_param._nb_prediction ]; + out_PREDICT_DIRECTION = new SC_OUT(Tcontrol_t) * [_param._nb_prediction ]; + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) +#ifdef POSITION + , IN + , WEST + , "Interface Predict" +#endif + ); + + in_PREDICT_VAL [i] = interface->set_signal_valack_in ("val" , VAL); + out_PREDICT_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); + in_PREDICT_ADDRESS [i] = interface->set_signal_in ("address" , _param._size_address); + out_PREDICT_HISTORY [i] = interface->set_signal_out ("history" , _param._size_history); + out_PREDICT_DIRECTION [i] = interface->set_signal_out ("direction", 1); + } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; + out_BRANCH_COMPLETE_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_branch_complete]; + in_BRANCH_COMPLETE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_branch_complete]; + in_BRANCH_COMPLETE_HISTORY = new SC_IN (Thistory_t) * [_param._nb_branch_complete]; + in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i) +#ifdef POSITION + , IN + , EAST + , "Interface branch complete" +#endif + ); + + in_BRANCH_COMPLETE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); + out_BRANCH_COMPLETE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); + in_BRANCH_COMPLETE_ADDRESS [i] = interface->set_signal_in ("address" , _param._size_address); + in_BRANCH_COMPLETE_HISTORY [i] = interface->set_signal_in ("history" , _param._size_history); + in_BRANCH_COMPLETE_DIRECTION [i] = interface->set_signal_in ("direction" , 1); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + string name_component; + + // =====[ component_Meta_Predictor_Glue ]============================= + + name_component = _name+"_Meta_Predictor_Glue"; + + log_printf(INFO,Meta_Predictor,"allocation","Allocation : %s",name_component.c_str()); + + component_Meta_Predictor_Glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::meta_predictor_glue::Meta_Predictor_Glue (name_component.c_str() , +#ifdef STATISTICS + _param_statistics , +#endif + *(_param._param_meta_predictor_glue)); + + + _component->set_component (component_Meta_Predictor_Glue->_component +#ifdef POSITION + , 75 + , 25 + , 10 + , 10 +#endif + ); + + + // =====[ component_Two_Level_Branch_Predictor_2 ]==================== + + name_component = _name+"_Two_Level_Branch_Predictor_2"; + + log_printf(INFO,Meta_Predictor,"allocation","Allocation : %s",name_component.c_str()); + + component_Two_Level_Branch_Predictor_2 = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor ::Two_Level_Branch_Predictor (name_component.c_str() , +#ifdef STATISTICS + _param_statistics , +#endif + *(_param._param_two_level_branch_predictor_2)); + + + _component->set_component (component_Two_Level_Branch_Predictor_2->_component +#ifdef POSITION + , 75 + , 25 + , 10 + , 10 +#endif + ); + + + + if (_param._have_meta_predictor) + { + // =====[ component_Two_Level_Branch_Predictor_1 ]==================== + + name_component = _name+"_Two_Level_Branch_Predictor_1"; + + log_printf(INFO,Meta_Predictor,"allocation","Allocation : %s",name_component.c_str()); + + component_Two_Level_Branch_Predictor_1 = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor ::Two_Level_Branch_Predictor (name_component.c_str() , +#ifdef STATISTICS + _param_statistics , +#endif + *(_param._param_two_level_branch_predictor_1)); + + _component->set_component (component_Two_Level_Branch_Predictor_1->_component +#ifdef POSITION + , 75 + , 25 + , 10 + , 10 +#endif + ); + + // =====[ component_Two_Level_Branch_Predictor_0 ]==================== + + name_component = _name+"_Two_Level_Branch_Predictor_0"; + + log_printf(INFO,Meta_Predictor,"allocation","Allocation : %s",name_component.c_str()); + + component_Two_Level_Branch_Predictor_0 = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor ::Two_Level_Branch_Predictor (name_component.c_str() , +#ifdef STATISTICS + _param_statistics , +#endif + *(_param._param_two_level_branch_predictor_0)); + + _component->set_component (component_Two_Level_Branch_Predictor_0->_component +#ifdef POSITION + , 75 + , 25 + , 10 + , 10 +#endif + ); + + } + + // ~~~~~[ Component - Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // =====[ component_Meta_Predictor_Glue - Instanciation ]============= + + name_component = _name+"_Meta_Predictor_Glue"; + + cout << "Instance : " << name_component << endl; + +#ifdef POSITION + _component->interface_map ("Meta_Predictor_Glue","", + _name ,""); +#endif + + _component->port_map(name_component, "in_CLOCK" , _name,"in_CLOCK" ); + _component->port_map(name_component, "in_NRESET", _name,"in_NRESET"); + + // Interface Predict + for (uint32_t i=0; i<_param._nb_prediction; i++) + { +#ifdef POSITION + _component->interface_map ("Meta_Predictor_Glue","predict_"+toString(i), + _name ,"predict_"+toString(i)); +#endif + + if (_param._have_meta_predictor) + { + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_PREDICTOR_0_ACK" , _name+"_Two_Level_Branch_Predictor_0" ,"out_PREDICT_"+toString(i)+"_ACK"); + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_PREDICTOR_1_ACK" , _name+"_Two_Level_Branch_Predictor_1" ,"out_PREDICT_"+toString(i)+"_ACK"); + } + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_PREDICTOR_2_ACK" , _name+"_Two_Level_Branch_Predictor_2" ,"out_PREDICT_"+toString(i)+"_ACK"); + _component->port_map(name_component, "out_PREDICT_"+toString(i)+"_ACK" , _name , "out_PREDICT_"+toString(i)+"_ACK"); + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_PREDICTOR_0_BHT_HISTORY", _name+"_Two_Level_Branch_Predictor_0" ,"out_PREDICT_"+toString(i)+"_BHT_HISTORY"); + if (_param._predictor_0_have_pht) + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_PREDICTOR_0_PHT_HISTORY", _name+"_Two_Level_Branch_Predictor_0" ,"out_PREDICT_"+toString(i)+"_PHT_HISTORY"); + if (_param._predictor_1_have_bht) + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_PREDICTOR_1_BHT_HISTORY", _name+"_Two_Level_Branch_Predictor_1" ,"out_PREDICT_"+toString(i)+"_BHT_HISTORY"); + if (_param._predictor_1_have_pht) + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_PREDICTOR_1_PHT_HISTORY", _name+"_Two_Level_Branch_Predictor_1" ,"out_PREDICT_"+toString(i)+"_PHT_HISTORY"); + } + if (_param._predictor_2_have_bht) + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_PREDICTOR_2_BHT_HISTORY", _name+"_Two_Level_Branch_Predictor_2" ,"out_PREDICT_"+toString(i)+"_BHT_HISTORY"); + if (_param._predictor_2_have_pht) + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_PREDICTOR_2_PHT_HISTORY", _name+"_Two_Level_Branch_Predictor_2" ,"out_PREDICT_"+toString(i)+"_PHT_HISTORY"); + _component->port_map(name_component, "out_PREDICT_"+toString(i)+"_HISTORY" , _name , "out_PREDICT_"+toString(i)+"_HISTORY"); + _component->port_map(name_component, "out_PREDICT_"+toString(i)+"_DIRECTION" , _name , "out_PREDICT_"+toString(i)+"_DIRECTION"); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { +#ifdef POSITION + _component->interface_map ("Meta_Predictor_Glue","branch_complete_"+toString(i), + _name ,"branch_complete_"+toString(i)); +#endif + + if (_param._have_meta_predictor) + { + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL"); + _component->port_map(name_component, "out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_VAL" , _name+"_Two_Level_Branch_Predictor_2", "in_BRANCH_COMPLETE_"+toString(i)+"_VAL"); + + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_0_ACK" , _name+"_Two_Level_Branch_Predictor_0", "out_BRANCH_COMPLETE_"+toString(i)+"_ACK"); + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_1_ACK" , _name+"_Two_Level_Branch_Predictor_1", "out_BRANCH_COMPLETE_"+toString(i)+"_ACK"); + } + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_ACK" , _name+"_Two_Level_Branch_Predictor_2", "out_BRANCH_COMPLETE_"+toString(i)+"_ACK"); + _component->port_map(name_component, "out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , _name ,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK"); + + if (_param._have_meta_predictor) + { + if (_param._predictor_0_have_bht) + _component->port_map(name_component, "out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_0_BHT_HISTORY" , _name+"_Two_Level_Branch_Predictor_0", "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY" ); + if (_param._predictor_0_have_pht) + _component->port_map(name_component, "out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_0_PHT_HISTORY" , _name+"_Two_Level_Branch_Predictor_0", "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_HISTORY" ); + if (_param._predictor_1_have_bht) + _component->port_map(name_component, "out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_1_BHT_HISTORY" , _name+"_Two_Level_Branch_Predictor_1", "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY" ); + if (_param._predictor_1_have_pht) + _component->port_map(name_component, "out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_1_PHT_HISTORY" , _name+"_Two_Level_Branch_Predictor_1", "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_HISTORY" ); + } + if (_param._predictor_2_have_bht) + _component->port_map(name_component, "out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_BHT_HISTORY" , _name+"_Two_Level_Branch_Predictor_2", "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY" ); + if (_param._predictor_2_have_pht) + _component->port_map(name_component, "out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_PHT_HISTORY" , _name+"_Two_Level_Branch_Predictor_2", "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_HISTORY" ); + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"); + if (_param._have_meta_predictor) + { + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION"); + _component->port_map(name_component, "out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_DIRECTION" , _name+"_Two_Level_Branch_Predictor_2" , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION"); + } + } + + // =====[ component_Two_Level_Branch_Predictor_2 - Instanciation ]==== + name_component = _name+"_Two_Level_Branch_Predictor_2"; + + cout << "Instance : " << name_component << endl; + +#ifdef POSITION + _component->interface_map ("Two_Level_Branch_Predictor_2","", + _name ,""); +#endif + + _component->port_map(name_component, "in_CLOCK" , _name,"in_CLOCK" ); + _component->port_map(name_component, "in_NRESET", _name,"in_NRESET"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { +#ifdef POSITION + _component->interface_map ("Two_Level_Branch_Predictor_2","predict_"+toString(i), + _name ,"predict_"+toString(i)); +#endif + + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_VAL" , _name, "in_PREDICT_"+toString(i)+"_VAL"); + _component->port_map(name_component,"out_PREDICT_"+toString(i)+"_ACK" , _name+"_Meta_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PREDICTOR_2_ACK"); + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_ADDRESS" , _name, "in_PREDICT_"+toString(i)+"_ADDRESS"); + if (_param._predictor_2_have_bht) + _component->port_map(name_component,"out_PREDICT_"+toString(i)+"_BHT_HISTORY" , _name+"_Meta_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PREDICTOR_2_BHT_HISTORY"); + if (_param._predictor_2_have_pht) + _component->port_map(name_component,"out_PREDICT_"+toString(i)+"_PHT_HISTORY" , _name+"_Meta_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PREDICTOR_2_PHT_HISTORY"); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { +#ifdef POSITION + _component->interface_map ("Two_Level_Branch_Predictor_2","branch_complete_"+toString(i), + _name ,"branch_complete_"+toString(i)); +#endif + if (_param._have_meta_predictor) + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" , _name+"_Meta_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_VAL" ); + else + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" , _name, "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); + _component->port_map(name_component,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , _name+"_Meta_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_ACK" ); + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , _name, "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" ); + if (_param._predictor_2_have_bht) + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY" , _name+"_Meta_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_BHT_HISTORY" ); + if (_param._predictor_2_have_pht) + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_HISTORY" , _name+"_Meta_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_PHT_HISTORY" ); + if (_param._have_meta_predictor) + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" , _name+"_Meta_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_2_DIRECTION" ); + else + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" , _name, "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" ); + } + + if (_param._have_meta_predictor) + { + // =====[ component_Two_Level_Branch_Predictor_1 - Instanciation ]==== + + name_component = _name+"_Two_Level_Branch_Predictor_1"; + + cout << "Instance : " << name_component << endl; + +#ifdef POSITION + _component->interface_map ("Two_Level_Branch_Predictor_1","", + _name ,""); +#endif + + _component->port_map(name_component, "in_CLOCK" , _name,"in_CLOCK" ); + _component->port_map(name_component, "in_NRESET", _name,"in_NRESET"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { +#ifdef POSITION + _component->interface_map ("Two_Level_Branch_Predictor_1","predict_"+toString(i), + _name ,"predict_"+toString(i)); +#endif + + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_VAL" , _name, "in_PREDICT_"+toString(i)+"_VAL"); + _component->port_map(name_component,"out_PREDICT_"+toString(i)+"_ACK" , _name+"_Meta_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PREDICTOR_1_ACK"); + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_ADDRESS" , _name, "in_PREDICT_"+toString(i)+"_ADDRESS"); + if (_param._predictor_1_have_bht) + _component->port_map(name_component,"out_PREDICT_"+toString(i)+"_BHT_HISTORY" , _name+"_Meta_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PREDICTOR_1_BHT_HISTORY"); + if (_param._predictor_1_have_pht) + _component->port_map(name_component,"out_PREDICT_"+toString(i)+"_PHT_HISTORY" , _name+"_Meta_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PREDICTOR_1_PHT_HISTORY"); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { +#ifdef POSITION + _component->interface_map ("Two_Level_Branch_Predictor_1","branch_complete_"+toString(i), + _name ,"branch_complete_"+toString(i)); +#endif + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" , _name, "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); + _component->port_map(name_component,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , _name+"_Meta_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_1_ACK" ); + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , _name, "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" ); + if (_param._predictor_1_have_bht) + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY" , _name+"_Meta_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_1_BHT_HISTORY" ); + if (_param._predictor_1_have_pht) + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_HISTORY" , _name+"_Meta_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_1_PHT_HISTORY" ); + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" , _name, "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" ); + } + // =====[ component_Two_Level_Branch_Predictor_0 - Instanciation ]==== + + name_component = _name+"_Two_Level_Branch_Predictor_0"; + + cout << "Instance : " << name_component << endl; + +#ifdef POSITION + _component->interface_map ("Two_Level_Branch_Predictor_0","", + _name ,""); +#endif + + _component->port_map(name_component, "in_CLOCK" , _name,"in_CLOCK" ); + _component->port_map(name_component, "in_NRESET", _name,"in_NRESET"); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { +#ifdef POSITION + _component->interface_map ("Two_Level_Branch_Predictor_0","predict_"+toString(i), + _name ,"predict_"+toString(i)); +#endif + + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_VAL" , _name, "in_PREDICT_"+toString(i)+"_VAL"); + _component->port_map(name_component,"out_PREDICT_"+toString(i)+"_ACK" , _name+"_Meta_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PREDICTOR_0_ACK"); + _component->port_map(name_component, "in_PREDICT_"+toString(i)+"_ADDRESS" , _name, "in_PREDICT_"+toString(i)+"_ADDRESS"); + if (_param._predictor_0_have_bht) + _component->port_map(name_component,"out_PREDICT_"+toString(i)+"_BHT_HISTORY" , _name+"_Meta_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PREDICTOR_0_BHT_HISTORY"); + if (_param._predictor_0_have_pht) + _component->port_map(name_component,"out_PREDICT_"+toString(i)+"_PHT_HISTORY" , _name+"_Meta_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PREDICTOR_0_PHT_HISTORY"); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { +#ifdef POSITION + _component->interface_map ("Two_Level_Branch_Predictor_0","branch_complete_"+toString(i), + _name ,"branch_complete_"+toString(i)); +#endif + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" , _name, "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); + _component->port_map(name_component,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , _name+"_Meta_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_0_ACK" ); + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , _name, "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" ); + if (_param._predictor_0_have_bht) + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY" , _name+"_Meta_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_0_BHT_HISTORY" ); + if (_param._predictor_0_have_pht) + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_HISTORY" , _name+"_Meta_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTOR_0_PHT_HISTORY" ); + _component->port_map(name_component, "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" , _name, "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" ); + } + } + + log_printf(FUNC,Meta_Predictor,"allocation","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_deallocation.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_deallocation.cpp (revision 45) @@ -0,0 +1,56 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + void Meta_Predictor::deallocation (void) + { + log_printf(FUNC,Meta_Predictor,"deallocation","Begin"); + + delete in_CLOCK; + delete in_NRESET; + + delete [] in_PREDICT_VAL ; + delete [] out_PREDICT_ACK ; + delete [] in_PREDICT_ADDRESS ; + delete [] out_PREDICT_HISTORY ; + delete [] out_PREDICT_DIRECTION ; + + delete [] in_BRANCH_COMPLETE_VAL ; + delete [] out_BRANCH_COMPLETE_ACK ; + delete [] in_BRANCH_COMPLETE_ADDRESS ; + delete [] in_BRANCH_COMPLETE_HISTORY ; + delete [] in_BRANCH_COMPLETE_DIRECTION ; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + if (_param._have_meta_predictor) + { + delete component_Two_Level_Branch_Predictor_0; + delete component_Two_Level_Branch_Predictor_1; + } + delete component_Two_Level_Branch_Predictor_2; + delete component_Meta_Predictor_Glue ; + delete _component; + + log_printf(FUNC,Meta_Predictor,"deallocation","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_statistics.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_statistics.cpp (revision 45) @@ -0,0 +1,44 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + string Meta_Predictor::statistics (uint32_t depth) + { + log_printf(FUNC,Meta_Predictor,"statistics","Begin"); + + string stat_component_Two_Level_Branch_Predictor_0 = (_param._have_meta_predictor==false)?"":component_Two_Level_Branch_Predictor_0->statistics(depth+1); + string stat_component_Two_Level_Branch_Predictor_1 = (_param._have_meta_predictor==false)?"":component_Two_Level_Branch_Predictor_1->statistics(depth+1); + string stat_component_Two_Level_Branch_Predictor_2 = component_Two_Level_Branch_Predictor_2->statistics(depth+1); + string stat_component_Meta_Predictor_Glue = component_Meta_Predictor_Glue ->statistics(depth+1); + + string txt = _stat->print(depth, + stat_component_Two_Level_Branch_Predictor_0 + + stat_component_Two_Level_Branch_Predictor_1 + + stat_component_Two_Level_Branch_Predictor_2 + + stat_component_Meta_Predictor_Glue ); + + log_printf(FUNC,Meta_Predictor,"statistics","End"); + + return txt; + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_transition.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_transition.cpp (revision 45) @@ -0,0 +1,41 @@ +#ifdef SYSTEMC +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + void Meta_Predictor::transition (void) + { + log_printf(FUNC,Meta_Predictor,"transition","Begin"); + +#ifdef STATISTICS + _stat->add(); +#endif + +#ifdef VHDL_TESTBENCH + vhdl_testbench_transition (); +#endif + + log_printf(FUNC,Meta_Predictor,"transition","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl.cpp (revision 45) @@ -0,0 +1,45 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + void Meta_Predictor::vhdl (void) + { + log_printf(FUNC,Meta_Predictor,"vhdl","Begin"); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port (vhdl); + _component ->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_printf(FUNC,Meta_Predictor,"vhdl","End"); + + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_body.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_body.cpp (revision 45) @@ -0,0 +1,31 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + void Meta_Predictor::vhdl_body (Vhdl * & vhdl) + { + log_printf(FUNC,Meta_Predictor,"vhdl_body","Begin"); + + log_printf(FUNC,Meta_Predictor,"vhdl_body","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_declaration.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_declaration.cpp (revision 45) @@ -0,0 +1,31 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + void Meta_Predictor::vhdl_declaration (Vhdl * & vhdl) + { + log_printf(FUNC,Meta_Predictor,"vhdl_declaration","Begin"); + + log_printf(FUNC,Meta_Predictor,"vhdl_declaration","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_port.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_port.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_port.cpp (revision 45) @@ -0,0 +1,52 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + void Meta_Predictor::vhdl_port (Vhdl & vhdl) + { + log_printf(FUNC,Meta_Predictor,"vhdl_port","Begin"); + + vhdl.set_port (" in_CLOCK ", IN, 1); + vhdl.set_port (" in_NRESET", IN, 1); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + vhdl.set_port (" in_PREDICT_VAL_"+toString(i)+" ", IN, 1); + vhdl.set_port ("out_PREDICT_ACK_"+toString(i)+" ",OUT, 1); + vhdl.set_port (" in_PREDICT_ADDRESS_"+toString(i)+" ", IN,_param._size_address); + vhdl.set_port ("out_PREDICT_HISTORY_"+toString(i)+" ",OUT,_param._size_history); + vhdl.set_port ("out_PREDICT_DIRECTION_"+toString(i)+" ",OUT,1); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + vhdl.set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", IN, 1); + vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" ",OUT, 1); + vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+" ", IN,_param._size_address); + vhdl.set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+" ", IN,_param._size_history); + vhdl.set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+" ", IN, 1); + } + + log_printf(FUNC,Meta_Predictor,"vhdl_port","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_testbench_label.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_testbench_label.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_testbench_label.cpp (revision 45) @@ -0,0 +1,33 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + void Meta_Predictor::vhdl_testbench_label (string label) + { + log_printf(FUNC,Meta_Predictor,"vhdl_testbench_label","Begin"); + +#ifdef VHDL_TESTBENCH + _vhdl_testbench->add_label(label); +#endif + + log_printf(FUNC,Meta_Predictor,"vhdl_testbench_label","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_testbench_port.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_testbench_port.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_testbench_port.cpp (revision 45) @@ -0,0 +1,51 @@ +#ifdef VHDL_TESTBENCH +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + void Meta_Predictor::vhdl_testbench_port () + { + log_printf(FUNC,Meta_Predictor,"vhdl_testbench_port","Begin"); + + _vhdl_testbench->set_port (" in_NRESET", IN, 1); + + for (uint32_t i=0; i<_param._nb_prediction; i++) + { + _vhdl_testbench->set_port (" in_PREDICT_VAL_"+toString(i)+" ", IN, 1); + _vhdl_testbench->set_port ("out_PREDICT_ACK_"+toString(i)+" ",OUT, 1); + _vhdl_testbench->set_port (" in_PREDICT_ADDRESS_"+toString(i)+" ", IN,_param._size_address); + _vhdl_testbench->set_port ("out_PREDICT_HISTORY_"+toString(i)+" ",OUT,_param._size_history); + _vhdl_testbench->set_port ("out_PREDICT_DIRECTION_"+toString(i)+" ",OUT,1); + } + + for (uint32_t i=0; i<_param._nb_branch_complete; i++) + { + _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", IN, 1); + _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" ",OUT, 1); + _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+" ", IN,_param._size_address); + _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+" ", IN,_param._size_history); + _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+" ", IN, 1); + } + + log_printf(FUNC,Meta_Predictor,"vhdl_testbench_port","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_testbench_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_testbench_transition.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Meta_Predictor_vhdl_testbench_transition.cpp (revision 45) @@ -0,0 +1,35 @@ +#ifdef VHDL_TESTBENCH +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + void Meta_Predictor::vhdl_testbench_transition () + { + log_printf(FUNC,Meta_Predictor,"vhdl_testbench_transition","Begin"); + +// sc_start(0); + + _interfaces->testbench(); + + log_printf(FUNC,Meta_Predictor,"vhdl_testbench_transition","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters.cpp (revision 45) @@ -0,0 +1,251 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Parameters.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + Parameters::Parameters (bool have_meta_predictor , + + bool predictor_0_have_bht , + uint32_t predictor_0_bht_size_shifter , + uint32_t predictor_0_bht_nb_shifter , + bool predictor_0_have_pht , + uint32_t predictor_0_pht_size_counter , + uint32_t predictor_0_pht_nb_counter , + uint32_t predictor_0_pht_size_address_share, + + bool predictor_1_have_bht , + uint32_t predictor_1_bht_size_shifter , + uint32_t predictor_1_bht_nb_shifter , + bool predictor_1_have_pht , + uint32_t predictor_1_pht_size_counter , + uint32_t predictor_1_pht_nb_counter , + uint32_t predictor_1_pht_size_address_share, + + bool predictor_2_have_bht , + uint32_t predictor_2_bht_size_shifter , + uint32_t predictor_2_bht_nb_shifter , + bool predictor_2_have_pht , + uint32_t predictor_2_pht_size_counter , + uint32_t predictor_2_pht_nb_counter , + uint32_t predictor_2_pht_size_address_share, + + uint32_t size_address , + uint32_t nb_prediction , + uint32_t nb_branch_complete ): + _have_meta_predictor (have_meta_predictor ), + + _predictor_0_have_bht ((have_meta_predictor==false)?false:predictor_0_have_bht ), + _predictor_0_bht_size_shifter ((_predictor_0_have_bht==false)?0:predictor_0_bht_size_shifter ), + _predictor_0_bht_nb_shifter ((_predictor_0_have_bht==false)?0:predictor_0_bht_nb_shifter ), + _predictor_0_have_pht ((have_meta_predictor==false)?false:predictor_0_have_pht ), + _predictor_0_pht_size_counter ((_predictor_0_have_pht==false)?0:predictor_0_pht_size_counter ), + _predictor_0_pht_nb_counter ((_predictor_0_have_pht==false)?0:predictor_0_pht_nb_counter ), + _predictor_0_pht_size_address_share (predictor_0_pht_size_address_share), + + _predictor_1_have_bht ((have_meta_predictor==false)?false:predictor_1_have_bht ), + _predictor_1_bht_size_shifter ((_predictor_1_have_bht==false)?0:predictor_1_bht_size_shifter ), + _predictor_1_bht_nb_shifter ((_predictor_1_have_bht==false)?0:predictor_1_bht_nb_shifter ), + _predictor_1_have_pht ((have_meta_predictor==false)?false:predictor_1_have_pht ), + _predictor_1_pht_size_counter ((_predictor_1_have_pht==false)?0:predictor_1_pht_size_counter ), + _predictor_1_pht_nb_counter ((_predictor_1_have_pht==false)?0:predictor_1_pht_nb_counter ), + _predictor_1_pht_size_address_share (predictor_1_pht_size_address_share), + + _predictor_2_have_bht (predictor_2_have_bht ), + _predictor_2_bht_size_shifter ((_predictor_2_have_bht==false)?0:predictor_2_bht_size_shifter ), + _predictor_2_bht_nb_shifter ((_predictor_2_have_bht==false)?0:predictor_2_bht_nb_shifter ), + _predictor_2_have_pht (predictor_2_have_pht ), + _predictor_2_pht_size_counter ((_predictor_2_have_pht==false)?0:predictor_2_pht_size_counter ), + _predictor_2_pht_nb_counter ((_predictor_2_have_pht==false)?0:predictor_2_pht_nb_counter ), + _predictor_2_pht_size_address_share (predictor_2_pht_size_address_share), + + _size_address (size_address ), + _nb_prediction (nb_prediction ), + _nb_branch_complete (nb_branch_complete ), + + _size_history (_predictor_0_bht_size_shifter + _predictor_0_pht_size_counter + + _predictor_1_bht_size_shifter + _predictor_1_pht_size_counter + + _predictor_2_bht_size_shifter + _predictor_2_pht_size_counter ) + { + log_printf(FUNC,Meta_Predictor,"Parameters","Begin"); + + if (_have_meta_predictor) + { + _param_two_level_branch_predictor_0 = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters (_predictor_0_have_bht , + _predictor_0_bht_size_shifter , + _predictor_0_bht_nb_shifter , + _predictor_0_have_pht , + _predictor_0_pht_size_counter , + _predictor_0_pht_nb_counter , + _predictor_0_pht_size_address_share, + _size_address , + _nb_prediction , + _nb_branch_complete ); + + _param_two_level_branch_predictor_1 = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters (_predictor_1_have_bht , + _predictor_1_bht_size_shifter , + _predictor_1_bht_nb_shifter , + _predictor_1_have_pht , + _predictor_1_pht_size_counter , + _predictor_1_pht_nb_counter , + _predictor_1_pht_size_address_share, + _size_address , + _nb_prediction , + _nb_branch_complete ); + } + + _param_two_level_branch_predictor_2 = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters (_predictor_2_have_bht , + _predictor_2_bht_size_shifter , + _predictor_2_bht_nb_shifter , + _predictor_2_have_pht , + _predictor_2_pht_size_counter , + _predictor_2_pht_nb_counter , + _predictor_2_pht_size_address_share, + _size_address , + _nb_prediction , + _nb_branch_complete ); + + + _param_meta_predictor_glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::meta_predictor_glue::Parameters (_have_meta_predictor , + _predictor_0_have_bht , + _predictor_0_bht_size_shifter , + _predictor_0_have_pht , + _predictor_0_pht_size_counter , + _predictor_1_have_bht , + _predictor_1_bht_size_shifter , + _predictor_1_have_pht , + _predictor_1_pht_size_counter , + _predictor_2_have_bht , + _predictor_2_bht_size_shifter , + _predictor_2_have_pht , + _predictor_2_pht_size_counter , + _nb_prediction , + _nb_branch_complete ); + + test(); + + log_printf(FUNC,Meta_Predictor,"Parameters","End"); + }; + + Parameters::Parameters (Parameters & param): + _have_meta_predictor (param._have_meta_predictor ), + + _predictor_0_have_bht (param._predictor_0_have_bht ), + _predictor_0_bht_size_shifter (param._predictor_0_bht_size_shifter ), + _predictor_0_bht_nb_shifter (param._predictor_0_bht_nb_shifter ), + _predictor_0_have_pht (param._predictor_0_have_pht ), + _predictor_0_pht_size_counter (param._predictor_0_pht_size_counter ), + _predictor_0_pht_nb_counter (param._predictor_0_pht_nb_counter ), + _predictor_0_pht_size_address_share (param._predictor_0_pht_size_address_share), + + _predictor_1_have_bht (param._predictor_1_have_bht ), + _predictor_1_bht_size_shifter (param._predictor_1_bht_size_shifter ), + _predictor_1_bht_nb_shifter (param._predictor_1_bht_nb_shifter ), + _predictor_1_have_pht (param._predictor_1_have_pht ), + _predictor_1_pht_size_counter (param._predictor_1_pht_size_counter ), + _predictor_1_pht_nb_counter (param._predictor_1_pht_nb_counter ), + _predictor_1_pht_size_address_share (param._predictor_1_pht_size_address_share), + + _predictor_2_have_bht (param._predictor_2_have_bht ), + _predictor_2_bht_size_shifter (param._predictor_2_bht_size_shifter ), + _predictor_2_bht_nb_shifter (param._predictor_2_bht_nb_shifter ), + _predictor_2_have_pht (param._predictor_2_have_pht ), + _predictor_2_pht_size_counter (param._predictor_2_pht_size_counter ), + _predictor_2_pht_nb_counter (param._predictor_2_pht_nb_counter ), + _predictor_2_pht_size_address_share (param._predictor_2_pht_size_address_share), + + _size_address (param._size_address ), + _nb_prediction (param._nb_prediction ), + _nb_branch_complete (param._nb_branch_complete ), + + _size_history (param._size_history ) + { + log_printf(FUNC,Meta_Predictor,"Parameters","Begin"); + + + if (_have_meta_predictor) + { + _param_two_level_branch_predictor_0 = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters (_predictor_0_have_bht , + _predictor_0_bht_size_shifter , + _predictor_0_bht_nb_shifter , + _predictor_0_have_pht , + _predictor_0_pht_size_counter , + _predictor_0_pht_nb_counter , + _predictor_0_pht_size_address_share, + _size_address , + _nb_prediction , + _nb_branch_complete ); + + _param_two_level_branch_predictor_1 = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters (_predictor_1_have_bht , + _predictor_1_bht_size_shifter , + _predictor_1_bht_nb_shifter , + _predictor_1_have_pht , + _predictor_1_pht_size_counter , + _predictor_1_pht_nb_counter , + _predictor_1_pht_size_address_share, + _size_address , + _nb_prediction , + _nb_branch_complete ); + } + + _param_two_level_branch_predictor_2 = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters (_predictor_2_have_bht , + _predictor_2_bht_size_shifter , + _predictor_2_bht_nb_shifter , + _predictor_2_have_pht , + _predictor_2_pht_size_counter , + _predictor_2_pht_nb_counter , + _predictor_2_pht_size_address_share, + _size_address , + _nb_prediction , + _nb_branch_complete ); + + _param_meta_predictor_glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::meta_predictor_glue::Parameters (_have_meta_predictor , + _predictor_0_have_bht , + _predictor_0_bht_size_shifter , + _predictor_0_have_pht , + _predictor_0_pht_size_counter , + _predictor_1_have_bht , + _predictor_1_bht_size_shifter , + _predictor_1_have_pht , + _predictor_1_pht_size_counter , + _predictor_2_have_bht , + _predictor_2_bht_size_shifter , + _predictor_2_have_pht , + _predictor_2_pht_size_counter , + _nb_prediction , + _nb_branch_complete ); + + test(); + log_printf(FUNC,Meta_Predictor,"Parameters","End"); + }; + + Parameters::~Parameters () + { + log_printf(FUNC,Meta_Predictor,"~Parameters","Begin"); + + if (_have_meta_predictor) + { + delete _param_two_level_branch_predictor_0; + delete _param_two_level_branch_predictor_1; + } + delete _param_two_level_branch_predictor_2; + delete _param_meta_predictor_glue; + + log_printf(FUNC,Meta_Predictor,"~Parameters","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters_msg_error.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters_msg_error.cpp (revision 45) @@ -0,0 +1,49 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Parameters.h" +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Types.h" +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + string Parameters::msg_error(void) + { + log_printf(FUNC,Meta_Predictor,"msg_error","Begin"); + + string msg = ""; + + // note : size_shifter and size_counter is set at 0 if not need + if ((8*sizeof(Thistory_t)) < _size_history) + { + msg += " - type \"Thistory_t\" is too little to the total size of history (shifter's size and counter's size)\n"; + msg += " * predictor_0_bht_size_shifter : " + toString(_predictor_0_bht_size_shifter) + "\n"; + msg += " * predictor_0_pht_size_counter : " + toString(_predictor_0_pht_size_counter) + "\n"; + msg += " * predictor_1_bht_size_shifter : " + toString(_predictor_1_bht_size_shifter) + "\n"; + msg += " * predictor_1_pht_size_counter : " + toString(_predictor_1_pht_size_counter) + "\n"; + msg += " * predictor_2_bht_size_shifter : " + toString(_predictor_2_bht_size_shifter) + "\n"; + msg += " * predictor_2_pht_size_counter : " + toString(_predictor_2_pht_size_counter) + "\n"; + msg += " * Thistory_t (bits): " + toString(8*(sizeof(Thistory_t))) + "\n"; + } + + return msg; + + log_printf(FUNC,Meta_Predictor,"msg_error","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters_print.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters_print.cpp (revision 45) @@ -0,0 +1,145 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Parameters.h" +#include "Behavioural/include/XML.h" +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + string Parameters::print (uint32_t depth) + { + log_printf(FUNC,Meta_Predictor,"print","Begin"); + + uint32_t size_predictor_0 = _predictor_0_bht_size_shifter*_predictor_0_bht_nb_shifter+_predictor_0_pht_size_counter*_predictor_0_pht_nb_counter; + uint32_t size_predictor_1 = _predictor_1_bht_size_shifter*_predictor_1_bht_nb_shifter+_predictor_1_pht_size_counter*_predictor_1_pht_nb_counter; + uint32_t size_predictor_2 = _predictor_2_bht_size_shifter*_predictor_2_bht_nb_shifter+_predictor_2_pht_size_counter*_predictor_2_pht_nb_counter; + uint32_t size_predictor = size_predictor_0+size_predictor_1+size_predictor_2; + + XML xml ("meta_predictor"); + xml.balise_open("meta_predictor"); + + xml. text(""); + xml. comment("size predictor : "+toString(size_predictor )+" bits"); + xml. comment("size predictor_0 : "+toString(size_predictor_0)+" bits"); + xml. comment("size predictor_1 : "+toString(size_predictor_1)+" bits"); + xml. comment("size predictor_2 : "+toString(size_predictor_2)+" bits"); + xml. text(""); + + xml. singleton_begin("have_meta_predictor "); + xml. attribut("value",toString(_have_meta_predictor )); + xml. singleton_end(); + + xml. singleton_begin("predictor_0_have_bht "); + xml. attribut("value",toString(_predictor_0_have_bht )); + xml. singleton_end(); + xml. singleton_begin("predictor_0_bht_size_shifter "); + xml. attribut("value",toString(_predictor_0_bht_size_shifter )); + xml. singleton_end(); + xml. singleton_begin("predictor_0_bht_nb_shifter "); + xml. attribut("value",toString(_predictor_0_bht_nb_shifter )); + xml. singleton_end(); + xml. singleton_begin("predictor_0_have_pht "); + xml. attribut("value",toString(_predictor_0_have_pht )); + xml. singleton_end(); + xml. singleton_begin("predictor_0_pht_size_counter "); + xml. attribut("value",toString(_predictor_0_pht_size_counter )); + xml. singleton_end(); + xml. singleton_begin("predictor_0_pht_nb_counter "); + xml. attribut("value",toString(_predictor_0_pht_nb_counter )); + xml. singleton_end(); + xml. singleton_begin("predictor_0_pht_size_address_share"); + xml. attribut("value",toString(_predictor_0_pht_size_address_share)); + xml. singleton_end(); + + xml. singleton_begin("predictor_1_have_bht "); + xml. attribut("value",toString(_predictor_1_have_bht )); + xml. singleton_end(); + xml. singleton_begin("predictor_1_bht_size_shifter "); + xml. attribut("value",toString(_predictor_1_bht_size_shifter )); + xml. singleton_end(); + xml. singleton_begin("predictor_1_bht_nb_shifter "); + xml. attribut("value",toString(_predictor_1_bht_nb_shifter )); + xml. singleton_end(); + xml. singleton_begin("predictor_1_have_pht "); + xml. attribut("value",toString(_predictor_1_have_pht )); + xml. singleton_end(); + xml. singleton_begin("predictor_1_pht_size_counter "); + xml. attribut("value",toString(_predictor_1_pht_size_counter )); + xml. singleton_end(); + xml. singleton_begin("predictor_1_pht_nb_counter "); + xml. attribut("value",toString(_predictor_1_pht_nb_counter )); + xml. singleton_end(); + xml. singleton_begin("predictor_1_pht_size_address_share"); + xml. attribut("value",toString(_predictor_1_pht_size_address_share)); + xml. singleton_end(); + + xml. singleton_begin("predictor_2_have_bht "); + xml. attribut("value",toString(_predictor_2_have_bht )); + xml. singleton_end(); + xml. singleton_begin("predictor_2_bht_size_shifter "); + xml. attribut("value",toString(_predictor_2_bht_size_shifter )); + xml. singleton_end(); + xml. singleton_begin("predictor_2_bht_nb_shifter "); + xml. attribut("value",toString(_predictor_2_bht_nb_shifter )); + xml. singleton_end(); + xml. singleton_begin("predictor_2_have_pht "); + xml. attribut("value",toString(_predictor_2_have_pht )); + xml. singleton_end(); + xml. singleton_begin("predictor_2_pht_size_counter "); + xml. attribut("value",toString(_predictor_2_pht_size_counter )); + xml. singleton_end(); + xml. singleton_begin("predictor_2_pht_nb_counter "); + xml. attribut("value",toString(_predictor_2_pht_nb_counter )); + xml. singleton_end(); + xml. singleton_begin("predictor_2_pht_size_address_share"); + xml. attribut("value",toString(_predictor_2_pht_size_address_share)); + xml. singleton_end(); + + xml. singleton_begin("size_address "); + xml. attribut("value",toString(_size_address )); + xml. singleton_end(); + xml. singleton_begin("nb_prediction "); + xml. attribut("value",toString(_nb_prediction )); + xml. singleton_end(); + xml. singleton_begin("nb_branch_complete "); + xml. attribut("value",toString(_nb_branch_complete )); + xml. singleton_end(); + + if (_have_meta_predictor) + { + xml. text(_param_two_level_branch_predictor_0->print(depth+1)); + xml. text(_param_two_level_branch_predictor_1->print(depth+1)); + } + xml. text(_param_two_level_branch_predictor_2->print(depth+1)); + xml. text(_param_meta_predictor_glue ->print(depth+1)); + + xml.balise_close(); + + log_printf(FUNC,Meta_Predictor,"print","End"); + + return xml.get_body(depth); + }; + + ostream& operator<< (ostream& output_stream , + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::Parameters & x) + { + output_stream << x.print(0); + + return output_stream; + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Statistics.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Statistics.cpp (revision 45) @@ -0,0 +1,42 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Statistics.h" + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + Statistics::Statistics (string name , + morpheo::behavioural::Parameters_Statistics parameters_statistics , + Parameters parameters + ) : + morpheo::behavioural::Statistics(name , + parameters_statistics ), + _parameters(parameters) + { + log_printf(FUNC,Meta_Predictor,"Statistics","Begin"); + log_printf(FUNC,Meta_Predictor,"Statistics","End"); + }; + + Statistics::~Statistics () + { + log_printf(FUNC,Meta_Predictor,"~Statistics","Begin"); + log_printf(FUNC,Meta_Predictor,"~Statistics","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Statistics_add.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Statistics_add.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Statistics_add.cpp (revision 45) @@ -0,0 +1,33 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + void Statistics::add () + { + log_printf(FUNC,Meta_Predictor,"add","Begin"); + log_printf(FUNC,Meta_Predictor,"add","End"); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Statistics_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Statistics_print.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Statistics_print.cpp (revision 45) @@ -0,0 +1,58 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + string Statistics::print (uint32_t depth, + string component_stat) + { + log_printf(FUNC,Meta_Predictor,"print","Begin"); + + string tab = string(depth,'\t'); + ostringstream msg; + + msg << tab << "" << endl + << print_body(depth+1) << endl + << component_stat + << tab << "" << endl; + + log_printf(FUNC,Meta_Predictor,"print","End"); + + return msg.str(); + }; + + string Statistics::print (uint32_t depth) + { + return print(depth,""); + }; + + ostream& operator<< (ostream& output_stream , + morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::Statistics & x) + { + output_stream << x.print(0); + + return output_stream; + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Statistics_print_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Statistics_print_body.cpp (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Statistics_print_body.cpp (revision 45) @@ -0,0 +1,41 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Statistics.h" + +#include +using namespace std; + +namespace morpheo { +namespace behavioural { +namespace stage_1_ifetch { +namespace predictor { +namespace meta_predictor { + + + string Statistics::print_body (uint32_t depth) + { + log_printf(FUNC,Meta_Predictor,"print_body","Begin"); + + string tab = string(depth,'\t'); + ostringstream msg; + + msg << tab << ""; + + log_printf(FUNC,Meta_Predictor,"print_body","End"); + + return msg.str(); + }; + +}; // end namespace meta_predictor +}; // end namespace predictor +}; // end namespace stage_1_ifetch + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/01_introduction.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/01_introduction.tex (revision 45) @@ -0,0 +1,83 @@ +\Section{Introduction}\label{introduction} +\subSection{Motivations} +Les processeurs haute performance lancent plusieurs instructions, de manière non ordonnée, spéculativement et provenant de plusieurs contextes matériels. Le processeur va donc exécuter plusieurs flots d'instructions contenant des accès mémoires et qui ne sont pas forcéments utiles (car spéculatif). Pour ces raisons, un défaut de cache (MISS) doit éviter de bloquer le processeur. Le cache doit être non bloquant, c'est à dire qu'il doit pouvoir accepter de nouvelles requêtes venant du processeur pendant le traitement d'un défaut d'une requête précédente. + +\subSection{Constitution du document} +Le document axé accès en cinq parties : +\begin{itemize} +\item Section \ref{introduction} : la section actuelle présente le comportement que doit avoir le cache, ainsi que les paramètres retenus. +\item Section \ref{overview_partial} : dans un second temps, nous allons présenter une architecture qui satisfait les requêtes courantes (lectures / écritures, succès / échec) sur des adresses non conflictuelles. Cette première architecture est utilisable dans la majorité des cas. +\item Section \ref{problem} : dans cette section, nous allons analyser les problèmes arrivant lors d'accès à des adresses conflictuelles, et/ou dans un environnement multi contextes. Pour chaque problème, nous proposons plusieurs solutions et nous énumérons leurs avantages et inconvénients. +\item Section \ref{overview_full} : cette section est la synthèse des deux précédentes. Nous allons modifier l'architecture de départ afin d'introduire des solutions aux problèmes énumérés dans la section \ref{problem}. +\item Section \ref{optimisation} : cette dernière section présente quelques optimisations pouvant être apportées au modèle défini dans la section \ref{overview_full}. +\end{itemize} + +\subSection{Paramètres} +Dans cette sous section, nous allons définir les paramètres du cache ainsi que les paramètres de l'interface entre le cache et le processeur. + +Pour chaque paramètre, nous précisons : +\begin{enumerate} +\item Une courte description présentant le paramètre +\item Un nom qui sera utilisé dans la suite du document +\item Un intervale de valeurs que peut prendre le paramètre +\item Un pas qui indique la fonction à appliquer pour passer d'une valeur à l'autre. +\end{enumerate} + +\subsubSection{Paramètres interne du cache} + +\begin{center} + \begin{tabular}{|ll|ccc|} + \hline + Paramètres & & Min & Max & Pas \\ + \hline + Taille du mot & SIZE\_WORD & 32 bits & 64 bits & *2 \\ + Nombre de lignes par mot & NB\_WORD & 1 mot & 64 mots & *2 \\ + Nombre de lignes & NB\_LINE & 1 ligne & 1024 lignes & *2 \\ + Associativité & ASSOC & 1 banc de NB\_LINE lignes & 16 bancs de NB\_LINE/16 lignes & *2 \\ + Taille des files internes & SIZE\_QUEUE & 1 case & 64 cases & *2 \\ + Nombre de requêtes pendantes & MAX\_REQ & 2 requêtes & 64 requêtes & *2 \\ + \hline + \end{tabular} +\end{center} + +\printgraphonly{CACHE_parameters}{.8} + +La taille du cache est $NB\_LINE * NB\_WORD * SIZE\_WORD~bits$. + +\subsubSection{Paramètres de l'interface cache / processeur} + +\begin{center} + \begin{tabular}{|ll|ccc|} + \hline + Paramètres & & Min & Max & Pas \\ + \hline + Taille d'une donnée & SIZE\_DATA & 32 bits & 64 bits & *2 \\ + Taille de l'adresse & SIZE\_ADDR & 32 bits & 64 bits & *2 \\ + Taille de l'identifiant du propriétaire & SIZE\_TRDID & 0 bits & 4 bits & +1 \\ + Taille de l'identifiant de transaction & SIZE\_PKTID & 0 bits & 4 bits & +1 \\ + \hline + \end{tabular} +\end{center} + +\subSection{Comportement} +\begin{description} +\item[Hierarchie mémoire : ] La hierarchie mémoire consiste à placer plusieurs mémoires entre le processeur et la mémoire principale. Le niveau d'un cache représente sa localisation par rapport au processeur. Plus le niveau est bas, plus le cache est proche du processeur. Un défaut de cache demande l'envoye d'une requête vers le niveau suivant (le niveau supérieur). Ce cache est prévu pour être un cache de niveau 1 (communiquant directement avec le processeur) et est également le cache qui communique avec le bus système. +\item[Write through : ] L'ajout d'un cache dans un système va provoquer une duplication des données. Lorsque le processeur va effectuer une requête d'écriture, le cache à l'obligation de modifier également la mémoire. Soit il le fait à chaque écriture, soit il attend l'évincement de la ligne. Ce cache implémente la statégie des écritures simultanées (Write Through) : chaque donnée est à la fois écrite dans le bloc du cache et dans le bloc de la mémoire de niveau supérieur. Ce protocole provoque une augmentation du trafic sur le bus, mais rend le cache plus simple et permet une gestion de la cohérence mémoire plus simplement. +\item[Write no allocate : ] Nous avons vus précédement qu'à chaque écriture, le processeur va également provoquer une écriture au niveau mémoire suivant. Il y a également une mise à jour du cache si la ligne est présente. Mais en cas d'absence de la ligne, faut il la rappatrier dans le cache? Si oui, il s'agit d'une écriture alloué. Or ce cache fait des écritures non alloué (Write no allocate). C'est à dire que les échecs d'écriture n'affectent pas le cache, le bloc n'est modifié que dans le niveau mémoire supérieur. Ceci permet de limiter le traffic sur le bus et de ne pas évincer une ligne qui peut encore être utile au profint d'une ligne pouvant ne pas être utile (le processeur est une architecture load-store : quand le programme écrit une variable en mémoire c'est que la variable est en fin de vie). +\item[Cache associatif : ] Un cache peut stocker plusieurs lignes de cache. Mais où peut on stocker une ligne précise dans le cache? S'il n'y a qu'une place possible alors le cache est appellé {\it direct map}, si le ligne peut être stockée n'importe où dans le cache alors le cache est appellé {\it full associatif}. Entre ces deux extrêmes, il y a les caches {\it semi-associatif}. Le cache est alors découpé en N bancs contenant chacun un nombre de lignes identiques. Une ligne peut être placée dans n'importe quel banc, mais ne peut être stockée qu'à un seul endroit dans chaque banc. Selon cette définition, un cache {\it direct map} ne contient qu'un seul banc alors qu'un cache {\it full associatif} n'a qu'une seule ligne par banc. Le cache que nous spécifions est {\it semi-associatif} qui est un bon compromit entre la compléxité et la performance. +\item[Non bloquant : ] Il s'agit de la principal caractéristique de notre cache. Comme expliquer en introduction, le cache est partagé entre plusieurs contextes, et cache contexte execute leurs instructions de manières désordonnées et spéculative. Un défaut de cache ne doit pas bloquer le cache. +\item[Processeur avec consistance mémoires relachées : ] Du point de vue du programmeur, les accès mémoires doivent se faire dans l'ordre du programme et que chaque accès mémoire doivent être lancée après que toute les instructions précédents soient terminées. Ceci assure une consistance mémoire parfaite, mais la dégradation de performance est catastrophique. Pour cela les processeurs implémentes des modèles de consistances mémoires relachés. Dans notre cas, le cache doit gérer les problèmes de consistance mémoire. +\end{description} + +\subSection{Hypothèse de travail}\label{hypothese} + +Nous allons supposer que le cache sera connecté à un processeur superscalaire d'ordre 4, que le code exécuté contient 20\% d'instructions de lectures et 10 \% d'instructions d'écritures. Nous avons donc en moyenne 4*30\%=1.2 accès mémoire par cycle. +Si nous ciblons un cache ayant au minimum 90\% de réussites, nous obtenons alors les ratios suivants : +\begin{itemize} +\item 60 \% de lectures qui réussissent. +\item 30 \% d'écritures qui réussissent. +\item 6,6\% de lectures qui échouent. +\item 3,3\% d'écritures qui échouent. +\end{itemize} + +On va supposer qu'un aller retour entre le processeur et la mémoire principal à une latence de 30 cycles en moyennes. Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/02_overview_partial.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/02_overview_partial.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/02_overview_partial.tex (revision 45) @@ -0,0 +1,144 @@ +\Section{Vue d'ensemble du cache - Modèle simplifié}\label{overview_partial} + +\printgraphonly{CACHE_overview_basic}{.8} + +Dans un premier temps, nous allons montrer un modèle qui satisfait les cas de requêtes courantes : read hit, write hit, read miss et write miss, sur des adresses non conflictuelles. + +Afin de réaliser un cache non bloquant, nous avons séparé l'interface des requêtes (à gauche sur les schémas), de l'interface des réponses (à droite sur les schémas). Ces interfaces sont eux même décomposées en deux parties : ceux impliquant le processeur (en haut sur les schémas) et ceux impliquant le bus (en bas sur les schémas). Le cache est donc découpés en 4 sections différentes : +\begin{enumerate} +\item {\bf SECTION\_DCACHE\_REQ :} Les requêtes émisent par le processeur. +\item {\bf SECTION\_DCACHE\_RSP :} Les réponses à retourner au processeur. +\item {\bf SECTION\_VCI\_REQ :} Les requêtes à émettre au bus. +\item {\bf SECTION\_VCI\_RSP :} Les réponses retournées par le bus. +\end{enumerate} + +Chaque partie est controlée par un automate et la communication entre deux sections ce fait par l'intermédiaire de files d'attentes (de type FIFO). Les ressources partagées sont les bancs mémoires contennant les lignes de caches ainsi que les informations sur les requêtes en cours de traitements. + +Nous allons maintenant voir les différents blocs internes : +\begin{itemize} +\item Quatre automates : + \begin{description} + \item[FSM\_DCACHE\_REQ :] Cette automate gère la section {\bf SECTION\_DCACHE\_REQ}. Il gère l'écriture dans la QUEUE\_READ\_HIT, l'écriture dans la QUEUE\_REQ, l'allocation d'une entrée dans la RAM\_INFO et la lecture de RAM\_TAG et RAM\_DATA et enfin gère un porte d'écriture dans RAM\_DATA. + +Pour chaque requête venant du processeur, l'adresse est envoyée au bloc RAM\_TAG. Ce dernier indique si la ligne contenant l'adresse demandée est dans le cache et, dans le cas d'un cache non direct map, retourne le numéro de banc contenant l'adresse. Si la requête est une lecture, alors avec le numéro de banc et le numéro de ligne, le cache va lire dans RAM\_DATA la donnée désirée. + +Si la requête est une écriture qui fait un succès, alors la donnée est écrite dans le bloc RAM\_DATA. + +Quelque soit le type de la requête, si cette dernière est acceptée par la section {\bf SECTION\_DCACHE\_REQ}, nous allons allouer une entrée dans le bloc RAM\_INFO. Un identifiant sera retourné lors de l'allocation. Pendant l'allocation, nous allons également stocker dans le bloc RAM\_INFO toute les informations concernant la requête : type, adresse, donnée ... L'identifiant permettra d'accéder à ces informations dans les différentes sections du cache. + +L'automate ne peut plus accepter de requêtes si l'une des RAM est occupée ou si la file de destination est pleine (la file de destination dépends de la requête). + \item[FSM\_DCACHE\_RSP :] Cette automate gère la section {\bf SECTION\_DCACHE\_RSP}. Il gère la lecture du bloc QUEUE\_READ\_HIT, la lecture de QUEUE\_RSP, la désallocation d'une entrée dans la RAM\_INFO et la mise à jour des blocs RAM\_TAG et RAM\_DATA. + +La plupart des requêtes envoyées par le processeur, par l'intermédiaire de l'interface DCACHE\_REQ, ont besoin qu'une réponse soit retourné au processeur. Ceci se fait par l'intermédiaire de l'interface DCACHE\_RSP. Les réponses peuvent provenir de deux files d'attentes : soit QUEUE\_READ\_HIT dans le cas d'une lecture avec succès, soit ,pour tout les autres cas, QUEUE\_RSP. + +Les informations étant stockées dans le bloc RAM\_INFO, les files d'attente contiennent un identifiant permettant d'adresser ce bloc. Lors d'une transaction réponse avec le processeur, le bloc RAM\_INFO va désallouer l'entrée concernée par la réponse. + +Les requêtes provenant de la file QUEUE\_RSP vont modifier le cache : soit en écrivant une ligne complète (read - miss) soit en écrivant une donnée (write - miss). Les requêtes provenant de la file QUEUE\_READ\_HIT vont modifier le bit de validité contenant dans le bloc RAM\_TAG (par exemple : invalidate et flush). + +L'automate ne peut plus envoyer de réponses au processeur si l'une des RAM est occupée ou les files d'attente sont vides. + \item[FSM\_VCI\_REQ :] Cette automate gère la section {\bf SECTION\_VCI\_REQ}. Il contrôle la consommation d'une requête dans la file QUEUE\_REQ, la lecture de l'information de la requête dans le bloc RAM\_INFO et l'envoye des requêtes sur l'interface VCI\_REQ. + +Toutes les requêtes d'écriture (car politique {\it write through}) et les échecs de lectures transitent par cette section. Les requêtes d'écritures et les accès mémoires non cachés vont provoquer l'envoye d'un paquet requête sur le bus (la section {\bf SECTION\_VCI\_RSP} devra recevoir un paquet réponse). Une lecture cachée va provoquer l'envoye de (NB\_WORD * SIZE\_WORD) / SIZE\_WORD\_VCI paquets requêtes. (SIZE\_WORD\_VCI représente la largeur d'une donnée transitant sur VCI. De plus il faut que SIZE\_WORD soit multiple de SIZE\_WORD\_VCI) + +\printgraphonly{CACHE_bloc_COUNTER}{.8} + +Comme le montre le graphe \ref{CACHE_bloc_COUNTER}, l'adresse envoyée est la concaténation entre un compteur et l'adresse de la requête (plus précisement c'est le Tag et l'Index de l'adresse qui est nécessaire). +La consommation d'une entrée dans la file QUEUE\_REQ ce fait lorsque l'intégralité des paquets sont envoyés. + +L'automate ne peut plus envoyer de requête au bus VCI si la RAM\_INFO est occupée et/ou si la file d'attente QUEUE\_REQ est vide. + \item[FSM\_VCI\_RSP :] Cette automate gère la section {\bf SECTION\_VCI\_RSP}. Il contrôle la réception des réponses par le bus VCI et les stocke dans la file QUEUE\_RSP. + +Chaque paquet requête VCI provoque la réception d'un paquet de réponse. Seul les échecs de lecture cachée vont avoir plus d'un paquet réponse. La ligne en cours de réception est stockée dans un tampon. Une fois le paquet de fin reçu, le contenu du tampon ou la réponse sera stocké dans la file QUEUE\_RSP. + +L'automate ne peux plus accepter de réponse VCI si QUEUE\_RSP est plein. + \end{description} +\item Trois files d'attentes : + \begin{description} + \item[QUEUE\_READ\_HIT :] Toute requête provenant du processeur et qui n'accède pas au bus VCI passe par cette file. Elle contient les requêtes de lectures cachés ayant fait un succès. + +Les informations sont stockés dans le bloc RAM\_INFO, cette file ne contient qu'un index permettant d'adresser le bloc RAM\_INFO. + \item[QUEUE\_REQ :] Toutes les requêtes qui ne sont pas stocké dans la file QUEUE\_READ\_HIT sont alors stockés dans la QUEUE\_REQ. Il s'agit des écritures ou des lectures ayant fait un MISS ou réalisant un accès non cacheable. + +Cette file est à la frontière entre les sections {\bf SECTION\_DCACHE\_REQ} et {\bf SECTION\_VCI\_REQ}. + \item[QUEUE\_RSP :] Chaque paquet requête émit sur l'interface VCI\_REQ provoque l'émission par la cible d'un paquet réponse. Une fois que la réponse entière est revenu au cache, elle est stockée dans la file QUEUE\_RSP. A la différence des deux autres files d'attente, elle ne contient pas qu'une adresse vers une entrée du bloc RAM\_INFO. Chaque entrée contient une ligne de cache provenant d'un échec de de lecture, ainsi que le code d'erreur envoyé par la cible. + +L'automate {\bf FSM\_DCACHE\_RSP} donne la priorité au réponse car le processeur à effectué depuis plusieurs cycle l'accès et attend une éventuelle réponse. Cette file n'a pas besoin d'avoir beaucoup d'entrées. + \end{description} +\item Trois blocs mémoires : + \begin{description} + \item[RAM\_DATA :] Cette ram contient toute les données du cache. Elle est décomposé en autant de banc que le degré d'associativité du cache (ASSOC). Pour indexer une ligne particulière, il faut donc le numéro de la ligne (l'index) et le numéro de banc. Chaque ligne contient plusieurs mots. Un mot particulier est adressé par le déplacement contenu dans l'adresse (l'offset). Enfin un mot est composé de plusieurs octects, qui est l'unité la plus petit que peut modifier le processeur. + + Cette ram possède un port d'écriture : il est accédé lors de la section {\bf SECTION\_DCACHE\_RSP} et va écrire, dans le cas d'un échec de lecture, une ligne complète dans la RAM\_DATA. Ce port est accèder lors de la section {\bf SECTION\_DCACHE\_RSP}. La section {\bf SECTION\_DCACHE\_REQ} va soit lire un mot dans le cas d'un read-hit, soit écrire un mot dans le cas d'un write-hit. Pour cela, il y a un port pour réaliser ces deux accès. + \item[RAM\_TAG :] Ce bloc mémoire contient les informations du contrôle du cache. Pour chaque ligne du cache contenus dans RAM\_DATA, nous sauvegardons deux informations : un bit de validité, qui indique si la ligne correspondante contient des données valide ou non, et un champ Tag qui contient l'étiquette de la ligne de cache. + +Le bloc RAM\_TAG possède 2 ports : le premier est un port de lecture contrôlé par la section {\bf SECTION\_DCACHE\_REQ}. Une requête provenant du processeur accède aux informations de la ligne de cache, le bloc RAM\_TAG va lire simultanément tous les tag de chaque banc et indiquer si l'accès réalise un succès. Si c'est le cas, il fournit le numéro de banc le réalisant. Le deuxième port est un port d'écriture accèdé lors de la section {\bf SECTION\_DCACHE\_RSP}. Après avoir choisit une victime (donc un numéro de banc pour la ligne de cache), nous allons enregistrer dans cette mémoire son étiquette et placer le bit de validité à 1. + \item[RAM\_INFO :] Ce bloc contient toute les informations des requêtes en cours de traitement (requêtes pendantes). Nous avons centralisé toutes les informations des requêtes dans une seule mémoire. Ceci permet de ne pas dupliquer les informations. Le nombre d'entrée de cette mémoire représente le nombre maximales de requêtes pendantes. + + Il y a 3 ports à cette mémoire : le premier est utilisé lors de la section {\bf SECTION\_DCACHE\_REQ} qui consiste à demander au bloc RAM\_INFO d'allouer une case et enregistrer les informations fournit par la requête. La requête provenant du processeur ne peux pas être accepter si aucune entrée n'est disponible. Le deuxième port est utilisé par la section {\bf SECTION\_VCI\_REQ} pour récuper les informations de la requête pour envoyer un paquet de requête : l'adresse, la commande, la donnée à écrire ainsi qu'un masque concernant les octects de la donnée. L'identifiant du paquet VCI sera le numéro d'entrée de la RAM\_INFO. Un paquet réponse revoye l'identifiant contenu dans le paquet requête. Ceci permet à la section {\bf SECTION\_DCACHE\_RSP} d'accèder au bloc RAM\_INFO pour récuperer les informations afin de constituer la réponse pour le processeur : identifiant de requête, erreur, ... Si la réponse est envoyée avec succès au processeur, le bloc RAM\_INFO va désallouer l'entrée utilisé lors de cette section. + \end{description} +\end{itemize} + +\subSection{Chemin des requêtes} +Dans cette section, nous allons voir le chemin des requêtes en fonction de leur type et de leur succès ou échec dans le cache. + +\begin{description} +\item[Read - cached - Hit :] Une requête de lecture provenant du processeur va accèder au bloc RAM\_TAG afin de définir si le cache fait un hit sur cette accès. En cas de cache associatif, le bloc RAM\_TAG va également retourner le numéro de banc dans lequel la ligne est stockée. Dans le même temps, la requête va demander une allocation d'une entrée dans le bloc RAM\_INFO, et y stocker les informations de requêtes ainsi que la donnée lut. + +L'identifiant retournée par le bloc RAM\_INFO est enregistré dans la file d'attente QUEUE\_READ\_HIT. Cette file est de type First In First Out. Une fois que la requête arrive en tête de file, alors elle sera traité par la section {\bf SECTION\_DCACHE\_RSP}. L'automate FSM\_DCACHE\_RSP donne la priorité à la file QUEUE\_RSP. La requête sera selectionnée une fois que la file QUEUE\_RSP est vide. Ensuite avec le numéro d'identifiant, nous adressons le bloc RAM\_INFO afin de lire les donnée utile pour une réponse : donnée à lire, identifiant de requête ... + +La requête de lecture est terminé dès que le processeur renvoie accepte la requête de réponses. + +\item[Read - cached - Miss :] Lors de l'accès au bloc RAM\_TAG, ce dernier indique que la ligne contenant l'adresse demandé n'est pas dans le cache. Dans ce cas nous avons un échec de lecture. Les informations concernant la requête est enregistré dans une ligne nouvellement alloué du bloc RAM\_INFO. L'identifiant retournée par ce bloc est enregistré dans la file d'attente QUEUE\_REQ. C'est également un file de type FIFO. + +Une fois que la requête arrive en tête de cette file, l'automate FSM\_VCI\_REQ va lire les informations à partir de RAM\_INFO. Avec ces informations l'automate va provoquer (NB\_WORD * SIZE\_WORD) / SIZE\_WORD\_VCI paquets requêtes. Les adresses des paquêts sont les adresses de la ligne de cache. Suivant la norme VCI seul le dernier paquet aura le champ EOP (End Of Packet) à 1. + +Une fois tous les paquets de requêtes envoyés, l'entrée contenue dans la file QUEUE\_REQ est supprimée. + +La section {\bf SECTION\_VCI\_RSP} attend les paquets réponses. A réception de la première réponse, nous allons remplir un buffer qui va contenir la ligne demandée. Suivant la norme VCI, les réponses sont atomiques, c'est à dire que lors de la réception d'une réponse, nous ne pouvons pas recevoir un paquet d'une autre réponse. Une fois le dernier paquet de réponse, nous enregistrons la ligne ainsi que le code d'erreur dans la file d'attente QUEUE\_RSP. + +La section {\bf SECTION\_DCACHE\_RSP} va lire l'entrée de la file QUEUE\_RSP. Comme l'identifiant de requête VCI sert aussi d'adresse pour le bloc RAM\_INFO, nous pouvons récupérer les informations de la requêtes mémoire. Si la requête n'a pas fait d'erreur, le cache sera mise à jour : choix d'un banc victime, écriture de la ligne dans le bloc RAM\_DATA et écriture de l'étiquette dans RAM\_TAG. Le bit de validité de la ligne est placé à 1. + +Dans tous les cas, la requête est envoyé sur le port DCACHE\_RSP du processeur. Dès que la réponse est accepté par le processeur, l'entrée contenue dans la file QUEUE\_RSP est supprimée. +\item[Read - uncached : ] Un accès en lecture non caché est identique à un accès en lecture caché réalisant un échec d'accès au cache. Néanmoins il y a 2 changements : +\begin{itemize} +\item Le premier est que SIZE\_WORD / SIZE\_WORD\_VCI paquets requête sera émis sur l'interconnect VCI. Ils ne contiendront que l'adresse désirée. Il y a un nombre équivalent de paquets réponses attendus. +\item Le cache ne sera pas mise à jour, c'est à dire pas d'écriture dans les blocs RAM\_DATA et RAM\_TAG. +\end{itemize} + +{\it {\bf Remarque :} Nous faisons l'hypothèse qu'une requête non cachable ne peut jamais être dans le cache. C'est à dire que si l'adresse cible ne peut changer de status en cours d'éxecution et que c'est toute la ligne qui la contient qui est cachable ou non. Si cette hypothèse n'est plus vrai, alors lors de l'émission de la requête, il faut que le cache invalide l'entrée la contenant.} + +\item[Write - cached - Hit :] Lors d'une requête d'écriture caché, nous accèdons au bloc RAM\_TAG. Ce dernier indique que la ligne contenant l'adresse demandé est dans le cache : c'est donc un succès. La ligne contenant l'adresse envoyée par le processeur doit être mise à jour. Pour cela, la requête accède au bloc RAM\_DATA et écrit la donnée envoye par le processeur. + +De plus les informations concernant la requête est enregistré dans une ligne nouvellement alloué du bloc RAM\_INFO. L'identifiant retournée par ce bloc est enregistré dans la file d'attente QUEUE\_REQ. + +Une fois que la requête arrive en tête de cette file, l'automate FSM\_VCI\_REQ va lire les informations à partir de RAM\_INFO. Avec ces informations l'automate va envoyer (SIZE\_WORD) / SIZE\_WORD\_VCI paquets requêtes avec les données à écrire. Suivant la norme VCI seul le dernier paquet aura le champ EOP (End Of Packet) à 1. + +Une fois tous les paquets de requêtes envoyés, l'entrée contenue dans la file QUEUE\_REQ est supprimée. + +La section {\bf SECTION\_VCI\_RSP} attend les paquets réponses. Seul les codes d'erreurs sont récupérés car l'écriture ne récupére aucune information. Une fois le dernier paquet de réponse, nous enregistrons le code d'erreur dans la file d'attente QUEUE\_RSP. + +La section {\bf SECTION\_DCACHE\_RSP} va lire l'entrée de la file QUEUE\_RSP. Comme l'identifiant de requête VCI sert aussi d'adresse pour le bloc RAM\_INFO, nous pouvons récupérer les informations de la requêtes mémoire. Si la requête a un code d'erreur non nul, alors une réponses sera envoyer au processeur. Sinon aucune réponse n'est envoyée au processeur lors d'une écriture. Ensuite l'entrée contenue dans la file QUEUE\_RSP est supprimée. +\item[Write - cached - Miss :] Un échec d'écriture est équivalent à une réussite d'écriture mais sans mise à jour du cache. +\item[Write - uncached : ] Un accès en écriture non caché est équivalent à un accès en écriture caché réalisant un défaut de cache. +\item[Prefetch :] La pré lecture (prefetch) est une technique qui consiste à anticipé l'accès à une adresse en pré-chargeant une ligne de chace. Comme cette ligne ne sera pas forcément utile, il ne faut pas qu'elle modifie le cache. La ligne est en général stocké dans un petit cache. Ce cache de pré lecture est accèdé en parralèle à l'accès au cache, ou après un MISS. Lors d'un hit dans le cache de prélecture, la ligne sera placée dans le cache. La décision de préchargé une ligne peut être aussi bien logiciel que matériel. La présence d'un type {\it PREFETCH} indique que le processeur (et le logiciel tournant sur le processeur) peut envoyer des directives de préchargements. + +Dans l'implémentation de ce cache, nous n'avons pas inclue de mécanisme de pré-lecture. Pour cela, ces accès mémoires sont ignorées. Nous ne fournissons pas de réponses à ces requêtes. +\item[Lock :] Le verrouillage de lignes est une technique qui permet d'enlever une ligne de la politique d'évincement du cache. Le programmeur qui a une vision global de l'application peut avoir une variable très utilisé. Dans ce cas, il envoie une directive de verrouillage de ligne et possède la donnée dans le cache. Ce mecanisme peut ressembler au mot clé {\bf register} en C qui une directive pour le compilateur de tenter de placer la variable dans un registre du processeur. + +Le verrouillage ce fait jusqu'à une demande d'invalidation ou de flush de la ligne. C'est au cache de ne pas verrouiller l'intégralité d'un ensemble de ligne. C'est à dire que le cache doit au moins avoir pour chaque index, une ligne non verrouiller. Ceci impose que le cache soit au moins semi associatif. Dans un cas de conflit (c'est à dire lors d'une demande de verrouillage de la dernier ligne disponible d'un sensemble), le cache doit choisir une victime parmit les lignes verrouiller. + +Dans l'implémentation de ce cache, nous n'avons pas inclue de mécanisme de verrouillage de ligne. Ces accès mémoires sont ignorés. Nous ne fournissons pas de réponses à ces requêtes. +\item[Invalidate :] Un accès mémoire de type {\it invalidation} est une directive qui va de supprimer la ligne correspondante dans le cache. L'invalidation ne va pas annuler les requêtes pendantes sur cette adresse. Mais à la fin de l'execution de cet accès mémoire, il ne doit avoir aucune instruction pendante sur l'ensemble de cette ligne de cache. + +D'après les hypothèse donnée en introduction de cette section, comme nous n'avons pas d'accès conflictuel. Si la ligne est dans le cache, la section {\bf SECTION\_DCACHE\_REQ} va placer le bit valide contenu dans le bloc RAM\_TAG. Sinon, cet requête n'aura aucun effet sur le cache. + +Le cache ne fournit pas de réponses à ces requêtes. + +\item[Flush :] Un accès de type {\it flush} consiste à rendre cohérent les caches locaux ainsi que la mémoire principal. Toute les modifications de la ligne contenant l'adresse fournit par la requête doit être envoyé à la mémoire principale. A la fin de l'execution de cette instruction, toute les écritures sur la ligne de cache ciblée doit être terminée. + +Pour notre implémentation de cache, celui-ci est write through. Il y a une cohérence entre le contenu du cache et le contenu de la mémoire. De plus, d'après les hypothèse donnée en introduction de cette section, comme nous n'avons pas d'accès conflictuel. Dans ce cas, cette commande est ignorée. + +\item[Synchronization :] Ce type spécial est intégralement géré par l'automate {\it FSM\_DCACHE\_REQ}. Après la réception de cette requête, le cache ne va accepter plus aucune requête provenant du processeur jusqu'a ce qu'il n'y ait plus aucune requête en cours de traitement. La condition de reprise du cache est que le bloc RAM\_INFO soit vide. Une fois la RAM\_INFO vide, alors toutes les lectures (succès ou échec) ont été retournée au processeur. De plus chaque requête d'écriture envoyé sur l'interconnect VCI retourne une réponse. Ce n'est qu'une fois la réponse VCI parvenue au cache que l'entrée dans le bloc RAM\_INFO peut être désalloué. Ceci garantie qu'il n'y a aucune requête (aussi bien de lecture que d'écriture) en cours d'éxecution. + +\end{description} + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/03_problem.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/03_problem.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/03_problem.tex (revision 45) @@ -0,0 +1,180 @@ +\Section{Quelques problèmes du modèle simplifié}\label{problem} + +Cette section est une énumérations de problèmes fonctionnels du modèle de base. Pour chacun d'entre eux, nous allons présenter un exemple où le problème peut survenir, ensuite nous allons exposer la nature du problème et enfin nous allons apporter des solutions et débattre de chacune d'entre elles. + +Pour cela, nous enlevons toutes les hypothèses vut en introduction de section \ref{overview_partial}. + +\subSection{Requêtes multiples d'échec de lectures}\label{multiple_read_miss} + +\subsubSection{Contexte} + +Le processeur execute un appel de fonction. Le prototype est en 7 étapes : +\begin{enumerate} +\item Sauvegarde des registres utilisés dans la pile +\item Modification du pointeur de pile +\item Corps de la fonction +\item Ecriture du résultat dans le registre de retour +\item Restauration du pointeur de pile +\item Restauration des registres +\item Retour vers l'appellant +\end{enumerate} + +Nous nous placons dans un envirronement 32 bits, de plus nous supposons que l'étape 6 est à une adresse de début d'une ligne de cache. Par exemple à l'adresse 0x100 avec un cache de 8 lignes de 4 mots. + +Nous allons supposer que la requête de lecture à l'adresse 0x100 fait un échec de lecture, alors les requêtes aux adresse consécutives suivante font également des échecs de lectures (les adresses 0x104, 0x108, 0x10C ...). + +\subsubSection{Problème} + +Deux problèmes ce présente : +\begin{enumerate} +\item Le premier étant la résolution par le cache de plusieurs échecs de lecture. Or la ligne concernée est identique pour toute les requêtes. +\item Le premier point n'est pas vraiment un problème, car il va juste rendre plus long les accès mémoires. Or si le cache n'est pas direct-map, alors la duplication des requêtes concernant la même ligne de cache va impliquer que la ligne concernée va être logée dans plusieurs endront du cache. Donc une même ligne peut être dans deux emplacements de lignes de cache différents. Dans ce cas, quels lignes modifier en cas d'écriture ? +\end{enumerate} + +Les causes sont les suivants : +\begin{enumerate} +\item {\it Le premier problème est causé par la non sauvegarde par le cache de l'historique des requêtes.} +\item {\it Le deuxième problème est causé par le non accès à la RAM\_TAG, au moment des réponses. } +\end{enumerate} + + +\subsubSection{Solutions} + +Il y a trois solutions pour remédier à ces problèmes : +\begin{enumerate} +\item Ajouter un port de lecture au bloc RAM\_TAG. Dans la section {\bf SECTION\_DCACHE\_RSP}, lors de la lecture du paquet réponse contenu dans la file QUEUE\_RSP, nous allons vérifier si l'accès au cache réalise toujours un MISS. Si c'est le cas alors on met à jour le cache. Sinon aucune mise à jour ne devra être effectué. + \begin{description} + \item[Avantages :] Coût minimum si on implémente le banc de registre TAG par un banc de registres multi-bancs (mais synchronisation entre les automates FSM\_DCACHE\_REQ et FSM\_DCACHE\_RSP). + \item[Inconvénients :] Accès à la mémoire inutile, les coût des miss deviennent plus long car on rappatrie une ligne entière à chaque fois + \end{description} +\item La deuxième solution est d'empêcher ce cas d'arriver. Pour cela il faut avoir un historique des requêtes. Pour chaque ensemble (un ensemble est la totalité des destinations où une lignes de caches peut être stockées. Un ensemble est composé de ASSOC lignes et il y a NB\_LINE / ASSOC ensembles dans un cache) nous ajoutons un bit de verrouillage. + +Lors de l'allocation d'une ligne, le bit est positionné à 0. Lors d'un échec de lecture on verrouille la ligne en positionant le bit à 1. Lors de la résolution du miss , donc lors du retour des paquets réponses, ce bit est remis à 0. Nous n'acceptons une requête que si le bit de verrouillage est positionné à 0. + \begin{description} + \item[Avantages :] Pas de duplication des requêtes. + \item[Inconvénients :] Ajout d'éléments mémorisant : 1 bit par ensemble. Solution non scalable avec l'augmentation de l'associativité : le nombre d'élément mémorisant va diminué mais le nombre de ligne vérrouiller va inversement augmenter. + \end{description} + +\item La troisième solution reprends l'idée de verrouillage mais en l'appliquant non plus au niveau de l'ensemble mais au niveau de la ligne. Le nombre de ligne verrouiller sera toujours de 1. Or dans la solution précedente, nous avons verrouiller un ensemble car nous savons que la ligne récupérer par l'échec de lecture va être placé dans un ensemble. Or le choix de la victime de fait lors de la réception de la réponses. + +Ici la solution est de placer le choix de la victime lors de l'émission de la requête, c'est à dire dans la section {\bf SECTION\_DCACHE\_REQ}. + \begin{description} + \item[Avantages :] Une seule ligne est vérrouillée. + \item[Inconvénients :] Coûte 1 bit par ligne de cache. De plus, entre l'allocation de la requête et l'écriture de la ligne dans le cache, le contenu de la ligne est indisponible. Nous avons potentiellement supprimé une ligne qui aurait put être utilisé durant cette tranche de temps. + \end{description} +\end{enumerate} + +{\it Remarque : } Le cycle d'acceptation de la requête (c'est à dire le signal DCACHE.REQ\_ACK) ne dépends plus seulement de l'état des FIFOs (disponible au début du cycle) mais également de la requête elle même. La chaîne critique sera donc un aller / retour entre le processeur et le cache. A cause du besoin de ne pas bloquer les requêtes, pipeliner cette accès devient difficile car quand nous refusons une requête, il ne faut pas quel soit taggué comme lancer par le processeur. Sinon, des problèmes de consistance mémoires peuvent arriver. Pour plus de détails, voir les sections \ref{pipeline} et \ref{consistance} + + +La différence principales entre les deux dernières solutions porte sur le nombre de lignes verrouillées. Ceci influe directement sur le coût en surface et sur la perte de performance. Dans la section \ref{consistance} nous allons voir que les solutions proposer sont basé sur le verrouillage de lignes de caches, donc afin d'uniformisé la solution retenue, nous n'allons pas choisir la première solution. + +%\subSection{Évincement précoce de ligne } +% +%\subsubSection{Contexte} +% +%\subsubSection{Problème} +% +%\subsubSection{Solutions} +% +% +%Dans le cas d'un write HIT, lors de la requête, on détermine le numéro de ligne, et le numéro de banc où la donnée doit être écrite. L'écriture effective se fait lors de la réponse. La ligne cible peut pendant ce temps être évincer par une autre réponse (un Read MISS par exemple). +%Les solutions apportés par ce problème sont presque les mêmes que pour le problème précèdent : +%\begin{enumerate} +%\item Ajouter un port d'écriture. Dans ce cas, l'écriture effective se fait lors de la requête. +%\item Verrouillage des lignes : ceci va empêcher l'évincement de la ligne concerné par l'écriture. +%\item Verrouillage des index : ceci va empêcher les évincements des lignes de cache. +%\end{enumerate} + +\subSection{Gestion de la Cohérence mémoire} + +La hierarchie mémoire doit assurer la cohérence mémoire (détermine quelle valeur est renvoyée par une lecture). Or les problèmes de cohérence mémoire ne surviennent que dans le cas d'un environnement avec un système multi-processeur et/ou avec des périphériques d'entrée/sortie. Nous n'aborderons pas ici les solutions matérielles pour résoudre ce problème. Le problème pouvant être résolu de manière logicielle en effectuant la séquence suivante présentée dans le graphe \ref{CACHE_coherence_memoire} + +\printgraphonly{CACHE_coherence_memoire}{.8} + +\subSection{Gestion de la Consistance mémoire}\label{consistance} + +La hierarchie mémoire doit également assurer la consistance mémoire (détermine quand une valeur écrite sera récupérée par une lecture). + +\subsubSection{Contexte} + +On suppose que le processeur effectue une requête de lecture à l'adresse 0x100 puis une requête d'écriture à cette même adresse. Nous supposons également que la ligne contenant l'adresse 0x100 n'est pas présente dans le cache. Dans ce cas, le cache peut alors lancer la requête de lecture sur l'interconnect VCI. Sans attendre la réponse de cette requête, le cache peut lancer la requête d'écriture. + +\subsubSection{Problème} + +La norme VCI n'impose pas à l'interconnect une garantie sur l'ordre d'acheminement des paquets. La norme VCI garantie seulement l'atomicité d'une réponse VCI (pas d'entrelacement de deux réponses VCI vers la même entité). Avec une telle propriété, les transactions de lecture et d'écriture entre en compétition pour l'accès à la zone mémoire. Ainsi ces requêtes peuvent accéder à la zone mémoire dans un ordre différent que dans l'ordre d'émission. + +Ce problème est amplifié par le fait qu'une demande de lecture va lire une ligne de cache entière. Dans ce cas pour un cache de 4 mots de 32 bits par lire, un accès en écriture à l'adresse 0x100 et une lecture à l'adresse 0x104 sont conflictuelle : la lecture se fait sur les adresses 0x100, 0x104, 0x108 et 0x10C. Et contient donc l'adresse de l'écriture. Il y a donc des dépendances si les deux adresses  sont dans la même ligne de cache et que l'un des deux accès est une lecture. + +Les problèmes de consistances mémoires peuvent se résumer en énumérant les 4 types de dépendances possibles : +\begin{description} +\item[RaR (Read after Read) :] Il s'agit de deux lectures successives vers la même ligne de cache.\\ +Dans le cadre d'une dépendance RaR, deux lectures concurentes ne posent de problèmes que si elles accèdent à une variable partagé par un autre processeur. Or ceci est résolue par les mécanisme de cohérence mémoire. Un autre problème a été vu à la section \ref{multiple_read_miss}, qui est la gestion de plusieurs échecs de lecture ciblant la même ligne de cache. +\item[WaR (Write after Read) :] Il s'agit d'une lecture suivit d'une écriture vers la même ligne de cache.\\ +Du point de vue du processeur et dans le cadre d'exception précise, une écriture n'a le droit de modifier le contexte visible du programmeur que si les instructions avant l'écriture sont terminée. Ceci inclue également les instructions de lecture mémoire. +Or les lectures sont bloquantes : tant que la donnée de la lecture n'est pas arrivé, la lecture ne peut se terminé. Donc au moment où la donnée arrive, le processeur peut savoir si la lecture à réaliser une exception. Le processeur gére alors les dépendances WaR. +\item[WaW (Write after Write) :] Il s'agit de deux écritures successives vers la même adresse.\\ +Dans l'item précédent, nous avons vut que le processeur ne doit pas lancer une écriture si toute les instuctions précédentes ne sont pas terminées. Donc au moment où une écriture est lancée, toute les lectures précedentes ont leurs opérandes et n'ont pas réaliser d'exception (Sinon le processeur appel la routine d'exception). +Or les écritures ne sont pas bloquantes. C'est à dire qu'il n'y a pas d'acquittement. Donc au moment où le processeur envoye une requête d'écriture au cache, il peut avoir plusieurs requêtes d'écriture en cours d'éxecution. C'est alors au cache de gérer ces dépendances. +\item[RaW (Read after Write) :] Il s'agit d'une écriture suivit d'une lecture vers la même ligne de cache.\\ +Les dépendances RaW sont les moins triviaux. Le processeur ne peut pas gérer ces dépendances pour la même raison que dans l'item précédent : il ne reçoit pas de réponse lorsque l'écriture est effective. De plus, en cas d'échec lors de l'accès au cache, une lecture va chargé une ligne. Donc les dépendance se font au niveau de la ligne, or le processeur ne connaissant pas la taille de la ligne, c'est au cache de gérer ces dépendances. +\end{description} + +\subsubSection{Solutions} + +Pour gérer ces différents problèmes, il y a deux solutions : +\begin{enumerate} +\item Gestion par le CPU : pour cela le processeur doit connaître la taille maximale d'une ligne de cache (nous définissons par taille maximale, la taille de la ligne de cache contenus dans le dernier niveau de cache avant la mémoire principal ou avant un cache possédant des mécanismes de gestions de consistance mémoires.) + +De plus, il faut aussi que toute les requêtes émisent par le processeur soit aquitter. Ceci inclue les requêtes d'écritures. + +Avec ces deux conditions, l'unités de gestion mémoire du processeur peut connaître quand deux instructions mémoires sont en dépendances. Et peut alors agir en conséquence en interdisant leur envoie. + +Or le cache que nous définissons va être utilisé avec un processeur qui lance dans le désordre les instructions et lance également dans le désordre les instructions mémoires. Les instructions mémoires sont stoqués dans une file d'attente (généralement appelé la LSQ (Load Store Queue)). Chaque adresse de chaque accès mémoire sera comparé avec les adresses de tous les accès mémoires précédents. Ceci permet de vérifier si un accès mémoire est indépendant d'un autre. Ce mécanisme peut être utilisé pour détecter les dépendances. + +Pour une file de taille $N$, il y a $\frac{(N-1)*N}{2}$ comparateurs de 32 ou 64 bits. + +En prenant les hypothèses fournit dans la section \ref{hypothese}, nous avons 1 accès mémoire par cycle, 1 instruction d'écriture tous les 3 cycles et un aller retour processeur/mémoire de 30 cycles. Si les instructions d'écriture doivent être aquitter avant de libérer une case, alors chaque instructions d'écriture doivent attendre 30 cycles avant de libérer l'entrée qu'il occupe dans la load store queue. Et pendant se laps de temps, il y a eu 30*4 soit 120 instructions nouvellement chargés dont 120*10\% = 12 nouvelles instructions d'écritures. Le processeur doit également attendre la fin d'une écriture avant d'en éxécuter une nouvelle. + +Nous pouvons conclure que quelque soit la taille de la LSQ, le débit entrant d'instruction d'écriture est 12 fois plus important que le débit sortant de ces mêmes instructions. + +C'est pour ces raisons que la gestion de la consistance mémoire ne doit par être gérer par le processeur. +\item Gestion par le Cache : + +Dans la section \ref{multiple_read_miss}, nous avons vu une manière de gérer de multiples requêtes de lectures qui réalisent un accès sur une ligne de caches non présente. Nous pouvons voir ce problème de manière plus général comme étant un problème de dépendance RaR. + +Nous allons réutiliser la solution du verrouillage de ligne de cache et l'étendre à toute les requête. Le principe étant simple : lors d'une requête (lecture ou écriture), nous vérrouillons la ligne qui contient (ou va contenir) l'adresse envoyer par le processeur. Ensuite lors de la réception de la réponse, nous déverrouillons la ligne. + +Si entre temps il y a une requête qui accède à une ligne verrouillé alors elle n'est pas accepter par le cache. + +Tout comme la section \ref{multiple_read_miss}, nous pouvons soit faire du verrouillage de famille soit faire du verrouillage de ligne. Pour les même raisons de scalabilité, nous préférons la solution de verrouiller au niveau ligne. Donc nous devons faire de l'allocation précose de ligne. Pour cela, nous devons avoir dans le cache l'étiquette de la ligne qui va être envoyé sur l'interconnect VCI. Ceci concerne les échec de lecture ainsi que les succès d'écriture. Mais également les échec d'écriture. Ceci signifie que nous allons évincer une ligne de cache afin d'avoir l'étiquette de l'échec d'écriture dans le cache. Or le cache n'est pas write allocate donc lors de la réception du paquet réponses, nous ne rappatrions pas une ligne de cache. C'est pour cela que dans ce cas préçit nous devons invalider la ligne. + + +\begin{tabular}{l|ll} +Cas & Action lors d'une requête du processeur & Action lors d'une réponse du bus \\ +\hline +Read Hit & Lecture de la donnée & Aucune réponse attendue \\ + & Pas de requête envoyée au bus & \\ +Read Miss & Allocation d'une ligne de cache & Écriture de la ligne\\ + & Verrouillage de la ligne de cache & Déverrouillage de la ligne de cache\\ +Write Hit & Ecriture de la donnée & \\ + & Verrouillage de la ligne de cache & Déverrouillage de la ligne de cache\\ +Write Miss & Allocation d'une ligne de cache & \\ + & Verrouillage de la ligne de cache & Invalidation de la ligne (write no-allocate)\\ +\end{tabular} +\end{enumerate} + +\subSection{Multi-Contexte} + +Le cache que nous sommes en train de spécifier doit pouvoir être utiliser avec un processeur multi-contexte (par exemple qui implémente du SMT (Simultaneous Multi Threading). +Le cache que nous nous proposons de faire sera physiquement indéxé et physiquement tagué. C'est à dire que la traduction entre l'adresse virtuelle et l'adresse physique ce fait en amont du cache. +Ceci à pour effet qu'il n'y a aucune difference entre la gestion d'un processeur mono contexte et d'un processeur multi contexte. + +Nous pouvons néanmoins montrer quelques effets de bords : + +Le cache est optimisé pour utiliser les propriétés de localité spatiale et temporelle d'un programme. Avec l'ajout du multi-contexte, le cache est soumi à plusieurs flot qui sont indépendant entre eux. +Ceci va entraîner des évincements de lignes en faveur d'un contexte, alors que la ligne victime pouvait être utilisée par un autre contexte. On appelle cette évènement le ``pourrissement du cache''. Afin de minimiser ces effets, le cache doit avoir un degré d'associativité qui est un multiple du nombre de contextes. + +Un autre effet de bord et la nécessité d'avoir un cache non bloquant. Si un contexte est bloqué à cause d'un évènement, les autres contextes ne sont pas forcément bloqués. + +Pour les solutions sur la consistance mémoire : avec l'augmentation conseillé de l'associativité, ainsi que l'augmentation de probabilité de deux requête accédant à la même famille, la solution du verrouillage de ligne va être plutôt choisit par rapport à la solution de verrouiller les familles. Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/04_overview_full.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/04_overview_full.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/04_overview_full.tex (revision 45) @@ -0,0 +1,190 @@ +\Section{Vue d'ensemble du cache - Modèle complet}\label{overview_full} +Cette section à pour but de montrer les modifications par rapport au modèle de base. + +\printgraphonly{CACHE_overview}{.8} + +\subSection{Solution retenue} + +Dans cette section, nous allons montrer la solution retenue. Il s'agit de l'intégration dans la modèle de base vue dans la section \ref{overview_partial} des solutions données au problème vus dans la section \ref{problem}. + +Le problème principal est la gestion par le cache de la consistance mémoire. Nous allons implémenté la solution consistant à vérrouiller les lignes de cache. Comme nous verrouillons au niveau des lignes de cache, nous avons besoin que la section {\bf SECTION\_DCACHE\_REQ} réalise le choix de la victime. + +La solution abordé dans la section précédente prévoit un bit de verrouillage qui est positionné à un lorsque une requête va être émise sur le bus, et positionné à 0 lors que la réponse reviens du bus. Tous requête qui accède à cette ligne de cache n'est pas accepter. De plus nous pouvons noter lors de la selection d'une victime, le cache n'accepte pas la requête si la victime est vérrouillé. + +Le tableau suivant résume pour tous les cas possibles, ce que la théorie autorise, et ce que notre algorithme actuelle autorise. + +\begin{tabular}{l|cc} +Cas & théorie & algo actuel \\ +\hline +2 lectures adressant la même adresse & oui & non \\ +2 lectures adressant la même ligne de cache & oui & non \\ +2 lectures adressant deux lignes de cache différentes & oui & oui \\ +2 écritures adressant la même adresse & non & non \\ +2 écritures adressant la même ligne de cache & oui & non \\ +2 écritures adressant deux lignes de cache différentes & oui & oui \\ +1 lecture suivit d'1 écriture adressant la même adresse & non & non \\ +1 lecture suivit d'1 écriture adressant la même ligne de cache & oui & non \\ +1 lecture suivit d'1 écriture adressant deux lignes de cache différentes & oui & oui \\ +1 écriture suivit d'1 lecture adressant la même adresse & non & non \\ +1 écriture suivit d'1 lecture adressant la même ligne de cache & oui & non \\ +1 écriture suivit d'1 lecture adressant deux lignes de cache différentes & oui & oui \\ +\end{tabular} + +La solution actuelle est très restrictive. Ceci est du au fait que quant le cache verrouille une ligne de cache, il ne sait pas si c'est un échec de lecture ou une écriture qui est la cause du verrouillage. + +Pour cela, nous modifions l'algorithme en ne proposant pas un bit de verrouillage mais deux bits de verrouillage : +\begin{description} +\item[Lock\_by\_read : ] la ligne de cache à été verrouiller par une lecture. (Un échec de lecture de cette ligne de cache est en cours de traitement). +\item[Lock\_by\_write : ] la ligne de cache à été verrouiller par une écriture. (Une écriture d'un mot de cette ligne de cache est en cours de traitement). +\end{description} + +En terme d'implémentation, nous avons ajouter un banc de registre RAM\_LOCK contenant ces deux bits de verrouillage. De plus nous avons déplacer le bit de validité contenant dans RAM\_TAG jusque dans ce bloc.% Ce déplacement provoque un petit changement : précédement lors que RAM\_TAG indiqué que l'accès était un succès alors ceci signifie que l'adresse envoyé par le processeur est dans une ligne de cache ET que cette ligne de cache est valide. Maintenant RAM\_TAG ne peut plus vérifier cette deuxième condition. + +\subSection{Protocole} + +Dans cette section, nous allons voir le protocole de gestion de la consistance mémoire. + +\printgraphonly{CACHE_protocole}{.55} + +Lors de l'arrivé d'une requête, la section {\bf SECTION\_DCACHE\_REQ} connait le type et à partir de l'adresse accède au bloc RAM\_TAG pour obtenir le numéro de banc. Avec ce dernier, le cache accède aux blocs RAM\_DATA et RAM\_LOCK. +\begin{itemize} +\item Si l'accès est une écriture, comme le cache est {\it write through}, cet accès va provoquer l'émission d'une requête sur l'interconnect VCI. + \begin{itemize} % write + \item Si l'écriture fait un succès dans le cache (RAM\_TAG contient l'adresse envoyé par le processeur), alors nous testons s'il n'y a pas une requête (aussi bien de lecture que d'écriture) en cours de traitement et que l'entrée dans le cache est valide. + \begin{itemize} % write hit + \item Si c'est le cas, alors nous n'acceptons pas cette requête d'écriture (sinon la requête d'écriture que nous evoyons risque de doubler la requête en cours de traitement). + \item Si aucun des bits de verrouillage n'est positionnée à 1, alors l'accès peut avoir lieu. Pour cela, nous indiquons qu'une requête d'écriture à lieu sur cette ligne de cache ({\it lock\_by\_write = 1}), puis nous chargeons les sections {\bf SECTION\_VCI\_REQ} et {\bf SECTION\_VCI\_RSP} d'effectuer la transaction avec la mémoire principale. La réception de la réponse par la section {\bf SECTION\_DCACHE\_RSP} va provoquer la mise à zéro du bit {\it lock\_by\_write}. + \end{itemize} + \item Si l'écriture fais un échec dans le cache, alors nous choisissons une victime. + \begin{itemize} % write miss + \item Si la victime n'est pas valide (les deux bits de verrouillage ne sont pas à 0), alors nous n'acceptons pas la requête d'écriture. + \item Si la victime est valide, alors nous verrouillons intégralement la ligne. Par intégrale, nous positionnons les bits {\it lock\_by\_write} et {\it lock\_by\_read} à 1. Le verrouillage intégrale empêche toutes lectures ultérieurs. Tous comme un succès d'écriture, la réception de la réponse va provoquer l'invalidation de la ligne de cache. Car comme le cache n'est pas write allocate, la ligne allouée ne sera pas remplit avec des données cohérentes. + \end{itemize} + \end{itemize} +\item Si l'accès est une lecture, nous devons tester la présence dans le cache de l'adresse envoyée par le processeur. + \begin{itemize} % read + \item Si l'adresse est contenu dans le cache, alors nous devons verifier si la ligne est verrouiller ({\it lock\_by\_read} = 1). Nous n'avons pas besoin de tester si la ligne est verrouiller par une écriture. Si c'est le cas et que l'écriture été une réussite, alors la donnée est à jour dans la ligne de cache, sinon le protocole place le bit {\it lock\_by\_read} à 1. + \begin{itemize} % read hit + \item Si ligne est verrouillée alors la requête n'est pas accepté. + \item Si au contraire, la ligne n'est pas verrouillé, alors la requête est accepté : on lit la donnée dans le bloc RAM\_DATA et on place la requête dans la file d'attente QUEUE\_READ\_HIT. Ensuite, la section {\bf SECTION\_DCACHE\_RSP} va s'occuper d'envoyer la réponse au processeur. + \end{itemize} + \item Si l'accès en lecture fait un échec, le cache doit choisir une victime. + \begin{itemize} + \item Si la victime n'est pas valide, alors la requête n'est pas acceptée. + \item Si la victime est valide, la section {\bf SECTION\_DCACHE\_REQ} peut effectuer une réquête. Pour cela elle inscrit les informations dans le bloc RAM\_INFO tout en verrouillant la ligne ({\it lock\_by\_read = 1}). Ensuite la donnée est écrite dans la file QUEUE\_REQ, ce qui provoque une emission puis une reception par les sections contrôlant l'interface VCI. A reception du paquet de réponse, la section {\bf SECTION\_DCACHE\_RSP} va écrire la ligne dans le cache et déverrouiller la ligne ({\it lock\_by\_read = 0}). + \end{itemize} + \end{itemize} +\end{itemize} + +\subSection{Structure interne} + +Dans cette section, nous allons voir comment sont structuré les ressources internes du cache non bloquant. + +Avant de détailler les interfaces de chaque composant, nous pouvons préciser que chaque interfaces suivent le protocole fifo. C'est a dire que pour chaque interface, il y a des blocs ``producteurs'' et des blocs ``consommateurs''. Les producteurs possède une sortie {\bf VAL} (c'est une entrée pour les consommateurs) qui indique si la requête qu'ils émettent est valide. Les consomateurs possède sortie {\bf ACK} (c'est une entrée pour les producteurs) qui indique si le consommateur peut accepter une requête. Il y a un transaction si $VAL and ACK = 1$ à la fin d'un cycle d'horloge. +L'avantage de ce protocole de la gestion intégré du contôle de flux : si un producteur n'a plus de donnée ou un consomateur ne peux plus accepter de transaction, il suffit de positionner respectivement les signaux {\bf VAL} et {\bf ACK} à 0 pour ne pas autoriser de transaction. + + +Nous allons maintenant détailler les ressources internes du cache non bloquant : +\begin{itemize} +\item Trois files d'attentes : + \begin{description} + \item[QUEUE\_READ\_HIT :] (figure \ref{CACHE_bloc_QUEUE_READ_HIT}) Cette file d'attente s'occupe de transmettre le plus tôt possible les requêtes de lecture ayant fait un HIT. + \begin{description} + %\item {\it Valid : } Indique si l'entrée correspondante contient une donnée valide + \item {\it Index : } Index vers une entrée de RAM\_INFO + \end{description} + \printgraphonly{CACHE_bloc_QUEUE_READ_HIT}{.8} + \item[QUEUE\_REQ :] (figure \ref{CACHE_bloc_QUEUE_REQ}) Cette file est utilisée comme tampon d'écriture et de requête de lecture ayant fait un miss. Elle attende leur envoie à la mémoire. + \begin{description} + %\item {\it Valid : } Indique si l'entrée correspondante contient une donnée valide + \item {\it Index : } Index vers une entrée de RAM\_INFO + \end{description} + \printgraphonly{CACHE_bloc_QUEUE_REQ}{.8} + \item[QUEUE\_RSP :] (figure \ref{CACHE_bloc_QUEUE_RSP}) La file est utilisée comme tampon pour les réponses provenant de la mémoire. + \begin{description} + %\item {\it Valid :} Indique si l'entrée correspondante contient une donnée valide + \item {\it Index :} Index vers une entrée de RAM\_INFO + \item {\it Line :} Contient une ligne de cache retournée par l'interface de réponse et devant être écrit dans le bloc RAM\_DATA. + \item {\it Error :} Indique si l'accès effectué à générée une erreur ou pas. L'erreur sera interprété par l'exception générique ``Erreur de Bus''. + \end{description} + \printgraphonly{CACHE_bloc_QUEUE_RSP}{.8} + \end{description} +\item Trois blocs mémoires : + \begin{description} + \item[RAM\_TAG :] (figure \ref{CACHE_bloc_RAM_TAG}) Contient les informations pouvant identifier les adresses contenus dans cette ligne de cache + \begin{description} + \item {\it Tag :} Il s'agit de l'étiquette de l'adresse. A partir du numéro de ligne et de l'étiquette, cette RAM peut déterminer si le cache fait un succès ou non. + \end{description} + \printgraphonly{CACHE_bloc_RAM_TAG}{.8} + \item[RAM\_DATA :] (figure \ref{CACHE_bloc_RAM_DATA}) Contient les données de la ligne de cache + \begin{description} + \item {\it Line :} Contient la ligne de cache proprement dite + \end{description} + \printgraphonly{CACHE_bloc_RAM_DATA}{.8} + \item[RAM\_LOCK :] (figure \ref{CACHE_bloc_RAM_LOCK}) Contient les bits de gestions de dépendances + \begin{description} + \item {\it Valid :} Indique si la ligne correspondant contient une donnée valide. + \item {\it Lock\_by\_read :} Si le bit est positionné, alors il existe une requête de lecture actuellement en cours de traitement par le cache. + \item {\it Lock\_by\_write :} Si le bit est positionné, alors il existe une requête d'écriture actuellement en cours de traitement par le cache. + \end{description} + \printgraphonly{CACHE_bloc_RAM_LOCK}{.8} + \item[RAM\_INFO :] (figure \ref{CACHE_bloc_RAM_INFO}) Contient les informations relative au requête pendante. Pour plus de détails voir la section \ref{RAM_INFO} + \begin{description} + \item {\it Valid :} Indique si l'entrée correspondante contient une donnée valide + \item {\it Trdid, Pktid :} Identifiant de la requête. Le trdid indique le numéro de contexte du processeur qui à émit la requête. Alors que le pktid est le numéro de paquet de ce contexte. Le processeur garantie l'unicité du couple {trdid, pktid}. + \item {\it Address :} Adresse de la requête. Pour une identification rapide de la ligne concernée. + \item {\it Type :} Type de la requête (lecture, écriture, taille de l'accès, ...) + \item {\it Uncached :} Indique si la réponse doit modifier le cache. Dans le cadre d'une lecture par exemple. + \item {\it Data :} Donnée (en cas d'écriture : DCACHE.REQ\_WDATA, en cas de lecture avec succès : contenu d'un mot de la ligne de cache) + \end{description} + \printgraphonly{CACHE_bloc_RAM_INFO}{.8} + \end{description} +\item Quatre automates : + \begin{description} + \item[FSM\_DCACHE\_REQ :] (figure \ref{CACHE_automate-fsm_dcache_req}) %Cet automate gère la consommation des requêtes provenant du cache et, suivant le type d'accès et la réussite de l'accès, l'écriture dans les QUEUE\_REQ et QUEUE\_READ\_HIT + \printgraphonly{CACHE_automate-fsm_dcache_req}{1} + + \item[FSM\_DCACHE\_RSP :] (figure \ref{CACHE_automate-fsm_dcache_rsp}) %L'automate gère la consommation de donnée de la QUEUE\_RSP et s'occupe d'écrire dans le cache les lignes chargées. + \printgraphonly{CACHE_automate-fsm_dcache_rsp}{.8} + \item[FSM\_VCI\_REQ :] (figure \ref{CACHE_automate-fsm_vci_req}) %L'automate s'occupe de consommer une donnée de QUEUE\_REQ (si la file n'est pas vide) et la lance sur l'interface VCI\_REQ (si l'interface n'est pas occupée). + \printgraphonly{CACHE_automate-fsm_vci_req}{.8} + \item[FSM\_VCI\_RSP :] (figure \ref{CACHE_automate-fsm_vci_rsp}) %L'automate s'occupe de consommer sur l'interface VCI\_RSP (si l'interface n'est pas occupée) et l'écrit dans  la file QUEUE\_RSP (si la file n'est pas pleine). + \printgraphonly{CACHE_automate-fsm_vci_rsp}{.8} + \end{description} +\end{itemize} + +\subSection{RAM\_INFO en détail}\label{RAM_INFO} +Le bloc RAM\_INFO contient les informations relative aux requêtes pendantes. Elle est accéder par trois section du cache différente : {\bf SECTION\_DCACHE\_REQ} afin d'allouer une entrée dans ce bloc et d'écrire les informations concernant la requête, {\bf SECTION\_VCI\_REQ} afin de lire les informations utilies pour créer une requête VCI, et {\bf SECTION\_DCACHE\_RSP} afin de lire les informations permettant de répondre au processeur et d'écrire dans le cache et de désallouer l'entrée de RAM\_INFO. + +Le numéro de l'entrée dans lequel est écrit les informations est souvent utilisé. Aussi bien dans les différentes files QUEUE\_REQ, QUEUE\_RSP et QUEUE\_READ\_HIT, que pour indexer un paquet VCI. Ceci permet de ne pas dupliquer les informations inutilement et donc d'avoir des FIFOs contenant peut d'information. + +Le numéro de l'entrée sert également comme identifiant de requête lors d'une transaction VCI. Parce que le cycle de vie de cette identifiant garantie son unicité sur le réseau VCI. + +Nous pouvons remarquer que le nombre d'entrée dans le bloc RAM\_INFO indique le nombre de requête pouvant être géré simultanément par le cache. Lorsque ce bloc est plein, aucun nouvelle requête ne peut être accepté. + +Le nombre d'entrée de cette mémoire est délimité par les tailles des files QUEUE\_REQ et QEUEUE\_READ\_HIT. C'est à dire, la taille de RAM\_INFO doit être comprit entre :\\ +$[ max(\{size\_QUEUE\_REQ\}, \{size\_QUEUE\_READ\_HIT\}) ; \{size\_QUEUE\_REQ\} * \{size\_QUEUE\_READ\_HIT\} ]$ + +\subSection{Choix de la victime} + +Dans cette section nous allons expliquer l'algorithme de selection de la victime et les motiviations de ce choix. + +Le chemin entre un processeur et son cache est souvent le chemin critique d'en un processeur. Il passe par la combinatoire qui indique que le processeur demande un accès et fait un aller retour avec l'aquittement du cache de la requête. + +Nous avons vut que l'aquittement donner par le cache est dépendante du type et donc du contenu du cache. Suivant le protocole définit dans la figure \ref{CACHE_protocole}, l'aquittement d'une requête dépend de la validité de la victime. + +Pour des raisons de rapidité, nous avons décider d'implémenter un algorithme pseudo aléatoire. Par exemple un compteur de ASSOC bits ou un LFSR (Linear Feedback Shift Register) de ASSOC+1 bits (car dans un LFSR, la combinaison 0 n'est pas une combinaison valide). + +\subSection{Structure du pipeline} + +Dans cette sous section nous allons présenter succintement les étage de pipelines. Suivant le type de la requête, le temps de réponses minimal différe. Pour cela, nous posons N le nombre de cycle aller/retour jusqu'à la mémoire et M le temps nécessaire pour avoir une ligne de cache complète après réception du premier paquet. On considére M et N comme des temps moyens et les files interne comme étant vide. +\begin{description} +\item[Read - Hit : ] 2 cycles. +\item[Read - Miss : ] 3 + N + M cycles. +\item[Write : ] 4 + N cycles. +\item[Lock et Prefetch : ] 2 cycles. +\item[Invalidate et Flush : ] 2 cycles. +\end{description} + +\printgraphonly{CACHE_pipeline}{.8} + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/05_optimisation.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/05_optimisation.tex (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/05_optimisation.tex (revision 45) @@ -0,0 +1,73 @@ +\Section{Optimisation}\label{optimisation} + +Dans cette dernière section nous allons voir des optimisations que nous pouvons apporter à la structure actuelle du cache non bloquant. + +%\subSection{Pipeliner l'accès au cache}\label{pipeline} +%Nous avons vut que DCACHE.REQ\_ACK ne dépend pas que de l'état des FIFOs (donc disponible au début d'un cycle) mais également des requêtes entrantes (qui sont disponible en fin de cycle). Pour couper cette chaîne critique, nous pouvons pipeliner l'accès au port de requêtes ainsi que celui des réponses. +% +%\subsubSection{DCACHE\_RSP} +% +%Sur cette interface, les réponses sont maintenues par le cache jusqu'à ce que le processeur accepte la réponse. Pour cela, nous pouvons implémenter une simple barrière de pipeline. +% +%\subsubSection{DCACHE\_REQ} +% +%Sur cette interface, les requêtes ne sont pas maintenues par le processeur quand le cache n'accepte pas une requête. Cette spécification permet au processeur de choisir une autre requête si elle n'a pas été acceptée. (Nous rappelons qu'une requête n'est pas acceptée si la file de destination est pleine ou si une requête précedente a verrouillée la ligne.) +% +%Dans ce cas ajouter une barrière de pipeline va consommer la requête mais le cache va être dans l'imposibilité de l'accepter et va empêcher d'en choisir une autre. + +\subSection{RAM mono-port multi-banc}\label{mono-port} + +La mémoire la plus dense est de la mémoire mono-port, c'est à dire qu'à chaque cycle, la mémoire mono-port accepte soit une lecture, soit une écriture et non les deux. + +Jusqu'ici nous n'avons pas indiquer la façon d'implémenter les bancs mémoires des blocs RAM\_TAG, RAM\_DATA, RAM\_LOCK et RAM\_INFO. Pour les deux premiers blocs, il est important qu'ils soient le plus dense possible car il contiennent toute la logique et les informations du cache. + +Comme chaque interface des blocs de RAM est une interface fifo, elle intègre implicitement un contrôle de flux. Ceci rends les interfaces indépendantent de l'implémentation des blocs proprement dit. (Par exemple, le bloc RAM\_DATA peut être implémenté avec de la mémoire dual-port, dans ce cas les sorties d'aquittement sont toujours égals à 1). + +\printgraph{CACHE_implementation_monolithic}{0.7}{Implémentation monolitique d'un banc de registres} + +De plus, les blocs internes peuvent être implémentés de manières multibancs. Comme le montre la figure \ref{CACHE_implementation_multi-banc}, un banc de registre monolitique (voir figure \ref{CACHE_implementation_monolithic} (contenant tous les registres) peut être décomposé en deux bancs de registre ayant chacun la moitié des registres. Le premier peut avoir les registres d'adresse paire, le second les registres d'adresse impaire. + +\printgraph{CACHE_implementation_multi-banc}{0.7}{Implémentation multi-banc d'un banc de registres} + +Avec la stratégie multi-banc, nous pouvons également implémenter une stratégie de partage des ports. Comme le montre la figure \ref{CACHE_implementation_multi-banc_x2_mono-port}, un module combinatoire vérifie si les adresses de chaque port n'entre pas en conflit, c'est à dire que chaque port cible deux bancs differents. En cas de conflits, une priorité doit être choisit. Nous faisons le choix de priorité fixe, en avantageant les ports utiliser par la section {\bf SECTION\_DCACHE\_RSP} puis {\bf SECTION\_VCI\_RSP}, puis {\bf SECTION\_VCI\_REQ} et enfin {\bf SECTION\_DCACHE\_REQ}. + +Le tableau suivant montre les conflits d'accès au banc par rapport aux bits de poids fort de l'adresse : +\begin{center} +\begin{tabular}{cc|cc} + & & \multicolumn{2}{|c}{Port 1} \\ + & MSB & 0 & 1\\ +\hline +Port 0 & 0 & conflit & ok\\ + & 1 & ok & conflit\\ +\end{tabular} +\end{center} + +\printgraph{CACHE_implementation_multi-banc_x2_mono-port}{0.7}{Implémentation multi-banc mono-port (x2) d'un banc de registres} + +Avec 2 ports et 2 bancs d'un port, la probabilité de conflit et de 50\%. Afin de réduire cette probabilité, il suffit d'augmenter le nombre de banc. Dans une configuration à 4 bancs, la probabilité est de 25\%. Ceci peut être vut dans le tableau suivant : +\begin{center} +\begin{tabular}{cc|cccc} + & & \multicolumn{4}{|c}{Port 1} \\ + & MSB & 00 & 01 & 10 & 11 \\ +\hline +Port 0 & 00 & conflit & ok & ok & ok \\ + & 01 & ok & conflit& ok & ok \\ + & 10 & ok & ok & conflit& ok \\ + & 11 & ok & ok & ok & conflit\\ +\end{tabular} +\end{center} + +\printgraph{CACHE_implementation_multi-banc_x4_mono-port}{0.7}{Implémentation multi-banc (x4) mono-port d'un banc de registres} + +La seule condition pour implémenter des mémoires mono-port est de ne pas faire de conflits systhématique. C'est à dire que dans une même section, on ne doit pas utiliser deux ports avec la même adresse. + +Les blocs posant problème sont sont RAM\_TAG et RAM\_LOCK. Le premier accède deux fois au cache de TAG mais avec deux adresses différentes : l'adresse de la requête et l'adresse de la victime. Par contre pour le bloc RAM\_LOCK, il accède 3 fois à ce bloc pendant la section {\bf SECTION\_DCACHE\_REQ}, une fois avec l'adress de la requête, et deux fois avec l'adresse de la victime. + +Comme le bloc RAM\_LOCK est relativement petit (NB\_LINE x 3 bits), on peut ce permettre d'avoir plusieurs accès sur ces bancs. Sinon, nous pouvons toujours pipeliner l'accès et faire un bypass entre le contenu du banc de la barrière de pipeline et la nouvelle requête du processeur. %Nous pouvons voir cette technique implémenter dans le graphe \ref{CACHE_overview_mono-port} + + +%\printgraphonly{CACHE_overview_mono-port}{.8} + + +%\subSection{Signaux de contrôles} +%Dans cette section, nous allons voir les fonctions combinatoires permettant de gérer les différents signaux de contrôles Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/root.tex (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-cache-specification/fr/root.tex (revision 45) @@ -1,393 +1,6 @@ -\Section{Introduction} -\subSection{Motivations} -Les processeurs haute performance lancent plusieurs instructions, de manière non ordonnée et spéculativement. Un défaut de cache ne doit pas bloquer le processeur. Le cache doit être non blouqant, c'est à dire qu'il doit pouvoir accepter des requêtes venant du processeur pendant le traitement d'un MISS. +\input{\dirroot/01_introduction.tex} +\input{\dirroot/02_overview_partial.tex} +\input{\dirroot/03_problem.tex} +\input{\dirroot/04_overview_full.tex} +\input{\dirroot/05_optimisation.tex} -\subSection{Démarche du document} -Le document est accès en quatre parties : -\begin{itemize} -\item Section \ref{overview_partial} : dans un premier temps, nous allons présenter une architecture qui satisfait des requêtes courantes (lectures / écritures, succès / échec) sur des adresses non conflictuelles. Cette première architecture est utilisable dans la majorité des cas. -\item Section \ref{problem} : dans cette section, nous allons analyser des problèmes arrivant lors d'accès à des adresses conflictuelles, et/ou dans un environnement multi contexte. Pour chaque problème, nous proposons des solutions. -\item Section \ref{overview_full} : cette section est la synthèse des deux précedentes. Nous allons modifier l'architecture de départ afin d'apporter des solutions aux problèmes énumérés dans la section \ref{problem}. -\item Section \ref{description} : cette dernière section énumère les structures internes, ainsi que les automates de la solution retenue dans la section \ref{overview_full}. -\end{itemize} - -\subSection{Paramètres nécessaires} -\subsubSection{Paramètres interne du cache} - -\begin{center} - \begin{tabular}{|ll|ccc|} - \hline - Paramètres & & Min & Max & Pas \\ - \hline - Taille du mot & SIZE\_WORD & 32 bits & 64 bits & *2 \\ - Nombre de lignes par mot & NB\_WORD & 1 mot & 64 mots & *2 \\ - Nombre de lignes & NB\_LINE & 1 ligne & 1024 lignes & *2 \\ - Associativité & ASSOC & 1 banc de NB\_LINE lignes & NB\_LINE/16 bancs de 16 lignes & *2 \\ - Taille des files internes & SIZE\_QUEUE & 1 case & 64 cases & *2 \\ - \hline - \end{tabular} -\end{center} - -\subsubSection{Paramètres de l'interface cache / processeur} - -\begin{center} - \begin{tabular}{|ll|ccc|} - \hline - Paramètres & & Min & Max & Pas \\ - \hline - Taille d'une donnée & SIZE\_DATA & 32 bits & 64 bits & *2 \\ - Taille de l'adresse & SIZE\_ADDR & 32 bits & 64 bits & *2 \\ - Taille de l'identifiant du propriétaire & SIZE\_TRDID & 0 bits & 4 bits & +1 \\ - Taille de l'identifiant de transaction & SIZE\_PKTID & 0 bits & 4 bits & +1 \\ - \hline - \end{tabular} -\end{center} - -\subSection{Spécification} -\begin{itemize} -\item Write through (Les données sont à la fois écrite dans le bloc du cache et dans le bloc de la mémoire de niveau inférieur). -\item Write no allocate (Les échecs d'écriture n'affectent pas le cache, le bloc n'est modifié que dans le niveau mémoire inférieur). -\item Cache associatif (Le cache est découpé plusieurs banc et une ligne peut être placé dans n'importe quel banc.) -\item Non bloquant (Le cache permet d'avoir plusieurs requêtes en cours de résolution) -\item Le modèle de consistance mémoires du processeur est relachés (Nous permettons aux lectures et aux écritures de se lancer et de se terminer de manière non ordonnées.) -\end{itemize} - -\subSection{Hypothèse de travail} - -Nous allons supposer que le cache sera connecté à un processeur superscalaire d'ordre 4. Que le code exécuté contient 20\% de lectures et 10 \% d'écritures. Nous avons donc en moyenne 1 accès mémoire par cycle. -Si nous ciblons un cache ayant au minimum 90\% de réussites, nous obtenons alors les ratios suivants : -\begin{itemize} -\item 60 \% de lectures qui réussissent. -\item 30 \% d'écritures qui réussissent. -\item 6,6\% de lectures qui échouent. -\item 3,3\% d'écritures qui échouent. -\end{itemize} - -\Section{Vue d'ensemble - Modèle simplifié}\label{overview_partial} - -\printgraphonly{CACHE_overview_basic}{.8} - -Dans un premier temps, nous allons montrer un modèle qui satisfait les cas de requêtes courantes : read hit, write hit, read miss et write miss, sur des adresses non conflictuelles. - - -Afin de réaliser un cache non bloquant, nous avons séparé l'interface des requêtes, de l'interface des réponses. Pour cela, 4 automates gèrent les interfaces et la gestion des ressources. La micro-architecture du cache ce décompose comme suit : -\begin{itemize} -\item Quatre automates : - \begin{description} - \item[FSM\_DCACHE\_REQ :] Cet automate gère la consommation des requêtes provenant du cache et, suivant le type d'accès et la réussite de l'accès, l'écriture dans les blocs QUEUE\_REQ et QUEUE\_READ\_HIT - \item[FSM\_DCACHE\_RSP :] L'automate gère la consommation de réponses contenues dans la QUEUE\_RSP et s'occupe d'écrire les lignes chargés dans le cache. - \item[FSM\_VCI\_REQ :] L'automate s'occupe de consommer une requête contenue dans la QUEUE\_REQ (si la file n'est pas vide) et la lance sur l'interface VCI\_REQ (si l'interface n'est pas occupée). - \item[FSM\_VCI\_RSP :] L'automate s'occupe de consommer des réponses sur l'interface VCI\_RSP (si l'interface n'est pas occupée) et l'écrit dans  la file QUEUE\_RSP (si la file n'est pas pleine). - \end{description} -\item Trois files d'attentes : - \begin{description} - \item[QUEUE\_READ\_HIT :] Cette file d'attente s'occupe de transmettre le plus tôt possible les requêtes de lectures ayant fait un HIT. - \item[QUEUE\_REQ :] Cette file est utilisée comme tampon d'écriture et de requête de lecture ayant fait un miss. Elle attend leur envoi à la mémoire. - \item[QUEUE\_RSP :] La file est utilisée comme tampon pour les réponses provenant de la mémoire. - \end{description} -\item Trois blocs mémoires : - \begin{description} - \item[RAM\_TAG :] Contient les informations pouvant identifier les adresses contenues dans cette ligne de cache. Ce bloc est composé de ASSOC bancs de tailles identiques. - \item[RAM\_DATA :] Contient les données de la ligne de cache. Ce bloc est composé de ASSOC bancs de tailles identiques. - \item[RAM\_INFO :] Contient les informations relative aux requêtes pendantes. - \end{description} -\end{itemize} - -\subSection{Acheminement des requêtes} -Dans cette section, nous allons voir l'acheminement d'une requête suivant son type. - -\begin{description} -\item[Read - Hit :] La requête accède en parallèle aux RAM\_TAG et au RAM\_DATA. La donnée lue est écrite dans la RAM\_INFO, alors que le pointeur vers RAM\_INFO est sauvegardé dans le bloc QUEUE\_READ\_HIT. Ensuite la requête attend d'être sélectionnée par l'automate FSM\_DCACHE\_RSP, puis lit les informations à partir de la RAM\_INFO et est acheminée vers le port de réponse. -\item[Read - Miss :] La requête de lecture réalisant un miss, écrit les informations concernant la requête dans la RAM\_INFO. Le pointeur de RAM\_INFO sera écrit dans la QUEUE\_REQ. L'automate FSM\_VCI\_REQ va envoyer la requête sur le réseau VCI. La réponse reviendra par l'intermédiaire de l'automate FSM\_VCI\_RSP qui enregistre la ligne de cache en cours d'arrivée dans un tampon. Dès la réception de la fin de paquet, le tampon est enregistré dans la QUEUE\_RSP. L'identifiant de requête vci sera un index vers RAM\_INFO, c'est pour cela que lorsque l'automate FSM\_DCACHE\_REQ récupère une réponse dans la QUEUE\_RSP, elle peut retrouver les informations de la requêtes dans RAM\_INFO. -\item[Write - Hit :] La gestion d'un write hit est équivalent à celle d'un read-miss : lors de la requête les informations sont stockées dans la RAM\_INFO (ainsi que la donnée à écrire). Lors de la réponse, (à la différence d'un read-miss, il n'y a pas de retour de ligne) la donnée à écrire va l'être dans le bloc RAM\_DATA. -\item[Write - Miss :] Un échec d'écriture est équivalent à une réussite d'écriture mais sans mise à jour du cache. -\item[Lock et Prefetch :] Ce cache n'implémentant ces fonctionnalités et étant le dernier niveau de cache avant l'accès à l'interconnect, alors ces requêtes sont traitées comme étant des Read Hit (sans lecture du cache) -\item[Invalidate :] Ce cache étant le dernier niveau de cache avant l'accès à l'interconnect, il est transmis à l'interface des réponses au travers de la QUEUE\_READ\_HIT. Lors de la lecture de cette file, on va accéder au cache et mettre le bit valid de la ligne à 0 -\item[Flush :] Le cache étant un cache write through, il y a une cohérence entre le contenu du cache et le contenu de la mémoire. L'effet de cette commande est identique à une commande Invalidate. -\end{description} -Une petite remarque concernant le Write-Hit : - - Quel automate doit gérer la mise à jour du cache : FSM\_DCACHE\_REQ ou FSM\_DCACHE\_RSP? Le premier à l'avantage de rendre la modification de la ligne visible rapidement pour les autres requêtes. Or il faudra soit rajouter un nouveau port d'écriture aux bancs RAM\_TAG et RAM\_DATA, soit synchroniser les automates afin de partager le port d'écriture. Le deuxième cas à pour avantage de n'avoir qu'un seul port d'écriture. - -Nous optons pour la deuxième solution. Ce choix est également motiver pour uniformiser les solutions proposées pour les problèmes de consistances mémoires. - -\Section{Quelques problèmes du modèle simplifié}\label{problem} -Dans cette section, nous allons voir quelques problèmes fonctionnelle du modèle de base et nous allons présenter des solutions. - -\subSection{Requêtes multiples d'échec de lectures} -Supposons le cas où le processeur réalise une suite d'accès en lecture sur des adresses consécutives en mémoire. Par exemple le processeur demande l'adresse 0x100, 0x104, 0x108, 0x10C pour une taille de ligne de 4 mots et un nombre de ligne de 8 lignes. Si la première requête de lecture fait un miss, alors les 3 autres requêtes vont également échouer. - -Il y aura dans ce cas deux problèmes. Le premier étant l'émission, par le cache, de 4 demandes de lignes, alors qu'une seule requête est vraiment utile. Ce n'est pas un problème en soit, mais ceci nous amène au deuxième problème : si le cache n'est pas direct-map, dans ce cas les 4 lignes identiques vont être logées à plusieurs endroit dans le cache. -\begin{itemize} -\item {\it Le premier problème est causé par la non sauvegarde par le cache de l'historique des requêtes. } -\item {\it Le deuxième problème est causé par le non accès à la RAM\_TAG, au moment des réponses. } -\end{itemize} - -Il y a trois solutions pour remédier à ces problèmes : -\begin{enumerate} -\item Ajouter un port de lecture au TAG. Quand les réponses arrivent, il faut tester si la requête de lecture fait toujours un miss. Si ce n'est plus le cas, alors aucune mise à jour de cache sera effectué. - \begin{description} - \item[+ :] coût minimum si on implémente le banc de registre TAG par un banc de registres multi-bancs (mais synchronisation entre les automates FSM\_DCACHE\_REQ et FSM\_DCACHE\_RSP). - \item[- :] accès lecture de mémoire inutile, coût des miss plus long - \end{description} -\item Empêcher ce cas d'arriver en faisant l'allocation de la ligne lors de la requête. Pour cela, nous allons ajouter un bit dans le TAG : "valid\_data", ce bit est mis à 0 lors d'une requête et positionné à 1 lors de la réponse. On accepte une requête si (valid\_data = 1). - \begin{description} - \item[+ :] pas de duplication des requêtes inutile. - \item[- :] coûte 1 bit par ligne de cache, suppression d'une ligne de cache alors qu'elle pouvait encore être utile. Si la requête n'est pas accepté, le processeur peut croire que le cache est bloqué et dans ce cas, maintient la requête. - \end{description} -\item Empêcher ce cas d'arriver en verrouillant les index. Pour chaque index, on rajoute un bit de lock. Ce bit est positionné à 0 lors d'une requête qui fait MISS et remit à 1 lors de la réponse. On accepte une requête qui fait miss si lock[index] = 0 - \begin{description} - \item[+ :] pas de duplication des requêtes, par rapport à la solution précédente, on a pas supprimé une ligne encore utile. - \item[- :] coûte 1 bit par index. Avec l'augmentation de l'associativité, on va diminué le coût mais augmenter le nombre de ligne verrouiller. - \end{description} -\end{enumerate} - -Pour les deux dernières solutions, nous pouvons faire deux remarques : -\begin{itemize} -\item Au lieu de refuser les requêtes qui ne satisfont pas les conditions, nous pouvons les accepter et les indiquer comme "uncached". Ceci aura pour effet de ne pas mettre à jour le cache, d'accepter les requêtes et donc d'avoir les réponses rapidement (car lors d'un accès non caché, nous n'avons pas besoin de chercher une ligne entière). -\item DCACHE.REQ\_ACK ne dépend plus que de l'état des FIFOs (donc disponible au début d'un cycle) mais également des requêtes entrantes (qui sont disponible en fin de cycle). Pour couper cette chaîne critique, nous pouvons pipeliner les accès au port de requêtes. Pour plus d'information, voir la section \ref{pipeline} -\end{itemize} - -La différence principales entre les deux dernières solutions porte sur le nombre de ligne verrouiller. Donc sur le coût du vérrouillage mais engendre des pertes de performances lors d'un cache fortement associatif. De plus, la solution de verrouiller l'index n'oblige pas de faire l'allocation de la ligne de cache lors de la requête. Car la totalité de l'index est verrouillé, alors il ne peut avoir aucune miss. - -\subSection{Évincement précoce de ligne } - -Dans le cas d'un write HIT, lors de la requête, on détermine le numéro de ligne, et le numéro de banc où la donnée doit être écrite. L'écriture effective se fait lors de la réponse. La ligne cible peut pendant ce temps être évincer par une autre réponse (un Read MISS par exemple). -Les solutions apportés par ce problème sont presque les mêmes que pour le problème précèdent : -\begin{enumerate} -\item Ajouter un port d'écriture. Dans ce cas, l'écriture effective se fait lors de la requête. -\item Verrouillage des lignes : ceci va empêcher l'évincement de la ligne concerné par l'écriture. -\item Verrouillage des index : ceci va empêcher les évincements des lignes de cache. -\end{enumerate} - -\subSection{Gestion de la Cohérence et Consistance mémoire} - -Le système mémoire doit assurer la cohérence mémoire (détermine quelle valeur est renvoyé par une lecture) et la consistance mémoire (détermine quand une valeur écrite sera récupérée par une lecture). - -Les problèmes de cohérence mémoire ne survienne que dans le cas d'un environnement multiprocesseur ou avec des périphériques d'entrée/sortie. Nous n'aborderons pas ici les solutions matériels pour résoudre ce problème. Le problème pouvant être résolue de manière logicielle en effectuant la séquence suivante présenté dans le graphe \ref{CACHE_coherence_memoire} - -\printgraphonly{CACHE_coherence_memoire}{.8} - -Nous allons principalement nous intéresser aux problèmes de consistance mémoire. -Le problème est le suivant : le cache lance deux requêtes, une lecture et une écriture. Ces requêtes ciblent le même bloc mémoire. L'interconnect qui relie le cache au bloc mémoire ne garantie pas l'ordre des requêtes. (La norme VCI n'impose pas d'interconnect qui délivre les messages dans l'ordre). La lecture et l'écriture entre en compétition pour l'accès à la zone mémoire, et peuvent accéder à la zone mémoire dans un ordre différent que dans l'ordre d'émission - -Ce problème est amplifié par le fait qu'une demande de lecture va lire une ligne de cache entière, donc il y a également des dépendances si les deux adresses  sont dans la même ligne de cache et que l'un des deux accès est une lecture. - -Il y a 4 types de dépendances : -\begin{description} -\item[RaR (Read after Read) :] Il s'agit de deux lectures successives vers la même ligne de cache. -\item[WaW (Write after Write) :] Il s'agit de deux écritures successives vers la même adresse. -\item[WaR (Write after Read) :] Il s'agit d'une lecture suivit d'une écriture vers la même ligne de cache. -\item[RaW (Read after Write) :] Il s'agit d'une écriture suivit d'une lecture vers la même ligne de cache. -\end{description} - -En reprenant les 4 types de dépendances, nous allons voir comment ces dépendances sont gérées : -\begin{itemize} -\item Dans le cadre d'une dépendance RaR, le seul problème provoqué est le lancement de requête multiple de lecture faisant des miss. (voir la section concerné). -\item Du point de vue du processeur, dans le cadre d'exception précise, une écriture n'a le droit de modifier le contexte visible du programmeur que si les instructions avant l'écriture sont terminée. Dans ce cas, les dépendances WaR sont gérées par le processeur. -\item Les dépendances WaW peuvent être implicitement géré par le processeur si les writes sont bloquants (donc attendent une réponse du cache). Les performances sont alors fortement dégradées car un write aura le même coût qu'un read faisant un MISS dans tous les niveaux de la hiérarchie mémoire. Nous pouvons tout de même noter qu'un write bloquant permet d'avoir une exception précise. -\item Les dépendances RaW sont moins triviale : le cpu peut vérifier les cas de RaW sur la même adresse et bypasser l'accès au cache. Or comme les lectures lisent une ligne de cache entière, deux adresses peuvent être différentes mais cibler la même ligne de cache. -\end{itemize} - -Pour gérer ces différents problèmes, il y a deux solutions : -\begin{enumerate} -\item Gestion par le CPU : les écritures demandent des acquittement une fois que la mémoire à été mise à jour. Dans ce cas à tous moment le processeur peut savoir si une écriture est en cours d'éxècution. Les lectures peuvent être lancées s'il n'y a pas de dépendances au niveau ligne avec des écritures. De même entre deux lectures et écritures. Malheureusement cette méthode à la mauvaise propriété de saturer l'unité de mémoire avec des écritures lancées mais attendant leur écriture en mémoire. Ce problème de latence peut être diminué si l'acquittement des écritures se fait jusqu'au premier niveau de cache qui intègre des mécanismes de consistance mémoire. -\item Gestion par le Cache : les problèmes d'évincement précoce de ligne de cache sont du à des lectures qui évincent une ligne qui aurait du contenir le résultat d'une écriture. C'est donc une dépendance RaW car les deux adresses ont les même index. Donc nous pouvons réutiliser la solution pour les problèmes de consistance mémoire. La solution proposée içi reprend celle proposée pour les deux problèmes analysés aux sections précédentes : -\end{enumerate} - -\begin{tabular}{l|ll} -Cas & Action lors d'une requête du processeur & Action lors d'une réponse du bus \\ -\hline -Read Hit & Lecture de la donnée & Aucune réponse attendue \\ - & Pas de requête envoyée au bus & \\ -Read Miss & Allocation d'une ligne de cache & Écriture de la ligne et déverrouillage \\ - & Verrouillage & \\ -Write Hit & Verrouillage de la ligne de cache & Écriture de la ligne et déverrouillage \\ -Write Miss & Allocation d'une ligne de cache & Invalidation de la ligne (write no-allocate)\\ - & Verrouillage & \\ -\end{tabular} - -Dans la deuxième solution, aucune requête provenant du processeur n'est accepté si elle concerne une ligne de cache verrouillée. - -\subSection{Multi-Contexte } -Ce cache non bloquant doit pouvoir être utilisé dans un environnement multi-contexte (exécution en parallèle de plusieurs threads). L'implication du multi-contexte ne va pas modifier le comportement du cache (Car ce cache est physiquement indéxé et tagué). - -Le cache est optimisé pour utiliser les propriétés de localité spatiale et temporelle d'un programme. Avec le multi-contexte, le cache va être soumit à plusieurs flot qui ne sont pas dépendant entre eux. Ceci va entraîner des évincements de lignes en faveur d'un contexte, alors que la ligne victime pouvait être utilisée par un autre contexte. De plus, ceci va augmenter le phénomène décrit dans la section "Évincement précoce de ligne" : des écritures non encore finalisées vont voir leur lignes cibles évincées. - -\Section{Vue d'ensemble - Modèle complet}\label{overview_full} -Cette section à pour but de montrer les modifications par rapport au modèle de base. - -\printgraphonly{CACHE_overview}{.8} - -\subSection{Solution retenue} - -Nous allons maintenant modifier le modèle de base en vue d'intégrer la solution retenue. La solution consiste en l'implémentation des deux principaux mécanismes vut précédemment : l'allocation précoce de victime et le verrouillage de lignes. Ces solutions ont l'avantage de garder les structures déjà présente dual-port, et de régler simplement les problèmes de consistance mémoire. - -Pour cela, nous ajoutons un banc de registre, RAM\_LOCK, qui contiendra 3 bits par ligne : -\begin{itemize} -\item Valid : qui est le bit valid anciennement contenu dans la RAM\_TAG. -\item Lock\_by\_read : indique si une lecture est actuellement pendante. -\item Lock\_by\_write : indique si une écriture est actuellement pendante. -\end{itemize} - -Détaillons les différentes actions : - -\printgraphonly{CACHE_protocole}{.6} - -Le choix de la victime est réalisé lors de l'émission de la requête. Un read hit vérifie si une requête de lecture est en cours sur cette même ligne de cache. Si c'est le cas, alors la requête sera non cachée (donc ne mettra pas à jour le cache). -Dans le cas d'un write hit ou d'un read miss, la ligne de cache correspondant va être verrouillée. Il est à noter que dans le cas d'un write qui fait miss, le cache va allouer une ligne pour ce write. Comme le cache est write no allocate, la ligne va être invalidée lors de la réponse. - -Reprenons les différents dépendances entre requêtes mémoires : - -\begin{tabular}{l|ll} -Dépendance & Dépendance de ligne et adresse identique & Dépendance de ligne et adresse différente\\ -\hline -RaR & Bypass dans le processeur & Rend la deuxième lecture non cachée \\ -WaW & Géré par le processeur (mono contexte) & Pas de problème \\ -WaR & Géré par le processeur (mono contexte) & La lecture verrouille la ligne.\\ - & & L'écriture devra attendre la fin de la lecture\\ -RaW & Bypass dans le processeur & L'écriture verrouille la ligne.\\ - & & La lecture devra attendre la fin de l'écriture\\ -\end{tabular} - -\Section{Description détaillée}\label{description} - -\subSection{Structure interne} - -Pour chaque composant interne, les interfaces suivent le protocole fifo (le producteur possède une sortie VAL qui indique s'il a une requête valide et le consommateur possède une sortie ACK qui indique s'il peut accepter une transaction. Il y a une transaction si VAL et ACK sont tous les deux à 1 à la fin d'un cycle). L'avantage est qu'il est très facile de faire du contrôle de flux. - -Nous allons maintenant détailler les ressources internes du cache non bloquant : -\begin{itemize} -\item Trois files d'attentes : - \begin{description} - \item[QUEUE\_READ\_HIT :] Cette file d'attente s'occupe de transmettre le plus tôt possible les requêtes de lecture ayant fait un HIT. - \begin{description} - %\item {\it Valid : } Indique si l'entrée correspondante contient une donnée valide - \item {\it Index : } Index vers une entrée de RAM\_INFO - \end{description} - \printgraphonly{CACHE_bloc_QUEUE_READ_HIT}{.8} - \item[QUEUE\_REQ :] Cette file est utilisée comme tampon d'écriture et de requête de lecture ayant fait un miss. Elle attende leur envoie à la mémoire. - \begin{description} - %\item {\it Valid : } Indique si l'entrée correspondante contient une donnée valide - \item {\it Index : } Index vers une entrée de RAM\_INFO - \end{description} - \printgraphonly{CACHE_bloc_QUEUE_REQ}{.8} - \item[QUEUE\_RSP :] La file est utilisée comme tampon pour les réponses provenant de la mémoire. - \begin{description} - %\item {\it Valid :} Indique si l'entrée correspondante contient une donnée valide - \item {\it Index :} Index vers une entrée de RAM\_INFO - \item {\it Line :} Contient la donnée retournée par l'interface de réponse - \item {\it Error :} Indique si l'accès effectué à généré une erreur ou pas. - \end{description} - \printgraphonly{CACHE_bloc_QUEUE_RSP}{.8} - \end{description} -\item Trois blocs mémoires : - \begin{description} - \item[RAM\_TAG :] Contient les informations pouvant identifier les adresses contenus dans cette ligne de cache - \begin{description} - \item {\it Tag :} Numéro du tag correspondant à la ligne - \end{description} - \printgraphonly{CACHE_bloc_RAM_TAG}{.8} - \item[RAM\_DATA :] Contient les données de la ligne de cache - \begin{description} - \item {\it Line :} Contient la ligne de cache proprement dite - \end{description} - \printgraphonly{CACHE_bloc_RAM_DATA}{.8} - \item[RAM\_LOCK :] Contient les bits de gestions de dépendances - \begin{description} - \item {\it Valid :} Indique si la ligne correspondant contient une donnée valide - \item {\it Lock\_by\_read :} Si le bit est positionné, alors il existe une lecture pendante - \item {\it Lock\_by\_write :} Si le bit est positionné, alors il existe une écriture pendante - \end{description} - \printgraphonly{CACHE_bloc_RAM_LOCK}{.8} - \item[RAM\_INFO :] Contient les informations relative au requête pendante. Pour plus de détails voir la section \ref{RAM_INFO} - \begin{description} - \item {\it Valid :} Indique si l'entrée correspondante contient une donnée valide - \item {\it Trdid, Pktid :} Identifiant de la requête - \item {\it Address :} Adresse de la requête. Pour une identification rapide de la ligne concernée. - \item {\it Type :} Type de la requête - \item {\it Uncached :} Indique si la réponse doit modifier le cache - \item {\it Data :} Donnée (en cas d'écriture : DCACHE.REQ\_WDATA, en cas de lecture avec succès : contenu d'un mot de la ligne de cache) - \end{description} - \printgraphonly{CACHE_bloc_RAM_INFO}{.8} - \end{description} -\item Quatre automates : - \begin{description} - \item[FSM\_DCACHE\_REQ :] Cet automate gère la consommation des requêtes provenant du cache et, suivant le type d'accès et la réussite de l'accès, l'écriture dans les QUEUE\_REQ et QUEUE\_READ\_HIT - \printgraphonly{CACHE_automate-fsm_dcache_req}{1} - - \item[FSM\_DCACHE\_RSP :] L'automate gère la consommation de donnée de la QUEUE\_RSP et s'occupe d'écrire dans le cache les lignes chargées. - \printgraphonly{CACHE_automate-fsm_dcache_rsp}{.8} - \item[FSM\_VCI\_REQ :] L'automate s'occupe de consommer une donnée de QUEUE\_REQ (si la file n'est pas vide) et la lance sur l'interface VCI\_REQ (si l'interface n'est pas occupée). - \printgraphonly{CACHE_automate-fsm_vci_req}{.8} - \item[FSM\_VCI\_RSP :] L'automate s'occupe de consommer sur l'interface VCI\_RSP (si l'interface n'est pas occupée) et l'écrit dans  la file QUEUE\_RSP (si la file n'est pas pleine). - \printgraphonly{CACHE_automate-fsm_vci_rsp}{.8} - \end{description} -\end{itemize} - -\subSection{RAM\_INFO en détail}\label{RAM_INFO} -La RAM\_INFO contient les informations relative aux requêtes pendantes. Elle possède trois ports : 2 ports de lecture et 1 port d'écriture. -Le numéro de registre dans lequel est écrit les informations est enregistré dans les files QUEUE\_REQ, QUEUE\_RSP et QUEUE\_READ\_HIT. Ceci permet de ne pas dupliquer les informations. - -Pour cela, lors d'une transaction acceptée sur l'interface DCACHE\_REQ, il faut allouer un registre de la RAM\_INFO. La dés-allocation de ce registre aura lieu pendant une transaction acceptée sur l'interface DCACHE\_RSP. -Le numéro de registre sert également comme identifiant de requête lors d'une transaction VCI. (Le cycle de vie de cette identifiant garantie son unicité sur le réseau VCI) - -Nous pouvons noter alors que nous pouvons accepter une requête sur le l'interface DCACHE\_REQ si la file de destination n'est pas vide ET s'il y a encore une place de libre dans RAM\_INFO. - -%@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -Dans un premier temps, la taille de RAM\_INFO sera le nombre maximal de requêtes pendantes que le processeur peut admettre soit : \{nombre de contexte\} * \{taille de la load store queue\} (dans ce premier cas, RAM\_INFO n'a pas besoin de contenir le pktid et le trdid de la requête). De plus le nombre de port de lecture sera de 2. - -Les optimisations possibles sont : -\begin{itemize} -\item Diminution du nombre de registres : en pratique, la taille de RAM\_INFO devra être comprit entre max(\{taille de la QUEUE\_REQ\}, \{taille de la QUEUE\_READ\_HIT\}) et \{taille de la QUEUE\_REQ\} * \{taille de la QUEUE\_READ\_HIT\}. -\item Un seul port de lecture : implémentation multi-banc de RAM\_INFO. Pour la gestion de conflit, il faut utiliser la même priorité que pour le choix entre la QUEUE\_READ\_HIT et la QUEUE\_RSP. -\end{itemize} - -\printgraphonly{CACHE_implementation_RAM_INFO}{1} - -\subSection{Pipeliner l'accès au cache}\label{pipeline} -Nous avons vut que DCACHE.REQ\_ACK ne dépend pas que de l'état des FIFOs (donc disponible au début d'un cycle) mais également des requêtes entrantes (qui sont disponible en fin de cycle). Pour couper cette chaîne critique, nous pouvons pipeliner l'accès au port de requêtes ainsi que celui des réponses. - -\subsubSection{DCACHE\_RSP} - -Sur cette interface, les réponses sont maintenues par le cache jusqu'à ce que le processeur accepte la réponse. Pour cela, nous pouvons implémenter une simple barrière de pipeline. - -\subsubSection{DCACHE\_REQ} - -Sur cette interface, les requêtes ne sont pas maintenues par le processeur quand le cache n'accepte pas une requête. Cette spécification permet au processeur de choisir une autre requête si elle n'a pas été acceptée. (Nous rappelons qu'une requête n'est pas acceptée si la file de destination est pleine ou si une requête précedente a verrouillée la ligne.) - -Dans ce cas ajouter une barrière de pipeline va consommer la requête mais le cache va être dans l'imposibilité de l'accepter et va empêcher d'en choisir une autre. - -\subSection{Choix de la victime} -Pour la sélection des lignes à evincer, nous allons implémenter un algorithme pseudo aléatoire. -L'avantage de cet algorithme est de ne pas avoir besoin de sauvegarder un historique des accès. - -\subSection{RAM mono-port}\label{mono-port} - -La mémoire la plus dense est de la mémoire mono-port (soit une lecture, soit une écriture par cycle). - -Comme chaque interface des blocs de RAM ont une interface fifo, elle intègre donc un contrôle de flux. Ceci les rends indépendant du nombre de port intégrer dans chaque bloc mémoire. (Par exemple, un le bloc RAM\_DATA est implémenté avec de la mémoire dual-port, alors les sorties READ\_ACK et WRITE\_ACK seront toujours égals à 1). - -Néanmoins, nous devons prendre soin à ce que chaque étage du cache ne commande pas deux interfaces d'un même bloc RAM. Or dans la solution retenue, nous avons les blocs RAM\_TAG et RAM\_LOCK qui ont besoin de deux interfaces durant la partie DCACHE\_REQ. Pour cela nous devons réaliser une barrière de pipeline. - -Le premier étages va réaliser les lectures, alors que le second va mettre à jour ces bancs. Il est à noter qu'il va devoir avoir un bypass car comme la RAM\_LOCK ainsi que le bloc RAM\_TAG n'a pas encore été mis à jour, cette requête peut être suivit par une autre requête qui entre en conflit. - -Le graphe \ref{CACHE_overview_mono-port} montre les modifications à apporter au cache pour n'avoir qu'un port par étage. - -\printgraphonly{CACHE_overview_mono-port}{.8} - -\subSection{Structure du pipeline} - -Suivant le type d'une requête, le temps de réponse minimal n'est pas le même (On pose N le nombre de cycle aller retour jusqu'a la mémoire et M le temps pour avoir une ligne de cache complète) : -\begin{itemize} -\item Read - Hit : 2 cycles. -\item Read - Miss : 4 + N + M cycles. -\item Write : 5 + N cycles. -\item Lock et Prefetch : 2 cycles. -\item Invalidate et Flush : 2 cycles. -\end{itemize} - -\printgraphonly{CACHE_pipeline}{.8} - -%\subSection{Signaux de contrôles} -%Dans cette section, nous allons voir les fonctions combinatoires permettant de gérer les différents signaux de contrôles Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-file_source.sed =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-file_source.sed (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-file_source.sed (revision 45) @@ -16,5 +16,5 @@ %------------------------------------------------------------------------------ -\pagestyle{empty} +\pagestyle{plain} \begin{document} @@ -22,5 +22,4 @@ % Créez une page de titre \maketitle -\thispagestyle{empty} %Table des matières et des figures Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-style.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-style.sty (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-style.sty (revision 45) @@ -80,4 +80,5 @@ \centering \includegraphics[scale=#2]{\dirschema/#1.eps} + \caption{} \label{#1} \end{figure} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-Design_a_CPU_with_High_Performance_and_High_Configurability_on_FPGA =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-Design_a_CPU_with_High_Performance_and_High_Configurability_on_FPGA (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-Design_a_CPU_with_High_Performance_and_High_Configurability_on_FPGA (revision 45) @@ -0,0 +1,1 @@ +doc Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-morpheo-share_architectural_ressources_between_hardware_context =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-morpheo-share_architectural_ressources_between_hardware_context (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-morpheo-share_architectural_ressources_between_hardware_context (revision 45) @@ -0,0 +1,1 @@ +doc Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-cache-specification =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-cache-specification (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-cache-specification (revision 45) @@ -0,0 +1,1 @@ +doc Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-configuration_file_syntax =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-configuration_file_syntax (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-configuration_file_syntax (revision 45) @@ -0,0 +1,1 @@ +doc Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-interface_processor_cache =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-interface_processor_cache (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-interface_processor_cache (revision 45) @@ -0,0 +1,1 @@ +doc Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-methodology =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-methodology (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-methodology (revision 45) @@ -0,0 +1,1 @@ +doc Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-new_component =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-new_component (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-new_component (revision 45) @@ -0,0 +1,1 @@ +doc Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-overview =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-overview (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-morpheo-overview (revision 45) @@ -0,0 +1,1 @@ +doc Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-viewer-specification =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-viewer-specification (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/document-viewer-specification (revision 45) @@ -0,0 +1,1 @@ +doc Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/poster-jnrdm_2007 =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/poster-jnrdm_2007 (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/poster-jnrdm_2007 (revision 45) @@ -0,0 +1,1 @@ +poster Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-internal_seminary_overview =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-internal_seminary_overview (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-internal_seminary_overview (revision 45) @@ -0,0 +1,1 @@ +ppt Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-share_architectural_ressources_between_hardware_context =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-share_architectural_ressources_between_hardware_context (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-share_architectural_ressources_between_hardware_context (revision 45) @@ -0,0 +1,1 @@ +ppt Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile (revision 45) @@ -19,5 +19,5 @@ # Directory #-------------------------------------------------------------------------------- -VERSION = "1.2" # 2007/02/21 +VERSION = "1.3" # 2007/07/18 DIR_DOCUMENTATION = .. @@ -26,5 +26,5 @@ DIR_DOCUMENTS = Documents DIR_LANGUAGE = Language -DIR_TYPE = Type +DIR_TYPE = Info DIR_GRAPH = Graph DIR_SCHEMA = Schema @@ -63,5 +63,5 @@ all : help -doc : $(DIR_TEX) $(PNG_FILES) +doc : $(PNG_FILES) $(DIR_TEX) @ \ for file in $(ALL_FILES); do \ @@ -79,6 +79,6 @@ fi; \ done; \ - done; - @$(MAKE) doc_all + done; \ + $(MAKE) doc_all; doc_all : $(PDF_FILES) @@ -89,24 +89,25 @@ #-------------------------------------------------------------------------------- %.pdf : %.ps - @$(ECHO) "Génération du fichier $*.pdf" - @$(PS2PDF) $< $@ - @$(CP) $@ $(DIR_DOCUMENTATION) + @\ + $(ECHO) "Génération du fichier $*.pdf"; \ + $(PS2PDF) $< $@; \ + $(CP) $@ $(DIR_DOCUMENTATION); %.ps : %.dvi - @$(ECHO) "Génération du fichier $*.ps" - @$(DVIPS) -o $@ $< + @\ + $(ECHO) "Génération du fichier $*.ps"; \ + $(DVIPS) -o $@ $<; %.dvi : $(DIR_TEX)/%.tex - @$(ECHO) "Génération du fichier $*.dvi" - @#touch $(patsubst %.tex,%.ind,$<) - @$(LATEX_WITH_ENV) $< - @$(LATEX_WITH_ENV) $< > /dev/null - @#$(MAKEINDEX) $(patsubst %.tex,%.idx,$<) - @citation=`$(GREP) "citation" $*.aux`; \ - if $(TEST) -n "$$citation" ; then \ - $(BIBTEX) $* ; \ - fi - @$(LATEX_WITH_ENV) $< > /dev/null - @$(LATEX_WITH_ENV) $< > /dev/null + @\ + $(ECHO) "Génération du fichier $*.dvi"; \ + $(LATEX_WITH_ENV) $<; \ + $(LATEX_WITH_ENV) $< > /dev/null; \ + citation=`$(GREP) "citation" $*.aux`; \ + if $(TEST) -n "$$citation" ; then \ + $(BIBTEX) $* ; \ + fi; \ + $(LATEX_WITH_ENV) $< > /dev/null; \ + $(LATEX_WITH_ENV) $< > /dev/null; #-------------------------------------------------------------------------------- @@ -363,30 +364,37 @@ #-------------------------------------------------------------------------------- $(DIR_SCHEMA_EPS) : - @$(ECHO) "Make directory : $@" - @$(MKDIR) $@ + @\ + $(ECHO) "Make directory : $@"; \ + $(MKDIR) $@; $(DIR_SCHEMA_PNG) : - @$(ECHO) "Make directory : $@" - @$(MKDIR) $@ + @\ + $(ECHO) "Make directory : $@"; \ + $(MKDIR) $@; $(DIR_TEX) : - @$(ECHO) "Make directory : $@" - @$(MKDIR) $@ + @\ + $(ECHO) "Make directory : $@"; \ + $(MKDIR) $@; $(DIR_SCHEMA_PNG)/%.png : $(DIR_SCHEMA_EPS)/%.eps $(DIR_SCHEMA_PNG) - @$(ECHO) "Generate files : $*.png" -# @$(EPS2PNG) $< $@ - -$(DIR_SCHEMA_EPS)/%.eps : $(DIR_SCHEMA)/%.eps $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_PNG) - @$(ECHO) "Generate files : $*.eps" - @$(CP) $(DIR_SCHEMA)/$*.eps $(DIR_SCHEMA_EPS) - -$(DIR_SCHEMA_EPS)/%.eps : $(DIR_SCHEMA)/%.fig $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_PNG) - @$(ECHO) "Generate files : $*.eps" - @$(FIG2EPS) $< $@ - -$(DIR_SCHEMA_EPS)/%.eps : $(DIR_GRAPH)/%.p $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_PNG) - @$(ECHO) "Generate files : $*.eps" - @$(CD) $(DIR_GRAPH); $(GNUPLOT) $*.p + @\ + $(ECHO) "Generate files : $*.png"; \ + $(EPS2PNG) $< $@; + +$(DIR_SCHEMA_EPS)/%.eps : $(DIR_SCHEMA)/%.eps $(DIR_SCHEMA_EPS) + @\ + $(ECHO) "Generate files : $*.eps"; \ + $(CP) $(DIR_SCHEMA)/$*.eps $(DIR_SCHEMA_EPS); + +$(DIR_SCHEMA_EPS)/%.eps : $(DIR_SCHEMA)/%.fig $(DIR_SCHEMA_EPS) + @\ + $(ECHO) "Generate files : $*.eps"; \ + $(FIG2EPS) $< $@; + +$(DIR_SCHEMA_EPS)/%.eps : $(DIR_GRAPH)/%.p $(DIR_SCHEMA_EPS) + @\ + $(ECHO) "Generate files : $*.eps"; \ + $(CD) $(DIR_GRAPH); $(GNUPLOT) $*.p; #-------------------------------------------------------------------------------- @@ -395,13 +403,15 @@ clean : - @$(ECHO) "Delete temporary files "$(PWD) - @$(RM) $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_PNG) $(DIR_TEX) $(DIR_PACKAGE)/*.aux - @$(RM) $(DVI_FILES) $(PS_FILES) $(PDF_FILES) - @$(MAKE) clean_rec DIR_CLEAN=. + @\ + $(ECHO) "Delete temporary files "$(PWD); \ + $(RM) $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_PNG) $(DIR_TEX) $(DIR_PACKAGE)/*.aux; \ + $(RM) $(DVI_FILES) $(PS_FILES) $(PDF_FILES); \ + $(MAKE) clean_rec DIR_CLEAN=. ; #Clean recursive clean_rec : - @$(ECHO) "Delete temporary files in directory $(DIR_CLEAN)" - @$(RM) $(DIR_CLEAN)/*~ \ + @\ + $(ECHO) "Delete temporary files in directory $(DIR_CLEAN)"; \ + $(RM) $(DIR_CLEAN)/*~ \ $(DIR_CLEAN)/*.bak \ $(DIR_CLEAN)/*.aux \ @@ -418,7 +428,6 @@ $(DIR_CLEAN)/*.nav \ $(DIR_CLEAN)/*.snm \ - $(DIR_CLEAN)/missfont.log - @# The .bbl file is to be removed if "bibtex" is used. - @for files in `$(LS) $(DIR_CLEAN)`; do \ + $(DIR_CLEAN)/missfont.log; \ + for files in `$(LS) $(DIR_CLEAN)`; do \ if $(TEST) -d $(DIR_CLEAN)/$$files; \ then \ @@ -428,6 +437,7 @@ clean_all : clean - @$(ECHO) "Delete temporary files (all)" - @$(RM) $(DIR_DOCUMENTATION)/*.pdf + @\ + $(ECHO) "Delete temporary files (all)"; \ + $(RM) $(DIR_DOCUMENTATION)/*.pdf; #-------------------------------------------------------------------------------- @@ -436,16 +446,17 @@ help : - @$(ECHO) "Environnement to generate documents and presentations" - @$(ECHO) "Version : $(VERSION)" - @$(ECHO) "" - @$(ECHO) "List of rules :" - @$(ECHO) " * all : Cf rules \"help\"" - @$(ECHO) " * clean : Erase generate files" - @$(ECHO) " * clean_all : Erase all generate files" - @$(ECHO) " * delete : Erase all file and directory of a document" - @$(ECHO) " * doc : Generate all documents" - @$(ECHO) " * help : Print this message" - @$(ECHO) " * new : Create all file and directy for a new document" - @$(ECHO) " * rename : Rename a document" - @$(ECHO) " * view : List all document to view" - @$(ECHO) "" + @\ + $(ECHO) "Environnement to generate documents and presentations"; \ + $(ECHO) "Version : $(VERSION)"; \ + $(ECHO) ""; \ + $(ECHO) "List of rules :"; \ + $(ECHO) " * all : Cf rules \"help\""; \ + $(ECHO) " * clean : Erase generate files"; \ + $(ECHO) " * clean_all : Erase all generate files"; \ + $(ECHO) " * delete : Erase all file and directory of a document"; \ + $(ECHO) " * doc : Generate all documents"; \ + $(ECHO) " * help : Print this message"; \ + $(ECHO) " * new : Create all file and directy for a new document"; \ + $(ECHO) " * rename : Rename a document"; \ + $(ECHO) " * view : List all document to view"; \ + $(ECHO) ""; Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-cache-specification.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-cache-specification.sty (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-cache-specification.sty (revision 45) @@ -1,12 +1,12 @@ -\def\review{2007/07/11} +\def\review{2007/08/06} %\def\review{\number\day/\number\month/\number\year\xspace} \title{Cache de données associatif et non bloquant\\{\it Spécification}} -\author{} +\author{Mathieu Rosière} -\affiliation{Laboratoire d'Informatique de Paris VI - Equipe SOC - France} +\affiliation{Laboratoire d'Informatique de Paris VI - Equipe ALSOC - France} -\email{} +\email{mathieu.rosiere@lip6.fr} \date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_automate-fsm_dcache_req.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_automate-fsm_dcache_req.fig (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_automate-fsm_dcache_req.fig (revision 45) @@ -8,6 +8,4 @@ -2 1200 2 -5 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5362.500 2700.000 5550 2700 5250 2550 5250 2850 - 3 0 1.00 60.00 120.00 5 1 0 1 0 7 50 -1 -1 0.000 0 0 1 0 6525.000 4725.000 6450 4200 6900 4350 7050 4800 3 0 1.00 60.00 120.00 @@ -22,14 +20,14 @@ 5 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5175.000 4725.000 5250 4200 4800 4350 4650 4800 3 0 1.00 60.00 120.00 -5 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5362.500 3750.000 5550 3750 5250 3600 5250 3900 +5 1 0 1 0 7 50 -1 -1 0.000 0 0 1 0 6675.000 3675.000 6150 3750 6300 3300 6750 3150 3 0 1.00 60.00 120.00 -6 5175 3675 6525 4425 -1 1 0 1 0 11 50 -1 20 0.000 1 0.0000 5850 4050 600 300 5850 4050 6450 3750 -4 1 0 50 -1 2 8 0.0000 0 105 420 5850 4050 Request\001 --6 -6 5175 2625 6525 3375 -1 1 0 1 0 11 50 -1 20 0.000 1 0.0000 5850 3000 600 300 5850 3000 6450 2700 -4 1 0 50 -1 2 8 0.0000 0 90 210 5850 3000 Init\001 --6 +5 1 0 1 0 7 50 -1 -1 0.000 0 0 1 0 6525.000 3375.000 7050 3300 6900 3750 6450 3900 + 3 0 1.00 60.00 120.00 +5 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5850.000 3637.500 6000 3750 5850 3450 5700 3750 + 3 0 1.00 60.00 120.00 +5 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 4350.000 2587.500 4500 2700 4350 2400 4200 2700 + 3 0 1.00 60.00 120.00 +5 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 7350.000 2587.500 7500 2700 7350 2400 7200 2700 + 3 0 1.00 60.00 120.00 6 6675 4725 8025 5475 1 1 0 1 0 11 50 -1 20 0.000 1 0.0000 7350 5100 600 300 7350 5100 7950 4800 @@ -42,20 +40,34 @@ 4 1 0 50 -1 2 8 0.0000 0 105 780 4350 5025 QUEUE_REQ\001 -6 +6 5175 3675 6525 4425 +1 1 0 1 0 11 50 -1 20 0.000 1 0.0000 5850 4050 600 300 5850 4050 6450 3750 +4 1 0 50 -1 2 8 0.0000 0 105 420 5850 4050 Request\001 +-6 +6 3675 2625 5025 3375 +1 1 0 1 0 11 50 -1 20 0.000 1 0.0000 4350 3000 600 300 4350 3000 4950 2700 +4 1 0 50 -1 2 8 0.0000 0 90 210 4350 3000 Init\001 +-6 +1 1 0 1 0 11 50 -1 20 0.000 1 0.0000 7350 3000 600 300 7350 3000 7950 2700 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4800 3225 5400 3825 2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 6450 2550 6300 2775 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 5850 3300 5850 3750 -4 0 0 50 -1 0 8 0.0000 0 105 645 5925 3525 (3) : end_init\001 + 3450 3000 3750 3000 4 1 0 50 -1 0 8 0.0000 0 120 1230 7350 5850 (5) : queue_read_hit.full\001 4 2 0 50 -1 0 8 0.0000 0 120 1485 6675 5250 (6) : not(queue_read_hit.full)\001 4 1 0 50 -1 0 8 0.0000 0 120 990 4350 5850 (8) : queue_req.full\001 4 0 0 50 -1 0 8 0.0000 0 120 1245 5025 5100 (9) : not(queue_req.full)\001 -4 2 0 50 -1 0 8 0.0000 0 105 885 5175 3525 (10) : not(A or B)\001 -4 0 0 50 -1 0 8 0.0000 0 120 2430 3750 6300 A : ((read and miss) or write).request_queue.full\001 -4 1 0 50 -1 0 8 0.0000 0 105 810 6525 2475 (1) : not(nreset)\001 -4 1 0 50 -1 0 8 0.0000 0 105 900 5175 2475 (2) : not(end_init)\001 -4 0 0 50 -1 0 8 0.0000 0 120 3345 3750 6450 B : ((read and not (miss)) or (type_others)) and queue_read_hit.full\001 4 0 0 50 -1 0 8 0.0000 0 105 315 6975 4275 (4) : B\001 4 2 0 50 -1 0 8 0.0000 0 105 330 4725 4275 (7) : A\001 +4 2 0 50 -1 0 8 0.0000 0 105 645 4950 3525 (3) : end_init\001 +4 1 0 50 -1 2 8 0.0000 0 120 420 7350 3000 synchro\001 +4 1 0 50 -1 0 8 0.0000 0 105 900 4350 2325 (2) : not(end_init)\001 +4 1 0 50 -1 0 8 0.0000 0 105 885 5850 3300 (13) : not(A or B)\001 +4 0 0 50 -1 0 8 0.0000 0 120 1200 7125 3525 (12) : queue_info.empty\001 +4 1 0 50 -1 0 8 0.0000 0 120 1455 7350 2325 (11) : not(queue_info.empty)\001 +4 2 0 50 -1 0 8 0.0000 0 105 390 6600 3000 (10) : C\001 +4 0 0 50 -1 0 8 0.0000 0 120 2940 3750 6300 A : ((read and miss) or write).request_queue.full and not C\001 +4 0 0 50 -1 0 8 0.0000 0 120 3825 3750 6450 B : ((read and not (miss)) or (type_others)) and queue_read_hit.fulland not C\001 +4 0 0 50 -1 0 8 0.0000 0 120 1305 3750 6600 C : type = synchronisation\001 +4 2 0 50 -1 0 8 0.0000 0 105 810 3375 3000 (1) : not(nreset)\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_COUNTER.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_COUNTER.fig (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_COUNTER.fig (revision 45) @@ -0,0 +1,86 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +6 6150 3300 6750 3600 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 6750 3600 6150 3600 6150 3300 6750 3300 6750 3600 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3 + 6150 3300 6450 3600 6750 3300 +-6 +6 6150 2700 6750 3000 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 6750 3000 6150 3000 6150 2700 6750 2700 6750 3000 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3 + 6150 2700 6450 3000 6750 2700 +-6 +6 4050 3900 5700 5100 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 5700 3900 4050 3900 4050 4200 5700 4200 5700 3900 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 5250 3900 5250 4200 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 4800 3900 4800 4200 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 4050 4800 5700 4800 5700 5100 4050 5100 4050 4800 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 4800 4800 4800 5100 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 5250 4800 5250 5100 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5025 4200 5025 4800 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4425 4200 4425 4800 +4 1 0 50 -1 0 8 0.0000 0 90 180 4425 4050 Tag\001 +4 1 0 50 -1 0 8 0.0000 0 75 300 5025 4050 Index\001 +4 1 0 50 -1 0 8 0.0000 0 75 330 5475 4050 Offset\001 +4 1 0 50 -1 0 8 0.0000 0 90 180 4425 4950 Tag\001 +4 1 0 50 -1 0 8 0.0000 0 75 300 5025 4950 Index\001 +4 1 0 50 -1 0 8 0.0000 0 75 330 5475 4950 Offset\001 +-6 +1 3 0 1 0 7 50 -1 -1 0.000 1 0.0000 6600 2250 150 150 6600 2250 6750 2250 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 6750 3900 6150 3900 6150 4200 6750 4200 6750 3900 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3 + 6750 3900 6600 4050 6750 4200 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6450 3600 6450 3900 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 6450 4500 7050 4500 7050 3150 6600 3150 6600 3300 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6450 3000 6300 3300 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6600 2400 6600 2700 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 7050 3150 7050 1800 6600 1800 6600 2100 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6300 2400 6300 2700 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5850 1800 5850 2850 6150 2850 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5550 1800 5550 3450 6150 3450 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 6450 4200 6450 4500 5475 4500 5475 4800 +4 1 0 50 -1 0 8 0.0000 0 75 135 6600 2250 +1\001 +4 1 0 50 -1 0 8 0.0000 0 75 150 6300 2325 "0"\001 +4 0 0 50 -1 0 8 0.4363 0 120 1560 5550 1650 VCI_REQ_CPT_write_enable\001 +4 0 0 50 -1 0 8 0.4363 0 105 1155 5850 1650 VCI_REQ_CPT_reset\001 +4 0 0 50 -1 0 8 0.0000 0 105 840 7200 4050 VCI_REQ_CPT\001 +4 2 0 50 -1 0 8 0.0000 0 105 1230 3900 4050 DCACHE_REQ.address\001 +4 2 0 50 -1 0 8 0.0000 0 105 930 3900 4950 VCI_REQ.address\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_QUEUE_READ_HIT.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_QUEUE_READ_HIT.fig (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_QUEUE_READ_HIT.fig (revision 45) @@ -8,33 +8,38 @@ -2 1200 2 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 +6 3825 2925 7275 4725 +2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 4 + 4950 3450 6150 3450 6150 4350 4950 4350 +2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 2 + 5850 3450 5850 4350 +2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 2 + 5550 4350 5550 3450 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 3 3 0 1.00 60.00 120.00 - 4650 3600 4950 3600 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 + 4650 3150 5100 3150 5100 3450 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 3 3 0 1.00 60.00 120.00 - 4950 3750 4650 3750 -2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 4 - 4950 3450 6150 3450 6150 4650 4950 4650 -2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 2 - 5850 3450 5850 4650 -2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 2 - 5550 4650 5550 3450 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 6150 3600 6450 3600 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 6450 3750 6150 3750 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 3 - 3 0 1.00 60.00 120.00 - 4650 4275 4725 4275 4950 4275 + 6000 3450 6000 3150 6450 3150 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 6150 4275 6450 4275 -4 1 0 50 -1 2 8 0.0000 0 105 1185 5550 3375 QUEUE_READ_HIT\001 -4 2 0 50 -1 0 8 6.2832 0 90 630 4500 3750 WRITE_ack\001 -4 2 0 50 -1 0 8 6.2832 0 90 615 4500 3600 WRITE_val\001 -4 2 0 50 -1 0 8 6.2832 0 90 675 4500 4275 WRITE_num\001 -4 0 0 50 -1 0 8 6.2832 0 90 570 6600 3750 READ_ack\001 -4 0 0 50 -1 0 8 6.2832 0 90 555 6600 3600 READ_val\001 -4 0 0 50 -1 0 8 6.2832 0 90 615 6600 4275 READ_num\001 + 6150 3900 6450 3900 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4650 3900 4950 3900 +2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 0 0 2 + 4800 3825 4725 3975 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5100 4350 5100 4650 4650 4650 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6450 4650 6000 4650 6000 4350 +4 1 0 50 -1 2 8 0.0000 0 105 1185 5550 3000 QUEUE_READ_HIT\001 +4 2 0 50 -1 0 8 0.0000 0 90 615 4500 3150 WRITE_val\001 +4 0 0 50 -1 0 8 0.0000 0 90 555 6600 3150 READ_val\001 +4 2 0 50 -1 0 8 0.0000 0 90 675 4500 3900 WRITE_num\001 +4 0 0 50 -1 0 8 0.0000 0 90 615 6600 3900 READ_num\001 +4 2 0 50 -1 0 8 0.0000 0 105 420 4725 4125 [1:6] bits\001 +4 2 0 50 -1 0 8 0.0000 0 90 630 4500 4650 WRITE_ack\001 +4 0 0 50 -1 0 8 0.0000 0 90 570 6600 4650 READ_ack\001 +-6 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_QUEUE_REQ.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_QUEUE_REQ.fig (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_QUEUE_REQ.fig (revision 45) @@ -8,33 +8,36 @@ -2 1200 2 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 +2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 4 + 4950 5550 6150 5550 6150 6450 4950 6450 +2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 2 + 5850 5550 5850 6450 +2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 2 + 5550 6450 5550 5550 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 3 3 0 1.00 60.00 120.00 - 4650 3600 4950 3600 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 + 4650 5250 5100 5250 5100 5550 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 3 3 0 1.00 60.00 120.00 - 4950 3750 4650 3750 -2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 4 - 4950 3450 6150 3450 6150 4650 4950 4650 -2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 2 - 5850 3450 5850 4650 -2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 2 - 5550 4650 5550 3450 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 6150 3600 6450 3600 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 6450 3750 6150 3750 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 3 - 3 0 1.00 60.00 120.00 - 4650 4275 4725 4275 4950 4275 + 6000 5550 6000 5250 6450 5250 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 6150 4275 6450 4275 -4 2 0 50 -1 0 8 0.0000 0 90 630 4500 3750 WRITE_ack\001 -4 2 0 50 -1 0 8 0.0000 0 90 615 4500 3600 WRITE_val\001 -4 2 0 50 -1 0 8 0.0000 0 90 675 4500 4275 WRITE_num\001 -4 0 0 50 -1 0 8 0.0000 0 90 570 6600 3750 READ_ack\001 -4 0 0 50 -1 0 8 0.0000 0 90 555 6600 3600 READ_val\001 -4 0 0 50 -1 0 8 0.0000 0 90 615 6600 4275 READ_num\001 -4 1 0 50 -1 2 8 0.0000 0 105 780 5550 3375 QUEUE_REQ\001 + 6150 6000 6450 6000 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4650 6000 4950 6000 +2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 0 0 2 + 4800 5925 4725 6075 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5100 6450 5100 6750 4650 6750 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6450 6750 6000 6750 6000 6450 +4 2 0 50 -1 0 8 0.0000 0 90 615 4500 5250 WRITE_val\001 +4 0 0 50 -1 0 8 0.0000 0 90 555 6600 5250 READ_val\001 +4 2 0 50 -1 0 8 0.0000 0 90 675 4500 6000 WRITE_num\001 +4 0 0 50 -1 0 8 0.0000 0 90 615 6600 6000 READ_num\001 +4 2 0 50 -1 0 8 0.0000 0 105 420 4725 6225 [1:6] bits\001 +4 2 0 50 -1 0 8 0.0000 0 90 630 4500 6750 WRITE_ack\001 +4 0 0 50 -1 0 8 0.0000 0 90 570 6600 6750 READ_ack\001 +4 1 0 50 -1 2 8 0.0000 0 105 780 5550 5100 QUEUE_REQ\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_QUEUE_RSP.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_QUEUE_RSP.fig (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_QUEUE_RSP.fig (revision 45) @@ -8,49 +8,58 @@ -2 1200 2 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 +2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 4 + 4807 5556 6007 5556 6007 6456 4807 6456 +2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 2 + 5707 5556 5707 6456 +2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 2 + 5407 6456 5407 5556 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 3 3 0 1.00 60.00 120.00 - 4650 3600 4950 3600 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 + 4507 5256 4957 5256 4957 5556 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 3 3 0 1.00 60.00 120.00 - 4950 3750 4650 3750 -2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 4 - 4950 3450 6150 3450 6150 4650 4950 4650 -2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 2 - 5850 3450 5850 4650 -2 1 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 2 - 5550 4650 5550 3450 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 6150 3600 6450 3600 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 6450 3750 6150 3750 + 5857 5556 5857 5256 6307 5256 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 6150 4275 6450 4275 + 6007 6006 6307 6006 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4957 6456 4957 6756 4507 6756 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6307 6756 5857 6756 5857 6456 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 4650 4275 4950 4275 + 4507 5706 4807 5706 +2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 0 0 2 + 4657 5631 4582 5781 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 4650 4425 4950 4425 + 4507 6006 4807 6006 +2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 0 0 2 + 4657 5931 4582 6081 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 4650 4125 4950 4125 + 4507 6300 4807 6300 +2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 0 0 2 + 4650 6225 4575 6375 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 6150 4125 6450 4125 + 6007 5700 6307 5700 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 6150 4425 6450 4425 -4 2 0 50 -1 0 8 0.0000 0 90 630 4500 3750 WRITE_ack\001 -4 2 0 50 -1 0 8 0.0000 0 90 615 4500 3600 WRITE_val\001 -4 0 0 50 -1 0 8 0.0000 0 90 570 6600 3750 READ_ack\001 -4 0 0 50 -1 0 8 0.0000 0 90 555 6600 3600 READ_val\001 -4 1 0 50 -1 2 8 0.0000 0 105 750 5550 3375 QUEUE_RSP\001 -4 0 0 50 -1 0 8 0.0000 0 90 615 6600 4125 READ_num\001 -4 0 0 50 -1 0 8 0.0000 0 105 600 6600 4275 READ_line\001 -4 0 0 50 -1 0 8 0.0000 0 90 660 6600 4425 READ_error\001 -4 2 0 50 -1 0 8 0.0000 0 90 675 4500 4125 WRITE_num\001 -4 2 0 50 -1 0 8 0.0000 0 105 660 4500 4275 WRITE_line\001 -4 2 0 50 -1 0 8 0.0000 0 90 720 4500 4425 WRITE_error\001 + 6007 6300 6307 6300 +4 2 0 50 -1 0 8 0.0000 0 90 615 4357 5256 WRITE_val\001 +4 0 0 50 -1 0 8 0.0000 0 90 555 6457 5256 READ_val\001 +4 2 0 50 -1 0 8 0.0000 0 90 630 4357 6756 WRITE_ack\001 +4 0 0 50 -1 0 8 0.0000 0 90 570 6457 6756 READ_ack\001 +4 2 0 50 -1 0 8 0.0000 0 90 675 4357 5706 WRITE_num\001 +4 2 0 50 -1 0 8 0.0000 0 105 420 4575 5850 [1:6] bits\001 +4 2 0 50 -1 0 8 0.0000 0 105 660 4357 6006 WRITE_line\001 +4 2 0 50 -1 0 8 0.0000 0 90 720 4350 6300 WRITE_error\001 +4 2 0 50 -1 0 8 0.0000 0 90 225 4582 6456 1 bit\001 +4 2 0 50 -1 0 8 0.0000 0 105 660 4575 6150 [32:4096] bits\001 +4 0 0 50 -1 0 8 0.0000 0 90 615 6450 5700 READ_num\001 +4 0 0 50 -1 0 8 0.0000 0 90 660 6450 6300 READ_error\001 +4 0 0 50 -1 0 8 0.0000 0 105 600 6457 6006 READ_line\001 +4 1 0 50 -1 2 8 0.0000 0 105 750 5400 5100 QUEUE_RSP\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_RAM_DATA.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_RAM_DATA.fig (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_RAM_DATA.fig (revision 45) @@ -8,59 +8,55 @@ -2 1200 2 -6 6150 3525 7200 3825 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 6150 4650 6150 3450 4950 3450 4950 4650 6150 4650 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4650 4125 4950 4125 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4950 4575 4650 4575 2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 6450 3600 6150 3600 + 4650 3525 4950 3525 2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 6150 3750 6450 3750 -4 0 0 50 -1 0 8 0.0000 0 90 615 6525 3600 WRITE_val\001 -4 0 0 50 -1 0 8 0.0000 0 90 630 6525 3750 WRITE_ack\001 --6 -6 3975 3525 4950 3825 + 4950 3675 4650 3675 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4650 4350 4950 4350 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4650 3900 4950 3900 2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 4650 3600 4950 3600 + 6450 3525 6150 3525 2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 4950 3750 4650 3750 -4 2 0 50 -1 0 8 0.0000 0 90 555 4575 3600 READ_val\001 -4 2 0 50 -1 0 8 0.0000 0 90 570 4575 3750 READ_ack\001 --6 -6 6150 3975 7650 4650 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 5 + 6150 3675 6450 3675 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 6450 4425 6375 4425 6300 4425 6225 4425 6150 4425 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 5 + 6450 4575 6150 4575 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 6450 4575 6375 4575 6300 4575 6225 4575 6150 4575 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 5 + 6450 4275 6150 4275 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 6450 4275 6375 4275 6300 4275 6225 4275 6150 4275 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 5 - 3 0 1.00 60.00 120.00 - 6450 4125 6375 4125 6300 4125 6225 4125 6150 4125 -4 0 0 50 -1 0 8 0.0000 0 105 660 6525 4575 WRITE_line\001 -4 0 0 50 -1 0 8 0.0000 0 105 750 6525 4125 WRITE_index\001 -4 0 0 50 -1 0 8 0.0000 0 90 690 6525 4275 WRITE_bank\001 -4 0 0 50 -1 0 8 0.0000 0 105 1080 6525 4425 WRITE_byte_enable\001 --6 -2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 - 6150 4650 6150 3450 4950 3450 4950 4650 6150 4650 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 5 - 3 0 1.00 60.00 120.00 - 4650 4125 4725 4125 4800 4125 4875 4125 4950 4125 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 5 - 3 0 1.00 60.00 120.00 - 4650 4275 4725 4275 4800 4275 4875 4275 4950 4275 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 5 - 3 0 1.00 60.00 120.00 - 4950 4575 4875 4575 4800 4575 4725 4575 4650 4575 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 5 - 3 0 1.00 60.00 120.00 - 4650 4425 4725 4425 4800 4425 4875 4425 4950 4425 + 6450 3975 6150 3975 +4 2 0 50 -1 0 8 0.0000 0 105 510 4575 4575 REQ_data\001 +4 0 0 50 -1 0 8 0.0000 0 105 495 6525 4575 RSP_line\001 +4 2 0 50 -1 0 8 0.0000 0 105 465 4575 3525 REQ_val\001 +4 2 0 50 -1 0 8 0.0000 0 105 480 4575 3675 REQ_ack\001 +4 2 0 50 -1 0 8 0.0000 0 120 600 4575 3900 REQ_index\001 +4 2 0 50 -1 0 8 0.0000 0 105 540 4575 4125 REQ_bank\001 +4 2 0 50 -1 0 8 0.0000 0 105 930 4575 4350 REQ_byte_enable\001 +4 2 0 50 -1 0 8 0.0000 0 105 420 4800 4275 [0:4] bits\001 +4 2 0 50 -1 0 8 0.0000 0 105 480 4800 4050 [0:10] bits\001 +4 2 0 50 -1 0 8 0.0000 0 105 480 4800 4500 [4:14] bits\001 +4 2 0 50 -1 0 8 0.0000 0 105 570 4800 4725 {32;64} bits\001 +4 0 0 50 -1 0 8 0.0000 0 90 450 6525 3525 RSP_val\001 +4 0 0 50 -1 0 8 0.0000 0 90 465 6525 3675 RSP_ack\001 +4 0 0 50 -1 0 8 0.0000 0 90 525 6525 4275 RSP_bank\001 +4 0 0 50 -1 0 8 0.0000 0 105 585 6525 3975 RSP_index\001 +4 0 0 50 -1 0 8 0.0000 0 105 660 6300 4725 [32:4096] bits\001 4 1 0 50 -1 2 8 0.0000 0 105 720 5550 4050 RAM_DATA\001 -4 2 0 50 -1 0 8 0.0000 0 105 690 4575 4125 READ_index\001 -4 2 0 50 -1 0 8 0.0000 0 90 630 4575 4275 READ_bank\001 -4 2 0 50 -1 0 8 0.0000 0 90 600 4575 4575 READ_data\001 -4 2 0 50 -1 0 8 0.0000 0 105 1020 4575 4425 READ_byte_enable\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_RAM_LOCK.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_RAM_LOCK.fig (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_RAM_LOCK.fig (revision 45) @@ -8,31 +8,6 @@ -2 1200 2 -6 3975 3525 4950 3825 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 4650 3600 4950 3600 -2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 4950 3750 4650 3750 -4 2 0 50 -1 0 8 0.0000 0 90 555 4575 3600 READ_val\001 -4 2 0 50 -1 0 8 0.0000 0 90 570 4575 3750 READ_ack\001 --6 2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 6150 4650 6150 3450 4950 3450 4950 4650 6150 4650 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 5 - 3 0 1.00 60.00 120.00 - 4650 3975 4725 3975 4800 3975 4875 3975 4950 3975 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 5 - 3 0 1.00 60.00 120.00 - 4650 4125 4725 4125 4800 4125 4875 4125 4950 4125 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 5 - 3 0 1.00 60.00 120.00 - 4950 4425 4875 4425 4800 4425 4725 4425 4650 4425 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 5 - 3 0 1.00 60.00 120.00 - 4950 4575 4875 4575 4800 4575 4725 4575 4650 4575 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 5 - 3 0 1.00 60.00 120.00 - 4950 4275 4875 4275 4800 4275 4725 4275 4650 4275 2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 @@ -77,17 +52,54 @@ 3 0 1.00 60.00 120.00 5925 3150 5925 3300 5925 3375 5925 3450 -4 2 0 50 -1 0 8 0.0000 0 90 630 4575 4125 READ_bank\001 -4 2 0 50 -1 0 8 0.0000 0 105 690 4575 3975 READ_index\001 -4 2 0 50 -1 0 8 0.0000 0 105 645 4575 4275 READ_valid\001 -4 2 0 50 -1 0 8 0.0000 0 105 1080 4575 4425 READ_lock_by_read\001 -4 2 0 50 -1 0 8 0.0000 0 120 1140 4575 4575 READ_lock_by_write\001 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6450 3600 6150 3600 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6150 3750 6450 3750 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6450 3975 6150 3975 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6450 4125 6150 4125 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6150 4575 6450 4575 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6150 4275 6450 4275 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6150 4425 6450 4425 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4650 3600 4950 3600 +2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4950 3750 4650 3750 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4650 3975 4950 3975 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4650 4125 4950 4125 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4950 4575 4650 4575 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4950 4275 4650 4275 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4950 4425 4650 4425 4 1 0 50 -1 2 8 0.0000 0 105 720 5550 4050 RAM_LOCK\001 -4 2 0 50 -1 0 8 -0.7854 0 105 930 5025 3075 WRITE_REQ_val\001 -4 2 0 50 -1 0 8 -0.7854 0 105 945 5175 3075 WRITE_REQ_ack\001 -4 2 0 50 -1 0 8 -0.7854 0 120 1065 5475 3075 WRITE_REQ_index\001 -4 2 0 50 -1 0 8 -0.7854 0 105 1005 5625 3075 WRITE_REQ_bank\001 -4 2 0 50 -1 0 8 -0.7854 0 120 1020 5775 3075 WRITE_REQ_valid\001 -4 2 0 50 -1 0 8 -0.7854 0 105 1455 5925 3075 WRITE_REQ_lock_by_read\001 -4 2 0 50 -1 0 8 -0.7854 0 120 1515 6075 3075 WRITE_REQ_lock_by_write\001 +4 2 0 50 -1 0 8 5.4978 0 105 930 5025 3075 WRITE_REQ_val\001 +4 2 0 50 -1 0 8 5.4978 0 105 945 5175 3075 WRITE_REQ_ack\001 +4 2 0 50 -1 0 8 5.4978 0 120 1065 5475 3075 WRITE_REQ_index\001 +4 2 0 50 -1 0 8 5.4978 0 105 1005 5625 3075 WRITE_REQ_bank\001 +4 2 0 50 -1 0 8 5.4978 0 120 1020 5775 3075 WRITE_REQ_valid\001 +4 2 0 50 -1 0 8 5.4978 0 105 1455 5925 3075 WRITE_REQ_lock_by_read\001 +4 2 0 50 -1 0 8 5.4978 0 120 1515 6075 3075 WRITE_REQ_lock_by_write\001 4 2 0 50 -1 0 8 0.7854 0 90 915 5025 5100 WRITE_RSP_val\001 4 2 0 50 -1 0 8 0.7854 0 90 930 5175 5100 WRITE_RSP_ack\001 @@ -97,2 +109,16 @@ 4 2 0 50 -1 0 8 0.7854 0 105 1440 5925 5100 WRITE_RSP_lock_by_read\001 4 2 0 50 -1 0 8 0.7854 0 120 1500 6075 5100 WRITE_RSP_lock_by_write\001 +4 2 0 50 -1 0 8 0.0000 0 105 870 4575 3600 READ_REQ_val\001 +4 2 0 50 -1 0 8 0.0000 0 105 885 4575 3750 READ_REQ_ack\001 +4 2 0 50 -1 0 8 0.0000 0 120 1005 4575 3975 READ_REQ_index\001 +4 2 0 50 -1 0 8 0.0000 0 105 945 4575 4125 READ_REQ_bank\001 +4 2 0 50 -1 0 8 0.0000 0 120 960 4575 4275 READ_REQ_valid\001 +4 2 0 50 -1 0 8 0.0000 0 105 1395 4575 4425 READ_REQ_lock_by_read\001 +4 2 0 50 -1 0 8 0.0000 0 120 1455 4575 4575 READ_REQ_lock_by_write\001 +4 0 0 50 -1 0 8 6.2832 0 90 1080 6525 3600 READ_VICTIM_val\001 +4 0 0 50 -1 0 8 6.2832 0 90 1095 6525 3750 READ_VICTIM_ack\001 +4 0 0 50 -1 0 8 6.2832 0 105 1215 6525 3975 READ_VICTIM_index\001 +4 0 0 50 -1 0 8 6.2832 0 90 1155 6525 4125 READ_VICTIM_bank\001 +4 0 0 50 -1 0 8 6.2832 0 105 1170 6525 4275 READ_VICTIM_valid\001 +4 0 0 50 -1 0 8 6.2832 0 105 1605 6525 4425 READ_VICTIM_lock_by_read\001 +4 0 0 50 -1 0 8 6.2832 0 120 1665 6525 4575 READ_VICTIM_lock_by_write\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_coherence_memoire.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_coherence_memoire.fig (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_coherence_memoire.fig (revision 45) @@ -8,20 +8,22 @@ -2 1200 2 -5 1 0 1 0 7 50 -1 -1 0.000 0 1 0 0 5193.750 4050.000 4800 3675 4650 4050 4800 4425 5 1 0 1 0 7 50 -1 -1 0.000 0 1 0 0 5193.750 2700.000 4800 2325 4650 2700 4800 3075 5 1 0 1 0 7 50 -1 -1 0.000 0 1 0 0 5193.750 5100.000 4800 4725 4650 5100 4800 5475 +6 3600 3300 5100 4200 +5 1 0 1 0 7 50 -1 -1 0.000 0 1 0 0 5193.750 3750.000 4800 3375 4650 3750 4800 4125 +4 0 0 50 -1 0 12 0.0000 4 15 135 4950 3750 ...\001 +4 2 0 50 -1 0 12 0.0000 4 135 585 4500 3600 Access\001 +4 2 0 50 -1 0 12 0.0000 4 135 690 4500 4050 variables\001 +4 2 0 50 -1 0 12 0.0000 4 135 840 4500 3825 to a shared\001 +-6 4 0 0 50 -1 0 12 0.0000 4 135 375 4950 3300 Lock\001 4 0 0 50 -1 0 12 0.0000 4 135 600 4950 4650 UnLock\001 -4 0 0 50 -1 0 12 0.0000 4 15 135 4950 4050 ...\001 4 0 0 50 -1 0 12 0.0000 4 15 135 4950 2700 ...\001 4 0 0 50 -1 0 12 0.0000 4 15 135 4950 5100 ...\001 -4 2 0 50 -1 0 12 0.0000 4 135 585 4500 3900 Access\001 4 2 0 50 -1 0 12 0.0000 4 135 810 4500 2550 No access\001 4 2 0 50 -1 0 12 0.0000 4 135 810 4500 4950 No access\001 4 2 0 50 -1 0 12 0.0000 4 135 690 4500 3000 variables\001 -4 2 0 50 -1 0 12 0.0000 4 135 690 4500 4350 variables\001 -4 2 0 50 -1 0 12 0.0000 4 135 840 4500 4125 to a shared\001 4 2 0 50 -1 0 12 0.0000 4 135 840 4500 2775 to a shared\001 4 2 0 50 -1 0 12 0.0000 4 135 840 4500 5175 to a shared\001 4 2 0 50 -1 0 12 0.0000 4 135 690 4500 5400 variables\001 -4 0 0 50 -1 0 12 0.0000 4 180 2700 4950 3600 Flush (addressof shared variables)\001 +4 0 0 50 -1 0 12 0.0000 4 180 3945 4950 4350 Flush and Invalidation (address of shared variables)\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_RAM_INFO.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_RAM_INFO.fig (revision 44) +++ (revision ) @@ -1,39 +1,0 @@ -#FIG 3.2 -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -1 1 0 1 0 27 50 -1 20 0.000 1 0.0000 5550 4650 300 225 5550 4650 5850 4425 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 6450 4575 5850 4575 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 6450 4725 5850 4725 -2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 5550 4425 5550 4200 -2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 5550 4875 5550 5100 -2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 - 6150 5700 6150 5100 4350 5100 4350 5700 6150 5700 -2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 - 6150 4200 6150 3600 4350 3600 4350 4200 6150 4200 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 3 - 3 0 1.00 60.00 120.00 - 4050 4650 4950 4650 4950 4200 -2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 4950 4650 4950 5100 -4 1 0 50 -1 0 8 0.0000 0 75 510 5250 5400 bank - odd\001 -4 1 0 50 -1 0 8 0.0000 0 75 570 5250 3900 bank - even\001 -4 1 0 50 -1 0 8 0.0000 0 90 345 5550 4575 conflit\001 -4 1 0 50 -1 0 8 0.0000 0 75 300 5550 4725 check\001 -4 2 0 50 -1 0 8 0.0000 0 90 390 3975 4650 Write 0\001 -4 0 0 50 -1 0 8 0.0000 0 75 345 6525 4575 Read 0\001 -4 0 0 50 -1 0 8 0.0000 0 75 345 6525 4725 Read 1\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_monolithic.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_monolithic.fig (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_monolithic.fig (revision 45) @@ -0,0 +1,23 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +2 2 2 1 0 31 50 -1 -1 3.000 0 0 -1 0 0 5 + 6300 3450 4200 3450 4200 5850 6300 5850 6300 3450 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4050 4650 4350 4650 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6450 4650 6150 4650 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 6150 5700 6150 3600 4350 3600 4350 5700 6150 5700 +4 2 0 50 -1 0 8 0.0000 0 105 300 3975 4650 port 0\001 +4 0 0 50 -1 0 8 0.0000 0 105 300 6525 4650 port 1\001 +4 1 0 50 -1 0 8 0.0000 0 105 1125 5250 4875 (address even and odd)\001 +4 1 0 50 -1 0 8 0.0000 0 75 315 5250 4500 bank 0\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_multi-banc.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_multi-banc.fig (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_multi-banc.fig (revision 45) @@ -0,0 +1,33 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5550 4650 5550 5100 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 6150 5700 6150 5100 4350 5100 4350 5700 6150 5700 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 6150 4200 6150 3600 4350 3600 4350 4200 6150 4200 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4050 4650 4950 4650 4950 4200 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4950 4650 4950 5100 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6450 4650 5550 4650 5550 4200 +2 2 2 1 0 31 50 -1 -1 3.000 0 0 -1 0 0 5 + 6300 3450 4200 3450 4200 5850 6300 5850 6300 3450 +4 2 0 50 -1 0 8 0.0000 0 105 300 3975 4650 port 0\001 +4 0 0 50 -1 0 8 0.0000 0 105 300 6525 4650 port 1\001 +4 1 0 50 -1 0 8 0.0000 0 75 315 5250 5325 bank 1\001 +4 1 0 50 -1 0 8 0.0000 0 75 315 5250 3825 bank 0\001 +4 1 0 50 -1 0 8 0.0000 0 105 720 5250 4050 (address even)\001 +4 1 0 50 -1 0 8 0.0000 0 105 660 5250 5550 (address odd)\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_multi-banc_x2_mono-port.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_multi-banc_x2_mono-port.fig (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_multi-banc_x2_mono-port.fig (revision 45) @@ -0,0 +1,38 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +6 4875 4200 5625 5100 +1 1 0 1 0 27 50 -1 20 0.000 1 0.0000 5250 4650 300 225 5250 4650 5550 4425 +2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5250 4425 5250 4200 +2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5250 4875 5250 5100 +4 1 0 50 -1 0 8 0.0000 0 90 345 5250 4575 conflit\001 +4 1 0 50 -1 0 8 0.0000 0 75 300 5250 4725 check\001 +-6 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 6150 5700 6150 5100 4350 5100 4350 5700 6150 5700 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 6150 4200 6150 3600 4350 3600 4350 4200 6150 4200 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6450 4650 5550 4650 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4050 4650 4950 4650 +2 2 2 1 0 31 50 -1 -1 3.000 0 0 -1 0 0 5 + 4200 5850 6300 5850 6300 3450 4200 3450 4200 5850 +4 2 0 50 -1 0 8 0.0000 0 105 300 3975 4650 port 0\001 +4 0 0 50 -1 0 8 0.0000 0 105 300 6525 4725 port 1\001 +4 1 0 50 -1 0 8 0.0000 0 105 720 5250 4050 (address even)\001 +4 1 0 50 -1 0 8 0.0000 0 75 315 5250 3825 bank 0\001 +4 1 0 50 -1 0 8 0.0000 0 75 315 5250 5325 bank 1\001 +4 1 0 50 -1 0 8 0.0000 0 105 660 5250 5550 (address odd)\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_multi-banc_x4_mono-port.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_multi-banc_x4_mono-port.fig (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_implementation_multi-banc_x4_mono-port.fig (revision 45) @@ -0,0 +1,46 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +1 1 0 1 0 27 50 -1 20 0.000 1 0.0000 5250 4650 300 225 5250 4650 5550 4425 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6450 4650 5550 4650 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4050 4650 4950 4650 +2 2 2 1 0 31 50 -1 -1 3.000 0 0 -1 0 0 5 + 4200 5850 6300 5850 6300 3450 4200 3450 4200 5850 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 5100 4200 5100 3600 4350 3600 4350 4200 5100 4200 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 6150 4200 6150 3600 5400 3600 5400 4200 6150 4200 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 5100 5700 5100 5100 4350 5100 4350 5700 5100 5700 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 6150 5700 6150 5100 5400 5100 5400 5700 6150 5700 +2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5100 4875 4725 5100 +2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5400 4875 5775 5100 +2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5400 4425 5775 4200 +2 1 0 1 0 27 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5100 4425 4725 4200 +4 2 0 50 -1 0 8 0.0000 0 105 300 3975 4650 port 0\001 +4 0 0 50 -1 0 8 0.0000 0 105 300 6525 4725 port 1\001 +4 1 0 50 -1 0 8 0.0000 0 90 345 5250 4575 conflit\001 +4 1 0 50 -1 0 8 0.0000 0 75 300 5250 4725 check\001 +4 1 0 50 -1 0 8 0.0000 0 75 315 4725 3900 bank 0\001 +4 1 0 50 -1 0 8 0.0000 0 75 315 5775 3900 bank 2\001 +4 1 0 50 -1 0 8 0.0000 0 75 315 4725 5400 bank 1\001 +4 1 0 50 -1 0 8 0.0000 0 75 315 5775 5400 bank 3\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_overview-all.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_overview-all.fig (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_overview-all.fig (revision 45) @@ -0,0 +1,399 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +6 3900 4425 9000 6000 +6 3900 4425 9000 6000 +6 5850 5400 7050 6000 +2 2 0 1 0 27 200 -1 20 0.000 0 0 -1 0 0 5 + 5850 6000 7050 6000 7050 5400 5850 5400 5850 6000 +4 1 0 200 -1 3 8 0.0000 0 105 690 6450 5700 RAM_LOCK\001 +-6 +1 3 0 1 0 7 200 -1 0 3.000 1 0.0000 5475 5925 19 19 5475 5925 5456 5926 +1 3 0 1 0 7 200 -1 0 3.000 1 0.0000 7275 5775 19 19 7275 5775 7256 5776 +1 3 0 1 0 7 200 -1 0 3.000 1 0.0000 5550 5475 19 19 5550 5475 5531 5476 +2 1 0 1 0 7 200 -1 -1 3.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5850 5550 4275 5550 4275 4425 +2 1 0 1 0 7 200 -1 -1 3.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4125 4425 4125 5700 5850 5700 +2 1 0 1 0 7 200 -1 -1 3.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5850 5850 3975 5850 3975 4425 +2 1 0 1 0 7 200 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 9000 4500 9000 5625 7050 5625 +2 1 0 1 0 7 200 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5475 5925 5850 5925 +2 1 0 1 0 7 200 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5550 5475 5850 5475 +2 1 0 1 0 7 200 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7275 5775 7050 5775 +4 0 0 200 -1 0 6 0.0000 4 90 450 4350 5475 access_lock\001 +4 0 0 200 -1 0 6 0.0000 4 90 480 4200 5625 request_lock\001 +4 0 0 200 -1 0 6 0.0000 4 90 465 4050 5775 victim_lock\001 +4 2 0 200 -1 0 6 0.0000 4 90 480 8925 5550 respons_lock\001 +-6 +-6 +6 6900 3750 10500 6150 +6 9675 4275 10500 4950 +6 9900 4500 10500 4950 +1 1 0 1 0 7 101 -1 20 0.000 1 0.0000 10200 4725 225 150 10200 4725 10425 4575 +4 1 0 101 -1 0 8 0.0000 0 90 345 10200 4725 Victim\001 +-6 +2 1 0 1 0 7 101 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9975 4575 9675 4275 +-6 +2 1 0 1 0 7 101 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8700 3825 7050 3825 +2 1 0 1 0 7 101 -1 -1 4.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 7275 4875 7650 4875 7650 3975 7050 3975 +4 2 0 101 -1 0 6 0.0000 4 60 270 7200 6150 address\001 +-6 +6 2700 3900 7200 6300 +6 2700 4275 3525 4950 +6 2700 4500 3300 4950 +1 1 0 1 0 7 201 -1 20 0.000 1 0.0000 3000 4725 225 150 3000 4725 3225 4575 +4 1 0 201 -1 0 8 0.0000 0 90 345 3000 4725 Victim\001 +-6 +2 1 0 1 0 7 201 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3225 4575 3525 4275 +-6 +1 3 0 1 0 7 201 -1 0 3.000 1 0.0000 5475 3975 19 19 5475 3975 5456 3976 +2 1 0 1 0 7 201 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4425 3975 5850 3975 +2 1 0 1 0 7 201 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5475 3975 5475 6300 +4 2 0 201 -1 0 6 0.0000 4 75 540 7200 6150 address - bank\001 +4 2 0 201 -1 0 6 0.0000 4 60 255 5025 4050 victim\001 +-6 +6 6150 3150 6750 3450 +2 1 0 1 0 11 100 -1 20 0.000 0 0 -1 0 0 4 + 6150 3450 6750 3450 6750 3150 6150 3150 +2 1 0 1 0 11 100 -1 20 0.000 0 0 -1 0 0 2 + 6600 3150 6600 3450 +2 1 0 1 0 11 100 -1 20 0.000 0 0 -1 0 0 2 + 6450 3150 6450 3450 +-6 +6 3450 3450 4500 4425 +5 1 0 1 0 14 100 -1 -1 0.000 0 1 1 0 3975.000 4162.500 3825 4275 3975 4350 4125 4275 + 3 0 1.00 60.00 120.00 +5 1 0 1 0 14 100 -1 -1 0.000 0 1 1 0 4143.750 3900.000 4275 3975 4275 3825 4125 3750 + 3 0 1.00 60.00 120.00 +5 1 0 1 0 14 100 -1 -1 0.000 0 1 1 0 3806.250 3900.000 3825 3750 3675 3825 3675 3975 + 3 0 1.00 60.00 120.00 +1 3 0 1 0 14 100 -1 20 0.000 1 0.0000 3975 3675 150 150 3975 3675 4125 3675 +1 3 0 1 0 14 100 -1 20 0.000 1 0.0000 4275 4125 150 150 4275 4125 4425 4125 +1 3 0 1 0 14 100 -1 20 0.000 1 0.0000 3675 4125 150 150 3675 4125 3825 4125 +-6 +6 4500 6300 4800 6900 +6 4500 6300 4800 6900 +2 1 0 1 0 11 100 -1 20 0.000 0 0 -1 0 0 4 + 4500 6300 4500 6900 4800 6900 4800 6300 +2 1 0 1 0 11 100 -1 20 0.000 0 0 -1 0 0 2 + 4800 6750 4500 6750 +2 1 0 1 0 11 100 -1 20 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0 6 0.0000 4 75 345 4500 7950 val - ack\001 +4 2 0 100 -1 0 6 0.0000 4 75 150 8175 4800 line\001 +4 2 0 100 -1 0 6 0.0000 4 60 165 8100 3000 data\001 +4 2 0 100 -1 0 6 0.0000 4 45 180 8250 4500 error\001 +4 2 0 100 -1 0 6 0.0000 4 60 210 7800 6450 index\001 +4 2 0 100 -1 0 6 0.0000 4 60 210 5025 7125 index\001 +4 2 0 100 -1 0 8 0.0000 0 105 735 4425 6750 QUEUE_REQ\001 +4 0 0 100 -1 0 6 0.0000 4 75 345 4050 6975 val - ack\001 +4 0 0 100 -1 0 6 0.0000 4 75 345 3675 6525 val - ack\001 +4 0 0 100 -1 3 8 0.0000 0 105 690 8475 6750 QUEUE_RSP\001 +4 1 0 100 -1 3 8 0.0000 0 105 795 8250 2475 DCACHE_RSP\001 +4 1 0 100 -1 3 8 0.0000 0 105 825 4650 2550 DCACHE_REQ\001 +4 2 0 100 -1 3 8 0.0000 0 105 810 3450 7650 FSM_VCI_REQ\001 +4 2 0 100 -1 3 8 0.0000 0 105 1140 3450 3975 FSM_DCACHE_REQ\001 +4 0 0 100 -1 3 8 0.0000 0 105 780 9750 7650 FSM_VCI_RSP\001 +4 0 0 100 -1 3 8 0.0000 0 105 1110 9750 3975 FSM_DCACHE_RSP\001 +4 0 0 100 -1 0 6 0.0000 4 75 345 8625 3000 val - ack\001 +4 2 0 100 -1 0 6 0.0000 4 60 120 5400 3900 Hit\001 +4 0 0 100 -1 0 6 0.0000 4 75 180 5625 4350 bank\001 +4 1 0 100 -1 0 8 0.0000 0 105 540 5325 8400 VCI_REQ\001 +4 2 0 100 -1 0 6 0.0000 4 75 345 9375 6300 val - ack\001 +4 2 0 100 -1 0 6 0.0000 4 90 285 8700 4275 priority\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_overview_floor_plan.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_overview_floor_plan.fig (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_overview_floor_plan.fig (revision 45) @@ -0,0 +1,46 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 5250 6900 5250 6300 4050 6300 4050 6900 5250 6900 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 8850 6900 8850 6300 7650 6300 7650 6900 8850 6900 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 7050 3300 7050 2700 5850 2700 5850 3300 7050 3300 +2 4 0 1 0 27 50 -1 20 0.000 0 0 7 0 0 5 + 7050 6000 7050 5400 5850 5400 5850 6000 7050 6000 +2 4 0 1 0 27 50 -1 20 0.000 0 0 7 0 0 5 + 7050 5100 7050 4500 5850 4500 5850 5100 7050 5100 +2 4 0 1 0 27 50 -1 20 0.000 0 0 7 0 0 5 + 7050 4200 7050 3600 5850 3600 5850 4200 7050 4200 +2 4 0 1 0 13 50 -1 20 0.000 0 0 7 0 0 5 + 5250 6000 5250 2700 4050 2700 4050 6000 5250 6000 +2 4 0 1 0 13 50 -1 20 0.000 0 0 7 0 0 5 + 8850 6000 8850 2700 7650 2700 7650 6000 8850 6000 +2 4 0 1 0 27 50 -1 20 0.000 0 0 7 0 0 5 + 7050 6900 7050 6300 5850 6300 5850 6900 7050 6900 +2 4 0 1 0 13 50 -1 20 0.000 0 0 7 0 0 5 + 6150 8100 6150 7200 4050 7200 4050 8100 6150 8100 +2 4 0 1 0 13 50 -1 20 0.000 0 0 7 0 0 5 + 8850 8100 8850 7200 6750 7200 6750 8100 8850 8100 +4 1 0 50 -1 0 8 0.0000 0 105 1095 6450 2625 QUEUE_READ_HIT\001 +4 1 0 50 -1 0 8 0.0000 0 90 705 6450 3525 RAM_DATA\001 +4 1 0 50 -1 0 8 0.0000 0 90 615 6450 4425 RAM_TAG\001 +4 1 0 50 -1 0 8 0.0000 0 90 705 6450 5325 RAM_LOCK\001 +4 1 0 50 -1 0 8 0.0000 0 90 660 6450 6225 RAM_INFO\001 +4 1 0 50 -1 0 8 0.0000 0 105 840 4650 2550 DCACHE_REQ\001 +4 1 0 50 -1 0 8 0.0000 0 90 825 8250 2550 DCACHE_RSP\001 +4 1 0 50 -1 0 8 0.0000 0 105 735 4650 6600 QUEUE_REQ\001 +4 1 0 50 -1 0 8 0.0000 0 105 720 8250 6600 QUEUE_RSP\001 +4 1 0 50 -1 0 8 0.0000 0 90 855 7800 7650 FSM_VCI_RSP\001 +4 1 0 50 -1 0 8 0.0000 0 105 870 5100 7650 FSM_VCI_REQ\001 +4 1 0 50 -1 0 8 0.0000 0 105 540 5100 8400 VCI_REQ\001 +4 1 0 50 -1 0 8 0.0000 0 90 525 7800 8400 VCI_RSP\001 +4 1 0 50 -1 0 8 0.0000 0 105 1170 4650 4350 FSM_DCACHE_REQ\001 +4 1 0 50 -1 0 8 0.0000 0 90 1155 8250 4350 FSM_DCACHE_RSP\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_parameters.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_parameters.fig (revision 45) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_parameters.fig (revision 45) @@ -0,0 +1,75 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +6 4500 2850 5700 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 4500 2850 5700 2850 5700 4800 4500 4800 4500 2850 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 4500 3150 5700 3150 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 4500 3450 5700 3450 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 4500 4500 5700 4500 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 4500 4200 5700 4200 +-6 +6 6450 2850 7650 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 6450 2850 7650 2850 7650 4800 6450 4800 6450 2850 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 6450 3150 7650 3150 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 6450 3450 7650 3450 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 6450 4500 7650 4500 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 6450 4200 7650 4200 +-6 +6 4200 1800 6000 2550 +6 4200 1800 6000 2100 +2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 4200 2100 6000 2100 6000 1800 4200 1800 4200 2100 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2 + 4500 1800 4500 2100 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2 + 4800 1800 4800 2100 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2 + 5700 1800 5700 2100 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2 + 5400 1800 5400 2100 +4 1 0 50 -1 0 12 0.0000 4 15 135 5100 1950 ...\001 +-6 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4200 2250 6000 2250 +4 1 0 50 -1 0 8 0.0000 0 90 885 5100 2475 NB_WORD mots\001 +-6 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 7650 5100 4500 5100 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4200 2850 4200 4800 +2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2 + 4500 2850 4200 2550 +2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2 + 5700 2850 6000 2550 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4200 1650 4500 1650 +4 1 0 50 -1 0 12 0.0000 4 15 135 6075 3825 ...\001 +4 1 0 50 -1 0 12 0.0000 4 15 135 7050 3825 ...\001 +4 1 0 50 -1 0 12 0.0000 4 15 135 5100 3825 ...\001 +4 1 0 50 -1 0 8 0.0000 0 75 720 6075 5325 ASSOC bancs\001 +4 2 0 50 -1 0 8 0.0000 0 105 1290 4050 3825 NB_LINE/ASSOC lignes\001 +4 1 0 50 -1 0 8 0.0000 0 105 930 4350 1500 SIZE_WORD bits\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_pipeline.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_pipeline.fig (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_pipeline.fig (revision 45) @@ -8,45 +8,4 @@ -2 1200 2 -6 4500 3600 9300 4050 -2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 - 5100 3600 5100 4050 4500 4050 4500 3600 5100 3600 -2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 - 5700 3600 5700 4050 5100 4050 5100 3600 5700 3600 -2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 - 6300 3600 6300 4050 5700 4050 5700 3600 6300 3600 -2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 - 7500 3600 7500 4050 6300 4050 6300 3600 7500 3600 -2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 - 8700 3600 8700 4050 7500 4050 7500 3600 8700 3600 -2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 - 9300 3600 9300 4050 8700 4050 8700 3600 9300 3600 -4 1 0 50 -1 0 8 0.0000 0 75 345 4800 3750 dcache\001 -4 1 0 50 -1 0 8 0.0000 0 105 375 4800 3975 request\001 -4 1 0 50 -1 0 8 0.0000 0 105 330 5400 3750 update\001 -4 1 0 50 -1 0 8 0.0000 0 75 285 5400 3975 status\001 -4 1 0 50 -1 0 8 0.0000 0 75 225 6000 3750 VCI\001 -4 1 0 50 -1 0 8 0.0000 0 105 375 6000 3975 request\001 -4 1 0 50 -1 0 8 0.0000 0 90 750 6900 3825 memory access\001 -4 1 0 50 -1 0 8 0.0000 0 75 225 8100 3750 VCI\001 -4 1 0 50 -1 0 8 0.0000 0 90 375 8100 3975 respons\001 -4 1 0 50 -1 0 8 0.0000 0 75 345 9000 3750 dcache\001 -4 1 0 50 -1 0 8 0.0000 0 90 375 9000 3975 respons\001 --6 -6 8100 4200 8700 4650 -2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 - 8700 4200 8700 4650 8100 4650 8100 4200 8700 4200 -4 1 0 50 -1 0 8 0.0000 0 75 345 8400 4350 dcache\001 -4 1 0 50 -1 0 8 0.0000 0 90 375 8400 4575 respons\001 --6 -6 4500 3000 5700 3450 -2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 - 5100 3000 5100 3450 4500 3450 4500 3000 5100 3000 -2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 - 5700 3000 5700 3450 5100 3450 5100 3000 5700 3000 -4 1 0 50 -1 0 8 0.0000 0 75 345 4800 3150 dcache\001 -4 1 0 50 -1 0 8 0.0000 0 105 375 4800 3375 request\001 -4 1 0 50 -1 0 8 0.0000 0 75 345 5400 3150 dcache\001 -4 1 0 50 -1 0 8 0.0000 0 90 375 5400 3375 respons\001 --6 6 4500 5400 5700 5850 2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 @@ -62,28 +21,33 @@ 5100 4200 5100 4650 4500 4650 4500 4200 5100 4200 2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 - 5700 4200 5700 4650 5100 4650 5100 4200 5700 4200 -2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 - 6300 4200 6300 4650 5700 4650 5700 4200 6300 4200 -2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 - 7500 4200 7500 4650 6300 4650 6300 4200 7500 4200 -2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 - 8100 4200 8100 4650 7500 4650 7500 4200 8100 4200 -2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 5100 4800 5100 5250 4500 5250 4500 4800 5100 4800 2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 5700 4800 5700 5250 5100 5250 5100 4800 5700 4800 -2 1 0 1 0 29 50 -1 20 0.000 0 0 -1 0 0 2 - 5100 5025 5700 5025 +2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 + 5100 3600 5100 4050 4500 4050 4500 3600 5100 3600 +2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 + 5700 4200 5700 4650 5100 4650 5100 4200 5700 4200 +2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 + 6900 4200 6900 4650 5700 4650 5700 4200 6900 4200 +2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 + 7500 4200 7500 4650 6900 4650 6900 4200 7500 4200 +2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 + 5700 3600 5700 4050 5100 4050 5100 3600 5700 3600 +2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 + 6900 3600 6900 4050 5700 4050 5700 3600 6900 3600 +2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 + 8100 3600 8100 4050 6900 4050 6900 3600 8100 3600 +2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 + 8700 3600 8700 4050 8100 4050 8100 3600 8700 3600 +2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 + 5100 3000 5100 3450 4500 3450 4500 3000 5100 3000 +2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 + 5700 3000 5700 3450 5100 3450 5100 3000 5700 3000 +2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5 + 8100 4200 8100 4650 7500 4650 7500 4200 8100 4200 4 2 0 50 -1 0 8 0.0000 0 90 525 4200 3300 Read - Hit\001 4 2 0 50 -1 0 8 0.0000 0 90 600 4200 3900 Read - Miss\001 4 1 0 50 -1 0 8 0.0000 0 75 345 4800 4350 dcache\001 4 1 0 50 -1 0 8 0.0000 0 105 375 4800 4575 request\001 -4 1 0 50 -1 0 8 0.0000 0 105 330 5400 4350 update\001 -4 1 0 50 -1 0 8 0.0000 0 75 285 5400 4575 status\001 -4 1 0 50 -1 0 8 0.0000 0 75 225 6000 4350 VCI\001 -4 1 0 50 -1 0 8 0.0000 0 105 375 6000 4575 request\001 -4 1 0 50 -1 0 8 0.0000 0 90 750 6900 4425 memory access\001 -4 1 0 50 -1 0 8 0.0000 0 75 225 7800 4350 VCI\001 -4 1 0 50 -1 0 8 0.0000 0 90 375 7800 4575 respons\001 4 2 0 50 -1 0 8 0.0000 0 90 570 4200 4350 Write - Hit\001 4 2 0 50 -1 0 8 0.0000 0 90 645 4200 4575 Write - Miss\001 @@ -94,6 +58,24 @@ 4 2 0 50 -1 0 8 0.0000 0 75 255 4200 5550 Lock\001 4 2 0 50 -1 0 8 0.0000 0 75 450 4200 5775 Prefetch\001 -4 1 0 50 -1 0 8 0.0000 0 105 330 5400 4875 update\001 -4 1 0 50 -1 0 8 0.0000 0 90 375 5400 5250 respons\001 -4 1 0 50 -1 0 8 0.0000 0 75 345 5400 5175 dcache\001 -4 1 0 50 -1 0 8 0.0000 0 75 285 5400 4950 status\001 +4 1 0 50 -1 0 8 0.0000 0 75 345 5400 4950 dcache\001 +4 1 0 50 -1 0 8 0.0000 0 90 375 5400 5175 respons\001 +4 1 0 50 -1 0 8 0.0000 0 75 345 4800 3750 dcache\001 +4 1 0 50 -1 0 8 0.0000 0 105 375 4800 3975 request\001 +4 1 0 50 -1 0 8 0.0000 0 75 225 5400 4350 VCI\001 +4 1 0 50 -1 0 8 0.0000 0 105 375 5400 4575 request\001 +4 1 0 50 -1 0 8 0.0000 0 90 750 6300 4425 memory access\001 +4 1 0 50 -1 0 8 0.0000 0 75 225 7200 4350 VCI\001 +4 1 0 50 -1 0 8 0.0000 0 90 375 7200 4575 respons\001 +4 1 0 50 -1 0 8 0.0000 0 75 225 5400 3750 VCI\001 +4 1 0 50 -1 0 8 0.0000 0 105 375 5400 3975 request\001 +4 1 0 50 -1 0 8 0.0000 0 90 750 6300 3825 memory access\001 +4 1 0 50 -1 0 8 0.0000 0 75 225 7500 3750 VCI\001 +4 1 0 50 -1 0 8 0.0000 0 90 375 7500 3975 respons\001 +4 1 0 50 -1 0 8 0.0000 0 75 345 8400 3750 dcache\001 +4 1 0 50 -1 0 8 0.0000 0 90 375 8400 3975 respons\001 +4 1 0 50 -1 0 8 0.0000 0 75 345 4800 3150 dcache\001 +4 1 0 50 -1 0 8 0.0000 0 105 375 4800 3375 request\001 +4 1 0 50 -1 0 8 0.0000 0 75 345 5400 3150 dcache\001 +4 1 0 50 -1 0 8 0.0000 0 90 375 5400 3375 respons\001 +4 1 0 50 -1 0 8 0.0000 0 75 345 7800 4350 dcache\001 +4 1 0 50 -1 0 8 0.0000 0 90 375 7800 4575 respons\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_protocole.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_protocole.fig (revision 44) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_protocole.fig (revision 45) @@ -3,10 +3,19 @@ Center Inches -Letter -100.00 +A4 +96.00 Single -2 1200 2 -6 2625 3750 6525 4650 +6 9600 6150 10800 6450 +2 4 0 1 0 4 50 -1 20 0.000 0 0 7 0 0 5 + 9600 6450 9600 6150 10800 6150 10800 6450 9600 6450 +4 1 0 50 -1 0 8 0.0000 0 120 930 10200 6300 lock_by_write = 1\001 +-6 +6 9600 8700 10800 9000 +2 4 0 1 0 14 50 -1 20 0.000 0 0 7 0 0 5 + 9600 9000 9600 8700 10800 8700 10800 9000 9600 9000 +4 1 0 50 -1 0 8 0.0000 0 120 930 10200 8850 lock_by_write = 0\001 +-6 6 4275 3750 5550 4350 2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5 @@ -16,80 +25,87 @@ 4 0 0 50 -1 0 8 0.0000 0 60 120 5400 3975 no\001 -6 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 - 3 0 1.00 60.00 120.00 - 5400 4050 6450 4050 6450 4650 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 - 3 0 1.00 60.00 120.00 - 4500 4050 2700 4050 2700 4650 --6 -6 2625 6150 4275 7050 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 - 3 0 1.00 60.00 120.00 - 3000 6450 2700 6450 2700 7050 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 - 3 0 1.00 60.00 120.00 - 3900 6450 4200 6450 4200 7050 -2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5 - 3900 6450 3450 6150 3000 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0 50 -1 0 8 0.0000 0 60 120 9900 4875 no\001 -4 1 0 50 -1 0 8 0.0000 0 75 225 9450 4875 lock\001 -4 1 0 50 -1 0 8 0.0000 0 105 435 9450 5025 by read ?\001 --6 -6 9600 8100 10800 8400 -2 4 0 1 0 7 50 -1 20 0.000 0 0 7 0 0 5 - 9600 8400 9600 8100 10800 8100 10800 8400 9600 8400 -4 1 0 50 -1 0 8 0.0000 0 105 1005 10200 8250 write RAM_DATA\001 --6 -6 9600 6450 10800 8100 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 10200 6450 10200 6750 -2 4 0 1 0 7 50 -1 20 0.000 0 0 7 0 0 5 - 9600 7200 9600 6750 10800 6750 10800 7200 9600 7200 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 10200 7200 10200 7500 -2 4 0 1 0 7 50 -1 20 0.000 0 0 7 0 0 5 - 9600 7800 9600 7500 10800 7500 10800 7800 9600 7800 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 10200 7800 10200 8100 -4 1 0 50 -1 0 8 0.0000 0 90 420 10200 6900 write in \001 -4 1 0 50 -1 0 8 0.0000 0 105 735 10200 7125 QUEUE_REQ\001 -4 1 0 50 -1 0 8 0.0000 0 120 615 10200 7650 wait respons\001 --6 -6 10275 3750 11550 4350 -2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5 - 11400 4050 10950 3750 10500 4050 10950 4350 11400 4050 -4 1 0 50 -1 0 8 0.0000 0 90 240 10950 4050 Hit ?\001 -4 2 0 50 -1 0 8 0.0000 0 90 165 10500 3975 yes\001 -4 0 0 50 -1 0 8 0.0000 0 60 120 11400 3975 no\001 --6 -6 11100 6750 12300 7200 -2 4 0 1 0 7 50 -1 20 0.000 0 0 7 0 0 5 - 11100 7200 11100 6750 12300 6750 12300 7200 11100 7200 -4 1 0 50 -1 0 8 0.0000 0 105 735 11700 7125 QUEUE_REQ\001 -4 1 0 50 -1 0 8 0.0000 0 90 420 11700 6900 write in \001 --6 -6 11100 7500 12300 7800 -2 4 0 1 0 7 50 -1 20 0.000 0 0 7 0 0 5 - 11100 7800 11100 7500 12300 7500 12300 7800 11100 7800 -4 1 0 50 -1 0 8 0.0000 0 120 615 11700 7650 wait respons\001 --6 +4 1 0 50 -1 0 8 0.0000 0 90 720 9450 5025 read or write ?\001 +4 1 0 50 -1 0 8 0.0000 0 105 375 9450 4875 lock by\001 +-6 +6 2100 5550 3300 9300 +6 2100 5550 3300 5850 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 2100 5850 2100 5550 3300 5550 3300 5850 2100 5850 +4 1 0 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7 0 0 5 - 5100 5850 5100 5550 6300 5550 6300 5850 5100 5850 -2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 - 2850 5850 2850 5550 4050 5550 4050 5850 2850 5850 -2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 - 1350 5850 1350 5550 2550 5550 2550 5850 1350 5850 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 7950 2550 7950 2850 -4 1 0 50 -1 0 8 0.0000 0 105 585 3450 5700 req_ack = 1\001 -4 2 0 50 -1 0 8 0.0000 0 90 165 2250 4875 yes\001 -4 0 0 50 -1 0 8 0.0000 0 60 120 3150 4875 no\001 -4 1 0 50 -1 0 8 0.0000 0 75 225 2700 4875 lock\001 -4 1 0 50 -1 0 8 0.0000 0 120 495 2700 5025 by write ?\001 -4 1 0 50 -1 0 8 0.0000 0 105 585 1950 5700 req_ack = 0\001 -4 1 0 50 -1 0 8 0.0000 0 75 660 2700 7200 uncached = 1\001 -4 1 0 50 -1 0 8 0.0000 0 90 945 4200 7200 read RAM_DATA\001 + 11100 9150 11100 8550 12300 8550 12300 9150 11100 9150 4 1 0 50 -1 0 8 0.0000 0 105 255 7950 3150 Type\001 4 2 0 50 -1 0 8 0.0000 0 75 210 7500 3075 read\001 @@ -296,14 +277,14 @@ 4 1 0 50 -1 0 8 0.0000 0 105 585 11700 5700 req_ack = 1\001 4 1 0 50 -1 0 8 0.0000 0 75 195 7950 9450 End\001 -4 1 0 50 -1 0 8 0.0000 0 90 420 2700 7800 write in \001 -4 1 0 50 -1 0 8 0.0000 0 105 735 2700 8025 QUEUE_REQ\001 -4 1 0 50 -1 0 8 0.0000 0 120 615 2700 8550 wait respons\001 -4 1 0 50 -1 0 8 0.0000 0 90 240 6450 4875 valid\001 -4 1 0 50 -1 0 8 0.0000 0 90 390 6450 5025 victim ?\001 -4 0 0 50 -1 0 8 0.0000 0 60 120 6900 4875 no\001 -4 2 0 50 -1 0 8 0.0000 0 90 165 6000 4875 yes\001 -4 1 0 50 -1 0 8 0.0000 0 105 585 7200 5700 req_ack = 0\001 -4 1 0 50 -1 0 8 0.0000 0 105 585 5700 5700 req_ack = 1\001 -4 1 0 50 -1 0 8 0.0000 0 120 615 5700 7650 wait respons\001 -4 1 0 50 -1 0 8 0.0000 0 105 870 5700 8850 lock_by_read = 0\001 4 0 0 50 -1 0 8 0.0000 0 90 270 8400 3075 write\001 +4 1 0 50 -1 0 8 0.0000 0 105 285 7950 2400 Begin\001 +4 1 0 50 -1 0 8 0.0000 0 120 930 11700 6225 lock_by_write = 1\001 +4 2 0 50 -1 0 8 0.0000 0 90 165 9000 4875 yes\001 +4 0 0 50 -1 0 8 0.0000 0 60 120 9900 4875 no\001 +4 2 0 50 -1 0 8 0.0000 0 90 165 10500 3975 yes\001 +4 0 0 50 -1 0 8 0.0000 0 60 120 11400 3975 no\001 +4 1 0 50 -1 0 8 0.0000 0 90 240 10950 4050 Hit ?\001 +4 1 0 50 -1 0 8 0.0000 0 105 870 11700 6375 lock_by_read = 1\001 +4 1 0 50 -1 0 8 0.0000 0 105 870 11700 8850 lock_by_read = 0\001 +4 1 0 50 -1 0 8 0.0000 0 120 930 11700 8700 lock_by_write = 0\001 +4 1 0 50 -1 0 8 0.0000 0 105 645 11700 9000 invalide_line\001