Changeset 50 for trunk/IPs/systemC/processor
- Timestamp:
- Aug 17, 2007, 6:00:56 PM (17 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo
- Files:
-
- 15 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h
r15 r50 12 12 #include <string> 13 13 #include <iostream> 14 #include <sys/time.h> 14 15 15 16 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h" … … 24 25 void test (string name, 25 26 morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters param); 27 28 class Time 29 { 30 private : timeval time_begin; 31 // private : timeval time_end; 32 33 public : Time () 34 { 35 gettimeofday(&time_begin ,NULL); 36 }; 37 38 public : ~Time () 39 { 40 cout << *this; 41 }; 42 43 public : friend ostream& operator<< (ostream& output_stream, 44 const Time & x) 45 { 46 timeval time_end; 47 48 gettimeofday(&time_end ,NULL); 49 50 uint32_t nb_cycles = static_cast<uint32_t>(sc_simulation_time()); 51 52 double average = static_cast<double>(nb_cycles) / static_cast<double>(time_end.tv_sec-x.time_begin.tv_sec); 53 54 output_stream << nb_cycles << "\t(" << average << " cycles / seconds )" << endl; 55 56 return output_stream; 57 } 58 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp
r44 r50 7 7 */ 8 8 9 #define NB_ITERATION 32 10 9 11 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h" 10 12 #include "Common/include/Test.h" … … 31 33 } 32 34 33 RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic (name.c_str() ,35 RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic (name.c_str() 34 36 #ifdef STATISTICS 35 morpheo::behavioural::Parameters_Statistics(5,50),37 ,morpheo::behavioural::Parameters_Statistics(5,1000) 36 38 #endif 37 param);39 ,param); 38 40 39 41 #ifdef SYSTEMC … … 79 81 } 80 82 83 cout << "<" << name << "> Start Simulation ............" << endl; 84 Time * _time = new Time(); 85 81 86 /******************************************************** 82 87 * Simulation - Begin 83 88 ********************************************************/ 84 89 85 cout << "<" << name << "> Start Simulation ............" << endl;86 90 // Initialisation 87 91 … … 100 104 NRESET.write(1); 101 105 102 cout << "<" << name << "> Write the RegisterFile (no read)" << endl; 103 104 uint32_t grain = 0; 105 //uint32_t grain = static_cast<uint32_t>(time(NULL)); 106 107 srand(grain); 108 109 Tdata_t data, data_wait; 110 Taddress_t address = 0; 111 112 while (address < param._nb_word) 113 { 114 uint32_t num_port = 0; 115 116 cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; 117 118 while (num_port<param._nb_port_write) 106 107 for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++) 108 { 109 cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl; 110 111 // random init 112 uint32_t grain = 0; 113 //uint32_t grain = static_cast<uint32_t>(time(NULL)); 114 115 srand(grain); 116 117 Tdata_t tab [param._nb_word]; 118 119 for (uint32_t i=0; i<param._nb_word; i++) 120 tab[i]= rand()%(1<<(param._size_word-1)); 121 122 Taddress_t address_next = 0; 123 Taddress_t nb_ack = 0; 124 125 while (nb_ack < param._nb_word) 119 126 { 120 data = rand()%(1<<(param._size_word-1)); 121 122 cout << "(" << num_port << ") [" << address << "] <= " << data << endl; 123 WRITE_VAL [num_port] .write(1); 124 WRITE_DATA [num_port] .write(data); 125 WRITE_ADDRESS [num_port] .write(address); 126 127 address ++; 128 num_port ++; 129 // Address can be not a multiple of nb_port_write 130 if (address >= param._nb_word) 131 break; 127 cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; 128 129 for (uint32_t num_port=0; num_port < param._nb_port_write; num_port ++) 130 { 131 if ((address_next < param._nb_word) and 132 (WRITE_VAL [num_port].read() == 0)) 133 { 134 cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl; 135 136 WRITE_VAL [num_port] .write(1); 137 WRITE_DATA [num_port] .write(tab[address_next]); 138 WRITE_ADDRESS [num_port] .write(address_next++); 139 140 // Address can be not a multiple of nb_port_write 141 if (address_next >= param._nb_word) 142 break; 143 } 144 } 145 146 sc_start(1); 147 148 // reset write_val port 149 for (uint32_t num_port=0; num_port < param._nb_port_write; num_port ++) 150 { 151 if ((WRITE_ACK [num_port].read() == 1) and 152 (WRITE_VAL [num_port].read() == 1)) 153 { 154 WRITE_VAL [num_port] .write(0); 155 nb_ack ++; 156 } 157 } 158 159 sc_start(0); 132 160 } 133 134 while (num_port<param._nb_port_write) 161 162 address_next = 0; 163 nb_ack = 0; 164 165 cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl; 166 167 Tdata_t read_address [param._nb_port_read]; 168 169 while (nb_ack < param._nb_word) 135 170 { 136 WRITE_VAL [num_port] .write(0); 137 num_port ++; 171 cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; 172 173 for (uint32_t num_port=0; num_port < param._nb_port_read; num_port ++) 174 { 175 if ((address_next < param._nb_word) and 176 (READ_VAL [num_port].read() == 0)) 177 { 178 read_address [num_port] = address_next++; 179 180 READ_VAL [num_port].write(1); 181 READ_ADDRESS [num_port].write(read_address [num_port]); 182 183 if (address_next >= param._nb_word) 184 break; 185 } 186 } 187 188 sc_start(1); 189 190 // reset write_val port 191 for (uint32_t num_port=0; num_port < param._nb_port_read; num_port ++) 192 { 193 if ((READ_ACK [num_port].read() == 1) and 194 (READ_VAL [num_port].read() == 1)) 195 { 196 READ_VAL [num_port] .write(0); 197 198 cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl; 199 200 TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]); 201 nb_ack ++; 202 } 203 } 204 205 sc_start(0); 138 206 } 139 140 sc_start(1); 141 } 142 cout << "<" << name << "> Read the RegisterFile (no write)" << endl; 143 144 srand(grain); 145 146 for (uint32_t i=0; i<param._nb_port_write; i++) 147 WRITE_VAL [i] .write (0); 148 149 sc_start(1); 150 151 address = 0; 152 while (address < param._nb_word) 153 { 154 uint32_t num_port = 0; 155 156 cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; 157 158 while (num_port<param._nb_port_read) 159 { 160 READ_VAL [num_port] .write(1); 161 READ_ADDRESS [num_port] .write(address); 162 163 sc_start(0); // evaluation 164 165 data_wait = rand()%(1<<(param._size_word-1)); 166 data = READ_DATA [num_port] .read(); 167 168 cout << "(" << num_port << ") [" << address << "] => " << data << endl; 169 170 TEST(Tdata_t,data,data_wait); 171 172 address ++; 173 num_port ++; 174 if (address >= param._nb_word) 175 break; 176 } 177 178 while (num_port<param._nb_port_read) 179 { 180 READ_VAL [num_port] .write(0); 181 num_port ++; 182 } 183 184 sc_start(1); 185 } 186 187 for (uint32_t i=0; i<param._nb_port_read; i++) 188 READ_VAL [i] .write (0); 189 190 sc_start(1); 207 } 191 208 192 209 /******************************************************** … … 194 211 ********************************************************/ 195 212 213 TEST_STR(bool,true,true, "End of Simulation"); 214 delete _time; 196 215 cout << "<" << name << "> ............ Stop Simulation" << endl; 197 216 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags
r44 r50 6 6 7 7 #-----[ Simulator ]---------------------------------------- 8 SIMULATOR = systemcass 8 SIMULATOR = systemcass_deps 9 9 10 10 # 3 simulators : … … 16 16 FLAGS = -DSYSTEMC \ 17 17 -DVHDL \ 18 -DVHDL_TESTBENCH \19 -DVHDL_TESTBENCH_ASSERT \20 18 -DDEBUG=DEBUG_NONE 21 19 20 # -DVHDL_TESTBENCH \ 21 # -DSTATISTICS \ 22 # -DVHDL_TESTBENCH_ASSERT \ 22 23 # -DCONFIGURATION \ 23 # -DSTATISTICS \24 24 # -DPOSITION \ 25 25 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/include/test.h
r2 r50 13 13 #include <string> 14 14 #include <iostream> 15 #include <sys/time.h> 15 16 16 17 #include "Behavioural/@DIRECTORY/include/@COMPONENT.h" … … 23 24 24 25 void test (string name, 25 morpheo::behavioural::@NAMESPACE_USE::Parameters param); 26 morpheo::behavioural::@NAMESPACE_USE::Parameters * param); 27 28 class Time 29 { 30 private : timeval time_begin; 31 // private : timeval time_end; 32 33 public : Time () 34 { 35 gettimeofday(&time_begin ,NULL); 36 }; 37 38 public : ~Time () 39 { 40 cout << *this; 41 }; 42 43 public : friend ostream& operator<< (ostream& output_stream, 44 const Time & x) 45 { 46 timeval time_end; 47 48 gettimeofday(&time_end ,NULL); 49 50 uint32_t nb_cycles = static_cast<uint32_t>(sc_simulation_time()); 51 52 double average = static_cast<double>(nb_cycles) / static_cast<double>(time_end.tv_sec-x.time_begin.tv_sec); 53 54 output_stream << nb_cycles << "\t(" << average << " cycles / seconds )" << endl; 55 56 return output_stream; 57 } 58 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/src/main.cpp
r15 r50 40 40 try 41 41 { 42 morpheo::behavioural::@NAMESPACE_USE::Parameters param (//size_data, 43 //nb_port 44 ); 42 morpheo::behavioural::@NAMESPACE_USE::Parameters * param = new morpheo::behavioural::@NAMESPACE_USE::Parameters 43 (//size_data, 44 //nb_port 45 ); 45 46 46 cout << param .print(1);47 cout << param->print(1); 47 48 48 49 test (name,param); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/src/test.cpp
r44 r50 7 7 */ 8 8 9 #define NB_ITERATION 110 11 #define LABEL(str) do {cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; _@COMPONENT->vhdl_testbench_label(str);} while (0)12 13 9 #include "Behavioural/@DIRECTORY/SelfTest/include/test.h" 14 10 #include "Common/include/Test.h" 15 11 12 #define NB_ITERATION 1 13 #define CYCLE_MAX (128*NB_ITERATION) 14 15 #define LABEL(str) \ 16 { \ 17 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \ 18 } while(0) 19 20 #define SC_START(cycle) \ 21 do \ 22 { \ 23 if (static_cast<uint32_t>(sc_simulation_time()) > CYCLE_MAX) \ 24 { \ 25 TEST_KO("Maximal cycles Reached"); \ 26 } \ 27 sc_start(cycle); \ 28 } while(0) 29 16 30 void test (string name, 17 morpheo::behavioural::@NAMESPACE_USE::Parameters _param)31 morpheo::behavioural::@NAMESPACE_USE::Parameters * _param) 18 32 { 19 33 cout << "<" << name << "> : Simulation SystemC" << endl; … … 23 37 morpheo::behavioural::Parameters_Statistics(5,50), 24 38 #endif 25 _param);39 *_param); 26 40 27 41 #ifdef SYSTEMC … … 48 62 49 63 cout << "<" << name << "> Start Simulation ............" << endl; 64 Time * _time = new Time(); 50 65 51 66 /******************************************************** … … 60 75 srand(seed); 61 76 62 sc_start(0);77 SC_START(0); 63 78 LABEL("Initialisation"); 64 79 … … 69 84 LABEL("Iteration "+toString(iteration)); 70 85 71 sc_start(1);86 SC_START(1); 72 87 } 73 88 … … 76 91 ********************************************************/ 77 92 93 TEST_OK ("End of Simulation"); 94 delete _time; 78 95 cout << "<" << name << "> ............ Stop Simulation" << endl; 79 96 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/New_Component.h
r44 r50 100 100 #if VHDL 101 101 public : void vhdl (void); 102 private : void vhdl_declaration (Vhdl & vhdl);103 private : void vhdl_body (Vhdl & vhdl);102 private : void vhdl_declaration (Vhdl * & vhdl); 103 private : void vhdl_body (Vhdl * & vhdl); 104 104 #endif 105 105 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_allocation.cpp
r42 r50 22 22 23 23 Entity * entity = _component->set_entity (_name 24 ,"@COMPONENT" 24 25 #ifdef POSITION 25 ,"@COMPONENT"26 26 ,COMBINATORY 27 27 #endif … … 40 40 ); 41 41 42 in_CLOCK = interface->set_signal_clk ("clock" ,1, PORT_VHDL_YES_TESTBENCH_NO); 43 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1); 44 42 in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); 43 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); 45 44 46 45 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 50 49 #endif 51 50 52 Log_printf(FUNC,@COMPONENT,"allocation","End");51 log_printf(FUNC,@COMPONENT,"allocation","End"); 53 52 }; 54 53 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl.cpp
r42 r50 18 18 log_printf(FUNC,@COMPONENT,"vhdl","Begin"); 19 19 20 Vhdl vhdl (_name);20 Vhdl * vhdl = new Vhdl (_name); 21 21 22 22 _interfaces->set_port(vhdl); … … 26 26 vhdl_body (vhdl); 27 27 28 vhdl .generate_file();28 vhdl->generate_file(); 29 29 30 30 delete vhdl; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_body.cpp
r2 r50 13 13 @NAMESPACE_BEGIN 14 14 15 void @COMPONENT::vhdl_body (Vhdl & vhdl)15 void @COMPONENT::vhdl_body (Vhdl * & vhdl) 16 16 { 17 17 log_printf(FUNC,@COMPONENT,"vhdl_body","Begin"); 18 vhdl .set_body ("");18 vhdl->set_body (""); 19 19 log_printf(FUNC,@COMPONENT,"vhdl_body","End"); 20 20 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_declaration.cpp
r2 r50 13 13 @NAMESPACE_BEGIN 14 14 15 void @COMPONENT::vhdl_declaration (Vhdl & vhdl)15 void @COMPONENT::vhdl_declaration (Vhdl * & vhdl) 16 16 { 17 17 log_printf(FUNC,@COMPONENT,"vhdl_declaration","Begin"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Debug_component.h
r44 r50 2 2 #define DEBUG_COMPONENT_H 3 3 4 #define DEBUG_Behavioural true 5 #define DEBUG_Generic false 6 #define DEBUG_Counter false 7 #define DEBUG_Group false 8 #define DEBUG_Shifter false 9 #define DEBUG_Register_File false 10 #define DEBUG_RegisterFile_Monolithic false 11 #define DEBUG_RegisterFile_Multi_Banked false 12 #define DEBUG_RegisterFile_Multi_Banked_Glue false 13 #define DEBUG_Select false 14 #define DEBUG_Select_Priority_Fixed false 15 #define DEBUG_Victim false 16 #define DEBUG_Victim_Pseudo_LRU false 17 #define DEBUG_Stage_1_Ifetch false 18 #define DEBUG_Predictor false 19 #define DEBUG_Meta_Predictor false 20 #define DEBUG_Meta_Predictor_Glue false 21 #define DEBUG_Two_Level_Branch_Predictor false 22 #define DEBUG_Two_Level_Branch_Predictor_Glue false 23 #define DEBUG_Branch_History_Table false 24 #define DEBUG_Pattern_History_Table false 25 #define DEBUG_Stage_5_Execute false 26 #define DEBUG_Execution_cluster false 27 #define DEBUG_Execution_group false 28 #define DEBUG_Execution_unit false 4 #define DEBUG_Behavioural false 5 #define DEBUG_Generic false 6 #define DEBUG_Counter false 7 #define DEBUG_Group false 8 #define DEBUG_Shifter false 9 #define DEBUG_Register_File false 10 #define DEBUG_RegisterFile_Monolithic false 11 #define DEBUG_RegisterFile_Multi_Banked true 12 #define DEBUG_Select false 13 #define DEBUG_Select_Priority_Fixed false 14 #define DEBUG_Victim false 15 #define DEBUG_Victim_Pseudo_LRU false 16 #define DEBUG_Core false 17 #define DEBUG_Multi_Front_end false 18 #define DEBUG_Front_end false 19 #define DEBUG_Prediction_unit false 20 #define DEBUG_Direction false 21 #define DEBUG_Meta_Predictor false 22 #define DEBUG_Meta_Predictor_Glue false 23 #define DEBUG_Two_Level_Branch_Predictor false 24 #define DEBUG_Two_Level_Branch_Predictor_Glue false 25 #define DEBUG_Branch_History_Table false 26 #define DEBUG_Pattern_History_Table false 29 27 30 28 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters_Statistics.h
r2 r50 10 10 */ 11 11 12 #include "Common/include/Debug.h" 12 13 #include <stdint.h> 13 14 using namespace std; -
trunk/IPs/systemC/processor/Morpheo/Common/include/Test.h
r44 r50 26 26 }; 27 27 28 void test_ko (char * file, uint32_t line) 29 { 30 string msg = ("<"+toString(num_test)+"> : Test KO\n" + 31 " * Localisation\n" + 32 " - File : "+file+"\n" + 33 " - Line : "+toString(line)+"\n"); 34 35 throw (ErrorMorpheo (msg)); 36 }; 37 28 38 void test_ok () 29 39 { … … 42 52 }; 43 53 44 #define TEST(type,exp1,exp2) do { test<type> (exp1,exp2,__FILE__,__LINE__);} while(0) 45 #define TEST_STR(type,exp1,exp2,str...) do { fprintf(stdout,str); test<type> (exp1,exp2,__FILE__,__LINE__);} while(0) 54 #define TEST(type,exp1,exp2) do {test<type> (exp1,exp2,__FILE__,__LINE__);} while(0) 55 #define TEST_STR(type,exp1,exp2,str...) do {fprintf(stdout,str); fprintf(stdout,"\n"); test<type> (exp1,exp2,__FILE__,__LINE__);} while(0) 56 #define TEST_OK(str...) do {fprintf(stdout,str); fprintf(stdout,"\n"); test_ok();} while(0) 57 #define TEST_KO(str...) do {fprintf(stdout,str); fprintf(stdout,"\n"); test_ko(__FILE__,__LINE__);} while(0) 58 46 59 47 60 #endif -
trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_bloc_RAM_DATA.fig
r45 r50 10 10 2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 11 11 6150 4650 6150 3450 4950 3450 4950 4650 6150 4650 12 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 213 3 0 1.00 60.00 120.0014 4650 4125 4950 412515 12 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 1 2 16 13 3 0 1.00 60.00 120.00 … … 23 20 3 0 1.00 60.00 120.00 24 21 4950 3675 4650 3675 25 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 226 3 0 1.00 60.00 120.0027 4650 4350 4950 435028 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 229 3 0 1.00 60.00 120.0030 4650 3900 4950 390031 22 2 1 2 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 32 23 3 0 1.00 60.00 120.00 … … 44 35 3 0 1.00 60.00 120.00 45 36 6450 3975 6150 3975 37 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 38 3 0 1.00 60.00 120.00 39 4650 3825 4950 3825 40 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 41 3 0 1.00 60.00 120.00 42 4650 3975 4950 3975 43 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 44 3 0 1.00 60.00 120.00 45 4650 4275 4950 4275 46 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 47 3 0 1.00 60.00 120.00 48 4650 4125 4950 4125 49 2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 50 3 0 1.00 60.00 120.00 51 4650 4425 4950 4425 46 52 4 2 0 50 -1 0 8 0.0000 0 105 510 4575 4575 REQ_data\001 47 53 4 0 0 50 -1 0 8 0.0000 0 105 495 6525 4575 RSP_line\001 48 54 4 2 0 50 -1 0 8 0.0000 0 105 465 4575 3525 REQ_val\001 49 55 4 2 0 50 -1 0 8 0.0000 0 105 480 4575 3675 REQ_ack\001 50 4 2 0 50 -1 0 8 0.0000 0 120 600 4575 3900 REQ_index\00151 4 2 0 50 -1 0 8 0.0000 0 105 540 4575 4125 REQ_bank\00152 4 2 0 50 -1 0 8 0.0000 0 105 930 4575 4350 REQ_byte_enable\00153 4 2 0 50 -1 0 8 0.0000 0 105 420 4800 4275 [0:4] bits\00154 4 2 0 50 -1 0 8 0.0000 0 105 480 4800 4050 [0:10] bits\00155 4 2 0 50 -1 0 8 0.0000 0 105 480 4800 4500 [4:14] bits\00156 56 4 2 0 50 -1 0 8 0.0000 0 105 570 4800 4725 {32;64} bits\001 57 57 4 0 0 50 -1 0 8 0.0000 0 90 450 6525 3525 RSP_val\001 … … 61 61 4 0 0 50 -1 0 8 0.0000 0 105 660 6300 4725 [32:4096] bits\001 62 62 4 1 0 50 -1 2 8 0.0000 0 105 720 5550 4050 RAM_DATA\001 63 4 2 0 50 -1 0 8 0.0000 0 120 600 4575 3825 REQ_index\001 64 4 2 0 50 -1 0 8 0.0000 0 105 480 4800 3900 [0:10] bits\001 65 4 2 0 50 -1 0 8 0.0000 0 105 540 4575 3975 REQ_bank\001 66 4 2 0 50 -1 0 8 0.0000 0 105 420 4800 4050 [0:4] bits\001 67 4 2 0 50 -1 0 8 0.0000 0 105 930 4575 4275 REQ_byte_enable\001 68 4 2 0 50 -1 0 8 0.0000 0 105 615 4575 4125 REQ_offset\001 69 4 2 0 50 -1 0 8 0.0000 0 105 420 4800 4200 [0:4] bits\001 70 4 2 0 50 -1 0 8 0.0000 0 105 450 4575 4425 REQ_rw\001 71 4 2 0 50 -1 0 8 0.0000 0 105 450 4800 4350 {4;8} bits\001
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