Changeset 55 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest
- Timestamp:
- Sep 24, 2007, 2:00:35 PM (17 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration.cfg
r23 r55 1 1 RegisterFile_Monolithic 2 2 8 *2 # nb_port_read 3 1 4 *2 # nb_port_write 4 32 256 *2 # nb_word 2 0 0 *2 # nb_port_read 3 0 0 *2 # nb_port_write 4 1 8 *2 # nb_port_read_write 5 32 32 *2 # nb_word 5 6 32 32 *2 # size_word -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h
r50 r55 24 24 25 25 void test (string name, 26 morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters param);26 morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * param); 27 27 28 28 class Time -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info
r23 r55 5 5 target_dep RegisterFile_Monolithic_0.prj RegisterFile_Monolithic_0_Pack.vhdl RegisterFile_Monolithic_0.vhdl 6 6 7 # RegisterFile_Monolithic_108 target_dep all RegisterFile_Monolithic_10.ngc9 target_dep RegisterFile_Monolithic_10.ngc RegisterFile_Monolithic_10.prj10 target_dep RegisterFile_Monolithic_10.prj RegisterFile_Monolithic_10_Pack.vhdl RegisterFile_Monolithic_10.vhdl11 12 # RegisterFile_Monolithic_1113 target_dep all RegisterFile_Monolithic_11.ngc14 target_dep RegisterFile_Monolithic_11.ngc RegisterFile_Monolithic_11.prj15 target_dep RegisterFile_Monolithic_11.prj RegisterFile_Monolithic_11_Pack.vhdl RegisterFile_Monolithic_11.vhdl16 17 # RegisterFile_Monolithic_1218 target_dep all RegisterFile_Monolithic_12.ngc19 target_dep RegisterFile_Monolithic_12.ngc RegisterFile_Monolithic_12.prj20 target_dep RegisterFile_Monolithic_12.prj RegisterFile_Monolithic_12_Pack.vhdl RegisterFile_Monolithic_12.vhdl21 22 # RegisterFile_Monolithic_1323 target_dep all RegisterFile_Monolithic_13.ngc24 target_dep RegisterFile_Monolithic_13.ngc RegisterFile_Monolithic_13.prj25 target_dep RegisterFile_Monolithic_13.prj RegisterFile_Monolithic_13_Pack.vhdl RegisterFile_Monolithic_13.vhdl26 27 # RegisterFile_Monolithic_1428 target_dep all RegisterFile_Monolithic_14.ngc29 target_dep RegisterFile_Monolithic_14.ngc RegisterFile_Monolithic_14.prj30 target_dep RegisterFile_Monolithic_14.prj RegisterFile_Monolithic_14_Pack.vhdl RegisterFile_Monolithic_14.vhdl31 32 # RegisterFile_Monolithic_1533 target_dep all RegisterFile_Monolithic_15.ngc34 target_dep RegisterFile_Monolithic_15.ngc RegisterFile_Monolithic_15.prj35 target_dep RegisterFile_Monolithic_15.prj RegisterFile_Monolithic_15_Pack.vhdl RegisterFile_Monolithic_15.vhdl36 37 # RegisterFile_Monolithic_1638 target_dep all RegisterFile_Monolithic_16.ngc39 target_dep RegisterFile_Monolithic_16.ngc RegisterFile_Monolithic_16.prj40 target_dep RegisterFile_Monolithic_16.prj RegisterFile_Monolithic_16_Pack.vhdl RegisterFile_Monolithic_16.vhdl41 42 # RegisterFile_Monolithic_1743 target_dep all RegisterFile_Monolithic_17.ngc44 target_dep RegisterFile_Monolithic_17.ngc RegisterFile_Monolithic_17.prj45 target_dep RegisterFile_Monolithic_17.prj RegisterFile_Monolithic_17_Pack.vhdl RegisterFile_Monolithic_17.vhdl46 47 # RegisterFile_Monolithic_1848 target_dep all RegisterFile_Monolithic_18.ngc49 target_dep RegisterFile_Monolithic_18.ngc RegisterFile_Monolithic_18.prj50 target_dep RegisterFile_Monolithic_18.prj RegisterFile_Monolithic_18_Pack.vhdl RegisterFile_Monolithic_18.vhdl51 52 # RegisterFile_Monolithic_1953 target_dep all RegisterFile_Monolithic_19.ngc54 target_dep RegisterFile_Monolithic_19.ngc RegisterFile_Monolithic_19.prj55 target_dep RegisterFile_Monolithic_19.prj RegisterFile_Monolithic_19_Pack.vhdl RegisterFile_Monolithic_19.vhdl56 57 7 # RegisterFile_Monolithic_1 58 8 target_dep all RegisterFile_Monolithic_1.ngc 59 9 target_dep RegisterFile_Monolithic_1.ngc RegisterFile_Monolithic_1.prj 60 target_dep RegisterFile_Monolithic_1.prj RegisterFile_Monolithic_10_Pack.vhdl RegisterFile_Monolithic_10.vhdl RegisterFile_Monolithic_11_Pack.vhdl RegisterFile_Monolithic_11.vhdl RegisterFile_Monolithic_12_Pack.vhdl RegisterFile_Monolithic_12.vhdl RegisterFile_Monolithic_13_Pack.vhdl RegisterFile_Monolithic_13.vhdl RegisterFile_Monolithic_14_Pack.vhdl RegisterFile_Monolithic_14.vhdl RegisterFile_Monolithic_15_Pack.vhdl RegisterFile_Monolithic_15.vhdl RegisterFile_Monolithic_16_Pack.vhdl RegisterFile_Monolithic_16.vhdl RegisterFile_Monolithic_17_Pack.vhdl RegisterFile_Monolithic_17.vhdl RegisterFile_Monolithic_18_Pack.vhdl RegisterFile_Monolithic_18.vhdl RegisterFile_Monolithic_19_Pack.vhdl RegisterFile_Monolithic_19.vhdl RegisterFile_Monolithic_1_Pack.vhdl RegisterFile_Monolithic_1.vhdl 61 62 # RegisterFile_Monolithic_20 63 target_dep all RegisterFile_Monolithic_20.ngc 64 target_dep RegisterFile_Monolithic_20.ngc RegisterFile_Monolithic_20.prj 65 target_dep RegisterFile_Monolithic_20.prj RegisterFile_Monolithic_20_Pack.vhdl RegisterFile_Monolithic_20.vhdl 66 67 # RegisterFile_Monolithic_21 68 target_dep all RegisterFile_Monolithic_21.ngc 69 target_dep RegisterFile_Monolithic_21.ngc RegisterFile_Monolithic_21.prj 70 target_dep RegisterFile_Monolithic_21.prj RegisterFile_Monolithic_21_Pack.vhdl RegisterFile_Monolithic_21.vhdl 71 72 # RegisterFile_Monolithic_22 73 target_dep all RegisterFile_Monolithic_22.ngc 74 target_dep RegisterFile_Monolithic_22.ngc RegisterFile_Monolithic_22.prj 75 target_dep RegisterFile_Monolithic_22.prj RegisterFile_Monolithic_22_Pack.vhdl RegisterFile_Monolithic_22.vhdl 76 77 # RegisterFile_Monolithic_23 78 target_dep all RegisterFile_Monolithic_23.ngc 79 target_dep RegisterFile_Monolithic_23.ngc RegisterFile_Monolithic_23.prj 80 target_dep RegisterFile_Monolithic_23.prj RegisterFile_Monolithic_23_Pack.vhdl RegisterFile_Monolithic_23.vhdl 81 82 # RegisterFile_Monolithic_24 83 target_dep all RegisterFile_Monolithic_24.ngc 84 target_dep RegisterFile_Monolithic_24.ngc RegisterFile_Monolithic_24.prj 85 target_dep RegisterFile_Monolithic_24.prj RegisterFile_Monolithic_24_Pack.vhdl RegisterFile_Monolithic_24.vhdl 86 87 # RegisterFile_Monolithic_25 88 target_dep all RegisterFile_Monolithic_25.ngc 89 target_dep RegisterFile_Monolithic_25.ngc RegisterFile_Monolithic_25.prj 90 target_dep RegisterFile_Monolithic_25.prj RegisterFile_Monolithic_25_Pack.vhdl RegisterFile_Monolithic_25.vhdl 91 92 # RegisterFile_Monolithic_26 93 target_dep all RegisterFile_Monolithic_26.ngc 94 target_dep RegisterFile_Monolithic_26.ngc RegisterFile_Monolithic_26.prj 95 target_dep RegisterFile_Monolithic_26.prj RegisterFile_Monolithic_26_Pack.vhdl RegisterFile_Monolithic_26.vhdl 96 97 # RegisterFile_Monolithic_27 98 target_dep all RegisterFile_Monolithic_27.ngc 99 target_dep RegisterFile_Monolithic_27.ngc RegisterFile_Monolithic_27.prj 100 target_dep RegisterFile_Monolithic_27.prj RegisterFile_Monolithic_27_Pack.vhdl RegisterFile_Monolithic_27.vhdl 101 102 # RegisterFile_Monolithic_28 103 target_dep all RegisterFile_Monolithic_28.ngc 104 target_dep RegisterFile_Monolithic_28.ngc RegisterFile_Monolithic_28.prj 105 target_dep RegisterFile_Monolithic_28.prj RegisterFile_Monolithic_28_Pack.vhdl RegisterFile_Monolithic_28.vhdl 106 107 # RegisterFile_Monolithic_29 108 target_dep all RegisterFile_Monolithic_29.ngc 109 target_dep RegisterFile_Monolithic_29.ngc RegisterFile_Monolithic_29.prj 110 target_dep RegisterFile_Monolithic_29.prj RegisterFile_Monolithic_29_Pack.vhdl RegisterFile_Monolithic_29.vhdl 10 target_dep RegisterFile_Monolithic_1.prj RegisterFile_Monolithic_1_Pack.vhdl RegisterFile_Monolithic_1.vhdl 111 11 112 12 # RegisterFile_Monolithic_2 113 13 target_dep all RegisterFile_Monolithic_2.ngc 114 14 target_dep RegisterFile_Monolithic_2.ngc RegisterFile_Monolithic_2.prj 115 target_dep RegisterFile_Monolithic_2.prj RegisterFile_Monolithic_20_Pack.vhdl RegisterFile_Monolithic_20.vhdl RegisterFile_Monolithic_21_Pack.vhdl RegisterFile_Monolithic_21.vhdl RegisterFile_Monolithic_22_Pack.vhdl RegisterFile_Monolithic_22.vhdl RegisterFile_Monolithic_23_Pack.vhdl RegisterFile_Monolithic_23.vhdl RegisterFile_Monolithic_24_Pack.vhdl RegisterFile_Monolithic_24.vhdl RegisterFile_Monolithic_25_Pack.vhdl RegisterFile_Monolithic_25.vhdl RegisterFile_Monolithic_26_Pack.vhdl RegisterFile_Monolithic_26.vhdl RegisterFile_Monolithic_27_Pack.vhdl RegisterFile_Monolithic_27.vhdl RegisterFile_Monolithic_28_Pack.vhdl RegisterFile_Monolithic_28.vhdl RegisterFile_Monolithic_29_Pack.vhdl RegisterFile_Monolithic_29.vhdl RegisterFile_Monolithic_2_Pack.vhdl RegisterFile_Monolithic_2.vhdl 116 117 # RegisterFile_Monolithic_30 118 target_dep all RegisterFile_Monolithic_30.ngc 119 target_dep RegisterFile_Monolithic_30.ngc RegisterFile_Monolithic_30.prj 120 target_dep RegisterFile_Monolithic_30.prj RegisterFile_Monolithic_30_Pack.vhdl RegisterFile_Monolithic_30.vhdl 121 122 # RegisterFile_Monolithic_31 123 target_dep all RegisterFile_Monolithic_31.ngc 124 target_dep RegisterFile_Monolithic_31.ngc RegisterFile_Monolithic_31.prj 125 target_dep RegisterFile_Monolithic_31.prj RegisterFile_Monolithic_31_Pack.vhdl RegisterFile_Monolithic_31.vhdl 126 127 # RegisterFile_Monolithic_32 128 target_dep all RegisterFile_Monolithic_32.ngc 129 target_dep RegisterFile_Monolithic_32.ngc RegisterFile_Monolithic_32.prj 130 target_dep RegisterFile_Monolithic_32.prj RegisterFile_Monolithic_32_Pack.vhdl RegisterFile_Monolithic_32.vhdl 131 132 # RegisterFile_Monolithic_33 133 target_dep all RegisterFile_Monolithic_33.ngc 134 target_dep RegisterFile_Monolithic_33.ngc RegisterFile_Monolithic_33.prj 135 target_dep RegisterFile_Monolithic_33.prj RegisterFile_Monolithic_33_Pack.vhdl RegisterFile_Monolithic_33.vhdl 136 137 # RegisterFile_Monolithic_34 138 target_dep all RegisterFile_Monolithic_34.ngc 139 target_dep RegisterFile_Monolithic_34.ngc RegisterFile_Monolithic_34.prj 140 target_dep RegisterFile_Monolithic_34.prj RegisterFile_Monolithic_34_Pack.vhdl RegisterFile_Monolithic_34.vhdl 141 142 # RegisterFile_Monolithic_35 143 target_dep all RegisterFile_Monolithic_35.ngc 144 target_dep RegisterFile_Monolithic_35.ngc RegisterFile_Monolithic_35.prj 145 target_dep RegisterFile_Monolithic_35.prj RegisterFile_Monolithic_35_Pack.vhdl RegisterFile_Monolithic_35.vhdl 15 target_dep RegisterFile_Monolithic_2.prj RegisterFile_Monolithic_2_Pack.vhdl RegisterFile_Monolithic_2.vhdl 146 16 147 17 # RegisterFile_Monolithic_3 148 18 target_dep all RegisterFile_Monolithic_3.ngc 149 19 target_dep RegisterFile_Monolithic_3.ngc RegisterFile_Monolithic_3.prj 150 target_dep RegisterFile_Monolithic_3.prj RegisterFile_Monolithic_3 0_Pack.vhdl RegisterFile_Monolithic_30.vhdl RegisterFile_Monolithic_31_Pack.vhdl RegisterFile_Monolithic_31.vhdl RegisterFile_Monolithic_32_Pack.vhdl RegisterFile_Monolithic_32.vhdl RegisterFile_Monolithic_33_Pack.vhdl RegisterFile_Monolithic_33.vhdl RegisterFile_Monolithic_34_Pack.vhdl RegisterFile_Monolithic_34.vhdl RegisterFile_Monolithic_35_Pack.vhdl RegisterFile_Monolithic_35.vhdl RegisterFile_Monolithic_3_Pack.vhdl RegisterFile_Monolithic_3.vhdl20 target_dep RegisterFile_Monolithic_3.prj RegisterFile_Monolithic_3_Pack.vhdl RegisterFile_Monolithic_3.vhdl 151 21 152 # RegisterFile_Monolithic_4153 target_dep all RegisterFile_Monolithic_4.ngc154 target_dep RegisterFile_Monolithic_4.ngc RegisterFile_Monolithic_4.prj155 target_dep RegisterFile_Monolithic_4.prj RegisterFile_Monolithic_4_Pack.vhdl RegisterFile_Monolithic_4.vhdl156 157 # RegisterFile_Monolithic_5158 target_dep all RegisterFile_Monolithic_5.ngc159 target_dep RegisterFile_Monolithic_5.ngc RegisterFile_Monolithic_5.prj160 target_dep RegisterFile_Monolithic_5.prj RegisterFile_Monolithic_5_Pack.vhdl RegisterFile_Monolithic_5.vhdl161 162 # RegisterFile_Monolithic_6163 target_dep all RegisterFile_Monolithic_6.ngc164 target_dep RegisterFile_Monolithic_6.ngc RegisterFile_Monolithic_6.prj165 target_dep RegisterFile_Monolithic_6.prj RegisterFile_Monolithic_6_Pack.vhdl RegisterFile_Monolithic_6.vhdl166 167 # RegisterFile_Monolithic_7168 target_dep all RegisterFile_Monolithic_7.ngc169 target_dep RegisterFile_Monolithic_7.ngc RegisterFile_Monolithic_7.prj170 target_dep RegisterFile_Monolithic_7.prj RegisterFile_Monolithic_7_Pack.vhdl RegisterFile_Monolithic_7.vhdl171 172 # RegisterFile_Monolithic_8173 target_dep all RegisterFile_Monolithic_8.ngc174 target_dep RegisterFile_Monolithic_8.ngc RegisterFile_Monolithic_8.prj175 target_dep RegisterFile_Monolithic_8.prj RegisterFile_Monolithic_8_Pack.vhdl RegisterFile_Monolithic_8.vhdl176 177 # RegisterFile_Monolithic_9178 target_dep all RegisterFile_Monolithic_9.ngc179 target_dep RegisterFile_Monolithic_9.ngc RegisterFile_Monolithic_9.prj180 target_dep RegisterFile_Monolithic_9.prj RegisterFile_Monolithic_9_Pack.vhdl RegisterFile_Monolithic_9.vhdl181 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/main.cpp
r15 r55 8 8 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h" 9 9 10 #define NB_PARAMS 410 #define NB_PARAMS 5 11 11 12 12 void usage (string exec) … … 14 14 cerr << "<Usage> " << exec << " name_instance list_params" << endl 15 15 << "list_params is :" << endl 16 << " - nb_port_read (unsigned int)" << endl 17 << " - nb_port_write (unsigned int)" << endl 18 << " - nb_word (unsigned int)" << endl 19 << " - size_word (unsigned int)" << endl; 16 << " - nb_port_read (unsigned int)" << endl 17 << " - nb_port_write (unsigned int)" << endl 18 << " - nb_port_read_write (unsigned int)" << endl 19 << " - nb_word (unsigned int)" << endl 20 << " - size_word (unsigned int)" << endl; 20 21 exit (1); 21 22 } … … 30 31 usage (argv[0]); 31 32 32 const string name = argv[1]; 33 const uint32_t nb_port_read = atoi(argv[2]); 34 const uint32_t nb_port_write = atoi(argv[3]); 35 const uint32_t nb_word = atoi(argv[4]); 36 const uint32_t size_word = atoi(argv[5]); 33 const string name = argv[1]; 34 const uint32_t nb_port_read = atoi(argv[2]); 35 const uint32_t nb_port_write = atoi(argv[3]); 36 const uint32_t nb_port_read_write = atoi(argv[4]); 37 const uint32_t nb_word = atoi(argv[5]); 38 const uint32_t size_word = atoi(argv[6]); 37 39 38 morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters param (nb_port_read , 39 nb_port_write, 40 nb_word , 41 size_word ); 42 40 morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * param = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters 41 (nb_port_read , 42 nb_port_write, 43 nb_port_read_write, 44 nb_word , 45 size_word ); 46 43 47 test (name,param); 44 48 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp
r50 r55 7 7 */ 8 8 9 #define NB_ITERATION 329 #define NB_ITERATION 2 10 10 11 11 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h" … … 13 13 14 14 void test (string name, 15 morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters param)15 morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param) 16 16 { 17 17 cout << "<" << name << "> : Simulation SystemC" << endl; … … 19 19 try 20 20 { 21 cout << param.print(1);22 param.test();21 cout << _param->print(1); 22 _param->test(); 23 23 } 24 24 catch (morpheo::ErrorMorpheo & error) … … 33 33 } 34 34 35 #ifdef STATISTICS 36 morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,1000); 37 #endif 35 38 RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic (name.c_str() 36 39 #ifdef STATISTICS 37 , morpheo::behavioural::Parameters_Statistics(5,1000)40 ,_param_stat 38 41 #endif 39 , param);42 ,_param); 40 43 41 44 #ifdef SYSTEMC … … 46 49 sc_signal<Tcontrol_t> NRESET; 47 50 48 sc_signal<Tcontrol_t> READ_VAL [param._nb_port_read]; 49 sc_signal<Tcontrol_t> READ_ACK [param._nb_port_read]; 50 sc_signal<Taddress_t> READ_ADDRESS [param._nb_port_read]; 51 sc_signal<Tdata_t> READ_DATA [param._nb_port_read]; 52 53 sc_signal<Tcontrol_t> WRITE_VAL [param._nb_port_write]; 54 sc_signal<Tcontrol_t> WRITE_ACK [param._nb_port_write]; 55 sc_signal<Taddress_t> WRITE_ADDRESS [param._nb_port_write]; 56 sc_signal<Tdata_t> WRITE_DATA [param._nb_port_write]; 51 sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read]; 52 sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read]; 53 sc_signal<Taddress_t> READ_ADDRESS [_param->_nb_port_read]; 54 sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read]; 55 56 sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write]; 57 sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write]; 58 sc_signal<Taddress_t> WRITE_ADDRESS [_param->_nb_port_write]; 59 sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write]; 60 61 sc_signal<Tcontrol_t> READ_WRITE_VAL [_param->_nb_port_read_write]; 62 sc_signal<Tcontrol_t> READ_WRITE_ACK [_param->_nb_port_read_write]; 63 sc_signal<Tcontrol_t> READ_WRITE_RW [_param->_nb_port_read_write]; 64 sc_signal<Taddress_t> READ_WRITE_ADDRESS [_param->_nb_port_read_write]; 65 sc_signal<Tdata_t> READ_WRITE_RDATA [_param->_nb_port_read_write]; 66 sc_signal<Tdata_t> READ_WRITE_WDATA [_param->_nb_port_read_write]; 57 67 58 68 /******************************************************** … … 65 75 (*(registerfile->in_NRESET)) (NRESET); 66 76 67 for (uint32_t i=0; i< param._nb_port_read; i++)77 for (uint32_t i=0; i<_param->_nb_port_read; i++) 68 78 { 69 79 (*(registerfile-> in_READ_VAL [i])) (READ_VAL [i]); … … 72 82 (*(registerfile->out_READ_DATA [i])) (READ_DATA [i]); 73 83 } 74 75 for (uint32_t i=0; i<param._nb_port_write; i++) 84 for (uint32_t i=0; i<_param->_nb_port_write; i++) 76 85 { 77 86 (*(registerfile-> in_WRITE_VAL [i])) (WRITE_VAL [i]); … … 80 89 (*(registerfile-> in_WRITE_DATA [i])) (WRITE_DATA [i]); 81 90 } 91 for (uint32_t i=0; i<_param->_nb_port_read_write; i++) 92 { 93 (*(registerfile-> in_READ_WRITE_VAL [i])) (READ_WRITE_VAL [i]); 94 (*(registerfile->out_READ_WRITE_ACK [i])) (READ_WRITE_ACK [i]); 95 (*(registerfile-> in_READ_WRITE_RW [i])) (READ_WRITE_RW [i]); 96 (*(registerfile-> in_READ_WRITE_ADDRESS [i])) (READ_WRITE_ADDRESS [i]); 97 (*(registerfile-> in_READ_WRITE_WDATA [i])) (READ_WRITE_WDATA [i]); 98 (*(registerfile->out_READ_WRITE_RDATA [i])) (READ_WRITE_RDATA [i]); 99 } 82 100 83 101 cout << "<" << name << "> Start Simulation ............" << endl; … … 92 110 sc_start(0); 93 111 94 for (uint32_t i=0; i< param._nb_port_write; i++)112 for (uint32_t i=0; i<_param->_nb_port_write; i++) 95 113 WRITE_VAL [i] .write (0); 96 97 for (uint32_t i=0; i<param._nb_port_read; i++) 114 for (uint32_t i=0; i<_param->_nb_port_read; i++) 98 115 READ_VAL [i] .write (0); 116 for (uint32_t i=0; i<_param->_nb_port_read_write; i++) 117 READ_WRITE_VAL [i] .write (0); 99 118 100 119 NRESET.write(0); … … 115 134 srand(grain); 116 135 117 Tdata_t tab [ param._nb_word];118 119 for (uint32_t i=0; i< param._nb_word; i++)120 tab[i]= rand()%(1<<( param._size_word-1));136 Tdata_t tab [_param->_nb_word]; 137 138 for (uint32_t i=0; i<_param->_nb_word; i++) 139 tab[i]= rand()%(1<<(_param->_size_word-1)); 121 140 122 141 Taddress_t address_next = 0; 123 142 Taddress_t nb_ack = 0; 124 143 125 while (nb_ack < param._nb_word)144 while (nb_ack < _param->_nb_word) 126 145 { 127 146 cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; 128 147 129 for (uint32_t num_port=0; num_port < param._nb_port_write; num_port ++)130 { 131 if ((address_next < param._nb_word) and148 for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) 149 { 150 if ((address_next < _param->_nb_word) and 132 151 (WRITE_VAL [num_port].read() == 0)) 133 152 { … … 139 158 140 159 // Address can be not a multiple of nb_port_write 141 if (address_next >= param._nb_word) 160 if (address_next >= _param->_nb_word) 161 break; 162 } 163 } 164 165 for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) 166 { 167 if ((address_next < _param->_nb_word) and 168 (READ_WRITE_VAL [num_port].read() == 0)) 169 { 170 cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl; 171 172 READ_WRITE_VAL [num_port] .write(1); 173 READ_WRITE_RW [num_port] .write(RW_WRITE); 174 READ_WRITE_WDATA [num_port] .write(tab[address_next]); 175 READ_WRITE_ADDRESS [num_port] .write(address_next++); 176 177 // Address can be not a multiple of nb_port_write 178 if (address_next >= _param->_nb_word) 142 179 break; 143 180 } … … 147 184 148 185 // reset write_val port 149 for (uint32_t num_port=0; num_port < param._nb_port_write; num_port ++)186 for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) 150 187 { 151 188 if ((WRITE_ACK [num_port].read() == 1) and … … 156 193 } 157 194 } 195 // reset write_val port 196 for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) 197 { 198 if ((READ_WRITE_ACK [num_port].read() == 1) and 199 (READ_WRITE_VAL [num_port].read() == 1)) 200 { 201 READ_WRITE_VAL [num_port] .write(0); 202 nb_ack ++; 203 } 204 } 158 205 159 206 sc_start(0); … … 165 212 cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl; 166 213 167 Tdata_t read_address [param._nb_port_read]; 168 169 while (nb_ack < param._nb_word) 214 Tdata_t read_address [_param->_nb_port_read]; 215 Tdata_t read_write_address [_param->_nb_port_read_write]; 216 217 while (nb_ack < _param->_nb_word) 170 218 { 171 219 cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; 172 220 173 for (uint32_t num_port=0; num_port < param._nb_port_read; num_port ++)174 { 175 if ((address_next < param._nb_word) and221 for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) 222 { 223 if ((address_next < _param->_nb_word) and 176 224 (READ_VAL [num_port].read() == 0)) 177 225 { … … 181 229 READ_ADDRESS [num_port].write(read_address [num_port]); 182 230 183 if (address_next >= param._nb_word) 184 break; 185 } 186 } 231 if (address_next >= _param->_nb_word) 232 break; 233 } 234 } 235 236 for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) 237 { 238 if ((address_next < _param->_nb_word) and 239 (READ_WRITE_VAL [num_port].read() == 0)) 240 { 241 read_write_address [num_port] = address_next++; 242 243 READ_WRITE_VAL [num_port].write(1); 244 READ_WRITE_RW [num_port].write(RW_READ); 245 READ_WRITE_ADDRESS [num_port].write(read_write_address [num_port]); 246 247 if (address_next >= _param->_nb_word) 248 break; 249 } 250 } 251 187 252 188 253 sc_start(1); 189 254 190 255 // reset write_val port 191 for (uint32_t num_port=0; num_port < param._nb_port_read; num_port ++)256 for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) 192 257 { 193 258 if ((READ_ACK [num_port].read() == 1) and … … 199 264 200 265 TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]); 266 nb_ack ++; 267 } 268 } 269 270 for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) 271 { 272 if ((READ_WRITE_ACK [num_port].read() == 1) and 273 (READ_WRITE_VAL [num_port].read() == 1)) 274 { 275 READ_WRITE_VAL [num_port] .write(0); 276 277 cout << "(" << num_port << ") [" << read_write_address [num_port] << "] => " << READ_WRITE_RDATA [num_port].read() << endl; 278 279 TEST(Tdata_t,READ_WRITE_RDATA [num_port].read(), tab[read_write_address [num_port]]); 201 280 nb_ack ++; 202 281 }
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