Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration.cfg	(revision 53)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration.cfg	(revision 55)
@@ -1,5 +1,6 @@
 RegisterFile_Monolithic
-2	8 	*2	# nb_port_read
-1	4	*2	# nb_port_write
-32	256	*2	# nb_word
+0	0 	*2	# nb_port_read
+0	0	*2	# nb_port_write
+1	8	*2	# nb_port_read_write
+32 	32 	*2	# nb_word
 32	32	*2	# size_word
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h	(revision 53)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h	(revision 55)
@@ -24,5 +24,5 @@
 
 void test   (string name,
-	     morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters param);
+	     morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * param);
 
 class Time 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info	(revision 53)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info	(revision 55)
@@ -5,177 +5,17 @@
 target_dep	RegisterFile_Monolithic_0.prj	RegisterFile_Monolithic_0_Pack.vhdl RegisterFile_Monolithic_0.vhdl
 
-# RegisterFile_Monolithic_10
-target_dep	all	RegisterFile_Monolithic_10.ngc
-target_dep	RegisterFile_Monolithic_10.ngc	RegisterFile_Monolithic_10.prj
-target_dep	RegisterFile_Monolithic_10.prj	RegisterFile_Monolithic_10_Pack.vhdl RegisterFile_Monolithic_10.vhdl
-
-# RegisterFile_Monolithic_11
-target_dep	all	RegisterFile_Monolithic_11.ngc
-target_dep	RegisterFile_Monolithic_11.ngc	RegisterFile_Monolithic_11.prj
-target_dep	RegisterFile_Monolithic_11.prj	RegisterFile_Monolithic_11_Pack.vhdl RegisterFile_Monolithic_11.vhdl
-
-# RegisterFile_Monolithic_12
-target_dep	all	RegisterFile_Monolithic_12.ngc
-target_dep	RegisterFile_Monolithic_12.ngc	RegisterFile_Monolithic_12.prj
-target_dep	RegisterFile_Monolithic_12.prj	RegisterFile_Monolithic_12_Pack.vhdl RegisterFile_Monolithic_12.vhdl
-
-# RegisterFile_Monolithic_13
-target_dep	all	RegisterFile_Monolithic_13.ngc
-target_dep	RegisterFile_Monolithic_13.ngc	RegisterFile_Monolithic_13.prj
-target_dep	RegisterFile_Monolithic_13.prj	RegisterFile_Monolithic_13_Pack.vhdl RegisterFile_Monolithic_13.vhdl
-
-# RegisterFile_Monolithic_14
-target_dep	all	RegisterFile_Monolithic_14.ngc
-target_dep	RegisterFile_Monolithic_14.ngc	RegisterFile_Monolithic_14.prj
-target_dep	RegisterFile_Monolithic_14.prj	RegisterFile_Monolithic_14_Pack.vhdl RegisterFile_Monolithic_14.vhdl
-
-# RegisterFile_Monolithic_15
-target_dep	all	RegisterFile_Monolithic_15.ngc
-target_dep	RegisterFile_Monolithic_15.ngc	RegisterFile_Monolithic_15.prj
-target_dep	RegisterFile_Monolithic_15.prj	RegisterFile_Monolithic_15_Pack.vhdl RegisterFile_Monolithic_15.vhdl
-
-# RegisterFile_Monolithic_16
-target_dep	all	RegisterFile_Monolithic_16.ngc
-target_dep	RegisterFile_Monolithic_16.ngc	RegisterFile_Monolithic_16.prj
-target_dep	RegisterFile_Monolithic_16.prj	RegisterFile_Monolithic_16_Pack.vhdl RegisterFile_Monolithic_16.vhdl
-
-# RegisterFile_Monolithic_17
-target_dep	all	RegisterFile_Monolithic_17.ngc
-target_dep	RegisterFile_Monolithic_17.ngc	RegisterFile_Monolithic_17.prj
-target_dep	RegisterFile_Monolithic_17.prj	RegisterFile_Monolithic_17_Pack.vhdl RegisterFile_Monolithic_17.vhdl
-
-# RegisterFile_Monolithic_18
-target_dep	all	RegisterFile_Monolithic_18.ngc
-target_dep	RegisterFile_Monolithic_18.ngc	RegisterFile_Monolithic_18.prj
-target_dep	RegisterFile_Monolithic_18.prj	RegisterFile_Monolithic_18_Pack.vhdl RegisterFile_Monolithic_18.vhdl
-
-# RegisterFile_Monolithic_19
-target_dep	all	RegisterFile_Monolithic_19.ngc
-target_dep	RegisterFile_Monolithic_19.ngc	RegisterFile_Monolithic_19.prj
-target_dep	RegisterFile_Monolithic_19.prj	RegisterFile_Monolithic_19_Pack.vhdl RegisterFile_Monolithic_19.vhdl
-
 # RegisterFile_Monolithic_1
 target_dep	all	RegisterFile_Monolithic_1.ngc
 target_dep	RegisterFile_Monolithic_1.ngc	RegisterFile_Monolithic_1.prj
-target_dep	RegisterFile_Monolithic_1.prj	RegisterFile_Monolithic_10_Pack.vhdl RegisterFile_Monolithic_10.vhdl RegisterFile_Monolithic_11_Pack.vhdl RegisterFile_Monolithic_11.vhdl RegisterFile_Monolithic_12_Pack.vhdl RegisterFile_Monolithic_12.vhdl RegisterFile_Monolithic_13_Pack.vhdl RegisterFile_Monolithic_13.vhdl RegisterFile_Monolithic_14_Pack.vhdl RegisterFile_Monolithic_14.vhdl RegisterFile_Monolithic_15_Pack.vhdl RegisterFile_Monolithic_15.vhdl RegisterFile_Monolithic_16_Pack.vhdl RegisterFile_Monolithic_16.vhdl RegisterFile_Monolithic_17_Pack.vhdl RegisterFile_Monolithic_17.vhdl RegisterFile_Monolithic_18_Pack.vhdl RegisterFile_Monolithic_18.vhdl RegisterFile_Monolithic_19_Pack.vhdl RegisterFile_Monolithic_19.vhdl RegisterFile_Monolithic_1_Pack.vhdl RegisterFile_Monolithic_1.vhdl
-
-# RegisterFile_Monolithic_20
-target_dep	all	RegisterFile_Monolithic_20.ngc
-target_dep	RegisterFile_Monolithic_20.ngc	RegisterFile_Monolithic_20.prj
-target_dep	RegisterFile_Monolithic_20.prj	RegisterFile_Monolithic_20_Pack.vhdl RegisterFile_Monolithic_20.vhdl
-
-# RegisterFile_Monolithic_21
-target_dep	all	RegisterFile_Monolithic_21.ngc
-target_dep	RegisterFile_Monolithic_21.ngc	RegisterFile_Monolithic_21.prj
-target_dep	RegisterFile_Monolithic_21.prj	RegisterFile_Monolithic_21_Pack.vhdl RegisterFile_Monolithic_21.vhdl
-
-# RegisterFile_Monolithic_22
-target_dep	all	RegisterFile_Monolithic_22.ngc
-target_dep	RegisterFile_Monolithic_22.ngc	RegisterFile_Monolithic_22.prj
-target_dep	RegisterFile_Monolithic_22.prj	RegisterFile_Monolithic_22_Pack.vhdl RegisterFile_Monolithic_22.vhdl
-
-# RegisterFile_Monolithic_23
-target_dep	all	RegisterFile_Monolithic_23.ngc
-target_dep	RegisterFile_Monolithic_23.ngc	RegisterFile_Monolithic_23.prj
-target_dep	RegisterFile_Monolithic_23.prj	RegisterFile_Monolithic_23_Pack.vhdl RegisterFile_Monolithic_23.vhdl
-
-# RegisterFile_Monolithic_24
-target_dep	all	RegisterFile_Monolithic_24.ngc
-target_dep	RegisterFile_Monolithic_24.ngc	RegisterFile_Monolithic_24.prj
-target_dep	RegisterFile_Monolithic_24.prj	RegisterFile_Monolithic_24_Pack.vhdl RegisterFile_Monolithic_24.vhdl
-
-# RegisterFile_Monolithic_25
-target_dep	all	RegisterFile_Monolithic_25.ngc
-target_dep	RegisterFile_Monolithic_25.ngc	RegisterFile_Monolithic_25.prj
-target_dep	RegisterFile_Monolithic_25.prj	RegisterFile_Monolithic_25_Pack.vhdl RegisterFile_Monolithic_25.vhdl
-
-# RegisterFile_Monolithic_26
-target_dep	all	RegisterFile_Monolithic_26.ngc
-target_dep	RegisterFile_Monolithic_26.ngc	RegisterFile_Monolithic_26.prj
-target_dep	RegisterFile_Monolithic_26.prj	RegisterFile_Monolithic_26_Pack.vhdl RegisterFile_Monolithic_26.vhdl
-
-# RegisterFile_Monolithic_27
-target_dep	all	RegisterFile_Monolithic_27.ngc
-target_dep	RegisterFile_Monolithic_27.ngc	RegisterFile_Monolithic_27.prj
-target_dep	RegisterFile_Monolithic_27.prj	RegisterFile_Monolithic_27_Pack.vhdl RegisterFile_Monolithic_27.vhdl
-
-# RegisterFile_Monolithic_28
-target_dep	all	RegisterFile_Monolithic_28.ngc
-target_dep	RegisterFile_Monolithic_28.ngc	RegisterFile_Monolithic_28.prj
-target_dep	RegisterFile_Monolithic_28.prj	RegisterFile_Monolithic_28_Pack.vhdl RegisterFile_Monolithic_28.vhdl
-
-# RegisterFile_Monolithic_29
-target_dep	all	RegisterFile_Monolithic_29.ngc
-target_dep	RegisterFile_Monolithic_29.ngc	RegisterFile_Monolithic_29.prj
-target_dep	RegisterFile_Monolithic_29.prj	RegisterFile_Monolithic_29_Pack.vhdl RegisterFile_Monolithic_29.vhdl
+target_dep	RegisterFile_Monolithic_1.prj	RegisterFile_Monolithic_1_Pack.vhdl RegisterFile_Monolithic_1.vhdl
 
 # RegisterFile_Monolithic_2
 target_dep	all	RegisterFile_Monolithic_2.ngc
 target_dep	RegisterFile_Monolithic_2.ngc	RegisterFile_Monolithic_2.prj
-target_dep	RegisterFile_Monolithic_2.prj	RegisterFile_Monolithic_20_Pack.vhdl RegisterFile_Monolithic_20.vhdl RegisterFile_Monolithic_21_Pack.vhdl RegisterFile_Monolithic_21.vhdl RegisterFile_Monolithic_22_Pack.vhdl RegisterFile_Monolithic_22.vhdl RegisterFile_Monolithic_23_Pack.vhdl RegisterFile_Monolithic_23.vhdl RegisterFile_Monolithic_24_Pack.vhdl RegisterFile_Monolithic_24.vhdl RegisterFile_Monolithic_25_Pack.vhdl RegisterFile_Monolithic_25.vhdl RegisterFile_Monolithic_26_Pack.vhdl RegisterFile_Monolithic_26.vhdl RegisterFile_Monolithic_27_Pack.vhdl RegisterFile_Monolithic_27.vhdl RegisterFile_Monolithic_28_Pack.vhdl RegisterFile_Monolithic_28.vhdl RegisterFile_Monolithic_29_Pack.vhdl RegisterFile_Monolithic_29.vhdl RegisterFile_Monolithic_2_Pack.vhdl RegisterFile_Monolithic_2.vhdl
-
-# RegisterFile_Monolithic_30
-target_dep	all	RegisterFile_Monolithic_30.ngc
-target_dep	RegisterFile_Monolithic_30.ngc	RegisterFile_Monolithic_30.prj
-target_dep	RegisterFile_Monolithic_30.prj	RegisterFile_Monolithic_30_Pack.vhdl RegisterFile_Monolithic_30.vhdl
-
-# RegisterFile_Monolithic_31
-target_dep	all	RegisterFile_Monolithic_31.ngc
-target_dep	RegisterFile_Monolithic_31.ngc	RegisterFile_Monolithic_31.prj
-target_dep	RegisterFile_Monolithic_31.prj	RegisterFile_Monolithic_31_Pack.vhdl RegisterFile_Monolithic_31.vhdl
-
-# RegisterFile_Monolithic_32
-target_dep	all	RegisterFile_Monolithic_32.ngc
-target_dep	RegisterFile_Monolithic_32.ngc	RegisterFile_Monolithic_32.prj
-target_dep	RegisterFile_Monolithic_32.prj	RegisterFile_Monolithic_32_Pack.vhdl RegisterFile_Monolithic_32.vhdl
-
-# RegisterFile_Monolithic_33
-target_dep	all	RegisterFile_Monolithic_33.ngc
-target_dep	RegisterFile_Monolithic_33.ngc	RegisterFile_Monolithic_33.prj
-target_dep	RegisterFile_Monolithic_33.prj	RegisterFile_Monolithic_33_Pack.vhdl RegisterFile_Monolithic_33.vhdl
-
-# RegisterFile_Monolithic_34
-target_dep	all	RegisterFile_Monolithic_34.ngc
-target_dep	RegisterFile_Monolithic_34.ngc	RegisterFile_Monolithic_34.prj
-target_dep	RegisterFile_Monolithic_34.prj	RegisterFile_Monolithic_34_Pack.vhdl RegisterFile_Monolithic_34.vhdl
-
-# RegisterFile_Monolithic_35
-target_dep	all	RegisterFile_Monolithic_35.ngc
-target_dep	RegisterFile_Monolithic_35.ngc	RegisterFile_Monolithic_35.prj
-target_dep	RegisterFile_Monolithic_35.prj	RegisterFile_Monolithic_35_Pack.vhdl RegisterFile_Monolithic_35.vhdl
+target_dep	RegisterFile_Monolithic_2.prj	RegisterFile_Monolithic_2_Pack.vhdl RegisterFile_Monolithic_2.vhdl
 
 # RegisterFile_Monolithic_3
 target_dep	all	RegisterFile_Monolithic_3.ngc
 target_dep	RegisterFile_Monolithic_3.ngc	RegisterFile_Monolithic_3.prj
-target_dep	RegisterFile_Monolithic_3.prj	RegisterFile_Monolithic_30_Pack.vhdl RegisterFile_Monolithic_30.vhdl RegisterFile_Monolithic_31_Pack.vhdl RegisterFile_Monolithic_31.vhdl RegisterFile_Monolithic_32_Pack.vhdl RegisterFile_Monolithic_32.vhdl RegisterFile_Monolithic_33_Pack.vhdl RegisterFile_Monolithic_33.vhdl RegisterFile_Monolithic_34_Pack.vhdl RegisterFile_Monolithic_34.vhdl RegisterFile_Monolithic_35_Pack.vhdl RegisterFile_Monolithic_35.vhdl RegisterFile_Monolithic_3_Pack.vhdl RegisterFile_Monolithic_3.vhdl
+target_dep	RegisterFile_Monolithic_3.prj	RegisterFile_Monolithic_3_Pack.vhdl RegisterFile_Monolithic_3.vhdl
 
-# RegisterFile_Monolithic_4
-target_dep	all	RegisterFile_Monolithic_4.ngc
-target_dep	RegisterFile_Monolithic_4.ngc	RegisterFile_Monolithic_4.prj
-target_dep	RegisterFile_Monolithic_4.prj	RegisterFile_Monolithic_4_Pack.vhdl RegisterFile_Monolithic_4.vhdl
-
-# RegisterFile_Monolithic_5
-target_dep	all	RegisterFile_Monolithic_5.ngc
-target_dep	RegisterFile_Monolithic_5.ngc	RegisterFile_Monolithic_5.prj
-target_dep	RegisterFile_Monolithic_5.prj	RegisterFile_Monolithic_5_Pack.vhdl RegisterFile_Monolithic_5.vhdl
-
-# RegisterFile_Monolithic_6
-target_dep	all	RegisterFile_Monolithic_6.ngc
-target_dep	RegisterFile_Monolithic_6.ngc	RegisterFile_Monolithic_6.prj
-target_dep	RegisterFile_Monolithic_6.prj	RegisterFile_Monolithic_6_Pack.vhdl RegisterFile_Monolithic_6.vhdl
-
-# RegisterFile_Monolithic_7
-target_dep	all	RegisterFile_Monolithic_7.ngc
-target_dep	RegisterFile_Monolithic_7.ngc	RegisterFile_Monolithic_7.prj
-target_dep	RegisterFile_Monolithic_7.prj	RegisterFile_Monolithic_7_Pack.vhdl RegisterFile_Monolithic_7.vhdl
-
-# RegisterFile_Monolithic_8
-target_dep	all	RegisterFile_Monolithic_8.ngc
-target_dep	RegisterFile_Monolithic_8.ngc	RegisterFile_Monolithic_8.prj
-target_dep	RegisterFile_Monolithic_8.prj	RegisterFile_Monolithic_8_Pack.vhdl RegisterFile_Monolithic_8.vhdl
-
-# RegisterFile_Monolithic_9
-target_dep	all	RegisterFile_Monolithic_9.ngc
-target_dep	RegisterFile_Monolithic_9.ngc	RegisterFile_Monolithic_9.prj
-target_dep	RegisterFile_Monolithic_9.prj	RegisterFile_Monolithic_9_Pack.vhdl RegisterFile_Monolithic_9.vhdl
-
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/main.cpp	(revision 53)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/main.cpp	(revision 55)
@@ -8,5 +8,5 @@
 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h"
 
-#define NB_PARAMS 4
+#define NB_PARAMS 5
 
 void usage (string exec)
@@ -14,8 +14,9 @@
   cerr << "<Usage> " << exec << " name_instance list_params" << endl
        << "list_params is :" << endl
-       << " - nb_port_read  (unsigned int)" << endl
-       << " - nb_port_write (unsigned int)" << endl
-       << " - nb_word       (unsigned int)" << endl
-       << " - size_word     (unsigned int)" << endl;
+       << " - nb_port_read       (unsigned int)" << endl
+       << " - nb_port_write      (unsigned int)" << endl
+       << " - nb_port_read_write (unsigned int)" << endl
+       << " - nb_word            (unsigned int)" << endl
+       << " - size_word          (unsigned int)" << endl;
   exit (1);
 }
@@ -30,15 +31,18 @@
     usage (argv[0]);
 
-  const string   name          = argv[1];
-  const uint32_t nb_port_read  = atoi(argv[2]);
-  const uint32_t nb_port_write = atoi(argv[3]);
-  const uint32_t nb_word       = atoi(argv[4]);
-  const uint32_t size_word     = atoi(argv[5]);
+  const string   name               = argv[1];
+  const uint32_t nb_port_read       = atoi(argv[2]);
+  const uint32_t nb_port_write      = atoi(argv[3]);
+  const uint32_t nb_port_read_write = atoi(argv[4]);
+  const uint32_t nb_word            = atoi(argv[5]);
+  const uint32_t size_word          = atoi(argv[6]);
   
-  morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters param (nb_port_read ,
-											  nb_port_write,
-								 nb_word      ,
-								 size_word    );
-
+  morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * param = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters
+    (nb_port_read ,
+     nb_port_write,
+     nb_port_read_write,
+     nb_word      ,
+     size_word    );
+  
   test (name,param);
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp	(revision 53)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp	(revision 55)
@@ -7,5 +7,5 @@
  */
 
-#define NB_ITERATION 32
+#define NB_ITERATION 2
 
 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h"
@@ -13,5 +13,5 @@
 
 void test (string name,
-	   morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters param)
+	   morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param)
 {
   cout << "<" << name << "> : Simulation SystemC" << endl;
@@ -19,6 +19,6 @@
   try 
     {
-      cout << param.print(1);
-      param.test();
+      cout << _param->print(1);
+      _param->test();
     }
   catch (morpheo::ErrorMorpheo & error)
@@ -33,9 +33,12 @@
     }
 
+#ifdef STATISTICS
+  morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,1000);
+#endif
   RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic (name.c_str()
 #ifdef STATISTICS
-									,morpheo::behavioural::Parameters_Statistics(5,1000)
+									,_param_stat
 #endif
-									,param);
+									,_param);
   
 #ifdef SYSTEMC
@@ -46,13 +49,20 @@
   sc_signal<Tcontrol_t>                    NRESET;
   
-  sc_signal<Tcontrol_t>                    READ_VAL      [param._nb_port_read];
-  sc_signal<Tcontrol_t>                    READ_ACK      [param._nb_port_read];
-  sc_signal<Taddress_t>                    READ_ADDRESS  [param._nb_port_read];
-  sc_signal<Tdata_t>                       READ_DATA     [param._nb_port_read];
-
-  sc_signal<Tcontrol_t>                    WRITE_VAL     [param._nb_port_write];
-  sc_signal<Tcontrol_t>                    WRITE_ACK     [param._nb_port_write];
-  sc_signal<Taddress_t>                    WRITE_ADDRESS [param._nb_port_write];
-  sc_signal<Tdata_t>                       WRITE_DATA    [param._nb_port_write];
+  sc_signal<Tcontrol_t>                    READ_VAL      [_param->_nb_port_read];
+  sc_signal<Tcontrol_t>                    READ_ACK      [_param->_nb_port_read];
+  sc_signal<Taddress_t>                    READ_ADDRESS  [_param->_nb_port_read];
+  sc_signal<Tdata_t>                       READ_DATA     [_param->_nb_port_read];
+
+  sc_signal<Tcontrol_t>                    WRITE_VAL     [_param->_nb_port_write];
+  sc_signal<Tcontrol_t>                    WRITE_ACK     [_param->_nb_port_write];
+  sc_signal<Taddress_t>                    WRITE_ADDRESS [_param->_nb_port_write];
+  sc_signal<Tdata_t>                       WRITE_DATA    [_param->_nb_port_write];
+
+  sc_signal<Tcontrol_t>                    READ_WRITE_VAL     [_param->_nb_port_read_write];
+  sc_signal<Tcontrol_t>                    READ_WRITE_ACK     [_param->_nb_port_read_write];
+  sc_signal<Tcontrol_t>                    READ_WRITE_RW      [_param->_nb_port_read_write];
+  sc_signal<Taddress_t>                    READ_WRITE_ADDRESS [_param->_nb_port_read_write];
+  sc_signal<Tdata_t>                       READ_WRITE_RDATA   [_param->_nb_port_read_write];
+  sc_signal<Tdata_t>                       READ_WRITE_WDATA   [_param->_nb_port_read_write];
 
   /********************************************************
@@ -65,5 +75,5 @@
   (*(registerfile->in_NRESET))       (NRESET);
 
-  for (uint32_t i=0; i<param._nb_port_read; i++)
+  for (uint32_t i=0; i<_param->_nb_port_read; i++)
     {
       (*(registerfile-> in_READ_VAL      [i]))        (READ_VAL      [i]);
@@ -72,6 +82,5 @@
       (*(registerfile->out_READ_DATA     [i]))        (READ_DATA     [i]);
     }
-
-  for (uint32_t i=0; i<param._nb_port_write; i++)
+  for (uint32_t i=0; i<_param->_nb_port_write; i++)
     {
       (*(registerfile-> in_WRITE_VAL     [i]))        (WRITE_VAL     [i]);
@@ -80,4 +89,13 @@
       (*(registerfile-> in_WRITE_DATA    [i]))        (WRITE_DATA    [i]);
     }
+  for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
+    {
+      (*(registerfile-> in_READ_WRITE_VAL     [i])) (READ_WRITE_VAL      [i]);
+      (*(registerfile->out_READ_WRITE_ACK     [i])) (READ_WRITE_ACK      [i]);
+      (*(registerfile-> in_READ_WRITE_RW      [i])) (READ_WRITE_RW       [i]);
+      (*(registerfile-> in_READ_WRITE_ADDRESS [i])) (READ_WRITE_ADDRESS  [i]);
+      (*(registerfile-> in_READ_WRITE_WDATA   [i])) (READ_WRITE_WDATA    [i]);
+      (*(registerfile->out_READ_WRITE_RDATA   [i])) (READ_WRITE_RDATA    [i]);
+    }
   
   cout << "<" << name << "> Start Simulation ............" << endl;
@@ -92,9 +110,10 @@
   sc_start(0);
   
-  for (uint32_t i=0; i<param._nb_port_write; i++)
+  for (uint32_t i=0; i<_param->_nb_port_write; i++)
     WRITE_VAL [i] .write (0);
-
-  for (uint32_t i=0; i<param._nb_port_read; i++)
+  for (uint32_t i=0; i<_param->_nb_port_read; i++)
     READ_VAL  [i] .write (0);
+  for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
+    READ_WRITE_VAL  [i] .write (0);
 
   NRESET.write(0);
@@ -115,19 +134,19 @@
       srand(grain);
 
-      Tdata_t tab [param._nb_word];
-      
-      for (uint32_t i=0; i<param._nb_word; i++)
-	tab[i]= rand()%(1<<(param._size_word-1));
+      Tdata_t tab [_param->_nb_word];
+      
+      for (uint32_t i=0; i<_param->_nb_word; i++)
+	tab[i]= rand()%(1<<(_param->_size_word-1));
       
       Taddress_t address_next = 0;
       Taddress_t nb_ack = 0;
       
-      while (nb_ack < param._nb_word)
+      while (nb_ack < _param->_nb_word)
 	{
 	  cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
 
-	  for (uint32_t num_port=0; num_port < param._nb_port_write; num_port ++)
-	    {
-	      if ((address_next < param._nb_word) and
+	  for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
+	    {
+	      if ((address_next < _param->_nb_word) and
 		  (WRITE_VAL [num_port].read() == 0))
 		{
@@ -139,5 +158,23 @@
 		  
 		  // Address can be not a multiple of nb_port_write
-		  if (address_next >= param._nb_word)
+		  if (address_next >= _param->_nb_word)
+		    break;
+		}
+	    }
+
+	  for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
+	    {
+	      if ((address_next < _param->_nb_word) and
+		  (READ_WRITE_VAL [num_port].read() == 0))
+		{
+		  cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl;
+		  
+		  READ_WRITE_VAL     [num_port] .write(1);
+		  READ_WRITE_RW      [num_port] .write(RW_WRITE);
+		  READ_WRITE_WDATA   [num_port] .write(tab[address_next]);
+		  READ_WRITE_ADDRESS [num_port] .write(address_next++);
+		  
+		  // Address can be not a multiple of nb_port_write
+		  if (address_next >= _param->_nb_word)
 		    break;
 		}
@@ -147,5 +184,5 @@
 
 	  // reset write_val port
-	  for (uint32_t num_port=0; num_port < param._nb_port_write; num_port ++)
+	  for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
 	    {
 	      if ((WRITE_ACK [num_port].read() == 1) and
@@ -156,4 +193,14 @@
 		}
 	    }
+	  // reset write_val port
+	  for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
+	    {
+	      if ((READ_WRITE_ACK [num_port].read() == 1) and
+		  (READ_WRITE_VAL [num_port].read() == 1))
+		{
+		  READ_WRITE_VAL  [num_port] .write(0);
+		  nb_ack ++;
+		}
+	    }
 
 	  sc_start(0);
@@ -165,13 +212,14 @@
       cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl;
       
-      Tdata_t read_address [param._nb_port_read];
-
-      while (nb_ack < param._nb_word)
+      Tdata_t read_address       [_param->_nb_port_read];
+      Tdata_t read_write_address [_param->_nb_port_read_write];
+
+      while (nb_ack < _param->_nb_word)
 	{
 	  cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
 	  
-	  for (uint32_t num_port=0; num_port < param._nb_port_read; num_port ++)
-	    {
-	      if ((address_next < param._nb_word) and
+	  for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
+	    {
+	      if ((address_next < _param->_nb_word) and
 		  (READ_VAL [num_port].read() == 0))
 		{
@@ -181,13 +229,30 @@
 		  READ_ADDRESS [num_port].write(read_address [num_port]);
 
-		  if (address_next >= param._nb_word)
-		    break;
-		}
-	    }
+		  if (address_next >= _param->_nb_word)
+		    break;
+		}
+	    }
+
+	  for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
+	    {
+	      if ((address_next < _param->_nb_word) and
+		  (READ_WRITE_VAL [num_port].read() == 0))
+		{
+		  read_write_address [num_port] = address_next++;
+
+		  READ_WRITE_VAL     [num_port].write(1);
+		  READ_WRITE_RW      [num_port].write(RW_READ);
+		  READ_WRITE_ADDRESS [num_port].write(read_write_address [num_port]);
+
+		  if (address_next >= _param->_nb_word)
+		    break;
+		}
+	    }
+
 
 	  sc_start(1);
 
 	  // reset write_val port
-	  for (uint32_t num_port=0; num_port < param._nb_port_read; num_port ++)
+	  for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
 	    {
 	      if ((READ_ACK [num_port].read() == 1) and
@@ -199,4 +264,18 @@
 
 		  TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]);
+		  nb_ack ++;
+		}
+	    }
+
+	  for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
+	    {
+	      if ((READ_WRITE_ACK [num_port].read() == 1) and
+		  (READ_WRITE_VAL [num_port].read() == 1))
+		{
+		  READ_WRITE_VAL  [num_port] .write(0);
+
+		  cout << "(" << num_port << ") [" << read_write_address [num_port] << "] => " << READ_WRITE_RDATA [num_port].read() << endl;
+
+		  TEST(Tdata_t,READ_WRITE_RDATA [num_port].read(), tab[read_write_address [num_port]]);
 		  nb_ack ++;
 		}
