Index: trunk/Documents/MORPHEO-Install.txt =================================================================== --- trunk/Documents/MORPHEO-Install.txt (revision 57) +++ trunk/Documents/MORPHEO-Install.txt (revision 57) @@ -0,0 +1,39 @@ +-------------------------------------------------- + install.txt +-------------------------------------------------- + +Follow this step to install the Morpheo Tools Chain + +1) Install GNU-Toolchain + +cf Tools-source/or1k_toolchain-build-instructions.txt + +2) Install newlib + +Now you can compile a software and use the libc and libm + +3) Install a simulator + +3a) systemC +... + +3b) systemCASS + +4) Install soclib + +... + +5) Link + +This step consist at create all symbolik link + * Morpheo/Tools : + - newlib + - or1k + - soclib + - systemc (or systemcass) + * Morpheo/Software/*/src/sys/ + - crt0.s with $TOOLS/newlib/libgloss/or32/crt0.S + * Morpheo/IPs/systemC/shared/ + - mapping_memory.h + +6) Enjoy Index: trunk/INSTALL =================================================================== --- trunk/INSTALL (revision 56) +++ (revision ) @@ -1,39 +1,0 @@ --------------------------------------------------- - install.txt --------------------------------------------------- - -Follow this step to install the Morpheo Tools Chain - -1) Install GNU-Toolchain - -cf Tools-source/or1k_toolchain-build-instructions.txt - -2) Install newlib - -Now you can compile a software and use the libc and libm - -3) Install a simulator - -3a) systemC -... - -3b) systemCASS - -4) Install soclib - -... - -5) Link - -This step consist at create all symbolik link - * Morpheo/Tools : - - newlib - - or1k - - soclib - - systemc (or systemcass) - * Morpheo/Software/*/src/sys/ - - crt0.s with $TOOLS/newlib/libgloss/or32/crt0.S - * Morpheo/IPs/systemC/shared/ - - mapping_memory.h - -6) Enjoy Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Constant/Constant_OpenRISC.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Constant/Constant_OpenRISC.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Constant/Constant_OpenRISC.h (revision 57) @@ -15,9 +15,5 @@ #define _size_instruction_log2 5 - //------------------------------------------------------[ Control ]----- - typedef bool Tcontrol_t; - //----------------------------------------------------[ Operation ]----- - typedef uint8_t Toperation_t; // #define _nb_operation 32 // #define _size_operation 5 @@ -57,5 +53,4 @@ //--------------------------------------------------[ destination ]----- - typedef uint8_t Tdestination1_t; #define _size_destination1 4 @@ -66,5 +61,4 @@ #define mask_DESTINATION1_MAC_UNIT 0x8 - typedef uint8_t Tdestination2_t; #define _size_destination2 3 @@ -75,5 +69,4 @@ //----------------------------------------------------[ exec_flag ]----- - typedef uint8_t Texec_flag_t; #define _size_exec_flag 2 @@ -84,5 +77,4 @@ //---------------------------------------------------[ exec_excep ]----- - typedef bool Texec_excep_t; #define _size_exec_excep 1 @@ -91,5 +83,4 @@ //----------------------------------------------------[ Condition ]----- - typedef uint8_t Tcondition_t; #define _size_condition 3 @@ -102,6 +93,4 @@ //-------------------------------------------------[ branch_state ]----- - typedef uint8_t Tbranch_state_t; - #define cst_BRANCH_STATE_NONE 0x0 // 0 0 #define cst_BRANCH_STATE_NSPEC_TAKE 0x1 // 0 1 -> incondionnal Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_mixte.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_mixte.cfg (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_mixte.cfg (revision 57) @@ -0,0 +1,6 @@ +RegisterFile_Monolithic +0 0 *2 # nb_port_read +0 0 *2 # nb_port_write +1 8 *2 # nb_port_read_write +32 32 *2 # nb_word +32 32 *2 # size_word Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_read.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_read.cfg (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_read.cfg (revision 57) @@ -0,0 +1,6 @@ +RegisterFile_Monolithic +1 8 *2 # nb_port_read +1 1 *2 # nb_port_write +0 0 *2 # nb_port_read_write +512 512 *2 # nb_word +32 32 *2 # size_word Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_write.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_write.cfg (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/config_write.cfg (revision 57) @@ -0,0 +1,6 @@ +RegisterFile_Monolithic +1 1 *2 # nb_port_read +2 8 *2 # nb_port_write +0 0 *2 # nb_port_read_write +512 512 *2 # nb_word +32 32 *2 # size_word Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration.cfg (revision 56) +++ (revision ) @@ -1,6 +1,0 @@ -RegisterFile_Monolithic -0 0 *2 # nb_port_read -0 0 *2 # nb_port_write -1 8 *2 # nb_port_read_write -32 32 *2 # nb_word -32 32 *2 # size_word Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info (revision 57) @@ -20,2 +20,17 @@ target_dep RegisterFile_Monolithic_3.prj RegisterFile_Monolithic_3_Pack.vhdl RegisterFile_Monolithic_3.vhdl +# RegisterFile_Monolithic_4 +target_dep all RegisterFile_Monolithic_4.ngc +target_dep RegisterFile_Monolithic_4.ngc RegisterFile_Monolithic_4.prj +target_dep RegisterFile_Monolithic_4.prj RegisterFile_Monolithic_4_Pack.vhdl RegisterFile_Monolithic_4.vhdl + +# RegisterFile_Monolithic_5 +target_dep all RegisterFile_Monolithic_5.ngc +target_dep RegisterFile_Monolithic_5.ngc RegisterFile_Monolithic_5.prj +target_dep RegisterFile_Monolithic_5.prj RegisterFile_Monolithic_5_Pack.vhdl RegisterFile_Monolithic_5.vhdl + +# RegisterFile_Monolithic_6 +target_dep all RegisterFile_Monolithic_6.ngc +target_dep RegisterFile_Monolithic_6.ngc RegisterFile_Monolithic_6.prj +target_dep RegisterFile_Monolithic_6.prj RegisterFile_Monolithic_6_Pack.vhdl RegisterFile_Monolithic_6.vhdl + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp (revision 57) @@ -7,5 +7,5 @@ */ -#define NB_ITERATION 2 +#define NB_ITERATION 1 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h" Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h (revision 57) @@ -27,4 +27,5 @@ #include "Behavioural/include/Vhdl.h" #endif +#include "Behavioural/include/Usage.h" using namespace std; @@ -46,6 +47,7 @@ // Parameters protected : const string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; - protected : const Parameters * _param; #ifdef STATISTICS private : Statistics * _stat; @@ -95,21 +97,24 @@ SC_HAS_PROCESS (RegisterFile_Monolithic); #endif - - public : RegisterFile_Monolithic ( + public : RegisterFile_Monolithic + ( #ifdef SYSTEMC - sc_module_name name, + sc_module_name name #else - string name, + string name #endif #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics * param_statistics, + ,morpheo::behavioural::Parameters_Statistics * param_statistics #endif - Parameters * param ); + ,Parameters * param + ,morpheo::behavioural::Tusage_t usage=USE_ALL + ); + public : ~RegisterFile_Monolithic (void); -#ifdef SYSTEMC private : void allocation (void); private : void deallocation (void); +#ifdef SYSTEMC public : void transition (void); //public : void genMoore (void) {/* empty */}; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Types.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Types.h (revision 57) @@ -9,5 +9,5 @@ */ -#include "Common/include/Types.h" +#include "Behavioural/include/Types.h" namespace morpheo { Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp (revision 57) @@ -14,24 +14,25 @@ namespace registerfile_monolithic { - RegisterFile_Monolithic::RegisterFile_Monolithic ( + RegisterFile_Monolithic::RegisterFile_Monolithic + ( #ifdef SYSTEMC - sc_module_name name, + sc_module_name name, #else - string name , + string name , #endif #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics * param_statistics, + morpheo::behavioural::Parameters_Statistics * param_statistics, #endif - morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * param ): - _name (name), - _param (param) + morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name), + _param (param), + _usage (usage) { log_printf(FUNC,RegisterFile_Monolithic,"RegisterFile_Monolithic","Begin"); -#ifdef SYSTEMC log_printf(INFO,RegisterFile_Monolithic,"RegisterFile_Monolithic","Allocation"); - allocation (); -#endif #ifdef STATISTICS @@ -47,42 +48,45 @@ #ifdef SYSTEMC - SC_METHOD (transition); - dont_initialize (); - sensitive_pos << *(in_CLOCK); + if (_usage & USE_SYSTEMC) + { + SC_METHOD (transition); + dont_initialize (); + sensitive_pos << *(in_CLOCK); + + SC_METHOD (genMealy_read); + dont_initialize (); + sensitive_neg << *(in_CLOCK); + for (uint32_t i=0; i<_param->_nb_port_read; i++) + sensitive << *(in_READ_VAL [i]) + << *(in_READ_ADDRESS [i]); + for (uint32_t i=0; i<_param->_nb_port_read_write; i++) + sensitive << *(in_READ_WRITE_VAL [i]) + << *(in_READ_WRITE_RW [i]) + << *(in_READ_WRITE_ADDRESS [i]); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param->_nb_port_read; i++) + { + (*(out_READ_DATA [i])) (*( in_READ_VAL [i])); + (*(out_READ_DATA [i])) (*( in_READ_ADDRESS [i])); + } + for (uint32_t i=0; i<_param->_nb_port_read_write; i++) + { + (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_VAL [i])); + (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_RW [i])); + (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_ADDRESS [i])); + } +# endif + + for (uint32_t i=0; i<_param->_nb_port_read ; i++) + PORT_WRITE(out_READ_ACK [i], 1); + for (uint32_t i=0; i<_param->_nb_port_write ; i++) + PORT_WRITE(out_WRITE_ACK [i], 1); + for (uint32_t i=0; i<_param->_nb_port_read_write ; i++) + PORT_WRITE(out_READ_WRITE_ACK [i], 1); + } +#endif - SC_METHOD (genMealy_read); - dont_initialize (); - sensitive_neg << *(in_CLOCK); - for (uint32_t i=0; i<_param->_nb_port_read; i++) - sensitive << *(in_READ_VAL [i]) - << *(in_READ_ADDRESS [i]); - for (uint32_t i=0; i<_param->_nb_port_read_write; i++) - sensitive << *(in_READ_WRITE_VAL [i]) - << *(in_READ_WRITE_RW [i]) - << *(in_READ_WRITE_ADDRESS [i]); - -#ifdef SYSTEMCASS_SPECIFIC - // List dependency information - for (uint32_t i=0; i<_param->_nb_port_read; i++) - { - (*(out_READ_DATA [i])) (*( in_READ_VAL [i])); - (*(out_READ_DATA [i])) (*( in_READ_ADDRESS [i])); - } - for (uint32_t i=0; i<_param->_nb_port_read_write; i++) - { - (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_VAL [i])); - (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_RW [i])); - (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_ADDRESS [i])); - } -#endif - - for (uint32_t i=0; i<_param->_nb_port_read ; i++) - PORT_WRITE(out_READ_ACK [i], 1); - for (uint32_t i=0; i<_param->_nb_port_write ; i++) - PORT_WRITE(out_WRITE_ACK [i], 1); - for (uint32_t i=0; i<_param->_nb_port_read_write ; i++) - PORT_WRITE(out_READ_WRITE_ACK [i], 1); -#endif - log_printf(FUNC,RegisterFile_Monolithic,"RegisterFile_Monolithic","End"); }; @@ -95,7 +99,5 @@ #endif -#ifdef SYSTEMC deallocation (); -#endif }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp (revision 57) @@ -1,3 +1,2 @@ -#ifdef SYSTEMC /* * $Id$ @@ -17,5 +16,5 @@ void RegisterFile_Monolithic::allocation (void) { - _component = new Component (); + _component = new Component (_usage); Entity * entity = _component->set_entity (_name @@ -133,3 +132,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp (revision 57) @@ -1,3 +1,2 @@ -#ifdef SYSTEMC /* * $Id$ @@ -19,28 +18,31 @@ delete _component; - delete in_CLOCK; - delete in_NRESET; - // ----- Interface Read - delete [] in_READ_VAL ; - delete [] out_READ_ACK ; - delete [] in_READ_ADDRESS; - delete [] out_READ_DATA ; - - // ----- Interface Write - delete [] in_WRITE_VAL ; - delete [] out_WRITE_ACK ; - delete [] in_WRITE_ADDRESS; - delete [] in_WRITE_DATA ; - - // ----- Interface Read_Write - delete [] in_READ_WRITE_VAL ; - delete [] out_READ_WRITE_ACK ; - delete [] in_READ_WRITE_RW ; - delete [] in_READ_WRITE_ADDRESS; - delete [] in_READ_WRITE_WDATA ; - delete [] out_READ_WRITE_RDATA ; - - // ----- Register - delete [] reg_DATA; + if (_usage & USE_SYSTEMC) + { + delete in_CLOCK; + delete in_NRESET; + // ----- Interface Read + delete [] in_READ_VAL ; + delete [] out_READ_ACK ; + delete [] in_READ_ADDRESS; + delete [] out_READ_DATA ; + + // ----- Interface Write + delete [] in_WRITE_VAL ; + delete [] out_WRITE_ACK ; + delete [] in_WRITE_ADDRESS; + delete [] in_WRITE_DATA ; + + // ----- Interface Read_Write + delete [] in_READ_WRITE_VAL ; + delete [] out_READ_WRITE_ACK ; + delete [] in_READ_WRITE_RW ; + delete [] in_READ_WRITE_ADDRESS; + delete [] in_READ_WRITE_WDATA ; + delete [] out_READ_WRITE_RDATA ; + + // ----- Register + delete [] reg_DATA; + } }; @@ -50,3 +52,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/Makefile.deps (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/Makefile.deps (revision 57) @@ -13,11 +13,21 @@ include $(DIR_MORPHEO)/Behavioural/Makefile.deps endif +ifndef RegisterFile_Monolithic +include $(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/Makefile.deps +endif +ifndef Select_Priority_Fixed +include $(DIR_MORPHEO)/Behavioural/Generic/Select/Select_Priority_Fixed/Makefile.deps +endif #-----[ Library ]------------------------------------------ -RegisterFile_Multi_Banked_LIBRARY = -lRegisterFile_Multi_Banked \ - $(Behavioural_LIBRARY) +RegisterFile_Multi_Banked_LIBRARY = -lRegisterFile_Multi_Banked \ + $(Behavioural_LIBRARY) \ + $(RegisterFile_Monolithic_LIBRARY) \ + $(Select_Priority_Fixed_LIBRARY) RegisterFile_Multi_Banked_DIR_LIBRARY = -L$(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/lib \ - $(Behavioural_DIR_LIBRARY) + $(Behavioural_DIR_LIBRARY) \ + $(RegisterFile_Monolithic_DIR_LIBRARY) \ + $(Select_Priority_Fixed_DIR_LIBRARY) #-----[ Rules ]-------------------------------------------- @@ -25,9 +35,13 @@ RegisterFile_Multi_Banked_library : @\ - $(MAKE) Behavioural_library; \ + $(MAKE) Behavioural_library; \ + $(MAKE) RegisterFile_Monolithic_library; \ + $(MAKE) Select_Priority_Fixed_library; \ $(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked --makefile=Makefile; RegisterFile_Multi_Banked_library_clean : @\ - $(MAKE) Behavioural_library_clean; \ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) RegisterFile_Monolithic_library_clean; \ + $(MAKE) Select_Priority_Fixed_library_clean; \ $(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp (revision 57) @@ -7,6 +7,6 @@ */ -#define NB_ITERATION 1024 -#define CYCLE_MAX (512*NB_ITERATION) +#define NB_ITERATION 1 +#define CYCLE_MAX (10240*NB_ITERATION) #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/include/test.h" @@ -34,9 +34,14 @@ cout << "<" << name << "> : Simulation SystemC" << endl; + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics(5,50); +#endif + RegisterFile_Multi_Banked * _RegisterFile_Multi_Banked = new RegisterFile_Multi_Banked (name.c_str(), #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics(5,50), + _param_stat, #endif - *_param); + _param); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Parameters.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Parameters.h (revision 57) @@ -73,7 +73,7 @@ // A lot of table to the partial crossbar public : uint32_t * _link_port_read_to_bank_read ; -// public : uint32_t * _link_port_read_to_num_bank ; +//public : uint32_t * _link_port_read_to_num_bank ; public : uint32_t * _link_port_write_to_bank_write; -// public : uint32_t * _link_port_write_to_num_bank ; +//public : uint32_t * _link_port_write_to_num_bank ; //-----[ methods ]----------------------------------------------------------- Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h (revision 57) @@ -43,7 +43,7 @@ // -----[ fields ]---------------------------------------------------- // Parameters - protected : const string _name; + protected : const string _name; - protected : const Parameters _param; + protected : const Parameters * _param; //#ifdef STATISTICS // protected : const morpheo::behavioural::Parameters_Statistics _param_statistics; @@ -98,14 +98,13 @@ public : RegisterFile_Multi_Banked ( #ifdef SYSTEMC - sc_module_name name, + sc_module_name name, #else - string name, + string name, #endif #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics param_statistics, + morpheo::behavioural::Parameters_Statistics * param_statistics, #endif - Parameters param ); + Parameters * param ); - public : RegisterFile_Multi_Banked (Parameters param ); public : ~RegisterFile_Multi_Banked (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Statistics.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Statistics.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Statistics.h (revision 57) @@ -28,10 +28,10 @@ { // -----[ fields ]---------------------------------------------------- - private : const Parameters _parameters; + private : const Parameters * _parameters; // -----[ methods ]--------------------------------------------------- - public : Statistics (string name , - morpheo::behavioural::Parameters_Statistics parameters_statistics , - Parameters parameters + public : Statistics (string name , + morpheo::behavioural::Parameters_Statistics * parameters_statistics , + Parameters * parameters ); //public : Statistics (Statistics & stat); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Types.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Types.h (revision 57) @@ -9,5 +9,5 @@ */ -#include "Common/include/Types.h" +#include "Behavioural/include/Types.h" namespace morpheo { Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Parameters.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Parameters.cpp (revision 57) @@ -53,33 +53,16 @@ _link_port_read_to_bank_read = new uint32_t [_nb_port_read ]; -// _link_port_read_to_num_bank = new uint32_t [_nb_port_read ]; _link_port_write_to_bank_write = new uint32_t [_nb_port_write]; -// _link_port_write_to_num_bank = new uint32_t [_nb_port_write]; -// uint32_t _nb_port_bank_by_bank_read_port [_nb_port_read_by_bank ]; -// uint32_t _nb_port_bank_by_bank_write_port [_nb_port_write_by_bank]; - // init -// for (uint32_t i=0; i<_nb_port_read_by_bank ;i++) -// _nb_port_bank_by_bank_read_port [i] = 0; - - for (uint32_t i=0; i<_nb_port_read ;i++) + for (uint32_t i=0; i<_nb_port_read ;i++) { uint32_t x = i%_nb_port_read_by_bank; _link_port_read_to_bank_read [i] = x; -// _link_port_read_to_num_bank [i] = _nb_port_bank_by_bank_read_port [x]; -// _nb_port_bank_by_bank_read_port [x] ++; } - - // init -// for (uint32_t i=0; i<_nb_port_write_by_bank ;i++) -// _nb_port_bank_by_bank_write_port [i] = 0; - - for (uint32_t i=0; i<_nb_port_write ;i++) + for (uint32_t i=0; i<_nb_port_write;i++) { uint32_t x = i%_nb_port_write_by_bank; _link_port_write_to_bank_write [i] = x; -// _link_port_write_to_num_bank [i] = _nb_port_bank_by_bank_write_port [x]; -// _nb_port_bank_by_bank_write_port [x] ++; } @@ -87,15 +70,14 @@ log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_read_to_bank_read"); for (uint32_t i=0; i<_nb_port_read ;i++) + { log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * Read in [%d] to out [%d]",i,_link_port_read_to_bank_read [i]); -// log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_read_to_num_bank "); -// for (uint32_t i=0; i<_nb_port_read ;i++) -// log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * Read in [%d] to bank [%d]",i,_link_port_read_to_num_bank [i]); - + printf(" * Read in [%d] to out [%d]\n",i,_link_port_read_to_bank_read [i]); + } log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_write_to_bank_write"); for (uint32_t i=0; i<_nb_port_write ;i++) - log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * Write in [%d] to out [%d]",i,_link_port_write_to_bank_write [i]); -// log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_write_to_num_bank "); -// for (uint32_t i=0; i<_nb_port_write ;i++) -// log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * Write in [%d] to bank [%d]",i,_link_port_write_to_num_bank [i]); + { + log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * Write in [%d] to out [%d]",i,_link_port_write_to_bank_write [i]); + printf(" * Write in [%d] to out [%d]\n",i,_link_port_write_to_bank_write [i]); + } } // else : don't allocate Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked.cpp (revision 57) @@ -21,7 +21,7 @@ #endif #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics param_statistics, + morpheo::behavioural::Parameters_Statistics * param_statistics, #endif - morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters param ): + morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters * param ): _name (name) ,_param (param) @@ -56,5 +56,5 @@ #ifdef SYSTEMC // Function pointer - if (_param._crossbar == FULL_CROSSBAR) + if (_param->_crossbar == FULL_CROSSBAR) { function_transition = &morpheo::behavioural::generic::registerfile::registerfile_multi_banked::RegisterFile_Multi_Banked:: full_crossbar_transition; @@ -84,5 +84,5 @@ dont_initialize (); sensitive_neg << *(in_CLOCK); - for (uint32_t i=0; i<_param._nb_port_read; i++) + for (uint32_t i=0; i<_param->_nb_port_read; i++) sensitive << *( in_READ_VAL [i]) << *( in_READ_ADDRESS [i]); @@ -90,5 +90,5 @@ #ifdef SYSTEMCASS_SPECIFIC // List dependency information - for (uint32_t i=0; i<_param._nb_port_read; i++) + for (uint32_t i=0; i<_param->_nb_port_read; i++) { (*(out_READ_ACK [i])) (*( in_READ_VAL [i])); @@ -97,4 +97,10 @@ (*(out_READ_DATA [i])) (*( in_READ_ADDRESS [i])); } +// for (uint32_t i=0; i<_param->_nb_port_read_write; i++) +// { +// (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_VAL [i])); +// (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_RW [i])); +// (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_ADDRESS [i])); +// } #endif @@ -102,5 +108,5 @@ dont_initialize (); sensitive_neg << *(in_CLOCK); - for (uint32_t i=0; i<_param._nb_port_write; i++) + for (uint32_t i=0; i<_param->_nb_port_write; i++) sensitive << *( in_WRITE_VAL [i]) << *( in_WRITE_ADDRESS [i]) @@ -109,5 +115,5 @@ #ifdef SYSTEMCASS_SPECIFIC // List dependency information - for (uint32_t i=0; i<_param._nb_port_write; i++) + for (uint32_t i=0; i<_param->_nb_port_write; i++) { (*(out_WRITE_ACK [i])) (*( in_WRITE_VAL [i])); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_address_xxx.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_address_xxx.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_address_xxx.cpp (revision 57) @@ -20,5 +20,5 @@ log_printf(FUNC,RegisterFile_Multi_Banked,"address_bank","Begin"); - Taddress_t _return = _param._bank_mask & (address >> _param._bank_shift); + Taddress_t _return = _param->_bank_mask & (address >> _param->_bank_shift); log_printf(FUNC,RegisterFile_Multi_Banked,"address_bank","End"); @@ -31,5 +31,5 @@ log_printf(FUNC,RegisterFile_Multi_Banked,"address_num_reg","Begin"); - Taddress_t _return = _param._num_reg_mask & (address >> _param._num_reg_shift); + Taddress_t _return = _param->_num_reg_mask & (address >> _param->_num_reg_shift); log_printf(FUNC,RegisterFile_Multi_Banked,"address_num_reg","End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp (revision 57) @@ -48,10 +48,10 @@ // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_READ_VAL = new SC_IN (Tcontrol_t) * [_param._nb_port_read]; - out_READ_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_port_read]; - in_READ_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_port_read]; - out_READ_DATA = new SC_OUT(Tdata_t ) * [_param._nb_port_read]; + in_READ_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read]; + out_READ_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read]; + in_READ_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read]; + out_READ_DATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read]; - for (uint32_t i=0; i<_param._nb_port_read; i++) + for (uint32_t i=0; i<_param->_nb_port_read; i++) { Interface_fifo * interface = _interfaces->set_interface("read_"+toString(i) @@ -65,16 +65,16 @@ in_READ_VAL [i] = interface->set_signal_valack_in ("val" , VAL); out_READ_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); - in_READ_ADDRESS [i] = interface->set_signal_in ("address", static_cast(log2(_param._nb_word))); - out_READ_DATA [i] = interface->set_signal_out ("data" , _param._size_word); + in_READ_ADDRESS [i] = interface->set_signal_in ("address", static_cast(log2(_param->_nb_word))); + out_READ_DATA [i] = interface->set_signal_out ("data" , _param->_size_word); } // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_port_write]; - out_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_port_write]; - in_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_port_write]; - in_WRITE_DATA = new SC_IN (Tdata_t ) * [_param._nb_port_write]; + in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_write]; + out_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_write]; + in_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_write]; + in_WRITE_DATA = new SC_IN (Tdata_t ) * [_param->_nb_port_write]; - for (uint32_t i=0; i<_param._nb_port_write; i++) + for (uint32_t i=0; i<_param->_nb_port_write; i++) { Interface_fifo * interface = _interfaces->set_interface("write_"+toString(i) @@ -88,17 +88,17 @@ in_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); out_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); - in_WRITE_ADDRESS [i] = interface->set_signal_in ("address", static_cast(log2(_param._nb_word))); - in_WRITE_DATA [i] = interface->set_signal_in ("data" , _param._size_word); + in_WRITE_ADDRESS [i] = interface->set_signal_in ("address", static_cast(log2(_param->_nb_word))); + in_WRITE_DATA [i] = interface->set_signal_in ("data" , _param->_size_word); } // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - reg_DATA = new SC_REGISTER (Tdata_t) ** [_param._nb_bank]; + reg_DATA = new SC_REGISTER (Tdata_t) ** [_param->_nb_bank]; - for (uint32_t i=0; i<_param._nb_bank; i++) + for (uint32_t i=0; i<_param->_nb_bank; i++) { - reg_DATA [i] = new SC_REGISTER (Tdata_t) * [_param._nb_word]; + reg_DATA [i] = new SC_REGISTER (Tdata_t) * [_param->_nb_word]; - for (uint32_t j=0; j<_param._nb_word; j++) + for (uint32_t j=0; j<_param->_nb_word; j++) { string rename = "reg_DATA_" + toString(i) + "_" + toString(j); @@ -108,7 +108,7 @@ // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - internal_WRITE_VAL = new bool [_param._nb_port_write]; - internal_WRITE_BANK = new Taddress_t [_param._nb_port_write]; - internal_WRITE_NUM_REG = new Taddress_t [_param._nb_port_write]; + internal_WRITE_VAL = new bool [_param->_nb_port_write]; + internal_WRITE_BANK = new Taddress_t [_param->_nb_port_write]; + internal_WRITE_NUM_REG = new Taddress_t [_param->_nb_port_write]; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_read.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_read.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_read.cpp (revision 57) @@ -21,11 +21,11 @@ log_printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read","Begin"); - bool read_port_use [_param._nb_bank][_param._nb_port_read_by_bank]; + bool read_port_use [_param->_nb_bank][_param->_nb_port_read_by_bank]; - for (uint32_t i=0; i<_param._nb_bank; i++) - for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) + for (uint32_t i=0; i<_param->_nb_bank; i++) + for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) read_port_use [i][j]=false; - for (uint32_t i=0; i<_param._nb_port_read; i++) + for (uint32_t i=0; i<_param->_nb_port_read; i++) { bool val = PORT_READ(in_READ_VAL [i]); @@ -43,5 +43,5 @@ // Search loop - for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) + for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) { // find a unbusy port on this bank Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_write.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_write.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_write.cpp (revision 57) @@ -21,11 +21,11 @@ log_printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_genMealy_write","Begin"); - bool write_port_use [_param._nb_bank][_param._nb_port_write_by_bank]; + bool write_port_use [_param->_nb_bank][_param->_nb_port_write_by_bank]; - for (uint32_t i=0; i<_param._nb_bank; i++) - for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) + for (uint32_t i=0; i<_param->_nb_bank; i++) + for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) write_port_use [i][j]=false; - for (uint32_t i=0; i<_param._nb_port_write; i++) + for (uint32_t i=0; i<_param->_nb_port_write; i++) { bool val = PORT_READ(in_WRITE_VAL [i]); @@ -44,5 +44,5 @@ // Search loop - for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) + for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) { // find a unbusy port on this bank Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_read.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_read.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_read.cpp (revision 57) @@ -21,11 +21,11 @@ log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_read","Begin"); - bool read_port_use [_param._nb_bank][_param._nb_port_read_by_bank]; + bool read_port_use [_param->_nb_bank][_param->_nb_port_read_by_bank]; - for (uint32_t i=0; i<_param._nb_bank; i++) - for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) + for (uint32_t i=0; i<_param->_nb_bank; i++) + for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) read_port_use [i][j]=false; - for (uint32_t i=0; i<_param._nb_port_read; i++) + for (uint32_t i=0; i<_param->_nb_port_read; i++) { bool val = PORT_READ(in_READ_VAL [i]); @@ -43,8 +43,8 @@ // // Search loop -// for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) +// for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) // { - uint32_t j = _param._link_port_read_to_bank_read [i]; + uint32_t j = _param->_link_port_read_to_bank_read [i]; // find a unbusy port on this bank Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.cpp (revision 57) @@ -21,10 +21,10 @@ log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_write","Begin"); - bool write_port_use [_param._nb_bank][_param._nb_port_write_by_bank]; - for (uint32_t i=0; i<_param._nb_bank; i++) - for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) + bool write_port_use [_param->_nb_bank][_param->_nb_port_write_by_bank]; + for (uint32_t i=0; i<_param->_nb_bank; i++) + for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) write_port_use [i][j]=false; - for (uint32_t i=0; i<_param._nb_port_write; i++) + for (uint32_t i=0; i<_param->_nb_port_write; i++) { bool val = PORT_READ(in_WRITE_VAL [i]); @@ -43,7 +43,7 @@ // // Search loop -// for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) +// for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) // { - uint32_t j = _param._link_port_write_to_bank_write [i]; + uint32_t j = _param->_link_port_write_to_bank_write [i]; // find a unbusy port on this bank Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_transition.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_transition.cpp (revision 57) @@ -24,5 +24,5 @@ // (this->*function_transition) (); - for (uint32_t i=0; i<_param._nb_port_write; i++) + for (uint32_t i=0; i<_param->_nb_port_write; i++) { if (internal_WRITE_VAL [i] == 1) @@ -34,6 +34,4 @@ } } - - #ifdef STATISTICS Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl.cpp (revision 57) @@ -8,4 +8,6 @@ #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h" +#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h" +#include "Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h" #include "Behavioural/include/Vhdl.h" @@ -16,9 +18,180 @@ namespace registerfile_multi_banked { - void RegisterFile_Multi_Banked::vhdl (void) { log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl","Begin"); - + + //=================================== + //===== Component ===== + //=================================== + + //----- RegisterFile_Monolithic ----- + + morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * param_bank; + morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic * bank; + + // Create all bank. All bank is identical + param_bank = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters + (_param->_nb_port_read_by_bank + ,_param->_nb_port_write_by_bank + ,0 // mixte port + ,_param->_nb_word/_param->_nb_bank + ,_param->_size_word); + + string bank_name = _name + "_bank"; + bank = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic + (bank_name.c_str() +#ifdef STATISTICS + ,NULL +#endif + ,param_bank + ,USE_VHDL); + + _component->set_component(bank->_component +#ifdef POSITION + , 0, 0, 0, 0 +#endif + , INSTANCE_LIBRARY + ); + + + //----- Select_Priority_Fixed ----- + + // Create all select_unit : + // * 4 units : to the read port, "quotient" ports and "rest" ports. Idem to the write port. + // * for a FULL_CROSSBAR, there are no "rest" ports + uint32_t nb_select_port_1 ; + uint32_t nb_select_port_2 ; + uint32_t nb_select_port_3 ; + uint32_t nb_select_port_4 ; + + if (_param->_crossbar == FULL_CROSSBAR) + { + nb_select_port_1 = _param->_nb_port_read ; + nb_select_port_3 = _param->_nb_port_write; + nb_select_port_2 = nb_select_port_4 = 0; + } + else + { + nb_select_port_2=(_param->_nb_port_read )/_param->_nb_port_read_by_bank; + nb_select_port_1=((_param->_nb_port_read%_param->_nb_port_read_by_bank)==0)?0:(nb_select_port_2+1); + nb_select_port_4=(_param->_nb_port_write )/_param->_nb_port_write_by_bank; + nb_select_port_3=((_param->_nb_port_write%_param->_nb_port_write_by_bank)==0)?0:(nb_select_port_4+1); + } + +// cout << "nb_select_port_1 : " << nb_select_port_1 << endl; +// cout << "nb_select_port_2 : " << nb_select_port_2 << endl; +// cout << "nb_select_port_3 : " << nb_select_port_3 << endl; +// cout << "nb_select_port_4 : " << nb_select_port_4 << endl; + + morpheo::behavioural::generic::select::select_priority_fixed::Parameters *param_select1 = NULL; + morpheo::behavioural::generic::select::select_priority_fixed::Parameters *param_select2 = NULL; + morpheo::behavioural::generic::select::select_priority_fixed::Parameters *param_select3 = NULL; + morpheo::behavioural::generic::select::select_priority_fixed::Parameters *param_select4 = NULL; + + morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed *select1 = NULL; + morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed *select2 = NULL; + morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed *select3 = NULL; + morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed *select4 = NULL; + + bool have_select1 = ((nb_select_port_1 != 0 )); + bool have_select2 = ((nb_select_port_2 != 0 ) and + (nb_select_port_2 != nb_select_port_1)); + bool have_select3 = ((nb_select_port_3 != 0 ) and + (nb_select_port_3 != nb_select_port_2) and + (nb_select_port_3 != nb_select_port_1)); + bool have_select4 = ((nb_select_port_4 != 0 ) and + (nb_select_port_4 != nb_select_port_3) and + (nb_select_port_4 != nb_select_port_2) and + (nb_select_port_4 != nb_select_port_1) ); + + string select_name1; + string select_name2; + string select_name3; + string select_name4; + + if (have_select1) + { + select_name1 = _name+"_select_"+toString(nb_select_port_1)+"_ports"; + param_select1 = new morpheo::behavioural::generic::select::select_priority_fixed::Parameters (nb_select_port_1,true, false); + select1 = new morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed + (select_name1.c_str() +#ifdef STATISTICS + ,NULL +#endif + ,param_select1 + ,USE_VHDL); + + _component->set_component(select1->_component +#ifdef POSITION + , 0, 0, 0, 0 +#endif + , INSTANCE_LIBRARY + ); + } + + if (have_select2) + { + select_name2 = _name+"_select_"+toString(nb_select_port_2)+"_ports"; + + param_select2 = new morpheo::behavioural::generic::select::select_priority_fixed::Parameters (nb_select_port_2,true, false); + select2 = new morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed + (select_name2.c_str() +#ifdef STATISTICS + ,NULL +#endif + ,param_select2 + ,USE_VHDL); + + _component->set_component(select2->_component +#ifdef POSITION + , 0, 0, 0, 0 +#endif + , INSTANCE_LIBRARY + ); + } + + if (have_select3) + { + select_name3 = _name+"_select_"+toString(nb_select_port_3)+"_ports"; + + param_select3 = new morpheo::behavioural::generic::select::select_priority_fixed::Parameters (nb_select_port_3,true, false); + select3 = new morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed + (select_name3.c_str() +#ifdef STATISTICS + ,NULL +#endif + ,param_select3 + ,USE_VHDL); + + _component->set_component(select3->_component +#ifdef POSITION + , 0, 0, 0, 0 +#endif + , INSTANCE_LIBRARY + ); + } + + if (have_select4) + { + select_name4 = _name+"_select_"+toString(nb_select_port_4)+"_ports"; + + param_select4 = new morpheo::behavioural::generic::select::select_priority_fixed::Parameters (nb_select_port_4,true, false); + select4 = new morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed + (select_name4.c_str() +#ifdef STATISTICS + ,NULL +#endif + ,param_select4 + ,USE_VHDL); + + _component->set_component(select4->_component +#ifdef POSITION + , 0, 0, 0, 0 +#endif + , INSTANCE_LIBRARY + ); + } + Vhdl * vhdl = new Vhdl (_name); @@ -32,4 +205,26 @@ delete vhdl; + delete bank; + delete param_bank; + if (have_select1) + { + delete select1; + delete param_select1; + } + if (have_select2) + { + delete select2; + delete param_select2; + } + if (have_select3) + { + delete select3; + delete param_select3; + } + if (have_select4) + { + delete select4; + delete param_select4; + } log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl","End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_body.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_body.cpp (revision 57) @@ -20,4 +20,289 @@ log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_body","Begin"); + uint32_t read_select_limit ; + uint32_t read_nb_select1 ; + uint32_t read_nb_select2 ; + uint32_t write_select_limit; + uint32_t write_nb_select1 ; + uint32_t write_nb_select2 ; + + read_select_limit = _param->_nb_port_read%_param->_nb_port_read_by_bank; + read_nb_select2 = _param->_nb_port_read/_param->_nb_port_read_by_bank; + read_nb_select1 = (read_select_limit==0)?0:(read_nb_select2+1); + + write_select_limit= _param->_nb_port_write%_param->_nb_port_write_by_bank; + write_nb_select2 = _param->_nb_port_write/_param->_nb_port_write_by_bank; + write_nb_select1 = (write_select_limit==0)?0:(write_nb_select2+1); + + vhdl->set_body(""); + vhdl->set_body("-----------------------------------"); + vhdl->set_body("-- Instance bank "); + vhdl->set_body("-----------------------------------"); + vhdl->set_body(""); + + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + vhdl->set_body(_name+"_bank_"+toString(i)+" : "+_name+"_bank"); + vhdl->set_body("port map ("); + vhdl->set_body("\t in_CLOCK \t=>\tin_CLOCK "); + vhdl->set_body("\t, in_NRESET\t=>\tin_NRESET"); + for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) + { + vhdl->set_body("\t, in_READ_"+toString(j)+"_VAL \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_VAL"); + vhdl->set_body("\t,out_READ_"+toString(j)+"_ACK \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ACK"); + vhdl->set_body("\t, in_READ_"+toString(j)+"_ADDRESS \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ADDRESS"); + vhdl->set_body("\t,out_READ_"+toString(j)+"_DATA \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_DATA"); + } + for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) + { + vhdl->set_body("\t, in_WRITE_"+toString(j)+"_VAL \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_VAL"); + vhdl->set_body("\t,out_WRITE_"+toString(j)+"_ACK \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ACK"); + vhdl->set_body("\t, in_WRITE_"+toString(j)+"_ADDRESS \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ADDRESS"); + vhdl->set_body("\t, in_WRITE_"+toString(j)+"_DATA \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_DATA"); + } + + vhdl->set_body(");"); + vhdl->set_body(""); + } + + vhdl->set_body(""); + vhdl->set_body("-----------------------------------"); + vhdl->set_body("-- Instance select"); + vhdl->set_body("-- (1 select by port)"); + vhdl->set_body("-----------------------------------"); + vhdl->set_body(""); + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) + { + uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((jset_body(_name+"_read_select_"+toString(i)+"_"+toString(j)+" : "+_name+"_select_"+toString(nb_port)+"_ports"); + vhdl->set_body("port map ("); + for (uint32_t k=0; k_nb_port_read_by_bank*k+j; + string separator = ((k==0)?" ":","); + + vhdl->set_body("\t"+separator+" in_VAL_"+toString(k)+" \t=>\tinternal_READ_"+toString(i)+"_"+toString(num_port)+"_VAL"); + vhdl->set_body("\t,out_ACK_"+toString(k)+" \t=>\tinternal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+"_VAL"); + } + vhdl->set_body(");"); + vhdl->set_body(""); + } + + for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) + { + uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((jset_body(_name+"_write_select_"+toString(i)+"_"+toString(j)+" : "+_name+"_select_"+toString(nb_port)+"_ports"); + vhdl->set_body("port map ("); + for (uint32_t k=0; k_nb_port_write_by_bank*k+j; + string separator = ((k==0)?" ":","); + + vhdl->set_body("\t"+separator+" in_VAL_"+toString(k)+" \t=>\tinternal_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL"); + vhdl->set_body("\t,out_ACK_"+toString(k)+" \t=>\tinternal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL"); + } + vhdl->set_body(");"); + vhdl->set_body(""); + } + } + + vhdl->set_body(""); + vhdl->set_body("-----------------------------------"); + vhdl->set_body("-- Bank Val"); + vhdl->set_body("-----------------------------------"); + vhdl->set_body(""); + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) + { + uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((jset_body("internal_BANK_READ_"+toString(i)+"_"+toString(j)+ "_VAL <= '0'"); + for (uint32_t k=0; k_nb_port_read_by_bank*k+j; + + vhdl->set_body("\tor internal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+"_VAL"); + } + vhdl->set_body(";"); + } + for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) + { + uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((jset_body("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+ "_VAL <= '0'"); + for (uint32_t k=0; k_nb_port_write_by_bank*k+j; + + vhdl->set_body("\tor internal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL"); + } + vhdl->set_body(";"); + } + } + + vhdl->set_body(""); + vhdl->set_body("-----------------------------------"); + vhdl->set_body("-- Bank Address"); + vhdl->set_body("-----------------------------------"); + vhdl->set_body(""); + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) + { + uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((jset_body("internal_BANK_READ_"+toString(i)+"_"+toString(j)+ "_ADDRESS <="); + for (uint32_t k=1; k_nb_port_read_by_bank*k+j; + + vhdl->set_body("\tin_READ_"+toString(num_port)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+" when internal_READ_"+toString(i)+"_"+toString(num_port)+"_VAL='1' else"); + } + vhdl->set_body("\tin_READ_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+";"); +// vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); + } + for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) + { + uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((jset_body("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+ "_ADDRESS <="); + for (uint32_t k=1; k_nb_port_write_by_bank*k+j; + + vhdl->set_body("\tin_WRITE_"+toString(num_port)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+" when internal_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL='1' else"); + } + vhdl->set_body("\tin_WRITE_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+";"); +// vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); + } + } + + vhdl->set_body(""); + vhdl->set_body("-----------------------------------"); + vhdl->set_body("-- Bank Data"); + vhdl->set_body("-----------------------------------"); + vhdl->set_body(""); + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) + { + uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((jset_body("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+ "_DATA <="); + for (uint32_t k=1; k_nb_port_write_by_bank*k+j; + + vhdl->set_body("\tin_WRITE_"+toString(num_port)+"_DATA when internal_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL='1' else"); + } + vhdl->set_body("\tin_WRITE_"+toString(j)+"_DATA;"); +// vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); + } + } + + vhdl->set_body(""); + vhdl->set_body("-----------------------------------"); + vhdl->set_body("-- VAL (to Select)"); + vhdl->set_body("-----------------------------------"); + vhdl->set_body(""); + + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + for (uint32_t j=0; j<_param->_nb_port_read; j ++) + { + string address = (_param->_nb_bank==1)?"":("and (in_READ_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address-1,_param->_size_address_by_bank)+"="+std_logic_conv( _param->_size_address-_param->_size_address_by_bank,i)+")"); + + vhdl->set_body("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL <= '1' when (in_READ_"+toString(j)+"_VAL='1') "+address+"else '0';"); + } + for (uint32_t j=0; j<_param->_nb_port_write; j ++) + { + string address = (_param->_nb_bank==1)?"":("and (in_WRITE_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address-1,_param->_size_address_by_bank)+"="+std_logic_conv( _param->_size_address-_param->_size_address_by_bank,i)+")"); + vhdl->set_body("internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL <= '1' when (in_WRITE_"+toString(j)+"_VAL='1') "+address+" else '0';"); + } + } + + vhdl->set_body(""); + vhdl->set_body("-----------------------------------"); + vhdl->set_body("-- OUTPUT"); + vhdl->set_body("-----------------------------------"); + vhdl->set_body(""); + + if (_param->_crossbar == FULL_CROSSBAR) + { + for (uint32_t i=0; i<_param->_nb_port_read; i ++) + { + vhdl->set_body("out_READ_"+toString(i)+"_ACK <= "); + for (uint32_t j=0; j<_param->_nb_bank; j ++) + { + for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k ++) + { + vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(k)+"_ACK when internal_SELECT_READ_"+toString(j)+"_"+toString(k)+"_VAL = '1' else"); + } + } + vhdl->set_body("\t'0';"); + vhdl->set_body("out_READ_"+toString(i)+"_DATA <= "); + for (uint32_t j=0; j<_param->_nb_bank; j ++) + { + for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k ++) + { + vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(k)+"_DATA when internal_SELECT_READ_"+toString(j)+"_"+toString(k)+"_VAL = '1' else"); + } + } + vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); + } + for (uint32_t i=0; i<_param->_nb_port_write; i ++) + { + vhdl->set_body("out_WRITE_"+toString(i)+"_ACK <= "); + for (uint32_t j=0; j<_param->_nb_bank; j ++) + { + for (uint32_t k=0; k<_param->_nb_port_write_by_bank; k ++) + { + vhdl->set_body("\tinternal_BANK_WRITE_"+toString(j)+"_"+toString(k)+"_ACK when internal_SELECT_WRITE_"+toString(j)+"_"+toString(k)+"_VAL = '1' else"); + } + } + vhdl->set_body("\t'0';"); + } + } + else + { + for (uint32_t i=0; i<_param->_nb_port_read; i ++) + { + uint32_t link = _param->_link_port_read_to_bank_read[i]; + + vhdl->set_body("out_READ_"+toString(i)+"_ACK <= "); + for (uint32_t j=0; j<_param->_nb_bank; j ++) + { + vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(link)+"_ACK when internal_SELECT_READ_"+toString(j)+"_"+toString(link)+"_VAL = '1' else"); + } +// vhdl->set_body("\tinternal_BANK_READ_"+toString(0)+"_"+toString(link)+"_ACK;"); + vhdl->set_body("\t'0';"); + + vhdl->set_body("out_READ_"+toString(i)+"_DATA <= "); + for (uint32_t j=1; j<_param->_nb_bank; j ++) + { + vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(link)+"_DATA when internal_SELECT_READ_"+toString(j)+"_"+toString(i)+"_VAL = '1' else"); + } + vhdl->set_body("\tinternal_BANK_READ_"+toString(0)+"_"+toString(link)+"_DATA;"); +// vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); + } + for (uint32_t i=0; i<_param->_nb_port_write; i ++) + { + uint32_t link = _param->_link_port_write_to_bank_write[i]; + + vhdl->set_body("out_WRITE_"+toString(i)+"_ACK <= "); + for (uint32_t j=0; j<_param->_nb_bank; j ++) + { + vhdl->set_body("\tinternal_BANK_WRITE_"+toString(j)+"_"+toString(link)+"_ACK when internal_SELECT_WRITE_"+toString(j)+"_"+toString(i)+"_VAL = '1' else"); + } +// vhdl->set_body("\tinternal_BANK_WRITE_"+toString(0)+"_"+toString(link)+"_ACK;"); + vhdl->set_body("\t'0';"); + } + } + log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_body","End"); }; @@ -26,5 +311,4 @@ }; // end namespace registerfile }; // end namespace generic - }; // end namespace behavioural }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_declaration.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_declaration.cpp (revision 57) @@ -20,21 +20,32 @@ log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_declaration","Begin"); - vhdl->set_type ("Tregfile", "array (" + toString(_param._nb_word_by_bank-1) + " downto 0) of " + std_logic(_param._size_word)); + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + for (uint32_t j=0; j<_param->_nb_port_read; j ++) + { + vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1); + vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_ACK" ,1); + vhdl->set_signal ("internal_SELECT_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1); - vhdl->set_type ("Tbank" , "array (" + toString(_param._nb_bank) + " downto 0) of Tregfile"); - - vhdl->set_signal ("reg_DATA", "Tbank"); - - for (uint32_t i=0; i<_param._nb_bank; i++) - { - for (uint32_t j=0; j<_param._nb_port_read_by_bank; j ++) + } + for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j ++) { - vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1); - vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_PORT" ,static_cast(ceil(log2(_param._nb_port_read)))); + vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1); + vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ACK" ,1); + vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ADDRESS",_param->_size_address_by_bank); + vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_DATA" ,_param->_size_word); } - for (uint32_t j=0; j<_param._nb_port_write_by_bank; j ++) + for (uint32_t j=0; j<_param->_nb_port_write; j ++) { vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL" ,1); - vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_PORT",static_cast(ceil(log2(_param._nb_port_write)))); + vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_ACK" ,1); + vhdl->set_signal ("internal_SELECT_WRITE_"+toString(i)+"_"+toString(j)+"_VAL" ,1); + } + for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j ++) + { + vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_VAL" ,1); + vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ACK" ,1); + vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ADDRESS",_param->_size_address_by_bank); + vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_DATA" ,_param->_size_word); } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Statistics.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Statistics.cpp (revision 57) @@ -17,6 +17,6 @@ Statistics::Statistics (string name , - morpheo::behavioural::Parameters_Statistics parameters_statistics , - Parameters parameters + morpheo::behavioural::Parameters_Statistics * parameters_statistics , + Parameters * parameters ) : morpheo::behavioural::Statistics(name , Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/Makefile.mkf =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/Makefile.mkf (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/Makefile.mkf (revision 57) @@ -0,0 +1,180 @@ +# +# Makefile generated by MKF configure script +# + +all: Select_Priority_Fixed_0.ngc Select_Priority_Fixed_10.ngc Select_Priority_Fixed_11.ngc Select_Priority_Fixed_1.ngc Select_Priority_Fixed_2.ngc Select_Priority_Fixed_3.ngc Select_Priority_Fixed_4.ngc Select_Priority_Fixed_5.ngc Select_Priority_Fixed_6.ngc Select_Priority_Fixed_7.ngc Select_Priority_Fixed_8.ngc Select_Priority_Fixed_9.ngc + +Select_Priority_Fixed_0.ngc: Select_Priority_Fixed_0.prj + echo run -keep_hierarchy yes -iobuf no -top Select_Priority_Fixed_0 -ifn Select_Priority_Fixed_0.prj -ofn Select_Priority_Fixed_0.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst + +Select_Priority_Fixed_0.prj: Select_Priority_Fixed_0_Pack.vhdl Select_Priority_Fixed_0.vhdl + for i in Select_Priority_Fixed_0_Pack.vhdl Select_Priority_Fixed_0.vhdl ; do echo "vhdl work $$i" ; done > Select_Priority_Fixed_0.prj + +Select_Priority_Fixed_0_Pack.vhdl: + +Select_Priority_Fixed_0.vhdl: + +Select_Priority_Fixed_10.ngc: Select_Priority_Fixed_10.prj + echo run -keep_hierarchy yes -iobuf no -top Select_Priority_Fixed_10 -ifn Select_Priority_Fixed_10.prj -ofn Select_Priority_Fixed_10.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst + +Select_Priority_Fixed_10.prj: Select_Priority_Fixed_10_Pack.vhdl Select_Priority_Fixed_10.vhdl + for i in Select_Priority_Fixed_10_Pack.vhdl Select_Priority_Fixed_10.vhdl ; do echo "vhdl work $$i" ; done > Select_Priority_Fixed_10.prj + +Select_Priority_Fixed_10_Pack.vhdl: + +Select_Priority_Fixed_10.vhdl: + +Select_Priority_Fixed_11.ngc: Select_Priority_Fixed_11.prj + echo run -keep_hierarchy yes -iobuf no -top Select_Priority_Fixed_11 -ifn Select_Priority_Fixed_11.prj -ofn Select_Priority_Fixed_11.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst + +Select_Priority_Fixed_11.prj: Select_Priority_Fixed_11_Pack.vhdl Select_Priority_Fixed_11.vhdl + for i in Select_Priority_Fixed_11_Pack.vhdl Select_Priority_Fixed_11.vhdl ; do echo "vhdl work $$i" ; done > Select_Priority_Fixed_11.prj + +Select_Priority_Fixed_11_Pack.vhdl: + +Select_Priority_Fixed_11.vhdl: + +Select_Priority_Fixed_1.ngc: Select_Priority_Fixed_1.prj + echo run -keep_hierarchy yes -iobuf no -top Select_Priority_Fixed_1 -ifn Select_Priority_Fixed_1.prj -ofn Select_Priority_Fixed_1.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst + +Select_Priority_Fixed_1.prj: Select_Priority_Fixed_10_Pack.vhdl Select_Priority_Fixed_10.vhdl Select_Priority_Fixed_11_Pack.vhdl Select_Priority_Fixed_11.vhdl Select_Priority_Fixed_1_Pack.vhdl Select_Priority_Fixed_1.vhdl + for i in Select_Priority_Fixed_10_Pack.vhdl Select_Priority_Fixed_10.vhdl Select_Priority_Fixed_11_Pack.vhdl Select_Priority_Fixed_11.vhdl Select_Priority_Fixed_1_Pack.vhdl Select_Priority_Fixed_1.vhdl ; do echo "vhdl work $$i" ; done > Select_Priority_Fixed_1.prj + +Select_Priority_Fixed_1_Pack.vhdl: + +Select_Priority_Fixed_1.vhdl: + +Select_Priority_Fixed_2.ngc: Select_Priority_Fixed_2.prj + echo run -keep_hierarchy yes -iobuf no -top Select_Priority_Fixed_2 -ifn Select_Priority_Fixed_2.prj -ofn Select_Priority_Fixed_2.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst + +Select_Priority_Fixed_2.prj: Select_Priority_Fixed_2_Pack.vhdl Select_Priority_Fixed_2.vhdl + for i in Select_Priority_Fixed_2_Pack.vhdl Select_Priority_Fixed_2.vhdl ; do echo "vhdl work $$i" ; done > Select_Priority_Fixed_2.prj + +Select_Priority_Fixed_2_Pack.vhdl: + +Select_Priority_Fixed_2.vhdl: + +Select_Priority_Fixed_3.ngc: Select_Priority_Fixed_3.prj + echo run -keep_hierarchy yes -iobuf no -top Select_Priority_Fixed_3 -ifn Select_Priority_Fixed_3.prj -ofn Select_Priority_Fixed_3.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst + +Select_Priority_Fixed_3.prj: Select_Priority_Fixed_3_Pack.vhdl Select_Priority_Fixed_3.vhdl + for i in Select_Priority_Fixed_3_Pack.vhdl Select_Priority_Fixed_3.vhdl ; do echo "vhdl work $$i" ; done > Select_Priority_Fixed_3.prj + +Select_Priority_Fixed_3_Pack.vhdl: + +Select_Priority_Fixed_3.vhdl: + +Select_Priority_Fixed_4.ngc: Select_Priority_Fixed_4.prj + echo run -keep_hierarchy yes -iobuf no -top Select_Priority_Fixed_4 -ifn Select_Priority_Fixed_4.prj -ofn Select_Priority_Fixed_4.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst + +Select_Priority_Fixed_4.prj: Select_Priority_Fixed_4_Pack.vhdl Select_Priority_Fixed_4.vhdl + for i in Select_Priority_Fixed_4_Pack.vhdl Select_Priority_Fixed_4.vhdl ; do echo "vhdl work $$i" ; done > Select_Priority_Fixed_4.prj + +Select_Priority_Fixed_4_Pack.vhdl: + +Select_Priority_Fixed_4.vhdl: + +Select_Priority_Fixed_5.ngc: Select_Priority_Fixed_5.prj + echo run -keep_hierarchy yes -iobuf no -top Select_Priority_Fixed_5 -ifn Select_Priority_Fixed_5.prj -ofn Select_Priority_Fixed_5.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst + +Select_Priority_Fixed_5.prj: Select_Priority_Fixed_5_Pack.vhdl Select_Priority_Fixed_5.vhdl + for i in Select_Priority_Fixed_5_Pack.vhdl Select_Priority_Fixed_5.vhdl ; do echo "vhdl work $$i" ; done > Select_Priority_Fixed_5.prj + +Select_Priority_Fixed_5_Pack.vhdl: + +Select_Priority_Fixed_5.vhdl: + +Select_Priority_Fixed_6.ngc: Select_Priority_Fixed_6.prj + echo run -keep_hierarchy yes -iobuf no -top Select_Priority_Fixed_6 -ifn Select_Priority_Fixed_6.prj -ofn Select_Priority_Fixed_6.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst + +Select_Priority_Fixed_6.prj: Select_Priority_Fixed_6_Pack.vhdl Select_Priority_Fixed_6.vhdl + for i in Select_Priority_Fixed_6_Pack.vhdl Select_Priority_Fixed_6.vhdl ; do echo "vhdl work $$i" ; done > Select_Priority_Fixed_6.prj + +Select_Priority_Fixed_6_Pack.vhdl: + +Select_Priority_Fixed_6.vhdl: + +Select_Priority_Fixed_7.ngc: Select_Priority_Fixed_7.prj + echo run -keep_hierarchy yes -iobuf no -top Select_Priority_Fixed_7 -ifn Select_Priority_Fixed_7.prj -ofn Select_Priority_Fixed_7.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst + +Select_Priority_Fixed_7.prj: Select_Priority_Fixed_7_Pack.vhdl Select_Priority_Fixed_7.vhdl + for i in Select_Priority_Fixed_7_Pack.vhdl Select_Priority_Fixed_7.vhdl ; do echo "vhdl work $$i" ; done > Select_Priority_Fixed_7.prj + +Select_Priority_Fixed_7_Pack.vhdl: + +Select_Priority_Fixed_7.vhdl: + +Select_Priority_Fixed_8.ngc: Select_Priority_Fixed_8.prj + echo run -keep_hierarchy yes -iobuf no -top Select_Priority_Fixed_8 -ifn Select_Priority_Fixed_8.prj -ofn Select_Priority_Fixed_8.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst + +Select_Priority_Fixed_8.prj: Select_Priority_Fixed_8_Pack.vhdl Select_Priority_Fixed_8.vhdl + for i in Select_Priority_Fixed_8_Pack.vhdl Select_Priority_Fixed_8.vhdl ; do echo "vhdl work $$i" ; done > Select_Priority_Fixed_8.prj + +Select_Priority_Fixed_8_Pack.vhdl: + +Select_Priority_Fixed_8.vhdl: + +Select_Priority_Fixed_9.ngc: Select_Priority_Fixed_9.prj + echo run -keep_hierarchy yes -iobuf no -top Select_Priority_Fixed_9 -ifn Select_Priority_Fixed_9.prj -ofn Select_Priority_Fixed_9.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst + +Select_Priority_Fixed_9.prj: Select_Priority_Fixed_9_Pack.vhdl Select_Priority_Fixed_9.vhdl + for i in Select_Priority_Fixed_9_Pack.vhdl Select_Priority_Fixed_9.vhdl ; do echo "vhdl work $$i" ; done > Select_Priority_Fixed_9.prj + +Select_Priority_Fixed_9_Pack.vhdl: + +Select_Priority_Fixed_9.vhdl: + +clean: + rm -f Select_Priority_Fixed_0.ngc + rm -f Select_Priority_Fixed_0.lso + rm -f -r xst + rm -f Select_Priority_Fixed_0.prj + rm -f Select_Priority_Fixed_10.ngc + rm -f Select_Priority_Fixed_10.lso + rm -f -r xst + rm -f Select_Priority_Fixed_10.prj + rm -f Select_Priority_Fixed_11.ngc + rm -f Select_Priority_Fixed_11.lso + rm -f -r xst + rm -f Select_Priority_Fixed_11.prj + rm -f Select_Priority_Fixed_1.ngc + rm -f Select_Priority_Fixed_1.lso + rm -f -r xst + rm -f Select_Priority_Fixed_1.prj + rm -f Select_Priority_Fixed_2.ngc + rm -f Select_Priority_Fixed_2.lso + rm -f -r xst + rm -f Select_Priority_Fixed_2.prj + rm -f Select_Priority_Fixed_3.ngc + rm -f Select_Priority_Fixed_3.lso + rm -f -r xst + rm -f Select_Priority_Fixed_3.prj + rm -f Select_Priority_Fixed_4.ngc + rm -f Select_Priority_Fixed_4.lso + rm -f -r xst + rm -f Select_Priority_Fixed_4.prj + rm -f Select_Priority_Fixed_5.ngc + rm -f Select_Priority_Fixed_5.lso + rm -f -r xst + rm -f Select_Priority_Fixed_5.prj + rm -f Select_Priority_Fixed_6.ngc + rm -f Select_Priority_Fixed_6.lso + rm -f -r xst + rm -f Select_Priority_Fixed_6.prj + rm -f Select_Priority_Fixed_7.ngc + rm -f Select_Priority_Fixed_7.lso + rm -f -r xst + rm -f Select_Priority_Fixed_7.prj + rm -f Select_Priority_Fixed_8.ngc + rm -f Select_Priority_Fixed_8.lso + rm -f -r xst + rm -f Select_Priority_Fixed_8.prj + rm -f Select_Priority_Fixed_9.ngc + rm -f Select_Priority_Fixed_9.lso + rm -f -r xst + rm -f Select_Priority_Fixed_9.prj + +re: clean all + +install: + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_compact.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_compact.cfg (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_compact.cfg (revision 57) @@ -0,0 +1,4 @@ +Select_Priority_Fixed +2 16 *2 # nb_entity +0 0 +1 # encoding_one_hot +1 1 +1 # encoding_compact Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_dual.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_dual.cfg (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_dual.cfg (revision 57) @@ -0,0 +1,4 @@ +Select_Priority_Fixed +2 16 *2 # nb_entity +1 1 +1 # encoding_one_hot +1 1 +1 # encoding_compact Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_one_hot.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_one_hot.cfg (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/config_one_hot.cfg (revision 57) @@ -0,0 +1,4 @@ +Select_Priority_Fixed +2 16 *2 # nb_entity +1 1 +1 # encoding_one_hot +0 0 +1 # encoding_compact Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/configuration.cfg (revision 56) +++ (revision ) @@ -1,4 +1,0 @@ -Select_Priority_Fixed -2 16 *2 # nb_entity -0 1 +1 # encoding_one_hot -1 1 +1 # encoding_compact Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/include/test.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/include/test.h (revision 57) @@ -25,3 +25,3 @@ void test (string name, - morpheo::behavioural::generic::select::select_priority_fixed::Parameters param); + morpheo::behavioural::generic::select::select_priority_fixed::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/mkf.info =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/mkf.info (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/mkf.info (revision 57) @@ -5,8 +5,18 @@ target_dep Select_Priority_Fixed_0.prj Select_Priority_Fixed_0_Pack.vhdl Select_Priority_Fixed_0.vhdl +# Select_Priority_Fixed_10 +target_dep all Select_Priority_Fixed_10.ngc +target_dep Select_Priority_Fixed_10.ngc Select_Priority_Fixed_10.prj +target_dep Select_Priority_Fixed_10.prj Select_Priority_Fixed_10_Pack.vhdl Select_Priority_Fixed_10.vhdl + +# Select_Priority_Fixed_11 +target_dep all Select_Priority_Fixed_11.ngc +target_dep Select_Priority_Fixed_11.ngc Select_Priority_Fixed_11.prj +target_dep Select_Priority_Fixed_11.prj Select_Priority_Fixed_11_Pack.vhdl Select_Priority_Fixed_11.vhdl + # Select_Priority_Fixed_1 target_dep all Select_Priority_Fixed_1.ngc target_dep Select_Priority_Fixed_1.ngc Select_Priority_Fixed_1.prj -target_dep Select_Priority_Fixed_1.prj Select_Priority_Fixed_1_Pack.vhdl Select_Priority_Fixed_1.vhdl +target_dep Select_Priority_Fixed_1.prj Select_Priority_Fixed_10_Pack.vhdl Select_Priority_Fixed_10.vhdl Select_Priority_Fixed_11_Pack.vhdl Select_Priority_Fixed_11.vhdl Select_Priority_Fixed_1_Pack.vhdl Select_Priority_Fixed_1.vhdl # Select_Priority_Fixed_2 @@ -40,2 +50,12 @@ target_dep Select_Priority_Fixed_7.prj Select_Priority_Fixed_7_Pack.vhdl Select_Priority_Fixed_7.vhdl +# Select_Priority_Fixed_8 +target_dep all Select_Priority_Fixed_8.ngc +target_dep Select_Priority_Fixed_8.ngc Select_Priority_Fixed_8.prj +target_dep Select_Priority_Fixed_8.prj Select_Priority_Fixed_8_Pack.vhdl Select_Priority_Fixed_8.vhdl + +# Select_Priority_Fixed_9 +target_dep all Select_Priority_Fixed_9.ngc +target_dep Select_Priority_Fixed_9.ngc Select_Priority_Fixed_9.prj +target_dep Select_Priority_Fixed_9.prj Select_Priority_Fixed_9_Pack.vhdl Select_Priority_Fixed_9.vhdl + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/src/main.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/src/main.cpp (revision 57) @@ -42,9 +42,10 @@ try { - morpheo::behavioural::generic::select::select_priority_fixed::Parameters param (nb_entity , - encoding_one_hot, - encoding_compact); + morpheo::behavioural::generic::select::select_priority_fixed::Parameters * param = new morpheo::behavioural::generic::select::select_priority_fixed::Parameters + (nb_entity , + encoding_one_hot, + encoding_compact); - cout << param.print(1); + cout << param->print(1); test (name,param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/src/test.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/src/test.cpp (revision 57) @@ -13,11 +13,15 @@ void test (string name, - morpheo::behavioural::generic::select::select_priority_fixed::Parameters _param) + morpheo::behavioural::generic::select::select_priority_fixed::Parameters * _param) { cout << "<" << name << "> : Simulation SystemC" << endl; + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,50); +#endif Select_Priority_Fixed * _Select_Priority_Fixed = new Select_Priority_Fixed (name.c_str(), #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics(5,50), + _param_stat, #endif _param); @@ -38,8 +42,8 @@ CLOCK = new sc_clock ("clock", 1.0, 0.5); NRESET = new sc_signal ("NRESET"); - VAL = new sc_signal * [_param._nb_entity]; - ACK = new sc_signal * [_param._nb_entity]; + VAL = new sc_signal * [_param->_nb_entity]; + ACK = new sc_signal * [_param->_nb_entity]; - for (uint32_t i=0; i<_param._nb_entity; i++) + for (uint32_t i=0; i<_param->_nb_entity; i++) { rename = "VAL_"+toString(i); @@ -61,11 +65,11 @@ (*(_Select_Priority_Fixed->in_NRESET)) (*(NRESET)); - for (uint32_t i=0; i<_param._nb_entity; i++) + for (uint32_t i=0; i<_param->_nb_entity; i++) { (*(_Select_Priority_Fixed-> in_VAL [i])) (*(VAL [i])); - if (_param._encoding_one_hot) + if (_param->_encoding_one_hot) (*(_Select_Priority_Fixed->out_ACK [i])) (*(ACK [i])); } - if (_param._encoding_compact) + if (_param->_encoding_compact) { (*(_Select_Priority_Fixed->out_ENTITY )) (*(ENTITY )); @@ -78,5 +82,5 @@ cout << "<" << name << "> Start Simulation ............" << endl; - if (_param._nb_entity > (8*sizeof (Tentity_t))) + if (_param->_nb_entity > (8*sizeof (Tentity_t))) throw ErrorMorpheo("No Selftest with nb_entity higher at "+toString(8*sizeof (Tentity_t))); @@ -99,5 +103,5 @@ bool find = false; - for (uint32_t i=0; i<_param._nb_entity; i++) + for (uint32_t i=0; i<_param->_nb_entity; i++) { Tcontrol_t val = rand() % 2; @@ -118,7 +122,7 @@ entity = (find)?entity:0; - if (_param._encoding_one_hot) + if (_param->_encoding_one_hot) TEST(Tcontrol_t, ACK [entity]->read(), find ); - if (_param._encoding_compact) + if (_param->_encoding_compact) { TEST(Tentity_t , ENTITY ->read(), entity); // burk Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h (revision 57) @@ -26,4 +26,5 @@ #include "Behavioural/include/Vhdl.h" #endif +#include "Behavioural/include/Usage.h" using namespace std; @@ -44,6 +45,6 @@ // Parameters protected : const string _name; - - protected : const Parameters _param; + protected : const Parameters * _param; + private : const Tusage_t _usage; //#ifdef STATISTICS // protected : const morpheo::behavioural::Parameters_Statistics _param_statistics; @@ -54,5 +55,5 @@ #endif - private : Component * _component; + public : Component * _component; private : Interfaces * _interfaces; @@ -81,16 +82,17 @@ SC_HAS_PROCESS (Select_Priority_Fixed); #endif - public : Select_Priority_Fixed ( + public : Select_Priority_Fixed + ( #ifdef SYSTEMC - sc_module_name name, + sc_module_name name, #else - string name, + string name, #endif #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics param_statistics, + morpheo::behavioural::Parameters_Statistics * param_statistics, #endif - Parameters param ); - - public : Select_Priority_Fixed (Parameters param ); + Parameters * param , + morpheo::behavioural::Tusage_t usage=USE_ALL); + public : ~Select_Priority_Fixed (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Statistics.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Statistics.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Statistics.h (revision 57) @@ -28,10 +28,10 @@ { // -----[ fields ]---------------------------------------------------- - private : const Parameters _parameters; + private : const Parameters * _parameters; // -----[ methods ]--------------------------------------------------- public : Statistics (string name , - morpheo::behavioural::Parameters_Statistics parameters_statistics , - Parameters parameters + morpheo::behavioural::Parameters_Statistics * parameters_statistics , + Parameters * parameters ); //public : Statistics (Statistics & stat); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Types.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Types.h (revision 57) @@ -9,5 +9,5 @@ */ -#include "Common/include/Types.h" +#include "Behavioural/include/Types.h" namespace morpheo { Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed.cpp (revision 57) @@ -15,15 +15,19 @@ + Select_Priority_Fixed::Select_Priority_Fixed + ( #ifdef SYSTEMC - Select_Priority_Fixed::Select_Priority_Fixed (sc_module_name name, + sc_module_name name, #else - Select_Priority_Fixed::Select_Priority_Fixed (string name, + string name, #endif #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics param_statistics, + morpheo::behavioural::Parameters_Statistics * param_statistics, #endif - morpheo::behavioural::generic::select::select_priority_fixed::Parameters param ): - _name (name) - ,_param (param) + morpheo::behavioural::generic::select::select_priority_fixed::Parameters * param, + morpheo::behavioural::Tusage_t usage ): + _name (name), + _param (param), + _usage (usage) // #ifdef STATISTICS // ,_param_statistics (param_statistics) @@ -32,9 +36,6 @@ log_printf(FUNC,Select_Priority_Fixed,"Select_Priority_Fixed","Begin"); -#ifdef SYSTEMC log_printf(INFO,Select_Priority_Fixed,"Select_Priority_Fixed","Allocation"); - allocation (); -#endif #ifdef STATISTICS @@ -55,35 +56,38 @@ #ifdef SYSTEMC -#if defined(STATISTICS) or defined(VHDL_TESTBENCH) - log_printf(INFO,Select_Priority_Fixed,"Select_Priority_Fixed","Method - transition"); - - SC_METHOD (transition); - dont_initialize (); - sensitive_pos << *(in_CLOCK); -#endif - - log_printf(INFO,Select_Priority_Fixed,"Select_Priority_Fixed","Method - genMealy_entity"); - - SC_METHOD (genMealy_entity); - dont_initialize (); - //sensitive_pos << *(in_CLOCK); - for (uint32_t i=0; i<_param._nb_entity; i++) - sensitive << *(in_VAL [i]); - + if (_usage & USE_SYSTEMC) + { +# if defined(STATISTICS) or defined(VHDL_TESTBENCH) + log_printf(INFO,Select_Priority_Fixed,"Select_Priority_Fixed","Method - transition"); + + SC_METHOD (transition); + dont_initialize (); + sensitive_pos << *(in_CLOCK); +# endif + + log_printf(INFO,Select_Priority_Fixed,"Select_Priority_Fixed","Method - genMealy_entity"); + + SC_METHOD (genMealy_entity); + dont_initialize (); + //sensitive_pos << *(in_CLOCK); + for (uint32_t i=0; i<_param->_nb_entity; i++) + sensitive << *(in_VAL [i]); + # ifdef SYSTEMCASS_SPECIFIC - // List dependency information - - for (uint32_t i=0; i<_param._nb_entity; i++) - { - if (_param._encoding_one_hot) - (*(out_ACK [i])) (*(in_VAL [i])); - if (_param._encoding_compact) + // List dependency information + + for (uint32_t i=0; i<_param->_nb_entity; i++) { - (*(out_ENTITY )) (*(in_VAL [i])); - (*(out_ENTITY_ACK)) (*(in_VAL [i])); + if (_param->_encoding_one_hot) + (*(out_ACK [i])) (*(in_VAL [i])); + if (_param->_encoding_compact) + { + (*(out_ENTITY )) (*(in_VAL [i])); + (*(out_ENTITY_ACK)) (*(in_VAL [i])); + } } + +# endif } - -# endif #endif log_printf(FUNC,Select_Priority_Fixed,"Select_Priority_Fixed","End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_allocation.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_allocation.cpp (revision 57) @@ -19,9 +19,9 @@ log_printf(FUNC,Select_Priority_Fixed,"allocation","Begin"); - _component = new Component (); + _component = new Component (_usage); Entity * entity = _component->set_entity (_name + ,"Select_Priority_Fixed" #ifdef POSITION - ,"Select_Priority_Fixed" ,COMBINATORY #endif @@ -41,19 +41,20 @@ in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_NO); - in_NRESET = interface->set_signal_in ("nreset",1); - in_VAL = new SC_IN (Tcontrol_t) * [_param._nb_entity]; - if (_param._encoding_one_hot) - out_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_entity]; + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_NO); - for (uint32_t i=0; i<_param._nb_entity; i++) + in_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_entity]; + if (_param->_encoding_one_hot) + out_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_entity]; + + for (uint32_t i=0; i<_param->_nb_entity; i++) { in_VAL [i] = interface->set_signal_in ("val_"+toString(i),1); - if (_param._encoding_one_hot) + if (_param->_encoding_one_hot) out_ACK [i] = interface->set_signal_out ("ack_"+toString(i),1); } - if (_param._encoding_compact) + if (_param->_encoding_compact) { - out_ENTITY = interface->set_signal_out ("entity" , _param._size_entity); + out_ENTITY = interface->set_signal_out ("entity" , _param->_size_entity); out_ENTITY_ACK = interface->set_signal_out ("entity_ack", 1); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_deallocation.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_deallocation.cpp (revision 57) @@ -20,18 +20,21 @@ log_printf(FUNC,Select_Priority_Fixed,"deallocation","Begin"); - delete in_CLOCK; - delete in_NRESET; - - delete [] in_VAL; - if (_param._encoding_one_hot) - delete [] out_ACK; - - if (_param._encoding_compact) + if (_usage & USE_SYSTEMC) { - delete out_ENTITY; - delete out_ENTITY_ACK; + delete in_CLOCK; + delete in_NRESET; + + delete [] in_VAL; + if (_param->_encoding_one_hot) + delete [] out_ACK; + + if (_param->_encoding_compact) + { + delete out_ENTITY; + delete out_ENTITY_ACK; + } } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - + delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_genMealy_entity.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_genMealy_entity.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_genMealy_entity.cpp (revision 57) @@ -22,19 +22,19 @@ // init - Tcontrol_t ack [_param._nb_entity]; + Tcontrol_t ack [_param->_nb_entity]; bool find = false; Tentity_t entity; - if (_param._encoding_one_hot) - for (uint32_t i=0; i<_param._nb_entity; i++) + if (_param->_encoding_one_hot) + for (uint32_t i=0; i<_param->_nb_entity; i++) ack [i] = 0; log_printf(TRACE,Select_Priority_Fixed,"genMealy_entity","Scearch..."); - for (entity=0; entity<_param._nb_entity; entity++) + for (entity=0; entity<_param->_nb_entity; entity++) { if (PORT_READ(in_VAL [entity]) == 1) { log_printf(TRACE,Select_Priority_Fixed,"genMealy_entity","Find! entity %d",entity); - if (_param._encoding_one_hot) + if (_param->_encoding_one_hot) ack [entity] = 1; find = true; @@ -44,9 +44,9 @@ // Write port - if (_param._encoding_one_hot) - for (uint32_t i=0; i<_param._nb_entity; i++) + if (_param->_encoding_one_hot) + for (uint32_t i=0; i<_param->_nb_entity; i++) PORT_WRITE(out_ACK [i], ack [i]); - if (_param._encoding_compact) + if (_param->_encoding_compact) { PORT_WRITE(out_ENTITY , (find==true)?entity:0); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_vhdl_body.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_vhdl_body.cpp (revision 57) @@ -22,22 +22,22 @@ vhdl->set_body("internal_entity <="); - for (uint32_t i=0; i<_param._nb_entity; i++) + for (uint32_t i=0; i<_param->_nb_entity; i++) { - vhdl->set_body("\t"+std_logic_conv(_param._size_entity+1,i)+" when in_VAL_"+toString(i)+"='1' else"); + vhdl->set_body("\t"+std_logic_conv(_param->_size_entity+1,i)+" when in_VAL_"+toString(i)+"='1' else"); } - vhdl->set_body("\t"+std_logic_conv(_param._size_entity+1,1<<_param._size_entity)+";"); + vhdl->set_body("\t"+std_logic_conv(_param->_size_entity+1,1<<_param->_size_entity)+";"); vhdl->set_body (""); - if (_param._encoding_one_hot) + if (_param->_encoding_one_hot) { - for (uint32_t i=0; i<_param._nb_entity; i++) - vhdl->set_body("out_ACK_"+toString(i)+" <= '1' when internal_entity"+std_logic_range(_param._size_entity+1)+" = "+std_logic_conv(_param._size_entity+1,i)+" else '0';"); + for (uint32_t i=0; i<_param->_nb_entity; i++) + vhdl->set_body("out_ACK_"+toString(i)+" <= '1' when internal_entity"+std_logic_range(_param->_size_entity+1)+" = "+std_logic_conv(_param->_size_entity+1,i)+" else '0';"); vhdl->set_body (""); } - if (_param._encoding_compact) + if (_param->_encoding_compact) { - vhdl->set_body ("out_ENTITY <= internal_entity"+std_logic_range(_param._size_entity-1, 0)+";"); - vhdl->set_body ("out_ENTITY_ACK <= not internal_entity"+std_logic_range(_param._size_entity ,_param._size_entity)+";"); + vhdl->set_body ("out_ENTITY <= internal_entity"+std_logic_range(_param->_size_entity-1, 0)+";"); + vhdl->set_body ("out_ENTITY_ACK <= not internal_entity"+std_logic_range(_param->_size_entity ,_param->_size_entity)+";"); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_vhdl_declaration.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_vhdl_declaration.cpp (revision 57) @@ -20,5 +20,5 @@ log_printf(FUNC,Select_Priority_Fixed,"vhdl_declaration","Begin"); - vhdl->set_signal("internal_entity",_param._size_entity+1); + vhdl->set_signal("internal_entity",_param->_size_entity+1); log_printf(FUNC,Select_Priority_Fixed,"vhdl_declaration","End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Statistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Statistics.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Statistics.cpp (revision 57) @@ -17,6 +17,6 @@ Statistics::Statistics (string name , - morpheo::behavioural::Parameters_Statistics parameters_statistics , - Parameters parameters + morpheo::behavioural::Parameters_Statistics * parameters_statistics , + Parameters * parameters ) : morpheo::behavioural::Statistics(name , Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags (revision 57) @@ -15,10 +15,11 @@ #-----[ Flags ]-------------------------------------------- MORPHEO_FLAGS = -DSYSTEMC \ + -DVHDL \ + -DVHDL_TESTBENCH \ + -DVHDL_TESTBENCH_ASSERT \ + -DSTATISTICS \ -DDEBUG=DEBUG_TRACE -# -DVHDL \ -# -DVHDL_TESTBENCH \ -# -DSTATISTICS \ -# -DVHDL_TESTBENCH_ASSERT \ + # -DCONFIGURATION \ # -DPOSITION \ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf (revision 57) @@ -3,15 +3,19 @@ # -all: _Generic/RegisterFile/RegisterFile_Monolithic/SelfTest Generic/Select/Priority_Fixed/SelfTest Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest +all: _Generic/RegisterFile/RegisterFile_Monolithic/SelfTest _Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest _Generic/Select/Select_Priority_Fixed/SelfTest _Generic/RegisterFile/RegisterFile_Monolithic/SelfTest: gmake all -C Generic/RegisterFile/RegisterFile_Monolithic/SelfTest -Generic/Select/Priority_Fixed/SelfTest: +_Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest: + gmake all -C Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest -Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest: +_Generic/Select/Select_Priority_Fixed/SelfTest: + gmake all -C Generic/Select/Select_Priority_Fixed/SelfTest clean: gmake clean -C Generic/RegisterFile/RegisterFile_Monolithic/SelfTest + gmake clean -C Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest + gmake clean -C Generic/Select/Select_Priority_Fixed/SelfTest re: clean all @@ -19,3 +23,5 @@ install: gmake install -C Generic/RegisterFile/RegisterFile_Monolithic/SelfTest + gmake install -C Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest + gmake install -C Generic/Select/Select_Priority_Fixed/SelfTest Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/New_Component.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/New_Component.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/New_Component.h (revision 57) @@ -16,7 +16,7 @@ #include "Common/include/ToString.h" #include "Common/include/Debug.h" +#include "Behavioural/include/Types.h" #include "Behavioural/@DIRECTORY/include/Parameters.h" -#include "Behavioural/@DIRECTORY/include/Types.h" #ifdef STATISTICS #include "Behavioural/@DIRECTORY/include/Statistics.h" @@ -26,4 +26,5 @@ #include "Behavioural/include/Vhdl.h" #endif +#include "Behavioural/include/Usage.h" using namespace std; @@ -31,4 +32,5 @@ namespace morpheo { namespace behavioural { + @NAMESPACE_BEGIN @@ -41,6 +43,7 @@ // Parameters protected : const string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; - protected : const Parameters * _param; //#ifdef STATISTICS // protected : const morpheo::behavioural::Parameters_Statistics * _param_statistics; @@ -72,20 +75,23 @@ SC_HAS_PROCESS (@COMPONENT); #endif - public : @COMPONENT ( + public : @COMPONENT + ( #ifdef SYSTEMC - sc_module_name name, + sc_module_name name, #else - string name, + string name, #endif #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics * param_statistics, + morpheo::behavioural::Parameters_Statistics * param_statistics, #endif - Parameters * param ); + Parameters * param, + morpheo::behavioural::Tusage_t usage=USE_ALL + ); public : ~@COMPONENT (void); -#ifdef SYSTEMC private : void allocation (void); private : void deallocation (void); +#ifdef SYSTEMC //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) public : void transition (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/Types.h (revision 56) +++ (revision ) @@ -1,21 +1,0 @@ -#ifndef morpheo_behavioural_@DEFINE_Type_h -#define morpheo_behavioural_@DEFINE_Type_h - -/* - * $Id$ - * - * [ Description ] - * - */ - -#include "Common/include/Types.h" - -namespace morpheo { -namespace behavioural { -@NAMESPACE_BEGIN - -@NAMESPACE_END -}; // end namespace behavioural -}; // end namespace morpheo - -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component.cpp (revision 57) @@ -14,15 +14,20 @@ #undef FUNCTION #define FUNCTION "@COMPONENT::@COMPONENT" + @COMPONENT::@COMPONENT + ( #ifdef SYSTEMC - @COMPONENT::@COMPONENT (sc_module_name name, + sc_module_name name, #else - @COMPONENT::@COMPONENT (string name, + string name, #endif #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics * param_statistics, + morpheo::behavioural::Parameters_Statistics * param_statistics, #endif - morpheo::behavioural::@NAMESPACE_USE::Parameters * param ): - _name (name) - ,_param (param) + morpheo::behavioural::@NAMESPACE_USE::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) // #ifdef STATISTICS // ,_param_statistics (param_statistics) @@ -31,9 +36,6 @@ log_printf(FUNC,@COMPONENT,FUNCTION,"Begin"); -#ifdef SYSTEMC log_printf(INFO,@COMPONENT,FUNCTION,"Allocation"); - allocation (); -#endif #ifdef STATISTICS @@ -80,13 +82,9 @@ _stat->generate_file(statistics(0)); - delete _stat; #endif -#ifdef SYSTEMC log_printf(INFO,@COMPONENT,FUNCTION,"Deallocation"); - deallocation (); -#endif log_printf(FUNC,@COMPONENT,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_allocation.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_allocation.cpp (revision 57) @@ -1,3 +1,2 @@ -#ifdef SYSTEMC /* * $Id$ @@ -58,3 +57,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_deallocation.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_deallocation.cpp (revision 57) @@ -1,6 +1,2 @@ -#undef FUNCTION -#define FUNCTION "@COMPONENT::" - -#ifdef SYSTEMC /* * $Id$ @@ -37,3 +33,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Parameters_msg_error.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Parameters_msg_error.cpp (revision 57) @@ -6,6 +6,6 @@ */ +#include "Behavioural/include/Types.h" #include "Behavioural/@DIRECTORY/include/Parameters.h" -#include "Behavioural/@DIRECTORY/include/Types.h" #include using namespace std; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Component.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Component.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Component.h (revision 57) @@ -20,4 +20,5 @@ #include "Common/include/ToString.h" #include "Common/include/Debug.h" +#include "Behavioural/include/Usage.h" using namespace std; @@ -26,12 +27,27 @@ namespace behavioural { + typedef uint8_t Tinstance_t; + +#define INSTANCE_NONE 0x0 +#define INSTANCE_LIBRARY 0x1 +#define INSTANCE_COMPONENT 0x2 +#define INSTANCE_POSITION 0x4 +#define INSTANCE_ALL 0x7 + + typedef struct + { + public : Tinstance_t _instance; + public : Entity * _entity ; + } Tcomponent_t; + class Component { // -----[ fields ]---------------------------------------------------- + private : const Tusage_t _usage; private : Entity * _entity ; - private : list * _list_component; - + private : list * _list_component; + // -----[ methods ]--------------------------------------------------- - public : Component (void); + public : Component (Tusage_t usage=USE_ALL); public : Component (const Component & component); public : ~Component (); @@ -52,4 +68,5 @@ ,uint32_t size_y #endif + ,Tinstance_t instance=INSTANCE_ALL ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Entity.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Entity.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Entity.h (revision 57) @@ -18,4 +18,5 @@ #include "Common/include/ToString.h" #include "Common/include/Debug.h" +#include "Behavioural/include/Usage.h" using namespace std; @@ -32,4 +33,6 @@ private : const schema_t _schema ; #endif + private : const Tusage_t _usage; + private : Interfaces * _interfaces ; @@ -50,4 +53,5 @@ ,schema_t schema #endif + ,Tusage_t usage=USE_ALL ); public : Entity (const Entity & entity); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface.h (revision 57) @@ -25,4 +25,5 @@ #include "Common/include/ErrorMorpheo.h" #include "Common/include/Debug.h" +#include "Behavioural/include/Usage.h" using namespace std; @@ -38,4 +39,8 @@ protected : const direction_t _direction ; protected : const localisation_t _localisation ; +#endif + protected : const Tusage_t _usage; + +#ifdef POSITION protected : string _comment ; #endif @@ -59,4 +64,5 @@ ,localisation_t localisation #endif + ,Tusage_t usage=USE_ALL ); @@ -97,7 +103,15 @@ Signal * sig = set_signal (name, IN , size, presence_port); - sc_in_clk * port = new sc_in_clk (sig->_name.c_str()); - - sig->alloc (static_cast(port)); + sc_in_clk * port; + + if (_usage & USE_SYSTEMC) + { + port = new sc_in_clk (sig->_name.c_str()); + sig->alloc (static_cast(port)); + } + else + { + port = NULL; + } log_printf(FUNC,Behavioural,"set_signal_clk","End"); @@ -118,7 +132,15 @@ Signal * sig = set_signal (name, IN , size, presence_port); - sc_in * port = new sc_in (sig->_name.c_str()); - - sig->alloc (static_cast(port)); + sc_in * port; + + if (_usage & USE_SYSTEMC) + { + port = new sc_in (sig->_name.c_str()); + sig->alloc (static_cast(port)); + } + else + { + port = NULL; + } log_printf(FUNC,Behavioural,"set_signal_in","End"); @@ -139,7 +161,15 @@ Signal * sig = set_signal (name, OUT , size, presence_port); - sc_out * port = new sc_out (sig->_name.c_str()); - - sig->alloc (static_cast(port)); + sc_out * port; + + if (_usage & USE_SYSTEMC) + { + port = new sc_out (sig->_name.c_str()); + sig->alloc (static_cast(port)); + } + else + { + port = NULL; + } log_printf(FUNC,Behavioural,"set_signal_out","End"); @@ -155,7 +185,15 @@ Signal * sig = set_signal (name, INTERNAL , size, PORT_VHDL_NO_TESTBENCH_NO); - sc_signal * port = new sc_signal (sig->_name.c_str()); - - sig->alloc (static_cast(port)); + sc_signal * port; + + if (_usage & USE_SYSTEMC) + { + port = new sc_signal (sig->_name.c_str()); + sig->alloc (static_cast(port)); + } + else + { + port = NULL; + } log_printf(FUNC,Behavioural,"set_signal_internal","End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface_fifo.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface_fifo.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface_fifo.h (revision 57) @@ -45,4 +45,5 @@ ,localisation_t localisation #endif + ,Tusage_t usage=USE_ALL ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interfaces.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interfaces.h (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interfaces.h (revision 57) @@ -18,4 +18,5 @@ #include "Behavioural/include/Vhdl.h" #endif +#include "Behavioural/include/Usage.h" using namespace std; @@ -28,8 +29,10 @@ // -----[ fields ]---------------------------------------------------- private : const string _name; + private : const Tusage_t _usage; private : list * _list_interface; // -----[ methods ]--------------------------------------------------- - public : Interfaces (string name); + public : Interfaces (string name, + Tusage_t usage=USE_ALL); public : Interfaces (const Interfaces & interfaces); public : ~Interfaces (); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h (revision 57) @@ -0,0 +1,31 @@ +#ifndef morpheo_behavioural_Types_h +#define morpheo_behavioural_Types_h + +#include "Common/include/Types.h" + +namespace morpheo { +namespace behavioural { + + typedef bool Tcontrol_t; + typedef uint8_t Toperation_t; +//typedef uint8_t Tdestination1_t; +//typedef uint8_t Tdestination2_t; +//typedef uint8_t Texec_flag_t; +//typedef bool Texec_excep_t; +//typedef uint8_t Tcondition_t; +//typedef uint8_t Tbranch_state_t; + + typedef uint8_t Tcontext_t; + typedef uint8_t Tpacket_t; + typedef uint8_t Ttype_t; + typedef uint8_t Tlsq_ptr_t; + + typedef uint8_t Tgeneral_address_t; + typedef uint32_t Tgeneral_data_t; + typedef uint8_t Tspecial_address_t; + typedef uint32_t Tspecial_data_t; + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Usage.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Usage.h (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Usage.h (revision 57) @@ -0,0 +1,20 @@ +#ifndef morpheo_behavioural_Usage_h +#define morpheo_behavioural_Usage_h + +namespace morpheo { +namespace behavioural { + + typedef uint8_t Tusage_t; + +#define USE_SYSTEMC 0x01 +#define USE_VHDL 0x02 +#define USE_VHDL_TESTBENCH 0x04 +#define USE_STATISTICS 0x08 +#define USE_POSITION 0x10 +#define USE_ALL 0x1F + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info (revision 57) @@ -15,16 +15,7 @@ # build src directory content -#target_dep all Generic/Counter/SelfTest target_dep all Generic/RegisterFile/RegisterFile_Monolithic/SelfTest -#target_dep all Generic/Shifter/SelfTest -target_dep all Generic/Select/Priority_Fixed/SelfTest -#target_dep all Generic/Victim/Pseudo_LRU/SelfTest -#target_dep all Stage_1_Ifetch/Predictor/Meta_Predictor/SelfTest -#target_dep all Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/SelfTest -#target_dep all Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest -#target_dep all Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest -#target_dep all Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest -target_dep all Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest -#target_dep all Stage_5_Execute/Execution_cluster/Execution_group/Execution_unit/SelfTest +target_dep all Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest +target_dep all Generic/Select/Select_Priority_Fixed/SelfTest # mkf include path Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component.cpp (revision 57) @@ -11,12 +11,14 @@ namespace behavioural { - Component::Component (void) + Component::Component (Tusage_t usage): + _usage (usage) { log_printf(FUNC,Behavioural,"Component::Component","Begin"); - _list_component = new list; + _list_component = new list; log_printf(FUNC,Behavioural,"Component::Component","End"); }; - Component::Component (const Component & component) + Component::Component (const Component & component): + _usage (component._usage) { log_printf(FUNC,Behavioural,"Component::Component (copy)","Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_find_entity.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_find_entity.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_find_entity.cpp (revision 57) @@ -22,11 +22,13 @@ if (_list_component->empty()== false) { - list::iterator i = _list_component->begin(); + list::iterator i = _list_component->begin(); while (i != _list_component->end()) { - if ((*i)->get_name() == name) + Entity * entity = (*i)->_entity; + + if (entity->get_name() == name) { - _return = *i; + _return = entity; break; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_get_component.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_get_component.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_get_component.cpp (revision 57) @@ -22,5 +22,5 @@ bool last_separator = false; - list::iterator i = _list_component->begin(); + list::iterator i = _list_component->begin(); bool empty = _list_component->empty(); @@ -33,5 +33,5 @@ if (i != _list_component->end()) { - text << tab << **i; + text << tab << *((*i)->_entity); ++i; } @@ -40,5 +40,5 @@ { text << separator; - text << tab << **i; + text << tab << *((*i)->_entity); ++i; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_set_component.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_set_component.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_set_component.cpp (revision 57) @@ -15,9 +15,10 @@ void Component::set_component (Component * component #ifdef POSITION - ,uint32_t pos_x - ,uint32_t pos_y - ,uint32_t size_x - ,uint32_t size_y + ,uint32_t pos_x + ,uint32_t pos_y + ,uint32_t size_x + ,uint32_t size_y #endif + ,Tinstance_t instance ) { @@ -26,8 +27,14 @@ Entity * entity = component->_entity; - _list_component->push_back(entity); + Tcomponent_t * entry = new Tcomponent_t; + + entry->_instance = instance; + entry->_entity = entity; + + _list_component->push_back(entry); #ifdef POSITION - entity->mapping( pos_x, pos_y, size_x, size_y); + if (instance & INSTANCE_POSITION) + entity->mapping( pos_x, pos_y, size_x, size_y); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_set_entity.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_set_entity.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_set_entity.cpp (revision 57) @@ -27,4 +27,5 @@ ,schema #endif + ,_usage ); _entity = entity; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_toXML.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_toXML.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_toXML.cpp (revision 57) @@ -27,9 +27,9 @@ if (_list_component->empty()== false) { - list::iterator i = _list_component->begin(); + list::iterator i = _list_component->begin(); while (i != _list_component->end()) { - xml.insert_XML ((*i)->toXML_mapping()); + xml.insert_XML ((*i)->_entity->toXML_mapping()); ++i; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_vhdl_instance.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_vhdl_instance.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_vhdl_instance.cpp (revision 57) @@ -75,59 +75,65 @@ // for each entity - list * list_component = _list_component; - list::iterator i = list_component->begin(); + list * list_component = _list_component; + list::iterator i = list_component->begin(); if (not list_component->empty()) { while (i != list_component->end()) { - vhdl->set_library_work ((*i)->get_name() + "_Pack"); + Entity * entity = (*i)->_entity; + Tinstance_t instance = (*i)->_instance; + + if (instance & INSTANCE_LIBRARY) + vhdl->set_library_work (entity->get_name() + "_Pack"); - list list_port_map; - - // for each interface - list * list_interface = (*i)->get_interfaces_list()->get_interface_list(); - list::iterator j = list_interface->begin(); - if (not list_interface->empty()) - { - while (j != list_interface->end()) - { - // for each signal - list * list_signal = (*j)->get_signal_list(); - list::iterator k = list_signal->begin(); - if (not list_signal->empty()) - { - while (k != list_signal->end()) - { - // test if is connect with external interface or with an another component. - Signal * signal_src = (*k); - - if (signal_src->presence_vhdl () == true) - { - Signal * signal_dest = signal_src->get_connect_to_signal(); - string name_src = signal_src->get_name(); - string name_dest; - + if (instance & INSTANCE_COMPONENT) + { + list list_port_map; + + // for each interface + list * list_interface = entity->get_interfaces_list()->get_interface_list(); + list::iterator j = list_interface->begin(); + if (not list_interface->empty()) + { + while (j != list_interface->end()) + { + // for each signal + list * list_signal = (*j)->get_signal_list(); + list::iterator k = list_signal->begin(); + if (not list_signal->empty()) + { + while (k != list_signal->end()) + { + // test if is connect with external interface or with an another component. + Signal * signal_src = (*k); + + if (signal_src->presence_vhdl () == true) + { + Signal * signal_dest = signal_src->get_connect_to_signal(); + string name_src = signal_src->get_name(); + string name_dest; + // // Test if destination signal is a interface port ? // if (_entity->find_signal(signal_dest) == false) // { - // find if signal is already link - map::iterator it = tab.find(signal_dest); - if (tab.find(signal_dest) == tab.end()) - { - // Create name - name_dest = "signal_"+toString(cpt++); - - tab [signal_src ] = name_dest; - tab [signal_dest] = name_dest; - - // Add a new signal - vhdl->set_signal (name_dest, signal_src->get_size()); - } - else - { - // find !!!! - name_dest = (*it).second; - tab [signal_src ] = name_dest; - } + // find if signal is already link + map::iterator it = tab.find(signal_dest); + if (tab.find(signal_dest) == tab.end()) + { + // Create name + name_dest = "signal_"+toString(cpt++); + + tab [signal_src ] = name_dest; + tab [signal_dest] = name_dest; + + // Add a new signal + vhdl->set_signal (name_dest, signal_src->get_size()); + } + else + { + // find !!!! + name_dest = (*it).second; + tab [signal_src ] = name_dest; + } // } // else @@ -150,13 +156,15 @@ // } - vhdl->set_body_component_port_map (list_port_map, name_src, name_dest); - } - ++k; - } - } - ++j; - } - } - vhdl->set_body_component ("instance_"+(*i)->get_name(),(*i)->get_name(),list_port_map); + vhdl->set_body_component_port_map (list_port_map, name_src, name_dest); + } + ++k; + } + } + ++j; + } + } + vhdl->set_body_component ("instance_"+entity->get_name(),entity->get_name(),list_port_map); + + } ++i; } @@ -164,5 +172,5 @@ log_printf(FUNC,Behavioural,FUNCTION,"End"); }; - + }; // end namespace behavioural }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Entity.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Entity.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Entity.cpp (revision 57) @@ -16,4 +16,5 @@ ,schema_t schema #endif + ,Tusage_t usage ): _name (name ) @@ -22,7 +23,8 @@ ,_schema (schema ) #endif + ,_usage (usage ) { log_printf(FUNC,Behavioural,"Entity","Begin"); - _interfaces = new Interfaces (name); + _interfaces = new Interfaces (name, usage); #ifdef POSITION _is_map = false; @@ -37,4 +39,5 @@ ,_schema (entity._schema ) #endif + ,_usage (entity._usage ) { log_printf(FUNC,Behavioural,"Entity (copy)","Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface.cpp (revision 57) @@ -16,4 +16,5 @@ ,localisation_t localisation #endif + ,Tusage_t usage ): _name (name ) @@ -22,4 +23,5 @@ ,_localisation (localisation) #endif + ,_usage (usage) { log_printf(FUNC,Behavioural,"Interface","Begin"); @@ -47,4 +49,5 @@ ,_localisation (interface._localisation) #endif + ,_usage (interface._usage) { log_printf(FUNC,Behavioural,"Interface (copy)","Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_fifo.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_fifo.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_fifo.cpp (revision 57) @@ -16,4 +16,5 @@ ,localisation_t localisation #endif + ,Tusage_t usage ): Interface (name @@ -22,4 +23,5 @@ ,localisation #endif + ,usage ) { Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces.cpp (revision 57) @@ -11,6 +11,8 @@ namespace behavioural { - Interfaces::Interfaces (string name): - _name (name) + Interfaces::Interfaces (string name, + Tusage_t usage): + _name (name), + _usage (usage) { log_printf(FUNC,Behavioural,"Interfaces","Begin"); @@ -20,5 +22,6 @@ Interfaces::Interfaces (const Interfaces & interfaces) : - _name (interfaces._name) + _name (interfaces._name), + _usage (interfaces._usage) { log_printf(FUNC,Behavioural,"Interfaces (copy)","Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_set_interface.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_set_interface.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_set_interface.cpp (revision 57) @@ -27,5 +27,5 @@ ,localisation #endif - ); + ,_usage); _list_interface->push_back (interface); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp (revision 57) @@ -66,8 +66,11 @@ string type; - if (max == min) - type = "("+toString(max)+")"; + if (max == 0) + type = ""; else - type = "("+toString(max)+" downto "+toString(min)+")"; + if (max == min) + type = "("+toString(max)+")"; + else + type = "("+toString(max)+" downto "+toString(min)+")"; log_printf(FUNC,Behavioural,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/presentation-internal_seminary_overview/fr/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/presentation-internal_seminary_overview/fr/root.tex (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/presentation-internal_seminary_overview/fr/root.tex (revision 57) @@ -1,55 +1,184 @@ \section{Motivations} - -%\ContentsCurrent - -\slidetitle{Problématique} - { - On désire une plateforme de confiance totale : - \begin{itemize} - \item La plateforme-matérielle est composée de processeur(s) généraliste(s). - \item La plateforme-logicielle est composée de plusieurs applications qui peuvent être cryptographique. - \end{itemize} - - Notre travail consiste à faire le processeur pour un tel système. - } - { - } - -\slidetitle{Ancienne tendance} +\ContentsCurrent + +\slidetitle{Cadre de la thèse} + { + \begin{itemize} + \item {\it Cadre :}\newline + Collaboration avec Bull sur le projet PFC\newline + (Plate-forme de confiance totale) + \item {\it Notre contribution :}\newline + Réalisation d'un générateur de processeur ouvert. + \end{itemize} + } + { + Expliquer PFC + } + +\slidetitle{Approche actuelle fondée sur le secret} { \begin{itemize} \item Composants fermés. - \item Label de sécurité. + \item Consortium de certification \begin{itemize} \item Trusted Computing Platform Alliance - \item Next-Generation Secure Computing Base - \end{itemize} - \item Plateforme multi-chip. - \end{itemize} - } - { +% \begin{itemize} +% \item Next-Generation Secure Computing Base +% \item Intel Trusted Execution Technology +% \end{itemize} + \end{itemize} + \end{itemize} + + \printgraph{Logo-trusted_computing_group}{0.8} + + Limite de l'approche : + + \begin{itemize} + \item Pas de confiance : + \begin{itemize} + \item Chevaux de troie + \end{itemize} + \item Pas de pérennité : + \begin{itemize} + \item Arrêt de production + \item Changement de protocole + \end{itemize} + \end{itemize} + } + { + Consortium : intel, amd, ibm, microsoft ... + + Le principe du TCG : + + \begin{itemize} + \item Assigner une signature à chaque objet informatique (logiciel, par extension matériel). + \item Déléguer à un {\it tiers de confiance} la tâche de vérifier si l'objet manipulé est autorisé à être utilisé sur le système local. + \end{itemize} + + Enjeux commerciaux != Ouvert et Pérennité. + } + +\slidetitle{Nouvelle approche} + { + \begin{itemize} + \item Composants ouverts + \begin{itemize} + \item Pas de fonctionnalités cachées. + \item Pas de secret à conserver. + \end{itemize} + \item Intégration : + \begin{itemize} + \item Field-Programmable Gate Array (FPGA). + \item System On Chip (SOC). + \end{itemize} + \end{itemize} + + \begin{center} + \begin{minipage}{.4\textwidth} + \printgraph{Logo-opencores}{0.8} + \end{minipage} + \begin{minipage}{.4\textwidth} + \printgraph{Logo-soclib}{0.8} + \end{minipage} + \end{center} + } + { + Composant matériel ouvert = code source disponible = FPGA = prototypage = SOC. + } + +\section{Cahier des charges} +\ContentsCurrent + +\slidetitle{Besoins : Cahier des charges} + { + Il faut une architecture : \begin{description} - \item[Trusted Computing Platform Alliance :] Le Trusted Computing Group (TCG, nommé jusqu'en 2003 TCPA pour Trusted Computing Platform Alliance) est une consortium d'entreprises d'informatique (Compaq, HP, IBM, Intel, Microsoft, AMD, etc.) visant à sécuriser les équipements et communications informatiques. - \item[Next-generation secure computing base :] Le Next-Generation Secure Computing Base (NGSCB, littéralement : Base d'information sécurisée de nouvelle génération) ou ordinateur sécurisé de la prochaine génération fait partie de la nouvelle architecture de Microsoft pour l'informatique de confiance. Ce projet était connu sous le nom de Palladium. + \item [Ouverte :] Évite les fonctionnalités cachées. + \item [Pérenne :] Évite les problèmes d'approvisionnements. + \item [Paramétrable :] S'adapte aux critères de l'application. + \item [Performante :] Applications nécessitant de la puissance de calculs. \end{description} } - -\slidetitle{Nouvelle tendance} - { - \begin{itemize} - \item Utilisation de composants ouvert. \\Evite les fonctionnalités cachés - \item Intégration de System On Chip (SOC).\\Réduit la vunérabilité des communications entre deux chips. - \end{itemize} - } - { - } - -\section{Besoins} -\slidetitle{Besoins} - { + { + Concevoir un cpu pour PFC : + + ouverte, pérenne, paramétrable, performante. + + Applications cibles : cryptographique. + } + +\subsection{Architecture Ouverte} +\slidetitle{Architecture Ouverte} + { + \begin{itemize} + \item Instruction Set Architecture gratuite. + %\item Présence d'une communauté autour de l'architecture logicielle. + \item Chaîne de compilation disponible et ouverte. + \item Modèle disponible : + \begin{itemize} + \item Modèle systemC-CABA + \item Modèle VHDL-RTL + \end{itemize} + \end{itemize} + } + { + Chaîne de compilation $\Rightarrow$ présence d'une communauté, espère une pérennité des logicielles. + + VHDL = FPGA + + SystemC = dévellopement + } + +\subsection{Architecture Pérenne} +\slidetitle{Architecture Pérenne} + { + \begin{itemize} + \item Instruction Set Architecture gratuite. + %\item Présence d'une communauté autour de l'architecture logicielle. + \item Chaîne de compilation disponible et ouverte. + \item Technologie cible flexible : FPGA. + \end{itemize} + } + { + ISA et Modèle disponible = implémentation possible. + } + +\subsection{Architecture Paramétrable} +\slidetitle{Architecture Paramétrable} + { + S'adapter aux critères de l'application : + \begin{itemize} + \item Performance + \item Surface + \item Consommation + \item Temps réel + \item \dots + \end{itemize} + + Pas un processeur mais plusieurs processeurs.\\ + \begin{itemize} + \item[$\Rightarrow$] Générateur d'architecture. + \item[$\Rightarrow$] Technologie cible : FPGA. + \end{itemize} + } + { + Aucune connaissance à priori des besoins des applications. Peuvent avoir des critères variés ... + + Pas 1CPU mais plusieurs CPU = ASIC trop onéreux + } + +\subsection{Architecture Performante} +\slidetitle{Architecture Performante} + { + \begin{center} + {\it Exécution de plusieurs instructions simultanément} + \end{center} + + Exploitation de toutes les formes de parallélisme. + \begin{description} - \item [Open :] Absence de fonctionnalités cachées. (Cheval de troie) - \item [Configurable :] Adaptable aux besoins des applications. - \item [Performance :] Application cryptographique. + \item[ILP :] Instruction Level Parallelism + \item[TLP :] Thread Level Parallelism + \item[DLP :] Data Level Parallelism \end{description} } @@ -57,49 +186,285 @@ } -\slidetitle{Besoins : Open} - { - \begin{itemize} - \item Instruction Set Architecture libre. (Implémentation possible) - \item Tools Chains présente et libre. - \item Implémentation sur FPGA (Pérennité). - \item Présence d'une communauté autour de l'architecture logicielle. - \end{itemize} - } - { - } - -\slidetitle{Besoins : Configurable} - { - \begin{itemize} - \item Pas de connaissance préalable du besoin des applications. - \item Toutes les applications non pas les mêmes besoins de Performance / Surface. - \end{itemize} - } - { - } - -\slidetitle{Besoins : Performance} - { - Exploitation de toutes les formes de parrallélisme. +%\subsubsection{ILP} +\slidetitle{Instruction Level Paralelism} + { + \begin{center} + {\it Exécution simultanée de plusieurs instructions provenant d'un même flux.} + \end{center} + \printgraph{GENERAL_ILP}{1 } + } + { + } +%\slide +% { +% \begin{description} +% \item[Avantages :]~ +% \begin{itemize} +% \item Exploitation implicite du point de vue logicielle. +% \end{itemize} +% \item[Inconvénients :]~ +% \begin{itemize} +% \item Coût quadratique du contrôle. +% \end{itemize} +% \end{description} +% } +% { +% } + + +%\subsubsection{TLP} +\slidetitle{Thread Level Paralelism} + { + \begin{center} + {\it Exécution simultanée de plusieurs instructions provenant de différents flux.} + \end{center} + + \printgraph{GENERAL_TLP}{1 } + } + { + } + +%\slide +% { +% \begin{description} +% \item[Avantages :]~ +% \begin{itemize} +% \item Implantation très simple : duplication des coeurs +% \item Ressources dédiés aux threads exécutés sur le coeur +% \end{itemize} +% \item[Inconvénients :]~ +% \begin{itemize} +% \item Il doit avoir plus de thread que de coeurs afin d'éviter l'oisiveté des coeurs +% \end{itemize} +% \end{description} +% } +% { +% } +% +%\slidetitle{TLP - Simulatenous Multi Threading (SMT)} +% { +% \printgraph{GENERAL_TLP-SMT}{1 } +% } +% { +% } +% +%\slide +% { +% \begin{description} +% \item[Avantages :]~ +% \begin{itemize} +% \item Implantation très simple et peu coûteuse en surface. +% \item Meilleur exploitation des ressources +% \end{itemize} +% \item[Inconvénients :]~ +% \begin{itemize} +% \item Dimensionner le nombre de threads proportionnellement à l'ILP exploitable. +% \end{itemize} +% \end{description} +% } +% { +% } + +%\subsubsection{DLP} +\slidetitle{Data Level Paralelism} + { + \begin{center} + {\it Exécution d'instructions avec plusieurs données. (SIMD)} + \end{center} + + \printgraph{GENERAL_DLP}{1 } + } + { + Matrice 3x3 + 10 + } +%\slide +% { +% \begin{description} +% \item[Avantages :]~ +% \begin{itemize} +% \item Une instruction SIMD est équivalente à beaucoup d'instructions SISD. +% \end{itemize} +% \item[Inconvénients :]~ +% \begin{itemize} +% \item Pas adapter pour les applications qui n'exploite pas le DLP. +% \item Exploitation explicite par le programmeur. +% \end{itemize} +% \end{description} +% } +% { +% } +% + +\slidetitle{Implémentation matérielle} + { + \printgraph{GENERAL_hardware}{.98} + } + { + Streaming SIMD Extensions, généralement abrégé SSE, est un jeu de 70 instructions supplémentaires pour microprocesseurs x86, apparu sur le Pentium III. Le fonctionnement est de type SIMD. + + + AltiVec est un ensemble d'instructions SIMD d'opérations en virgule flottante conçu par, et propriété de, Apple, IBM et Motorola (l'AIM alliance), et mis en application sur des versions du PowerPC telle le G4 de Motorola et le G5 d'IBM. + } + +\slide + { \begin{description} - \item [ILP :] Instruction Level Paralelism - \item [TLP :] Thread Level Paralelism - \item [DLP :] Data Level Paralelism + \item[ILP] + \begin{itemize} + \item Super Scalaire\\ + \item \sout{VLIW} + \begin{itemize} + \item[$\Rightarrow$] Compilateur spécialisé. + \item[$\Rightarrow$] Pas scalable + \end{itemize} + \end{itemize} + \item[TLP] + \begin{itemize} + \item CMP + \begin{itemize} + \item[$\Rightarrow$] Scalable mais sous utilisation des ressources. + \end{itemize} + \item SMT + \begin{itemize} + \item[$\Rightarrow$] Utilisation optimale des ressources mais peu scalable. + \end{itemize} + \item Mixte + \end{itemize} + \item[DLP] + \begin{itemize} + \item Extension SIMD\\ + \end{itemize} \end{description} } { - } - -\slidetitle{ILP} - { + Mixte : tirer partie du CMP et SMT + } + +\section{État actuel} +\ContentsCurrent + +\slidetitle{Processeurs libres existants} + { + \begin{tabular}{l|ccccc} + + {\it Processeur} & {\it Date} & {\it ISA} & \multicolumn{2}{c}{{\it Support}} \\ + & & & {\it ASIC} & {\it FPGA} \\ + + \hline + OpenRISC 1200 & 2001 & or1000-ORBIS32 & X & X\\ %&Mono-core, Scalaire 5 étages, 32 bits\\ + LEON2 & 2003 & SPARC-V8 & X & X\\ %&Mono-core, Scalaire 5 étages, 32 bits\\ + LEON3 & 2005 & SPARC-V8e & X & X\\ %&Mono-core, Scalaire 7 étages, 32 bits\\ + OpenSparcT1 & 2005 & UltraSPARC-V9 & X & X\\ + MANIK & 2006 & MANIK & & X\\ + aeMB & 2007 & Xilinx EDK 3.2 & & X\\ %&Mono-core, Scalaire 3 étages, 32 bits\\ + OpenFIRE & 2007 & Xilinx EDK 6.3 & & X\\ %&Mono-core, Scalaire 3 étages, 32 bits\\ + OpenSparcS1 & 2007 & UltraSPARC-V9 & X & X\\ + OpenSparcT2 &$>$2007 & UltraSPARC-V9 & & \\ + \end{tabular} + } + { + Xilinx EDK 3.2 : 2003 + + Xilinx EDK 6.3 : 2004 + + \begin{tabular}{l|cccc} + + {\it Processeur} & FPGA & taille & freq (Mhz) & remarque\\ + + \hline + OpenRISC 1200 & statix 2 & 3000 & 33 & sans cache\\ + LEON2 & virtex 2 & 5000 + RAM & 80 & \\ + LEON3 & ? & 3500 & 125 & \\ + MANIK & & & & \\ + aeMB & & & & \\ + OpenFIRE & virtex 2 & 641 & 100\\ + \end{tabular} + + + Xilinx XC4VLX200 SPARC FPU CCX + LUTs 134,973 13,863 25,090 + + + With FPGA\_SYN, FPGA\_SYN\_1THREAD, and FPGA\_SYN\_NO\_SPU options: + Xilinx XC4VFX100 SPARC FPU CCX + LUTs 40,613 9,398 26,051 + + + + With FPGA\_SYN and FPGA\_SYN\_NO\_SPU options (4 threaded core): + Xilinx XC4VFX100 SPARC FPU CCX + LUTs 68,476 9,398 26,051 + } + +\slidetitle{État actuel} + { + Il existe plusieurs processeurs libres, mais : + + \begin{itemize} + \item Aucun processeur n'exploite l'ILP. + \item Les paramètres concernent principalement le cache. + \item Seuls les modèles de l'OpenSPARC exploitent le TLP. + \end{itemize} + } + { + } + +%\slidetitle{Fonction de coûts} +% { +% Comparaison de deux instances du générateur : +% +% \begin{itemize} +% \item Soit : obtenir le meilleur compromis Performance / Complexité. +% \begin{itemize} +% \item Performance : nombre de cycles nécessaire pour exécuter les Benchmarks. +% \item Complexité : surface occupée du FPGA. +% \end{itemize} +% \item Soit : obtenir le meilleur partage des ressources entre les contextes matériels. (Gain Performance / Coût surface). +% \begin{itemize} +% \item Gain en performance : rapport entre la performance MT sur la performance ST. +% \item Coût en surface : rapport entre la surface MT sur la surface ST. +% \end{itemize} +% \end{itemize} +% } +% { +% benchmark : SPECINT2k, Dhrystone +% +% +% } + +\section{Morpheo} +\ContentsCurrent + +%\slidetitle{Morpheo} +% { +% \printgraph{MORPHEO_service}{0.75} +% } +% { +% } + +\subsection{Paramètres} +\slidetitle{Paramètres} + { + 3 types : \begin{description} - \item[Avantages :]~ - \begin{itemize} - \item Exploitation implicite. - \end{itemize} - \item[Inconvénients :]~ - \begin{itemize} - \item Coût quadratique du contrôle. - \end{itemize} + \item [Global] + \begin{itemize} + \item Occurrence de chaque entité [1:8] + \item Nombre d'instructions pour chaque entité [1:8] + \end{itemize} + \item [Local] + \begin{itemize} + \item Présence/Absence du réseau de bypass + \item Nombre de registres physiques [32:512] + \item Nombre de ports du banc de registres [2:16] + \item Taille des files d'attente (fetch\_queue, \dots) [2:8] + \item Taille des structures internes (BTB, RAS, \dots) + \item Type et taille du prédicteur de branchement + \item Type des unités d'exécution + \end{itemize} + \item [Routage] + \begin{itemize} + \item Entre les différentes entités + \end{itemize} \end{description} } @@ -107,98 +472,6 @@ } -\slidetitle{TLP - Chip Multi Processor (CMP)} - { - \begin{description} - \item[Avantages :]~ - \begin{itemize} - \item Implémentation très simple : duplication des cores - \item Ressources dédiés au thread executé sur le core - \end{itemize} - \item[Inconvénients :]~ - \begin{itemize} - \item Il doit avoir plus de thread que de core afin d'éviter l'oisiveté des cores. - \end{itemize} - \end{description} - } - { - } - -\slidetitle{TLP - Simulatenous Multi Threading (SMT)} - { - \begin{description} - \item[Avantages :]~ - \begin{itemize} - \item Implémentation très simple et peu coûteuse en surface. - \item Meilleur exploitation des ressources - \end{itemize} - \item[Inconvénients :]~ - \begin{itemize} - \item Dimensionnement du nombre de thread proportionnel à l'ILP exploitable. - \end{itemize} - \end{description} - } - { - } - -\slidetitle{DLP} - { - \begin{description} - \item[Avantages :]~ - \begin{itemize} - \item Une instruction SIMD est équivalente à beaucoup d'instructions SISD. - \end{itemize} - \item[Inconvénients :]~ - \begin{itemize} - \item Pas adapter pour les applications qui n'exploite pas le DLP. - \item Exploitation explicite par le programmeur. - \end{itemize} - \end{description} - } - { - } - - -\slidetitle{Etat de l'art} - { - \begin{description} - \item [sofcore :]~ - \begin{description} - \item [Commercial :] Nios, MicroBlaze, ... - \item [Libre :] OpenRISC 1200, Leon 2/3, OpenSPARC T1/S1 - \end{description} - {\it Non : Peu configurable, faible exploitation du paralélisme d'instruction} - \item [Simulateur :] SimpleScalar, SMTSim, ...\\ - {\it Non : Simulateur non prévut pour avoir une synthèse} - \item [Hardcore :] POWER5, Intel Pentium 3/4, MIPS R10000, ...\\ - {\it Non : ISA non libre} - \end{description} - } - { - } - -\slidetitle{Objectif} - { - } - { - } - -\slidetitle{Service offert} - { - \printgraph{MORPHEO_service}{0.75} - } - { - } - -\slidetitle{Fonction de coûts} - { - } - { - } - -\section{Morpheo} -%\ContentsCurrent - -\subsection{Micro Architecture} -\slidetitle{Micro Architecture : Overview} +\subsection{Architecture interne} +\slidetitle{Architecture interne} { \printgraph{MORPHEO_micro_architecture-overview}{0.48} @@ -207,34 +480,120 @@ 3 grandes parties : \begin{description} - \item[Front end :] Amène des paquets d'instructions en séquence, et les décodes. Calcules les addresses suivantes (spéculation) et maintiens l'état des threads (idle, wait, run ...) - \item[Out Of Order Engine :] Renome les registres (annulations des dépendances RAW, WAW et WAR). Re Order Buffer : mettre à jour l'état du contexte dans l'ordre d'arrivé des threads. - \item[Execution Loop :] Boucle ``Read, execute, Write''. Ainsi que les bypass. Instructions peuvent ce lancer dans le désordres. + \item[Front end :] Amène des paquets d'instructions en séquence, et les décodes. Calcules les adresses suivantes (spéculation) et maintiens l'état des threads (idle, wait, run ...) + \item[Out Of Order Engine :] Renomme les registres (annulations des dépendances RAW, WAW et WAR). Re Order Buffer : mettre à jour l'état du contexte dans l'ordre d'arriver des threads. + \item[Execution Loop :] Boucle ``Read, execute, Write''. Ainsi que les bypass. Instructions peuvent ce lancer dans le désordres. \end{description} } -\slidetitle{Micro Architecture : Front end} - { - \printgraph{MORPHEO_micro_architecture-front_end}{0.7} - } - { - } - -\slidetitle{Micro Architecture : Out Of Order Engine} - { - \printgraph{MORPHEO_micro_architecture-out_of_order_engine}{0.7} - } - { - } - -\slidetitle{Micro Architecture : Execution Loop} - { - \printgraph{MORPHEO_micro_architecture-execute_loop}{0.7} - } - { - } - +\slide + { + \printgraph{MORPHEO_micro_architecture-ex01}{0.48} + } + { + Hypothèse de départ + + SMT 2 + } + +\slide + { + \printgraph{MORPHEO_micro_architecture-ex02}{0.48} + } + { + contexte x4 prédicteur dédié + } + +\slide + { + \printgraph{MORPHEO_micro_architecture-ex03}{0.48} + } + { + Select ... + } + +\slide + { + \printgraph{MORPHEO_micro_architecture-ex04}{0.48} + } + { + possibilité de CMP + } + + +%\slidetitle{Micro Architecture : Front end} +% { +% \printgraph{MORPHEO_micro_architecture-front_end}{0.7} +% } +% { +% } +% +%\slidetitle{Micro Architecture : Out Of Order Engine} +% { +% \printgraph{MORPHEO_micro_architecture-out_of_order_engine}{0.7} +% } +% { +% } +% +%\slidetitle{Micro Architecture : Execution Loop} +% { +% \printgraph{MORPHEO_micro_architecture-execute_loop}{0.7} +% } +% { +% } +% +\section{Validation fonctionnelle} +\ContentsCurrent + +\subsection{Validation du modèle systemC/CABA} \slidetitle{Environnement de simulation} { + \begin{itemize} + \item Benchmark SPECINT2k. + \begin{tabular}{ll} + 164.gzip & Compression. \\ + 175.vpr & Placement et routage de circuit FPGA. \\ + 181.mcf & Optimisation combinatoire. \\ + 255.vortex & Object-oriented Database. \\ + 256.bzip2 & Compression. \\ + 300.twolf & Simulateur de placement et de routage.\\ + \end{tabular} + \item Appel système : librairie {\it newlib}. + \item Plate-forme matérielle ``custom'' + \begin{itemize} + \item Gestion de l'endienness. + \item Pont entre la simulation et le système hôte. + \end{itemize} + \end{itemize} + } + { + sim2os : + \begin{itemize} + \item SERVICE\_OPEN + \item SERVICE\_CLOSE + \item SERVICE\_READ + \item SERVICE\_WRITE + \item SERVICE\_TIME + \item SERVICE\_CLOCK + \item SERVICE\_LSEEK + \end{itemize} + } + +\slidetitle{Hypothèse de travail} + { + Architecture de références + \begin{itemize} + \item 4 Threads + \item 8 Unités d'exécutions + \item 8 Instructions lancées par cycle + \end{itemize} + + Variation de l'architecture + \begin{itemize} + \item Nombre de cache de premier niveau + \item Nombre d'unité de lancement (Front\_End et OoO\_Engine) + \item Nombre de contexte matériel + \item Partage des unités fonctionnelles + \end{itemize} } { @@ -243,292 +602,72 @@ \slidetitle{Résultats} { - } - { - } - -\slidetitle{Morpheo on FPGA} - { - } - { - } - - - -%\section{Besoins} -% -%\ContentsCurrent -% -%\slidetitle{Besoins} -% {Besoins pour les processeurs embarquées : -% -% \begin{itemize} -% \item Maîtrise du système -% \item Souplesse -% \item Performance -% \end{itemize} -% } -% { -% Où : téléphone portable, baladeur mp3/vidéo, automobile ... -% -% \begin{description} -% \item[Maitrise du système :] Les processeurs généralistes sont utilisés dans un vaste échantillon d'application. Ceci touche également la sécurité. -% \item[Souplesse :] Pour un concepteur de système embarqués : bien dimensionner son système -% \item[Performance :] Application cible de plus en plus gourmande en ressources : beaucoup de threads avec des impératifs de rapidité. -% \end{description} -% } -% -%\subsection{Maîtrise du système} -%\slidetitle{Besoin de la Maîtrise du système} -% { -% {\bf Plate-forme de confiance totale} -% -% \begin{itemize} -% \item Projet Open -% \item ISA Open -% \item Instructions customisables -% \end{itemize} -% } -% { -% Morpheo s'inscrit dans le cadre du projet plate-forme de confiance totale. -% -% Instructions customisables : possibilité à l'utilisateur de rajouter de nouvelles instructions. Comme par exemple pour le chiffrement ou le déchiffrement ... -%% On doit supposer que la mémoire d'instruction et de donnée ce trouve en milieu accéssible par les pirates. Leur chiffrement en devient obligatoire. -%% -%% En hard dans le proc? cache? interconnect? I/O? -% } -% -% -%\subsection{Souplesse} -%\slidetitle{Besoin de Souplesse} -% { -% {\bf Adapation aux besoins des concepteurs} -% -% \begin{itemize} -% \item Processeur hautement paramètrables -% \item Ressources internes hétérogènes -% \item FPGA -% \end{itemize} -% } -% { -% Souplesse : s'adapter aux besoins des concepteur de SoC. -% -% \begin{description} -% \item[Paramètrables :] Fournir un grand jeu de paramètres afin de satisfaire les contraintes du concepteur -% \item[Hétérogènes :] En découle des paramètres -% \item[FPGA :] Cible de + en + utilisé, Si mappage possible sur les ressources limités d'un FPGA, alors possible également sur un ASIC -% \end{description} -% } -% -%\subsection{Performance} -%\slidetitle{Besoin de Performance (1) - ILP vs TLP} -% { -% {\bf Exploitation des différentes formes de parallélisme} -% -% Paquet d'instruction pouvant s'éxecuter en parallèle : -% \begin{itemize} -% \item {\it Intra flot} : exploitation de l'ILP\newline limitation intrasèque au soft (3-5 instructions) -% \item {\it Inter flot} : exploitation du TLP \newline limitation intrasèque au système cible -% \end{itemize} -% } -% { -% \begin{itemize} -% \item ILP : superscalaire, OutOfOrder, Spéculation -% \item TLP : CMP, SMT -% \end{itemize} -% } -% -%\slidetitle{Besoin de Performance (2) - CMP vs SMT} -% { -% \printgraph{GENERAL_type_of_multi_thread}{0.5} -% -%% (schéma) -%% -%% Comparaison théorique de 5 types d'architectures : -%% ||Mono Coeur ||Mono Contexte ||Largeur infini||Idéal || -%% ||Mono Coeur ||Mono Contexte ||Largeur 4 ||Monolithique|| -%% ||Multi Coeur d'ordre 4||Mono Contexte ||Largeur 1 ||CMP || -%% ||Mono Coeur ||Multi Contexte d'ordre 4||Largeur 4 ||SMT || -%% ||Multi coeur d'ordre 2||Multi Contexte d'ordre 2||Largeur 2 ||CMP de SMT || -% } -% { -% \begin{itemize} -% \item A et B : 17 instructions en 7 UT idéale -% \item (1) : 14 UT -% \item (2) : 17 UT, 34 slot vide, occupation 50\% -% \item (3) : 12 UT, 14 slot vide, occupation 70\% -% \item (4) : 11 UT, 10 slot vide, occupation 77\% -% \end{itemize} -% } -%\slidetitle{Besoin de Performance (3) - Entre le CMP et le SMT} -% { -% \begin{description} -% \item[CMP :] L'intégralité des ressources d'un coeur sont dédiées à un contexte. -% \item[SMT :] L'intégralité des ressources d'un coeur sont partagées entre tous les contextes. -% \item[Hybride :] Multitude de possibilité de partage des ressources internes.\\ -% Une ressource est soit dédiée à un contexte soit partagée entre un certain nombre de contextes. -% \end{description} -% } -% { -% Définir ce qu'est une ressource : ALU, predicteur de branchement, cache ... -% } -% -% -%\section{Solution} -%\ContentsCurrent -%\subsection{Initiatives actuelles} -%\slidetitle{Initiatives actuelles} -% { -% Tous les processeurs sont des RISC scalaires. -% -% \begin{description} -% \item[OpenRISC 1200 :] 32 bits, 5 étages. Jusqu'à 8 contextes. -% \item[Leon 2 :] 32 bits, 5 étages. -% \item[Leon 3 :] Leon 2 en 7 étages. -% \item[OpenSparcS1 :] 1 coeur 64bits, 6 étages et CMT 4. -% \item[OpenSparcT1 :] OpenSparcS1 avec 8 coeurs. Version OpenSource du Niagara. -% \item[Micro32 :] 32 bits, 6 étages. -% \item[OpenFire :] 32 bits, 3 étages. Dérivés du MicroBlaze -% \item[aeMB :] 32 bits, 3 étages. Dérivés du MicroBlaze -% \end{description} -% } -% { -% \begin{description} -% \item[OpenRISC 1200 :] Présence icache, dcache, immu, dmmu. Taille des caches, des opérandes, du banc de registres. Matériel spécifique : div, rotate, mul, mac. -% \item[Leon 2 et 3 :] Présence de div, mul, mac, floating point. Taille du banc de registres . Nombre de load delai. Configuration avancé du cache et de la MMU (fetch, decod, execute, memory, write) (fetch, decod, register access, execute, memory, exception, write) -% \item[OpenSparc :] Présence de la Stream Processing Unit (cryptographie), 1 seul thread par coeur. -% \item[Micro32 :] Présence icache, dcache, debug. Taille des caches. Matériel spécifique : div, rotate, mul pipeline, extension de signes. -% \item[OpenFire :] 3 étages (Fetch, Decod, Execute). Faiblement configurable (largeur des données, espace d'addressage, presence de mul et de cmp). Aucun support de caches -% \item[aeMB :] 3 étages (Fetch, Decod, Execute). Support de caches. Pas configurable (Juste la largeur de l'espace d'addressage) -% \end{description} -% } -% -%\slide { -% \printgraph{GENERAL_Art_of_State-Comparaison}{0.8} -% } -% { -% } -%\subsection{Solution proposée} -%\slidetitle{Solution proposée} -% { -% \begin{itemize} -% \item Partir d'une micro-architecture HighPerf. -% \item Ajout de la gestion du multi-thread. -% \item Rendre paramétrable les ressources internes. -% \item Mappage des instances de ce générateur de processeur sur les ressources limitées d'un FPGA. -% \end{itemize} -% } -% { -% Pentium 4, MipsR10000, Power5 -% } -% -%\subsection{Métrique} -%\slidetitle{Métrique} -% { -% \begin{itemize} -% \item Obtenir le meilleur compromis Performance / Complexité. -% \begin{itemize} -% \item Performance : nombre de cycles nécessaire pour éxecuter les Benchmarks. -% \item Compléxité : surface occupée du FPGA. -% \end{itemize} -% \item Obtenir le meilleur partage des ressources entre les contextes matériels. (Gain Performance / Coût surface). -% \begin{itemize} -% \item Gain en performance : rapport entre la performance MT sur la performance ST. -% \item Coût en surface : rapport entre la surface MT sur la surface ST. -% \end{itemize} -% \end{itemize} -% } -% { -% benchmark : SPECINT2k, Dhrystone -% -% FPGA : virtex5LX 330 -% } -% -%\section{Morpheo} -%\ContentsCurrent -% -%\subsection{Micro Architecture} -%\slidetitle{Micro Architecture : Overview} -% { -% \printgraph{MORPHEO_micro_architecture-overview}{0.48} -% } -% { -% 3 grandes parties : -% \begin{description} -% \item[Front end :] Amène des paquets d'instructions en séquence, et les décodes. Calcules les addresses suivantes (spéculation) et maintiens l'état des threads (idle, wait, run ...) -% \item[Out Of Order Engine :] Renome les registres (annulations des dépendances RAW, WAW et WAR). Re Order Buffer : mettre à jour l'état du contexte dans l'ordre d'arrivé des threads. -% \item[Execution Loop :] Boucle ``Read, execute, Write''. Ainsi que les bypass. Instructions peuvent ce lancer dans le désordres. -% \end{description} -% } -% -%\slidetitle{Micro Architecture : Front end} -% { -% \printgraph{MORPHEO_micro_architecture-front_end}{0.7} -% } -% { -% } -% -%\slidetitle{Micro Architecture : Out Of Order Engine} -% { -% \printgraph{MORPHEO_micro_architecture-out_of_order_engine}{0.7} -% } -% { -% } -% -%\slidetitle{Micro Architecture : Execution Loop} -% { -% \printgraph{MORPHEO_micro_architecture-execute_loop}{0.7} -% } -% { -% } -% -%\subsection{Méthodologie} -%\slidetitle{Service proposé} -% { -% \printgraph{MORPHEO_service}{0.75} -% } -% { -% libMorpheo : -% \begin{itemize} -% \item Simulation systemC -% \begin{itemize} -% \item TestBench Vhdl -% \item Statistiques lors de la simulation -% \end{itemize} -% \item Vhdl : synthétisable sur FPGA -% \item Positions: Point d'entrée d'un outil de visualisation architectural (Stage M1) -% \end{itemize} -% } -% -%\slidetitle{Méthodologie - Boucle d'Iteration} -% { -% \printgraph{MORPHEO_methodologie}{0.3} -% } -% { -% \begin{enumerate} -% \item SystemC -% \begin{enumerate} -% \item Ecriture du modèle systemC -% \item Ecriture d'un TestBench pour le systemc - goto 1.1 -% \end{enumerate} -% \item VHDL -% \begin{enumerate} -% \item Ecriture du vhdl -% \item Validation de la stricte compatibilité entre le systemC et le Vhdl - goto 2.1 ou 1.1 -% \end{enumerate} -% \item FPGA -% \begin{enumerate} -% \item Synthèse sur FPGA - goto 2.1, 1.1 -% \item Mappage sur FPGA -% \end{enumerate} -% \end{enumerate} -% } -% -%\subsection{Perspective} -%\slidetitle{Comment remplir nos journées?} -% { -% Il "reste" à faire ... -% } -% { -% } - -\slide{}{} + \begin{center} + Variation du partage des ressources entre les contextes matérielles. + \end{center} + %Rapport entre la performance MT sur la performance ST. + + \printgraph{simulation_performance}{0.7} + } + { + DIRE : ST / MT. + + MT = exécution parallèle des benchmarks + + ST = exécution séquentielle des benchmarks + + + ordonnée : IPC + + abscisse : degré de partage + } + +\slide + { + %Rapport entre la performance MT sur la performance ST. + + \printgraph{simulation_surface}{0.7} + } + { + } + +\subsection{Méthodologie pour le modèle VHDL/RTL} + +\slidetitle{Méthodologie pour l'écriture du générateur VHDL} + { + \printgraph{VHDL_methodologie}{0.7} + } + { + FPGA : virtex5LX 330 + } + +\slidetitle{Exemple : Banc de registres 512x32 bits} + { + \printgraph{synthese_FPGA-registerfile}{0.7} + } + { + } + +\slidetitle{Planning} + { + \begin{itemize} + \item Optimisation du modèle SytemC/CABA + \item Écriture du générateur de VHDL/RTL + \item Réalisation d'un démonstrateur : + \begin{itemize} + \item synthèse sur un FPGA d'une instance du générateur. + \item exécution d'une application de test + \end{itemize} + \end{itemize} + } + { + } + +\slidetitle{Conclusion} + { + \begin{itemize} + \item Définition d'un processeur ouvert, haute performance, paramétrable et pérenne. + \item Disposer d'un outil d'aide à l'exploration architecturale + \end{itemize} + } + { + } Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all.dat (revision 56) +++ (revision ) @@ -1,13 +1,0 @@ -1.46 # x04_w08-01_e08-01 X4-1_1_4-8 -2.37 # x04_w08-04_e08-01 X4-1_2_2-8 -2.37 # x04_w08-04_e08-07 X4-1_2_2-4 -2.94 # x04_w08-07_e08-01 X4-1_4_1-8 -3.27 # x04_w08-07_e08-15 X4-1_4_1-2 -2.51 # x04_w08-08_e08-01 X4-2_1_2-8 -2.4 # x04_w08-08_e08-07 X4-2_1_2-4 -3.38 # x04_w08-11_e08-01 X4-2_2_1-8 -3.41 # x04_w08-11_e08-07b X4-2_2_1-4 -3.63 # x04_w08-11_e08-15 X4-2_2_1-2 -3.94 # x04_w08-15_e08-01 X4-4_1_1-8 -3.88 # x04_w08-15_e08-07 X4-4_1_1-4 -3.92 # x04_w08-15_e08-15 X4-4_1_1-2 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all.p =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all.p (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all.p (revision 57) @@ -8,26 +8,27 @@ set data style boxes -set boxwidth 0.5 +set boxwidth 2 set style fill solid 1.000000 border -1 - + set grid set xlabel "Architecture" -set ylabel "Speed Up MT/ST" -set yrange [0:4] +set ylabel "Ratio MT/ST" + set yrange [0:4.5] -set xtics rotate by -25 ('X4-1_1_4-8' 0 , \ - 'X4-1_2_2-8' 1 , \ - 'X4-1_2_2-4' 2 , \ - 'X4-1_4_1-8' 3 , \ - 'X4-1_4_1-2' 4 , \ - 'X4-2_1_2-8' 5 , \ - 'X4-2_1_2-4' 6 , \ - 'X4-2_2_1-8' 7 , \ - 'X4-2_2_1-4' 8 , \ - 'X4-2_2_1-2' 9 , \ - 'X4-4_1_1-8' 10, \ - 'X4-4_1_1-4' 11, \ - 'X4-4_1_1-2' 12 ) +set xtics rotate by -25 ('X4-1_1_4-8' 0 , \ + 'X4-1_2_2-8' 10 , \ + 'X4-1_2_2-4' 20 , \ + 'X4-2_1_2-8' 30 , \ + 'X4-2_1_2-4' 40 , \ + 'X4-1_4_1-8' 50 , \ + 'X4-1_4_1-2' 60 , \ + 'X4-2_2_1-8' 70 , \ + 'X4-2_2_1-4' 80 , \ + 'X4-2_2_1-2' 90 , \ + 'X4-4_1_1-8' 100, \ + 'X4-4_1_1-4' 110, \ + 'X4-4_1_1-2' 120 ) -plot "simulation_all.dat" notitle - + +plot "simulation_all_perf.dat" title "Gain de performance",\ + "simulation_all_surface.dat" title "Augmentation surface" Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all_perf.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all_perf.dat (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all_perf.dat (revision 57) @@ -0,0 +1,13 @@ +0 1.46 # x04_w08-01_e08-01 X4-1_1_4-8 +10 2.37 # x04_w08-04_e08-01 X4-1_2_2-8 +20 2.37 # x04_w08-04_e08-07 X4-1_2_2-4 +30 2.51 # x04_w08-08_e08-01 X4-2_1_2-8 +40 2.4 # x04_w08-08_e08-07 X4-2_1_2-4 +50 2.94 # x04_w08-07_e08-01 X4-1_4_1-8 +60 3.27 # x04_w08-07_e08-15 X4-1_4_1-2 +70 3.38 # x04_w08-11_e08-01 X4-2_2_1-8 +80 3.41 # x04_w08-11_e08-07b X4-2_2_1-4 +90 3.63 # x04_w08-11_e08-15 X4-2_2_1-2 +100 3.94 # x04_w08-15_e08-01 X4-4_1_1-8 +110 3.88 # x04_w08-15_e08-07 X4-4_1_1-4 +120 3.92 # x04_w08-15_e08-15 X4-4_1_1-2 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all_surface.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all_surface.dat (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all_surface.dat (revision 57) @@ -0,0 +1,13 @@ +2 1.18 # x04_w08-01_e08-01 X4-1_1_4-8 +12 2.21 # x04_w08-04_e08-01 X4-1_2_2-8 +22 2.21 # x04_w08-04_e08-07 X4-1_2_2-4 +32 2.21 # x04_w08-08_e08-01 X4-2_1_2-8 +42 2.21 # x04_w08-08_e08-07 X4-2_1_2-4 +52 4.00 # x04_w08-07_e08-01 X4-1_4_1-8 +62 4.00 # x04_w08-07_e08-15 X4-1_4_1-2 +72 4.00 # x04_w08-11_e08-01 X4-2_2_1-8 +82 4.00 # x04_w08-11_e08-07b X4-2_2_1-4 +92 4.00 # x04_w08-11_e08-15 X4-2_2_1-2 +102 4.00 # x04_w08-15_e08-01 X4-4_1_1-8 +112 4.00 # x04_w08-15_e08-07 X4-4_1_1-4 +122 4.00 # x04_w08-15_e08-15 X4-4_1_1-2 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_cachel1.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_cachel1.dat (revision 56) +++ (revision ) @@ -1,3 +1,0 @@ -2.94 # x04_w08-07_e08-01 -3.38 # x04_w08-11_e08-01 -3.94 # x04_w08-15_e08-01 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_cachel1.p =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_cachel1.p (revision 56) +++ (revision ) @@ -1,24 +1,0 @@ -set size 0.5, 1.0 -set terminal postscript eps enhanced color - -set out "../Schema_eps/simulation_cachel1.eps" - -unset label -unset log - -set data style boxes -set boxwidth 0.5 -set style fill solid 1.000000 border -1 - -set grid -set xlabel "Architecture" -set ylabel "Speed Up MT/ST" -set yrange [2:4] - -set xtics rotate by -25 ('x04\_w08-07\_e08-01 ' 0 , \ - 'x04\_w08-11\_e08-01 ' 1 , \ - 'x04\_w08-15\_e08-01 ' 2 \ - ) - -plot "simulation_cachel1.dat" notitle - Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_operative.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_operative.dat (revision 56) +++ (revision ) @@ -1,5 +1,0 @@ -1.46 # x04_w08-01_e08-01 -2.37 # x04_w08-04_e08-01 -2.94 # x04_w08-07_e08-01 -3.38 # x04_w08-11_e08-01 -3.94 # x04_w08-15_e08-01 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_operative.p =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_operative.p (revision 56) +++ (revision ) @@ -1,26 +1,0 @@ -set size 0.5, 1.0 -set terminal postscript eps enhanced color - -set out "../Schema_eps/simulation_operative.eps" - -unset label -unset log - -set data style boxes -set boxwidth 0.5 -set style fill solid 1.000000 border -1 - -set grid -set xlabel "Architecture" -set ylabel "Speed Up MT/ST" -set yrange [0:4] - -set xtics rotate by -25 ('x04\_w08-01\_e08-01 ' 0 , \ - 'x04\_w08-04\_e08-01 ' 1 , \ - 'x04\_w08-07\_e08-01 ' 2 , \ - 'x04\_w08-11\_e08-01 ' 4 , \ - 'x04\_w08-15\_e08-01 ' 5 \ - ) - -plot "simulation_operative.dat" notitle - Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_performance.p =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_performance.p (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_performance.p (revision 57) @@ -0,0 +1,34 @@ +set size 1.0, 1.0 +set terminal postscript eps enhanced color + +set out "../Schema_eps/simulation_performance.eps" + +unset label +unset log + +set data style boxes +set boxwidth 4 +set style fill solid 1.000000 border -1 + +set grid +set xlabel "Architecture" +set ylabel "IPC" +set yrange [0:5] + +set xtics rotate by -25 ('X4-1_1_4-8' 0 , \ + 'X4-1_2_2-8' 10 , \ + 'X4-1_2_2-4' 20 , \ + 'X4-2_1_2-8' 30 , \ + 'X4-2_1_2-4' 40 , \ + 'X4-1_4_1-8' 50 , \ + 'X4-1_4_1-2' 60 , \ + 'X4-2_2_1-8' 70 , \ + 'X4-2_2_1-4' 80 , \ + 'X4-2_2_1-2' 90 , \ + 'X4-4_1_1-8' 100, \ + 'X4-4_1_1-4' 110, \ + 'X4-4_1_1-2' 120 ) + +plot "simulation_performance_ST.dat" title "Performance ST",\ + "simulation_performance_MT.dat" title "Performance MT" + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_performance_MT.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_performance_MT.dat (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_performance_MT.dat (revision 57) @@ -0,0 +1,13 @@ + 4 2.93 # x04_w08-01_e08-01 X4-1_1_4-8 + 14 3.38 # x04_w08-04_e08-01 X4-1_2_2-8 + 24 3.38 # x04_w08-04_e08-07 X4-1_2_2-4 + 34 3.44 # x04_w08-08_e08-01 X4-2_1_2-8 + 44 3.39 # x04_w08-08_e08-07 X4-2_1_2-4 + 54 3.57 # x04_w08-07_e08-01 X4-1_4_1-8 + 64 3.74 # x04_w08-07_e08-15 X4-1_4_1-2 + 74 3.68 # x04_w08-11_e08-01 X4-2_2_1-8 + 84 3.75 # x04_w08-11_e08-07b X4-2_2_1-4 + 94 3.88 # x04_w08-11_e08-15 X4-2_2_1-2 +104 4.03 # x04_w08-15_e08-01 X4-4_1_1-8 +114 3.97 # x04_w08-15_e08-07 X4-4_1_1-4 +124 4.04 # x04_w08-15_e08-15 X4-4_1_1-2 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_performance_ST.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_performance_ST.dat (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_performance_ST.dat (revision 57) @@ -0,0 +1,13 @@ + 0 2.01 # x04_w08-01_e08-01 X4-1_1_4-8 + 10 1.43 # x04_w08-04_e08-01 X4-1_2_2-8 + 20 1.43 # x04_w08-04_e08-07 X4-1_2_2-4 + 30 1.37 # x04_w08-08_e08-01 X4-2_1_2-8 + 40 1.41 # x04_w08-08_e08-07 X4-2_1_2-4 + 50 1.21 # x04_w08-07_e08-01 X4-1_4_1-8 + 60 1.15 # x04_w08-07_e08-15 X4-1_4_1-2 + 70 1.09 # x04_w08-11_e08-01 X4-2_2_1-8 + 80 1.10 # x04_w08-11_e08-07b X4-2_2_1-4 + 90 1.07 # x04_w08-11_e08-15 X4-2_2_1-2 +100 1.02 # x04_w08-15_e08-01 X4-4_1_1-8 +110 1.02 # x04_w08-15_e08-07 X4-4_1_1-4 +120 1.03 # x04_w08-15_e08-15 X4-4_1_1-2 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_ratio_performance_vs_surface.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_ratio_performance_vs_surface.dat (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_ratio_performance_vs_surface.dat (revision 57) @@ -0,0 +1,13 @@ +0 1.46 # x04_w08-01_e08-01 X4-1_1_4-8 +10 1.16 # x04_w08-04_e08-01 X4-1_2_2-8 +20 1.16 # x04_w08-04_e08-07 X4-1_2_2-4 +30 1.23 # x04_w08-08_e08-01 X4-2_1_2-8 +40 1.17 # x04_w08-08_e08-07 X4-2_1_2-4 +50 0.73 # x04_w08-07_e08-01 X4-1_4_1-8 +60 0.82 # x04_w08-07_e08-15 X4-1_4_1-2 +70 0.84 # x04_w08-11_e08-01 X4-2_2_1-8 +80 0.85 # x04_w08-11_e08-07b X4-2_2_1-4 +90 0.91 # x04_w08-11_e08-15 X4-2_2_1-2 +100 0.98 # x04_w08-15_e08-01 X4-4_1_1-8 +110 0.97 # x04_w08-15_e08-07 X4-4_1_1-4 +120 0.98 # x04_w08-15_e08-15 X4-4_1_1-2 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_ratio_performance_vs_surface.p =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_ratio_performance_vs_surface.p (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_ratio_performance_vs_surface.p (revision 57) @@ -0,0 +1,32 @@ +set size 1.0, 1.0 +set terminal postscript eps enhanced color + +set out "../Schema_eps/simulation_ratio_performance_vs_surface.eps" + +unset label +unset log + +set data style boxes +set boxwidth 5 +set style fill solid 1.000000 border -1 + +set grid +set xlabel "Architecture" +set ylabel "Ratio MT/ST" + set yrange [0:1.5] + +set xtics rotate by -25 ('X4-1_1_4-8' 0 , \ + 'X4-1_2_2-8' 10 , \ + 'X4-1_2_2-4' 20 , \ + 'X4-2_1_2-8' 30 , \ + 'X4-2_1_2-4' 40 , \ + 'X4-1_4_1-8' 50 , \ + 'X4-1_4_1-2' 60 , \ + 'X4-2_2_1-8' 70 , \ + 'X4-2_2_1-4' 80 , \ + 'X4-2_2_1-2' 90 , \ + 'X4-4_1_1-8' 100, \ + 'X4-4_1_1-4' 110, \ + 'X4-4_1_1-2' 120 ) + +plot "simulation_ratio_performance_vs_surface.dat" notitle Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_surface.p =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_surface.p (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_surface.p (revision 57) @@ -0,0 +1,34 @@ +set size 1.0, 1.0 +set terminal postscript eps enhanced color + +set out "../Schema_eps/simulation_surface.eps" + +unset label +unset log + +set data style boxes +set boxwidth 4 +set style fill solid 1.000000 border -1 + +set grid +set xlabel "Architecture" +set ylabel "Nb registers" +set yrange [0:220000] + +set xtics rotate by -25 ('X4-1_1_4-8' 0 , \ + 'X4-1_2_2-8' 10 , \ + 'X4-1_2_2-4' 20 , \ + 'X4-2_1_2-8' 30 , \ + 'X4-2_1_2-4' 40 , \ + 'X4-1_4_1-8' 50 , \ + 'X4-1_4_1-2' 60 , \ + 'X4-2_2_1-8' 70 , \ + 'X4-2_2_1-4' 80 , \ + 'X4-2_2_1-2' 90 , \ + 'X4-4_1_1-8' 100, \ + 'X4-4_1_1-4' 110, \ + 'X4-4_1_1-2' 120 ) + +plot "simulation_surface_ST.dat" title "Surface ST",\ + "simulation_surface_MT.dat" title "Surface MT" + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_surface_MT.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_surface_MT.dat (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_surface_MT.dat (revision 57) @@ -0,0 +1,26 @@ + 4 217359 # x04_w08-01_e08-01 X4-1_1_4-8 + 14 189108 # x04_w08-04_e08-01 X4-1_2_2-8 + 24 189108 # x04_w08-04_e08-07 X4-1_2_2-4 + 34 189108 # x04_w08-08_e08-01 X4-2_1_2-8 + 44 189108 # x04_w08-08_e08-07 X4-2_1_2-4 + 54 171580 # x04_w08-07_e08-01 X4-1_4_1-8 + 64 171580 # x04_w08-07_e08-15 X4-1_4_1-2 + 74 171580 # x04_w08-11_e08-01 X4-2_2_1-8 + 84 171580 # x04_w08-11_e08-07b X4-2_2_1-4 + 94 171580 # x04_w08-11_e08-15 X4-2_2_1-2 +104 171580 # x04_w08-15_e08-01 X4-4_1_1-8 +114 171580 # x04_w08-15_e08-07 X4-4_1_1-4 +124 171580 # x04_w08-15_e08-15 X4-4_1_1-2 +# 4 100453 # x04_w08-01_e08-01 X4-1_1_4-8 +# 14 88000 # x04_w08-04_e08-01 X4-1_2_2-8 +# 24 88000 # x04_w08-04_e08-07 X4-1_2_2-4 +# 34 88000 # x04_w08-08_e08-01 X4-2_1_2-8 +# 44 88000 # x04_w08-08_e08-07 X4-2_1_2-4 +# 54 80000 # x04_w08-07_e08-01 X4-1_4_1-8 +# 64 80000 # x04_w08-07_e08-15 X4-1_4_1-2 +# 74 80000 # x04_w08-11_e08-01 X4-2_2_1-8 +# 84 80000 # x04_w08-11_e08-07b X4-2_2_1-4 +# 94 80000 # x04_w08-11_e08-15 X4-2_2_1-2 +#104 80000 # x04_w08-15_e08-01 X4-4_1_1-8 +#114 80000 # x04_w08-15_e08-07 X4-4_1_1-4 +#124 80000 # x04_w08-15_e08-15 X4-4_1_1-2 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_surface_ST.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_surface_ST.dat (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_surface_ST.dat (revision 57) @@ -0,0 +1,26 @@ + 0 180837 # x04_w08-01_e08-01 X4-1_1_4-8 + 10 84532 # x04_w08-04_e08-01 X4-1_2_2-8 + 20 84532 # x04_w08-04_e08-07 X4-1_2_2-4 + 30 84532 # x04_w08-08_e08-01 X4-2_1_2-8 + 40 84532 # x04_w08-08_e08-07 X4-2_1_2-4 + 50 42849 # x04_w08-07_e08-01 X4-1_4_1-8 + 60 42849 # x04_w08-07_e08-15 X4-1_4_1-2 + 70 42849 # x04_w08-11_e08-01 X4-2_2_1-8 + 80 42849 # x04_w08-11_e08-07b X4-2_2_1-4 + 90 42849 # x04_w08-11_e08-15 X4-2_2_1-2 +100 42849 # x04_w08-15_e08-01 X4-4_1_1-8 +110 42849 # x04_w08-15_e08-07 X4-4_1_1-4 +120 42849 # x04_w08-15_e08-15 X4-4_1_1-2 +# 0 85000 # x04_w08-01_e08-01 X4-1_1_4-8 +# 10 40000 # x04_w08-04_e08-01 X4-1_2_2-8 +# 20 40000 # x04_w08-04_e08-07 X4-1_2_2-4 +# 30 40000 # x04_w08-08_e08-01 X4-2_1_2-8 +# 40 40000 # x04_w08-08_e08-07 X4-2_1_2-4 +# 50 20000 # x04_w08-07_e08-01 X4-1_4_1-8 +# 60 20000 # x04_w08-07_e08-15 X4-1_4_1-2 +# 70 20000 # x04_w08-11_e08-01 X4-2_2_1-8 +# 80 20000 # x04_w08-11_e08-07b X4-2_2_1-4 +# 90 20000 # x04_w08-11_e08-15 X4-2_2_1-2 +#100 20000 # x04_w08-15_e08-01 X4-4_1_1-8 +#110 20000 # x04_w08-15_e08-07 X4-4_1_1-4 +#120 20000 # x04_w08-15_e08-15 X4-4_1_1-2 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_ue.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_ue.dat (revision 56) +++ (revision ) @@ -1,4 +1,0 @@ -3.38 # x04_w08-11_e08-01 -3.64 # x04_w08-11_e08-07a -3.41 # x04_w08-11_e08-07b -3.63 # x04_w08-11_e08-15 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_ue.p =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_ue.p (revision 56) +++ (revision ) @@ -1,25 +1,0 @@ -set size 0.5, 1.0 -set terminal postscript eps enhanced color - -set out "../Schema_eps/simulation_ue.eps" - -unset label -unset log - -set data style boxes -set boxwidth 0.5 -set style fill solid 1.000000 border -1 - -set grid -set xlabel "Architecture" -set ylabel "Speed Up MT/ST" -set yrange [2:4] - -set xtics rotate by -25 ('x04\_w08-11\_e08-01 ' 0 , \ - 'x04\_w08-11\_e08-07a' 1 , \ - 'x04\_w08-11\_e08-07b' 2 , \ - 'x04\_w08-11\_e08-15 ' 3 \ - ) - -plot "simulation_ue.dat" notitle - Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile.p =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile.p (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile.p (revision 57) @@ -0,0 +1,32 @@ +set size 1.0, 1.0 +set terminal postscript eps enhanced color + +set out "../Schema_eps/synthese_FPGA-registerfile.eps" + +unset label +unset log + +set data style boxes +set boxwidth 10 +set style fill solid 1.000000 border -1 + +set grid +set xlabel "Architecture" +set ylabel "Nombre LUTs" +set yrange [1:100000] +unset logscale; set logscale y +set xtics rotate by -25 ('R:1 W:1' 0 , \ + 'R:2 W:1' 60 , \ + 'R:4 W:1' 120 , \ + 'R:8 W:1' 180 , \ + 'R:1 W:2' 240 , \ + 'R:1 W:4' 300 , \ + 'R:1 W:8' 360 ) + +plot "synthese_FPGA-registerfile_monolithic.dat" title "monolithic",\ + "synthese_FPGA-registerfile_1_bank.dat" title "1 banc" ,\ + "synthese_FPGA-registerfile_2_bank.dat" title "2 bancs" ,\ + "synthese_FPGA-registerfile_4_bank.dat" title "4 bancs" ,\ + "synthese_FPGA-registerfile_8_bank.dat" title "8 bancs" + + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_1_bank.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_1_bank.dat (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_1_bank.dat (revision 57) @@ -0,0 +1,29 @@ + 10 580 # R:1 W:1 0 96 ( 32 64) + 10 512 # R:1 W:1 0 96 ( 32 64) + 70 591 # R:2 W:1 0 103 ( 39 64) + 70 512 # R:2 W:1 0 103 ( 39 64) +130 602 # R:4 W:1 0 110 ( 46 64) +130 512 # R:4 W:1 0 110 ( 46 64) +190 628 # R:8 W:1 0 127 ( 63 64) +190 512 # R:8 W:1 0 127 ( 63 64) +250 623 # R:1 W:2 0 135 ( 71 64) +250 512 # R:1 W:2 0 135 ( 71 64) +310 666 # R:1 W:4 0 174 ( 110 64) +310 512 # R:1 W:4 0 174 ( 110 64) +370 756 # R:1 W:8 0 256 ( 192 64) +370 512 # R:1 W:8 0 256 ( 192 64) +# 10 96 # R:1 W:1 0 96 ( 32 64) +# 10 64 # R:1 W:1 0 96 ( 32 64) +# 70 103 # R:2 W:1 0 103 ( 39 64) +# 70 64 # R:2 W:1 0 103 ( 39 64) +#130 110 # R:4 W:1 0 110 ( 46 64) +#130 64 # R:4 W:1 0 110 ( 46 64) +#190 127 # R:8 W:1 0 127 ( 63 64) +#190 64 # R:8 W:1 0 127 ( 63 64) +#250 135 # R:1 W:2 0 135 ( 71 64) +#250 64 # R:1 W:2 0 135 ( 71 64) +#310 174 # R:1 W:4 0 174 ( 110 64) +#310 64 # R:1 W:4 0 174 ( 110 64) +#370 256 # R:1 W:8 0 256 ( 192 64) +#370 64 # R:1 W:8 0 256 ( 192 64) + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_2_bank.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_2_bank.dat (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_2_bank.dat (revision 57) @@ -0,0 +1,28 @@ + 20 618 # R:1 W:1 0 228 ( 100 128) + 20 512 # R:1 W:1 0 228 ( 100 128) + 80 672 # R:2 W:1 0 274 ( 146 128) + 80 512 # R:2 W:1 0 274 ( 146 128) +140 760 # R:4 W:1 0 354 ( 226 128) +140 512 # R:4 W:1 0 354 ( 226 128) +200 942 # R:8 W:1 0 520 ( 392 128) +200 512 # R:8 W:1 0 520 ( 392 128) +260 705 # R:1 W:2 0 309 ( 181 128) +260 512 # R:1 W:2 0 309 ( 181 128) +320 795 # R:1 W:4 0 391 ( 263 128) +320 512 # R:1 W:4 0 391 ( 263 128) +380 979 # R:1 W:8 0 559 ( 431 128) +380 512 # R:1 W:8 0 559 ( 431 128) +# 20 228 # R:1 W:1 0 228 ( 100 128) +# 20 128 # R:1 W:1 0 228 ( 100 128) +# 80 274 # R:2 W:1 0 274 ( 146 128) +# 80 128 # R:2 W:1 0 274 ( 146 128) +#140 354 # R:4 W:1 0 354 ( 226 128) +#140 128 # R:4 W:1 0 354 ( 226 128) +#200 520 # R:8 W:1 0 520 ( 392 128) +#200 128 # R:8 W:1 0 520 ( 392 128) +#260 309 # R:1 W:2 0 309 ( 181 128) +#260 128 # R:1 W:2 0 309 ( 181 128) +#320 391 # R:1 W:4 0 391 ( 263 128) +#320 128 # R:1 W:4 0 391 ( 263 128) +#380 559 # R:1 W:8 0 559 ( 431 128) +#380 128 # R:1 W:8 0 559 ( 431 128) Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_4_bank.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_4_bank.dat (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_4_bank.dat (revision 57) @@ -0,0 +1,14 @@ + 30 714 # R:1 W:1 0 456 ( 200 256) + 30 512 # R:1 W:1 0 456 ( 200 256) + 90 818 # R:2 W:1 0 544 ( 288 256) + 90 512 # R:2 W:1 0 544 ( 288 256) +150 990 # R:4 W:1 0 700 ( 444 256) +150 512 # R:4 W:1 0 700 ( 444 256) +210 1090 # R:8 W:1 0 772 ( 516 256) +210 512 # R:8 W:1 0 772 ( 516 256) +270 883 # R:1 W:2 0 611 ( 355 256) +270 512 # R:1 W:2 0 611 ( 355 256) +330 1057 # R:1 W:4 0 769 ( 513 256) +330 512 # R:1 W:4 0 769 ( 513 256) +390 1413 # R:1 W:8 0 1093 ( 837 256) +390 512 # R:1 W:8 0 1093 ( 837 256) Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_8_bank.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_8_bank.dat (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_8_bank.dat (revision 57) @@ -0,0 +1,14 @@ + 40 885 # R:1 W:1 0 881 ( 369 512) + 40 512 # R:1 W:1 0 881 ( 369 512) +100 1120 # R:2 W:1 0 1084 ( 572 512) +100 512 # R:2 W:1 0 1084 ( 572 512) +160 1460 # R:4 W:1 0 1392 ( 880 512) +160 512 # R:4 W:1 0 1392 ( 880 512) +220 2163 # R:8 W:1 0 2024 (1512 512) +220 512 # R:8 W:1 0 2024 (1512 512) +280 1215 # R:1 W:2 0 1183 ( 671 512) +280 512 # R:1 W:2 0 1183 ( 671 512) +340 1555 # R:1 W:4 0 1491 ( 979 512) +340 512 # R:1 W:4 0 1491 ( 979 512) +400 2285 # R:1 W:8 0 2156 (1644 512) +400 512 # R:1 W:8 0 2156 (1644 512) Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_monolithic.dat =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_monolithic.dat (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile_monolithic.dat (revision 57) @@ -0,0 +1,28 @@ + 0 580 # R:1 W:1 0 96 ( 32 64) + 0 512 # R:1 W:1 0 96 ( 32 64) + 60 1156 # R:2 W:1 0 192 ( 64 128) + 60 1024 # R:2 W:1 0 192 ( 64 128) +120 2308 # R:4 W:1 0 384 ( 128 256) +120 2048 # R:4 W:1 0 384 ( 128 256) +180 4612 # R:8 W:1 0 768 ( 256 512) +180 4096 # R:8 W:1 0 768 ( 256 512) +240 23526 # R:1 W:2 1024 1476 (1476 0) +240 16384 # R:1 W:2 1024 1476 (1476 0) +300 43052 # R:1 W:4 1024 2639 (2639 0) +300 16384 # R:1 W:4 1024 2639 (2639 0) +360 90104 # R:1 W:8 1024 4597 (4597 0) +360 16384 # R:1 W:8 1024 4597 (4597 0) +# 0 96 # R:1 W:1 0 96 ( 32 64) +# 0 64 # R:1 W:1 0 96 ( 32 64) +# 60 192 # R:2 W:1 0 192 ( 64 128) +# 60 128 # R:2 W:1 0 192 ( 64 128) +#120 384 # R:4 W:1 0 384 ( 128 256) +#120 256 # R:4 W:1 0 384 ( 128 256) +#180 768 # R:8 W:1 0 768 ( 256 512) +#180 512 # R:8 W:1 0 768 ( 256 512) +#240 1476 # R:1 W:2 1024 1476 (1476 0) +#240 1024 # R:1 W:2 1024 1476 (1476 0) +#300 2639 # R:1 W:4 1024 2639 (2639 0) +#300 1024 # R:1 W:4 1024 2639 (2639 0) +#360 4597 # R:1 W:8 1024 4597 (4597 0) +#360 1024 # R:1 W:8 1024 4597 (4597 0) Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.sed =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.sed (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.sed (revision 57) @@ -1,4 +1,2 @@ -\documentclass{beamer} - \def\lang{@LANG} \def\file{@FILE} @@ -9,8 +7,8 @@ \def\dirroot{\dirdoc/\lang} +% Package de variables d'environnement : Titre, command etc ... -% Package de variables d'environnement : Titre, command etc ... +\include{\dirpackage/\file} \usepackage{Include/ppt-style} -\include{\dirpackage/\file} \usepackage{\dirpackage/\file} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.tex (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.tex (revision 57) @@ -1,2 +1,5 @@ +%\documentclass{article} +\documentclass{beamer} + \usepackage{beamerthemetree} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-style.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-style.sty (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-style.sty (revision 57) @@ -1,4 +1,5 @@ \typeout{Fichier de style `ppt-style.sty'.} +\usepackage{beamerarticle} \usepackage{graphicx} \usepackage{tabularx} @@ -9,7 +10,12 @@ \usepackage{pgf,pgfarrows,pgfheaps,pgfnodes,pgfpages,pgfshade} \usepackage{openbib} +\usepackage{ulem} \bibliographystyle{plain} -%\useoutertheme{infolines} +\addtobeamertemplate{footline}{\insertframenumber/\inserttotalframenumber} + +\setbeameroption{show notes on second screen} + +%\useoutertheme{splitbarsbackground} %\usetheme{Darmstadt} %\usetheme{Malmoe} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-internal_seminary_overview.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-internal_seminary_overview.sty (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-internal_seminary_overview.sty (revision 57) @@ -1,15 +1,14 @@ -\def\review{2007/09/21} +\def\review{2007/09/28} %\def\review{\number\day/\number\month/\number\year\xspace} -\title{Séminaire interne :\newline Processeur libre, haute performance et paramètrable} +\title{MORPHEO :\newline Processeur ouvert, haute performance, paramétrable et pérenne pour plate-forme de confiance.} -\institute{Département ALSOC - Laboratoire d'informatique de Paris VI - France} +\institute{Département SOC - Laboratoire d'informatique de Paris VI - France} -\author{Mathieu Rosière\\ - encadrement :\\ - Nathalie Drach-Temam\\ - Jean-Lou Desbarbieux\\ - Franck Wajsbürt -} +\author{Mathieu Rosière\newline + encadrement :\newline + Nathalie Drach-Temam\newline + Jean-Lou Desbarbieux\newline + Franck Wajsbürt} \date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-internal_seminary_overview.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-internal_seminary_overview.tex (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-internal_seminary_overview.tex (revision 57) @@ -1,3 +1,8 @@ +%\documentclass[10pt,a4paper,onecolumn]{article} +\documentclass{beamer} \usepackage{beamerthemetree} -%\setbeameroption{show notes on second screen} + + + + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-share_architectural_ressources_between_hardware_context.lang =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-share_architectural_ressources_between_hardware_context.lang (revision 56) +++ (revision ) @@ -1,1 +1,0 @@ -fr Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-share_architectural_ressources_between_hardware_context.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-share_architectural_ressources_between_hardware_context.sty (revision 56) +++ (revision ) @@ -1,9 +1,0 @@ -\def\review{2006/10/13} - -\title{Incidence du partage des ressources architecturales entre les contextes matériels} - -\institute{Equipe SOC - Laboratoire d'information de Paris VI - France} - -\author{Mathieu Rosière} - -\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-share_architectural_ressources_between_hardware_context.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-share_architectural_ressources_between_hardware_context.tex (revision 56) +++ (revision ) @@ -1,3 +1,0 @@ -\usepackage{beamerthemetree} - -%\setbeameroption{show notes on second screen} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-share_architectural_ressources_between_hardware_context.type =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-share_architectural_ressources_between_hardware_context.type (revision 56) +++ (revision ) @@ -1,1 +1,0 @@ -ppt Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Link/presentation-share_architectural_ressources_between_hardware_context-fr =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Link/presentation-share_architectural_ressources_between_hardware_context-fr (revision 56) +++ (revision ) @@ -1,1 +1,0 @@ -link ../Documents/presentation-share_architectural_ressources_between_hardware_context/fr Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile (revision 57) @@ -94,11 +94,11 @@ %.pdf : %.ps @\ - $(ECHO) "Génération du fichier $*.pdf"; \ - $(PS2PDF) $< $@; \ + $(ECHO) "Génération du fichier $*.pdf"; \ + $(PS2PDF) $< $@; \ $(CP) $@ $(DIR_DOCUMENTATION); %.ps : %.dvi @\ - $(ECHO) "Génération du fichier $*.ps"; \ + $(ECHO) "Génération du fichier $*.ps"; \ $(DVIPS) -o $@ $<; @@ -106,13 +106,15 @@ %.dvi : $(DIR_TEX)/%.tex @\ - $(ECHO) "Génération du fichier $*.dvi"; \ - $(LATEX_WITH_ENV) $<; \ - $(LATEX_WITH_ENV) $< > /dev/null; \ - citation=`$(GREP) "citation" $*.aux`; \ - if $(TEST) -n "$$citation" ; then \ - $(BIBTEX) $* ; \ - fi; \ - $(LATEX_WITH_ENV) $< > /dev/null; \ - $(LATEX_WITH_ENV) $< > /dev/null; + $(ECHO) "Génération du fichier $*.dvi"; \ + $(LATEX_WITH_ENV) $<; \ + if $(TEST) $? -eq 0; then \ + $(LATEX_WITH_ENV) $< > /dev/null; \ + citation=`$(GREP) "citation" $*.aux`; \ + if $(TEST) -n "$$citation" ; then \ + $(BIBTEX) $* ; \ + fi; \ + $(LATEX_WITH_ENV) $< > /dev/null; \ + $(LATEX_WITH_ENV) $< > /dev/null; \ + fi; #-------------------------------------------------------------------------------- @@ -348,6 +350,6 @@ declare -a VIEWER; \ \ - FORMAT=("pdf" "pdf" "ps" "dvi"); \ - VIEWER=($(VIEWPDF_FS) $(VIEWPDF) $(VIEWPS) $(VIEWDVI)); \ + FORMAT=("pdf" "pdf" "ps" "dvi"); \ + VIEWER=("$(VIEWPDF_FS)" "$(VIEWPDF)" "$(VIEWPS)" "$(VIEWDVI)"); \ \ CPT=0; \ @@ -378,35 +380,35 @@ $(DIR_SCHEMA_EPS) : @\ - $(ECHO) "Make directory : $@"; \ + $(ECHO) "Make directory : $@"; \ $(MKDIR) $@; $(DIR_SCHEMA_PNG) : @\ - $(ECHO) "Make directory : $@"; \ + $(ECHO) "Make directory : $@"; \ $(MKDIR) $@; $(DIR_TEX) : @\ - $(ECHO) "Make directory : $@"; \ + $(ECHO) "Make directory : $@"; \ $(MKDIR) $@; $(DIR_SCHEMA_PNG)/%.png : $(DIR_SCHEMA_EPS)/%.eps $(DIR_SCHEMA_PNG) @\ - $(ECHO) "Generate files : $*.png"; \ + $(ECHO) "Generate files : $*.png"; \ $(EPS2PNG) $< $@; $(DIR_SCHEMA_EPS)/%.eps : $(DIR_SCHEMA)/%.eps $(DIR_SCHEMA_EPS) @\ - $(ECHO) "Generate files : $*.eps"; \ + $(ECHO) "Generate files : $*.eps"; \ $(CP) $(DIR_SCHEMA)/$*.eps $(DIR_SCHEMA_EPS); $(DIR_SCHEMA_EPS)/%.eps : $(DIR_SCHEMA)/%.fig $(DIR_SCHEMA_EPS) @\ - $(ECHO) "Generate files : $*.eps"; \ + $(ECHO) "Generate files : $*.eps"; \ $(FIG2EPS) $< $@; $(DIR_SCHEMA_EPS)/%.eps : $(DIR_GRAPH)/%.p $(DIR_SCHEMA_EPS) @\ - $(ECHO) "Generate files : $*.eps"; \ + $(ECHO) "Generate files : $*.eps"; \ $(CD) $(DIR_GRAPH); $(GNUPLOT) $*.p; Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_DLP.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_DLP.fig (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_DLP.fig (revision 57) @@ -0,0 +1,137 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 3870 1980 4680 2790 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 3870 2250 4680 2250 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 3870 2520 4680 2520 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 4140 1980 4140 2790 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 4410 1980 4410 2790 +2 2 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 5 + 3870 1980 4680 1980 4680 2790 3870 2790 3870 1980 +4 1 0 50 -1 0 8 0.0000 0 75 120 4005 2160 22\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 4275 2430 125\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 4545 2160 215\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 4005 2700 48\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 4005 2430 35\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 4275 2160 79\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 4545 2700 129\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 4545 2430 168\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 4275 2700 177\001 +-6 +6 5490 1980 6300 2790 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 5490 2250 6300 2250 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 5490 2520 6300 2520 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 5760 1980 5760 2790 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 6030 1980 6030 2790 +2 2 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 5 + 5490 1980 6300 1980 6300 2790 5490 2790 5490 1980 +4 1 0 50 -1 0 8 0.0000 0 75 120 5625 2160 32\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 5625 2430 45\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 5625 2700 58\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 5895 2160 89\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 5895 2430 135\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 5895 2700 187\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 6165 2700 139\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 6165 2430 178\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 6165 2160 225\001 +-6 +6 3870 3330 4680 4140 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 3870 3600 4680 3600 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 3870 3870 4680 3870 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 4140 3330 4140 4140 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 4410 3330 4410 4140 +2 2 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 5 + 3870 3330 4680 3330 4680 4140 3870 4140 3870 3330 +4 1 0 50 -1 0 8 0.0000 0 75 120 4005 3510 22\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 4275 3780 125\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 4545 3510 215\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 4005 4050 48\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 4005 3780 35\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 4275 3510 79\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 4545 4050 129\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 4545 3780 168\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 4275 4050 177\001 +-6 +6 5490 3330 6300 4140 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 5490 3600 6300 3600 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 5490 3870 6300 3870 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 5760 3330 5760 4140 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 6030 3330 6030 4140 +2 2 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 5 + 5490 3330 6300 3330 6300 4140 5490 4140 5490 3330 +4 1 0 50 -1 0 8 0.0000 0 75 120 5625 3510 32\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 5625 3780 45\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 5895 3510 89\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 5895 3780 135\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 5895 4050 187\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 6165 4050 139\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 6165 3780 178\001 +4 1 0 50 -1 0 8 0.0000 0 75 180 6165 3510 225\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 5625 4050 58\001 +-6 +1 3 0 1 1 7 50 -1 -1 4.000 1 0.0000 4005 2115 180 180 4005 2115 4185 2115 +1 3 0 1 1 7 50 -1 -1 4.000 1 0.0000 4275 3735 557 557 4275 3735 4815 3600 +3 2 0 1 4 7 50 -1 -1 4.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 3915 2025 4725 1755 5535 2025 + 0.000 -1.000 0.000 +3 2 0 1 4 7 50 -1 -1 4.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 4279 2038 5089 1768 5899 2038 + 0.000 -1.000 0.000 +3 2 0 1 4 7 50 -1 -1 4.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 4635 2025 5445 1755 6255 2025 + 0.000 -1.000 0.000 +3 2 0 1 4 7 50 -1 -1 4.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 3919 2758 4729 3028 5539 2758 + 0.000 -1.000 0.000 +3 2 0 1 4 7 50 -1 -1 4.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 4275 2745 5085 3015 5895 2745 + 0.000 -1.000 0.000 +3 2 0 1 4 7 50 -1 -1 4.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 4545 2745 5355 3015 6165 2745 + 0.000 -1.000 0.000 +3 2 0 1 4 7 50 -1 -1 4.000 0 1 0 2 + 3 0 1.00 60.00 120.00 + 4005 2295 5625 2295 + 0.000 0.000 +3 2 0 1 4 7 50 -1 -1 4.000 0 1 0 2 + 3 0 1.00 60.00 120.00 + 4275 2385 5895 2385 + 0.000 0.000 +3 2 0 1 4 7 50 -1 -1 4.000 0 1 0 2 + 3 0 1.00 60.00 120.00 + 4545 2475 6165 2475 + 0.000 0.000 +3 2 0 1 4 7 50 -1 -1 4.000 0 1 0 2 + 3 0 1.00 60.00 120.00 + 4275 3735 5895 3735 + 0.000 0.000 +4 2 0 50 -1 0 10 0.0000 0 135 750 3645 2160 Type de base\001 +4 2 0 50 -1 0 10 0.0000 0 135 750 3645 3780 Type de base\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_ILP.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_ILP.fig (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_ILP.fig (revision 57) @@ -0,0 +1,91 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 3690 1890 5130 2655 +6 3690 1935 3960 2655 +4 1 0 50 -1 0 10 0.0000 0 135 195 3825 2250 (2)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3825 2070 (1)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3825 2430 (3)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3825 2610 (4)\001 +-6 +1 3 0 1 4 0 50 -1 -1 0.000 1 0.0000 4095 2025 101 101 4095 2025 4185 2070 +1 3 0 1 4 0 50 -1 -1 0.000 1 0.0000 4455 2205 90 90 4455 2205 4545 2205 +2 1 0 1 4 0 50 -1 -1 0.000 0 0 -1 0 0 2 + 4185 2070 4365 2160 +4 1 0 50 -1 0 10 0.0000 0 105 135 4095 2070 r1\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 4275 2070 =\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4455 2070 r2\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4095 2250 r4\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 4275 2250 =\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 4275 2430 =\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 4275 2610 =\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4455 2250 r1\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4095 2430 r6\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4455 2430 r7\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4095 2610 r9\001 +4 1 0 50 -1 0 10 0.0000 0 105 210 4455 2610 r10\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4995 2430 r8\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4995 2250 r5\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4995 2070 r3\001 +4 1 0 50 -1 0 10 0.0000 0 105 210 4995 2610 r11\001 +4 1 14 50 -1 0 10 0.0000 0 135 225 4725 2610 op1\001 +4 1 14 50 -1 0 10 0.0000 0 135 225 4725 2250 op1\001 +4 1 14 50 -1 0 10 0.0000 0 135 225 4725 2070 op1\001 +4 1 1 50 -1 0 10 0.0000 0 135 225 4725 2430 op2\001 +-6 +2 1 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 2 + 4230 2880 4230 3060 +2 1 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 2 + 4410 2880 4410 3060 +2 1 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 2 + 4590 2880 4590 3060 +2 2 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 5 + 4050 2880 4770 2880 4770 3060 4050 3060 4050 2880 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 3870 3690 3870 3330 4950 3330 4950 3690 3870 3690 +2 4 0 1 0 14 50 -1 20 0.000 0 0 7 0 0 5 + 3600 4230 3600 3960 3870 3960 3870 4230 3600 4230 +2 4 0 1 0 1 50 -1 20 0.000 0 0 7 0 0 5 + 5220 4230 5220 3960 4950 3960 4950 4230 5220 4230 +2 4 0 1 0 1 50 -1 20 0.000 0 0 7 0 0 5 + 4320 4230 4320 3960 4050 3960 4050 4230 4320 4230 +2 4 0 1 0 14 50 -1 20 0.000 0 0 7 0 0 5 + 4500 4230 4500 3960 4770 3960 4770 4230 4500 4230 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 4140 3060 4005 3510 3735 3960 + 0.000 -1.000 0.000 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 4500 3060 4410 3510 4185 3960 + 0.000 -1.000 0.000 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 4680 3060 4680 3510 4635 3960 + 0.000 -1.000 0.000 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 2 + 3 0 1.00 60.00 120.00 + 4320 3060 4320 3240 + 0.000 0.000 +3 2 0 1 4 14 50 -1 -1 0.000 0 0 0 2 + 4365 3285 4275 3195 + 0.000 0.000 +3 2 0 1 4 14 50 -1 -1 0.000 0 0 0 2 + 4275 3285 4365 3195 + 0.000 0.000 +4 1 0 50 -1 0 10 0.0000 0 135 195 4680 3015 (4)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4500 3015 (3)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4320 3015 (2)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4140 3015 (1)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3735 4410 (1)\001 +4 0 0 50 -1 0 10 0.0000 0 105 630 5400 4140 Execution\001 +4 0 0 50 -1 0 10 0.0000 0 105 960 5400 3510 Select and Issue\001 +4 0 0 50 -1 0 10 0.0000 0 105 1215 5400 3015 Instructions bundle\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4635 4410 (4)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4185 4410 (3)\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_TLP-CMP.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_TLP-CMP.fig (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_TLP-CMP.fig (revision 57) @@ -0,0 +1,101 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 3600 1935 6615 4455 +6 3645 2295 5175 2655 +4 1 0 50 -1 0 10 0.0000 0 45 90 4320 2430 =\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 4320 2610 =\001 +4 1 14 50 -1 0 10 0.0000 0 135 225 4770 2610 op1\001 +4 1 1 50 -1 0 10 0.0000 0 135 225 4770 2430 op2\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4140 2430 r7\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4500 2430 r8\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 5040 2430 r9\001 +4 1 0 50 -1 0 10 0.0000 0 105 210 4140 2610 r10\001 +4 1 0 50 -1 0 10 0.0000 0 105 210 4500 2610 r11\001 +4 1 0 50 -1 0 10 0.0000 0 105 210 5040 2610 r12\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3780 2430 (3)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3780 2610 (4)\001 +-6 +6 3645 1935 5130 2295 +4 1 0 50 -1 0 10 0.0000 0 105 135 4140 2070 r1\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 4320 2070 =\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4500 2070 r2\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4140 2250 r4\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 4320 2250 =\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 5040 2070 r3\001 +4 1 14 50 -1 0 10 0.0000 0 135 225 4770 2250 op1\001 +4 1 14 50 -1 0 10 0.0000 0 135 225 4770 2070 op1\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4500 2250 r5\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 5040 2250 r6\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3780 2250 (2)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3780 2070 (1)\001 +-6 +6 4635 2880 5085 3060 +2 1 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 2 + 4860 2880 4860 3060 +4 1 0 50 -1 0 10 0.0000 0 135 195 4950 3015 (4)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4770 3015 (3)\001 +-6 +6 3735 2880 4185 3060 +2 1 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 2 + 3960 2880 3960 3060 +4 1 0 50 -1 0 10 0.0000 0 135 195 4050 3015 (2)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3870 3015 (1)\001 +-6 +6 4005 3060 4095 3285 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 2 + 3 0 1.00 60.00 120.00 + 4050 3060 4050 3240 + 0.000 0.000 +3 2 0 1 4 14 50 -1 -1 0.000 0 0 0 2 + 4095 3285 4005 3195 + 0.000 0.000 +3 2 0 1 4 14 50 -1 -1 0.000 0 0 0 2 + 4005 3285 4095 3195 + 0.000 0.000 +-6 +2 4 0 1 0 14 50 -1 20 0.000 0 0 7 0 0 5 + 3600 4230 3600 3960 3870 3960 3870 4230 3600 4230 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 3690 3690 3690 3330 4230 3330 4230 3690 3690 3690 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 4590 3690 4590 3330 5130 3330 5130 3690 4590 3690 +2 4 0 1 0 1 50 -1 20 0.000 0 0 7 0 0 5 + 4320 4230 4320 3960 4050 3960 4050 4230 4320 4230 +2 4 0 1 0 1 50 -1 20 0.000 0 0 7 0 0 5 + 5220 4230 5220 3960 4950 3960 4950 4230 5220 4230 +2 4 0 1 0 14 50 -1 20 0.000 0 0 7 0 0 5 + 4500 4230 4500 3960 4770 3960 4770 4230 4500 4230 +2 2 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 5 + 3780 2880 4140 2880 4140 3060 3780 3060 3780 2880 +2 2 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 5 + 4680 2880 5040 2880 5040 3060 4680 3060 4680 2880 +2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2 + 3600 2295 5220 2295 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 3870 3060 3780 3510 3735 3960 + 0.000 -1.000 0.000 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 4950 3060 4950 3510 4635 3960 + 0.000 -1.000 0.000 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 4770 3060 4770 3510 5085 3960 + 0.000 -1.000 0.000 +4 1 0 50 -1 0 10 0.0000 0 135 195 3735 4410 (1)\001 +4 0 0 50 -1 0 10 0.0000 0 105 630 5400 4140 Execution\001 +4 0 0 50 -1 0 10 0.0000 0 105 960 5400 3510 Select and Issue\001 +4 0 0 50 -1 0 10 0.0000 0 105 1215 5400 3015 Instructions bundle\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 5085 4410 (3)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4635 4410 (4)\001 +4 0 0 50 -1 0 10 0.0000 0 105 525 5400 2160 Thread 0\001 +4 0 0 50 -1 0 10 0.0000 0 105 525 5400 2520 Thread 1\001 +-6 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_TLP-SMT.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_TLP-SMT.fig (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_TLP-SMT.fig (revision 57) @@ -0,0 +1,101 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 3645 2295 5175 2655 +4 1 0 50 -1 0 10 0.0000 0 45 90 4320 2430 =\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 4320 2610 =\001 +4 1 14 50 -1 0 10 0.0000 0 135 225 4770 2610 op1\001 +4 1 1 50 -1 0 10 0.0000 0 135 225 4770 2430 op2\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4140 2430 r7\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4500 2430 r8\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 5040 2430 r9\001 +4 1 0 50 -1 0 10 0.0000 0 105 210 4140 2610 r10\001 +4 1 0 50 -1 0 10 0.0000 0 105 210 4500 2610 r11\001 +4 1 0 50 -1 0 10 0.0000 0 105 210 5040 2610 r12\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3780 2430 (3)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3780 2610 (4)\001 +-6 +6 3645 1935 5130 2295 +4 1 0 50 -1 0 10 0.0000 0 105 135 4140 2070 r1\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 4320 2070 =\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4500 2070 r2\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4140 2250 r4\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 4320 2250 =\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 5040 2070 r3\001 +4 1 14 50 -1 0 10 0.0000 0 135 225 4770 2250 op1\001 +4 1 14 50 -1 0 10 0.0000 0 135 225 4770 2070 op1\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4500 2250 r5\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 5040 2250 r6\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3780 2250 (2)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3780 2070 (1)\001 +-6 +6 4455 2880 4905 3060 +6 4455 2880 4905 3060 +2 1 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 2 + 4680 2880 4680 3060 +4 1 0 50 -1 0 10 0.0000 0 135 195 4770 3015 (4)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4590 3015 (3)\001 +-6 +2 2 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 5 + 4500 2880 4860 2880 4860 3060 4500 3060 4500 2880 +-6 +6 3915 2880 4365 3060 +6 3915 2880 4365 3060 +2 1 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 2 + 4140 2880 4140 3060 +4 1 0 50 -1 0 10 0.0000 0 135 195 4230 3015 (2)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4050 3015 (1)\001 +-6 +2 2 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 5 + 3960 2880 4320 2880 4320 3060 3960 3060 3960 2880 +-6 +6 4725 3060 4815 3285 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 2 + 3 0 1.00 60.00 120.00 + 4770 3060 4770 3240 + 0.000 0.000 +3 2 0 1 4 14 50 -1 -1 0.000 0 0 0 2 + 4815 3285 4725 3195 + 0.000 0.000 +3 2 0 1 4 14 50 -1 -1 0.000 0 0 0 2 + 4725 3285 4815 3195 + 0.000 0.000 +-6 +2 4 0 1 0 14 50 -1 20 0.000 0 0 7 0 0 5 + 3600 4230 3600 3960 3870 3960 3870 4230 3600 4230 +2 4 0 1 0 1 50 -1 20 0.000 0 0 7 0 0 5 + 4320 4230 4320 3960 4050 3960 4050 4230 4320 4230 +2 4 0 1 0 1 50 -1 20 0.000 0 0 7 0 0 5 + 5220 4230 5220 3960 4950 3960 4950 4230 5220 4230 +2 4 0 1 0 14 50 -1 20 0.000 0 0 7 0 0 5 + 4500 4230 4500 3960 4770 3960 4770 4230 4500 4230 +2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2 + 3600 2295 5220 2295 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 3780 3690 3780 3330 5040 3330 5040 3690 3780 3690 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 4050 3060 3960 3510 3735 3960 + 0.000 -1.000 0.000 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 4230 3060 4320 3510 4635 3960 + 0.000 -1.000 0.000 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 4590 3060 4680 3510 5085 3960 + 0.000 -1.000 0.000 +4 1 0 50 -1 0 10 0.0000 0 135 195 3735 4410 (1)\001 +4 0 0 50 -1 0 10 0.0000 0 105 630 5400 4140 Execution\001 +4 0 0 50 -1 0 10 0.0000 0 105 960 5400 3510 Select and Issue\001 +4 0 0 50 -1 0 10 0.0000 0 105 1215 5400 3015 Instructions bundle\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 5085 4410 (3)\001 +4 0 0 50 -1 0 10 0.0000 0 105 525 5400 2160 Thread 0\001 +4 0 0 50 -1 0 10 0.0000 0 105 525 5400 2520 Thread 1\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4635 4410 (2)\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_TLP.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_TLP.fig (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_TLP.fig (revision 57) @@ -0,0 +1,105 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 4635 2880 5085 3060 +2 1 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 2 + 4860 2880 4860 3060 +4 1 0 50 -1 0 10 0.0000 0 135 195 4950 3015 (4)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4770 3015 (3)\001 +-6 +6 3735 2880 4185 3060 +2 1 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 2 + 3960 2880 3960 3060 +4 1 0 50 -1 0 10 0.0000 0 135 195 4050 3015 (2)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 3870 3015 (1)\001 +-6 +6 4005 3060 4095 3285 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 2 + 3 0 1.00 60.00 120.00 + 4050 3060 4050 3240 + 0.000 0.000 +3 2 0 1 4 14 50 -1 -1 0.000 0 0 0 2 + 4095 3285 4005 3195 + 0.000 0.000 +3 2 0 1 4 14 50 -1 -1 0.000 0 0 0 2 + 4005 3285 4095 3195 + 0.000 0.000 +-6 +6 4905 3060 4995 3285 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 2 + 3 0 1.00 60.00 120.00 + 4950 3060 4950 3240 + 0.000 0.000 +3 2 0 1 4 14 50 -1 -1 0.000 0 0 0 2 + 4995 3285 4905 3195 + 0.000 0.000 +3 2 0 1 4 14 50 -1 -1 0.000 0 0 0 2 + 4905 3285 4995 3195 + 0.000 0.000 +-6 +6 3015 2295 4095 2655 +4 1 0 50 -1 0 10 0.0000 0 105 135 3105 2430 r1\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 3285 2430 =\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 3465 2430 r2\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 3105 2610 r4\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 3285 2610 =\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4005 2430 r3\001 +4 1 14 50 -1 0 10 0.0000 0 135 225 3735 2610 op1\001 +4 1 14 50 -1 0 10 0.0000 0 135 225 3735 2430 op1\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 3465 2610 r5\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4005 2610 r6\001 +-6 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 4410 4500 4410 2160 +2 4 0 1 0 14 50 -1 20 0.000 0 0 7 0 0 5 + 3600 4230 3600 3960 3870 3960 3870 4230 3600 4230 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 3690 3690 3690 3330 4230 3330 4230 3690 3690 3690 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 4590 3690 4590 3330 5130 3330 5130 3690 4590 3690 +2 4 0 1 0 1 50 -1 20 0.000 0 0 7 0 0 5 + 4320 4230 4320 3960 4050 3960 4050 4230 4320 4230 +2 4 0 1 0 1 50 -1 20 0.000 0 0 7 0 0 5 + 5220 4230 5220 3960 4950 3960 4950 4230 5220 4230 +2 4 0 1 0 14 50 -1 20 0.000 0 0 7 0 0 5 + 4500 4230 4500 3960 4770 3960 4770 4230 4500 4230 +2 2 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 5 + 3780 2880 4140 2880 4140 3060 3780 3060 3780 2880 +2 2 0 1 0 0 50 -1 -1 0.000 0 0 -1 0 0 5 + 4680 2880 5040 2880 5040 3060 4680 3060 4680 2880 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 3870 3060 3780 3510 3735 3960 + 0.000 -1.000 0.000 +3 2 0 1 5 14 50 -1 -1 0.000 0 1 0 3 + 3 0 1.00 60.00 120.00 + 4770 3060 4770 3510 5085 3960 + 0.000 -1.000 0.000 +4 1 0 50 -1 0 10 0.0000 0 135 195 3735 4410 (1)\001 +4 0 0 50 -1 0 10 0.0000 0 105 630 5400 4140 Execution\001 +4 0 0 50 -1 0 10 0.0000 0 105 960 5400 3510 Select and Issue\001 +4 0 0 50 -1 0 10 0.0000 0 105 1215 5400 3015 Instructions bundle\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 5085 4410 (3)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4635 4410 (4)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4545 2430 (3)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4545 2610 (4)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4275 2430 (1)\001 +4 1 0 50 -1 0 10 0.0000 0 135 195 4275 2610 (2)\001 +4 0 0 50 -1 0 10 0.0000 0 105 525 4545 2250 Thread 1\001 +4 2 0 50 -1 0 10 0.0000 0 105 525 4275 2250 Thread 0\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 4815 2430 r7\001 +4 1 0 50 -1 0 10 0.0000 0 105 210 4815 2610 r10\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 4995 2430 =\001 +4 1 0 50 -1 0 10 0.0000 0 45 90 4995 2610 =\001 +4 1 1 50 -1 0 10 0.0000 0 135 225 5445 2430 op2\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 5175 2430 r8\001 +4 1 0 50 -1 0 10 0.0000 0 105 135 5715 2430 r9\001 +4 1 0 50 -1 0 10 0.0000 0 105 210 5175 2610 r11\001 +4 1 0 50 -1 0 10 0.0000 0 105 210 5715 2610 r12\001 +4 1 1 50 -1 0 10 0.0000 0 135 225 5445 2610 op2\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_hardware.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_hardware.fig (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/GENERAL_hardware.fig (revision 57) @@ -0,0 +1,42 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +2 1 0 1 0 0 49 -1 -1 0.000 0 0 -1 0 0 2 + 3000 4950 5400 4950 +2 1 0 1 0 0 49 -1 -1 0.000 0 0 -1 0 0 2 + 6000 4950 8400 4950 +2 1 0 1 0 0 49 -1 -1 0.000 0 0 -1 0 0 2 + 4425 3300 6825 3300 +2 4 0 1 0 6 50 -1 20 0.000 0 0 7 0 0 5 + 3000 5625 3000 4275 5400 4275 5400 5625 3000 5625 +2 4 0 1 0 5 50 -1 20 0.000 0 0 7 0 0 5 + 8400 4275 8400 5625 6000 5625 6000 4275 8400 4275 +2 4 0 1 0 14 50 -1 20 0.000 0 0 7 0 0 5 + 6825 3975 4425 3975 4425 2625 6825 2625 6825 3975 +4 1 0 50 -1 0 10 0.0000 0 135 870 7200 4875 Cell, Cray, ...\001 +4 1 0 50 -1 0 10 0.0000 0 135 1005 7200 5550 SSE, Altivec, ...\001 +4 1 0 50 -1 0 10 0.0000 0 135 1800 4200 5550 Pentium 4 HT, POWER 5, ...\001 +4 1 0 50 -1 0 10 0.0000 0 150 1800 4200 5325 Ressources internes partag\351es\001 +4 1 0 50 -1 0 10 0.0000 0 120 1665 4200 4650 Ressources internes d\351di\351es\001 +4 1 0 50 -1 0 10 0.0000 0 135 1710 7200 4650 Vecteur comme type de base\001 +4 1 0 50 -1 0 10 0.0000 0 135 1995 7200 5325 Vecteur comme type additionnel\001 +4 1 0 50 -1 0 10 0.0000 0 135 1755 5625 3900 Itanium, TriMedia, Stacs, ...\001 +4 1 0 50 -1 0 10 0.0000 0 135 1095 5625 3675 Controle statique\001 +4 1 0 50 -1 0 10 0.0000 0 135 1755 5625 3225 Pentium 4, Mips R10000, ...\001 +4 1 0 50 -1 0 10 0.0000 0 135 1260 5625 3000 Controle dynamique\001 +4 1 0 50 -1 0 10 0.0000 0 135 1710 4200 4875 Core duo, Athlon 64 X2, ...\001 +4 1 0 50 -1 2 12 0.0000 0 180 1740 4200 4425 Chip Multi Processing\001 +4 1 0 50 -1 2 12 0.0000 0 135 1710 7200 4425 Processeur vectoriel\001 +4 1 0 50 -1 2 12 0.0000 0 180 1185 5625 2775 Super Scalaire\001 +4 1 0 50 -1 2 12 0.0000 0 180 2265 5625 3450 Very Long Instruction Word\001 +4 1 0 50 -1 2 12 0.0000 0 135 1320 7200 5100 Extension SIMD\001 +4 1 0 50 -1 2 12 0.0000 0 180 2385 4200 5100 Simultaneous Multi Threading\001 +4 1 0 50 -1 3 12 0.0000 0 135 330 4200 4200 TLP\001 +4 1 0 50 -1 3 12 0.0000 0 135 360 7200 4200 DLP\001 +4 1 0 50 -1 3 12 0.0000 0 135 300 5625 2550 ILP\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex01.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex01.fig (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex01.fig (revision 57) @@ -0,0 +1,179 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 4770 3690 5490 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3960 decod\001 +-6 +6 4770 3240 5490 3690 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001 +-6 +6 5850 3690 6570 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 6570 4140 5850 4140 5850 3690 6570 3690 6570 4140 +4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 3960 rename\001 +-6 +6 8370 3690 9090 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9090 4140 8370 4140 8370 3690 9090 3690 9090 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 330 8730 3960 read\001 +-6 +6 11250 3690 11970 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 11970 4140 11250 4140 11250 3690 11970 3690 11970 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 390 11610 3960 write\001 +-6 +6 9810 2475 10530 2925 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 2925 9810 2925 9810 2475 10530 2475 10530 2925 +4 1 0 50 -1 -1 12 0.0000 4 150 300 10170 2835 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001 +-6 +6 6570 3015 7290 3465 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 +-6 +6 3825 3060 4635 3510 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 3330 predictor\001 +-6 +6 2970 3690 3690 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3960 fetch\001 +-6 +6 1890 3690 2610 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 +-6 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 6930 3015 6930 2790 5130 2790 5130 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5130 2790 4230 2790 4230 3060 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 2790 6030 3690 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 3915 5850 3915 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6390 3690 6390 3240 6570 3240 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 3915 7650 3915 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 0 0 1 + 7650 3780 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 3915 8370 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 3915 12150 3915 12150 3240 8010 3240 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11430 4140 11430 4500 8820 4500 8820 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8640 4680 8640 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11790 4140 11790 4680 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 11970 5040 11970 4680 8370 4680 8370 5040 11970 5040 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 8190 3105 12330 3105 12330 5220 8190 5220 8190 3105 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11070 3510 11070 4320 10710 4320 10710 3510 11070 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11070 3915 11250 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9090 3915 9270 3915 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 9630 3510 9630 4320 9270 4320 9270 3510 9630 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 4185 9810 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 4185 10710 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 3645 10710 3645 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 3645 9810 3645 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 2925 10170 3420 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7650 3240 7290 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 3465 6930 3915 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 3510 4410 3870 4770 3870 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 3915 2610 3915 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 1710 5400 12510 5400 12510 2295 1710 2295 1710 5400 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 3510 4050 3870 3690 3870 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 2880 2790 2880 2790 4320 5580 4320 5580 2880 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 7470 4320 5760 4320 5760 2610 7470 2610 7470 4320 +2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 + 8010 2880 8010 4320 7650 4320 7650 2880 8010 2880 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 4410 9810 4410 9810 3960 10530 3960 10530 4410 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 3870 9810 3870 9810 3420 10530 3420 10530 3870 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 3960 4770 3960 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 4050 3060 4050 3060 3600 3780 3600 3780 4050 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 3510 3960 3780 3780 3780 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 4050 4770 4050 +4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 9495 3915 select\001 +4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 +4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 2790 Front End\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 2520 Out Of Order Engine\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 3600 select\001 +4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 4230 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 3690 memory\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex02.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex02.fig (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex02.fig (revision 57) @@ -0,0 +1,227 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 5850 3690 6570 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 6570 4140 5850 4140 5850 3690 6570 3690 6570 4140 +4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 3960 rename\001 +-6 +6 8370 3690 9090 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9090 4140 8370 4140 8370 3690 9090 3690 9090 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 330 8730 3960 read\001 +-6 +6 11250 3690 11970 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 11970 4140 11250 4140 11250 3690 11970 3690 11970 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 390 11610 3960 write\001 +-6 +6 9810 2475 10530 2925 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 2925 9810 2925 9810 2475 10530 2475 10530 2925 +4 1 0 50 -1 -1 12 0.0000 4 150 300 10170 2835 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001 +-6 +6 6570 3015 7290 3465 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 +-6 +6 4770 3285 5490 3735 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 3735 4770 3735 4770 3285 5490 3285 5490 3735 +4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3555 decod\001 +-6 +6 4770 2835 5490 3285 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 3285 4770 3285 4770 2835 5490 2835 5490 3285 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3015 context\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3195 state\001 +-6 +6 3825 2655 4635 3105 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 3105 3870 3105 3870 2655 4590 2655 4590 3105 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 2925 predictor\001 +-6 +6 2970 3285 3690 3735 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 3735 2970 3735 2970 3285 3690 3285 3690 3735 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3555 fetch\001 +-6 +6 1890 3690 2610 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 +-6 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5130 2340 4230 2340 4230 2655 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 2790 6030 3690 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6390 3690 6390 3240 6570 3240 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 3915 7650 3915 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 0 0 1 + 7650 3780 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 3915 8370 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 3915 12150 3915 12150 3240 8010 3240 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11430 4140 11430 4500 8820 4500 8820 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8640 4680 8640 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11790 4140 11790 4680 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 11970 5040 11970 4680 8370 4680 8370 5040 11970 5040 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 8190 3105 12330 3105 12330 5220 8190 5220 8190 3105 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11070 3510 11070 4320 10710 4320 10710 3510 11070 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11070 3915 11250 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9090 3915 9270 3915 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 9630 3510 9630 4320 9270 4320 9270 3510 9630 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 4185 9810 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 4185 10710 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 3645 10710 3645 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 3645 9810 3645 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 2925 10170 3420 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7650 3240 7290 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 3465 6930 3915 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 7470 4320 5760 4320 5760 2610 7470 2610 7470 4320 +2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 + 8010 2880 8010 4320 7650 4320 7650 2880 8010 2880 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 4410 9810 4410 9810 3960 10530 3960 10530 4410 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 3870 9810 3870 9810 3420 10530 3420 10530 3870 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 3105 4410 3465 4770 3465 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 3510 2610 3870 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 3105 4050 3465 3690 3465 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 2475 2790 2475 2790 3915 5580 3915 5580 2475 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 3555 4770 3555 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 3645 3060 3645 3060 3195 3780 3195 3780 3645 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 3105 3960 3375 3780 3375 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 3645 4770 3645 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 4725 4410 4365 4770 4365 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 4320 2610 4005 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 4725 4050 4365 3690 4365 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 5355 2790 5355 2790 3915 5580 3915 5580 5355 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 4275 4770 4275 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 4185 3060 4185 3060 4635 3780 4635 3780 4185 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 4725 3960 4455 3780 4455 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 4185 4770 4185 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 3510 5850 3780 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 4320 5843 4060 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4230 2655 4230 4725 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5130 2835 5130 4545 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 6930 3015 6930 2790 6030 2790 5130 2340 5130 2835 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 1710 5535 12510 5535 12510 2295 1710 2295 1710 5535 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 4545 4770 4545 4770 4995 5490 4995 5490 4545 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 4095 4770 4095 4770 4545 5490 4545 5490 4095 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 4725 3870 4725 3870 5175 4590 5175 4590 4725 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 4095 2970 4095 2970 4545 3690 4545 3690 4095 +4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 9495 3915 select\001 +4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 2520 Out Of Order Engine\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 3600 select\001 +4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 4230 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 3690 memory\001 +4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 2430 Front End\001 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 4365 fetch\001 +4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 4365 decod\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 4725 state\001 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 4860 context\001 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 4995 predictor\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex03.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex03.fig (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex03.fig (revision 57) @@ -0,0 +1,299 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 9810 2475 10530 2925 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 2925 9810 2925 9810 2475 10530 2475 10530 2925 +4 1 0 50 -1 -1 12 0.0000 4 150 300 10170 2835 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001 +-6 +6 8190 5220 12330 7335 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11430 6300 11430 5940 8820 5940 8820 6300 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8640 5760 8640 6300 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11790 6300 11790 5760 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 11970 5400 11970 5760 8370 5760 8370 5400 11970 5400 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 8190 7335 12330 7335 12330 5220 8190 5220 8190 7335 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11070 6930 11070 6120 10710 6120 10710 6930 11070 6930 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11070 6525 11250 6525 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9090 6525 9270 6525 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 9630 6930 9630 6120 9270 6120 9270 6930 9630 6930 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 6255 9810 6255 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 6255 10710 6255 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 6795 10710 6795 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 6795 9810 6795 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 6030 9810 6030 9810 6480 10530 6480 10530 6030 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 6570 9810 6570 9810 7020 10530 7020 10530 6570 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9090 6300 8370 6300 8370 6750 9090 6750 9090 6300 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 11970 6300 11250 6300 11250 6750 11970 6750 11970 6300 +4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 5625 register\001 +4 1 0 50 -1 -1 12 0.0000 4 135 330 8730 6570 read\001 +4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 6300 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 6840 memory\001 +4 1 0 50 -1 -1 12 0.0000 4 135 390 11610 6570 write\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 6525 select\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 9495 6525 select\001 +-6 +6 8190 3105 12330 5220 +6 8370 3690 9090 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9090 4140 8370 4140 8370 3690 9090 3690 9090 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 330 8730 3960 read\001 +-6 +6 11250 3690 11970 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 11970 4140 11250 4140 11250 3690 11970 3690 11970 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 390 11610 3960 write\001 +-6 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11430 4140 11430 4500 8820 4500 8820 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8640 4680 8640 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11790 4140 11790 4680 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 11970 5040 11970 4680 8370 4680 8370 5040 11970 5040 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 8190 3105 12330 3105 12330 5220 8190 5220 8190 3105 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11070 3510 11070 4320 10710 4320 10710 3510 11070 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11070 3915 11250 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9090 3915 9270 3915 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 9630 3510 9630 4320 9270 4320 9270 3510 9630 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 4185 9810 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 4185 10710 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 3645 10710 3645 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 3645 9810 3645 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 4410 9810 4410 9810 3960 10530 3960 10530 4410 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 3870 9810 3870 9810 3420 10530 3420 10530 3870 +4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 9495 3915 select\001 +4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 4230 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 3690 memory\001 +-6 +6 9810 7515 10530 7965 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 7965 9810 7965 9810 7515 10530 7515 10530 7965 +4 1 0 50 -1 -1 12 0.0000 4 150 300 10170 7875 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 7695 dcache\001 +-6 +6 1890 3600 7650 6660 +6 5850 4995 6570 5445 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 6570 5445 5850 5445 5850 4995 6570 4995 6570 5445 +4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 5265 rename\001 +-6 +6 6570 4320 7290 4770 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 4770 6570 4770 6570 4320 7290 4320 7290 4770 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 4590 commit\001 +-6 +6 4770 4590 5490 5040 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 5040 4770 5040 4770 4590 5490 4590 5490 5040 +4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 4860 decod\001 +-6 +6 4770 4140 5490 4590 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 4590 4770 4590 4770 4140 5490 4140 5490 4590 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 4320 context\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 4500 state\001 +-6 +6 3825 3960 4635 4410 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 4410 3870 4410 3870 3960 4590 3960 4590 4410 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 4230 predictor\001 +-6 +6 2970 4590 3690 5040 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 5040 2970 5040 2970 4590 3690 4590 3690 5040 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 4860 fetch\001 +-6 +6 1890 4995 2610 5445 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 5445 1890 5445 1890 4995 2610 4995 2610 5445 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 5355 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 5175 icache\001 +-6 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5130 3645 4230 3645 4230 3960 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 4095 6030 4995 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6390 4995 6390 4545 6570 4545 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 5220 7650 5220 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 0 0 1 + 7650 5085 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7650 4545 7290 4545 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 4770 6930 5220 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 7470 5625 5760 5625 5760 3915 7470 3915 7470 5625 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 4410 4410 4770 4770 4770 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 4815 2610 5175 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 4410 4050 4770 3690 4770 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 3780 2790 3780 2790 5220 5580 5220 5580 3780 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 4860 4770 4860 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 4950 3060 4950 3060 4500 3780 4500 3780 4950 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 4410 3960 4680 3780 4680 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 4950 4770 4950 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 6030 4410 5670 4770 5670 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 5625 2610 5310 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 6030 4050 5670 3690 5670 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 6660 2790 6660 2790 5220 5580 5220 5580 6660 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 5580 4770 5580 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 5490 3060 5490 3060 5940 3780 5940 3780 5490 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 6030 3960 5760 3780 5760 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 5490 4770 5490 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 4815 5850 5085 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 5625 5843 5365 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4230 3960 4230 6030 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5130 4140 5130 5850 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 6930 4320 6930 4095 6030 4095 5130 3645 5130 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 5850 4770 5850 4770 6300 5490 6300 5490 5850 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 5400 4770 5400 4770 5850 5490 5850 5490 5400 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 6030 3870 6030 3870 6480 4590 6480 4590 6030 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 5400 2970 5400 2970 5850 3690 5850 3690 5400 +4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 3825 Out Of Order Engine\001 +4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 3735 Front End\001 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 5670 fetch\001 +4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 5670 decod\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 6030 state\001 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 6165 context\001 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 6300 predictor\001 +-6 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 3915 8370 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 3915 12150 3915 12150 3240 8010 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 2925 10170 3420 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 7020 10170 7515 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 1710 8145 12510 8145 12510 2295 1710 2295 1710 8145 +2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 + 8010 2880 8010 7560 7650 7560 7650 2880 8010 2880 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 6525 8370 6525 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 6525 12150 6525 12150 7200 8010 7200 +4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 5220 select\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex04.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex04.fig (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex04.fig (revision 57) @@ -0,0 +1,327 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 9810 2475 10530 2925 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 2925 9810 2925 9810 2475 10530 2475 10530 2925 +4 1 0 50 -1 -1 12 0.0000 4 150 300 10170 2835 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001 +-6 +6 1890 3690 2610 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 +-6 +6 8190 5220 12330 7335 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11430 6300 11430 5940 8820 5940 8820 6300 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8640 5760 8640 6300 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11790 6300 11790 5760 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 11970 5400 11970 5760 8370 5760 8370 5400 11970 5400 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 8190 7335 12330 7335 12330 5220 8190 5220 8190 7335 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11070 6930 11070 6120 10710 6120 10710 6930 11070 6930 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11070 6525 11250 6525 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9090 6525 9270 6525 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 9630 6930 9630 6120 9270 6120 9270 6930 9630 6930 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 6255 9810 6255 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 6255 10710 6255 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 6795 10710 6795 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 6795 9810 6795 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 6030 9810 6030 9810 6480 10530 6480 10530 6030 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 6570 9810 6570 9810 7020 10530 7020 10530 6570 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9090 6300 8370 6300 8370 6750 9090 6750 9090 6300 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 11970 6300 11250 6300 11250 6750 11970 6750 11970 6300 +4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 5625 register\001 +4 1 0 50 -1 -1 12 0.0000 4 135 330 8730 6570 read\001 +4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 6300 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 6840 memory\001 +4 1 0 50 -1 -1 12 0.0000 4 135 390 11610 6570 write\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 6525 select\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 9495 6525 select\001 +-6 +6 8190 3105 12330 5220 +6 8370 3690 9090 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9090 4140 8370 4140 8370 3690 9090 3690 9090 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 330 8730 3960 read\001 +-6 +6 11250 3690 11970 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 11970 4140 11250 4140 11250 3690 11970 3690 11970 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 390 11610 3960 write\001 +-6 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11430 4140 11430 4500 8820 4500 8820 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8640 4680 8640 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11790 4140 11790 4680 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 11970 5040 11970 4680 8370 4680 8370 5040 11970 5040 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 8190 3105 12330 3105 12330 5220 8190 5220 8190 3105 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11070 3510 11070 4320 10710 4320 10710 3510 11070 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11070 3915 11250 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9090 3915 9270 3915 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 9630 3510 9630 4320 9270 4320 9270 3510 9630 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 4185 9810 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 4185 10710 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 3645 10710 3645 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 3645 9810 3645 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 4410 9810 4410 9810 3960 10530 3960 10530 4410 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 3870 9810 3870 9810 3420 10530 3420 10530 3870 +4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 9495 3915 select\001 +4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 4230 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 3690 memory\001 +-6 +6 9810 7515 10530 7965 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 7965 9810 7965 9810 7515 10530 7515 10530 7965 +4 1 0 50 -1 -1 12 0.0000 4 150 300 10170 7875 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 7695 dcache\001 +-6 +6 5760 2610 7470 4320 +6 5850 3690 6570 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 6570 4140 5850 4140 5850 3690 6570 3690 6570 4140 +4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 3960 rename\001 +-6 +6 6570 3015 7290 3465 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 +-6 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 2790 6030 3690 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6390 3690 6390 3240 6570 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 3465 6930 3915 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 7470 4320 5760 4320 5760 2610 7470 2610 7470 4320 +-6 +6 2790 2880 5580 4320 +6 4770 3690 5490 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3960 decod\001 +-6 +6 4770 3240 5490 3690 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001 +-6 +6 3825 3060 4635 3510 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 3330 predictor\001 +-6 +6 2970 3690 3690 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3960 fetch\001 +-6 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 3510 4410 3870 4770 3870 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 3510 4050 3870 3690 3870 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 3960 4770 3960 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 4050 3060 4050 3060 3600 3780 3600 3780 4050 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 3510 3960 3780 3780 3780 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 4050 4770 4050 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 2880 2790 2880 2790 4320 5580 4320 5580 2880 +-6 +6 1890 6300 2610 6750 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 6750 1890 6750 1890 6300 2610 6300 2610 6750 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 6660 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 6480 icache\001 +-6 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5130 2790 4230 2790 4230 3060 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 3915 7650 3915 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 0 0 1 + 7650 3780 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 3915 8370 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 3915 12150 3915 12150 3240 8010 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 2925 10170 3420 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7650 3240 7290 3240 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 3915 2610 3915 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 3915 5850 3915 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 6930 3015 6930 2790 6030 2790 5130 2790 5130 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 7020 10170 7515 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 1710 8145 12510 8145 12510 2295 1710 2295 1710 8145 +2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 + 8010 2880 8010 7560 7650 7560 7650 2880 8010 2880 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 6525 8370 6525 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 6525 12150 6525 12150 7200 8010 7200 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 6525 7650 6525 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 6525 5850 6525 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 6930 7425 6930 7650 6030 7650 5130 7650 5130 7200 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5130 7650 4230 7650 4230 7380 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 6930 4410 6570 4770 6570 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 6525 2610 6525 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 6930 4050 6570 3690 6570 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 7560 2790 7560 2790 6120 5580 6120 5580 7560 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 6480 4770 6480 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 6390 3060 6390 3060 6840 3780 6840 3780 6390 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 6930 3960 6660 3780 6660 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 6390 4770 6390 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 6750 4770 6750 4770 7200 5490 7200 5490 6750 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 6300 4770 6300 4770 6750 5490 6750 5490 6300 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 6930 3870 6930 3870 7380 4590 7380 4590 6930 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 6300 2970 6300 2970 6750 3690 6750 3690 6300 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 7650 6030 6750 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6390 6750 6390 7200 6570 7200 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 6975 6930 6525 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 7470 6120 5760 6120 5760 7830 7470 7830 7470 6120 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 6975 6570 6975 6570 7425 7290 7425 7290 6975 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 6570 6300 5850 6300 5850 6750 6570 6750 6570 6300 +4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 2520 Out Of Order Engine\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 5220 select\001 +4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 2790 Front End\001 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 6570 fetch\001 +4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 6570 decod\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 6930 state\001 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 7065 context\001 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 7200 predictor\001 +4 1 0 50 -1 -1 12 6.2832 4 135 555 6930 7245 commit\001 +4 1 0 50 -1 -1 12 6.2832 4 90 555 6210 6525 rename\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-front_end.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-front_end.fig (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-front_end.fig (revision 57) @@ -1,3 +1,3 @@ -#FIG 3.2 Produced by xfig version 3.2.5-alpha5 +#FIG 3.2 Landscape Center @@ -36,5 +36,5 @@ 3330 6930 2610 6930 2610 6480 3330 6480 3330 6930 4 1 0 50 -1 -1 10 0.0000 4 105 315 2970 6660 fetch\001 -4 1 0 50 -1 -1 10 0.0000 4 120 345 2970 6840 queue\001 +4 1 0 50 -1 -1 10 0.0000 4 105 345 2970 6840 queue\001 -6 6 2610 5670 3330 6120 @@ -43,10 +43,4 @@ 4 1 0 50 -1 -1 10 0.0000 4 105 450 2970 5850 address\001 4 1 0 50 -1 -1 10 0.0000 4 120 585 2970 6030 generator\001 --6 -6 1710 6075 2430 6525 -2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 - 2430 6525 1710 6525 1710 6075 2430 6075 2430 6525 -4 1 0 50 -1 -1 10 0.0000 4 105 240 2070 6255 inst\001 -4 1 0 50 -1 -1 10 0.0000 4 105 360 2070 6435 ROM\001 -6 1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 5040 5221 24 24 5040 5221 5064 5217 @@ -102,5 +96,5 @@ 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 2610 5895 1350 5895 + 2610 5895 2250 5895 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 1 2250 5895 @@ -109,13 +103,5 @@ 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 2070 5895 2070 6075 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 1350 6705 2610 6705 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 2070 6525 2070 6705 -2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 - 3510 5490 1530 5490 1530 7110 3510 7110 3510 5490 + 2250 6705 2610 6705 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 @@ -127,18 +113,20 @@ 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 5310 6930 4590 6930 4590 6480 5310 6480 5310 6930 -4 2 0 50 -1 -1 10 0.0000 4 150 435 2880 4320 predict\001 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 3510 5490 2430 5490 2430 7110 3510 7110 3510 5490 +4 2 0 50 -1 -1 10 0.0000 4 135 435 2880 4320 predict\001 4 1 0 50 -1 -1 10 0.0000 4 105 315 4005 6660 fetch\001 4 0 0 50 -1 -1 10 0.0000 4 150 825 5085 6435 decod_branch\001 4 1 0 50 -1 -1 10 0.0000 4 105 360 3600 5805 Event\001 4 1 0 50 -1 -1 10 0.0000 4 105 345 4950 4995 Table\001 -4 1 0 50 -1 -1 10 0.0000 4 150 450 4950 4815 Update\001 +4 1 0 50 -1 -1 10 0.0000 4 135 450 4950 4815 Update\001 4 1 0 50 -1 -1 10 0.0000 4 105 420 4950 4635 Branch\001 4 2 0 50 -1 -1 10 0.0000 4 150 690 4815 6435 decod_sync\001 -4 2 0 50 -1 -1 10 0.0000 4 150 405 6705 5715 update\001 +4 2 0 50 -1 -1 10 0.0000 4 135 405 6705 5715 update\001 4 0 0 50 -1 -1 10 0.0000 4 105 315 3060 6345 alloc\001 -4 0 0 50 -1 -1 10 0.0000 4 150 645 1395 5805 Icache_req\001 -4 0 0 50 -1 -1 10 0.0000 4 150 645 1395 6885 Icache_rsp\001 4 2 0 50 -1 -1 10 0.0000 4 105 345 6750 7065 decod\001 4 1 0 50 -1 -1 10 0.0000 4 105 345 4950 6750 decod\001 4 1 0 50 -1 -1 10 0.0000 4 105 345 6030 6660 decod\001 -4 1 0 50 -1 -1 10 0.0000 4 120 345 6030 6840 queue\001 +4 1 0 50 -1 -1 10 0.0000 4 105 345 6030 6840 queue\001 +4 2 0 50 -1 -1 10 0.0000 4 150 645 2340 5805 Icache_req\001 +4 2 0 50 -1 -1 10 0.0000 4 150 645 2340 6885 Icache_rsp\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview.fig (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview.fig (revision 57) @@ -1,3 +1,3 @@ -#FIG 3.2 Produced by xfig version 3.2.5-alpha5 +#FIG 3.2 Landscape Center @@ -11,63 +11,53 @@ 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140 -4 1 0 50 -1 -1 12 0.0000 4 135 495 5130 3960 decod\001 +4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3960 decod\001 -6 6 4770 3240 5490 3690 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 -4 1 0 50 -1 -1 12 0.0000 4 120 615 5130 3420 context\001 -4 1 0 50 -1 -1 12 0.0000 4 120 375 5130 3600 state\001 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001 -6 6 5850 3690 6570 4140 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 6570 4140 5850 4140 5850 3690 6570 3690 6570 4140 -4 1 0 50 -1 -1 12 0.0000 4 90 585 6210 3960 rename\001 +4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 3960 rename\001 -6 6 8370 3690 9090 4140 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 9090 4140 8370 4140 8370 3690 9090 3690 9090 4140 -4 1 0 50 -1 -1 12 0.0000 4 135 345 8730 3960 read\001 +4 1 0 50 -1 -1 12 0.0000 4 135 330 8730 3960 read\001 -6 6 11250 3690 11970 4140 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 11970 4140 11250 4140 11250 3690 11970 3690 11970 4140 -4 1 0 50 -1 -1 12 0.0000 4 135 405 11610 3960 write\001 --6 -6 9810 3420 10530 3870 -2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 - 10530 3870 9810 3870 9810 3420 10530 3420 10530 3870 -4 1 0 50 -1 -1 12 0.0000 4 135 660 10170 3690 memory\001 --6 -6 9810 3960 10530 4410 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 10530 4410 9810 4410 9810 3960 10530 3960 10530 4410 -4 1 0 50 -1 -1 12 0.0000 4 120 630 10170 4230 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 135 390 11610 3960 write\001 -6 6 9810 2475 10530 2925 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 10530 2925 9810 2925 9810 2475 10530 2475 10530 2925 -4 1 0 50 -1 -1 12 0.0000 4 165 330 10170 2835 port\001 -4 1 0 50 -1 -1 12 0.0000 4 135 570 10170 2655 dcache\001 +4 1 0 50 -1 -1 12 0.0000 4 150 300 10170 2835 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001 -6 6 6570 3015 7290 3465 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 -4 1 0 50 -1 -1 12 0.0000 4 135 615 6930 3285 commit\001 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 -6 6 3825 3060 4635 3510 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510 -4 1 0 50 -1 -1 12 0.0000 4 180 735 4230 3330 predictor\001 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 3330 predictor\001 -6 6 2970 3690 3690 4140 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140 -4 1 0 50 -1 -1 12 0.0000 4 135 405 3330 3960 fetch\001 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3960 fetch\001 -6 6 1890 3690 2610 4140 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140 -4 1 0 50 -1 -1 12 0.0000 4 165 330 2250 4050 port\001 -4 1 0 50 -1 -1 12 0.0000 4 135 525 2250 3870 icache\001 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 -6 6 1800 4590 5265 5355 @@ -78,7 +68,7 @@ 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 2160 5310 1800 5310 1800 5130 2160 5130 2160 5310 -4 0 0 50 -1 -1 12 0.0000 4 180 600 2340 4770 Groupe\001 -4 0 0 50 -1 -1 12 0.0000 4 180 2430 2340 5310 Une occurence dans le groupe\001 -4 0 0 50 -1 -1 12 0.0000 4 180 2910 2340 5040 Plusieurs occurences dans le groupe\001 +4 0 0 50 -1 -1 12 0.0000 4 180 555 2340 4770 Groupe\001 +4 0 0 50 -1 -1 12 0.0000 4 180 2280 2340 5310 Une occurence dans le groupe\001 +4 0 0 50 -1 -1 12 0.0000 4 180 2760 2340 5040 Plusieurs occurences dans le groupe\001 -6 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4 @@ -176,10 +166,16 @@ 2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 8010 2880 8010 4320 7650 4320 7650 2880 8010 2880 -4 1 0 50 -1 -1 12 0.0000 4 180 600 10170 4905 register\001 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 4410 9810 4410 9810 3960 10530 3960 10530 4410 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 3870 9810 3870 9810 3420 10530 3420 10530 3870 +4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001 4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001 4 1 0 50 -1 -1 12 1.5708 4 135 465 9495 3915 select\001 -4 0 1 50 -1 -1 12 0.0000 4 135 390 1710 2205 Core\001 -4 0 1 50 -1 -1 12 0.0000 4 135 810 2790 2790 Front End\001 -4 0 1 50 -1 -1 12 0.0000 4 180 1320 8190 3015 Execution Loop\001 -4 0 1 50 -1 -1 12 0.0000 4 180 1665 5760 2520 Out Of Order Engine\001 +4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 +4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 2790 Front End\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 2520 Out Of Order Engine\001 4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 3600 select\001 +4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 4230 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 3690 memory\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_service.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_service.fig (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_service.fig (revision 57) @@ -8,6 +8,10 @@ -2 1200 2 -5 1 0 1 0 29 50 -1 20 0.000 0 1 0 0 4575.000 2100.000 4350 2400 4575 2475 4800 2400 -5 1 0 1 0 2 48 -1 40 0.000 0 0 0 0 5025.000 2700.000 4800 2400 5025 2325 5250 2400 +5 1 0 1 0 29 50 -1 20 0.000 0 1 0 0 5850.000 2100.000 5625 2400 5850 2475 6075 2400 +5 1 0 1 0 2 48 -1 40 0.000 0 0 0 0 6300.000 2700.000 6075 2400 6300 2325 6525 2400 +5 1 0 1 0 2 49 -1 40 0.000 0 0 0 0 6825.000 4800.000 6600 4500 6825 4425 7050 4500 +5 1 0 1 0 2 49 -1 40 0.000 0 0 0 0 6225.000 5850.000 6000 5550 6225 5475 6450 5550 +5 1 0 1 0 29 50 -1 20 0.000 0 1 0 0 6375.000 4200.000 6150 4500 6375 4575 6600 4500 +5 1 0 1 0 29 50 -1 20 0.000 0 1 0 0 5775.000 5250.000 5550 5550 5775 5625 6000 5550 6 3675 4050 4725 4650 5 1 0 1 0 2 50 -1 20 0.000 0 1 0 0 3975.000 4200.000 3750 4500 3975 4575 4200 4500 @@ -22,23 +26,21 @@ 4350 5550 4350 5100 5250 5100 5250 5550 -6 -6 5475 5100 6525 5700 -5 1 0 1 0 2 49 -1 40 0.000 0 0 0 0 6225.000 5850.000 6000 5550 6225 5475 6450 5550 -5 1 0 1 0 31 50 -1 20 0.000 0 1 0 0 5775.000 5250.000 5550 5550 5775 5625 6000 5550 -2 1 0 1 0 31 50 -1 20 0.000 0 0 7 0 0 4 - 5550 5550 5550 5100 6450 5100 6450 5550 +6 4950 3000 5850 3450 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 5850 3450 5850 3000 4950 3000 4950 3450 5850 3450 +4 1 0 50 -1 -1 10 0.0000 4 105 615 5400 3225 Generator\001 -6 -6 6075 4050 7125 4650 -5 1 0 1 0 2 49 -1 40 0.000 0 0 0 0 6825.000 4800.000 6600 4500 6825 4425 7050 4500 -5 1 0 1 0 31 50 -1 20 0.000 0 1 0 0 6375.000 4200.000 6150 4500 6375 4575 6600 4500 -2 1 0 1 0 31 50 -1 20 0.000 0 0 7 0 0 4 - 6150 4500 6150 4050 7050 4050 7050 4500 +6 6600 1950 7650 2550 +5 1 0 1 0 29 50 -1 20 0.000 0 1 0 0 6900.000 2100.000 6675 2400 6900 2475 7125 2400 +5 1 0 1 0 2 48 -1 40 0.000 0 0 0 0 7350.000 2700.000 7125 2400 7350 2325 7575 2400 +2 1 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 4 + 6675 2400 6675 1950 7575 1950 7575 2400 +4 1 0 50 -1 -1 10 0.0000 4 135 240 7125 2325 .cfg\001 +4 1 0 50 -1 -1 10 0.0000 4 135 885 7125 2100 Configuration\001 -6 -6 5550 1950 6450 2550 -5 1 0 1 0 29 50 -1 20 0.000 0 1 0 0 5775.000 2100.000 5550 2400 5775 2475 6000 2400 -5 1 0 1 0 2 48 -1 40 0.000 0 0 0 0 6225.000 2700.000 6000 2400 6225 2325 6450 2400 -2 1 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 4 - 5550 2400 5550 1950 6450 1950 6450 2400 -4 1 0 50 -1 -1 10 0.0000 4 135 240 6000 2325 .cfg\001 -4 1 0 50 -1 -1 10 0.0000 4 135 885 6000 2100 Configuration\001 +6 7350 3000 8250 3450 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 8250 3450 8250 3000 7350 3000 7350 3450 8250 3450 +4 1 0 50 -1 -1 10 0.0000 4 105 465 7800 3225 Viewer\001 -6 2 1 0 1 0 26 50 -1 -1 0.000 0 0 -1 1 0 2 @@ -57,31 +59,32 @@ 3 0 1.00 60.00 120.00 5400 4500 4800 5100 -2 1 0 1 0 26 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 4800 2400 5100 3000 -2 1 0 1 0 26 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 6000 2400 5700 3000 -2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 - 7950 3450 7950 3000 7050 3000 7050 3450 7950 3450 -2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 - 5850 3450 5850 3000 4950 3000 4950 3450 5850 3450 2 1 0 1 0 26 50 -1 -1 0.000 0 0 -1 0 1 2 3 0 1.00 60.00 120.00 7500 3450 6600 4050 -2 1 0 1 0 29 50 -1 -1 0.000 0 0 -1 1 0 4 - 3 0 1.00 60.00 120.00 - 4800 1950 4800 1350 7650 1350 7650 3000 -2 1 0 1 0 29 50 -1 -1 0.000 0 0 7 0 1 4 - 3 0 1.00 60.00 120.00 - 7200 3000 7200 1650 6075 1650 6075 1950 -2 1 0 1 0 29 50 -1 -1 0.000 0 0 7 1 0 4 - 3 0 1.00 60.00 120.00 - 7350 3000 7350 1500 5925 1500 5925 1950 2 4 0 1 0 4 50 -1 20 0.000 0 0 7 0 0 5 5850 4050 4950 4050 4950 4500 5850 4500 5850 4050 +2 1 0 1 0 11 50 -1 -1 3.000 0 0 -1 1 1 4 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 5550 3000 5550 2850 7650 2850 7650 3000 +2 1 0 1 0 11 50 -1 -1 3.000 0 0 -1 1 1 4 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 5250 3000 5250 2775 7950 2775 7950 3000 +2 1 0 1 0 11 50 -1 -1 3.000 0 0 -1 0 0 2 + 6075 2400 6075 2850 +2 1 0 1 0 11 50 -1 -1 3.000 0 0 -1 0 0 2 + 7125 2400 7125 2775 +2 1 0 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 8100 3000 8100 1650 7125 1650 7125 1950 +2 4 2 1 0 6 51 -1 20 3.000 0 0 7 0 0 5 + 8550 2700 4650 2700 4650 3750 8550 3750 8550 2700 2 1 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 4 - 4350 2400 4350 1950 5250 1950 5250 2400 -4 1 0 50 -1 -1 10 0.0000 4 135 570 5400 3225 Morpheo\001 + 5625 2400 5625 1950 6525 1950 6525 2400 +2 1 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 4 + 5550 5550 5550 5100 6450 5100 6450 5550 +2 1 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 4 + 6150 4500 6150 4050 7050 4050 7050 4500 4 1 0 50 -1 -1 10 0.0000 4 105 435 4200 4275 VHDL\001 4 1 0 50 -1 -1 10 0.0000 4 105 435 4800 5475 VHDL\001 @@ -90,6 +93,6 @@ 4 1 0 50 -1 -1 10 0.0000 4 105 585 6600 4200 Positions\001 4 1 0 50 -1 -1 10 0.0000 4 105 255 6600 4425 .pos\001 -4 1 0 50 -1 -1 10 0.0000 4 105 465 7500 3225 Viewer\001 4 1 0 50 -1 -1 10 0.0000 4 135 555 5400 4275 SystemC\001 -4 1 0 50 -1 -1 10 0.0000 4 105 255 4800 2325 .gen\001 -4 1 0 50 -1 -1 10 0.0000 4 105 615 4800 2100 Generator\001 +4 1 0 50 -1 2 12 0.0000 0 180 735 6600 3300 Morpheo\001 +4 1 0 50 -1 -1 10 0.0000 4 105 255 6075 2325 .gen\001 +4 1 0 50 -1 -1 10 0.0000 4 105 420 6075 2100 Limits\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/VHDL_methodologie.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/VHDL_methodologie.fig (revision 57) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/VHDL_methodologie.fig (revision 57) @@ -0,0 +1,72 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +6 -1425 -600 2850 4050 +1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 -750 750 600 225 -750 750 -150 525 +1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 2175 600 225 1500 2175 2100 1950 +1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 3075 600 225 1500 3075 2100 2850 +2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1650 600 2250 1050 +2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1350 600 1050 1050 +2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 750 1500 1350 1950 +2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2250 1500 1650 1950 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 900 2175 0 2175 0 900 450 900 450 1050 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1500 2400 1500 2850 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1500 3300 1500 3750 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + -150 750 750 750 750 1050 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + -750 525 -750 -75 1200 -75 1200 150 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 900 3075 -750 3075 -750 975 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1500 -300 1500 150 +2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5 + 2100 -300 900 -300 900 -600 2100 -600 2100 -300 +2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5 + 2100 4050 900 4050 900 3750 2100 3750 2100 4050 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 2100 600 900 600 900 150 2100 150 2100 600 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 1350 1500 150 1500 150 1050 1350 1050 1350 1500 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 2850 1500 1650 1500 1650 1050 2850 1050 2850 1500 +4 1 0 50 -1 2 8 0.0000 0 75 240 1500 2175 Test\001 +4 1 0 50 -1 2 8 0.0000 0 90 990 2250 1275 TestBench VHDL\001 +4 1 0 50 -1 2 8 0.0000 0 105 1005 750 1275 G\351n\351rateur VHDL\001 +4 1 0 50 -1 2 8 0.0000 0 105 465 1500 375 SystemC\001 +4 1 0 50 -1 2 8 0.0000 0 90 1050 -750 675 Modification locale\001 +4 1 0 50 -1 2 8 0.0000 0 105 1035 -750 825 (micro architecture)\001 +4 1 0 50 -1 2 8 0.0000 0 105 315 1500 -450 D\351but\001 +4 1 0 50 -1 2 8 0.0000 0 135 810 1500 3075 Synth\350tisable ?\001 +4 1 0 50 -1 2 8 0.0000 0 90 195 1500 3900 Fin\001 +-6 +4 0 0 51 -1 0 8 0.0000 0 75 120 1575 3450 ok\001 +4 0 0 51 -1 0 8 0.0000 0 75 315 -75 675 locale\001 +4 0 0 51 -1 0 8 0.0000 0 90 375 -675 450 globale\001 +4 2 0 51 -1 0 8 0.0000 0 75 120 900 3000 ko\001 +4 2 0 51 -1 0 8 0.0000 0 75 120 900 2100 ko\001 +4 0 0 51 -1 0 8 0.0000 0 75 120 1575 2550 ok\001 Index: trunk/IPs/systemC/processor/Morpheo/Script/range.sh =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Script/range.sh (revision 56) +++ trunk/IPs/systemC/processor/Morpheo/Script/range.sh (revision 57) @@ -19,8 +19,12 @@ declare step=$3; - while test $a -le $b; do + while test $a -lt $b; do echo $a; a=$(($a $step)); - done + done + + if test $a -eq $b; then + echo $a; + fi; } @@ -33,8 +37,12 @@ declare iter=$4; - while test $a -le $b -a $iter -gt 1; do + while test $a -lt $b -a $iter -gt 1; do a=$(($a $step)); iter=$(($iter-1)); done; + + if test $a -eq $b; then + echo $a; + fi; if test $iter -eq 1; then Index: trunk/Makefile.tools =================================================================== --- trunk/Makefile.tools (revision 56) +++ trunk/Makefile.tools (revision 57) @@ -42,5 +42,6 @@ VIEWPS = gv VIEWPDF = xpdf -VIEWPDF_FS = acroread +VIEWPDF_FS = xpdf -fullscreen +#VIEWPDF_FS = acroread #---------------------------------------------------------- @@ -70,5 +71,5 @@ SYSTEMC_LIBDIR_systemcass_deps = $(SYSTEMC_LIBDIR_systemcass) -SYSTEMC_LIBNAME_systemcass = -lsystemc +SYSTEMC_LIBNAME_systemcass = -lsystemc_g++ SYSTEMC_LIBNAME_systemcass_deps = $(SYSTEMC_LIBNAME_systemcass)