Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/Makefile.mkf
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/Makefile.mkf	(revision 58)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/Makefile.mkf	(revision 58)
@@ -0,0 +1,110 @@
+#
+# Makefile generated by MKF configure script
+#
+
+all: RegisterFile_Monolithic_0.ngc RegisterFile_Monolithic_1.ngc RegisterFile_Monolithic_2.ngc RegisterFile_Monolithic_3.ngc RegisterFile_Monolithic_4.ngc RegisterFile_Monolithic_5.ngc RegisterFile_Monolithic_6.ngc
+
+RegisterFile_Monolithic_0.ngc: RegisterFile_Monolithic_0.prj
+	echo run -keep_hierarchy yes -iobuf no -top RegisterFile_Monolithic_0 -ifn RegisterFile_Monolithic_0.prj -ofn RegisterFile_Monolithic_0.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+RegisterFile_Monolithic_0.prj: RegisterFile_Monolithic_0_Pack.vhdl RegisterFile_Monolithic_0.vhdl
+	for i in RegisterFile_Monolithic_0_Pack.vhdl RegisterFile_Monolithic_0.vhdl ; do echo "vhdl work $$i" ; done > RegisterFile_Monolithic_0.prj
+
+RegisterFile_Monolithic_0_Pack.vhdl:
+
+RegisterFile_Monolithic_0.vhdl:
+
+RegisterFile_Monolithic_1.ngc: RegisterFile_Monolithic_1.prj
+	echo run -keep_hierarchy yes -iobuf no -top RegisterFile_Monolithic_1 -ifn RegisterFile_Monolithic_1.prj -ofn RegisterFile_Monolithic_1.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+RegisterFile_Monolithic_1.prj: RegisterFile_Monolithic_1_Pack.vhdl RegisterFile_Monolithic_1.vhdl
+	for i in RegisterFile_Monolithic_1_Pack.vhdl RegisterFile_Monolithic_1.vhdl ; do echo "vhdl work $$i" ; done > RegisterFile_Monolithic_1.prj
+
+RegisterFile_Monolithic_1_Pack.vhdl:
+
+RegisterFile_Monolithic_1.vhdl:
+
+RegisterFile_Monolithic_2.ngc: RegisterFile_Monolithic_2.prj
+	echo run -keep_hierarchy yes -iobuf no -top RegisterFile_Monolithic_2 -ifn RegisterFile_Monolithic_2.prj -ofn RegisterFile_Monolithic_2.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+RegisterFile_Monolithic_2.prj: RegisterFile_Monolithic_2_Pack.vhdl RegisterFile_Monolithic_2.vhdl
+	for i in RegisterFile_Monolithic_2_Pack.vhdl RegisterFile_Monolithic_2.vhdl ; do echo "vhdl work $$i" ; done > RegisterFile_Monolithic_2.prj
+
+RegisterFile_Monolithic_2_Pack.vhdl:
+
+RegisterFile_Monolithic_2.vhdl:
+
+RegisterFile_Monolithic_3.ngc: RegisterFile_Monolithic_3.prj
+	echo run -keep_hierarchy yes -iobuf no -top RegisterFile_Monolithic_3 -ifn RegisterFile_Monolithic_3.prj -ofn RegisterFile_Monolithic_3.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+RegisterFile_Monolithic_3.prj: RegisterFile_Monolithic_3_Pack.vhdl RegisterFile_Monolithic_3.vhdl
+	for i in RegisterFile_Monolithic_3_Pack.vhdl RegisterFile_Monolithic_3.vhdl ; do echo "vhdl work $$i" ; done > RegisterFile_Monolithic_3.prj
+
+RegisterFile_Monolithic_3_Pack.vhdl:
+
+RegisterFile_Monolithic_3.vhdl:
+
+RegisterFile_Monolithic_4.ngc: RegisterFile_Monolithic_4.prj
+	echo run -keep_hierarchy yes -iobuf no -top RegisterFile_Monolithic_4 -ifn RegisterFile_Monolithic_4.prj -ofn RegisterFile_Monolithic_4.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+RegisterFile_Monolithic_4.prj: RegisterFile_Monolithic_4_Pack.vhdl RegisterFile_Monolithic_4.vhdl
+	for i in RegisterFile_Monolithic_4_Pack.vhdl RegisterFile_Monolithic_4.vhdl ; do echo "vhdl work $$i" ; done > RegisterFile_Monolithic_4.prj
+
+RegisterFile_Monolithic_4_Pack.vhdl:
+
+RegisterFile_Monolithic_4.vhdl:
+
+RegisterFile_Monolithic_5.ngc: RegisterFile_Monolithic_5.prj
+	echo run -keep_hierarchy yes -iobuf no -top RegisterFile_Monolithic_5 -ifn RegisterFile_Monolithic_5.prj -ofn RegisterFile_Monolithic_5.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+RegisterFile_Monolithic_5.prj: RegisterFile_Monolithic_5_Pack.vhdl RegisterFile_Monolithic_5.vhdl
+	for i in RegisterFile_Monolithic_5_Pack.vhdl RegisterFile_Monolithic_5.vhdl ; do echo "vhdl work $$i" ; done > RegisterFile_Monolithic_5.prj
+
+RegisterFile_Monolithic_5_Pack.vhdl:
+
+RegisterFile_Monolithic_5.vhdl:
+
+RegisterFile_Monolithic_6.ngc: RegisterFile_Monolithic_6.prj
+	echo run -keep_hierarchy yes -iobuf no -top RegisterFile_Monolithic_6 -ifn RegisterFile_Monolithic_6.prj -ofn RegisterFile_Monolithic_6.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+RegisterFile_Monolithic_6.prj: RegisterFile_Monolithic_6_Pack.vhdl RegisterFile_Monolithic_6.vhdl
+	for i in RegisterFile_Monolithic_6_Pack.vhdl RegisterFile_Monolithic_6.vhdl ; do echo "vhdl work $$i" ; done > RegisterFile_Monolithic_6.prj
+
+RegisterFile_Monolithic_6_Pack.vhdl:
+
+RegisterFile_Monolithic_6.vhdl:
+
+clean:
+	rm -f RegisterFile_Monolithic_0.ngc
+	rm -f RegisterFile_Monolithic_0.lso
+	rm -f -r xst
+	rm -f RegisterFile_Monolithic_0.prj
+	rm -f RegisterFile_Monolithic_1.ngc
+	rm -f RegisterFile_Monolithic_1.lso
+	rm -f -r xst
+	rm -f RegisterFile_Monolithic_1.prj
+	rm -f RegisterFile_Monolithic_2.ngc
+	rm -f RegisterFile_Monolithic_2.lso
+	rm -f -r xst
+	rm -f RegisterFile_Monolithic_2.prj
+	rm -f RegisterFile_Monolithic_3.ngc
+	rm -f RegisterFile_Monolithic_3.lso
+	rm -f -r xst
+	rm -f RegisterFile_Monolithic_3.prj
+	rm -f RegisterFile_Monolithic_4.ngc
+	rm -f RegisterFile_Monolithic_4.lso
+	rm -f -r xst
+	rm -f RegisterFile_Monolithic_4.prj
+	rm -f RegisterFile_Monolithic_5.ngc
+	rm -f RegisterFile_Monolithic_5.lso
+	rm -f -r xst
+	rm -f RegisterFile_Monolithic_5.prj
+	rm -f RegisterFile_Monolithic_6.ngc
+	rm -f RegisterFile_Monolithic_6.lso
+	rm -f -r xst
+	rm -f RegisterFile_Monolithic_6.prj
+
+re: clean all
+
+install:
+
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp	(revision 57)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp	(revision 58)
@@ -95,6 +95,9 @@
   {
 #ifdef STATISTICS
-    _stat->generate_file(statistics(0));
-    delete _stat;
+    if (_usage & USE_STATISTICS)
+      {
+	_stat->generate_file(statistics(0));
+	delete _stat;
+      }
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info	(revision 58)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info	(revision 58)
@@ -0,0 +1,31 @@
+
+# RegisterFile_Multi_Banked_0
+target_dep	all	RegisterFile_Multi_Banked_0.ngc
+target_dep	RegisterFile_Multi_Banked_0.ngc	RegisterFile_Multi_Banked_0.prj
+target_dep	RegisterFile_Multi_Banked_0.prj	RegisterFile_Multi_Banked_0_bank_Pack.vhdl RegisterFile_Multi_Banked_0_bank.vhdl RegisterFile_Multi_Banked_0_Pack.vhdl RegisterFile_Multi_Banked_0_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_4_ports.vhdl RegisterFile_Multi_Banked_0.vhdl
+
+# RegisterFile_Multi_Banked_1
+target_dep	all	RegisterFile_Multi_Banked_1.ngc
+target_dep	RegisterFile_Multi_Banked_1.ngc	RegisterFile_Multi_Banked_1.prj
+target_dep	RegisterFile_Multi_Banked_1.prj	RegisterFile_Multi_Banked_1_bank_Pack.vhdl RegisterFile_Multi_Banked_1_bank.vhdl RegisterFile_Multi_Banked_1_Pack.vhdl RegisterFile_Multi_Banked_1_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_4_ports.vhdl RegisterFile_Multi_Banked_1.vhdl
+
+# RegisterFile_Multi_Banked_2
+target_dep	all	RegisterFile_Multi_Banked_2.ngc
+target_dep	RegisterFile_Multi_Banked_2.ngc	RegisterFile_Multi_Banked_2.prj
+target_dep	RegisterFile_Multi_Banked_2.prj	RegisterFile_Multi_Banked_2_bank_Pack.vhdl RegisterFile_Multi_Banked_2_bank.vhdl RegisterFile_Multi_Banked_2_Pack.vhdl RegisterFile_Multi_Banked_2_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_2_select_4_ports.vhdl RegisterFile_Multi_Banked_2.vhdl
+
+# RegisterFile_Multi_Banked_3
+target_dep	all	RegisterFile_Multi_Banked_3.ngc
+target_dep	RegisterFile_Multi_Banked_3.ngc	RegisterFile_Multi_Banked_3.prj
+target_dep	RegisterFile_Multi_Banked_3.prj	RegisterFile_Multi_Banked_3_bank_Pack.vhdl RegisterFile_Multi_Banked_3_bank.vhdl RegisterFile_Multi_Banked_3_Pack.vhdl RegisterFile_Multi_Banked_3_select_8_ports_Pack.vhdl RegisterFile_Multi_Banked_3_select_8_ports.vhdl RegisterFile_Multi_Banked_3.vhdl
+
+# RegisterFile_Multi_Banked_4
+target_dep	all	RegisterFile_Multi_Banked_4.ngc
+target_dep	RegisterFile_Multi_Banked_4.ngc	RegisterFile_Multi_Banked_4.prj
+target_dep	RegisterFile_Multi_Banked_4.prj	RegisterFile_Multi_Banked_4_bank_Pack.vhdl RegisterFile_Multi_Banked_4_bank.vhdl RegisterFile_Multi_Banked_4_Pack.vhdl RegisterFile_Multi_Banked_4_select_8_ports_Pack.vhdl RegisterFile_Multi_Banked_4_select_8_ports.vhdl RegisterFile_Multi_Banked_4.vhdl
+
+# RegisterFile_Multi_Banked_5
+target_dep	all	RegisterFile_Multi_Banked_5.ngc
+target_dep	RegisterFile_Multi_Banked_5.ngc	RegisterFile_Multi_Banked_5.prj
+target_dep	RegisterFile_Multi_Banked_5.prj	RegisterFile_Multi_Banked_5_bank_Pack.vhdl RegisterFile_Multi_Banked_5_bank.vhdl RegisterFile_Multi_Banked_5_Pack.vhdl RegisterFile_Multi_Banked_5_select_8_ports_Pack.vhdl RegisterFile_Multi_Banked_5_select_8_ports.vhdl RegisterFile_Multi_Banked_5.vhdl
+
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp	(revision 57)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp	(revision 58)
@@ -98,5 +98,4 @@
    * Simulation - Begin
    ********************************************************/
-  const bool     simulate_read = false;
   const uint32_t nb_request    = _param->_nb_word;
   // random init
@@ -177,52 +176,51 @@
       
 
-      if (simulate_read == true)
-	{
-	  cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl;
-	  
-	  nb_val = 0;
-	  nb_ack = 0;
-	  Tdata_t read_address [_param->_nb_port_read];
-
-	  while (nb_ack < nb_request)
-	    {
-	      cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
+      {
+	cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl;
+	
+	nb_val = 0;
+	nb_ack = 0;
+	Tdata_t read_address [_param->_nb_port_read];
+	
+	while (nb_ack < nb_request)
+	  {
+	    cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
+	    
+	    for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
+	      {
+		if ((nb_val < nb_request) and
+		    (READ_VAL [num_port].read() == 0))
+		  {
+		    read_address [num_port] = tab_address[nb_val];
+		    READ_VAL     [num_port].write(1);
+		    READ_ADDRESS [num_port].write(read_address [num_port]);
+		    
+		    nb_val ++;
+		    
+		    if (nb_val >= nb_request)
+		      break;
+		  }
+	      }
 	      
-	      for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
-		{
-		  if ((nb_val < nb_request) and
-		      (READ_VAL [num_port].read() == 0))
-		    {
-		      read_address [num_port] = tab_address[nb_val];
-		      READ_VAL     [num_port].write(1);
-		      READ_ADDRESS [num_port].write(read_address [num_port]);
-		      
-		      nb_val ++;
-		      
-		      if (nb_val >= nb_request)
-			break;
-		    }
-		}
-	      
-	      SC_START(1);
-	      
-	      // reset write_val port
-	      for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
-		{
-		  if ((READ_ACK [num_port].read() == 1) and
-		      (READ_VAL [num_port].read() == 1))
-		    {
-		      READ_VAL  [num_port] .write(0);
-		      
-		      cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl;
-		      
-		      TEST(Tdata_t,READ_DATA [num_port].read(), tab_data[read_address [num_port]]);
-		      nb_ack ++;
-		    }
-		}
-	      
-	      SC_START(0);
-	    }
-	}
+	    SC_START(1);
+	    
+	    // reset write_val port
+	    for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
+	      {
+		if ((READ_ACK [num_port].read() == 1) and
+		    (READ_VAL [num_port].read() == 1))
+		  {
+		    READ_VAL  [num_port] .write(0);
+		    
+		    cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl;
+		    
+		    TEST(Tdata_t,READ_DATA [num_port].read(), tab_data[read_address [num_port]]);
+		    nb_ack ++;
+		  }
+	      }
+	    
+	    SC_START(0);
+	  }
+      }
     }
   
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_body.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_body.cpp	(revision 57)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_body.cpp	(revision 58)
@@ -82,9 +82,10 @@
 	    for (uint32_t k=0; k<nb_port; k++)
 	      {
-		uint32_t num_port  = _param->_nb_port_read_by_bank*k+j;
+		uint32_t num_port  = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_read_by_bank*k+j);
 		string   separator = ((k==0)?" ":",");
-		
-		vhdl->set_body("\t"+separator+" in_VAL_"+toString(k)+"     \t=>\tinternal_READ_"+toString(i)+"_"+toString(num_port)+"_VAL");
-		vhdl->set_body("\t,out_ACK_"+toString(k)+"     \t=>\tinternal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+"_VAL");
+		string   index     = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):"";
+
+		vhdl->set_body("\t"+separator+" in_VAL_"+toString(k)+"     \t=>\tinternal_READ_"+toString(i)+"_"+toString(num_port)+index+"_VAL");
+		vhdl->set_body("\t,out_ACK_"+toString(k)+"     \t=>\tinternal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+index+"_VAL");
 	      }
 	    vhdl->set_body(");");
@@ -100,9 +101,10 @@
 	    for (uint32_t k=0; k<nb_port; k++)
 	      {
-		uint32_t num_port  = _param->_nb_port_write_by_bank*k+j;
+		uint32_t num_port  = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_write_by_bank*k+j);
 		string   separator = ((k==0)?" ":",");
+		string   index     = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):"";
 		
-		vhdl->set_body("\t"+separator+" in_VAL_"+toString(k)+"     \t=>\tinternal_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL");
-		vhdl->set_body("\t,out_ACK_"+toString(k)+"     \t=>\tinternal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL");
+		vhdl->set_body("\t"+separator+" in_VAL_"+toString(k)+"     \t=>\tinternal_WRITE_"+toString(i)+"_"+toString(num_port)+index+"_VAL");
+		vhdl->set_body("\t,out_ACK_"+toString(k)+"     \t=>\tinternal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+index+"_VAL");
 	      }
 	    vhdl->set_body(");");
@@ -122,10 +124,10 @@
 	    uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((j<read_select_limit)?read_nb_select1:read_nb_select2);
 
-	    vhdl->set_body("internal_BANK_READ_"+toString(i)+"_"+toString(j)+ "_VAL <= '0'");
+	    vhdl->set_body("internal_BANK_READ_"+toString(i)+"_"+toString(j)+ "_VAL  <= '0'");
 	    for (uint32_t k=0; k<nb_port; k++)
 	      {
-		uint32_t num_port  = _param->_nb_port_read_by_bank*k+j;
-
-		vhdl->set_body("\tor internal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+"_VAL");
+		uint32_t num_port  = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_read_by_bank*k+j);
+		string   index     = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):"";
+		vhdl->set_body("\tor internal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+index+"_VAL");
 	      }
 	    vhdl->set_body(";");
@@ -138,7 +140,8 @@
 	    for (uint32_t k=0; k<nb_port; k++)
 	      {
-		uint32_t num_port  = _param->_nb_port_write_by_bank*k+j;
-
-		vhdl->set_body("\tor internal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL");
+		uint32_t num_port  = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_write_by_bank*k+j);
+		string   index     = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):"";
+
+		vhdl->set_body("\tor internal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+index+"_VAL");
 	      }
 	    vhdl->set_body(";");
@@ -157,10 +160,11 @@
 	    uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((j<read_select_limit)?read_nb_select1:read_nb_select2);
 
-	    vhdl->set_body("internal_BANK_READ_"+toString(i)+"_"+toString(j)+ "_ADDRESS <=");
+	    vhdl->set_body("internal_BANK_READ_"+toString(i)+"_"+toString(j)+ "_ADDRESS  <=");
 	    for (uint32_t k=1; k<nb_port; k++)
 	      {
-		uint32_t num_port  = _param->_nb_port_read_by_bank*k+j;
-		
-		vhdl->set_body("\tin_READ_"+toString(num_port)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+" when internal_READ_"+toString(i)+"_"+toString(num_port)+"_VAL='1' else");
+		uint32_t num_port  = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_read_by_bank*k+j);
+		string   index     = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):"";
+				
+		vhdl->set_body("\tin_READ_"+toString(num_port)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+"  when internal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+index+"_VAL ='1' else");
 	      }
 	    vhdl->set_body("\tin_READ_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+";");
@@ -174,7 +178,8 @@
 	    for (uint32_t k=1; k<nb_port; k++)
 	      {
-		uint32_t num_port  = _param->_nb_port_write_by_bank*k+j;
-
-		vhdl->set_body("\tin_WRITE_"+toString(num_port)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+" when internal_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL='1' else");
+		uint32_t num_port  = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_write_by_bank*k+j);
+		string   index     = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):"";
+
+		vhdl->set_body("\tin_WRITE_"+toString(num_port)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+" when internal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+index+"_VAL='1' else");
 	      }
 	    vhdl->set_body("\tin_WRITE_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+";");
@@ -197,7 +202,7 @@
 	    for (uint32_t k=1; k<nb_port; k++)
 	      {
-		uint32_t num_port  = _param->_nb_port_write_by_bank*k+j;
-
-		vhdl->set_body("\tin_WRITE_"+toString(num_port)+"_DATA when internal_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL='1' else");
+		uint32_t num_port  = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_write_by_bank*k+j);
+		string   index     = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):"";
+		vhdl->set_body("\tin_WRITE_"+toString(num_port)+"_DATA when internal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+index+"_VAL='1' else");
 	      }
 	    vhdl->set_body("\tin_WRITE_"+toString(j)+"_DATA;");
@@ -216,15 +221,50 @@
 	for (uint32_t j=0; j<_param->_nb_port_read; j ++)
 	  {
-	    string address = (_param->_nb_bank==1)?"":("and (in_READ_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address-1,_param->_size_address_by_bank)+"="+std_logic_conv( _param->_size_address-_param->_size_address_by_bank,i)+")");
-
-	    vhdl->set_body("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL <= '1' when (in_READ_"+toString(j)+"_VAL='1') "+address+"else '0';");
+	    string address = (_param->_nb_bank==1)?"":("and (in_READ_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address-1,_param->_size_address_by_bank)+"="+std_logic_conv( _param->_size_address-_param->_size_address_by_bank,i)+") ");
+
+	    vhdl->set_body("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL  <= '1' when (in_READ_"+toString(j)+"_VAL ='1') "+address+"else '0';");
 	  }
 	for (uint32_t j=0; j<_param->_nb_port_write; j ++)
 	  {
-	    string address = (_param->_nb_bank==1)?"":("and (in_WRITE_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address-1,_param->_size_address_by_bank)+"="+std_logic_conv( _param->_size_address-_param->_size_address_by_bank,i)+")");
-	    vhdl->set_body("internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL <= '1' when (in_WRITE_"+toString(j)+"_VAL='1') "+address+" else '0';");
-	  }
-      }
-
+	    string address = (_param->_nb_bank==1)?"":("and (in_WRITE_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address-1,_param->_size_address_by_bank)+"="+std_logic_conv( _param->_size_address-_param->_size_address_by_bank,i)+") ");
+	    vhdl->set_body("internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL <= '1' when (in_WRITE_"+toString(j)+"_VAL='1') "+address+"else '0';");
+	  }
+      }
+
+    if (_param->_crossbar == FULL_CROSSBAR)
+      {
+	for (uint32_t i=0; i<_param->_nb_bank; i++)
+	  {
+	    for (uint32_t j=0; j<_param->_nb_port_read; j++)
+	      {
+		for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k++)
+		  {
+		    vhdl->set_body("internal_READ_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL  <= internal_READ_"+toString(i)+"_"+toString(j)+"_VAL  and not");
+		    vhdl->set_body("\t('0'");
+		    for (uint32_t l=0; l<k; l++)
+		      {
+			vhdl->set_body("\tor internal_SELECT_READ_"+toString(i)+"_"+toString(j)+"_"+toString(l)+"_VAL"); 
+		      }
+		    
+		    vhdl->set_body("\t);");
+		  }
+	      }
+	    for (uint32_t j=0; j<_param->_nb_port_write; j++)
+	      {
+		for (uint32_t k=0; k<_param->_nb_port_write_by_bank; k++)
+		  {
+		    vhdl->set_body("internal_WRITE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL <= internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL and not");
+		    vhdl->set_body("\t('0'");
+
+		      for (uint32_t l=0; l<k; l++)
+		      {
+			vhdl->set_body("\tor internal_SELECT_WRITE_"+toString(i)+"_"+toString(j)+"_"+toString(l)+"_VAL"); 
+		      }
+		    
+		    vhdl->set_body("\t);");
+		  }
+	      }
+	  }
+      }
     vhdl->set_body("");
     vhdl->set_body("-----------------------------------");
@@ -237,10 +277,10 @@
 	for (uint32_t i=0; i<_param->_nb_port_read; i ++)
 	  {
-	    vhdl->set_body("out_READ_"+toString(i)+"_ACK <= ");
+	    vhdl->set_body("out_READ_"+toString(i)+"_ACK  <= ");
 	    for (uint32_t j=0; j<_param->_nb_bank; j ++)
 	      {
 		for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k ++)
 		  {
-		    vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(k)+"_ACK when internal_SELECT_READ_"+toString(j)+"_"+toString(k)+"_VAL = '1' else");
+		    vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(k)+"_ACK  when internal_SELECT_READ_"+toString(j)+"_"+toString(i)+"_"+toString(k)+"_VAL  = '1' else");
 		  }
 	      }
@@ -251,5 +291,5 @@
 		for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k ++)
 		  {
-		    vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(k)+"_DATA when internal_SELECT_READ_"+toString(j)+"_"+toString(k)+"_VAL = '1' else");
+		    vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(k)+"_DATA when internal_SELECT_READ_"+toString(j)+"_"+toString(i)+"_"+toString(k)+"_VAL  = '1' else");
 		  }
 	      }
@@ -263,5 +303,5 @@
 		for (uint32_t k=0; k<_param->_nb_port_write_by_bank; k ++)
 		  {
-		    vhdl->set_body("\tinternal_BANK_WRITE_"+toString(j)+"_"+toString(k)+"_ACK when internal_SELECT_WRITE_"+toString(j)+"_"+toString(k)+"_VAL = '1' else");
+		    vhdl->set_body("\tinternal_BANK_WRITE_"+toString(j)+"_"+toString(k)+"_ACK when internal_SELECT_WRITE_"+toString(j)+"_"+toString(i)+"_"+toString(k)+"_VAL = '1' else");
 		  }
 	      }
@@ -275,8 +315,8 @@
 	    uint32_t link = _param->_link_port_read_to_bank_read[i];
 
-	    vhdl->set_body("out_READ_"+toString(i)+"_ACK <= ");
-	    for (uint32_t j=0; j<_param->_nb_bank; j ++)
-	      {
-		vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(link)+"_ACK when internal_SELECT_READ_"+toString(j)+"_"+toString(link)+"_VAL = '1' else");
+	    vhdl->set_body("out_READ_"+toString(i)+"_ACK  <= ");
+	    for (uint32_t j=0; j<_param->_nb_bank; j ++)
+	      {
+		vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(link)+"_ACK  when internal_SELECT_READ_"+toString(j)+"_"+toString(i)+"_VAL  = '1' else");
 	      }
 // 	    vhdl->set_body("\tinternal_BANK_READ_"+toString(0)+"_"+toString(link)+"_ACK;");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_declaration.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_declaration.cpp	(revision 57)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_declaration.cpp	(revision 58)
@@ -24,8 +24,16 @@
 	for (uint32_t j=0; j<_param->_nb_port_read; j ++)
 	  {
+	    if (_param->_crossbar == FULL_CROSSBAR)
+	      {
+		for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k++)
+		  {
+		    vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL" ,1);
+		    vhdl->set_signal ("internal_SELECT_READ_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL" ,1);
+		  }
+	      }
+	    else
+	      vhdl->set_signal ("internal_SELECT_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1);
 	    vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1);
 	    vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_ACK" ,1);
-	    vhdl->set_signal ("internal_SELECT_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1);
-
 	  }
 	for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j ++)
@@ -36,9 +44,19 @@
 	    vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_DATA"   ,_param->_size_word);
 	  }
+
 	for (uint32_t j=0; j<_param->_nb_port_write; j ++)
 	  {
+	    if (_param->_crossbar == FULL_CROSSBAR)
+	      {
+		for (uint32_t k=0; k<_param->_nb_port_write_by_bank; k++)
+		  {
+		    vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL" ,1);
+		    vhdl->set_signal ("internal_SELECT_WRITE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL"    ,1);
+		  }
+	      }
+	    else
+	      vhdl->set_signal ("internal_SELECT_WRITE_"+toString(i)+"_"+toString(j)+"_VAL"    ,1);
 	    vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL" ,1);
 	    vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_ACK" ,1);
-	    vhdl->set_signal ("internal_SELECT_WRITE_"+toString(i)+"_"+toString(j)+"_VAL"    ,1);
 	  }
 	for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j ++)
